module_content
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1.05M
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module instantiation for Port-0
mig_7series_v2_0_init_mem_pattern_ctr #
(
.TCQ (TCQ),
.DWIDTH (DATA_WIDTH),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_TYPE (MEM_TYPE),
.FAMILY (TG_FAMILY),
.BL_WIDTH (10),
.ADDR_WIDTH (ADDR_WIDTH),
.BEGIN_ADDRESS (BEGIN_ADDRESS_INT),
.END_ADDRESS (END_ADDRESS_INT),
.CMD_SEED_VALUE (32'h56456783),
.DATA_SEED_VALUE (32'h12345678),
.DATA_MODE (TG_INIT_DATA_MODE),
.PORT_MODE (PORT_MODE)
)
u_init_mem_pattern_ctr
(
.clk_i (clk),
.rst_i (tg_rst),
.memc_cmd_en_i (memc_cmd_en),
.memc_wr_en_i (tg_memc_wr_en),
.single_write_button (1'b0), // tie off these group of signals for 13.3
.single_read_button (1'b0),
.slow_write_read_button (1'b0),
.single_operation (1'b0),
.vio_modify_enable (vio_modify_enable),
.vio_instr_mode_value (tg_instr_mode_value),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value), // always set to PRBS_BL mode
.vio_fixed_bl_value (lcl_v_fixed_bl_value), // always set to 64 in order to run PRBS data pattern
.vio_data_mask_gen (vio_data_mask_gen),
.vio_fixed_instr_value (vio_fixed_instr_value),
.memc_init_done_i (memc_init_done),
.cmp_error (error),
.run_traffic_o (run_traffic),
.start_addr_o (tg_start_addr),
.end_addr_o (tg_end_addr),
.cmd_seed_o (tg_cmd_seed),
.data_seed_o (tg_data_seed),
.load_seed_o (tg_load_seed),
.addr_mode_o (tg_addr_mode),
.instr_mode_o (tg_instr_mode),
.bl_mode_o (tg_bl_mode),
.data_mode_o (tg_data_mode),
.mode_load_o (tg_mode_load),
.fixed_bl_o (tg_fixed_bl),
.fixed_instr_o (tg_fixed_instr),
.mem_pattern_init_done_o (mem_pattern_init_done)
);
// traffic generator instantiation for Port-0
mig_7series_v2_0_memc_traffic_gen #
(
.TCQ (TCQ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.nCK_PER_CLK (nCK_PER_CLK),
.PORT_MODE (PORT_MODE),
.DWIDTH (DATA_WIDTH),
.FAMILY (TG_FAMILY),
.MEM_TYPE (MEM_TYPE),
.SIMULATION (SIMULATION),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN ),
.ADDR_WIDTH (ADDR_WIDTH),
.BL_WIDTH (10),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.PRBS_SADDR_MASK_POS (BEGIN_ADDRESS_INT),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR (BEGIN_ADDRESS_INT),
.PRBS_EADDR (END_ADDRESS_INT),
.EYE_TEST (EYE_TEST)
)
u_memc_traffic_gen
(
.clk_i (clk),
.rst_i (tg_rst),
.run_traffic_i (tg_run_traffic),
.manual_clear_error (manual_clear_error),
.cmds_gap_delay_value (cmds_gap_delay_value),
.vio_instr_mode_value (tg_instr_mode_value),
.vio_percent_write ('b0), // bring this to top if want to specify percentage of write commands
// instr_mode_i has to be == 4 if want to use this command pattern
// runtime parameter
.mem_pattern_init_done_i (mem_pattern_init_done),
.single_operation (1'b0),
.start_addr_i (tg_start_addr),
.end_addr_i (tg_end_addr),
.cmd_seed_i (tg_cmd_seed),
.data_seed_i (tg_data_seed),
.load_seed_i (tg_load_seed),
.addr_mode_i (tg_addr_mode),
.instr_mode_i (tg_instr_mode),
.bl_mode_i (tg_bl_mode),
.data_mode_i (tg_data_mode),
.mode_load_i (tg_mode_load),
.wr_data_mask_gen_i (tg_data_mask_gen),
// fixed pattern inputs interface
.fixed_bl_i (tg_fixed_bl),
.fixed_instr_i (tg_fixed_instr),
.fixed_addr_i (fixed_addr_i),
.fixed_data_i (fixed_data_i),
// BRAM interface.
.bram_cmd_i (bram_cmd_i),
// .bram_addr_i (bram_addr_i ),
// .bram_instr_i ( bram_instr_i),
.bram_valid_i (bram_valid_i),
.bram_rdy_o (bram_rdy_o),
// MCB INTERFACE
.memc_cmd_en_o (memc_cmd_en),
.memc_cmd_instr_o (memc_cmd_instr),
.memc_cmd_bl_o (memc_cmd_bl),
.memc_cmd_addr_o (memc_cmd_addr),
.memc_cmd_full_i (memc_cmd_full),
.memc_wr_en_o (memc_wr_en),
.memc_wr_data_end_o (memc_wr_end),
.memc_wr_mask_o (memc_wr_mask),
.memc_wr_data_o (memc_wr_data),
.memc_wr_full_i (memc_wr_full),
.memc_rd_en_o (memc_rd_en),
.memc_rd_data_i (memc_rd_data),
.memc_rd_empty_i (memc_rd_empty),
.qdr_wr_cmd_o (qdr_wr_cmd_o),
.qdr_rd_cmd_o (qdr_rd_cmd_o),
// status feedback
.counts_rst (tg_rst),
.wr_data_counts (wr_data_counts),
.rd_data_counts (rd_data_counts),
.error (error), // asserted whenever the read back data is not correct.
.error_status (error_status), // TBD how signals mapped
.cmp_data (cmp_data),
.cmp_data_valid (cmp_data_valid),
.cmp_error (cmp_error),
.mem_rd_data (),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
.cumlative_dq_lane_error (cumlative_dq_lane_error),
.cumlative_dq_r0_bit_error (),
.cumlative_dq_f0_bit_error (),
.cumlative_dq_r1_bit_error (),
.cumlative_dq_f1_bit_error (),
.dq_r0_bit_error_r (),
.dq_f0_bit_error_r (),
.dq_r1_bit_error_r (),
.dq_f1_bit_error_r (),
.dq_r0_read_bit (),
.dq_f0_read_bit (),
.dq_r1_read_bit (),
.dq_f1_read_bit (),
.dq_r0_expect_bit (),
.dq_f0_expect_bit (),
.dq_r1_expect_bit (),
.dq_f1_expect_bit (),
.error_addr ()
);
reg [8:0] wr_cmd_cnt;
reg [8:0] dat_cmd_cnt;
reg rst_remem;
reg [2:0] app_cmd1;
reg [2:0] app_cmd2;
reg [2:0] app_cmd3;
reg [2:0] app_cmd4;
reg [8:0] rst_cntr;
always @(posedge clk) begin
if (rst) begin
rst_remem <= 1'b0;
end else if (tg_only_rst) begin
rst_remem <= 1'b1;
end else if (rst_cntr == 9'h0) begin
rst_remem <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
tg_rst <= 1'b1;
end else begin
tg_rst <= (rst_cntr != 9'h1ff);
end
end
always @ (posedge clk)
begin
if (rst)
rst_cntr <= 9'h1ff;
else if (rst_remem & (wr_cmd_cnt==dat_cmd_cnt) & (app_cmd3==3'h1) & (app_cmd4==3'h0))
rst_cntr <= 9'h0;
else if (rst_cntr != 9'h1ff)
rst_cntr <= rst_cntr + 1'b1;
end
always @(posedge clk) begin
if (rst | tg_rst) begin
wr_cmd_cnt <= 1'b0;
end else if (memc_cmd_en & (!memc_cmd_full)& (memc_cmd_instr == 3'h0)) begin
wr_cmd_cnt <= wr_cmd_cnt + 1'b1;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
dat_cmd_cnt <= 1'b0;
end else if (memc_wr_en & (!memc_wr_full)) begin
dat_cmd_cnt <= dat_cmd_cnt + 1'b1;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
app_cmd1 <= 'b0;
app_cmd2 <= 'b0;
app_cmd3 <= 'b0;
app_cmd4 <= 'b0;
end else if (memc_cmd_en & (!memc_cmd_full)) begin
app_cmd1 <= memc_cmd_instr;
app_cmd2 <= app_cmd1;
app_cmd3 <= app_cmd2;
app_cmd4 <= app_cmd3;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
cmd_wdt <= 1'b0;
end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (memc_cmd_full | (!memc_cmd_en)) & wdt_en_i) begin
// init_calib_done !app_rdy app_en
cmd_wdt <= cmd_wdt + 1'b1;
// end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (!memc_cmd_full) & memc_cmd_en & wdt_en_w) begin
end else if ((!memc_cmd_full) & memc_cmd_en) begin
// init_calib_done !app_rdy app_en
cmd_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
rd_wdt <= 1'b0;
end else if (mem_pattern_init_done & (rd_wdt != RD_WDT) & (memc_rd_empty) & wdt_en_i) begin
// !app_rd_data_valid
rd_wdt <= rd_wdt + 1'b1;
end else if (!memc_rd_empty) begin
// !app_rd_data_valid
rd_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
wr_wdt <= 1'b0;
end else if (mem_pattern_init_done & (wr_wdt != WR_WDT) & (!memc_wr_en) & wdt_en_i) begin
// app_wdf_wren
wr_wdt <= wr_wdt + 1'b1;
end else if (memc_wr_en) begin
// app_wdf_wren
wr_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
cmd_wdt_err_o <= 'b0;
rd_wdt_err_o <= 'b0;
wr_wdt_err_o <= 'b0;
end else begin
cmd_wdt_err_o <= cmd_wdt == CMD_WDT;
rd_wdt_err_o <= rd_wdt == RD_WDT;
wr_wdt_err_o <= wr_wdt == WR_WDT;
end
end
//synthesis translate_off
initial
begin
@ (posedge cmd_wdt_err_o);
$display ("ERROR: COMMAND Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge rd_wdt_err_o);
$display ("ERROR: READ Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge wr_wdt_err_o)
$display ("ERROR: WRITE Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge error)
repeat (20) @ (posedge clk);
$finish;
end
//synthesis translate_on
endmodule |
module sky130_fd_sc_hd__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule |
module biasWorker (
input clk,
input rst_n,
// Worker Control Interface (WCI) Slave Signals...
input [2:0] wci_MCmd,
input [0:0] wci_MAddrSpace,
input [3:0] wci_MByteEn,
input [19:0] wci_MAddr,
input [31:0] wci_MData,
output reg [1:0] wci_SResp,
output reg [31:0] wci_SData,
input [1:0] wci_MFlag,
output reg [1:0] wci_SFlag,
output reg wci_SThreadBusy,
// Worker Streaming Interface (WSI0) Slave Signals...
input [2:0] wsi0_MCmd,
input wsi0_MReqLast,
input wsi0_MBurstPrecise,
input [11:0] wsi0_MBurstLength,
input [31:0] wsi0_MData,
input [3:0] wsi0_MByteEn,
input [7:0] wsi0_MReqInfo,
output wsi0_SThreadBusy,
// Worker Streaming Interface (WSI1) Master Signals...
output reg [2:0] wsi1_MCmd,
output reg wsi1_MReqLast,
output reg wsi1_MBurstPrecise,
output reg [11:0] wsi1_MBurstLength,
output reg [31:0] wsi1_MData,
output reg [3:0] wsi1_MByteEn,
output reg [7:0] wsi1_MReqInfo,
input wsi1_SThreadBusy,
// Peer to Peer OCP Resets...
output wsi_m_MReset_n,
input wsi_m_SReset_n,
input wsi_s_MReset_n,
output wsi_s_SReset_n
);
reg [31:0] biasValue;
reg [2:0] wci_ctlSt;
wire wci_cfg_write, wci_cfg_read, wci_ctl_op;
assign wci_cfg_write = (wci_MCmd==3'h1 && wci_MAddrSpace[0]==1'b1);
assign wci_cfg_read = (wci_MCmd==3'h2 && wci_MAddrSpace[0]==1'b1);
assign wci_ctl_op = (wci_MCmd==3'h2 && wci_MAddrSpace[0]==1'b0);
// When this worker is WCI reset, propagate reset out to WSI partners...
assign wsi_m_MReset_n = rst_n;
assign wsi_s_SReset_n = rst_n;
//Pass the SThreadBusy upstream without pipelining...
assign wsi0_SThreadBusy = (wsi1_SThreadBusy || (wci_ctlSt!=2'h2));
always@(posedge clk)
begin
// Registered Operations that don't care about reset...
if (wci_ctlSt == 2'h2) begin // Implement the biasWorker function when operating...
wsi1_MData = wsi0_MData + biasValue; // add the bias
wsi1_MCmd = wsi0_MCmd;
end else begin // Or block the WSI pipeline cleanly...
wsi1_MData = 0;
wsi1_MCmd = 3'h0; // Idle
end
// Pass through signals of the WSI interface that we maintain, but do not use...
wsi1_MReqLast = wsi0_MReqLast;
wsi1_MBurstPrecise = wsi0_MBurstPrecise;
wsi1_MBurstLength = wsi0_MBurstLength;
wsi1_MByteEn = wsi0_MByteEn;
wsi1_MReqInfo = wsi0_MReqInfo;
// Implement minimal WCI attach logic...
wci_SThreadBusy = 1'b0;
wci_SResp = 2'b0;
if (rst_n==1'b0) begin // Reset Conditions...
wci_ctlSt = 3'h0;
wci_SResp = 2'h0;
wci_SFlag = 2'h0;
wci_SThreadBusy = 2'b1;
biasValue = 32'h0000_0000;
end else begin // When not Reset...
// WCI Configuration Property Writes...
if (wci_cfg_write==1'b1) begin
biasValue = wci_MData; // Write the biasValue Configuration Property
wci_SResp = 2'h1;
end
// WCI Configuration Property Reads...
if (wci_cfg_read==1'b1) begin
wci_SData = biasValue; // Read the biasValue Configuration Property
wci_SResp = 2'h1;
end
//WCI Control Operations...
if (wci_ctl_op==1'b1) begin
case (wci_MAddr[4:2])
2'h0 : wci_ctlSt = 3'h1; // when wciCtlOp_Initialize => wci_ctlSt <= wciCtlSt_Initialized;
2'h1 : wci_ctlSt = 3'h2; // when wciCtlOp_Start => wci_ctlSt <= wciCtlSt_Operating;
2'h2 : wci_ctlSt = 3'h3; // when wciCtlOp_Stop => wci_ctlSt <= wciCtlSt_Suspended;
2'h3 : wci_ctlSt = 3'h0; // when wciCtlOp_Release => wci_ctlSt <= wciCtlSt_Exists;
endcase
wci_SData = 32'hC0DE_4201;
wci_SResp = 2'h1;
end
end // end of not reset clause
end // end of always block
endmodule |
module NPSAT1_ARM_CFTP_Interface(
// ARM Interface
inout wire [15:0] ARM_Data_inout,
input wire [10:0] ARM_Address_in,
input wire ARM_Read_in, //active-low
input wire ARM_Write_in, //active-low
input wire ARM_CS_in, //active-low
input wire ARM_BCLK_in, //51MHz
output wire ARM_IRQ_out, //active-high(???)
output wire ARM_Data_Direction, //High_in, Low_out
// CFTP Interface
input wire CFTP_Address_in,
input wire [31:0] CFTP_Data_in,
output wire [31:0] CFTP_Data_out,
input wire CFTP_Read_in, //active-high
input wire CFTP_Write_in, //active-high
output wire CFTP_Ready_out, //active-high
input wire CFTP_BCLK_in, //200MHz
input wire CFTP_Reset_in, //active-high
output wire CFTP_IRQ_out //active-high
);
wire Incoming_Full, Incoming_Empty, Outgoing_Full, Outgoing_Empty;
//ARM Interface Signals and Parameters
parameter ARM_STATE_IDLE = 3'b000;
parameter ARM_STATE_READ = 3'b001;
parameter ARM_STATE_READ_WAIT = 3'b010;
parameter ARM_STATE_HIZ = 3'b011;
parameter ARM_STATE_WRITE = 3'b100;
parameter ARM_STATE_WRITE_WAIT = 3'b101;
reg [2:0] ARM_CurrentState, ARM_NextState;
wire Decode;
wire [15:0] ARM_Data_FIFO, ARM_Data_in, ARM_Status;
wire [10:0] Outgoing_FIFO_Count;
//CFTP Interface Signals and Parameters
parameter CFTP_STATE_IDLE = 2'b00;
parameter CFTP_STATE_WRITE = 2'b01;
parameter CFTP_STATE_READ = 2'b10;
parameter CFTP_STATE_ACK = 2'b11;
reg [1:0] CFTP_CurrentState, CFTP_NextState;
reg [7:0] Top8;
reg [15:0] ARM_Data_out;
wire [9:0] Incoming_FIFO_Count;
wire [31:0] CFTP_Data;
ARM_FIFO_in INCOMING ( //Uses first word fall through FIFO
.rst(CFTP_Reset_in),
.wr_clk(ARM_BCLK_in),
.rd_clk(CFTP_BCLK_in),
.din({Top8,ARM_Data_inout[7:0]}),
.wr_en((ARM_CurrentState == ARM_STATE_WRITE) && (ARM_Address_in == 11'h340)),
.rd_en((CFTP_CurrentState == CFTP_STATE_READ) && (CFTP_Address_in == 1'b0)),
.dout(CFTP_Data),
.full(Incoming_Full),
.empty(Incoming_Empty),
.rd_data_count(Incoming_FIFO_Count)
);
ARM_FIFO_out OUTGOING ( //Uses regular FIFO
.rst(CFTP_Reset_in),
.wr_clk(CFTP_BCLK_in),
.rd_clk(ARM_BCLK_in),
.din(CFTP_Data_in),
.wr_en((CFTP_CurrentState == CFTP_STATE_WRITE) && (CFTP_Address_in == 1'b0)),
.rd_en((ARM_CurrentState == ARM_STATE_READ) && (ARM_Address_in == 11'h341)),
.dout(ARM_Data_FIFO),
.full(Outgoing_Full),
.empty(Outgoing_Empty),
.rd_data_count(Outgoing_FIFO_Count)
);
//ARM Interface Assignments
assign ARM_Status = {3'b0, Outgoing_FIFO_Count, Incoming_Full, ~Outgoing_Empty};
assign ARM_Data_inout = (Decode && ~ARM_Read_in) ? ARM_Data_out : 16'dz;
assign Decode = (((ARM_Address_in >= 11'h340) && (ARM_Address_in <= 11'h34F)) && ~ARM_CS_in);
assign ARM_Data_Direction = ~(Decode&&~ARM_Read_in); //High is into FPGA, Low is out of FPGA...
// assign ARM_IRQ_out = ~Outgoing_Empty;
//ARM Interface Synchronous Transitions
always@(posedge ARM_BCLK_in) ARM_Data_out = (ARM_CurrentState == ARM_STATE_READ) ? (ARM_Address_in == 11'h340) ? {ARM_Data_FIFO[7:0],ARM_Data_FIFO[15:8]} :
(ARM_Address_in == 11'h341) ? {ARM_Data_FIFO[7:0],ARM_Data_FIFO[15:8]} :
(ARM_Address_in == 11'h342) ? ARM_Status : ARM_Data_out : ARM_Data_out;
always@(negedge ARM_BCLK_in) ARM_CurrentState = ARM_NextState;
always@(posedge ARM_BCLK_in) Top8 = ((ARM_CurrentState == ARM_STATE_WRITE) && (ARM_Address_in == 11'h341)) ? ARM_Data_inout[15:8] : Top8; //Temporarily Store the High Byte Since the ARM is doing 8-bit transactions
//ARM Interface State Transitions
always@(*) begin
case (ARM_CurrentState)
ARM_STATE_IDLE: ARM_NextState = (Decode) ? (~ARM_Write_in) ? ARM_STATE_WRITE : (~ARM_Read_in) ? ARM_STATE_HIZ : ARM_STATE_IDLE : ARM_STATE_IDLE;
ARM_STATE_WRITE: ARM_NextState = ARM_STATE_WRITE_WAIT;
ARM_STATE_WRITE_WAIT: ARM_NextState = (ARM_Write_in) ? ARM_STATE_IDLE : ARM_STATE_WRITE_WAIT;
ARM_STATE_HIZ: ARM_NextState = ARM_STATE_READ; //Allow one clock cycle to transition the bus transcievers to prevent driving bus from both the FPGA and Bus Transcievers.
ARM_STATE_READ: ARM_NextState = ARM_STATE_READ_WAIT;
ARM_STATE_READ_WAIT: ARM_NextState = (ARM_Read_in) ? ARM_STATE_IDLE : ARM_STATE_READ_WAIT;
default : ARM_NextState = ARM_STATE_IDLE;
endcase
end
//CFTP Interface Assignments
assign CFTP_IRQ_out = ~Incoming_Empty;
assign CFTP_Ready_out = (CFTP_CurrentState == CFTP_STATE_ACK);
assign CFTP_Data_out = (CFTP_Address_in) ? {22'd0 ,Incoming_FIFO_Count} : CFTP_Data;
//CFTP Interface Synchronous Transitions
always@(negedge CFTP_BCLK_in) CFTP_CurrentState = CFTP_NextState;
//CFTP Interface State Transitions
always@(*) begin
case (CFTP_CurrentState)
CFTP_STATE_IDLE: CFTP_NextState = (CFTP_Write_in) ? CFTP_STATE_WRITE : (CFTP_Read_in) ? CFTP_STATE_READ : CFTP_STATE_IDLE;
CFTP_STATE_WRITE: CFTP_NextState = CFTP_STATE_ACK;
CFTP_STATE_READ: CFTP_NextState = CFTP_STATE_ACK;
CFTP_STATE_ACK: CFTP_NextState = ~(CFTP_Write_in || CFTP_Read_in) ? CFTP_STATE_IDLE : CFTP_STATE_ACK;
default : CFTP_NextState = CFTP_STATE_IDLE;
endcase
end
endmodule |
module test_bench(clk, rst);
input clk;
input rst;
wire [31:0] wire_39069600;
wire wire_39069600_stb;
wire wire_39069600_ack;
wire [31:0] wire_39795024;
wire wire_39795024_stb;
wire wire_39795024_ack;
wire [31:0] wire_39795168;
wire wire_39795168_stb;
wire wire_39795168_ack;
file_reader_a file_reader_a_39796104(
.clk(clk),
.rst(rst),
.output_z(wire_39069600),
.output_z_stb(wire_39069600_stb),
.output_z_ack(wire_39069600_ack));
file_reader_b file_reader_b_39759816(
.clk(clk),
.rst(rst),
.output_z(wire_39795024),
.output_z_stb(wire_39795024_stb),
.output_z_ack(wire_39795024_ack));
file_writer file_writer_39028208(
.clk(clk),
.rst(rst),
.input_a(wire_39795168),
.input_a_stb(wire_39795168_stb),
.input_a_ack(wire_39795168_ack));
adder adder_39759952(
.clk(clk),
.rst(rst),
.input_a(wire_39069600),
.input_a_stb(wire_39069600_stb),
.input_a_ack(wire_39069600_ack),
.input_b(wire_39795024),
.input_b_stb(wire_39795024_stb),
.input_b_ack(wire_39795024_ack),
.output_z(wire_39795168),
.output_z_stb(wire_39795168_stb),
.output_z_ack(wire_39795168_ack));
endmodule |
module PLL_ADF4158(
input clk,
input reset_n,
output reg writeData,
output reg loadEnable,
output pll_clk
);
localparam s0 = 2'b00;
localparam s1 = 2'b01;
localparam s2 = 2'b10;
localparam s3 = 2'b11;
localparam num_registers_to_set = 8;
reg [31:0] writeDataArray [num_registers_to_set - 1:0];
reg [31:0] current_register;
reg [1:0] nextState, state;
reg [4:0] bit_counter;
reg [2:0] register_counter;
reg dec_register_counter, dec_bit_counter;
assign pll_clk = clk;
initial begin
state = s0;
bit_counter = 31;
register_counter = num_registers_to_set - 1;
dec_register_counter = 0;
dec_bit_counter = 0;
loadEnable = 0;
writeDataArray[0] = 32'b1_0000_000011000110_000000000000_000; //reg 0
writeDataArray[1] = 32'b0000_0000000000000_000000000000_001; //reg 1
writeDataArray[2] = 32'b000_0_1111_0_1_1_0_00001_000000000001_010; //reg 2
writeDataArray[3] = 32'b0000000000000000_1_0_00_01_0_0_0_0_0_0_0_011; //reg 3
writeDataArray[4] = 32'b0_00000_0_11_00_11_000000000001_0000_100; //reg 4
writeDataArray[5] = 32'b00_0_0_00_0_0_0_0000_0010010101110010_101; //reg 5 DEV SEL = 0
writeDataArray[6] = 32'b00000000_0_00000011011010110000_110; //reg 6 STEP SEL = 0
writeDataArray[7] = 32'b0000_0000_0000_0000_0000_0000_0000_0_111; //reg 7
end
always @ (negedge clk) begin
if(!reset_n) begin
state <= s0;
end
else begin
state <= nextState;
end
end
always @(negedge clk) begin
if(dec_register_counter == 1) begin
register_counter <= register_counter - 1;
end
if(dec_bit_counter == 1) begin
bit_counter <= bit_counter - 1;
end
end
always @ * begin
dec_bit_counter = 0;
dec_register_counter = 0;
loadEnable = 0;
current_register = writeDataArray[register_counter];
writeData = current_register[bit_counter];
case(state)
s0: begin
dec_bit_counter = 1;
nextState = s1;
end
s1: begin
if(bit_counter == 0) begin
nextState = s2;
end else begin
nextState = s1;
dec_bit_counter = 1;
end
end
s2: begin
loadEnable = 1;
if(register_counter != 0) begin
nextState = s0;
dec_register_counter = 1;
dec_bit_counter = 1;
end else begin
nextState = s3;
end
end
s3: begin
nextState = s3;
end
endcase
end
endmodule |
module sky130_fd_sc_ls__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, C1, B1, and0_out, D1);
buf buf0 (X , or0_out_X );
endmodule |
module char_array (
byteena_a,
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [3:0] byteena_a;
input [31:0] data;
input [9:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena_a;
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.byteena_a (byteena_a),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 4;
endmodule |
module uart_wb #(
parameter reg LITTLE_ENDIAN=1,
parameter reg DATA_BUS_WIDTH_8=0,
parameter reg WORD_SIZE_REGS=1) (
clk, wb_rst_i, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
we_o, re_o // Write and read enable output for the core
);
parameter int DATA_WIDTH = (DATA_BUS_WIDTH_8==1)?8:32;
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line
input [DATA_WIDTH-1:0] wb_dat_i; //input WISHBONE bus
output [DATA_WIDTH-1:0] wb_dat_o;
reg [DATA_WIDTH-1:0] wb_dat_o;
wire [DATA_WIDTH-1:0] wb_dat_i;
reg [DATA_WIDTH-1:0] wb_dat_is;
output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0] wb_dat8_i;
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
reg [7:0] wb_dat8_i;
wire [7:0] wb_dat8_o;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
reg [`UART_ADDR_WIDTH-1:0] wb_adr_is;
reg wb_we_is;
reg wb_cyc_is;
reg wb_stb_is;
reg [3:0] wb_sel_is;
wire [3:0] wb_sel_i;
reg wre ;// timing control signal for write or read enable
// wb_ack_o FSM
reg [1:0] wbstate;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_ack_o <= #1 1'b0;
wbstate <= #1 0;
wre <= #1 1'b1;
end else
case (wbstate)
0: begin
if (wb_stb_is & wb_cyc_is) begin
wre <= #1 0;
wbstate <= #1 1;
wb_ack_o <= #1 1;
end else begin
wre <= #1 1;
wb_ack_o <= #1 0;
end
end
1: begin
wb_ack_o <= #1 0;
wbstate <= #1 2;
wre <= #1 0;
end
2,3: begin
wb_ack_o <= #1 0;
wbstate <= #1 0;
wre <= #1 0;
end
endcase
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
// Sample input signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_adr_is <= #1 0;
wb_we_is <= #1 0;
wb_cyc_is <= #1 0;
wb_stb_is <= #1 0;
wb_dat_is <= #1 0;
wb_sel_is <= #1 0;
end else begin
wb_adr_is <= #1 wb_adr_i;
wb_we_is <= #1 wb_we_i;
wb_cyc_is <= #1 wb_cyc_i;
wb_stb_is <= #1 wb_stb_i;
wb_dat_is <= #1 wb_dat_i;
wb_sel_is <= #1 wb_sel_i;
end
generate
if (DATA_BUS_WIDTH_8 == 1) begin
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 0;
else
wb_dat_o <= #1 wb_dat8_o;
always @(wb_dat_is)
wb_dat8_i = wb_dat_is;
assign wb_adr_int = wb_adr_is;
end else begin // 32-bit bus
if (WORD_SIZE_REGS == 1) begin
always @(posedge clk or posedge wb_rst_i) begin
if (wb_rst_i) begin
wb_dat_o <= 0;
end else if (re_o) begin
wb_dat_o <= {wb_dat8_o, wb_dat8_o, wb_dat8_o, wb_dat8_o};
end
end
always @(wb_sel_is or wb_dat_is) begin
wb_dat8_i = wb_dat_is[7:0];
end
assign wb_adr_int = {2'b0, wb_adr_is[`UART_ADDR_WIDTH-1:2]};
end else begin // 8-bit regs
// put output to the correct byte in 32 bits using select line
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 0;
else if (re_o)
case (wb_sel_is)
4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
default: wb_dat_o <= #1 0;
endcase // case(wb_sel_i)
reg [1:0] wb_adr_int_lsb;
always @(wb_sel_is or wb_dat_is)
begin
case (wb_sel_is)
4'b0001 : wb_dat8_i = wb_dat_is[7:0];
4'b0010 : wb_dat8_i = wb_dat_is[15:8];
4'b0100 : wb_dat8_i = wb_dat_is[23:16];
4'b1000 : wb_dat8_i = wb_dat_is[31:24];
default : wb_dat8_i = wb_dat_is[7:0];
endcase // case(wb_sel_i)
if (LITTLE_ENDIAN == 1) begin
case (wb_sel_is)
4'b0001 : wb_adr_int_lsb = 2'h0;
4'b0010 : wb_adr_int_lsb = 2'h1;
4'b0100 : wb_adr_int_lsb = 2'h2;
4'b1000 : wb_adr_int_lsb = 2'h3;
default : wb_adr_int_lsb = 2'h0;
endcase // case(wb_sel_i)
end else begin // Big Endian
case (wb_sel_is)
4'b0001 : wb_adr_int_lsb = 2'h3;
4'b0010 : wb_adr_int_lsb = 2'h2;
4'b0100 : wb_adr_int_lsb = 2'h1;
4'b1000 : wb_adr_int_lsb = 2'h0;
default : wb_adr_int_lsb = 2'h0;
endcase // case(wb_sel_i)
end
end
assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb};
end
end
endgenerate
endmodule |
module sky130_fd_sc_hd__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module sky130_fd_sc_hdll__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule |
module fpga (
/*
* Clock: 100 MHz
* Reset: Push button, active low
*/
input wire clk2_100m_fpga_2i_p,
input wire cpu_resetn,
/*
* GPIO
*/
input wire user_pb,
output wire [3:0] user_led_g,
/*
* Ethernet: QSFP28
*/
output wire [3:0] qsfp1_tx_p,
output wire [3:0] qsfp1_tx_n,
input wire [3:0] qsfp1_rx_p,
input wire [3:0] qsfp1_rx_n,
output wire [3:0] qsfp2_tx_p,
output wire [3:0] qsfp2_tx_n,
input wire [3:0] qsfp2_rx_p,
input wire [3:0] qsfp2_rx_n,
input wire clk_156p25m_qsfp0_p
);
// Clock and reset
wire ninit_done;
reset_release reset_release_inst (
.ninit_done (ninit_done)
);
wire clk_100mhz = clk2_100m_fpga_2i_p;
wire rst_100mhz;
sync_reset #(
.N(4)
)
sync_reset_100mhz_inst (
.clk(clk_100mhz),
.rst(~cpu_resetn || ninit_done),
.out(rst_100mhz)
);
wire clk_161mhz;
wire rst_161mhz;
// GPIO
wire btn_int;
wire [3:0] led_int;
debounce_switch #(
.WIDTH(1),
.N(4),
.RATE(161132)
)
debounce_switch_inst (
.clk(clk_161mhz),
.rst(rst_161mhz),
.in({~user_pb}),
.out({btn_int})
);
assign user_led_g = led_int;
// QSFP interfaces
wire qsfp1_mac_1_clk_int;
wire qsfp1_mac_1_rst_int;
wire [63:0] qsfp1_mac_1_rx_axis_tdata_int;
wire [7:0] qsfp1_mac_1_rx_axis_tkeep_int;
wire qsfp1_mac_1_rx_axis_tvalid_int;
wire qsfp1_mac_1_rx_axis_tlast_int;
wire qsfp1_mac_1_rx_axis_tuser_int;
wire [63:0] qsfp1_mac_1_tx_axis_tdata_int;
wire [7:0] qsfp1_mac_1_tx_axis_tkeep_int;
wire qsfp1_mac_1_tx_axis_tvalid_int;
wire qsfp1_mac_1_tx_axis_tready_int;
wire qsfp1_mac_1_tx_axis_tlast_int;
wire qsfp1_mac_1_tx_axis_tuser_int;
wire qsfp1_mac_2_clk_int;
wire qsfp1_mac_2_rst_int;
wire [63:0] qsfp1_mac_2_rx_axis_tdata_int;
wire [7:0] qsfp1_mac_2_rx_axis_tkeep_int;
wire qsfp1_mac_2_rx_axis_tvalid_int;
wire qsfp1_mac_2_rx_axis_tlast_int;
wire qsfp1_mac_2_rx_axis_tuser_int;
wire [63:0] qsfp1_mac_2_tx_axis_tdata_int;
wire [7:0] qsfp1_mac_2_tx_axis_tkeep_int;
wire qsfp1_mac_2_tx_axis_tvalid_int;
wire qsfp1_mac_2_tx_axis_tready_int;
wire qsfp1_mac_2_tx_axis_tlast_int;
wire qsfp1_mac_2_tx_axis_tuser_int;
wire qsfp1_mac_3_clk_int;
wire qsfp1_mac_3_rst_int;
wire [63:0] qsfp1_mac_3_rx_axis_tdata_int;
wire [7:0] qsfp1_mac_3_rx_axis_tkeep_int;
wire qsfp1_mac_3_rx_axis_tvalid_int;
wire qsfp1_mac_3_rx_axis_tlast_int;
wire qsfp1_mac_3_rx_axis_tuser_int;
wire [63:0] qsfp1_mac_3_tx_axis_tdata_int;
wire [7:0] qsfp1_mac_3_tx_axis_tkeep_int;
wire qsfp1_mac_3_tx_axis_tvalid_int;
wire qsfp1_mac_3_tx_axis_tready_int;
wire qsfp1_mac_3_tx_axis_tlast_int;
wire qsfp1_mac_3_tx_axis_tuser_int;
wire qsfp1_mac_4_clk_int;
wire qsfp1_mac_4_rst_int;
wire [63:0] qsfp1_mac_4_rx_axis_tdata_int;
wire [7:0] qsfp1_mac_4_rx_axis_tkeep_int;
wire qsfp1_mac_4_rx_axis_tvalid_int;
wire qsfp1_mac_4_rx_axis_tlast_int;
wire qsfp1_mac_4_rx_axis_tuser_int;
wire [63:0] qsfp1_mac_4_tx_axis_tdata_int;
wire [7:0] qsfp1_mac_4_tx_axis_tkeep_int;
wire qsfp1_mac_4_tx_axis_tvalid_int;
wire qsfp1_mac_4_tx_axis_tready_int;
wire qsfp1_mac_4_tx_axis_tlast_int;
wire qsfp1_mac_4_tx_axis_tuser_int;
wire qsfp2_mac_1_clk_int;
wire qsfp2_mac_1_rst_int;
wire [63:0] qsfp2_mac_1_rx_axis_tdata_int;
wire [7:0] qsfp2_mac_1_rx_axis_tkeep_int;
wire qsfp2_mac_1_rx_axis_tvalid_int;
wire qsfp2_mac_1_rx_axis_tlast_int;
wire qsfp2_mac_1_rx_axis_tuser_int;
wire [63:0] qsfp2_mac_1_tx_axis_tdata_int;
wire [7:0] qsfp2_mac_1_tx_axis_tkeep_int;
wire qsfp2_mac_1_tx_axis_tvalid_int;
wire qsfp2_mac_1_tx_axis_tready_int;
wire qsfp2_mac_1_tx_axis_tlast_int;
wire qsfp2_mac_1_tx_axis_tuser_int;
wire qsfp2_mac_2_clk_int;
wire qsfp2_mac_2_rst_int;
wire [63:0] qsfp2_mac_2_rx_axis_tdata_int;
wire [7:0] qsfp2_mac_2_rx_axis_tkeep_int;
wire qsfp2_mac_2_rx_axis_tvalid_int;
wire qsfp2_mac_2_rx_axis_tlast_int;
wire qsfp2_mac_2_rx_axis_tuser_int;
wire [63:0] qsfp2_mac_2_tx_axis_tdata_int;
wire [7:0] qsfp2_mac_2_tx_axis_tkeep_int;
wire qsfp2_mac_2_tx_axis_tvalid_int;
wire qsfp2_mac_2_tx_axis_tready_int;
wire qsfp2_mac_2_tx_axis_tlast_int;
wire qsfp2_mac_2_tx_axis_tuser_int;
wire qsfp2_mac_3_clk_int;
wire qsfp2_mac_3_rst_int;
wire [63:0] qsfp2_mac_3_rx_axis_tdata_int;
wire [7:0] qsfp2_mac_3_rx_axis_tkeep_int;
wire qsfp2_mac_3_rx_axis_tvalid_int;
wire qsfp2_mac_3_rx_axis_tlast_int;
wire qsfp2_mac_3_rx_axis_tuser_int;
wire [63:0] qsfp2_mac_3_tx_axis_tdata_int;
wire [7:0] qsfp2_mac_3_tx_axis_tkeep_int;
wire qsfp2_mac_3_tx_axis_tvalid_int;
wire qsfp2_mac_3_tx_axis_tready_int;
wire qsfp2_mac_3_tx_axis_tlast_int;
wire qsfp2_mac_3_tx_axis_tuser_int;
wire qsfp2_mac_4_clk_int;
wire qsfp2_mac_4_rst_int;
wire [63:0] qsfp2_mac_4_rx_axis_tdata_int;
wire [7:0] qsfp2_mac_4_rx_axis_tkeep_int;
wire qsfp2_mac_4_rx_axis_tvalid_int;
wire qsfp2_mac_4_rx_axis_tlast_int;
wire qsfp2_mac_4_rx_axis_tuser_int;
wire [63:0] qsfp2_mac_4_tx_axis_tdata_int;
wire [7:0] qsfp2_mac_4_tx_axis_tkeep_int;
wire qsfp2_mac_4_tx_axis_tvalid_int;
wire qsfp2_mac_4_tx_axis_tready_int;
wire qsfp2_mac_4_tx_axis_tlast_int;
wire qsfp2_mac_4_tx_axis_tuser_int;
assign clk_161mhz = qsfp1_mac_1_clk_int;
assign rst_161mhz = qsfp1_mac_1_rst_int;
eth_mac_quad_wrapper qsfp1_mac_inst (
.ctrl_clk(clk_100mhz),
.ctrl_rst(rst_100mhz),
.tx_serial_data_p(qsfp1_tx_p),
.tx_serial_data_n(qsfp1_tx_n),
.rx_serial_data_p(qsfp1_rx_p),
.rx_serial_data_n(qsfp1_rx_n),
.ref_clk(clk_156p25m_qsfp0_p),
.mac_1_clk(qsfp1_mac_1_clk_int),
.mac_1_rst(qsfp1_mac_1_rst_int),
.mac_1_rx_axis_tdata(qsfp1_mac_1_rx_axis_tdata_int),
.mac_1_rx_axis_tkeep(qsfp1_mac_1_rx_axis_tkeep_int),
.mac_1_rx_axis_tvalid(qsfp1_mac_1_rx_axis_tvalid_int),
.mac_1_rx_axis_tlast(qsfp1_mac_1_rx_axis_tlast_int),
.mac_1_rx_axis_tuser(qsfp1_mac_1_rx_axis_tuser_int),
.mac_1_tx_axis_tdata(qsfp1_mac_1_tx_axis_tdata_int),
.mac_1_tx_axis_tkeep(qsfp1_mac_1_tx_axis_tkeep_int),
.mac_1_tx_axis_tvalid(qsfp1_mac_1_tx_axis_tvalid_int),
.mac_1_tx_axis_tready(qsfp1_mac_1_tx_axis_tready_int),
.mac_1_tx_axis_tlast(qsfp1_mac_1_tx_axis_tlast_int),
.mac_1_tx_axis_tuser(qsfp1_mac_1_tx_axis_tuser_int),
.mac_2_clk(qsfp1_mac_3_clk_int),
.mac_2_rst(qsfp1_mac_3_rst_int),
.mac_2_rx_axis_tdata(qsfp1_mac_3_rx_axis_tdata_int),
.mac_2_rx_axis_tkeep(qsfp1_mac_3_rx_axis_tkeep_int),
.mac_2_rx_axis_tvalid(qsfp1_mac_3_rx_axis_tvalid_int),
.mac_2_rx_axis_tlast(qsfp1_mac_3_rx_axis_tlast_int),
.mac_2_rx_axis_tuser(qsfp1_mac_3_rx_axis_tuser_int),
.mac_2_tx_axis_tdata(qsfp1_mac_3_tx_axis_tdata_int),
.mac_2_tx_axis_tkeep(qsfp1_mac_3_tx_axis_tkeep_int),
.mac_2_tx_axis_tvalid(qsfp1_mac_3_tx_axis_tvalid_int),
.mac_2_tx_axis_tready(qsfp1_mac_3_tx_axis_tready_int),
.mac_2_tx_axis_tlast(qsfp1_mac_3_tx_axis_tlast_int),
.mac_2_tx_axis_tuser(qsfp1_mac_3_tx_axis_tuser_int),
.mac_3_clk(qsfp1_mac_2_clk_int),
.mac_3_rst(qsfp1_mac_2_rst_int),
.mac_3_rx_axis_tdata(qsfp1_mac_2_rx_axis_tdata_int),
.mac_3_rx_axis_tkeep(qsfp1_mac_2_rx_axis_tkeep_int),
.mac_3_rx_axis_tvalid(qsfp1_mac_2_rx_axis_tvalid_int),
.mac_3_rx_axis_tlast(qsfp1_mac_2_rx_axis_tlast_int),
.mac_3_rx_axis_tuser(qsfp1_mac_2_rx_axis_tuser_int),
.mac_3_tx_axis_tdata(qsfp1_mac_2_tx_axis_tdata_int),
.mac_3_tx_axis_tkeep(qsfp1_mac_2_tx_axis_tkeep_int),
.mac_3_tx_axis_tvalid(qsfp1_mac_2_tx_axis_tvalid_int),
.mac_3_tx_axis_tready(qsfp1_mac_2_tx_axis_tready_int),
.mac_3_tx_axis_tlast(qsfp1_mac_2_tx_axis_tlast_int),
.mac_3_tx_axis_tuser(qsfp1_mac_2_tx_axis_tuser_int),
.mac_4_clk(qsfp1_mac_4_clk_int),
.mac_4_rst(qsfp1_mac_4_rst_int),
.mac_4_rx_axis_tdata(qsfp1_mac_4_rx_axis_tdata_int),
.mac_4_rx_axis_tkeep(qsfp1_mac_4_rx_axis_tkeep_int),
.mac_4_rx_axis_tvalid(qsfp1_mac_4_rx_axis_tvalid_int),
.mac_4_rx_axis_tlast(qsfp1_mac_4_rx_axis_tlast_int),
.mac_4_rx_axis_tuser(qsfp1_mac_4_rx_axis_tuser_int),
.mac_4_tx_axis_tdata(qsfp1_mac_4_tx_axis_tdata_int),
.mac_4_tx_axis_tkeep(qsfp1_mac_4_tx_axis_tkeep_int),
.mac_4_tx_axis_tvalid(qsfp1_mac_4_tx_axis_tvalid_int),
.mac_4_tx_axis_tready(qsfp1_mac_4_tx_axis_tready_int),
.mac_4_tx_axis_tlast(qsfp1_mac_4_tx_axis_tlast_int),
.mac_4_tx_axis_tuser(qsfp1_mac_4_tx_axis_tuser_int)
);
eth_mac_quad_wrapper qsfp2_mac_inst (
.ctrl_clk(clk_100mhz),
.ctrl_rst(rst_100mhz),
.tx_serial_data_p(qsfp2_tx_p),
.tx_serial_data_n(qsfp2_tx_n),
.rx_serial_data_p(qsfp2_rx_p),
.rx_serial_data_n(qsfp2_rx_n),
.ref_clk(clk_156p25m_qsfp0_p),
.mac_1_clk(qsfp2_mac_1_clk_int),
.mac_1_rst(qsfp2_mac_1_rst_int),
.mac_1_rx_axis_tdata(qsfp2_mac_1_rx_axis_tdata_int),
.mac_1_rx_axis_tkeep(qsfp2_mac_1_rx_axis_tkeep_int),
.mac_1_rx_axis_tvalid(qsfp2_mac_1_rx_axis_tvalid_int),
.mac_1_rx_axis_tlast(qsfp2_mac_1_rx_axis_tlast_int),
.mac_1_rx_axis_tuser(qsfp2_mac_1_rx_axis_tuser_int),
.mac_1_tx_axis_tdata(qsfp2_mac_1_tx_axis_tdata_int),
.mac_1_tx_axis_tkeep(qsfp2_mac_1_tx_axis_tkeep_int),
.mac_1_tx_axis_tvalid(qsfp2_mac_1_tx_axis_tvalid_int),
.mac_1_tx_axis_tready(qsfp2_mac_1_tx_axis_tready_int),
.mac_1_tx_axis_tlast(qsfp2_mac_1_tx_axis_tlast_int),
.mac_1_tx_axis_tuser(qsfp2_mac_1_tx_axis_tuser_int),
.mac_2_clk(qsfp2_mac_3_clk_int),
.mac_2_rst(qsfp2_mac_3_rst_int),
.mac_2_rx_axis_tdata(qsfp2_mac_3_rx_axis_tdata_int),
.mac_2_rx_axis_tkeep(qsfp2_mac_3_rx_axis_tkeep_int),
.mac_2_rx_axis_tvalid(qsfp2_mac_3_rx_axis_tvalid_int),
.mac_2_rx_axis_tlast(qsfp2_mac_3_rx_axis_tlast_int),
.mac_2_rx_axis_tuser(qsfp2_mac_3_rx_axis_tuser_int),
.mac_2_tx_axis_tdata(qsfp2_mac_3_tx_axis_tdata_int),
.mac_2_tx_axis_tkeep(qsfp2_mac_3_tx_axis_tkeep_int),
.mac_2_tx_axis_tvalid(qsfp2_mac_3_tx_axis_tvalid_int),
.mac_2_tx_axis_tready(qsfp2_mac_3_tx_axis_tready_int),
.mac_2_tx_axis_tlast(qsfp2_mac_3_tx_axis_tlast_int),
.mac_2_tx_axis_tuser(qsfp2_mac_3_tx_axis_tuser_int),
.mac_3_clk(qsfp2_mac_2_clk_int),
.mac_3_rst(qsfp2_mac_2_rst_int),
.mac_3_rx_axis_tdata(qsfp2_mac_2_rx_axis_tdata_int),
.mac_3_rx_axis_tkeep(qsfp2_mac_2_rx_axis_tkeep_int),
.mac_3_rx_axis_tvalid(qsfp2_mac_2_rx_axis_tvalid_int),
.mac_3_rx_axis_tlast(qsfp2_mac_2_rx_axis_tlast_int),
.mac_3_rx_axis_tuser(qsfp2_mac_2_rx_axis_tuser_int),
.mac_3_tx_axis_tdata(qsfp2_mac_2_tx_axis_tdata_int),
.mac_3_tx_axis_tkeep(qsfp2_mac_2_tx_axis_tkeep_int),
.mac_3_tx_axis_tvalid(qsfp2_mac_2_tx_axis_tvalid_int),
.mac_3_tx_axis_tready(qsfp2_mac_2_tx_axis_tready_int),
.mac_3_tx_axis_tlast(qsfp2_mac_2_tx_axis_tlast_int),
.mac_3_tx_axis_tuser(qsfp2_mac_2_tx_axis_tuser_int),
.mac_4_clk(qsfp2_mac_4_clk_int),
.mac_4_rst(qsfp2_mac_4_rst_int),
.mac_4_rx_axis_tdata(qsfp2_mac_4_rx_axis_tdata_int),
.mac_4_rx_axis_tkeep(qsfp2_mac_4_rx_axis_tkeep_int),
.mac_4_rx_axis_tvalid(qsfp2_mac_4_rx_axis_tvalid_int),
.mac_4_rx_axis_tlast(qsfp2_mac_4_rx_axis_tlast_int),
.mac_4_rx_axis_tuser(qsfp2_mac_4_rx_axis_tuser_int),
.mac_4_tx_axis_tdata(qsfp2_mac_4_tx_axis_tdata_int),
.mac_4_tx_axis_tkeep(qsfp2_mac_4_tx_axis_tkeep_int),
.mac_4_tx_axis_tvalid(qsfp2_mac_4_tx_axis_tvalid_int),
.mac_4_tx_axis_tready(qsfp2_mac_4_tx_axis_tready_int),
.mac_4_tx_axis_tlast(qsfp2_mac_4_tx_axis_tlast_int),
.mac_4_tx_axis_tuser(qsfp2_mac_4_tx_axis_tuser_int)
);
// Core logic
fpga_core
core_inst (
/*
* Clock: 161.1328125 MHz
* Synchronous reset
*/
.clk(clk_161mhz),
.rst(rst_161mhz),
/*
* GPIO
*/
.btn(btn_int),
.led(led_int),
/*
* Ethernet: QSFP28
*/
.qsfp1_mac_1_rx_clk(qsfp1_mac_1_clk_int),
.qsfp1_mac_1_rx_rst(qsfp1_mac_1_rst_int),
.qsfp1_mac_1_rx_axis_tdata(qsfp1_mac_1_rx_axis_tdata_int),
.qsfp1_mac_1_rx_axis_tkeep(qsfp1_mac_1_rx_axis_tkeep_int),
.qsfp1_mac_1_rx_axis_tvalid(qsfp1_mac_1_rx_axis_tvalid_int),
.qsfp1_mac_1_rx_axis_tlast(qsfp1_mac_1_rx_axis_tlast_int),
.qsfp1_mac_1_rx_axis_tuser(qsfp1_mac_1_rx_axis_tuser_int),
.qsfp1_mac_1_tx_clk(qsfp1_mac_1_clk_int),
.qsfp1_mac_1_tx_rst(qsfp1_mac_1_rst_int),
.qsfp1_mac_1_tx_axis_tdata(qsfp1_mac_1_tx_axis_tdata_int),
.qsfp1_mac_1_tx_axis_tkeep(qsfp1_mac_1_tx_axis_tkeep_int),
.qsfp1_mac_1_tx_axis_tvalid(qsfp1_mac_1_tx_axis_tvalid_int),
.qsfp1_mac_1_tx_axis_tready(qsfp1_mac_1_tx_axis_tready_int),
.qsfp1_mac_1_tx_axis_tlast(qsfp1_mac_1_tx_axis_tlast_int),
.qsfp1_mac_1_tx_axis_tuser(qsfp1_mac_1_tx_axis_tuser_int),
.qsfp1_mac_2_rx_clk(qsfp1_mac_2_clk_int),
.qsfp1_mac_2_rx_rst(qsfp1_mac_2_rst_int),
.qsfp1_mac_2_rx_axis_tdata(qsfp1_mac_2_rx_axis_tdata_int),
.qsfp1_mac_2_rx_axis_tkeep(qsfp1_mac_2_rx_axis_tkeep_int),
.qsfp1_mac_2_rx_axis_tvalid(qsfp1_mac_2_rx_axis_tvalid_int),
.qsfp1_mac_2_rx_axis_tlast(qsfp1_mac_2_rx_axis_tlast_int),
.qsfp1_mac_2_rx_axis_tuser(qsfp1_mac_2_rx_axis_tuser_int),
.qsfp1_mac_2_tx_clk(qsfp1_mac_2_clk_int),
.qsfp1_mac_2_tx_rst(qsfp1_mac_2_rst_int),
.qsfp1_mac_2_tx_axis_tdata(qsfp1_mac_2_tx_axis_tdata_int),
.qsfp1_mac_2_tx_axis_tkeep(qsfp1_mac_2_tx_axis_tkeep_int),
.qsfp1_mac_2_tx_axis_tvalid(qsfp1_mac_2_tx_axis_tvalid_int),
.qsfp1_mac_2_tx_axis_tready(qsfp1_mac_2_tx_axis_tready_int),
.qsfp1_mac_2_tx_axis_tlast(qsfp1_mac_2_tx_axis_tlast_int),
.qsfp1_mac_2_tx_axis_tuser(qsfp1_mac_2_tx_axis_tuser_int),
.qsfp1_mac_3_rx_clk(qsfp1_mac_3_clk_int),
.qsfp1_mac_3_rx_rst(qsfp1_mac_3_rst_int),
.qsfp1_mac_3_rx_axis_tdata(qsfp1_mac_3_rx_axis_tdata_int),
.qsfp1_mac_3_rx_axis_tkeep(qsfp1_mac_3_rx_axis_tkeep_int),
.qsfp1_mac_3_rx_axis_tvalid(qsfp1_mac_3_rx_axis_tvalid_int),
.qsfp1_mac_3_rx_axis_tlast(qsfp1_mac_3_rx_axis_tlast_int),
.qsfp1_mac_3_rx_axis_tuser(qsfp1_mac_3_rx_axis_tuser_int),
.qsfp1_mac_3_tx_clk(qsfp1_mac_3_clk_int),
.qsfp1_mac_3_tx_rst(qsfp1_mac_3_rst_int),
.qsfp1_mac_3_tx_axis_tdata(qsfp1_mac_3_tx_axis_tdata_int),
.qsfp1_mac_3_tx_axis_tkeep(qsfp1_mac_3_tx_axis_tkeep_int),
.qsfp1_mac_3_tx_axis_tvalid(qsfp1_mac_3_tx_axis_tvalid_int),
.qsfp1_mac_3_tx_axis_tready(qsfp1_mac_3_tx_axis_tready_int),
.qsfp1_mac_3_tx_axis_tlast(qsfp1_mac_3_tx_axis_tlast_int),
.qsfp1_mac_3_tx_axis_tuser(qsfp1_mac_3_tx_axis_tuser_int),
.qsfp1_mac_4_rx_clk(qsfp1_mac_4_clk_int),
.qsfp1_mac_4_rx_rst(qsfp1_mac_4_rst_int),
.qsfp1_mac_4_rx_axis_tdata(qsfp1_mac_4_rx_axis_tdata_int),
.qsfp1_mac_4_rx_axis_tkeep(qsfp1_mac_4_rx_axis_tkeep_int),
.qsfp1_mac_4_rx_axis_tvalid(qsfp1_mac_4_rx_axis_tvalid_int),
.qsfp1_mac_4_rx_axis_tlast(qsfp1_mac_4_rx_axis_tlast_int),
.qsfp1_mac_4_rx_axis_tuser(qsfp1_mac_4_rx_axis_tuser_int),
.qsfp1_mac_4_tx_clk(qsfp1_mac_4_clk_int),
.qsfp1_mac_4_tx_rst(qsfp1_mac_4_rst_int),
.qsfp1_mac_4_tx_axis_tdata(qsfp1_mac_4_tx_axis_tdata_int),
.qsfp1_mac_4_tx_axis_tkeep(qsfp1_mac_4_tx_axis_tkeep_int),
.qsfp1_mac_4_tx_axis_tvalid(qsfp1_mac_4_tx_axis_tvalid_int),
.qsfp1_mac_4_tx_axis_tready(qsfp1_mac_4_tx_axis_tready_int),
.qsfp1_mac_4_tx_axis_tlast(qsfp1_mac_4_tx_axis_tlast_int),
.qsfp1_mac_4_tx_axis_tuser(qsfp1_mac_4_tx_axis_tuser_int),
.qsfp2_mac_1_rx_clk(qsfp2_mac_1_clk_int),
.qsfp2_mac_1_rx_rst(qsfp2_mac_1_rst_int),
.qsfp2_mac_1_rx_axis_tdata(qsfp2_mac_1_rx_axis_tdata_int),
.qsfp2_mac_1_rx_axis_tkeep(qsfp2_mac_1_rx_axis_tkeep_int),
.qsfp2_mac_1_rx_axis_tvalid(qsfp2_mac_1_rx_axis_tvalid_int),
.qsfp2_mac_1_rx_axis_tlast(qsfp2_mac_1_rx_axis_tlast_int),
.qsfp2_mac_1_rx_axis_tuser(qsfp2_mac_1_rx_axis_tuser_int),
.qsfp2_mac_1_tx_clk(qsfp2_mac_1_clk_int),
.qsfp2_mac_1_tx_rst(qsfp2_mac_1_rst_int),
.qsfp2_mac_1_tx_axis_tdata(qsfp2_mac_1_tx_axis_tdata_int),
.qsfp2_mac_1_tx_axis_tkeep(qsfp2_mac_1_tx_axis_tkeep_int),
.qsfp2_mac_1_tx_axis_tvalid(qsfp2_mac_1_tx_axis_tvalid_int),
.qsfp2_mac_1_tx_axis_tready(qsfp2_mac_1_tx_axis_tready_int),
.qsfp2_mac_1_tx_axis_tlast(qsfp2_mac_1_tx_axis_tlast_int),
.qsfp2_mac_1_tx_axis_tuser(qsfp2_mac_1_tx_axis_tuser_int),
.qsfp2_mac_2_rx_clk(qsfp2_mac_2_clk_int),
.qsfp2_mac_2_rx_rst(qsfp2_mac_2_rst_int),
.qsfp2_mac_2_rx_axis_tdata(qsfp2_mac_2_rx_axis_tdata_int),
.qsfp2_mac_2_rx_axis_tkeep(qsfp2_mac_2_rx_axis_tkeep_int),
.qsfp2_mac_2_rx_axis_tvalid(qsfp2_mac_2_rx_axis_tvalid_int),
.qsfp2_mac_2_rx_axis_tlast(qsfp2_mac_2_rx_axis_tlast_int),
.qsfp2_mac_2_rx_axis_tuser(qsfp2_mac_2_rx_axis_tuser_int),
.qsfp2_mac_2_tx_clk(qsfp2_mac_2_clk_int),
.qsfp2_mac_2_tx_rst(qsfp2_mac_2_rst_int),
.qsfp2_mac_2_tx_axis_tdata(qsfp2_mac_2_tx_axis_tdata_int),
.qsfp2_mac_2_tx_axis_tkeep(qsfp2_mac_2_tx_axis_tkeep_int),
.qsfp2_mac_2_tx_axis_tvalid(qsfp2_mac_2_tx_axis_tvalid_int),
.qsfp2_mac_2_tx_axis_tready(qsfp2_mac_2_tx_axis_tready_int),
.qsfp2_mac_2_tx_axis_tlast(qsfp2_mac_2_tx_axis_tlast_int),
.qsfp2_mac_2_tx_axis_tuser(qsfp2_mac_2_tx_axis_tuser_int),
.qsfp2_mac_3_rx_clk(qsfp2_mac_3_clk_int),
.qsfp2_mac_3_rx_rst(qsfp2_mac_3_rst_int),
.qsfp2_mac_3_rx_axis_tdata(qsfp2_mac_3_rx_axis_tdata_int),
.qsfp2_mac_3_rx_axis_tkeep(qsfp2_mac_3_rx_axis_tkeep_int),
.qsfp2_mac_3_rx_axis_tvalid(qsfp2_mac_3_rx_axis_tvalid_int),
.qsfp2_mac_3_rx_axis_tlast(qsfp2_mac_3_rx_axis_tlast_int),
.qsfp2_mac_3_rx_axis_tuser(qsfp2_mac_3_rx_axis_tuser_int),
.qsfp2_mac_3_tx_clk(qsfp2_mac_3_clk_int),
.qsfp2_mac_3_tx_rst(qsfp2_mac_3_rst_int),
.qsfp2_mac_3_tx_axis_tdata(qsfp2_mac_3_tx_axis_tdata_int),
.qsfp2_mac_3_tx_axis_tkeep(qsfp2_mac_3_tx_axis_tkeep_int),
.qsfp2_mac_3_tx_axis_tvalid(qsfp2_mac_3_tx_axis_tvalid_int),
.qsfp2_mac_3_tx_axis_tready(qsfp2_mac_3_tx_axis_tready_int),
.qsfp2_mac_3_tx_axis_tlast(qsfp2_mac_3_tx_axis_tlast_int),
.qsfp2_mac_3_tx_axis_tuser(qsfp2_mac_3_tx_axis_tuser_int),
.qsfp2_mac_4_rx_clk(qsfp2_mac_4_clk_int),
.qsfp2_mac_4_rx_rst(qsfp2_mac_4_rst_int),
.qsfp2_mac_4_rx_axis_tdata(qsfp2_mac_4_rx_axis_tdata_int),
.qsfp2_mac_4_rx_axis_tkeep(qsfp2_mac_4_rx_axis_tkeep_int),
.qsfp2_mac_4_rx_axis_tvalid(qsfp2_mac_4_rx_axis_tvalid_int),
.qsfp2_mac_4_rx_axis_tlast(qsfp2_mac_4_rx_axis_tlast_int),
.qsfp2_mac_4_rx_axis_tuser(qsfp2_mac_4_rx_axis_tuser_int),
.qsfp2_mac_4_tx_clk(qsfp2_mac_4_clk_int),
.qsfp2_mac_4_tx_rst(qsfp2_mac_4_rst_int),
.qsfp2_mac_4_tx_axis_tdata(qsfp2_mac_4_tx_axis_tdata_int),
.qsfp2_mac_4_tx_axis_tkeep(qsfp2_mac_4_tx_axis_tkeep_int),
.qsfp2_mac_4_tx_axis_tvalid(qsfp2_mac_4_tx_axis_tvalid_int),
.qsfp2_mac_4_tx_axis_tready(qsfp2_mac_4_tx_axis_tready_int),
.qsfp2_mac_4_tx_axis_tlast(qsfp2_mac_4_tx_axis_tlast_int),
.qsfp2_mac_4_tx_axis_tuser(qsfp2_mac_4_tx_axis_tuser_int)
);
endmodule |
module test_fetch;
// Inputs
reg clock;
reg PC_source;
reg [11:0] PC_offset;
reg [11:0] ISR_adr;
reg branch_ISR;
reg stall_d;
reg stall_f;
reg flush_d;
// Outputs
wire [15:0] IR;
wire [11:0] PC;
// Instantiate the Unit Under Test (UUT)
IR_fetch uut (
.clock(clock),
.PC_source(PC_source),
.PC_offset(PC_offset),
.ISR_adr(ISR_adr),
.branch_ISR(branch_ISR),
.stall_d(stall_d),
.stall_f(stall_f),
.flush_d(flush_d),
.IR(IR),
.PC(PC)
);
initial begin
// Initialize Inputs
clock = 0;
PC_source = 0;
PC_offset = 0;
ISR_adr = 0;
branch_ISR = 0;
stall_f = 0;
stall_d = 0;
flush_d = 0;
// Wait 100 ns for global reset to finish
//#100;
#10;
#400;
flush_d = 1;
#20;
flush_d = 0;
end
always #10 clock = !clock;
endmodule |
module sky130_fd_sc_lp__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module still needs to be addressed
reg [ABUSWIDTH-1:0] PREV_BUS_ADD;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
PREV_BUS_ADD <= BUS_ADD;
end
end
always @(*) begin
if(PREV_BUS_ADD < 32)
BUS_DATA_OUT = BUS_DATA_OUT_REG;
else if(PREV_BUS_ADD < 32 + MEM_BYTES )
BUS_DATA_OUT = BUS_IN_MEM;
else
BUS_DATA_OUT = 8'hxx;
end
reg [15:0] out_bit_cnt;
wire [ADDR_SIZEB-1:0] memout_addrb;
//assign memout_addrb = out_bit_cnt-1;
assign memout_addrb = out_bit_cnt < CONF_COUNT ? out_bit_cnt-1 : CONF_COUNT-1; //do not change during wait
wire [ADDR_SIZEA-1:0] memout_addra;
wire [ABUSWIDTH-1:0] BUS_ADD_MEM;
assign BUS_ADD_MEM = BUS_ADD-32;
generate
if (OUT_BITS<=8) begin
assign memout_addra = BUS_ADD_MEM;
end else begin
assign memout_addra = {BUS_ADD_MEM[ABUSWIDTH-1:OUT_BITS/8-1], {(OUT_BITS/8-1){1'b0}}} + (OUT_BITS/8-1) - (BUS_ADD_MEM % (OUT_BITS/8)); //Byte order
end
endgenerate
reg [OUT_BITS-1:0] SEQ_OUT_MEM;
wire WEA;
assign WEA = BUS_WR && BUS_ADD >=32 && BUS_ADD < 32+MEM_BYTES;
generate
if (OUT_BITS==8) begin
reg [7:0] mem [(2**ADDR_SIZEA)-1:0];
// synthesis translate_off
//to make simulator happy (no X propagation)
integer i;
initial begin
for(i = 0; i<(2**ADDR_SIZEA); i = i + 1)
mem[i] = 0;
end
// synthesis translate_on
always @(posedge BUS_CLK) begin
if (WEA)
mem[memout_addra] <= BUS_DATA_IN;
BUS_IN_MEM <= mem[memout_addra];
end
always @(posedge SEQ_CLK)
SEQ_OUT_MEM <= mem[memout_addrb];
end else begin
wire [7:0] douta;
wire [OUT_BITS-1:0] doutb;
seq_gen_blk_mem memout(
.clka(BUS_CLK), .clkb(SEQ_CLK), .douta(douta), .doutb(doutb),
.wea(WEA), .web(1'b0), .addra(memout_addra), .addrb(memout_addrb),
.dina(BUS_DATA_IN), .dinb({OUT_BITS{1'b0}})
);
always@(*) begin
BUS_IN_MEM = douta;
SEQ_OUT_MEM = doutb;
end
end
endgenerate
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SEQ_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC_CDC;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SEQ_CLK), .pulse_out(START_SYNC_CDC));
reg DONE;
wire START_SYNC_PRE;
assign START_SYNC_PRE = (START_SYNC_CDC | (SEQ_EXT_START & CONF_EN_EXT_START));
assign START_SYNC = START_SYNC_PRE & DONE; //no START if previous not finished
wire [15:0] STOP_BIT;
assign STOP_BIT = CONF_COUNT + CONF_WAIT;
reg [15:0] REPEAT_COUNT;
reg [15:0] REPEAT_NESTED_COUNT;
reg [7:0] dev_cnt;
wire REP_START;
assign REP_START = (out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV && (CONF_REPEAT==0 || REPEAT_COUNT < CONF_REPEAT));
wire REP_NESTED_START;
assign REP_NESTED_START = (out_bit_cnt == CONF_NESTED_STOP && dev_cnt == CONF_CLK_DIV && (REPEAT_NESTED_COUNT < CONF_NESTED_REPEAT));
always @ (posedge SEQ_CLK)
if (RST_SYNC)
out_bit_cnt <= 0;
else if(START_SYNC)
out_bit_cnt <= 1;
else if(REP_START)
out_bit_cnt <= CONF_REP_START+1;
else if(REP_NESTED_START)
out_bit_cnt <= CONF_NESTED_START+1;
else if(out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV)
out_bit_cnt <= out_bit_cnt;
else if(out_bit_cnt != 0 && dev_cnt == CONF_CLK_DIV)
out_bit_cnt <= out_bit_cnt + 1;
always @ (posedge SEQ_CLK)
if (RST_SYNC | START_SYNC | REP_START)
dev_cnt <= 0;
else if(out_bit_cnt != 0 && dev_cnt == CONF_CLK_DIV)
dev_cnt <= 0;
else if(out_bit_cnt != 0)
dev_cnt <= dev_cnt + 1;
always @ (posedge SEQ_CLK)
if (RST_SYNC | START_SYNC)
REPEAT_COUNT <= 1;
else if(out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV && REPEAT_COUNT <= CONF_REPEAT)
REPEAT_COUNT <= REPEAT_COUNT + 1;
always @ (posedge SEQ_CLK)
if (RST_SYNC | START_SYNC | REP_START)
REPEAT_NESTED_COUNT <= 1;
else if(REP_NESTED_START)
REPEAT_NESTED_COUNT <= REPEAT_NESTED_COUNT + 1;
always @(posedge SEQ_CLK)
if(RST_SYNC)
DONE <= 1;
else if(START_SYNC_PRE)
DONE <= 0;
else if(REPEAT_COUNT > CONF_REPEAT)
DONE <= 1;
always @(posedge SEQ_CLK)
SEQ_OUT <= SEQ_OUT_MEM;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(SEQ_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
wire EXT_START_SYNC;
cdc_pulse_sync ext_start_pulse_sync (.clk_in(SEQ_CLK), .pulse_in(SEQ_EXT_START), .clk_out(BUS_CLK), .pulse_out(EXT_START_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START | (CONF_EN_EXT_START & EXT_START_SYNC))
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule |
module sky130_fd_sc_hd__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hd__o2bb2a_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2bb2a base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule |
module sky130_fd_sc_ls__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hs__udp_dff$PE_pp$PG$N (
Q ,
D ,
CLK ,
DATA_EN ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input DATA_EN ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule |
module resize(output wire logic[4:0] result);
reg logic[6:0] a;
assign result = (5'(a + 2));
initial begin
a = 7'd39;
end
endmodule |
module resize_test();
logic [4:0] result;
resize dut(result);
initial begin
#1;
if(result !== 5'd9) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule |
module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ ( // new ports to cater for mii with RGMII interface are added
// inputs
rgmii_in,
speed,
//data
gm_tx_d,
m_tx_d,
//control
gm_tx_en,
m_tx_en,
gm_tx_err,
m_tx_err,
reset_rx_clk,
reset_tx_clk,
rx_clk,
rx_control,
tx_clk,
// outputs:
rgmii_out,
gm_rx_d,
m_rx_d,
gm_rx_dv,
m_rx_en,
gm_rx_err,
m_rx_err,
m_rx_col,
m_rx_crs,
tx_control
);
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output [ 3: 0] rgmii_out;
output [ 7: 0] gm_rx_d;
output [ 3: 0] m_rx_d;
output gm_rx_dv;
output m_rx_en;
output gm_rx_err;
output m_rx_err;
output m_rx_col;
output m_rx_crs;
output tx_control;
input [ 3: 0] rgmii_in;
input speed;
input [ 7: 0] gm_tx_d;
input [ 3: 0] m_tx_d;
input gm_tx_en;
input m_tx_en;
input gm_tx_err;
input m_tx_err;
input reset_rx_clk;
input reset_tx_clk;
input rx_clk;
input rx_control;
input tx_clk;
wire [ 3: 0] rgmii_out;
wire [ 7: 0] gm_rx_d;
wire gm_rx_dv;
wire m_rx_en;
wire gm_rx_err;
wire m_rx_err;
wire m_rx_col;
reg m_rx_col_reg;
reg m_rx_crs;
reg rx_dv;
reg rx_err;
wire tx_control;
//wire tx_err;
reg [ 7: 0] rgmii_out_4_wire;
reg rgmii_out_1_wire_inp1;
reg rgmii_out_1_wire_inp2;
wire [ 7:0 ] rgmii_in_4_wire;
reg [ 7:0 ] rgmii_in_4_reg;
reg [ 7:0 ] rgmii_in_4_temp_reg;
wire [ 1:0 ] rgmii_in_1_wire;
reg [ 1:0 ] rgmii_in_1_temp_reg;
wire speed_reg;
reg m_tx_en_reg1;
reg m_tx_en_reg2;
reg m_tx_en_reg3;
reg m_tx_en_reg4;
assign gm_rx_d = rgmii_in_4_reg;
assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
altera_tse_rgmii_in4 the_rgmii_in4
(
.aclr (), //INPUT
.datain (rgmii_in), //INPUT
.dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
.dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
.inclock (rx_clk) //OUTPUT
);
altera_tse_rgmii_in1 the_rgmii_in1
(
.aclr (), //INPUT
.datain (rx_control), //INPUT
.dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
.dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
.inclock (rx_clk) //OUTPUT
);
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_temp_reg <= {8{1'b0}};
rgmii_in_1_temp_reg <= {2{1'b0}};
end
else begin
rgmii_in_4_temp_reg <= rgmii_in_4_wire;
rgmii_in_1_temp_reg <= rgmii_in_1_wire;
end
end
always @(posedge rx_clk or posedge reset_rx_clk)
begin
if (reset_rx_clk == 1'b1) begin
rgmii_in_4_reg <= {8{1'b0}};
rx_err <= 1'b0;
rx_dv <= 1'b0;
end
else begin
rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
rx_err <= rgmii_in_1_wire[0];
rx_dv <= rgmii_in_1_temp_reg[1];
end
end
always @(rx_dv or rx_err or rgmii_in_4_reg)
begin
m_rx_crs = 1'b0;
if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
begin
m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
end
end
always @(posedge tx_clk or posedge reset_tx_clk)
begin
if(reset_tx_clk == 1'b1)
begin
m_tx_en_reg1 <= 1'b0;
m_tx_en_reg2 <= 1'b0;
m_tx_en_reg3 <= 1'b0;
m_tx_en_reg4 <= 1'b0;
end
else
begin
m_tx_en_reg1 <= m_tx_en;
m_tx_en_reg2 <= m_tx_en_reg1;
m_tx_en_reg3 <= m_tx_en_reg2;
m_tx_en_reg4 <= m_tx_en_reg3;
end
end
always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
begin
m_rx_col_reg = 1'b0;
if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
begin
m_rx_col_reg = 1'b1;
end
end
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(m_rx_col_reg), //INPUT
.dout(m_rx_col));// OUTPUT
altera_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_2(
.clk(tx_clk), // INPUT
.reset_n(~reset_tx_clk), //INPUT
.din(speed), //INPUT
.dout(speed_reg));// OUTPUT
assign gm_rx_err = rx_err ^ rx_dv;
assign gm_rx_dv = rx_dv;
assign m_rx_err = rx_err ^ rx_dv;
assign m_rx_en = rx_dv;
// mux for Out 4
always @(*)
begin
case (speed_reg)
1'b1: rgmii_out_4_wire = gm_tx_d;
1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
endcase
end
// mux for Out 1
always @(*)
begin
case (speed_reg)
1'b1:
begin
rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
end
1'b0:
begin
rgmii_out_1_wire_inp1 = m_tx_en;
rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
end
endcase
end
altera_tse_rgmii_out4 the_rgmii_out4
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
.datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
.dataout (rgmii_out), //INPUT
.outclock (tx_clk) //OUTPUT
);
//assign tx_err = gm_tx_en ^ gm_tx_err;
altera_tse_rgmii_out1 the_rgmii_out1
(
.aclr (reset_tx_clk), //INPUT
.datain_h (rgmii_out_1_wire_inp1), //INPUT
.datain_l (rgmii_out_1_wire_inp2), //INPUT
.dataout (tx_control), //INPUT
.outclock (tx_clk) //OUTPUT
);
endmodule |
module pm(
input clk_sys,
input start,
input pon,
input work,
input hlt_n,
input stop,
input clo,
input hlt,
input cycle,
input irq,
output _wait,
output run,
input ekc_1,
input ekc_i,
input ekc_2,
input got,
input ekc_fp,
input clm,
input strob1,
input strob1b,
input strob2,
input strob2b,
input ldstate,
output sp0,
output przerw,
output si1,
output sp1,
input k2,
input panel_store,
input panel_fetch,
input panel_load,
input panel_bin,
input rdt9,
input rdt11,
input k1,
output laduj,
output k2_bin_store,
output k2fetch,
output w_rbc,
output w_rba,
output w_rbb,
input p0,
output ep0,
output stp0,
output ek2,
output ek1,
input j$,
input bcoc$,
input zs,
input p2,
input ssp$,
input sc$,
input md,
input xi,
output p,
output mc_3,
output mc_0,
output xi$,
input p4,
input b0,
input na,
input c0,
input ka2,
input ka1,
input p3,
input p1,
input nef,
input p5,
input i2,
output pp,
output ep5,
output ep4,
output ep3,
output ep1,
output ep2,
output icp1,
input exl,
input lipsp,
input gr,
input wx,
input shc,
input read_fp,
input ir7,
input inou,
input rok,
output arp1,
output lg_3,
output lg_0,
input rsc,
input ir10,
input lpb,
input ir11,
input rsb,
input ir12,
input rsa,
input lpa,
input rlp_fp,
output rc,
output rb,
output ra,
input bod,
input ir15,
input ir14,
input ir13,
input ir9,
input ir8,
output lk,
input rj,
input uj,
input lwlwt,
input sr,
input lac,
input lrcb,
input rpc,
input rc$,
input ng$,
input ls,
input oc,
input wa,
input wm,
input wz,
input ww,
input wr,
input wp,
output wls,
input ri,
input war,
input wre,
input i3,
input s_fp,
input sar$,
input lar$,
input in,
input bs,
input zb$,
output w_r,
input wic,
input i4,
input wac,
input i1,
output w_ic,
output w_ac,
output w_ar,
input wrz,
input wrs,
input mb,
input im,
input lj,
input lwrs,
input jkrb,
output lrz,
output w_bar,
output w_rm,
input we,
input ib,
input ir6,
input cb,
input i5,
input rb$,
input w$,
input i3_ex_przer,
output baa,
output bab,
output bac,
output aa,
output ab,
input at15,
input srez$,
input rz,
input wir,
input blw_pw,
output wpb, // WPB - Wskaźnik Prawego Bajtu
output bwb,
output bwa,
output kia,
output kib,
output w_ir,
input ki,
input dt_w,
input f13,
input wkb,
output mwa,
output mwb,
output mwc
);
// START, WAIT, CYCLE
wire start_reset = hlt_n | stop | clo;
wire start_clk = pon & work;
reg startq;
always @ (posedge clk_sys, posedge start_reset) begin
if (start_reset) startq <= 1'b0;
else if (start_clk | start) startq <= 1'b1;
end
wire wait_reset = start_reset | si1;
always @ (posedge clk_sys, posedge wait_reset) begin
if (wait_reset) _wait <= 1'b0;
else if (wx) _wait <= hlt;
end
reg __cycle_q;
always @ (posedge clk_sys, posedge cycle) begin
if (cycle) __cycle_q <= 1'b1;
else if (rescyc) __cycle_q <= 1'b0;
end
assign run = startq & ~_wait;
wire stpc = dpr | dprzerw;
wire ekc = ekc_1 | ekc_i | ekc_2 | p2 | p0stpc;
wire kc_reset = clo | pc;
wire rescyc = clm | strob2 | si1;
wire dpr = run | __cycle_q;
wire dprzerw = (__cycle_q | startq) & irq & ~p & mc_0;
// PR (pobranie rozkazu - instruction fetch)
// PP (przyjęcie przerwania - interrupt receive)
// KC (koniec cyklu - cycle end)
// PC (początek cyklu - cycle start)
wire kc, pc;
wire pr;
kcpc KCPC(
.clk_sys(clk_sys),
.kc_reset(kc_reset),
.ekc(ekc),
.ekc_fp(ekc_fp),
.ldstate(ldstate),
.rescyc(rescyc),
.dpr(dpr),
.clm(clm),
.dprzerw(dprzerw),
.przerw(przerw),
.pr(pr),
.kc(kc),
.pc(pc)
);
assign sp0 = ~pr & ~przerw & pc;
assign si1 = pc & przerw;
assign sp1 = ~przerw & pr & pc;
wire zerstan = kc | clm | p0;
// FETCH, STORE, LOAD, BIN (bootstrap)
wire st2k2 = strob2 & k2;
wire bin, load;
reg fetch;
wire store;
always @ (posedge clk_sys, posedge panel_store) begin
if (panel_store) store <= 1'b1;
else if (clm | st2k2) store <= 1'b0;
end
always @ (posedge clk_sys, posedge panel_fetch) begin
if (panel_fetch) fetch <= 1'b1;
else if (clm | st2k2) fetch <= 1'b0;
end
always @ (posedge clk_sys, posedge panel_load) begin
if (panel_load) load <= 1'b1;
else if (clm | st2k2) load <= 1'b0;
end
wire bin_d = ~(rdt9 & rdt11 & lg_0);
wire s1k1 = strob1 & k1;
always @ (posedge clk_sys, posedge panel_bin) begin
if (panel_bin) bin <= 1'b1;
else if (clm) bin <= 1'b0;
else if (s1k1) bin <= bin_d;
end
assign laduj = load;
wire sfl = store | fetch | load;
wire ur = k2 & (load | fetch);
wire ar_1 = k2 & ~load;
wire k2store = k2 & store;
assign k2_bin_store = k2 & (store | bin);
assign k2fetch = k2 & fetch;
wire k1s1 = k1 & strob1;
assign w_rbc = k1s1 & lg_0;
assign w_rba = k1s1 & lg_2;
assign w_rbb = k1s1 & lg_1;
// control panel state transitions
// transition to P0 state
wire psr = p0 | k2store;
wire p0stpc = p0 & stpc;
wire p0_k2 = p0 | k2;
assign ep0 = (k2 | k1) & ~bin;
assign stp0 = bin | stpc | sfl;
assign ek2 = (p0 & sfl) | (bin & lg_3 & k1);
assign ek1 = (p0_k2 & bin) | (k1 & bin & ~lg_3);
wire lg_plus_1 = (bin & k2) | (k1 & rdt9);
// P - wskaźnik przeskoku (branch indicator)
always @ (posedge clk_sys, posedge clm) begin
if (clm) p <= 1'b0;
else if (strob1) begin
if (rok & ~inou & wm) p <= 1'b1;
else if (p2) p <= 1'b0;
else if (ssp$ & w$) p <= p_d;
end
end
wire p_d = (~j$ & bcoc$) | zs;
wire p_set = (p2 & strob1) | clm;
wire setwp = strob1 & wx & md;
wire reswp = p_set | (sc$ & strob2 & p1);
wire reset_mc = reswp | (~md & p4);
// MC - premodification counter
mc MC(
.clk_sys(clk_sys),
.inc(setwp),
.reset(reset_mc),
.mc_3(mc_3),
.mc_0(mc_0)
);
assign xi$ = ~p & p1 & strob2 & xi;
wire wm_d = pr & ~c0 & na;
// WMI - wskaźnik rozkazu dwusłowowego (2-word instruction indicator)
// TODO: moved from strob2 to strob1b
// trzeba pewnie będzie ostatecznie wrócić do strob2 jakoś
reg wm_q;
always @ (posedge clk_sys) begin
if (strob1b) begin
if (~p & p1 & xi) wm_q <= 1'b0;
else wm_q <= wm_d;
end
end
wire wb_j = pr & ~b0 & na;
wire wb_k = (p4 & ~wpp) | p2;
// WBI - wskaźnik B-modyfikacji (B-modification indicator)
reg wb;
always @ (posedge clk_sys, posedge zerstan) begin
if (zerstan) wb <= 1'b0;
else if (strob1b) begin
case ({wb_j, wb_k})
2'b00: wb <= wb;
2'b01: wb <= 1'b0;
2'b10: wb <= 1'b1;
2'b11: wb <= ~wb;
endcase
end
end
// WPI - wskaźnik premodyfikacji (premodification indicator)
reg wpp;
always @ (posedge clk_sys, posedge reswp) begin
if (reswp) wpp <= 1'b0;
else if (strob1b) begin
if (wx & md) wpp <= 1'b1; // wire setwp = strob1 & wx & md;
else if (p4) wpp <= 1'b0;
end
end
wire p4wp = p4 & wpp;
// Wskaźnik Premodyfikacji lub B-modyfikacji (było: wpb)
wire wpbmod = wb | wpp;
wire bla = p4 & ka1ir6 & ~wpp;
wire nair6 = na & ir6;
wire ka12x = (na & c0) | ka2 | ka1;
wire ka1ir6 = ka1 & ir6;
// interrupt loop state transition signals
wire p3_p4 = p3 | p4;
wire p5_p4 = p5 | p4;
wire p1ef = p1 & ~nef;
wire p3ka1ir6 = p3 & ka1ir6;
wire wm_ka12x = wm_q | ka12x;
wire nair6_wpbmod = nair6 | wpbmod;
assign pp = p5 | (p3_p4 & ~nair6_wpbmod & ~p3ka1ir6) | (p1ef & ~nair6_wpbmod & ~wm_ka12x);
assign ep1 = p1ef & wm_q;
assign ep2 = p1 & nef;
assign ep3 = p1ef & ka12x;
assign ep4 = p3ka1ir6 | (p3_p4 & wpbmod) | (~wm_ka12x & p1ef & wpbmod);
assign ep5 = (p3_p4 & nair6 & ~wpbmod) | (nair6 & ~wm_ka12x & p1ef & ~wpbmod);
wire load_ac = p5_p4 | p1 | p3 | i2;
assign icp1 = (wm_q & p2) | p1 | ic_1;
wire lolk = slg2 | (strob2 & p1 & shc) | (strob1 & wm & inou);
wire downlk = strob1 & (wrwwgr | ((shc | inou) & wx));
wire wrwwgr = gr & wrww;
// group counter (licznik grupowy)
assign arp1 = ar_1 | read_fp | i3 | wrwwgr;
// LG+1
wire lg_p1 = strob1b & (i3 | wrwwgr | lg_plus_1);
// LG reset
wire lg_reset = zerstan | i1;
// LG load
wire slg1 = strob2 & ~gr & p1 & ~exl & ~lipsp; // "common" preload at P1
wire slg2 = strob1 & gr & wx; // preload for register group operations (at WX)
wire lg_2, lg_1;
wire lga, lgb, lgc;
lg LG(
.clk_sys(clk_sys),
.cu(lg_p1),
.reset(lg_reset),
.gr(gr),
.slg1(slg1),
.slg2(slg2),
.ir({ir7, ir8, ir9}),
.lg_0(lg_0),
.lg_1(lg_1),
.lg_2(lg_2),
.lg_3(lg_3),
.lga(lga),
.lgb(lgb),
.lgc(lgc)
);
wire ic_1 = wx & inou;
wire okinou = inou & rok;
// general register selectors
assign rc = _7_rkod | (p3 & ir13) | (p4 & ir10) | (p0_k2 & rsc) | (rlp_fp & 1'b0) | (w & lgc);
assign rb = _7_rkod | (p3 & ir14) | (p4 & ir11) | (p0_k2 & rsb) | (rlp_fp & lpb) | (w & lgb);
assign ra = _7_rkod | (p3 & ir15) | (p4 & ir12) | (p0_k2 & rsa) | (rlp_fp & lpa) | (w & lga);
// step counter (licznik kroków)
wire [0:3] lk_in;
assign lk_in[3] = (shc & ir15) | (gr & (ir9 | ir8)) | (inou & bod);
assign lk_in[2] = (shc & ir14) | (gr) | okinou;
assign lk_in[1] = (shc & ir13) | (gr & (~ir9 & ir8));
assign lk_in[0] = (shc & ir6);
lk CNT_LK(
.clk_sys(clk_sys),
.cd(downlk),
.i(lk_in),
.l(lolk),
.r(zerstan),
.lk(lk)
);
wire ruj = rj | uj;
wire pac = rj | uj | lwlwt;
wire lwtsr = lwlwt | sr;
wire lrcblac = lac | lrcb;
wire pat = lrcb | sr;
wire rjcpc = rj | rpc | rc$;
wire lrcbngls$ = lrcb | ng$ | ls;
wire M95_10 = ~w$ & ls;
always @ (posedge clk_sys, negedge M95_10) begin
if (~M95_10) wls <= 1'b0;
else if (wa & strob1) wls <= 1'b1;
end
wire M24_8 = ~oc & ~bs & w$;
wire M36_3 = ~ls & we;
wire w = wa | M24_8 | M36_3 | wm | wz | ww | wr | wp;
wire wrww = wr | ww;
// W bus to Rx microoperation
wire warx = (p1 & ~wpp) | (~wpp & p3) | (ri & wa) | (war & ur);
wire w_r_1 = (ur & wre) | (lipsp & lg_1 & i3) | (lwtsr & wp) | (wa & rjcpc);
wire w_r_2 = (wr & sar$) | (zb$ & we) | (lar$ & w$) | (wm & in & rok);
assign w_r = w_r_1 | s_fp | w_r_2;
wire _7_rkod = (w$ & bs) | (ls & we);
// W bus to IC, AC, AR microoperations
wire bs_wls = bs | wls;
wire wrinou = inou & wr;
assign w_ic = (lg_0 & lipsp & i3) | (ljkrb & we) | (wp & ruj) | (ur & wic) | wrinou | i4;
assign w_ac = (bs_wls & we) | (ur & wac) | (wa & lrcbngls$) | (wr & lrcblac) | load_ac;
assign w_ar = (~wls & ls & we) | (we & lwrs) | (wp & lrcb) | warx | i1 | p5_p4;
// W bus to block number (NB) and interrupt mask (RM)
assign lrz = ur & wrz;
wire wrsz = wrz ^ wrs;
assign w_bar = (wrs & ur) | (mb & wr) | (i3 & lipsp & lg_2);
assign w_rm = (wrs & ur) | (wr & im) | (lg_2 & lipsp & i3);
wire abx = (psr & wic) | (wa & rj) | (we & (lwrs | jkrb)) | (lj & ww);
wire ljkrb = lj | jkrb;
// A bus control signals
wire ib_ng = ib | ng$;
wire cb_oc = cb | oc;
wire M9_6 = (zb$ & ir6) ^ lj;
wire M9_3 = (zb$ & ~ir6) ^ lj;
wire M67_8 = (we & M9_6) | (w$ & ib_ng);
wire M72_8 = (ib_ng & w$) | (cb_oc & w$) | (we & M9_3) | (~na & p3);
wire M71_8 = (w$ & ls) | (psr & war);
wire M89_4 = ~wpb & rb$;
wire M71_6 = (~na & p3) | (w$ & M89_4);
wire M10_4 = ~ir6 & rc$;
wire M55_8 = (M10_4 & wa) | (lg_0 & i3_ex_przer);
assign baa = bla | M67_8;
assign bab = bla | M67_8 | (ka1 & p3);
assign bac = bla | M72_8;
assign aa = M71_6 | i5 | p4wp | M71_8;
assign ab = M71_6 | M55_8 | abx;
// left/right byte selection signals
wire str1wx = strob1b & wx;
reg WPB;
assign wpb = WPB;
always @ (posedge clk_sys, negedge lrcb) begin
if (~lrcb) WPB <= 1'b0;
else if (str1wx) WPB <= at15;
end
assign w_ir = (wir & ur) | pr;
// KI bus control signals
assign kia = f13 | (psr & wrs) | i3_ex_przer;
assign kib = f13 | bin;
// W bus control signals
wire bw = blw_pw | (ww & rz);
assign bwa = bw;
assign bwb = bw | (cb & wpb & wr);
wire wirpsr = wir & psr;
wire mwax = (i3_ex_przer & lg_3) | (wp & pac) | (ri & ww) | (wac & psr);
wire mwbx = (pat & wp) | (srez$ & ww);
wire M56_8 = (wrsz & psr) | (i3_ex_przer & lg_2) | (bin & k2) | (ww & ki);
wire M73_8 = (k2 & load) | (psr & wkb) | (ir6 & wa & rc$);
assign mwa = wirpsr | mwax | M56_8 | f13 | dt_w;
assign mwb = wirpsr | mwbx | M56_8 | f13 | we | w$ | p4 | M73_8;
assign mwc = wirpsr | dt_w | M73_8 | (wa & lrcb);
endmodule |
module top(
output led_r,
output led_b,
output gpio_2, // cs
output gpio_46, // clk
output gpio_47 // do
);
wire reset = 0;
wire clk_48mhz, clk = clk_48mhz;
SB_HFOSC osc(1,1,clk_48mhz);
reg [11:0] lineto_x;
reg [11:0] lineto_y;
reg lineto_strobe;
wire lineto_ready;
wire axis;
wire [11:0] value_x;
wire [11:0] value_y;
reg dac_strobe;
wire dac_ready;
lineto #(.BITS(12)) drawer(
.clk(clk),
.reset(reset),
.strobe(lineto_strobe),
.x_in(lineto_x),
.y_in(lineto_y),
.ready(lineto_ready),
.x_out(value_x),
.y_out(value_y),
.axis(axis)
);
mpc4922 dac(
.clk(clk),
.reset(reset),
.cs_pin(gpio_2),
.clk_pin(gpio_46),
.data_pin(gpio_47),
.value(axis ? value_x : value_y),
.axis(axis),
.strobe(dac_strobe),
.ready(dac_ready)
);
reg [15:0] counter;
always @(posedge clk) begin
counter <= counter + 1;
led_r = !(counter < value_x);
led_b = 1; //!dac_strobe; //!(counter < value_y);
end
always @(posedge clk)
begin
dac_strobe <= 0;
lineto_strobe <= 0;
if (!dac_ready || dac_strobe)
begin
// do nothing
end else //if (counter == 0)
begin
dac_strobe <= 1;
lineto_x <= lineto_x + 3;
lineto_y <= lineto_y + 2;
end
if (lineto_ready)
lineto_strobe <= 1;
end
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input rst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [11:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [11:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [11:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "12" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "4kx9" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "4094" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "4093" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "12" *)
(* C_RD_DEPTH = "4096" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "12" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "12" *)
(* C_WR_DEPTH = "4096" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "12" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[11:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[11:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[11:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.clk(clk),
.din(din[3:0]),
.dout(dout[3:0]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.Q(Q),
.clk(clk),
.din(din[12:4]),
.dout(dout[12:4]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.Q(Q),
.clk(clk),
.din(din[21:13]),
.dout(dout[21:13]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.Q(Q),
.clk(clk),
.din(din[30:22]),
.dout(dout[30:22]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.Q(Q),
.clk(clk),
.din(din[39:31]),
.dout(dout[39:31]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.Q(Q),
.clk(clk),
.din(din[48:40]),
.dout(dout[48:40]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.Q(Q),
.clk(clk),
.din(din[57:49]),
.dout(dout[57:49]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.Q(Q),
.clk(clk),
.din(din[63:58]),
.dout(dout[63:58]),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [3:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [3:0]din;
wire [11:0]Q;
wire clk;
wire [3:0]din;
wire [3:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [5:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [5:0]din;
wire [11:0]Q;
wire clk;
wire [5:0]din;
wire [5:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [3:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [3:0]din;
wire [11:0]Q;
wire clk;
wire [3:0]din;
wire [3:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({Q,1'b0,1'b0}),
.ADDRBWRADDR({\gc0.count_d1_reg[11] ,1'b0,1'b0}),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:4],dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [8:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [8:0]din;
wire [11:0]Q;
wire clk;
wire [8:0]din;
wire [8:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [5:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [5:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [11:0]Q;
wire clk;
wire [5:0]din;
wire [5:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[11] ,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clk),
.CLKBWRCLK(clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,din}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_78 ,dout}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ram_full_fb_i_reg),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg,ram_full_fb_i_reg}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(ram_full_comb,
v1_reg,
wr_en,
comp1,
wr_rst_busy,
out,
E);
output ram_full_comb;
input [5:0]v1_reg;
input wr_en;
input comp1;
input wr_rst_busy;
input out;
input [0:0]E;
wire [0:0]E;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire out;
wire ram_full_comb;
wire [5:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
LUT6 #(
.INIT(64'h0055000000FFC0C0))
ram_full_fb_i_i_1
(.I0(comp0),
.I1(wr_en),
.I2(comp1),
.I3(wr_rst_busy),
.I4(out),
.I5(E),
.O(ram_full_comb));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
(comp1,
v1_reg_0);
output comp1;
input [5:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire [5:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg_0[5:4]}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
(ram_empty_i_reg,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
rd_en,
out,
comp1,
wr_en,
ram_full_fb_i_reg);
output ram_empty_i_reg;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input rd_en;
input out;
input comp1;
input wr_en;
input ram_full_fb_i_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp0;
wire comp1;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire rd_en;
wire wr_en;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S({\gcc0.gc0.count_d1_reg[6] ,\gcc0.gc0.count_d1_reg[4] ,\gcc0.gc0.count_d1_reg[2] ,\gcc0.gc0.count_d1_reg[0] }));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp0,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],\gcc0.gc0.count_d1_reg[10] ,\gcc0.gc0.count_d1_reg[8] }));
LUT6 #(
.INIT(64'hFCF0FCF05050FCF0))
ram_empty_fb_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.I4(wr_en),
.I5(ram_full_fb_i_reg),
.O(ram_empty_i_reg));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
(comp1,
v1_reg);
output comp1;
input [5:0]v1_reg;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire carrynet_4;
wire comp1;
wire [5:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:2],comp1,carrynet_4}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:2],1'b0,1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:2],v1_reg[5:4]}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.rd_n_14 ;
wire \gntv_or_sync_fifo.gl0.wr_n_0 ;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_21 ;
wire \gntv_or_sync_fifo.gl0.wr_n_22 ;
wire \gntv_or_sync_fifo.gl0.wr_n_23 ;
wire \gntv_or_sync_fifo.gl0.wr_n_24 ;
wire \gntv_or_sync_fifo.gl0.wr_n_25 ;
wire \gntv_or_sync_fifo.gl0.wr_n_26 ;
wire [5:0]\grss.rsts/c2/v1_reg ;
wire [11:0]p_0_out;
wire [11:0]p_11_out;
wire p_2_out;
wire rd_en;
wire [11:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_en;
wire wr_rst_busy;
wire [1:1]wr_rst_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.D(rd_pntr_plus1),
.E(\gntv_or_sync_fifo.gl0.rd_n_14 ),
.Q(p_0_out),
.clk(clk),
.empty(empty),
.\gcc0.gc0.count_d1_reg[0] (\gntv_or_sync_fifo.gl0.wr_n_21 ),
.\gcc0.gc0.count_d1_reg[10] (\gntv_or_sync_fifo.gl0.wr_n_26 ),
.\gcc0.gc0.count_d1_reg[2] (\gntv_or_sync_fifo.gl0.wr_n_22 ),
.\gcc0.gc0.count_d1_reg[4] (\gntv_or_sync_fifo.gl0.wr_n_23 ),
.\gcc0.gc0.count_d1_reg[6] (\gntv_or_sync_fifo.gl0.wr_n_24 ),
.\gcc0.gc0.count_d1_reg[8] (\gntv_or_sync_fifo.gl0.wr_n_25 ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (rd_rst_i[2]),
.out(p_2_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.rd_en(rd_en),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.D(rd_pntr_plus1),
.E(\gntv_or_sync_fifo.gl0.rd_n_14 ),
.Q(p_11_out),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[11] (p_0_out),
.\gcc0.gc0.count_d1_reg[11] (\gntv_or_sync_fifo.gl0.wr_n_2 ),
.\grstd1.grst_full.grst_f.rst_d2_reg (rst_full_ff_i),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (wr_rst_i),
.out(\gntv_or_sync_fifo.gl0.wr_n_0 ),
.ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_21 ),
.ram_empty_i_reg_0(\gntv_or_sync_fifo.gl0.wr_n_22 ),
.ram_empty_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_23 ),
.ram_empty_i_reg_2(\gntv_or_sync_fifo.gl0.wr_n_24 ),
.ram_empty_i_reg_3(\gntv_or_sync_fifo.gl0.wr_n_25 ),
.ram_empty_i_reg_4(\gntv_or_sync_fifo.gl0.wr_n_26 ),
.v1_reg(\grss.rsts/c2/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.Q(p_11_out),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (p_0_out),
.out(rd_rst_i[0]),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.tmp_ram_rd_en(tmp_ram_rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo rstblk
(.clk(clk),
.\gc0.count_reg[0] ({rd_rst_i[2],rd_rst_i[0]}),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_rst_busy(wr_rst_busy));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [11:0]prog_empty_thresh;
input [11:0]prog_empty_thresh_assert;
input [11:0]prog_empty_thresh_negate;
input [11:0]prog_full_thresh;
input [11:0]prog_full_thresh_assert;
input [11:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [11:0]data_count;
output [11:0]rd_data_count;
output [11:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[11] = \<const0> ;
assign data_count[10] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[11] = \<const0> ;
assign rd_data_count[10] = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[11] = \<const0> ;
assign wr_data_count[10] = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(wr_rst_busy,
dout,
empty,
full,
rd_en,
wr_en,
clk,
din,
rst);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
input rd_en;
input wr_en;
input clk;
input [63:0]din;
input rst;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
clk,
ram_full_fb_i_reg,
tmp_ram_rd_en,
out,
Q,
\gc0.count_d1_reg[11] ,
din);
output [63:0]dout;
input clk;
input ram_full_fb_i_reg;
input tmp_ram_rd_en;
input [0:0]out;
input [11:0]Q;
input [11:0]\gc0.count_d1_reg[11] ;
input [63:0]din;
wire [11:0]Q;
wire clk;
wire [63:0]din;
wire [63:0]dout;
wire [11:0]\gc0.count_d1_reg[11] ;
wire [0:0]out;
wire ram_full_fb_i_reg;
wire tmp_ram_rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.tmp_ram_rd_en(tmp_ram_rd_en));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(D,
Q,
ram_empty_fb_i_reg,
clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output [11:0]D;
output [11:0]Q;
input ram_empty_fb_i_reg;
input clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [11:0]D;
wire [11:0]Q;
wire clk;
wire \gc0.count[0]_i_2_n_0 ;
wire \gc0.count[0]_i_3_n_0 ;
wire \gc0.count[0]_i_4_n_0 ;
wire \gc0.count[0]_i_5_n_0 ;
wire \gc0.count[4]_i_2_n_0 ;
wire \gc0.count[4]_i_3_n_0 ;
wire \gc0.count[4]_i_4_n_0 ;
wire \gc0.count[4]_i_5_n_0 ;
wire \gc0.count[8]_i_2_n_0 ;
wire \gc0.count[8]_i_3_n_0 ;
wire \gc0.count[8]_i_4_n_0 ;
wire \gc0.count[8]_i_5_n_0 ;
wire \gc0.count_reg[0]_i_1_n_0 ;
wire \gc0.count_reg[0]_i_1_n_1 ;
wire \gc0.count_reg[0]_i_1_n_2 ;
wire \gc0.count_reg[0]_i_1_n_3 ;
wire \gc0.count_reg[0]_i_1_n_4 ;
wire \gc0.count_reg[0]_i_1_n_5 ;
wire \gc0.count_reg[0]_i_1_n_6 ;
wire \gc0.count_reg[0]_i_1_n_7 ;
wire \gc0.count_reg[4]_i_1_n_0 ;
wire \gc0.count_reg[4]_i_1_n_1 ;
wire \gc0.count_reg[4]_i_1_n_2 ;
wire \gc0.count_reg[4]_i_1_n_3 ;
wire \gc0.count_reg[4]_i_1_n_4 ;
wire \gc0.count_reg[4]_i_1_n_5 ;
wire \gc0.count_reg[4]_i_1_n_6 ;
wire \gc0.count_reg[4]_i_1_n_7 ;
wire \gc0.count_reg[8]_i_1_n_1 ;
wire \gc0.count_reg[8]_i_1_n_2 ;
wire \gc0.count_reg[8]_i_1_n_3 ;
wire \gc0.count_reg[8]_i_1_n_4 ;
wire \gc0.count_reg[8]_i_1_n_5 ;
wire \gc0.count_reg[8]_i_1_n_6 ;
wire \gc0.count_reg[8]_i_1_n_7 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire ram_empty_fb_i_reg;
wire [3:3]\NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_2
(.I0(D[3]),
.O(\gc0.count[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_3
(.I0(D[2]),
.O(\gc0.count[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[0]_i_4
(.I0(D[1]),
.O(\gc0.count[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_5
(.I0(D[0]),
.O(\gc0.count[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_2
(.I0(D[7]),
.O(\gc0.count[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_3
(.I0(D[6]),
.O(\gc0.count[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_4
(.I0(D[5]),
.O(\gc0.count[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[4]_i_5
(.I0(D[4]),
.O(\gc0.count[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_2
(.I0(D[11]),
.O(\gc0.count[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_3
(.I0(D[10]),
.O(\gc0.count[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_4
(.I0(D[9]),
.O(\gc0.count[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gc0.count[8]_i_5
(.I0(D[8]),
.O(\gc0.count[8]_i_5_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[10]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[11]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(D[9]),
.Q(Q[9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.D(\gc0.count_reg[0]_i_1_n_7 ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(D[0]));
CARRY4 \gc0.count_reg[0]_i_1
(.CI(1'b0),
.CO({\gc0.count_reg[0]_i_1_n_0 ,\gc0.count_reg[0]_i_1_n_1 ,\gc0.count_reg[0]_i_1_n_2 ,\gc0.count_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\gc0.count_reg[0]_i_1_n_4 ,\gc0.count_reg[0]_i_1_n_5 ,\gc0.count_reg[0]_i_1_n_6 ,\gc0.count_reg[0]_i_1_n_7 }),
.S({\gc0.count[0]_i_2_n_0 ,\gc0.count[0]_i_3_n_0 ,\gc0.count[0]_i_4_n_0 ,\gc0.count[0]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[10]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[8]_i_1_n_5 ),
.Q(D[10]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[11]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[8]_i_1_n_4 ),
.Q(D[11]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[0]_i_1_n_6 ),
.Q(D[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[0]_i_1_n_5 ),
.Q(D[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[0]_i_1_n_4 ),
.Q(D[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[4]_i_1_n_7 ),
.Q(D[4]));
CARRY4 \gc0.count_reg[4]_i_1
(.CI(\gc0.count_reg[0]_i_1_n_0 ),
.CO({\gc0.count_reg[4]_i_1_n_0 ,\gc0.count_reg[4]_i_1_n_1 ,\gc0.count_reg[4]_i_1_n_2 ,\gc0.count_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gc0.count_reg[4]_i_1_n_4 ,\gc0.count_reg[4]_i_1_n_5 ,\gc0.count_reg[4]_i_1_n_6 ,\gc0.count_reg[4]_i_1_n_7 }),
.S({\gc0.count[4]_i_2_n_0 ,\gc0.count[4]_i_3_n_0 ,\gc0.count[4]_i_4_n_0 ,\gc0.count[4]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[4]_i_1_n_6 ),
.Q(D[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[4]_i_1_n_5 ),
.Q(D[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[4]_i_1_n_4 ),
.Q(D[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[8]_i_1_n_7 ),
.Q(D[8]));
CARRY4 \gc0.count_reg[8]_i_1
(.CI(\gc0.count_reg[4]_i_1_n_0 ),
.CO({\NLW_gc0.count_reg[8]_i_1_CO_UNCONNECTED [3],\gc0.count_reg[8]_i_1_n_1 ,\gc0.count_reg[8]_i_1_n_2 ,\gc0.count_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gc0.count_reg[8]_i_1_n_4 ,\gc0.count_reg[8]_i_1_n_5 ,\gc0.count_reg[8]_i_1_n_6 ,\gc0.count_reg[8]_i_1_n_7 }),
.S({\gc0.count[8]_i_2_n_0 ,\gc0.count[8]_i_3_n_0 ,\gc0.count[8]_i_4_n_0 ,\gc0.count[8]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(clk),
.CE(ram_empty_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(\gc0.count_reg[8]_i_1_n_6 ),
.Q(D[9]));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(out,
empty,
D,
E,
Q,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
v1_reg,
clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output [11:0]D;
output [0:0]E;
output [11:0]Q;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input [5:0]v1_reg;
input clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire [11:0]D;
wire [0:0]E;
wire [11:0]Q;
wire clk;
wire empty;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire out;
wire ram_full_fb_i_reg;
wire rd_en;
wire [5:0]v1_reg;
wire wr_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss \grss.rsts
(.clk(clk),
.empty(empty),
.\gc0.count_d1_reg[11] (E),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.out(out),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.v1_reg(v1_reg),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.D(D),
.Q(Q),
.clk(clk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.ram_empty_fb_i_reg(E));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
(out,
empty,
\gc0.count_d1_reg[11] ,
\gcc0.gc0.count_d1_reg[0] ,
\gcc0.gc0.count_d1_reg[2] ,
\gcc0.gc0.count_d1_reg[4] ,
\gcc0.gc0.count_d1_reg[6] ,
\gcc0.gc0.count_d1_reg[8] ,
\gcc0.gc0.count_d1_reg[10] ,
v1_reg,
clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ,
rd_en,
wr_en,
ram_full_fb_i_reg);
output out;
output empty;
output \gc0.count_d1_reg[11] ;
input \gcc0.gc0.count_d1_reg[0] ;
input \gcc0.gc0.count_d1_reg[2] ;
input \gcc0.gc0.count_d1_reg[4] ;
input \gcc0.gc0.count_d1_reg[6] ;
input \gcc0.gc0.count_d1_reg[8] ;
input \gcc0.gc0.count_d1_reg[10] ;
input [5:0]v1_reg;
input clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
input rd_en;
input wr_en;
input ram_full_fb_i_reg;
wire c1_n_0;
wire clk;
wire comp1;
wire \gc0.count_d1_reg[11] ;
wire \gcc0.gc0.count_d1_reg[0] ;
wire \gcc0.gc0.count_d1_reg[10] ;
wire \gcc0.gc0.count_d1_reg[2] ;
wire \gcc0.gc0.count_d1_reg[4] ;
wire \gcc0.gc0.count_d1_reg[6] ;
wire \gcc0.gc0.count_d1_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire ram_full_fb_i_reg;
wire rd_en;
wire [5:0]v1_reg;
wire wr_en;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 c1
(.comp1(comp1),
.\gcc0.gc0.count_d1_reg[0] (\gcc0.gc0.count_d1_reg[0] ),
.\gcc0.gc0.count_d1_reg[10] (\gcc0.gc0.count_d1_reg[10] ),
.\gcc0.gc0.count_d1_reg[2] (\gcc0.gc0.count_d1_reg[2] ),
.\gcc0.gc0.count_d1_reg[4] (\gcc0.gc0.count_d1_reg[4] ),
.\gcc0.gc0.count_d1_reg[6] (\gcc0.gc0.count_d1_reg[6] ),
.\gcc0.gc0.count_d1_reg[8] (\gcc0.gc0.count_d1_reg[8] ),
.out(ram_empty_fb_i),
.ram_empty_i_reg(c1_n_0),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.rd_en(rd_en),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 c2
(.comp1(comp1),
.v1_reg(v1_reg));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[11]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(\gc0.count_d1_reg[11] ));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(c1_n_0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
(out,
\gc0.count_reg[0] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [0:0]out;
output [1:0]\gc0.count_reg[0] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire clk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[0] [1] = rd_rst_reg[2];
assign \gc0.count_reg[0] [0] = rd_rst_reg[0];
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[0] = wr_rst_reg[1];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.clk(clk),
.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.clk(clk),
.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.clk(clk),
.in0(rd_rst_asreg),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.clk(clk),
.in0(wr_rst_asreg),
.out(p_8_out));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(v1_reg_0,
Q,
v1_reg,
v1_reg_1,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
ram_empty_i_reg_4,
ram_full_fb_i_reg,
clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
\gc0.count_d1_reg[11] ,
D);
output [5:0]v1_reg_0;
output [11:0]Q;
output [5:0]v1_reg;
output [5:0]v1_reg_1;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
output ram_empty_i_reg_4;
input ram_full_fb_i_reg;
input clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input [11:0]\gc0.count_d1_reg[11] ;
input [11:0]D;
wire [11:0]D;
wire [11:0]Q;
wire clk;
wire [11:0]\gc0.count_d1_reg[11] ;
wire \gcc0.gc0.count[0]_i_2_n_0 ;
wire \gcc0.gc0.count[0]_i_3_n_0 ;
wire \gcc0.gc0.count[0]_i_4_n_0 ;
wire \gcc0.gc0.count[0]_i_5_n_0 ;
wire \gcc0.gc0.count[4]_i_2_n_0 ;
wire \gcc0.gc0.count[4]_i_3_n_0 ;
wire \gcc0.gc0.count[4]_i_4_n_0 ;
wire \gcc0.gc0.count[4]_i_5_n_0 ;
wire \gcc0.gc0.count[8]_i_2_n_0 ;
wire \gcc0.gc0.count[8]_i_3_n_0 ;
wire \gcc0.gc0.count[8]_i_4_n_0 ;
wire \gcc0.gc0.count[8]_i_5_n_0 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_0 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[0]_i_1_n_7 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_0 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[4]_i_1_n_7 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_1 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_2 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_3 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_4 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_5 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_6 ;
wire \gcc0.gc0.count_reg[8]_i_1_n_7 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [11:0]p_12_out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire ram_empty_i_reg_4;
wire ram_full_fb_i_reg;
wire [5:0]v1_reg;
wire [5:0]v1_reg_0;
wire [5:0]v1_reg_1;
wire [3:3]\NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_2
(.I0(p_12_out[3]),
.O(\gcc0.gc0.count[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_3
(.I0(p_12_out[2]),
.O(\gcc0.gc0.count[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[0]_i_4
(.I0(p_12_out[1]),
.O(\gcc0.gc0.count[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\gcc0.gc0.count[0]_i_5
(.I0(p_12_out[0]),
.O(\gcc0.gc0.count[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_2
(.I0(p_12_out[7]),
.O(\gcc0.gc0.count[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_3
(.I0(p_12_out[6]),
.O(\gcc0.gc0.count[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_4
(.I0(p_12_out[5]),
.O(\gcc0.gc0.count[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[4]_i_5
(.I0(p_12_out[4]),
.O(\gcc0.gc0.count[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_2
(.I0(p_12_out[11]),
.O(\gcc0.gc0.count[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_3
(.I0(p_12_out[10]),
.O(\gcc0.gc0.count[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_4
(.I0(p_12_out[9]),
.O(\gcc0.gc0.count[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\gcc0.gc0.count[8]_i_5
(.I0(p_12_out[8]),
.O(\gcc0.gc0.count[8]_i_5_n_0 ));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[0]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[10]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[11]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[1]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[2]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[3]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[4]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[5]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[6]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[7]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[8]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_d1_reg[9]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_12_out[9]),
.Q(Q[9]));
FDPE #(
.INIT(1'b1))
\gcc0.gc0.count_reg[0]
(.C(clk),
.CE(ram_full_fb_i_reg),
.D(\gcc0.gc0.count_reg[0]_i_1_n_7 ),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(p_12_out[0]));
CARRY4 \gcc0.gc0.count_reg[0]_i_1
(.CI(1'b0),
.CO({\gcc0.gc0.count_reg[0]_i_1_n_0 ,\gcc0.gc0.count_reg[0]_i_1_n_1 ,\gcc0.gc0.count_reg[0]_i_1_n_2 ,\gcc0.gc0.count_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\gcc0.gc0.count_reg[0]_i_1_n_4 ,\gcc0.gc0.count_reg[0]_i_1_n_5 ,\gcc0.gc0.count_reg[0]_i_1_n_6 ,\gcc0.gc0.count_reg[0]_i_1_n_7 }),
.S({\gcc0.gc0.count[0]_i_2_n_0 ,\gcc0.gc0.count[0]_i_3_n_0 ,\gcc0.gc0.count[0]_i_4_n_0 ,\gcc0.gc0.count[0]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[10]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[8]_i_1_n_5 ),
.Q(p_12_out[10]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[11]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[8]_i_1_n_4 ),
.Q(p_12_out[11]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[1]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[0]_i_1_n_6 ),
.Q(p_12_out[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[2]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[0]_i_1_n_5 ),
.Q(p_12_out[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[3]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[0]_i_1_n_4 ),
.Q(p_12_out[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[4]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[4]_i_1_n_7 ),
.Q(p_12_out[4]));
CARRY4 \gcc0.gc0.count_reg[4]_i_1
(.CI(\gcc0.gc0.count_reg[0]_i_1_n_0 ),
.CO({\gcc0.gc0.count_reg[4]_i_1_n_0 ,\gcc0.gc0.count_reg[4]_i_1_n_1 ,\gcc0.gc0.count_reg[4]_i_1_n_2 ,\gcc0.gc0.count_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gcc0.gc0.count_reg[4]_i_1_n_4 ,\gcc0.gc0.count_reg[4]_i_1_n_5 ,\gcc0.gc0.count_reg[4]_i_1_n_6 ,\gcc0.gc0.count_reg[4]_i_1_n_7 }),
.S({\gcc0.gc0.count[4]_i_2_n_0 ,\gcc0.gc0.count[4]_i_3_n_0 ,\gcc0.gc0.count[4]_i_4_n_0 ,\gcc0.gc0.count[4]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[5]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[4]_i_1_n_6 ),
.Q(p_12_out[5]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[6]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[4]_i_1_n_5 ),
.Q(p_12_out[6]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[7]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[4]_i_1_n_4 ),
.Q(p_12_out[7]));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[8]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[8]_i_1_n_7 ),
.Q(p_12_out[8]));
CARRY4 \gcc0.gc0.count_reg[8]_i_1
(.CI(\gcc0.gc0.count_reg[4]_i_1_n_0 ),
.CO({\NLW_gcc0.gc0.count_reg[8]_i_1_CO_UNCONNECTED [3],\gcc0.gc0.count_reg[8]_i_1_n_1 ,\gcc0.gc0.count_reg[8]_i_1_n_2 ,\gcc0.gc0.count_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\gcc0.gc0.count_reg[8]_i_1_n_4 ,\gcc0.gc0.count_reg[8]_i_1_n_5 ,\gcc0.gc0.count_reg[8]_i_1_n_6 ,\gcc0.gc0.count_reg[8]_i_1_n_7 }),
.S({\gcc0.gc0.count[8]_i_2_n_0 ,\gcc0.gc0.count[8]_i_3_n_0 ,\gcc0.gc0.count[8]_i_4_n_0 ,\gcc0.gc0.count[8]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\gcc0.gc0.count_reg[9]
(.C(clk),
.CE(ram_full_fb_i_reg),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gcc0.gc0.count_reg[8]_i_1_n_6 ),
.Q(p_12_out[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(Q[0]),
.I1(D[0]),
.I2(Q[1]),
.I3(D[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_12_out[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(p_12_out[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(Q[0]),
.I1(\gc0.count_d1_reg[11] [0]),
.I2(Q[1]),
.I3(\gc0.count_d1_reg[11] [1]),
.O(ram_empty_i_reg));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(Q[2]),
.I1(D[2]),
.I2(Q[3]),
.I3(D[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_12_out[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(p_12_out[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(Q[2]),
.I1(\gc0.count_d1_reg[11] [2]),
.I2(Q[3]),
.I3(\gc0.count_d1_reg[11] [3]),
.O(ram_empty_i_reg_0));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(Q[4]),
.I1(D[4]),
.I2(Q[5]),
.I3(D[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_12_out[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(p_12_out[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(Q[4]),
.I1(\gc0.count_d1_reg[11] [4]),
.I2(Q[5]),
.I3(\gc0.count_d1_reg[11] [5]),
.O(ram_empty_i_reg_1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(Q[6]),
.I1(D[6]),
.I2(Q[7]),
.I3(D[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_12_out[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(p_12_out[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(Q[6]),
.I1(\gc0.count_d1_reg[11] [6]),
.I2(Q[7]),
.I3(\gc0.count_d1_reg[11] [7]),
.O(ram_empty_i_reg_2));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(Q[8]),
.I1(D[8]),
.I2(Q[9]),
.I3(D[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_12_out[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(p_12_out[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(v1_reg_1[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(Q[8]),
.I1(\gc0.count_d1_reg[11] [8]),
.I2(Q[9]),
.I3(\gc0.count_d1_reg[11] [9]),
.O(ram_empty_i_reg_3));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1
(.I0(Q[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(Q[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(v1_reg_0[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__0
(.I0(Q[10]),
.I1(D[10]),
.I2(Q[11]),
.I3(D[11]),
.O(v1_reg[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__1
(.I0(p_12_out[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(p_12_out[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(v1_reg_1[5]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[5].gms.ms_i_1__2
(.I0(Q[10]),
.I1(\gc0.count_d1_reg[11] [10]),
.I2(Q[11]),
.I3(\gc0.count_d1_reg[11] [11]),
.O(ram_empty_i_reg_4));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(out,
full,
\gcc0.gc0.count_d1_reg[11] ,
Q,
v1_reg,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_empty_i_reg_1,
ram_empty_i_reg_2,
ram_empty_i_reg_3,
ram_empty_i_reg_4,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
wr_en,
\gc0.count_d1_reg[11] ,
D,
wr_rst_busy,
E);
output out;
output full;
output \gcc0.gc0.count_d1_reg[11] ;
output [11:0]Q;
output [5:0]v1_reg;
output ram_empty_i_reg;
output ram_empty_i_reg_0;
output ram_empty_i_reg_1;
output ram_empty_i_reg_2;
output ram_empty_i_reg_3;
output ram_empty_i_reg_4;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input wr_en;
input [11:0]\gc0.count_d1_reg[11] ;
input [11:0]D;
input wr_rst_busy;
input [0:0]E;
wire [11:0]D;
wire [0:0]E;
wire [11:0]Q;
wire [5:0]\c0/v1_reg ;
wire [5:0]\c1/v1_reg ;
wire clk;
wire full;
wire [11:0]\gc0.count_d1_reg[11] ;
wire \gcc0.gc0.count_d1_reg[11] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire out;
wire ram_empty_i_reg;
wire ram_empty_i_reg_0;
wire ram_empty_i_reg_1;
wire ram_empty_i_reg_2;
wire ram_empty_i_reg_3;
wire ram_empty_i_reg_4;
wire [5:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss \gwss.wsts
(.E(E),
.clk(clk),
.full(full),
.\gcc0.gc0.count_d1_reg[11] (\gcc0.gc0.count_d1_reg[11] ),
.\grstd1.grst_full.grst_f.rst_d2_reg (\grstd1.grst_full.grst_f.rst_d2_reg ),
.out(out),
.v1_reg(\c0/v1_reg ),
.v1_reg_0(\c1/v1_reg ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.D(D),
.Q(Q),
.clk(clk),
.\gc0.count_d1_reg[11] (\gc0.count_d1_reg[11] ),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.ram_empty_i_reg(ram_empty_i_reg),
.ram_empty_i_reg_0(ram_empty_i_reg_0),
.ram_empty_i_reg_1(ram_empty_i_reg_1),
.ram_empty_i_reg_2(ram_empty_i_reg_2),
.ram_empty_i_reg_3(ram_empty_i_reg_3),
.ram_empty_i_reg_4(ram_empty_i_reg_4),
.ram_full_fb_i_reg(\gcc0.gc0.count_d1_reg[11] ),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.v1_reg_1(\c1/v1_reg ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
(out,
full,
\gcc0.gc0.count_d1_reg[11] ,
v1_reg,
v1_reg_0,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
wr_rst_busy,
E);
output out;
output full;
output \gcc0.gc0.count_d1_reg[11] ;
input [5:0]v1_reg;
input [5:0]v1_reg_0;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input wr_rst_busy;
input [0:0]E;
wire [0:0]E;
wire clk;
wire comp1;
wire \gcc0.gc0.count_d1_reg[11] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire ram_afull_fb;
(* DONT_TOUCH *) wire ram_afull_i;
wire ram_full_comb;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [5:0]v1_reg;
wire [5:0]v1_reg_0;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(\gcc0.gc0.count_d1_reg[11] ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c0
(.E(E),
.comp1(comp1),
.out(ram_full_fb_i),
.ram_full_comb(ram_full_comb),
.v1_reg(v1_reg),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b1),
.O(ram_afull_i));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b1),
.O(ram_afull_fb));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module axi_traffic_gen_v2_0_id_track
#(
parameter ID_WIDTH = 1
) (
input Clk ,
input rst_l ,
input [ID_WIDTH-1:0] in_push_id ,
input in_push ,
input [ID_WIDTH-1:0] in_search_id ,
input [3:0] in_clear_pos ,
input in_only_entry0,
output [3:0] out_push_pos ,
output [3:0] out_search_hit,
output [3:0] out_free
);
reg [ID_WIDTH:0] id_arr0_ff, id_arr1_ff, id_arr2_ff, id_arr3_ff;
reg [3:0] push_pos_ff, push_pos_2ff;
reg [3:0] in_clear_pos_ff;
wire [ID_WIDTH:0] push_id = { 1'b1, in_push_id[ID_WIDTH-1:0] };
wire [3:0] push_search = { (push_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(push_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] free_pre = { ~id_arr3_ff[ID_WIDTH], ~id_arr2_ff[ID_WIDTH],
~id_arr1_ff[ID_WIDTH], ~id_arr0_ff[ID_WIDTH] };
wire [3:0] free = (in_only_entry0) ? { 3'b000, free_pre[0] } : free_pre[3:0];
wire [3:0] first_free = (free[0]) ? 4'h1 :
(free[1]) ? 4'h2 :
(free[2]) ? 4'h4 :
(free[3]) ? 4'h8 : 4'h0;
wire [3:0] push_pos = (in_push == 1'b0) ? 4'h0 :
(push_search[3:0] != 4'h0) ? push_search[3:0] :
first_free[3:0];
wire [ID_WIDTH:0] search_id = { 1'b1, in_search_id[ID_WIDTH-1:0] };
wire [3:0] search_pos = { (search_id[ID_WIDTH:0] == id_arr3_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr2_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr1_ff[ID_WIDTH:0]),
(search_id[ID_WIDTH:0] == id_arr0_ff[ID_WIDTH:0]) };
wire [3:0] do_clear = ~push_pos_ff[3:0] & ~push_pos_2ff[3:0] &
in_clear_pos_ff[3:0];
wire [ID_WIDTH:0] id_arr0 = (push_pos[0]) ? push_id[ID_WIDTH:0] :
{ (do_clear[0]) ? 1'b0:id_arr0_ff[ID_WIDTH], id_arr0_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr1 = (push_pos[1]) ? push_id[ID_WIDTH:0] :
{ (do_clear[1]) ? 1'b0:id_arr1_ff[ID_WIDTH], id_arr1_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr2 = (push_pos[2]) ? push_id[ID_WIDTH:0] :
{ (do_clear[2]) ? 1'b0:id_arr2_ff[ID_WIDTH], id_arr2_ff[ID_WIDTH-1:0] };
wire [ID_WIDTH:0] id_arr3 = (push_pos[3]) ? push_id[ID_WIDTH:0] :
{ (do_clear[3]) ? 1'b0:id_arr3_ff[ID_WIDTH], id_arr3_ff[ID_WIDTH-1:0] };
always @(posedge Clk) begin
id_arr0_ff[ID_WIDTH:0] <= (rst_l) ? id_arr0[ID_WIDTH:0] : 1'b0;
id_arr1_ff[ID_WIDTH:0] <= (rst_l) ? id_arr1[ID_WIDTH:0] : 1'b0;
id_arr2_ff[ID_WIDTH:0] <= (rst_l) ? id_arr2[ID_WIDTH:0] : 1'b0;
id_arr3_ff[ID_WIDTH:0] <= (rst_l) ? id_arr3[ID_WIDTH:0] : 1'b0;
push_pos_ff[3:0] <= (rst_l) ? push_pos[3:0] : 4'h0;
push_pos_2ff[3:0] <= (rst_l) ? push_pos_ff[3:0] : 4'h0;
in_clear_pos_ff[3:0] <= (rst_l) ? in_clear_pos[3:0] : 4'h0;
end
assign out_search_hit[3:0] = search_pos[3:0];
assign out_push_pos[3:0] = push_pos[3:0];
assign out_free[3:0] = free[3:0];
endmodule |
module sky130_fd_sc_lp__clkdlybuf4s15 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule |
module pd(
input clk_sys,
input [0:15] w, // internal W bus
input strob1, // STROB1
input strob1b, // STROB1 back
input w_ir, // W -> IR: send bus W to instruction register IR
output [0:15] ir, // IR register
input si1, // invalidate IR contents
// --- Instructions ------------------------------------------------------
output ls, // LS
output rj, // RJ
output bs, // BS
output ou, // OU
output in, // IN
output is, // IS
output ri, // RI
output pufa, // any of the wide or floating point arithmetic instructions
output rb$, // RB
output cb, // CB
output sc$, // S/C opcode group
output oc, // BRC, BLC
output ka2, // KA2 opcode group
output gr, // G/L opcode group
output hlt, // HLT
output mcl, // MCL
output sin, // SIU, SIL, SIT, CIT
output gi, // GIU, GIL
output lip, // LIP
output mb, // MB
output im, // IM
output ki, // KI
output fi, // FI
output sp, // SP
output rz, // RZ
output ib, // IB
output lpc, // LPC
output rpc, // RPC
output shc, // SHC
output rc$, // RIC, RKY
output ng$, // NGA, NGC
output zb$, // ZLB, ZRB
output uj, // UJ
output lwlwt, // LWT, LW
output lj, // LJ
output ka1, // KA1 opcode group
output exl, // EXL
output inou, // IN, OU
output sr, // SRX, SRY, SRZ, SHC (shift right)
output md, // MD
output jkrb, // JS, IRB, DRB
output lwrs, // LWS, RWS
output lrcb, // LB, CB, RB (byte-addressing ops)
output nrf, // NRF
// --- Instruction params ------------------------------------------------
output b0, // B==0 (opcode field B is 0 - no B-modification)
output c0, // C==0 (opcode field C is 0 - instruction argument is stored in the next word)
output na, // instruction with a Normal Argument
output xi, // instruction is illegal
output nef, // instruction is ineffective
input q, // Q system flag
input mc_3, // MC==3: three consecutive pre-modifications
input [0:8] r0, // upper R0 register (CPU flags)
output _0_v, // A14
input p, // P flag (branch)
output amb, // A75
output apb, // B65
output ap1, // register A plus 1 (for IRB)
output am1, // register A minus 1 (for DRB)
input wls, // A70
output bcoc$, // A89
output saryt, // SARYT: ALU operation mode (0 - logic, 1 - arythmetic)
output sd, // ALU function select
output scb, // ALU function select
output sca, // ALU function select
output sb, // ALU function select
output sab, // ALU function select
output saa, // ALU function select
output aryt, // A68
output sbar$, // B91
input at15, // A07
output ust_z, // B49
output ust_v, // A08
output ust_mc, // B80
output ust_leg, // B93
output eat0, // A13
output ust_y, // A53
output ust_x, // A47
output blr, // A87
input wpb, // A58
input wr, // A60
input pp, // A62
input ww, // B60
input wm, // A38
input wp, // A37
input wzi, // "0" indicator (Wskaźnik Zera)
// --- States ------------------------------------------------------------
input w$, // W& state
input p4, // P4 state
input we, // WE state
input wx, // WX state
input wa, // WA state
input wz, // WZ state
// --- State transitions -------------------------------------------------
output ewz, // Enter WZ
output ew$, // Enter W&
output ewe, // Enter WE
output ewa, // Enter WA
output ewp, // Enter WP
output ewr, // Enter WR
output ewm, // Enter WM
output eww, // Enter WW
output ewx, // Enter WX
output ekc_1, // EKC*1 - Enter cycle end (Koniec Cyklu)
output ekc_2, // EKC*2 - Enter cycle end (Koniec Cyklu)
output lar$, // B82
output ssp$, // B81
output p16, // A36
input lk, // LK != 0
output efp, // A11
output sar$, // A05
output srez$, // A17
output axy, // A46
output lac // B43
);
parameter INOU_USER_ILLEGAL;
wor __NC; // unconnected signals here, to suppress warnings
// IR - instruction register
wire ir_clk = strob1 & w_ir;
ir REG_IR(
.clk_sys(clk_sys),
.d(w),
.c(ir_clk),
.invalidate(si1),
.q(ir)
);
assign c0 = (ir[13:15] != 0);
wire ir13_14 = (ir[13:14] != 0);
wire ir01 = (ir[0:1] != 0);
wire b_1 = (ir[10:12] == 1);
assign b0 = (ir[10:12] == 0);
// decoder for 2-arg instructions with normal argument (opcodes 020-036 and 040-057)
// decoder for KA1 instruction group (opcodes 060-067)
wire lw, tw, rw, pw, bb, bm, bc, bn;
wire aw, ac, sw, cw, _or, om, nr, nm, er, em, xr, xm, cl, lb;
wire awt, trb, irb, drb, cwt, lwt, lws, rws, js, c, s, j, l, g, b_n;
idec1 IDEC1(
.i(ir[0:5]),
.o({lw, tw, ls, ri, rw, pw, rj, is, bb, bm, bs, bc, bn, ou, in, pufa, aw, ac, sw, cw, _or, om, nr, nm, er, em, xr, xm, cl, lb, rb$, cb, awt, trb, irb, drb, cwt, lwt, lws, rws, js, ka2, c, s, j, l, g, b_n})
);
assign sc$ = s | c;
assign oc = ka2 & ~ir[7];
assign gr = l | g;
// opcode field A register number decoder
wire [0:7] a_eq;
decoder8 DEC_A_EQ(
.i(ir[7:9]),
.ena(1'b1),
.o({a_eq})
);
// S opcode group decoder
decoder8 DEC_S(
.i(ir[7:9]),
.ena(s),
.o({hlt, mcl, sin, gi, lip, __NC, __NC, __NC})
);
// B/N opcode group decoder
decoder8 DEC_BN(
.i(ir[7:9]),
.ena(b_n),
.o({mb, im, ki, fi, sp, md, rz, ib})
);
wire ngl, srz;
decoder8 DEC_D(
.i({b_1, ir[15], ir[6]}),
.ena(c),
.o({__NC, __NC, __NC, __NC, ngl, srz, rpc, lpc})
);
assign shc = c & ir[11];
wire c_b0 = c & b0;
// C opcode group decoder
wire sx, sz, sly, slx, srxy;
decoder8 DEC_OTHER(
.i(ir[13:15]),
.ena(c_b0),
.o({rc$, zb$, sx, ng$, sz, sly, slx, srxy})
);
// --- Ineffective, illegal instr. ---------------------------------------
wire snef = (a_eq[5:7] != 0);
wire M85_11 = ir[10] | (ir[11] & ir[12]);
wire xi_1 = (INOU_USER_ILLEGAL & inou & q) | (M85_11 & c) | (q & s) | (q & ~snef & b_n);
wire xi_2 = (md & mc_3) | (c & ir13_14 & b_1) | (snef & s);
wire nef_jcs = a_eq[7] & ~r0[3];
wire nef_jys = a_eq[6] & ~r0[7];
wire nef_jxs = a_eq[5] & ~r0[8];
wire nef_jvs = a_eq[4] & ~r0[2];
wire nef_js = js & (nef_jcs | nef_jys | nef_jxs | nef_jvs);
wire nef_jg = a_eq[3] & ~r0[6];
wire nef_je = a_eq[2] & ~r0[5];
wire nef_jl = a_eq[1] & ~r0[4];
wire nef_jjs = (j | js) & (nef_jg | nef_je | nef_jl);
wire nef_jn = j & a_eq[6] & r0[5];
wire nef_jm = j & a_eq[5] & ~r0[1];
wire nef_jz = j & a_eq[4] & ~r0[0];
assign xi = ~ir01 | xi_1 | xi_2;
assign nef = xi | p | nef_js | nef_jjs | nef_jm | nef_jn | nef_jz;
// --- Instruction groups ------------------------------------------------
wire cns = ccb | ng$ | sw;
wire a = aw | ac | awt;
assign lwrs = lws | rws;
wire ans = sw | ng$ | a;
wire riirb = ri | irb;
wire krb = irb | drb;
assign jkrb = js | krb;
wire nglbb = ngl | bb;
assign bcoc$ = bc | oc;
wire wlsbs = wls | bs;
wire emnm = em | nm;
wire orxr = _or | xr;
wire lbcb = lb | cb;
assign lrcb = lbcb | rb$;
wire mis = m | is;
assign aryt = cw | cwt;
wire c$ = cw | cwt | cl;
wire ccb = c$ | cb;
assign inou = in | ou;
wire rbib = rb$ | ib;
wire bmib = bm | ib;
assign sr = srxy | srz | shc;
wire lrcbsr = lrcb | sr;
wire gmio = mcl | gi | inou;
wire hsm = hlt | sin | md;
wire sl = slx | sz | sly;
wire pcrs = rpc | lpc | rc$ | sx;
wire fimb = fi | im | mb;
// --- ALU control signals -----------------------------------------------
wire uka = ka1 & ir[6];
wire M90_8 = sl | ri | krb;
assign saryt = (we & M49_6) | (p4) | (w$ & M90_8) | ((cns ^ M90_12) & w$);
wire M90_12 = a | trb | ib;
wire M49_6 = lwrs | lj | js | krb;
assign apb = (~uka & p4) | (M90_12 & w$) | (M49_6 & we);
assign amb = (uka & p4) | (cns & w$);
wire M84_8 = riirb ^ nglbb;
wire M67_8 = bm | is | er | xr;
wire sds = (wz & (xm | em)) | (M67_8 & w$) | (w$ & M84_8) | (we & wlsbs);
wire ssb = w$ & (ngl | oc | bc);
assign sd = sds | amb;
assign sb = apb | ssb | sl | ap1;
wire M93_12 = sl | ls | orxr;
wire M50_8 = (M93_12 & w$) | (w$ & nglbb) | (wlsbs & we) | (wz & ~nm & (mis | lrcb));
wire ssab = rb$ & w$ & wpb;
wire ssaa = (rb$ & w$ & ~wpb) | (w$ & lb);
wire ssca = (M84_8 & w$) | (w$ & (bs | bn | nr)) | (wz & (emnm | lrcb)) | (we & ls);
assign sca = ssca | apb | ssaa;
assign scb = ssca | apb | ssab;
assign saa = ssaa | amb | ap1 | M50_8;
assign sab = ssab | amb | ap1 | M50_8;
assign sbar$ = lrcb | mis | (gr & ir[7]) | bm | pw | tw;
assign nrf = ir[7] & ka2 & ir[6];
wire fppn = pufa ^ nrf;
assign _0_v = js & a_eq[4] & we;
assign ap1 = riirb & w$;
assign am1 = drb & w$;
// R0 flags control signals
wire nor$ = ngl | er | nr | orxr;
assign ust_z = (nor$ & w$) | (w$ & ans) | (m & wz);
wire m = xm | om | emnm;
assign ust_v = (ans ^ (ir[6] & sl)) & w$;
assign ust_mc = ans & w$;
assign ust_leg = ccb & w$;
wire M59_8 = (ir[6] & r0[8]) | (~ir[6] & r0[7]);
assign eat0 = (srxy & M59_8) | (shc & at15); // | was ^, but there is no need for ^
assign ust_y = (w$ & sl) | (sr & ~shc & wx);
assign ust_x = wa & sx;
assign blr = w$ & oc & ~ir[6];
// execution phase control signals
wire ngrij = ng$ | ri | rj;
wire prawy = lbcb & wpb;
assign lwlwt = lwt | lw;
assign uj = j & ~a_eq[7]; // Note: jump conditions are checked during ineffective instruction tests, so everything becomes "UJ"
assign lj = j & a_eq[7];
assign ewa = (pcrs & pp) | (ngrij & pp) | (we & ~wls & ls) | (~wpb & lbcb & wr);
assign ewp = (lrcb & wx) | (wx & sr & ~lk) | (rj & wa) | (pp & (uj | lwlwt));
assign ewe = (lj & ww) | (ls & wa) | (pp & (llb | zb$ | js)) | (~wzi & krb & w$);
// execution phase control signals
// instruction cycle end signal
wire grlk = gr & lk;
wire M59_6 = rbib | (~wzi & (krb | is));
assign ekc_1 = (~lac & wr & ~grlk & ~lrcb) | (~lrcb & wp) | (~llb & we) | (~M59_6 & w$);
assign ewz = (w$ & ~wzi & is) | (wr & m) | (pp & lrcbsr);
wire M88_6 = is | rb$ | bmib | prawy;
assign ew$ = (wr & M88_6) | (we & wlsbs) | (ri & ww) | ((ng$ | lbcb) & wa) | (pp & sew$);
// control signals
assign lar$ = lb | ri | ans | trb | ls | sl | nor$ | krb;
wire M92_12 = bc | bn | bb | trb | oc;
assign ssp$ = is | bmib | M92_12 | bs;
wire sew$ = M92_12 | krb | nor$ | sl | sw | a | c$;
wire llb = bs | ls | lwrs;
assign ka1 = js | (ir[0:2] == 3'b110);
assign na = ~ka1 & ~ka2 & ~sc$ & ir01;
assign exl = ka2 & (ir[6:7] == 2'b01);
wire M63_3 = ng$ & ir[6];
wire M31_6 = ((ac | M63_3) & w$ & r0[3]) | (r0[7] & sly) | (uka & p4) | (lj & we);
assign p16 = (~M63_3 & w$ & cns) | (riirb & w$) | (ib & w$) | (slx & r0[8]) | M31_6;
// execution phase control signals
wire M60_8 = ~lk & inou;
wire M76_3 = l ^ M60_8;
assign ewr = (wp & lrcb) | (lk & wr & l) | (lws & we) | (M76_3 & wx) | M20_9 | M20_10;
wire M20_9 = M60_8 & wm;
wire M20_10 = (fimb | lac | tw) & pp;
assign ewm = gmio & pp;
assign efp = fppn & pp;
assign sar$ = l | lws | tw;
wire M75_6 = pw | rw | lj | rz | ki;
assign eww = (we & rws) | (pp & M75_6) | (ri & wa) | (lk & ww & g) | (wx & g) | (mis & wz) | (rbib & w$);
assign srez$ = rbib | mis; // it was ^ instead of |, but there is no need for ^
// execution phase control signal
// instruction cycle end signal
assign ewx = (lrcbsr & wz) | (pp & (gr ^ hsm)) | ((inou & lk) & wm) | (lk & (inou | sr) & wx);
assign axy = sr | (ir[6] & rbib);
assign ekc_2 = (wx & hsm) | (wm & ~inou) | (~grlk & ~lj & ~ri & ww) | (pcrs & wa);
assign lac = bmib | mis;
endmodule |
module mod_grid_display(
input in_pix_clk, // Clock to sync all pixel inputs/outputs to
input [9:0] in_pix_x, // Current pixel output position (x,y)
input [9:0] in_pix_y,
input in_latch,
input [7:0] in_pixel_r, // Parent video pixel data to overlay on
input [7:0] in_pixel_g,
input [7:0] in_pixel_b,
output [7:0] out_pixel_r, // Video pixel data after overlay
output [7:0] out_pixel_g,
output [7:0] out_pixel_b
);
reg is_overlay;
reg [7:0] pixel_r;
reg [7:0] pixel_g;
reg [7:0] pixel_b;
always @(posedge in_pix_clk) begin
if (in_pix_y[3:0] == 4'b0000 || in_pix_y[3:0] == 4'b1111) begin
is_overlay <= 1'b1;
end else if (in_pix_x[3:0] == 4'b0000 || in_pix_x[3:0] == 4'b1111) begin
is_overlay <= 1'b1;
end else begin
is_overlay <= 1'b0;
end
pixel_r <= 8'b00000000;
pixel_g <= 8'b00000000;
pixel_b <= 8'b11111111;
end
assign out_pixel_r = is_overlay ? pixel_r : in_pixel_r;
assign out_pixel_g = is_overlay ? pixel_g : in_pixel_g;
assign out_pixel_b = is_overlay ? pixel_b : in_pixel_b;
endmodule |
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy // AVR Rx buffer full
);
wire rst = ~rst_n; // make reset active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
// generate 8 pulse waveforms and output to LED array
genvar i;
generate
for (i = 0; i < 8; i=i+1) begin: pwm_gen_loop
pwm #(.CTR_SIZE(3)) pwm (
.rst(rst),
.clk(clk),
.compare(i),
.pwm(led[i])
);
end
endgenerate
//assign led[7:1] = 7'b0101010;
//blinker blinkLastLed(.clk(clk), .rst(rst), .blink(led[0]));
endmodule |
module a23_decode
(
input i_clk,
input [31:0] i_read_data,
input i_fetch_stall, // stall all stages of the cpu at the same time
input i_irq, // interrupt request
input i_firq, // Fast interrupt request
input i_dabt, // data abort interrupt request
input i_iabt, // instruction pre-fetch abort flag
input i_adex, // Address Exception
input [31:0] i_execute_address, // Registered address output by execute stage
// 2 LSBs of read address used for calculating
// shift in LDRB ops
input [7:0] i_abt_status, // Abort status
input [31:0] i_execute_status_bits, // current status bits values in execute stage
input i_multiply_done, // multiply unit is nearly done
// --------------------------------------------------
// Control signals to execute stage
// --------------------------------------------------
output reg [31:0] o_read_data = 1'd0,
output reg [4:0] o_read_data_alignment = 1'd0, // 2 LSBs of read address used for calculating shift in LDRB ops
output reg [31:0] o_imm32 = 'd0,
output reg [4:0] o_imm_shift_amount = 'd0,
output reg o_shift_imm_zero = 'd0,
output wire [3:0] o_condition,
output reg o_exclusive_exec = 'd0, // exclusive access request ( swap instruction )
output reg o_data_access_exec = 'd0, // high means the memory access is a read
// read or write, low for instruction
output wire [1:0] o_status_bits_mode,
output wire o_status_bits_irq_mask,
output wire o_status_bits_firq_mask,
output reg [3:0] o_rm_sel = 'd0,
output reg [3:0] o_rds_sel = 'd0,
output reg [3:0] o_rn_sel = 'd0,
output [3:0] o_rm_sel_nxt,
output [3:0] o_rds_sel_nxt,
output [3:0] o_rn_sel_nxt,
output reg [1:0] o_barrel_shift_amount_sel = 'd0,
output reg [1:0] o_barrel_shift_data_sel = 'd0,
output reg [1:0] o_barrel_shift_function = 'd0,
output reg [8:0] o_alu_function = 'd0,
output reg o_use_carry_in = 'd0,
output reg [1:0] o_multiply_function = 'd0,
output reg [2:0] o_interrupt_vector_sel = 'd0,
output wire [3:0] o_address_sel,
output wire [1:0] o_pc_sel,
output reg [1:0] o_byte_enable_sel = 'd0, // byte, halfword or word write
output reg [2:0] o_status_bits_sel = 'd0,
output reg [2:0] o_reg_write_sel,
output reg o_user_mode_regs_load,
output reg o_user_mode_regs_store_nxt,
output reg o_firq_not_user_mode,
output reg o_write_data_wen = 'd0,
output reg o_base_address_wen = 'd0, // save LDM base address register
// in case of data abort
output wire o_pc_wen,
output reg [14:0] o_reg_bank_wen = 'd0,
output reg [3:0] o_reg_bank_wsel = 'd0,
output reg o_status_bits_flags_wen = 'd0,
output reg o_status_bits_mode_wen = 'd0,
output reg o_status_bits_irq_mask_wen = 'd0,
output reg o_status_bits_firq_mask_wen = 'd0,
// --------------------------------------------------
// Co-Processor interface
// --------------------------------------------------
output reg [2:0] o_copro_opcode1 = 'd0,
output reg [2:0] o_copro_opcode2 = 'd0,
output reg [3:0] o_copro_crn = 'd0,
output reg [3:0] o_copro_crm = 'd0,
output reg [3:0] o_copro_num = 'd0,
output reg [1:0] o_copro_operation = 'd0, // 0 = no operation,
// 1 = Move to Amber Core Register from Coprocessor
// 2 = Move to Coprocessor from Amber Core Register
output reg o_copro_write_data_wen = 'd0,
output o_iabt_trigger,
output [31:0] o_iabt_address,
output [7:0] o_iabt_status,
output o_dabt_trigger,
output [31:0] o_dabt_address,
output [7:0] o_dabt_status
);
`include "a23_localparams.vh"
`include "a23_functions.vh"
localparam [4:0] RST_WAIT1 = 5'd0,
RST_WAIT2 = 5'd1,
INT_WAIT1 = 5'd2,
INT_WAIT2 = 5'd3,
EXECUTE = 5'd4,
PRE_FETCH_EXEC = 5'd5, // Execute the Pre-Fetched Instruction
MEM_WAIT1 = 5'd6, // conditionally decode current instruction, in case
// previous instruction does not execute in S2
MEM_WAIT2 = 5'd7,
PC_STALL1 = 5'd8, // Program Counter altered
// conditionally decude current instruction, in case
// previous instruction does not execute in S2
PC_STALL2 = 5'd9,
MTRANS_EXEC1 = 5'd10,
MTRANS_EXEC2 = 5'd11,
MTRANS_EXEC3 = 5'd12,
MTRANS_EXEC3B = 5'd13,
MTRANS_EXEC4 = 5'd14,
MTRANS5_ABORT = 5'd15,
MULT_PROC1 = 5'd16, // first cycle, save pre fetch instruction
MULT_PROC2 = 5'd17, // do multiplication
MULT_STORE = 5'd19, // save RdLo
MULT_ACCUMU = 5'd20, // Accumulate add lower 32 bits
SWAP_WRITE = 5'd22,
SWAP_WAIT1 = 5'd23,
SWAP_WAIT2 = 5'd24,
COPRO_WAIT = 5'd25;
// ========================================================
// Internal signals
// ========================================================
wire [31:0] instruction;
wire instruction_iabt; // abort flag, follows the instruction
wire instruction_adex; // address exception flag, follows the instruction
wire [31:0] instruction_address; // instruction virtual address, follows
// the instruction
wire [7:0] instruction_iabt_status; // abort status, follows the instruction
wire [1:0] instruction_sel;
reg [3:0] itype;
wire [3:0] opcode;
wire [7:0] imm8;
wire [31:0] offset12;
wire [31:0] offset24;
wire [4:0] shift_imm;
wire opcode_compare;
wire mem_op;
wire load_op;
wire store_op;
wire write_pc;
wire immediate_shifter_operand;
wire rds_use_rs;
wire branch;
wire mem_op_pre_indexed;
wire mem_op_post_indexed;
// Flop inputs
wire [31:0] imm32_nxt;
wire [4:0] imm_shift_amount_nxt;
wire shift_imm_zero_nxt;
wire [3:0] condition_nxt;
reg exclusive_exec_nxt;
reg data_access_exec_nxt;
wire shift_extend;
reg [1:0] barrel_shift_function_nxt;
wire [8:0] alu_function_nxt;
reg use_carry_in_nxt;
reg [1:0] multiply_function_nxt;
reg [1:0] status_bits_mode_nxt;
reg status_bits_irq_mask_nxt;
reg status_bits_firq_mask_nxt;
reg [1:0] barrel_shift_amount_sel_nxt;
reg [1:0] barrel_shift_data_sel_nxt;
reg [3:0] address_sel_nxt;
reg [1:0] pc_sel_nxt;
reg [1:0] byte_enable_sel_nxt;
reg [2:0] status_bits_sel_nxt;
reg [2:0] reg_write_sel_nxt;
reg user_mode_regs_load_nxt;
wire firq_not_user_mode_nxt;
// ALU Function signals
reg alu_swap_sel_nxt;
reg alu_not_sel_nxt;
reg [1:0] alu_cin_sel_nxt;
reg alu_cout_sel_nxt;
reg [3:0] alu_out_sel_nxt;
reg write_data_wen_nxt;
reg copro_write_data_wen_nxt;
reg base_address_wen_nxt;
reg pc_wen_nxt;
reg [3:0] reg_bank_wsel_nxt;
reg status_bits_flags_wen_nxt;
reg status_bits_mode_wen_nxt;
reg status_bits_irq_mask_wen_nxt;
reg status_bits_firq_mask_wen_nxt;
reg saved_current_instruction_wen; // saved load instruction
reg pre_fetch_instruction_wen; // pre-fetch instruction
reg [4:0] control_state = RST_WAIT1;
reg [4:0] control_state_nxt;
wire dabt;
reg dabt_reg = 'd0;
reg dabt_reg_d1;
reg iabt_reg = 'd0;
reg adex_reg = 'd0;
reg [31:0] abt_address_reg = 'd0;
reg [7:0] abt_status_reg = 'd0;
reg [31:0] saved_current_instruction = 'd0;
reg saved_current_instruction_iabt = 'd0; // access abort flag
reg saved_current_instruction_adex = 'd0; // address exception
reg [31:0] saved_current_instruction_address = 'd0; // virtual address of abort instruction
reg [7:0] saved_current_instruction_iabt_status = 'd0; // status of abort instruction
reg [31:0] pre_fetch_instruction = 'd0;
reg pre_fetch_instruction_iabt = 'd0; // access abort flag
reg pre_fetch_instruction_adex = 'd0; // address exception
reg [31:0] pre_fetch_instruction_address = 'd0; // virtual address of abort instruction
reg [7:0] pre_fetch_instruction_iabt_status = 'd0; // status of abort instruction
wire instruction_valid;
wire instruction_execute;
reg [3:0] mtrans_reg; // the current register being accessed as part of STM/LDM
reg [3:0] mtrans_reg_d1 = 'd0; // delayed by 1 period
reg [3:0] mtrans_reg_d2 = 'd0; // delayed by 2 periods
reg [31:0] mtrans_instruction_nxt;
wire [31:0] mtrans_base_reg_change;
wire [4:0] mtrans_num_registers;
wire use_saved_current_instruction;
wire use_pre_fetch_instruction;
wire interrupt;
wire [1:0] interrupt_mode;
wire [2:0] next_interrupt;
reg irq = 'd0;
reg firq = 'd0;
wire firq_request;
wire irq_request;
wire swi_request;
wire und_request;
wire dabt_request;
reg [1:0] copro_operation_nxt;
reg mtrans_r15 = 'd0;
reg mtrans_r15_nxt;
reg restore_base_address = 'd0;
reg restore_base_address_nxt;
wire regop_set_flags;
// ========================================================
// registers for output ports with non-zero initial values
// ========================================================
reg [3:0] condition_r = 4'he; // 4'he = al
reg [1:0] status_bits_mode_r = 2'b11; // SVC
reg status_bits_irq_mask_r = 1'd1;
reg status_bits_firq_mask_r = 1'd1;
reg [3:0] address_sel_r = 4'd2;
reg [1:0] pc_sel_r = 2'd2;
reg pc_wen_r = 1'd1;
assign o_condition = condition_r;
assign o_status_bits_mode = status_bits_mode_r;
assign o_status_bits_irq_mask = status_bits_irq_mask_r;
assign o_status_bits_firq_mask = status_bits_firq_mask_r;
assign o_address_sel = address_sel_r;
assign o_pc_sel = pc_sel_r;
assign o_pc_wen = pc_wen_r;
// ========================================================
// Instruction Abort and Data Abort outputs
// ========================================================
assign o_iabt_trigger = instruction_iabt && status_bits_mode_r == SVC && control_state == INT_WAIT1;
assign o_iabt_address = instruction_address;
assign o_iabt_status = instruction_iabt_status;
assign o_dabt_trigger = dabt_reg && !dabt_reg_d1;
assign o_dabt_address = abt_address_reg;
assign o_dabt_status = abt_status_reg;
// ========================================================
// Instruction Decode
// ========================================================
// for instructions that take more than one cycle
// the instruction is saved in the 'saved_mem_instruction'
// register and then that register is used for the rest of
// the execution of the instruction.
// But if the instruction does not execute because of the
// condition, then need to select the next instruction to
// decode
assign use_saved_current_instruction = instruction_execute &&
( control_state == MEM_WAIT1 ||
control_state == MEM_WAIT2 ||
control_state == MTRANS_EXEC1 ||
control_state == MTRANS_EXEC2 ||
control_state == MTRANS_EXEC3 ||
control_state == MTRANS_EXEC3B ||
control_state == MTRANS_EXEC4 ||
control_state == MTRANS5_ABORT ||
control_state == MULT_PROC1 ||
control_state == MULT_PROC2 ||
control_state == MULT_ACCUMU ||
control_state == MULT_STORE ||
control_state == INT_WAIT1 ||
control_state == INT_WAIT2 ||
control_state == SWAP_WRITE ||
control_state == SWAP_WAIT1 ||
control_state == SWAP_WAIT2 ||
control_state == COPRO_WAIT );
assign use_pre_fetch_instruction = control_state == PRE_FETCH_EXEC;
assign instruction_sel = use_saved_current_instruction ? 2'd1 : // saved_current_instruction
use_pre_fetch_instruction ? 2'd2 : // pre_fetch_instruction
2'd0 ; // o_read_data
assign instruction = instruction_sel == 2'd0 ? o_read_data :
instruction_sel == 2'd1 ? saved_current_instruction :
pre_fetch_instruction ;
// abort flag
assign instruction_iabt = instruction_sel == 2'd0 ? iabt_reg :
instruction_sel == 2'd1 ? saved_current_instruction_iabt :
pre_fetch_instruction_iabt ;
assign instruction_address = instruction_sel == 2'd0 ? abt_address_reg :
instruction_sel == 2'd1 ? saved_current_instruction_address :
pre_fetch_instruction_address ;
assign instruction_iabt_status = instruction_sel == 2'd0 ? abt_status_reg :
instruction_sel == 2'd1 ? saved_current_instruction_iabt_status :
pre_fetch_instruction_iabt_status ;
// instruction address exception
assign instruction_adex = instruction_sel == 2'd0 ? adex_reg :
instruction_sel == 2'd1 ? saved_current_instruction_adex :
pre_fetch_instruction_adex ;
// Instruction Decode - Order is important!
always @*
casez ({instruction[27:20], instruction[7:4]})
12'b00010?001001 : itype = SWAP;
12'b000000??1001 : itype = MULT;
12'b00?????????? : itype = REGOP;
12'b01?????????? : itype = TRANS;
12'b100????????? : itype = MTRANS;
12'b101????????? : itype = BRANCH;
12'b110????????? : itype = CODTRANS;
12'b1110???????0 : itype = COREGOP;
12'b1110???????1 : itype = CORTRANS;
default: itype = SWI;
endcase
// ========================================================
// Fixed fields within the instruction
// ========================================================
assign opcode = instruction[24:21];
assign condition_nxt = instruction[31:28];
assign o_rm_sel_nxt = instruction[3:0];
assign o_rn_sel_nxt = branch ? 4'd15 : // Use PC to calculate branch destination
instruction[19:16] ;
assign o_rds_sel_nxt = control_state == SWAP_WRITE ? instruction[3:0] : // Rm gets written out to memory
itype == MTRANS ? mtrans_reg :
branch ? 4'd15 : // Update the PC
rds_use_rs ? instruction[11:8] :
instruction[15:12] ;
assign shift_imm = instruction[11:7];
// this is used for RRX
assign shift_extend = !instruction[25] && !instruction[4] && !(|instruction[11:7]) && instruction[6:5] == 2'b11;
assign offset12 = { 20'h0, instruction[11:0]};
assign offset24 = {{6{instruction[23]}}, instruction[23:0], 2'd0 }; // sign extend
assign imm8 = instruction[7:0];
assign immediate_shifter_operand = instruction[25];
assign rds_use_rs = (itype == REGOP && !instruction[25] && instruction[4]) ||
(itype == MULT &&
(control_state == MULT_PROC1 ||
control_state == MULT_PROC2 ||
instruction_valid && !interrupt )) ;
assign branch = itype == BRANCH;
assign opcode_compare =
opcode == CMP ||
opcode == CMN ||
opcode == TEQ ||
opcode == TST ;
assign mem_op = itype == TRANS;
assign load_op = mem_op && instruction[20];
assign store_op = mem_op && !instruction[20];
assign write_pc = pc_wen_nxt && pc_sel_nxt != 2'd0;
assign regop_set_flags = itype == REGOP && instruction[20];
assign mem_op_pre_indexed = instruction[24] && instruction[21];
assign mem_op_post_indexed = !instruction[24];
assign imm32_nxt = // add 0 to Rm
itype == MULT ? { 32'd0 } :
// 4 x number of registers
itype == MTRANS ? { mtrans_base_reg_change } :
itype == BRANCH ? { offset24 } :
itype == TRANS ? { offset12 } :
instruction[11:8] == 4'h0 ? { 24'h0, imm8[7:0] } :
instruction[11:8] == 4'h1 ? { imm8[1:0], 24'h0, imm8[7:2] } :
instruction[11:8] == 4'h2 ? { imm8[3:0], 24'h0, imm8[7:4] } :
instruction[11:8] == 4'h3 ? { imm8[5:0], 24'h0, imm8[7:6] } :
instruction[11:8] == 4'h4 ? { imm8[7:0], 24'h0 } :
instruction[11:8] == 4'h5 ? { 2'h0, imm8[7:0], 22'h0 } :
instruction[11:8] == 4'h6 ? { 4'h0, imm8[7:0], 20'h0 } :
instruction[11:8] == 4'h7 ? { 6'h0, imm8[7:0], 18'h0 } :
instruction[11:8] == 4'h8 ? { 8'h0, imm8[7:0], 16'h0 } :
instruction[11:8] == 4'h9 ? { 10'h0, imm8[7:0], 14'h0 } :
instruction[11:8] == 4'ha ? { 12'h0, imm8[7:0], 12'h0 } :
instruction[11:8] == 4'hb ? { 14'h0, imm8[7:0], 10'h0 } :
instruction[11:8] == 4'hc ? { 16'h0, imm8[7:0], 8'h0 } :
instruction[11:8] == 4'hd ? { 18'h0, imm8[7:0], 6'h0 } :
instruction[11:8] == 4'he ? { 20'h0, imm8[7:0], 4'h0 } :
{ 22'h0, imm8[7:0], 2'h0 } ;
assign imm_shift_amount_nxt = shift_imm ;
// This signal is encoded in the decode stage because
// it is on the critical path in the execute stage
assign shift_imm_zero_nxt = imm_shift_amount_nxt == 5'd0 && // immediate amount = 0
barrel_shift_amount_sel_nxt == 2'd2; // shift immediate amount
assign alu_function_nxt = { alu_swap_sel_nxt,
alu_not_sel_nxt,
alu_cin_sel_nxt,
alu_cout_sel_nxt,
alu_out_sel_nxt };
// ========================================================
// MTRANS Operations
// ========================================================
// Bit 15 = r15
// Bit 0 = R0
// In LDM and STM instructions R0 is loaded or stored first
always @*
casez (instruction[15:0])
16'b???????????????1 : mtrans_reg = 4'h0 ;
16'b??????????????10 : mtrans_reg = 4'h1 ;
16'b?????????????100 : mtrans_reg = 4'h2 ;
16'b????????????1000 : mtrans_reg = 4'h3 ;
16'b???????????10000 : mtrans_reg = 4'h4 ;
16'b??????????100000 : mtrans_reg = 4'h5 ;
16'b?????????1000000 : mtrans_reg = 4'h6 ;
16'b????????10000000 : mtrans_reg = 4'h7 ;
16'b???????100000000 : mtrans_reg = 4'h8 ;
16'b??????1000000000 : mtrans_reg = 4'h9 ;
16'b?????10000000000 : mtrans_reg = 4'ha ;
16'b????100000000000 : mtrans_reg = 4'hb ;
16'b???1000000000000 : mtrans_reg = 4'hc ;
16'b??10000000000000 : mtrans_reg = 4'hd ;
16'b?100000000000000 : mtrans_reg = 4'he ;
default : mtrans_reg = 4'hf ;
endcase
always @*
casez (instruction[15:0])
16'b???????????????1 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 1], 1'd0};
16'b??????????????10 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 2], 2'd0};
16'b?????????????100 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 3], 3'd0};
16'b????????????1000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 4], 4'd0};
16'b???????????10000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 5], 5'd0};
16'b??????????100000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 6], 6'd0};
16'b?????????1000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 7], 7'd0};
16'b????????10000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 8], 8'd0};
16'b???????100000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15: 9], 9'd0};
16'b??????1000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:10], 10'd0};
16'b?????10000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:11], 11'd0};
16'b????100000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:12], 12'd0};
16'b???1000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:13], 13'd0};
16'b??10000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15:14], 14'd0};
16'b?100000000000000 : mtrans_instruction_nxt = {instruction[31:16], instruction[15 ], 15'd0};
default : mtrans_instruction_nxt = {instruction[31:16], 16'd0};
endcase
// number of registers to be stored
assign mtrans_num_registers = {4'd0, instruction[15]} +
{4'd0, instruction[14]} +
{4'd0, instruction[13]} +
{4'd0, instruction[12]} +
{4'd0, instruction[11]} +
{4'd0, instruction[10]} +
{4'd0, instruction[ 9]} +
{4'd0, instruction[ 8]} +
{4'd0, instruction[ 7]} +
{4'd0, instruction[ 6]} +
{4'd0, instruction[ 5]} +
{4'd0, instruction[ 4]} +
{4'd0, instruction[ 3]} +
{4'd0, instruction[ 2]} +
{4'd0, instruction[ 1]} +
{4'd0, instruction[ 0]} ;
// 4 x number of registers to be stored
assign mtrans_base_reg_change = {25'd0, mtrans_num_registers, 2'd0};
// ========================================================
// Interrupts
// ========================================================
assign firq_request = firq && !i_execute_status_bits[26];
assign irq_request = irq && !i_execute_status_bits[27];
assign swi_request = itype == SWI;
assign dabt_request = dabt_reg;
// copro15 and copro13 only supports reg trans opcodes
// all other opcodes involving co-processors cause an
// undefined instrution interrupt
assign und_request = itype == CODTRANS ||
itype == COREGOP ||
( itype == CORTRANS && instruction[11:8] != 4'd15 );
// in order of priority !!
// Highest
// 1 Reset
// 2 Data Abort (including data TLB miss)
// 3 FIRQ
// 4 IRQ
// 5 Prefetch Abort (including prefetch TLB miss)
// 6 Undefined instruction, SWI
// Lowest
assign next_interrupt = dabt_request ? 3'd1 : // Data Abort
firq_request ? 3'd2 : // FIRQ
irq_request ? 3'd3 : // IRQ
instruction_adex ? 3'd4 : // Address Exception
instruction_iabt ? 3'd5 : // PreFetch Abort, only triggered
// if the instruction is used
und_request ? 3'd6 : // Undefined Instruction
swi_request ? 3'd7 : // SWI
3'd0 ; // none
// SWI and undefined instructions do not cause an interrupt in the decode
// stage. They only trigger interrupts if they arfe executed, so the
// interrupt is triggered if the execute condition is met in the execute stage
assign interrupt = next_interrupt != 3'd0 &&
next_interrupt != 3'd7 && // SWI
next_interrupt != 3'd6 ; // undefined interrupt
assign interrupt_mode = next_interrupt == 3'd2 ? FIRQ :
next_interrupt == 3'd3 ? IRQ :
next_interrupt == 3'd4 ? SVC :
next_interrupt == 3'd5 ? SVC :
next_interrupt == 3'd6 ? SVC :
next_interrupt == 3'd7 ? SVC :
next_interrupt == 3'd1 ? SVC :
USR ;
// ========================================================
// Generate control signals
// ========================================================
always @*
begin
// default mode
status_bits_mode_nxt = i_execute_status_bits[1:0]; // change to mode in execute stage get reflected
// back to this stage automatically
status_bits_irq_mask_nxt = status_bits_irq_mask_r;
status_bits_firq_mask_nxt = status_bits_firq_mask_r;
exclusive_exec_nxt = 1'd0;
data_access_exec_nxt = 1'd0;
copro_operation_nxt = 'd0;
// Save an instruction to use later
saved_current_instruction_wen = 1'd0;
pre_fetch_instruction_wen = 1'd0;
mtrans_r15_nxt = mtrans_r15;
restore_base_address_nxt = restore_base_address;
// default Mux Select values
barrel_shift_amount_sel_nxt = 'd0; // don't shift the input
barrel_shift_data_sel_nxt = 'd0; // immediate value
barrel_shift_function_nxt = 'd0;
use_carry_in_nxt = 'd0;
multiply_function_nxt = 'd0;
address_sel_nxt = 'd0;
pc_sel_nxt = 'd0;
byte_enable_sel_nxt = 'd0;
status_bits_sel_nxt = 'd0;
reg_write_sel_nxt = 'd0;
user_mode_regs_load_nxt = 'd0;
o_user_mode_regs_store_nxt = 'd0;
// ALU Muxes
alu_swap_sel_nxt = 'd0;
alu_not_sel_nxt = 'd0;
alu_cin_sel_nxt = 'd0;
alu_cout_sel_nxt = 'd0;
alu_out_sel_nxt = 'd0;
// default Flop Write Enable values
write_data_wen_nxt = 'd0;
copro_write_data_wen_nxt = 'd0;
base_address_wen_nxt = 'd0;
pc_wen_nxt = 'd1;
reg_bank_wsel_nxt = 'hF; // Don't select any
status_bits_flags_wen_nxt = 'd0;
status_bits_mode_wen_nxt = 'd0;
status_bits_irq_mask_wen_nxt = 'd0;
status_bits_firq_mask_wen_nxt = 'd0;
if ( instruction_valid && !interrupt )
begin
if ( itype == REGOP )
begin
if ( !opcode_compare )
begin
// Check is the load destination is the PC
if (instruction[15:12] == 4'd15)
begin
pc_sel_nxt = 2'd1; // alu_out
address_sel_nxt = 4'd1; // alu_out
end
else
reg_bank_wsel_nxt = instruction[15:12];
end
if ( !immediate_shifter_operand )
barrel_shift_function_nxt = instruction[6:5];
if ( !immediate_shifter_operand )
barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
if ( !immediate_shifter_operand && instruction[4] )
barrel_shift_amount_sel_nxt = 2'd1; // Shift amount from Rs registter
if ( !immediate_shifter_operand && !instruction[4] )
barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount
// regops that do not change the overflow flag
if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ ||
opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN )
status_bits_sel_nxt = 3'd5;
if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
begin
alu_out_sel_nxt = 4'd1; // Add
use_carry_in_nxt = shift_extend;
end
if ( opcode == ADC ) // Add with Carry
begin
alu_out_sel_nxt = 4'd1; // Add
alu_cin_sel_nxt = 2'd2; // carry in from status_bits
use_carry_in_nxt = shift_extend;
end
if ( opcode == SUB || opcode == CMP ) // Subtract
begin
alu_out_sel_nxt = 4'd1; // Add
alu_cin_sel_nxt = 2'd1; // cin = 1
alu_not_sel_nxt = 1'd1; // invert B
end
// SBC (Subtract with Carry) subtracts the value of its
// second operand and the value of NOT(Carry flag) from
// the value of its first operand.
// Rd = Rn - shifter_operand - NOT(C Flag)
if ( opcode == SBC ) // Subtract with Carry
begin
alu_out_sel_nxt = 4'd1; // Add
alu_cin_sel_nxt = 2'd2; // carry in from status_bits
alu_not_sel_nxt = 1'd1; // invert B
use_carry_in_nxt = 1'd1;
end
if ( opcode == RSB ) // Reverse Subtract
begin
alu_out_sel_nxt = 4'd1; // Add
alu_cin_sel_nxt = 2'd1; // cin = 1
alu_not_sel_nxt = 1'd1; // invert B
alu_swap_sel_nxt = 1'd1; // swap A and B
end
if ( opcode == RSC ) // Reverse Subtract with carry
begin
alu_out_sel_nxt = 4'd1; // Add
alu_cin_sel_nxt = 2'd2; // carry in from status_bits
alu_not_sel_nxt = 1'd1; // invert B
alu_swap_sel_nxt = 1'd1; // swap A and B
use_carry_in_nxt = 1'd1;
end
if ( opcode == AND || opcode == TST ) // Logical AND, Test (using AND operator)
begin
alu_out_sel_nxt = 4'd8; // AND
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
end
if ( opcode == EOR || opcode == TEQ ) // Logical Exclusive OR, Test Equivalence (using EOR operator)
begin
alu_out_sel_nxt = 4'd6; // XOR
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
use_carry_in_nxt = 1'd1;
end
if ( opcode == ORR )
begin
alu_out_sel_nxt = 4'd7; // OR
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
use_carry_in_nxt = 1'd1;
end
if ( opcode == BIC ) // Bit Clear (using AND & NOT operators)
begin
alu_out_sel_nxt = 4'd8; // AND
alu_not_sel_nxt = 1'd1; // invert B
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
use_carry_in_nxt = 1'd1;
end
if ( opcode == MOV ) // Move
begin
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
use_carry_in_nxt = 1'd1;
end
if ( opcode == MVN ) // Move NOT
begin
alu_not_sel_nxt = 1'd1; // invert B
alu_cout_sel_nxt = 1'd1; // i_barrel_shift_carry
use_carry_in_nxt = 1'd1;
end
end
// Load & Store instructions
if ( mem_op )
begin
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later
pc_wen_nxt = 1'd0; // hold current PC value
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
// rather than an instruction fetch
alu_out_sel_nxt = 4'd1; // Add
if ( !instruction[23] ) // U: Subtract offset
begin
alu_cin_sel_nxt = 2'd1; // cin = 1
alu_not_sel_nxt = 1'd1; // invert B
end
if ( store_op )
begin
write_data_wen_nxt = 1'd1;
if ( itype == TRANS && instruction[22] )
byte_enable_sel_nxt = 2'd1; // Save byte
end
// need to update the register holding the address ?
// This is Rn bits [19:16]
if ( mem_op_pre_indexed || mem_op_post_indexed )
begin
// Check is the load destination is the PC
if ( o_rn_sel_nxt == 4'd15 )
pc_sel_nxt = 2'd1;
else
reg_bank_wsel_nxt = o_rn_sel_nxt;
end
// if post-indexed, then use Rn rather than ALU output, as address
if ( mem_op_post_indexed )
address_sel_nxt = 4'd4; // Rn
else
address_sel_nxt = 4'd1; // alu out
if ( instruction[25] && itype == TRANS )
barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
if ( itype == TRANS && instruction[25] && shift_imm != 5'd0 )
begin
barrel_shift_function_nxt = instruction[6:5];
barrel_shift_amount_sel_nxt = 2'd2; // imm_shift_amount
end
end
if ( itype == BRANCH )
begin
pc_sel_nxt = 2'd1; // alu_out
address_sel_nxt = 4'd1; // alu_out
alu_out_sel_nxt = 4'd1; // Add
if ( instruction[24] ) // Link
begin
reg_bank_wsel_nxt = 4'd14; // Save PC to LR
reg_write_sel_nxt = 3'd1; // pc - 32'd4
end
end
if ( itype == MTRANS )
begin
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later
pc_wen_nxt = 1'd0; // hold current PC value
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
// rather than an instruction fetch
alu_out_sel_nxt = 4'd1; // Add
mtrans_r15_nxt = instruction[15]; // load or save r15 ?
base_address_wen_nxt = 1'd1; // Save the value of the register used for the base address,
// in case of a data abort, and need to restore the value
// The spec says -
// If the instruction would have overwritten the base with data
// (that is, it has the base in the transfer list), the overwriting is prevented.
// This is true even when the abort occurs after the base word gets loaded
restore_base_address_nxt = instruction[20] &&
(instruction[15:0] & (1'd1 << instruction[19:16]));
// Increment or Decrement
if ( instruction[23] ) // increment
begin
if ( instruction[24] ) // increment before
address_sel_nxt = 4'd7; // Rn + 4
else
address_sel_nxt = 4'd4; // Rn
end
else // decrement
begin
alu_cin_sel_nxt = 2'd1; // cin = 1
alu_not_sel_nxt = 1'd1; // invert B
if ( !instruction[24] ) // decrement after
address_sel_nxt = 4'd6; // alu out + 4
else
address_sel_nxt = 4'd1; // alu out
end
// Load or store ?
if ( !instruction[20] ) // Store
write_data_wen_nxt = 1'd1;
// LDM: load into user mode registers, when in priviledged mode
// Don't use mtrans_r15 here because its not loaded yet
//if ( {instruction[22],instruction[20],instruction[15]} == 3'b110 )
if ( {instruction[22:20],instruction[15]} == 4'b1010 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
//if ( {instruction[22],instruction[20]} == 3'b10 )
if ( {instruction[22:20]} == 3'b100 )
o_user_mode_regs_store_nxt = 1'd1;
// update the base register ?
if ( instruction[21] ) // the W bit
reg_bank_wsel_nxt = o_rn_sel_nxt;
end
if ( itype == MULT )
begin
multiply_function_nxt[0] = 1'd1; // set enable
// some bits can be changed just below
saved_current_instruction_wen = 1'd1; // Save the Multiply instruction to
// refer back to later
pc_wen_nxt = 1'd0; // hold current PC value
if ( instruction[21] )
multiply_function_nxt[1] = 1'd1; // accumulate
end
// swp - do read part first
if ( itype == SWAP )
begin
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later
pc_wen_nxt = 1'd0; // hold current PC value
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
// rather than an instruction fetch
barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
address_sel_nxt = 4'd4; // Rn
exclusive_exec_nxt = 1'd1; // signal an exclusive access
end
// mcr & mrc - takes two cycles
if ( itype == CORTRANS && !und_request )
begin
saved_current_instruction_wen = 1'd1; // Save the memory access instruction to refer back to later
pc_wen_nxt = 1'd0; // hold current PC value
address_sel_nxt = 4'd3; // pc (not pc + 4)
if ( instruction[20] ) // MRC
copro_operation_nxt = 2'd1; // Register transfer from Co-Processor
else // MCR
begin
// Don't enable operation to Co-Processor until next period
// So it gets the Rd value from the execution stage at the same time
copro_operation_nxt = 2'd0;
copro_write_data_wen_nxt = 1'd1; // Rd register value to co-processor
end
end
if ( itype == SWI || und_request )
begin
// save address of next instruction to Supervisor Mode LR
reg_write_sel_nxt = 3'd1; // pc -4
reg_bank_wsel_nxt = 4'd14; // LR
address_sel_nxt = 4'd2; // interrupt_vector
pc_sel_nxt = 2'd2; // interrupt_vector
status_bits_mode_nxt = interrupt_mode; // e.g. Supervisor mode
status_bits_mode_wen_nxt = 1'd1;
// disable normal interrupts
status_bits_irq_mask_nxt = 1'd1;
status_bits_irq_mask_wen_nxt = 1'd1;
end
if ( regop_set_flags )
begin
status_bits_flags_wen_nxt = 1'd1;
// If <Rd> is r15, the ALU output is copied to the Status Bits.
// Not allowed to use r15 for mul or lma instructions
if ( instruction[15:12] == 4'd15 )
begin
status_bits_sel_nxt = 3'd1; // alu out
// Priviledged mode? Then also update the other status bits
if ( i_execute_status_bits[1:0] != USR )
begin
status_bits_mode_wen_nxt = 1'd1;
status_bits_irq_mask_wen_nxt = 1'd1;
status_bits_firq_mask_wen_nxt = 1'd1;
end
end
end
end
// Handle asynchronous interrupts.
// interrupts are processed only during execution states
// multicycle instructions must complete before the interrupt starts
// SWI, Address Exception and Undefined Instruction interrupts are only executed if the
// instruction that causes the interrupt is conditionally executed so
// its not handled here
if ( instruction_valid && interrupt && next_interrupt != 3'd6 )
begin
// Save the interrupt causing instruction to refer back to later
// This also saves the instruction abort vma and status, in the case of an
// instruction abort interrupt
saved_current_instruction_wen = 1'd1;
// save address of next instruction to Supervisor Mode LR
// Address Exception ?
if ( next_interrupt == 3'd4 )
reg_write_sel_nxt = 3'd7; // pc
else
reg_write_sel_nxt = 3'd1; // pc -4
reg_bank_wsel_nxt = 4'd14; // LR
address_sel_nxt = 4'd2; // interrupt_vector
pc_sel_nxt = 2'd2; // interrupt_vector
status_bits_mode_nxt = interrupt_mode; // e.g. Supervisor mode
status_bits_mode_wen_nxt = 1'd1;
// disable normal interrupts
status_bits_irq_mask_nxt = 1'd1;
status_bits_irq_mask_wen_nxt = 1'd1;
// disable fast interrupts
if ( next_interrupt == 3'd2 ) // FIRQ
begin
status_bits_firq_mask_nxt = 1'd1;
status_bits_firq_mask_wen_nxt = 1'd1;
end
end
// previous instruction was either ldr or sdr
// if it is currently executing in the execute stage do the following
if ( control_state == MEM_WAIT1 )
begin
// Save the next instruction to execute later
// Do this even if this instruction does not execute because of Condition
pre_fetch_instruction_wen = 1'd1;
if ( instruction_execute ) // conditional execution state
begin
address_sel_nxt = 4'd3; // pc (not pc + 4)
pc_wen_nxt = 1'd0; // hold current PC value
end
end
// completion of load operation
if ( control_state == MEM_WAIT2 && load_op )
begin
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
barrel_shift_amount_sel_nxt = 2'd3; // shift by address[1:0] x 8
// shift needed
if ( i_execute_address[1:0] != 2'd0 )
barrel_shift_function_nxt = ROR;
// load a byte
if ( itype == TRANS && instruction[22] )
alu_out_sel_nxt = 4'd3; // zero_extend8
if ( !dabt ) // dont load data there is an abort on the data read
begin
// Check if the load destination is the PC
if (instruction[15:12] == 4'd15)
begin
pc_sel_nxt = 2'd1; // alu_out
address_sel_nxt = 4'd1; // alu_out
end
else
reg_bank_wsel_nxt = instruction[15:12];
end
end
// second cycle of multiple load or store
if ( control_state == MTRANS_EXEC1 )
begin
// Save the next instruction to execute later
// Do this even if this instruction does not execute because of Condition
pre_fetch_instruction_wen = 1'd1;
if ( instruction_execute ) // conditional execution state
begin
address_sel_nxt = 4'd5; // o_address
pc_wen_nxt = 1'd0; // hold current PC value
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
// rather than an instruction fetch
if ( !instruction[20] ) // Store
write_data_wen_nxt = 1'd1;
// LDM: load into user mode registers, when in priviledged mode
//if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
//if ( {instruction[22],instruction[20]} == 2'b10 )
if ( {instruction[22:20]} == 3'b100 )
o_user_mode_regs_store_nxt = 1'd1;
end
end
// third cycle of multiple load or store
if ( control_state == MTRANS_EXEC2 )
begin
address_sel_nxt = 4'd5; // o_address
pc_wen_nxt = 1'd0; // hold current PC value
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
// rather than an instruction fetch
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
// Load or Store
if ( instruction[20] ) // Load
begin
// Can never be loading the PC in this state, as the PC is always
// the last register in the set to be loaded
if ( !dabt )
reg_bank_wsel_nxt = mtrans_reg_d2;
end
else // Store
write_data_wen_nxt = 1'd1;
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
// second or fourth cycle of multiple load or store
if ( control_state == MTRANS_EXEC3 && instruction_execute )
begin
address_sel_nxt = 4'd3; // pc (not pc + 4)
pc_wen_nxt = 1'd0; // hold current PC value
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
// Can never be loading the PC in this state, as the PC is always
// the last register in the set to be loaded
if ( instruction[20] && !dabt ) // Load
reg_bank_wsel_nxt = mtrans_reg_d2;
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
//if ( {instruction[22:20]} == 3'b100 )
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
// state is used for LMD/STM of a single register
if ( control_state == MTRANS_EXEC3B && instruction_execute )
begin
// Save the next instruction to execute later
// Do this even if this instruction does not execute because of Condition
pre_fetch_instruction_wen = 1'd1;
address_sel_nxt = 4'd3; // pc (not pc + 4)
pc_wen_nxt = 1'd0; // hold current PC value
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
if ( control_state == MTRANS_EXEC4 )
begin
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
if ( instruction[20] ) // Load
begin
if (!dabt) // dont overwrite registers or status if theres a data abort
begin
if ( mtrans_reg_d2 == 4'd15 ) // load new value into PC
begin
address_sel_nxt = 4'd1; // alu_out - read instructions using new PC value
pc_sel_nxt = 2'd1; // alu_out
pc_wen_nxt = 1'd1; // write PC
// ldm with S bit and pc: the Status bits are updated
// Node this must be done only at the end
// so the register set is the set in the mode before it
// gets changed.
if ( instruction[22] )
begin
status_bits_sel_nxt = 3'd1; // alu out
status_bits_flags_wen_nxt = 1'd1;
// Can't change the mode or mask bits in User mode
if ( i_execute_status_bits[1:0] != USR )
begin
status_bits_mode_wen_nxt = 1'd1;
status_bits_irq_mask_wen_nxt = 1'd1;
status_bits_firq_mask_wen_nxt = 1'd1;
end
end
end
else
begin
reg_bank_wsel_nxt = mtrans_reg_d2;
end
end
end
// we have a data abort interrupt
if ( dabt )
begin
pc_wen_nxt = 1'd0; // hold current PC value
end
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
user_mode_regs_load_nxt = 1'd1;
// SDM: store the user mode registers, when in priviledged mode
if ( {instruction[22],instruction[20]} == 2'b10 )
o_user_mode_regs_store_nxt = 1'd1;
end
// state is for when a data abort interrupt is triggered during an LDM
if ( control_state == MTRANS5_ABORT )
begin
// Restore the Base Address, if the base register is included in the
// list of registers being loaded
if (restore_base_address) // LDM with base address in register list
begin
reg_write_sel_nxt = 3'd6; // write base_register
reg_bank_wsel_nxt = instruction[19:16]; // to Rn
end
end
// Multiply or Multiply-Accumulate
if ( control_state == MULT_PROC1 && instruction_execute )
begin
// Save the next instruction to execute later
// Do this even if this instruction does not execute because of Condition
pre_fetch_instruction_wen = 1'd1;
pc_wen_nxt = 1'd0; // hold current PC value
multiply_function_nxt = o_multiply_function;
end
// Multiply or Multiply-Accumulate
// Do multiplication
// Wait for done or accumulate signal
if ( control_state == MULT_PROC2 )
begin
// Save the next instruction to execute later
// Do this even if this instruction does not execute because of Condition
pc_wen_nxt = 1'd0; // hold current PC value
address_sel_nxt = 4'd3; // pc (not pc + 4)
multiply_function_nxt = o_multiply_function;
end
// Save RdLo
// always last cycle of all multiply or multiply accumulate operations
if ( control_state == MULT_STORE )
begin
reg_write_sel_nxt = 3'd2; // multiply_out
multiply_function_nxt = o_multiply_function;
if ( itype == MULT ) // 32-bit
reg_bank_wsel_nxt = instruction[19:16]; // Rd
else // 64-bit / Long
reg_bank_wsel_nxt = instruction[15:12]; // RdLo
if ( instruction[20] ) // the 'S' bit
begin
status_bits_sel_nxt = 3'd4; // { multiply_flags, status_bits_flags[1:0] }
status_bits_flags_wen_nxt = 1'd1;
end
end
// Add lower 32 bits to multiplication product
if ( control_state == MULT_ACCUMU )
begin
multiply_function_nxt = o_multiply_function;
pc_wen_nxt = 1'd0; // hold current PC value
address_sel_nxt = 4'd3; // pc (not pc + 4)
end
// swp - do write request in 2nd cycle
if ( control_state == SWAP_WRITE && instruction_execute )
begin
barrel_shift_data_sel_nxt = 2'd2; // Shift value from Rm register
address_sel_nxt = 4'd4; // Rn
write_data_wen_nxt = 1'd1;
data_access_exec_nxt = 1'd1; // indicate that its a data read or write,
// rather than an instruction fetch
if ( instruction[22] )
byte_enable_sel_nxt = 2'd1; // Save byte
if ( instruction_execute ) // conditional execution state
pc_wen_nxt = 1'd0; // hold current PC value
// Save the next instruction to execute later
// Do this even if this instruction does not execute because of Condition
pre_fetch_instruction_wen = 1'd1;
end
// swp - receive read response in 3rd cycle
if ( control_state == SWAP_WAIT1 )
begin
barrel_shift_data_sel_nxt = 2'd1; // load word from memory
barrel_shift_amount_sel_nxt = 2'd3; // shift by address[1:0] x 8
// shift needed
if ( i_execute_address[1:0] != 2'd0 )
barrel_shift_function_nxt = ROR;
if ( instruction_execute ) // conditional execution state
begin
address_sel_nxt = 4'd3; // pc (not pc + 4)
pc_wen_nxt = 1'd0; // hold current PC value
end
// load a byte
if ( instruction[22] )
alu_out_sel_nxt = 4'd3; // zero_extend8
if ( !dabt )
begin
// Check is the load destination is the PC
if ( instruction[15:12] == 4'd15 )
begin
pc_sel_nxt = 2'd1; // alu_out
address_sel_nxt = 4'd1; // alu_out
end
else
reg_bank_wsel_nxt = instruction[15:12];
end
end
// 1 cycle delay for Co-Processor Register access
if ( control_state == COPRO_WAIT && instruction_execute )
begin
pre_fetch_instruction_wen = 1'd1;
if ( instruction[20] ) // mrc instruction
begin
// Check is the load destination is the PC
if ( instruction[15:12] == 4'd15 )
begin
// If r15 is specified for <Rd>, the condition code flags are
// updated instead of a general-purpose register.
status_bits_sel_nxt = 3'd3; // i_copro_data
status_bits_flags_wen_nxt = 1'd1;
// Can't change these in USR mode
if ( i_execute_status_bits[1:0] != USR )
begin
status_bits_mode_wen_nxt = 1'd1;
status_bits_irq_mask_wen_nxt = 1'd1;
status_bits_firq_mask_wen_nxt = 1'd1;
end
end
else
reg_bank_wsel_nxt = instruction[15:12];
reg_write_sel_nxt = 3'd5; // i_copro_data
end
else // mcr instruction
begin
copro_operation_nxt = 2'd2; // Register transfer to Co-Processor
end
end
// Have just changed the status_bits mode but this
// creates a 1 cycle gap with the old mode
// coming back from execute into instruction_decode
// So squash that old mode value during this
// cycle of the interrupt transition
if ( control_state == INT_WAIT1 )
status_bits_mode_nxt = status_bits_mode_r; // Supervisor mode
end
// Speed up the long path from u_decode/o_read_data to u_register_bank/r8_firq
// This pre-encodes the firq_s3 signal thats used in u_register_bank
assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ;
// ========================================================
// Next State Logic
// ========================================================
// this replicates the current value of the execute signal in the execute stage
assign instruction_execute = conditional_execute ( condition_r, i_execute_status_bits[31:28] );
assign instruction_valid = (control_state == EXECUTE || control_state == PRE_FETCH_EXEC) ||
// when last instruction was multi-cycle instruction but did not execute
// because condition was false then act like you're in the execute state
(!instruction_execute && (control_state == PC_STALL1 ||
control_state == MEM_WAIT1 ||
control_state == COPRO_WAIT ||
control_state == SWAP_WRITE ||
control_state == MULT_PROC1 ||
control_state == MTRANS_EXEC1 ||
control_state == MTRANS_EXEC3 ||
control_state == MTRANS_EXEC3B ) );
always @*
begin
// default is to hold the current state
control_state_nxt = control_state;
// Note: The order is important here
if ( control_state == RST_WAIT1 ) control_state_nxt = RST_WAIT2;
if ( control_state == RST_WAIT2 ) control_state_nxt = EXECUTE;
if ( control_state == INT_WAIT1 ) control_state_nxt = INT_WAIT2;
if ( control_state == INT_WAIT2 ) control_state_nxt = EXECUTE;
if ( control_state == COPRO_WAIT ) control_state_nxt = PRE_FETCH_EXEC;
if ( control_state == PC_STALL1 ) control_state_nxt = PC_STALL2;
if ( control_state == PC_STALL2 ) control_state_nxt = EXECUTE;
if ( control_state == SWAP_WRITE ) control_state_nxt = SWAP_WAIT1;
if ( control_state == SWAP_WAIT1 ) control_state_nxt = SWAP_WAIT2;
if ( control_state == MULT_STORE ) control_state_nxt = PRE_FETCH_EXEC;
if ( control_state == MTRANS5_ABORT ) control_state_nxt = PRE_FETCH_EXEC;
if ( control_state == MEM_WAIT1 )
control_state_nxt = MEM_WAIT2;
if ( control_state == MEM_WAIT2 ||
control_state == SWAP_WAIT2 )
begin
if ( write_pc ) // writing to the PC!!
control_state_nxt = PC_STALL1;
else
control_state_nxt = PRE_FETCH_EXEC;
end
if ( control_state == MTRANS_EXEC1 )
begin
if (mtrans_instruction_nxt[15:0] != 16'd0)
control_state_nxt = MTRANS_EXEC2;
else // if the register list holds a single register
control_state_nxt = MTRANS_EXEC3;
end
// Stay in State MTRANS_EXEC2 until the full list of registers to
// load or store has been processed
if ( control_state == MTRANS_EXEC2 && mtrans_num_registers == 5'd1 )
control_state_nxt = MTRANS_EXEC3;
if ( control_state == MTRANS_EXEC3 ) control_state_nxt = MTRANS_EXEC4;
if ( control_state == MTRANS_EXEC3B ) control_state_nxt = MTRANS_EXEC4;
if ( control_state == MTRANS_EXEC4 )
begin
if ( dabt ) // data abort
control_state_nxt = MTRANS5_ABORT;
else if (write_pc) // writing to the PC!!
control_state_nxt = PC_STALL1;
else
control_state_nxt = PRE_FETCH_EXEC;
end
if ( control_state == MULT_PROC1 )
begin
if (!instruction_execute)
control_state_nxt = PRE_FETCH_EXEC;
else
control_state_nxt = MULT_PROC2;
end
if ( control_state == MULT_PROC2 )
begin
if ( i_multiply_done )
if ( o_multiply_function[1] ) // Accumulate ?
control_state_nxt = MULT_ACCUMU;
else
control_state_nxt = MULT_STORE;
end
if ( control_state == MULT_ACCUMU )
begin
control_state_nxt = MULT_STORE;
end
// This should come at the end, so that conditional execution works
// correctly
if ( instruction_valid )
begin
// default is to stay in execute state, or to move into this
// state from a conditional execute state
control_state_nxt = EXECUTE;
if ( mem_op ) // load or store word or byte
control_state_nxt = MEM_WAIT1;
if ( write_pc )
control_state_nxt = PC_STALL1;
if ( itype == MTRANS )
begin
if ( mtrans_num_registers != 5'd0 )
begin
// check for LDM/STM of a single register
if ( mtrans_num_registers == 5'd1 )
control_state_nxt = MTRANS_EXEC3B;
else
control_state_nxt = MTRANS_EXEC1;
end
else
control_state_nxt = MTRANS_EXEC3;
end
if ( itype == MULT )
control_state_nxt = MULT_PROC1;
if ( itype == SWAP )
control_state_nxt = SWAP_WRITE;
if ( itype == CORTRANS && !und_request )
control_state_nxt = COPRO_WAIT;
// interrupt overrides everything else so its last
if ( interrupt )
control_state_nxt = INT_WAIT1;
end
end
// ========================================================
// Register Update
// ========================================================
always @ ( posedge i_clk )
if (!i_fetch_stall)
begin
o_read_data <= i_read_data;
o_read_data_alignment <= {i_execute_address[1:0], 3'd0};
abt_address_reg <= i_execute_address;
iabt_reg <= i_iabt;
adex_reg <= i_adex;
abt_status_reg <= i_abt_status;
status_bits_mode_r <= status_bits_mode_nxt;
status_bits_irq_mask_r <= status_bits_irq_mask_nxt;
status_bits_firq_mask_r <= status_bits_firq_mask_nxt;
o_imm32 <= imm32_nxt;
o_imm_shift_amount <= imm_shift_amount_nxt;
o_shift_imm_zero <= shift_imm_zero_nxt;
// when have an interrupt, execute the interrupt operation
// unconditionally in the execute stage
// ensures that status_bits register gets updated correctly
// Likewise when in middle of multi-cycle instructions
// execute them unconditionally
condition_r <= instruction_valid && !interrupt ? condition_nxt : AL;
o_exclusive_exec <= exclusive_exec_nxt;
o_data_access_exec <= data_access_exec_nxt;
o_rm_sel <= o_rm_sel_nxt;
o_rds_sel <= o_rds_sel_nxt;
o_rn_sel <= o_rn_sel_nxt;
o_barrel_shift_amount_sel <= barrel_shift_amount_sel_nxt;
o_barrel_shift_data_sel <= barrel_shift_data_sel_nxt;
o_barrel_shift_function <= barrel_shift_function_nxt;
o_alu_function <= alu_function_nxt;
o_use_carry_in <= use_carry_in_nxt;
o_multiply_function <= multiply_function_nxt;
o_interrupt_vector_sel <= next_interrupt;
address_sel_r <= address_sel_nxt;
pc_sel_r <= pc_sel_nxt;
o_byte_enable_sel <= byte_enable_sel_nxt;
o_status_bits_sel <= status_bits_sel_nxt;
o_reg_write_sel <= reg_write_sel_nxt;
o_user_mode_regs_load <= user_mode_regs_load_nxt;
o_firq_not_user_mode <= firq_not_user_mode_nxt;
o_write_data_wen <= write_data_wen_nxt;
o_base_address_wen <= base_address_wen_nxt;
pc_wen_r <= pc_wen_nxt;
o_reg_bank_wsel <= reg_bank_wsel_nxt;
o_reg_bank_wen <= decode ( reg_bank_wsel_nxt );
o_status_bits_flags_wen <= status_bits_flags_wen_nxt;
o_status_bits_mode_wen <= status_bits_mode_wen_nxt;
o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt;
o_status_bits_firq_mask_wen <= status_bits_firq_mask_wen_nxt;
o_copro_opcode1 <= instruction[23:21];
o_copro_opcode2 <= instruction[7:5];
o_copro_crn <= instruction[19:16];
o_copro_crm <= instruction[3:0];
o_copro_num <= instruction[11:8];
o_copro_operation <= copro_operation_nxt;
o_copro_write_data_wen <= copro_write_data_wen_nxt;
mtrans_r15 <= mtrans_r15_nxt;
restore_base_address <= restore_base_address_nxt;
control_state <= control_state_nxt;
mtrans_reg_d1 <= mtrans_reg;
mtrans_reg_d2 <= mtrans_reg_d1;
end
always @ ( posedge i_clk )
if ( !i_fetch_stall )
begin
// sometimes this is a pre-fetch instruction
// e.g. two ldr instructions in a row. The second ldr will be saved
// to the pre-fetch instruction register
// then when its decoded, a copy is saved to the saved_current_instruction
// register
if (itype == MTRANS)
begin
saved_current_instruction <= mtrans_instruction_nxt;
saved_current_instruction_iabt <= instruction_iabt;
saved_current_instruction_adex <= instruction_adex;
saved_current_instruction_address <= instruction_address;
saved_current_instruction_iabt_status <= instruction_iabt_status;
end
else if (saved_current_instruction_wen)
begin
saved_current_instruction <= instruction;
saved_current_instruction_iabt <= instruction_iabt;
saved_current_instruction_adex <= instruction_adex;
saved_current_instruction_address <= instruction_address;
saved_current_instruction_iabt_status <= instruction_iabt_status;
end
if (pre_fetch_instruction_wen)
begin
pre_fetch_instruction <= o_read_data;
pre_fetch_instruction_iabt <= iabt_reg;
pre_fetch_instruction_adex <= adex_reg;
pre_fetch_instruction_address <= abt_address_reg;
pre_fetch_instruction_iabt_status <= abt_status_reg;
end
end
always @ ( posedge i_clk )
if ( !i_fetch_stall )
begin
irq <= i_irq;
firq <= i_firq;
if ( control_state == INT_WAIT1 && status_bits_mode_r == SVC )
begin
dabt_reg <= 1'd0;
end
else
begin
dabt_reg <= dabt_reg || i_dabt;
end
dabt_reg_d1 <= dabt_reg;
end
assign dabt = dabt_reg || i_dabt;
// ========================================================
// Decompiler for debugging core - not synthesizable
// ========================================================
//synopsys translate_off
`include "debug_functions.vh"
a23_decompile u_decompile (
.i_clk ( i_clk ),
.i_fetch_stall ( i_fetch_stall ),
.i_instruction ( instruction ),
.i_instruction_valid ( instruction_valid ),
.i_instruction_execute ( instruction_execute ),
.i_instruction_address ( instruction_address ),
.i_interrupt ( {3{interrupt}} & next_interrupt ),
.i_interrupt_state ( control_state == INT_WAIT2 ),
.i_instruction_undefined ( und_request ),
.i_pc_sel ( pc_sel_r ),
.i_pc_wen ( pc_wen_r ));
wire [(15*8)-1:0] xCONTROL_STATE;
wire [(15*8)-1:0] xMODE;
assign xCONTROL_STATE =
control_state == RST_WAIT1 ? "RST_WAIT1" :
control_state == RST_WAIT2 ? "RST_WAIT2" :
control_state == INT_WAIT1 ? "INT_WAIT1" :
control_state == INT_WAIT2 ? "INT_WAIT2" :
control_state == EXECUTE ? "EXECUTE" :
control_state == PRE_FETCH_EXEC ? "PRE_FETCH_EXEC" :
control_state == MEM_WAIT1 ? "MEM_WAIT1" :
control_state == MEM_WAIT2 ? "MEM_WAIT2" :
control_state == PC_STALL1 ? "PC_STALL1" :
control_state == PC_STALL2 ? "PC_STALL2" :
control_state == MTRANS_EXEC1 ? "MTRANS_EXEC1" :
control_state == MTRANS_EXEC2 ? "MTRANS_EXEC2" :
control_state == MTRANS_EXEC3 ? "MTRANS_EXEC3" :
control_state == MTRANS_EXEC3B ? "MTRANS_EXEC3B" :
control_state == MTRANS_EXEC4 ? "MTRANS_EXEC4" :
control_state == MTRANS5_ABORT ? "MTRANS5_ABORT" :
control_state == MULT_PROC1 ? "MULT_PROC1" :
control_state == MULT_PROC2 ? "MULT_PROC2" :
control_state == MULT_STORE ? "MULT_STORE" :
control_state == MULT_ACCUMU ? "MULT_ACCUMU" :
control_state == SWAP_WRITE ? "SWAP_WRITE" :
control_state == SWAP_WAIT1 ? "SWAP_WAIT1" :
control_state == SWAP_WAIT2 ? "SWAP_WAIT2" :
control_state == COPRO_WAIT ? "COPRO_WAIT" :
"UNKNOWN " ;
assign xMODE = mode_name ( status_bits_mode_r );
always @( posedge i_clk )
if (control_state == EXECUTE && ((instruction[0] === 1'bx) || (instruction[31] === 1'bx)))
begin
`TB_ERROR_MESSAGE
$display("Instruction with x's =%08h", instruction);
end
//synopsys translate_on
endmodule |
module sky130_fd_sc_ms__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, b, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule |
module Clock
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_100M,
output CLK_50M,
output CLK_25M,
output CLK_10M,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clk2x;
wire clkfx;
wire clkdv;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (10),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("2X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (clk2x),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (clkdv),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk2x));
BUFG clkout1_buf
(.O (CLK_100M),
.I (clk2x));
BUFG clkout2_buf
(.O (CLK_50M),
.I (clk0));
BUFG clkout3_buf
(.O (CLK_25M),
.I (clkdv));
BUFG clkout4_buf
(.O (CLK_10M),
.I (clkfx));
endmodule |
module float_add_sub_altbarrel_shift_02e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [25:0] data;
input [4:0] distance;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [25:0] sbit_piper1d;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [155:0] sbit_w;
wire [4:0] sel_w;
wire [129:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[4]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 26'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[129:104];
assign
dir_w = {dir_pipe[0], dir_w[3:0], direction_w},
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[155:130],
sbit_w = {sbit_piper1d, smux_w[103:0], data},
sel_w = {distance[4:0]},
smux_w = {((({26{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[113:104], pad_w[15:0]}) | ({26{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[129:120]})) | ({26{(~ sel_w[4])}} & sbit_w[129:104])), ((({26{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[95:78], pad_w[7:0]}) | ({26{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[103:86]})) | ({26{(~ sel_w[3])}} & sbit_w[103:78])), ((({26{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[73:52], pad_w[3:0]}) | ({26{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[77:56]})) | ({26{(~ sel_w[2])}} & sbit_w[77:52])), ((({26{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[49:26], pad_w[1:0]}) | ({26{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[51:28]})) | ({26{(~ sel_w[1])}} & sbit_w[51:26])), ((({26{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[24:0], pad_w[0]}) | ({26{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[25:1]})) | ({26{(~ sel_w[0])}} & sbit_w[25:0]))};
endmodule |
module float_add_sub_altbarrel_shift_lib
(
data,
distance,
result) ;
input [25:0] data;
input [4:0] distance;
output [25:0] result;
wire [5:0] dir_w;
wire direction_w;
wire [15:0] pad_w;
wire [155:0] sbit_w;
wire [4:0] sel_w;
wire [129:0] smux_w;
assign
dir_w = {dir_w[4:0], direction_w},
direction_w = 1'b1,
pad_w = {16{1'b0}},
result = sbit_w[155:130],
sbit_w = {smux_w[129:0], data},
sel_w = {distance[4:0]},
smux_w = {((({26{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[113:104], pad_w[15:0]}) | ({26{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[129:120]})) | ({26{(~ sel_w[4])}} & sbit_w[129:104])), ((({26{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[95:78], pad_w[7:0]}) | ({26{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[103:86]})) | ({26{(~ sel_w[3])}} & sbit_w[103:78])), ((({26{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[73:52], pad_w[3:0]}) | ({26{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[77:56]})) | ({26{(~ sel_w[2])}} & sbit_w[77:52])), ((({26{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[49:26], pad_w[1:0]}) | ({26{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[51:28]})) | ({26{(~ sel_w[1])}} & sbit_w[51:26])), ((({26{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[24:0], pad_w[0]}) | ({26{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[25:1]})) | ({26{(~ sel_w[0])}} & sbit_w[25:0]))};
endmodule |
module float_add_sub_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule |
module float_add_sub_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [0:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
float_add_sub_altpriority_encoder_3e8 altpriority_encoder13
(
.data(data[1:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
float_add_sub_altpriority_encoder_3e8 altpriority_encoder14
(
.data(data[3:2]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), ((wire_altpriority_encoder14_zero & wire_altpriority_encoder13_q) | ((~ wire_altpriority_encoder14_zero) & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule |
module float_add_sub_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [1:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
float_add_sub_altpriority_encoder_6e8 altpriority_encoder11
(
.data(data[3:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
float_add_sub_altpriority_encoder_6e8 altpriority_encoder12
(
.data(data[7:4]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({2{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({2{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule |
module float_add_sub_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule |
module float_add_sub_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder17_q;
wire [0:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
float_add_sub_altpriority_encoder_3v7 altpriority_encoder17
(
.data(data[1:0]),
.q(wire_altpriority_encoder17_q));
float_add_sub_altpriority_encoder_3e8 altpriority_encoder18
(
.data(data[3:2]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), ((wire_altpriority_encoder18_zero & wire_altpriority_encoder17_q) | ((~ wire_altpriority_encoder18_zero) & wire_altpriority_encoder18_q))};
endmodule |
module float_add_sub_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder15_q;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
float_add_sub_altpriority_encoder_6v7 altpriority_encoder15
(
.data(data[3:0]),
.q(wire_altpriority_encoder15_q));
float_add_sub_altpriority_encoder_6e8 altpriority_encoder16
(
.data(data[7:4]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), (({2{wire_altpriority_encoder16_zero}} & wire_altpriority_encoder15_q) | ({2{(~ wire_altpriority_encoder16_zero)}} & wire_altpriority_encoder16_q))};
endmodule |
module float_add_sub_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [2:0] wire_altpriority_encoder9_q;
float_add_sub_altpriority_encoder_be8 altpriority_encoder10
(
.data(data[15:8]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
float_add_sub_altpriority_encoder_bv7 altpriority_encoder9
(
.data(data[7:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({3{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({3{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule |
module float_add_sub_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
wire [2:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
float_add_sub_altpriority_encoder_be8 altpriority_encoder19
(
.data(data[7:0]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero));
float_add_sub_altpriority_encoder_be8 altpriority_encoder20
(
.data(data[15:8]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({3{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({3{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))},
zero = (wire_altpriority_encoder19_zero & wire_altpriority_encoder20_zero);
endmodule |
module float_add_sub_altpriority_encoder_qb6
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder7_q;
wire [3:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
float_add_sub_altpriority_encoder_r08 altpriority_encoder7
(
.data(data[15:0]),
.q(wire_altpriority_encoder7_q));
float_add_sub_altpriority_encoder_rf8 altpriority_encoder8
(
.data(data[31:16]),
.q(wire_altpriority_encoder8_q),
.zero(wire_altpriority_encoder8_zero));
assign
q = {(~ wire_altpriority_encoder8_zero), (({4{wire_altpriority_encoder8_zero}} & wire_altpriority_encoder7_q) | ({4{(~ wire_altpriority_encoder8_zero)}} & wire_altpriority_encoder8_q))};
endmodule |
module float_add_sub_altpriority_encoder_nh8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {(~ data[0])},
zero = (~ (data[0] | data[1]));
endmodule |
module float_add_sub_altpriority_encoder_qh8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder27_q;
wire wire_altpriority_encoder27_zero;
wire [0:0] wire_altpriority_encoder28_q;
wire wire_altpriority_encoder28_zero;
float_add_sub_altpriority_encoder_nh8 altpriority_encoder27
(
.data(data[1:0]),
.q(wire_altpriority_encoder27_q),
.zero(wire_altpriority_encoder27_zero));
float_add_sub_altpriority_encoder_nh8 altpriority_encoder28
(
.data(data[3:2]),
.q(wire_altpriority_encoder28_q),
.zero(wire_altpriority_encoder28_zero));
assign
q = {wire_altpriority_encoder27_zero, ((wire_altpriority_encoder27_zero & wire_altpriority_encoder28_q) | ((~ wire_altpriority_encoder27_zero) & wire_altpriority_encoder27_q))},
zero = (wire_altpriority_encoder27_zero & wire_altpriority_encoder28_zero);
endmodule |
module float_add_sub_altpriority_encoder_vh8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
wire [1:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
float_add_sub_altpriority_encoder_qh8 altpriority_encoder25
(
.data(data[3:0]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero));
float_add_sub_altpriority_encoder_qh8 altpriority_encoder26
(
.data(data[7:4]),
.q(wire_altpriority_encoder26_q),
.zero(wire_altpriority_encoder26_zero));
assign
q = {wire_altpriority_encoder25_zero, (({2{wire_altpriority_encoder25_zero}} & wire_altpriority_encoder26_q) | ({2{(~ wire_altpriority_encoder25_zero)}} & wire_altpriority_encoder25_q))},
zero = (wire_altpriority_encoder25_zero & wire_altpriority_encoder26_zero);
endmodule |
module float_add_sub_altpriority_encoder_fj8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
wire [2:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
float_add_sub_altpriority_encoder_vh8 altpriority_encoder23
(
.data(data[7:0]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
float_add_sub_altpriority_encoder_vh8 altpriority_encoder24
(
.data(data[15:8]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero));
assign
q = {wire_altpriority_encoder23_zero, (({3{wire_altpriority_encoder23_zero}} & wire_altpriority_encoder24_q) | ({3{(~ wire_altpriority_encoder23_zero)}} & wire_altpriority_encoder23_q))},
zero = (wire_altpriority_encoder23_zero & wire_altpriority_encoder24_zero);
endmodule |
module float_add_sub_altpriority_encoder_n28
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {(~ data[0])};
endmodule |
module float_add_sub_altpriority_encoder_q28
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder33_q;
wire wire_altpriority_encoder33_zero;
wire [0:0] wire_altpriority_encoder34_q;
float_add_sub_altpriority_encoder_nh8 altpriority_encoder33
(
.data(data[1:0]),
.q(wire_altpriority_encoder33_q),
.zero(wire_altpriority_encoder33_zero));
float_add_sub_altpriority_encoder_n28 altpriority_encoder34
(
.data(data[3:2]),
.q(wire_altpriority_encoder34_q));
assign
q = {wire_altpriority_encoder33_zero, ((wire_altpriority_encoder33_zero & wire_altpriority_encoder34_q) | ((~ wire_altpriority_encoder33_zero) & wire_altpriority_encoder33_q))};
endmodule |
module float_add_sub_altpriority_encoder_v28
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder31_q;
wire wire_altpriority_encoder31_zero;
wire [1:0] wire_altpriority_encoder32_q;
float_add_sub_altpriority_encoder_qh8 altpriority_encoder31
(
.data(data[3:0]),
.q(wire_altpriority_encoder31_q),
.zero(wire_altpriority_encoder31_zero));
float_add_sub_altpriority_encoder_q28 altpriority_encoder32
(
.data(data[7:4]),
.q(wire_altpriority_encoder32_q));
assign
q = {wire_altpriority_encoder31_zero, (({2{wire_altpriority_encoder31_zero}} & wire_altpriority_encoder32_q) | ({2{(~ wire_altpriority_encoder31_zero)}} & wire_altpriority_encoder31_q))};
endmodule |
module float_add_sub_altpriority_encoder_f48
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder29_q;
wire wire_altpriority_encoder29_zero;
wire [2:0] wire_altpriority_encoder30_q;
float_add_sub_altpriority_encoder_vh8 altpriority_encoder29
(
.data(data[7:0]),
.q(wire_altpriority_encoder29_q),
.zero(wire_altpriority_encoder29_zero));
float_add_sub_altpriority_encoder_v28 altpriority_encoder30
(
.data(data[15:8]),
.q(wire_altpriority_encoder30_q));
assign
q = {wire_altpriority_encoder29_zero, (({3{wire_altpriority_encoder29_zero}} & wire_altpriority_encoder30_q) | ({3{(~ wire_altpriority_encoder29_zero)}} & wire_altpriority_encoder29_q))};
endmodule |
module float_add_sub_altpriority_encoder_e48
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder21_q;
wire wire_altpriority_encoder21_zero;
wire [3:0] wire_altpriority_encoder22_q;
float_add_sub_altpriority_encoder_fj8 altpriority_encoder21
(
.data(data[15:0]),
.q(wire_altpriority_encoder21_q),
.zero(wire_altpriority_encoder21_zero));
float_add_sub_altpriority_encoder_f48 altpriority_encoder22
(
.data(data[31:16]),
.q(wire_altpriority_encoder22_q));
assign
q = {wire_altpriority_encoder21_zero, (({4{wire_altpriority_encoder21_zero}} & wire_altpriority_encoder22_q) | ({4{(~ wire_altpriority_encoder21_zero)}} & wire_altpriority_encoder21_q))};
endmodule |
module float_add_sub_altfp_add_sub_2jk
(
clk_en,
clock,
dataa,
datab,
overflow,
result) ;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [25:0] wire_lbarrel_shift_result;
wire [25:0] wire_rbarrel_shift_result;
wire [4:0] wire_leading_zeroes_cnt_q;
wire [4:0] wire_trailing_zeros_cnt_q;
reg both_inputs_are_infinite_dffe1;
reg [7:0] data_exp_dffe1;
reg [25:0] dataa_man_dffe1;
reg dataa_sign_dffe1;
reg [25:0] datab_man_dffe1;
reg datab_sign_dffe1;
reg denormal_res_dffe3;
reg denormal_res_dffe4;
reg [1:0] exp_adj_dffe21;
reg [7:0] exp_out_dffe5;
reg [7:0] exp_res_dffe2;
reg [7:0] exp_res_dffe21;
reg [7:0] exp_res_dffe3;
reg [7:0] exp_res_dffe4;
reg infinite_output_sign_dffe1;
reg infinite_output_sign_dffe2;
reg infinite_output_sign_dffe21;
reg infinite_output_sign_dffe3;
reg infinite_output_sign_dffe31;
reg infinite_output_sign_dffe4;
reg infinite_res_dffe3;
reg infinite_res_dffe4;
reg infinity_magnitude_sub_dffe2;
reg infinity_magnitude_sub_dffe21;
reg infinity_magnitude_sub_dffe3;
reg infinity_magnitude_sub_dffe31;
reg infinity_magnitude_sub_dffe4;
reg input_is_infinite_dffe1;
reg input_is_infinite_dffe2;
reg input_is_infinite_dffe21;
reg input_is_infinite_dffe3;
reg input_is_infinite_dffe31;
reg input_is_infinite_dffe4;
reg input_is_nan_dffe1;
reg input_is_nan_dffe2;
reg input_is_nan_dffe21;
reg input_is_nan_dffe3;
reg input_is_nan_dffe31;
reg input_is_nan_dffe4;
reg [25:0] man_add_sub_res_mag_dffe21;
reg man_add_sub_res_sign_dffe21;
reg [25:0] man_dffe31;
reg [4:0] man_leading_zeros_dffe31;
reg [22:0] man_out_dffe5;
reg [22:0] man_res_dffe4;
reg man_res_is_not_zero_dffe3;
reg man_res_is_not_zero_dffe31;
reg man_res_is_not_zero_dffe4;
reg need_complement_dffe2;
reg overflow_flag_dffe5;
reg round_bit_dffe21;
reg round_bit_dffe3;
reg round_bit_dffe31;
reg rounded_res_infinity_dffe4;
reg sign_dffe31;
reg sign_out_dffe5;
reg sign_res_dffe3;
reg sign_res_dffe4;
reg sticky_bit_dffe1;
reg sticky_bit_dffe2;
reg sticky_bit_dffe21;
reg sticky_bit_dffe3;
reg sticky_bit_dffe31;
reg zero_man_sign_dffe2;
reg zero_man_sign_dffe21;
wire [8:0] wire_add_sub1_result;
wire [8:0] wire_add_sub2_result;
wire [5:0] wire_add_sub3_result;
wire [8:0] wire_add_sub4_result;
wire [8:0] wire_add_sub5_result;
wire [8:0] wire_add_sub6_result;
wire wire_man_2comp_res_lower_cout;
wire [13:0] wire_man_2comp_res_lower_result;
wire [13:0] wire_man_2comp_res_upper0_result;
wire [13:0] wire_man_2comp_res_upper1_result;
wire wire_man_add_sub_lower_cout;
wire [13:0] wire_man_add_sub_lower_result;
wire [13:0] wire_man_add_sub_upper0_result;
wire [13:0] wire_man_add_sub_upper1_result;
wire wire_man_res_rounding_add_sub_lower_cout;
wire [12:0] wire_man_res_rounding_add_sub_lower_result;
wire [12:0] wire_man_res_rounding_add_sub_upper1_result;
wire wire_trailing_zeros_limit_comparator_agb;
wire aclr;
wire add_sub_dffe25_wi;
wire add_sub_dffe25_wo;
wire add_sub_w2;
wire [12:0] adder_upper_w;
wire [8:0] aligned_dataa_exp_dffe12_wi;
wire [8:0] aligned_dataa_exp_dffe12_wo;
wire [8:0] aligned_dataa_exp_dffe13_wi;
wire [8:0] aligned_dataa_exp_dffe13_wo;
wire [8:0] aligned_dataa_exp_dffe14_wi;
wire [8:0] aligned_dataa_exp_dffe14_wo;
wire [8:0] aligned_dataa_exp_dffe15_wi;
wire [8:0] aligned_dataa_exp_dffe15_wo;
wire [8:0] aligned_dataa_exp_w;
wire [23:0] aligned_dataa_man_dffe12_wi;
wire [23:0] aligned_dataa_man_dffe12_wo;
wire [23:0] aligned_dataa_man_dffe13_wi;
wire [23:0] aligned_dataa_man_dffe13_wo;
wire [23:0] aligned_dataa_man_dffe14_wi;
wire [23:0] aligned_dataa_man_dffe14_wo;
wire [25:0] aligned_dataa_man_dffe15_w;
wire [23:0] aligned_dataa_man_dffe15_wi;
wire [23:0] aligned_dataa_man_dffe15_wo;
wire [25:0] aligned_dataa_man_w;
wire aligned_dataa_sign_dffe12_wi;
wire aligned_dataa_sign_dffe12_wo;
wire aligned_dataa_sign_dffe13_wi;
wire aligned_dataa_sign_dffe13_wo;
wire aligned_dataa_sign_dffe14_wi;
wire aligned_dataa_sign_dffe14_wo;
wire aligned_dataa_sign_dffe15_wi;
wire aligned_dataa_sign_dffe15_wo;
wire aligned_dataa_sign_w;
wire [8:0] aligned_datab_exp_dffe12_wi;
wire [8:0] aligned_datab_exp_dffe12_wo;
wire [8:0] aligned_datab_exp_dffe13_wi;
wire [8:0] aligned_datab_exp_dffe13_wo;
wire [8:0] aligned_datab_exp_dffe14_wi;
wire [8:0] aligned_datab_exp_dffe14_wo;
wire [8:0] aligned_datab_exp_dffe15_wi;
wire [8:0] aligned_datab_exp_dffe15_wo;
wire [8:0] aligned_datab_exp_w;
wire [23:0] aligned_datab_man_dffe12_wi;
wire [23:0] aligned_datab_man_dffe12_wo;
wire [23:0] aligned_datab_man_dffe13_wi;
wire [23:0] aligned_datab_man_dffe13_wo;
wire [23:0] aligned_datab_man_dffe14_wi;
wire [23:0] aligned_datab_man_dffe14_wo;
wire [25:0] aligned_datab_man_dffe15_w;
wire [23:0] aligned_datab_man_dffe15_wi;
wire [23:0] aligned_datab_man_dffe15_wo;
wire [25:0] aligned_datab_man_w;
wire aligned_datab_sign_dffe12_wi;
wire aligned_datab_sign_dffe12_wo;
wire aligned_datab_sign_dffe13_wi;
wire aligned_datab_sign_dffe13_wo;
wire aligned_datab_sign_dffe14_wi;
wire aligned_datab_sign_dffe14_wo;
wire aligned_datab_sign_dffe15_wi;
wire aligned_datab_sign_dffe15_wo;
wire aligned_datab_sign_w;
wire borrow_w;
wire both_inputs_are_infinite_dffe1_wi;
wire both_inputs_are_infinite_dffe1_wo;
wire both_inputs_are_infinite_dffe25_wi;
wire both_inputs_are_infinite_dffe25_wo;
wire [7:0] data_exp_dffe1_wi;
wire [7:0] data_exp_dffe1_wo;
wire [31:0] dataa_dffe11_wi;
wire [31:0] dataa_dffe11_wo;
wire [25:0] dataa_man_dffe1_wi;
wire [25:0] dataa_man_dffe1_wo;
wire dataa_sign_dffe1_wi;
wire dataa_sign_dffe1_wo;
wire dataa_sign_dffe25_wi;
wire dataa_sign_dffe25_wo;
wire [31:0] datab_dffe11_wi;
wire [31:0] datab_dffe11_wo;
wire [25:0] datab_man_dffe1_wi;
wire [25:0] datab_man_dffe1_wo;
wire datab_sign_dffe1_wi;
wire datab_sign_dffe1_wo;
wire denormal_flag_w;
wire denormal_res_dffe32_wi;
wire denormal_res_dffe32_wo;
wire denormal_res_dffe33_wi;
wire denormal_res_dffe33_wo;
wire denormal_res_dffe3_wi;
wire denormal_res_dffe3_wo;
wire denormal_res_dffe41_wi;
wire denormal_res_dffe41_wo;
wire denormal_res_dffe42_wi;
wire denormal_res_dffe42_wo;
wire denormal_res_dffe4_wi;
wire denormal_res_dffe4_wo;
wire denormal_result_w;
wire [7:0] exp_a_all_one_w;
wire [7:0] exp_a_not_zero_w;
wire [6:0] exp_adj_0pads;
wire [1:0] exp_adj_dffe21_wi;
wire [1:0] exp_adj_dffe21_wo;
wire [1:0] exp_adj_dffe23_wi;
wire [1:0] exp_adj_dffe23_wo;
wire [1:0] exp_adj_dffe26_wi;
wire [1:0] exp_adj_dffe26_wo;
wire [1:0] exp_adjust_by_add1;
wire [1:0] exp_adjust_by_add2;
wire [8:0] exp_adjustment2_add_sub_dataa_w;
wire [8:0] exp_adjustment2_add_sub_datab_w;
wire [8:0] exp_adjustment2_add_sub_w;
wire [8:0] exp_adjustment_add_sub_dataa_w;
wire [8:0] exp_adjustment_add_sub_datab_w;
wire [8:0] exp_adjustment_add_sub_w;
wire [7:0] exp_all_ones_w;
wire [7:0] exp_all_zeros_w;
wire exp_amb_mux_dffe13_wi;
wire exp_amb_mux_dffe13_wo;
wire exp_amb_mux_dffe14_wi;
wire exp_amb_mux_dffe14_wo;
wire exp_amb_mux_dffe15_wi;
wire exp_amb_mux_dffe15_wo;
wire exp_amb_mux_w;
wire [8:0] exp_amb_w;
wire [7:0] exp_b_all_one_w;
wire [7:0] exp_b_not_zero_w;
wire [8:0] exp_bma_w;
wire [2:0] exp_diff_abs_exceed_max_w;
wire [4:0] exp_diff_abs_max_w;
wire [7:0] exp_diff_abs_w;
wire [7:0] exp_intermediate_res_dffe41_wi;
wire [7:0] exp_intermediate_res_dffe41_wo;
wire [7:0] exp_intermediate_res_dffe42_wi;
wire [7:0] exp_intermediate_res_dffe42_wo;
wire [7:0] exp_intermediate_res_w;
wire [7:0] exp_out_dffe5_wi;
wire [7:0] exp_out_dffe5_wo;
wire [7:0] exp_res_dffe21_wi;
wire [7:0] exp_res_dffe21_wo;
wire [7:0] exp_res_dffe22_wi;
wire [7:0] exp_res_dffe22_wo;
wire [7:0] exp_res_dffe23_wi;
wire [7:0] exp_res_dffe23_wo;
wire [7:0] exp_res_dffe25_wi;
wire [7:0] exp_res_dffe25_wo;
wire [7:0] exp_res_dffe26_wi;
wire [7:0] exp_res_dffe26_wo;
wire [7:0] exp_res_dffe27_wi;
wire [7:0] exp_res_dffe27_wo;
wire [7:0] exp_res_dffe2_wi;
wire [7:0] exp_res_dffe2_wo;
wire [7:0] exp_res_dffe32_wi;
wire [7:0] exp_res_dffe32_wo;
wire [7:0] exp_res_dffe33_wi;
wire [7:0] exp_res_dffe33_wo;
wire [7:0] exp_res_dffe3_wi;
wire [7:0] exp_res_dffe3_wo;
wire [7:0] exp_res_dffe4_wi;
wire [7:0] exp_res_dffe4_wo;
wire [7:0] exp_res_max_w;
wire [8:0] exp_res_not_zero_w;
wire [8:0] exp_res_rounding_adder_dataa_w;
wire [8:0] exp_res_rounding_adder_w;
wire exp_rounded_res_infinity_w;
wire [7:0] exp_rounded_res_max_w;
wire [7:0] exp_rounded_res_w;
wire [8:0] exp_rounding_adjustment_w;
wire [8:0] exp_value;
wire force_infinity_w;
wire force_nan_w;
wire force_zero_w;
wire guard_bit_dffe3_wo;
wire infinite_output_sign_dffe1_wi;
wire infinite_output_sign_dffe1_wo;
wire infinite_output_sign_dffe21_wi;
wire infinite_output_sign_dffe21_wo;
wire infinite_output_sign_dffe22_wi;
wire infinite_output_sign_dffe22_wo;
wire infinite_output_sign_dffe23_wi;
wire infinite_output_sign_dffe23_wo;
wire infinite_output_sign_dffe25_wi;
wire infinite_output_sign_dffe25_wo;
wire infinite_output_sign_dffe26_wi;
wire infinite_output_sign_dffe26_wo;
wire infinite_output_sign_dffe27_wi;
wire infinite_output_sign_dffe27_wo;
wire infinite_output_sign_dffe2_wi;
wire infinite_output_sign_dffe2_wo;
wire infinite_output_sign_dffe31_wi;
wire infinite_output_sign_dffe31_wo;
wire infinite_output_sign_dffe32_wi;
wire infinite_output_sign_dffe32_wo;
wire infinite_output_sign_dffe33_wi;
wire infinite_output_sign_dffe33_wo;
wire infinite_output_sign_dffe3_wi;
wire infinite_output_sign_dffe3_wo;
wire infinite_output_sign_dffe41_wi;
wire infinite_output_sign_dffe41_wo;
wire infinite_output_sign_dffe42_wi;
wire infinite_output_sign_dffe42_wo;
wire infinite_output_sign_dffe4_wi;
wire infinite_output_sign_dffe4_wo;
wire infinite_res_dff32_wi;
wire infinite_res_dff32_wo;
wire infinite_res_dff33_wi;
wire infinite_res_dff33_wo;
wire infinite_res_dffe3_wi;
wire infinite_res_dffe3_wo;
wire infinite_res_dffe41_wi;
wire infinite_res_dffe41_wo;
wire infinite_res_dffe42_wi;
wire infinite_res_dffe42_wo;
wire infinite_res_dffe4_wi;
wire infinite_res_dffe4_wo;
wire infinity_magnitude_sub_dffe21_wi;
wire infinity_magnitude_sub_dffe21_wo;
wire infinity_magnitude_sub_dffe22_wi;
wire infinity_magnitude_sub_dffe22_wo;
wire infinity_magnitude_sub_dffe23_wi;
wire infinity_magnitude_sub_dffe23_wo;
wire infinity_magnitude_sub_dffe26_wi;
wire infinity_magnitude_sub_dffe26_wo;
wire infinity_magnitude_sub_dffe27_wi;
wire infinity_magnitude_sub_dffe27_wo;
wire infinity_magnitude_sub_dffe2_wi;
wire infinity_magnitude_sub_dffe2_wo;
wire infinity_magnitude_sub_dffe31_wi;
wire infinity_magnitude_sub_dffe31_wo;
wire infinity_magnitude_sub_dffe32_wi;
wire infinity_magnitude_sub_dffe32_wo;
wire infinity_magnitude_sub_dffe33_wi;
wire infinity_magnitude_sub_dffe33_wo;
wire infinity_magnitude_sub_dffe3_wi;
wire infinity_magnitude_sub_dffe3_wo;
wire infinity_magnitude_sub_dffe41_wi;
wire infinity_magnitude_sub_dffe41_wo;
wire infinity_magnitude_sub_dffe42_wi;
wire infinity_magnitude_sub_dffe42_wo;
wire infinity_magnitude_sub_dffe4_wi;
wire infinity_magnitude_sub_dffe4_wo;
wire input_dataa_denormal_dffe11_wi;
wire input_dataa_denormal_dffe11_wo;
wire input_dataa_denormal_w;
wire input_dataa_infinite_dffe11_wi;
wire input_dataa_infinite_dffe11_wo;
wire input_dataa_infinite_dffe12_wi;
wire input_dataa_infinite_dffe12_wo;
wire input_dataa_infinite_dffe13_wi;
wire input_dataa_infinite_dffe13_wo;
wire input_dataa_infinite_dffe14_wi;
wire input_dataa_infinite_dffe14_wo;
wire input_dataa_infinite_dffe15_wi;
wire input_dataa_infinite_dffe15_wo;
wire input_dataa_infinite_w;
wire input_dataa_nan_dffe11_wi;
wire input_dataa_nan_dffe11_wo;
wire input_dataa_nan_dffe12_wi;
wire input_dataa_nan_dffe12_wo;
wire input_dataa_nan_w;
wire input_dataa_zero_dffe11_wi;
wire input_dataa_zero_dffe11_wo;
wire input_dataa_zero_w;
wire input_datab_denormal_dffe11_wi;
wire input_datab_denormal_dffe11_wo;
wire input_datab_denormal_w;
wire input_datab_infinite_dffe11_wi;
wire input_datab_infinite_dffe11_wo;
wire input_datab_infinite_dffe12_wi;
wire input_datab_infinite_dffe12_wo;
wire input_datab_infinite_dffe13_wi;
wire input_datab_infinite_dffe13_wo;
wire input_datab_infinite_dffe14_wi;
wire input_datab_infinite_dffe14_wo;
wire input_datab_infinite_dffe15_wi;
wire input_datab_infinite_dffe15_wo;
wire input_datab_infinite_w;
wire input_datab_nan_dffe11_wi;
wire input_datab_nan_dffe11_wo;
wire input_datab_nan_dffe12_wi;
wire input_datab_nan_dffe12_wo;
wire input_datab_nan_w;
wire input_datab_zero_dffe11_wi;
wire input_datab_zero_dffe11_wo;
wire input_datab_zero_w;
wire input_is_infinite_dffe1_wi;
wire input_is_infinite_dffe1_wo;
wire input_is_infinite_dffe21_wi;
wire input_is_infinite_dffe21_wo;
wire input_is_infinite_dffe22_wi;
wire input_is_infinite_dffe22_wo;
wire input_is_infinite_dffe23_wi;
wire input_is_infinite_dffe23_wo;
wire input_is_infinite_dffe25_wi;
wire input_is_infinite_dffe25_wo;
wire input_is_infinite_dffe26_wi;
wire input_is_infinite_dffe26_wo;
wire input_is_infinite_dffe27_wi;
wire input_is_infinite_dffe27_wo;
wire input_is_infinite_dffe2_wi;
wire input_is_infinite_dffe2_wo;
wire input_is_infinite_dffe31_wi;
wire input_is_infinite_dffe31_wo;
wire input_is_infinite_dffe32_wi;
wire input_is_infinite_dffe32_wo;
wire input_is_infinite_dffe33_wi;
wire input_is_infinite_dffe33_wo;
wire input_is_infinite_dffe3_wi;
wire input_is_infinite_dffe3_wo;
wire input_is_infinite_dffe41_wi;
wire input_is_infinite_dffe41_wo;
wire input_is_infinite_dffe42_wi;
wire input_is_infinite_dffe42_wo;
wire input_is_infinite_dffe4_wi;
wire input_is_infinite_dffe4_wo;
wire input_is_nan_dffe13_wi;
wire input_is_nan_dffe13_wo;
wire input_is_nan_dffe14_wi;
wire input_is_nan_dffe14_wo;
wire input_is_nan_dffe15_wi;
wire input_is_nan_dffe15_wo;
wire input_is_nan_dffe1_wi;
wire input_is_nan_dffe1_wo;
wire input_is_nan_dffe21_wi;
wire input_is_nan_dffe21_wo;
wire input_is_nan_dffe22_wi;
wire input_is_nan_dffe22_wo;
wire input_is_nan_dffe23_wi;
wire input_is_nan_dffe23_wo;
wire input_is_nan_dffe25_wi;
wire input_is_nan_dffe25_wo;
wire input_is_nan_dffe26_wi;
wire input_is_nan_dffe26_wo;
wire input_is_nan_dffe27_wi;
wire input_is_nan_dffe27_wo;
wire input_is_nan_dffe2_wi;
wire input_is_nan_dffe2_wo;
wire input_is_nan_dffe31_wi;
wire input_is_nan_dffe31_wo;
wire input_is_nan_dffe32_wi;
wire input_is_nan_dffe32_wo;
wire input_is_nan_dffe33_wi;
wire input_is_nan_dffe33_wo;
wire input_is_nan_dffe3_wi;
wire input_is_nan_dffe3_wo;
wire input_is_nan_dffe41_wi;
wire input_is_nan_dffe41_wo;
wire input_is_nan_dffe42_wi;
wire input_is_nan_dffe42_wo;
wire input_is_nan_dffe4_wi;
wire input_is_nan_dffe4_wo;
wire [27:0] man_2comp_res_dataa_w;
wire [27:0] man_2comp_res_datab_w;
wire [27:0] man_2comp_res_w;
wire [22:0] man_a_not_zero_w;
wire [27:0] man_add_sub_dataa_w;
wire [27:0] man_add_sub_datab_w;
wire [25:0] man_add_sub_res_mag_dffe21_wi;
wire [25:0] man_add_sub_res_mag_dffe21_wo;
wire [25:0] man_add_sub_res_mag_dffe23_wi;
wire [25:0] man_add_sub_res_mag_dffe23_wo;
wire [25:0] man_add_sub_res_mag_dffe26_wi;
wire [25:0] man_add_sub_res_mag_dffe26_wo;
wire [27:0] man_add_sub_res_mag_dffe27_wi;
wire [27:0] man_add_sub_res_mag_dffe27_wo;
wire [27:0] man_add_sub_res_mag_w2;
wire man_add_sub_res_sign_dffe21_wo;
wire man_add_sub_res_sign_dffe23_wi;
wire man_add_sub_res_sign_dffe23_wo;
wire man_add_sub_res_sign_dffe26_wi;
wire man_add_sub_res_sign_dffe26_wo;
wire man_add_sub_res_sign_dffe27_wi;
wire man_add_sub_res_sign_dffe27_wo;
wire man_add_sub_res_sign_w2;
wire [27:0] man_add_sub_w;
wire [22:0] man_all_zeros_w;
wire [22:0] man_b_not_zero_w;
wire [25:0] man_dffe31_wo;
wire [25:0] man_intermediate_res_w;
wire [4:0] man_leading_zeros_cnt_w;
wire [4:0] man_leading_zeros_dffe31_wi;
wire [4:0] man_leading_zeros_dffe31_wo;
wire [22:0] man_nan_w;
wire [22:0] man_out_dffe5_wi;
wire [22:0] man_out_dffe5_wo;
wire [22:0] man_res_dffe4_wi;
wire [22:0] man_res_dffe4_wo;
wire man_res_is_not_zero_dffe31_wi;
wire man_res_is_not_zero_dffe31_wo;
wire man_res_is_not_zero_dffe32_wi;
wire man_res_is_not_zero_dffe32_wo;
wire man_res_is_not_zero_dffe33_wi;
wire man_res_is_not_zero_dffe33_wo;
wire man_res_is_not_zero_dffe3_wi;
wire man_res_is_not_zero_dffe3_wo;
wire man_res_is_not_zero_dffe41_wi;
wire man_res_is_not_zero_dffe41_wo;
wire man_res_is_not_zero_dffe42_wi;
wire man_res_is_not_zero_dffe42_wo;
wire man_res_is_not_zero_dffe4_wi;
wire man_res_is_not_zero_dffe4_wo;
wire [25:0] man_res_mag_w2;
wire man_res_not_zero_dffe23_wi;
wire man_res_not_zero_dffe23_wo;
wire man_res_not_zero_dffe26_wi;
wire man_res_not_zero_dffe26_wo;
wire [24:0] man_res_not_zero_w2;
wire [25:0] man_res_rounding_add_sub_datab_w;
wire [25:0] man_res_rounding_add_sub_w;
wire [23:0] man_res_w3;
wire [22:0] man_rounded_res_w;
wire man_rounding_add_value_w;
wire [23:0] man_smaller_dffe13_wi;
wire [23:0] man_smaller_dffe13_wo;
wire [23:0] man_smaller_w;
wire need_complement_dffe22_wi;
wire need_complement_dffe22_wo;
wire need_complement_dffe2_wi;
wire need_complement_dffe2_wo;
wire overflow_flag_dffe5_wi;
wire overflow_flag_dffe5_wo;
wire overflow_flag_w;
wire [1:0] pos_sign_bit_ext;
wire [3:0] priority_encoder_1pads_w;
wire round_bit_dffe21_wi;
wire round_bit_dffe21_wo;
wire round_bit_dffe23_wi;
wire round_bit_dffe23_wo;
wire round_bit_dffe26_wi;
wire round_bit_dffe26_wo;
wire round_bit_dffe31_wi;
wire round_bit_dffe31_wo;
wire round_bit_dffe32_wi;
wire round_bit_dffe32_wo;
wire round_bit_dffe33_wi;
wire round_bit_dffe33_wo;
wire round_bit_dffe3_wi;
wire round_bit_dffe3_wo;
wire round_bit_w;
wire rounded_res_infinity_dffe4_wi;
wire rounded_res_infinity_dffe4_wo;
wire [4:0] rshift_distance_dffe13_wi;
wire [4:0] rshift_distance_dffe13_wo;
wire [4:0] rshift_distance_dffe14_wi;
wire [4:0] rshift_distance_dffe14_wo;
wire [4:0] rshift_distance_dffe15_wi;
wire [4:0] rshift_distance_dffe15_wo;
wire [4:0] rshift_distance_w;
wire sign_dffe31_wi;
wire sign_dffe31_wo;
wire sign_dffe32_wi;
wire sign_dffe32_wo;
wire sign_dffe33_wi;
wire sign_dffe33_wo;
wire sign_out_dffe5_wi;
wire sign_out_dffe5_wo;
wire sign_res_dffe3_wi;
wire sign_res_dffe3_wo;
wire sign_res_dffe41_wi;
wire sign_res_dffe41_wo;
wire sign_res_dffe42_wi;
wire sign_res_dffe42_wo;
wire sign_res_dffe4_wi;
wire sign_res_dffe4_wo;
wire [5:0] sticky_bit_cnt_dataa_w;
wire [5:0] sticky_bit_cnt_datab_w;
wire [5:0] sticky_bit_cnt_res_w;
wire sticky_bit_dffe1_wi;
wire sticky_bit_dffe1_wo;
wire sticky_bit_dffe21_wi;
wire sticky_bit_dffe21_wo;
wire sticky_bit_dffe22_wi;
wire sticky_bit_dffe22_wo;
wire sticky_bit_dffe23_wi;
wire sticky_bit_dffe23_wo;
wire sticky_bit_dffe25_wi;
wire sticky_bit_dffe25_wo;
wire sticky_bit_dffe26_wi;
wire sticky_bit_dffe26_wo;
wire sticky_bit_dffe27_wi;
wire sticky_bit_dffe27_wo;
wire sticky_bit_dffe2_wi;
wire sticky_bit_dffe2_wo;
wire sticky_bit_dffe31_wi;
wire sticky_bit_dffe31_wo;
wire sticky_bit_dffe32_wi;
wire sticky_bit_dffe32_wo;
wire sticky_bit_dffe33_wi;
wire sticky_bit_dffe33_wo;
wire sticky_bit_dffe3_wi;
wire sticky_bit_dffe3_wo;
wire sticky_bit_w;
wire [5:0] trailing_zeros_limit_w;
wire zero_man_sign_dffe21_wi;
wire zero_man_sign_dffe21_wo;
wire zero_man_sign_dffe22_wi;
wire zero_man_sign_dffe22_wo;
wire zero_man_sign_dffe23_wi;
wire zero_man_sign_dffe23_wo;
wire zero_man_sign_dffe26_wi;
wire zero_man_sign_dffe26_wo;
wire zero_man_sign_dffe27_wi;
wire zero_man_sign_dffe27_wo;
wire zero_man_sign_dffe2_wi;
wire zero_man_sign_dffe2_wo;
float_add_sub_altbarrel_shift_02e lbarrel_shift
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data(man_dffe31_wo),
.distance(man_leading_zeros_cnt_w),
.result(wire_lbarrel_shift_result));
float_add_sub_altbarrel_shift_lib rbarrel_shift
(
.data({man_smaller_dffe13_wo, {2{1'b0}}}),
.distance(rshift_distance_dffe13_wo),
.result(wire_rbarrel_shift_result));
float_add_sub_altpriority_encoder_qb6 leading_zeroes_cnt
(
.data({man_add_sub_res_mag_dffe21_wo[25:1], 1'b1, {6{1'b0}}}),
.q(wire_leading_zeroes_cnt_q));
float_add_sub_altpriority_encoder_e48 trailing_zeros_cnt
(
.data({{9{1'b1}}, man_smaller_dffe13_wo[22:0]}),
.q(wire_trailing_zeros_cnt_q));
// synopsys translate_off
initial
both_inputs_are_infinite_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_inputs_are_infinite_dffe1 <= 1'b0;
else if (clk_en == 1'b1) both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
// synopsys translate_off
initial
data_exp_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) data_exp_dffe1 <= 8'b0;
else if (clk_en == 1'b1) data_exp_dffe1 <= data_exp_dffe1_wi;
// synopsys translate_off
initial
dataa_man_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_dffe1 <= 26'b0;
else if (clk_en == 1'b1) dataa_man_dffe1 <= dataa_man_dffe1_wi;
// synopsys translate_off
initial
dataa_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
// synopsys translate_off
initial
datab_man_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_dffe1 <= 26'b0;
else if (clk_en == 1'b1) datab_man_dffe1 <= datab_man_dffe1_wi;
// synopsys translate_off
initial
datab_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) datab_sign_dffe1 <= datab_sign_dffe1_wi;
// synopsys translate_off
initial
denormal_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) denormal_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) denormal_res_dffe3 <= denormal_res_dffe3_wi;
// synopsys translate_off
initial
denormal_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) denormal_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) denormal_res_dffe4 <= denormal_res_dffe4_wi;
// synopsys translate_off
initial
exp_adj_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_adj_dffe21 <= 2'b0;
else if (clk_en == 1'b1) exp_adj_dffe21 <= exp_adj_dffe21_wi;
// synopsys translate_off
initial
exp_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_out_dffe5 <= 8'b0;
else if (clk_en == 1'b1) exp_out_dffe5 <= exp_out_dffe5_wi;
// synopsys translate_off
initial
exp_res_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe2 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe2 <= exp_res_dffe2_wi;
// synopsys translate_off
initial
exp_res_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe21 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe21 <= exp_res_dffe21_wi;
// synopsys translate_off
initial
exp_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe3 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe3 <= exp_res_dffe3_wi;
// synopsys translate_off
initial
exp_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_res_dffe4 <= 8'b0;
else if (clk_en == 1'b1) exp_res_dffe4 <= exp_res_dffe4_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe31 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
// synopsys translate_off
initial
infinite_output_sign_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_output_sign_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
// synopsys translate_off
initial
infinite_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinite_res_dffe3 <= infinite_res_dffe3_wi;
// synopsys translate_off
initial
infinite_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinite_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinite_res_dffe4 <= infinite_res_dffe4_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe2 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe21 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe3 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe31 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
// synopsys translate_off
initial
infinity_magnitude_sub_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_magnitude_sub_dffe4 <= 1'b0;
else if (clk_en == 1'b1) infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
// synopsys translate_off
initial
input_is_infinite_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
// synopsys translate_off
initial
input_is_infinite_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
// synopsys translate_off
initial
input_is_infinite_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe21 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
// synopsys translate_off
initial
input_is_infinite_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
// synopsys translate_off
initial
input_is_infinite_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe31 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
// synopsys translate_off
initial
input_is_infinite_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinite_dffe4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
// synopsys translate_off
initial
input_is_nan_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
// synopsys translate_off
initial
input_is_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
// synopsys translate_off
initial
input_is_nan_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe21 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
// synopsys translate_off
initial
input_is_nan_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
// synopsys translate_off
initial
input_is_nan_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe31 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
// synopsys translate_off
initial
input_is_nan_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
// synopsys translate_off
initial
man_add_sub_res_mag_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_mag_dffe21 <= 26'b0;
else if (clk_en == 1'b1) man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
// synopsys translate_off
initial
man_add_sub_res_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_add_sub_res_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
// synopsys translate_off
initial
man_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_dffe31 <= 26'b0;
else if (clk_en == 1'b1) man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
// synopsys translate_off
initial
man_leading_zeros_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_leading_zeros_dffe31 <= 5'b0;
else if (clk_en == 1'b1) man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
// synopsys translate_off
initial
man_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_out_dffe5 <= 23'b0;
else if (clk_en == 1'b1) man_out_dffe5 <= man_out_dffe5_wi;
// synopsys translate_off
initial
man_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_dffe4 <= 23'b0;
else if (clk_en == 1'b1) man_res_dffe4 <= man_res_dffe4_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe3 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe31 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
// synopsys translate_off
initial
man_res_is_not_zero_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_res_is_not_zero_dffe4 <= 1'b0;
else if (clk_en == 1'b1) man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
// synopsys translate_off
initial
need_complement_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) need_complement_dffe2 <= 1'b0;
else if (clk_en == 1'b1) need_complement_dffe2 <= need_complement_dffe2_wi;
// synopsys translate_off
initial
overflow_flag_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) overflow_flag_dffe5 <= 1'b0;
else if (clk_en == 1'b1) overflow_flag_dffe5 <= overflow_flag_dffe5_wi;
// synopsys translate_off
initial
round_bit_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe21 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe21 <= round_bit_dffe21_wi;
// synopsys translate_off
initial
round_bit_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe3 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe3 <= round_bit_dffe3_wi;
// synopsys translate_off
initial
round_bit_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_bit_dffe31 <= 1'b0;
else if (clk_en == 1'b1) round_bit_dffe31 <= round_bit_dffe31_wi;
// synopsys translate_off
initial
rounded_res_infinity_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rounded_res_infinity_dffe4 <= 1'b0;
else if (clk_en == 1'b1) rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
// synopsys translate_off
initial
sign_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe31 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe31 <= sign_dffe31_wi;
// synopsys translate_off
initial
sign_out_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_out_dffe5 <= 1'b0;
else if (clk_en == 1'b1) sign_out_dffe5 <= sign_out_dffe5_wi;
// synopsys translate_off
initial
sign_res_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_res_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sign_res_dffe3 <= sign_res_dffe3_wi;
// synopsys translate_off
initial
sign_res_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_res_dffe4 <= 1'b0;
else if (clk_en == 1'b1) sign_res_dffe4 <= sign_res_dffe4_wi;
// synopsys translate_off
initial
sticky_bit_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe1 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
// synopsys translate_off
initial
sticky_bit_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe2 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
// synopsys translate_off
initial
sticky_bit_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe21 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
// synopsys translate_off
initial
sticky_bit_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
// synopsys translate_off
initial
sticky_bit_dffe31 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_bit_dffe31 <= 1'b0;
else if (clk_en == 1'b1) sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
// synopsys translate_off
initial
zero_man_sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_man_sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
// synopsys translate_off
initial
zero_man_sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_man_sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
lpm_add_sub add_sub1
(
.cout(),
.dataa(aligned_dataa_exp_w),
.datab(aligned_datab_exp_w),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "SUB",
add_sub1.lpm_representation = "SIGNED",
add_sub1.lpm_width = 9,
add_sub1.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub2
(
.cout(),
.dataa(aligned_datab_exp_w),
.datab(aligned_dataa_exp_w),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "SUB",
add_sub2.lpm_representation = "SIGNED",
add_sub2.lpm_width = 9,
add_sub2.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub3
(
.cout(),
.dataa(sticky_bit_cnt_dataa_w),
.datab(sticky_bit_cnt_datab_w),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_representation = "SIGNED",
add_sub3.lpm_width = 6,
add_sub3.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub4
(
.cout(),
.dataa(exp_adjustment_add_sub_dataa_w),
.datab(exp_adjustment_add_sub_datab_w),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "ADD",
add_sub4.lpm_representation = "SIGNED",
add_sub4.lpm_width = 9,
add_sub4.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(exp_adjustment2_add_sub_dataa_w),
.datab(exp_adjustment2_add_sub_datab_w),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "ADD",
add_sub5.lpm_pipeline = 1,
add_sub5.lpm_representation = "SIGNED",
add_sub5.lpm_width = 9,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cout(),
.dataa(exp_res_rounding_adder_dataa_w),
.datab(exp_rounding_adjustment_w),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_representation = "SIGNED",
add_sub6.lpm_width = 9,
add_sub6.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_lower
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(borrow_w),
.clken(clk_en),
.clock(clock),
.cout(wire_man_2comp_res_lower_cout),
.dataa(man_2comp_res_dataa_w[13:0]),
.datab(man_2comp_res_datab_w[13:0]),
.overflow(),
.result(wire_man_2comp_res_lower_result));
defparam
man_2comp_res_lower.lpm_pipeline = 1,
man_2comp_res_lower.lpm_representation = "SIGNED",
man_2comp_res_lower.lpm_width = 14,
man_2comp_res_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_upper0
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_2comp_res_dataa_w[27:14]),
.datab(man_2comp_res_datab_w[27:14]),
.overflow(),
.result(wire_man_2comp_res_upper0_result));
defparam
man_2comp_res_upper0.lpm_pipeline = 1,
man_2comp_res_upper0.lpm_representation = "SIGNED",
man_2comp_res_upper0.lpm_width = 14,
man_2comp_res_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub man_2comp_res_upper1
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b1),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_2comp_res_dataa_w[27:14]),
.datab(man_2comp_res_datab_w[27:14]),
.overflow(),
.result(wire_man_2comp_res_upper1_result));
defparam
man_2comp_res_upper1.lpm_pipeline = 1,
man_2comp_res_upper1.lpm_representation = "SIGNED",
man_2comp_res_upper1.lpm_width = 14,
man_2comp_res_upper1.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_lower
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(borrow_w),
.clken(clk_en),
.clock(clock),
.cout(wire_man_add_sub_lower_cout),
.dataa(man_add_sub_dataa_w[13:0]),
.datab(man_add_sub_datab_w[13:0]),
.overflow(),
.result(wire_man_add_sub_lower_result));
defparam
man_add_sub_lower.lpm_pipeline = 1,
man_add_sub_lower.lpm_representation = "SIGNED",
man_add_sub_lower.lpm_width = 14,
man_add_sub_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_upper0
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_add_sub_dataa_w[27:14]),
.datab(man_add_sub_datab_w[27:14]),
.overflow(),
.result(wire_man_add_sub_upper0_result));
defparam
man_add_sub_upper0.lpm_pipeline = 1,
man_add_sub_upper0.lpm_representation = "SIGNED",
man_add_sub_upper0.lpm_width = 14,
man_add_sub_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub man_add_sub_upper1
(
.aclr(aclr),
.add_sub(add_sub_w2),
.cin(1'b1),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(man_add_sub_dataa_w[27:14]),
.datab(man_add_sub_datab_w[27:14]),
.overflow(),
.result(wire_man_add_sub_upper1_result));
defparam
man_add_sub_upper1.lpm_pipeline = 1,
man_add_sub_upper1.lpm_representation = "SIGNED",
man_add_sub_upper1.lpm_width = 14,
man_add_sub_upper1.lpm_type = "lpm_add_sub";
lpm_add_sub man_res_rounding_add_sub_lower
(
.cout(wire_man_res_rounding_add_sub_lower_cout),
.dataa(man_intermediate_res_w[12:0]),
.datab(man_res_rounding_add_sub_datab_w[12:0]),
.overflow(),
.result(wire_man_res_rounding_add_sub_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_res_rounding_add_sub_lower.lpm_direction = "ADD",
man_res_rounding_add_sub_lower.lpm_representation = "SIGNED",
man_res_rounding_add_sub_lower.lpm_width = 13,
man_res_rounding_add_sub_lower.lpm_type = "lpm_add_sub";
lpm_add_sub man_res_rounding_add_sub_upper1
(
.cin(1'b1),
.cout(),
.dataa(man_intermediate_res_w[25:13]),
.datab(man_res_rounding_add_sub_datab_w[25:13]),
.overflow(),
.result(wire_man_res_rounding_add_sub_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_res_rounding_add_sub_upper1.lpm_direction = "ADD",
man_res_rounding_add_sub_upper1.lpm_representation = "SIGNED",
man_res_rounding_add_sub_upper1.lpm_width = 13,
man_res_rounding_add_sub_upper1.lpm_type = "lpm_add_sub";
lpm_compare trailing_zeros_limit_comparator
(
.aeb(),
.agb(wire_trailing_zeros_limit_comparator_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(sticky_bit_cnt_res_w),
.datab(trailing_zeros_limit_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
trailing_zeros_limit_comparator.lpm_representation = "SIGNED",
trailing_zeros_limit_comparator.lpm_width = 6,
trailing_zeros_limit_comparator.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
add_sub_dffe25_wi = add_sub_w2,
add_sub_dffe25_wo = add_sub_dffe25_wi,
add_sub_w2 = (~ (dataa_sign_dffe1_wo ^ datab_sign_dffe1_wo)),
adder_upper_w = man_intermediate_res_w[25:13],
aligned_dataa_exp_dffe12_wi = aligned_dataa_exp_w,
aligned_dataa_exp_dffe12_wo = aligned_dataa_exp_dffe12_wi,
aligned_dataa_exp_dffe13_wi = aligned_dataa_exp_dffe12_wo,
aligned_dataa_exp_dffe13_wo = aligned_dataa_exp_dffe13_wi,
aligned_dataa_exp_dffe14_wi = aligned_dataa_exp_dffe13_wo,
aligned_dataa_exp_dffe14_wo = aligned_dataa_exp_dffe14_wi,
aligned_dataa_exp_dffe15_wi = aligned_dataa_exp_dffe14_wo,
aligned_dataa_exp_dffe15_wo = aligned_dataa_exp_dffe15_wi,
aligned_dataa_exp_w = {1'b0, ({8{(~ input_dataa_denormal_dffe11_wo)}} & dataa_dffe11_wo[30:23])},
aligned_dataa_man_dffe12_wi = aligned_dataa_man_w[25:2],
aligned_dataa_man_dffe12_wo = aligned_dataa_man_dffe12_wi,
aligned_dataa_man_dffe13_wi = aligned_dataa_man_dffe12_wo,
aligned_dataa_man_dffe13_wo = aligned_dataa_man_dffe13_wi,
aligned_dataa_man_dffe14_wi = aligned_dataa_man_dffe13_wo,
aligned_dataa_man_dffe14_wo = aligned_dataa_man_dffe14_wi,
aligned_dataa_man_dffe15_w = {aligned_dataa_man_dffe15_wo, {2{1'b0}}},
aligned_dataa_man_dffe15_wi = aligned_dataa_man_dffe14_wo,
aligned_dataa_man_dffe15_wo = aligned_dataa_man_dffe15_wi,
aligned_dataa_man_w = {(((~ input_dataa_infinite_dffe11_wo) & (~ input_dataa_denormal_dffe11_wo)) & (~ input_dataa_zero_dffe11_wo)), ({23{(~ input_dataa_denormal_dffe11_wo)}} & dataa_dffe11_wo[22:0]), {2{1'b0}}},
aligned_dataa_sign_dffe12_wi = aligned_dataa_sign_w,
aligned_dataa_sign_dffe12_wo = aligned_dataa_sign_dffe12_wi,
aligned_dataa_sign_dffe13_wi = aligned_dataa_sign_dffe12_wo,
aligned_dataa_sign_dffe13_wo = aligned_dataa_sign_dffe13_wi,
aligned_dataa_sign_dffe14_wi = aligned_dataa_sign_dffe13_wo,
aligned_dataa_sign_dffe14_wo = aligned_dataa_sign_dffe14_wi,
aligned_dataa_sign_dffe15_wi = aligned_dataa_sign_dffe14_wo,
aligned_dataa_sign_dffe15_wo = aligned_dataa_sign_dffe15_wi,
aligned_dataa_sign_w = dataa_dffe11_wo[31],
aligned_datab_exp_dffe12_wi = aligned_datab_exp_w,
aligned_datab_exp_dffe12_wo = aligned_datab_exp_dffe12_wi,
aligned_datab_exp_dffe13_wi = aligned_datab_exp_dffe12_wo,
aligned_datab_exp_dffe13_wo = aligned_datab_exp_dffe13_wi,
aligned_datab_exp_dffe14_wi = aligned_datab_exp_dffe13_wo,
aligned_datab_exp_dffe14_wo = aligned_datab_exp_dffe14_wi,
aligned_datab_exp_dffe15_wi = aligned_datab_exp_dffe14_wo,
aligned_datab_exp_dffe15_wo = aligned_datab_exp_dffe15_wi,
aligned_datab_exp_w = {1'b0, ({8{(~ input_datab_denormal_dffe11_wo)}} & datab_dffe11_wo[30:23])},
aligned_datab_man_dffe12_wi = aligned_datab_man_w[25:2],
aligned_datab_man_dffe12_wo = aligned_datab_man_dffe12_wi,
aligned_datab_man_dffe13_wi = aligned_datab_man_dffe12_wo,
aligned_datab_man_dffe13_wo = aligned_datab_man_dffe13_wi,
aligned_datab_man_dffe14_wi = aligned_datab_man_dffe13_wo,
aligned_datab_man_dffe14_wo = aligned_datab_man_dffe14_wi,
aligned_datab_man_dffe15_w = {aligned_datab_man_dffe15_wo, {2{1'b0}}},
aligned_datab_man_dffe15_wi = aligned_datab_man_dffe14_wo,
aligned_datab_man_dffe15_wo = aligned_datab_man_dffe15_wi,
aligned_datab_man_w = {(((~ input_datab_infinite_dffe11_wo) & (~ input_datab_denormal_dffe11_wo)) & (~ input_datab_zero_dffe11_wo)), ({23{(~ input_datab_denormal_dffe11_wo)}} & datab_dffe11_wo[22:0]), {2{1'b0}}},
aligned_datab_sign_dffe12_wi = aligned_datab_sign_w,
aligned_datab_sign_dffe12_wo = aligned_datab_sign_dffe12_wi,
aligned_datab_sign_dffe13_wi = aligned_datab_sign_dffe12_wo,
aligned_datab_sign_dffe13_wo = aligned_datab_sign_dffe13_wi,
aligned_datab_sign_dffe14_wi = aligned_datab_sign_dffe13_wo,
aligned_datab_sign_dffe14_wo = aligned_datab_sign_dffe14_wi,
aligned_datab_sign_dffe15_wi = aligned_datab_sign_dffe14_wo,
aligned_datab_sign_dffe15_wo = aligned_datab_sign_dffe15_wi,
aligned_datab_sign_w = datab_dffe11_wo[31],
borrow_w = ((~ sticky_bit_dffe1_wo) & (~ add_sub_w2)),
both_inputs_are_infinite_dffe1_wi = (input_dataa_infinite_dffe15_wo & input_datab_infinite_dffe15_wo),
both_inputs_are_infinite_dffe1_wo = both_inputs_are_infinite_dffe1,
both_inputs_are_infinite_dffe25_wi = both_inputs_are_infinite_dffe1_wo,
both_inputs_are_infinite_dffe25_wo = both_inputs_are_infinite_dffe25_wi,
data_exp_dffe1_wi = (({8{(~ exp_amb_mux_dffe15_wo)}} & aligned_dataa_exp_dffe15_wo[7:0]) | ({8{exp_amb_mux_dffe15_wo}} & aligned_datab_exp_dffe15_wo[7:0])),
data_exp_dffe1_wo = data_exp_dffe1,
dataa_dffe11_wi = dataa,
dataa_dffe11_wo = dataa_dffe11_wi,
dataa_man_dffe1_wi = (({26{(~ exp_amb_mux_dffe15_wo)}} & aligned_dataa_man_dffe15_w) | ({26{exp_amb_mux_dffe15_wo}} & wire_rbarrel_shift_result)),
dataa_man_dffe1_wo = dataa_man_dffe1,
dataa_sign_dffe1_wi = aligned_dataa_sign_dffe15_wo,
dataa_sign_dffe1_wo = dataa_sign_dffe1,
dataa_sign_dffe25_wi = dataa_sign_dffe1_wo,
dataa_sign_dffe25_wo = dataa_sign_dffe25_wi,
datab_dffe11_wi = datab,
datab_dffe11_wo = datab_dffe11_wi,
datab_man_dffe1_wi = (({26{(~ exp_amb_mux_dffe15_wo)}} & wire_rbarrel_shift_result) | ({26{exp_amb_mux_dffe15_wo}} & aligned_datab_man_dffe15_w)),
datab_man_dffe1_wo = datab_man_dffe1,
datab_sign_dffe1_wi = aligned_datab_sign_dffe15_wo,
datab_sign_dffe1_wo = datab_sign_dffe1,
denormal_flag_w = ((((~ force_nan_w) & (~ force_infinity_w)) & (~ force_zero_w)) & denormal_res_dffe4_wo),
denormal_res_dffe32_wi = denormal_result_w,
denormal_res_dffe32_wo = denormal_res_dffe32_wi,
denormal_res_dffe33_wi = denormal_res_dffe32_wo,
denormal_res_dffe33_wo = denormal_res_dffe33_wi,
denormal_res_dffe3_wi = denormal_res_dffe33_wo,
denormal_res_dffe3_wo = denormal_res_dffe3,
denormal_res_dffe41_wi = denormal_res_dffe42_wo,
denormal_res_dffe41_wo = denormal_res_dffe41_wi,
denormal_res_dffe42_wi = denormal_res_dffe3_wo,
denormal_res_dffe42_wo = denormal_res_dffe42_wi,
denormal_res_dffe4_wi = denormal_res_dffe41_wo,
denormal_res_dffe4_wo = denormal_res_dffe4,
denormal_result_w = ((~ exp_res_not_zero_w[8]) | exp_adjustment2_add_sub_w[8]),
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_adj_0pads = {7{1'b0}},
exp_adj_dffe21_wi = (({2{man_add_sub_res_mag_dffe27_wo[26]}} & exp_adjust_by_add2) | ({2{(~ man_add_sub_res_mag_dffe27_wo[26])}} & exp_adjust_by_add1)),
exp_adj_dffe21_wo = exp_adj_dffe21,
exp_adj_dffe23_wi = exp_adj_dffe21_wo,
exp_adj_dffe23_wo = exp_adj_dffe23_wi,
exp_adj_dffe26_wi = exp_adj_dffe23_wo,
exp_adj_dffe26_wo = exp_adj_dffe26_wi,
exp_adjust_by_add1 = 2'b01,
exp_adjust_by_add2 = 2'b10,
exp_adjustment2_add_sub_dataa_w = exp_value,
exp_adjustment2_add_sub_datab_w = exp_adjustment_add_sub_w,
exp_adjustment2_add_sub_w = wire_add_sub5_result,
exp_adjustment_add_sub_dataa_w = {priority_encoder_1pads_w, wire_leading_zeroes_cnt_q},
exp_adjustment_add_sub_datab_w = {exp_adj_0pads, exp_adj_dffe26_wo},
exp_adjustment_add_sub_w = wire_add_sub4_result,
exp_all_ones_w = {8{1'b1}},
exp_all_zeros_w = {8{1'b0}},
exp_amb_mux_dffe13_wi = exp_amb_mux_w,
exp_amb_mux_dffe13_wo = exp_amb_mux_dffe13_wi,
exp_amb_mux_dffe14_wi = exp_amb_mux_dffe13_wo,
exp_amb_mux_dffe14_wo = exp_amb_mux_dffe14_wi,
exp_amb_mux_dffe15_wi = exp_amb_mux_dffe14_wo,
exp_amb_mux_dffe15_wo = exp_amb_mux_dffe15_wi,
exp_amb_mux_w = exp_amb_w[8],
exp_amb_w = wire_add_sub1_result,
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_bma_w = wire_add_sub2_result,
exp_diff_abs_exceed_max_w = {(exp_diff_abs_exceed_max_w[1] | exp_diff_abs_w[7]), (exp_diff_abs_exceed_max_w[0] | exp_diff_abs_w[6]), exp_diff_abs_w[5]},
exp_diff_abs_max_w = {5{1'b1}},
exp_diff_abs_w = (({8{(~ exp_amb_mux_w)}} & exp_amb_w[7:0]) | ({8{exp_amb_mux_w}} & exp_bma_w[7:0])),
exp_intermediate_res_dffe41_wi = exp_intermediate_res_dffe42_wo,
exp_intermediate_res_dffe41_wo = exp_intermediate_res_dffe41_wi,
exp_intermediate_res_dffe42_wi = exp_intermediate_res_w,
exp_intermediate_res_dffe42_wo = exp_intermediate_res_dffe42_wi,
exp_intermediate_res_w = exp_res_dffe3_wo,
exp_out_dffe5_wi = (({8{force_nan_w}} & exp_all_ones_w) | ({8{(~ force_nan_w)}} & (({8{force_infinity_w}} & exp_all_ones_w) | ({8{(~ force_infinity_w)}} & (({8{(force_zero_w | denormal_flag_w)}} & exp_all_zeros_w) | ({8{(~ (force_zero_w | denormal_flag_w))}} & exp_res_dffe4_wo)))))),
exp_out_dffe5_wo = exp_out_dffe5,
exp_res_dffe21_wi = exp_res_dffe27_wo,
exp_res_dffe21_wo = exp_res_dffe21,
exp_res_dffe22_wi = exp_res_dffe2_wo,
exp_res_dffe22_wo = exp_res_dffe22_wi,
exp_res_dffe23_wi = exp_res_dffe21_wo,
exp_res_dffe23_wo = exp_res_dffe23_wi,
exp_res_dffe25_wi = data_exp_dffe1_wo,
exp_res_dffe25_wo = exp_res_dffe25_wi,
exp_res_dffe26_wi = exp_res_dffe23_wo,
exp_res_dffe26_wo = exp_res_dffe26_wi,
exp_res_dffe27_wi = exp_res_dffe22_wo,
exp_res_dffe27_wo = exp_res_dffe27_wi,
exp_res_dffe2_wi = exp_res_dffe25_wo,
exp_res_dffe2_wo = exp_res_dffe2,
exp_res_dffe32_wi = ({8{(~ denormal_result_w)}} & exp_adjustment2_add_sub_w[7:0]),
exp_res_dffe32_wo = exp_res_dffe32_wi,
exp_res_dffe33_wi = exp_res_dffe32_wo,
exp_res_dffe33_wo = exp_res_dffe33_wi,
exp_res_dffe3_wi = exp_res_dffe33_wo,
exp_res_dffe3_wo = exp_res_dffe3,
exp_res_dffe4_wi = exp_rounded_res_w,
exp_res_dffe4_wo = exp_res_dffe4,
exp_res_max_w = {(exp_res_max_w[6] & exp_adjustment2_add_sub_w[7]), (exp_res_max_w[5] & exp_adjustment2_add_sub_w[6]), (exp_res_max_w[4] & exp_adjustment2_add_sub_w[5]), (exp_res_max_w[3] & exp_adjustment2_add_sub_w[4]), (exp_res_max_w[2] & exp_adjustment2_add_sub_w[3]), (exp_res_max_w[1] & exp_adjustment2_add_sub_w[2]), (exp_res_max_w[0] & exp_adjustment2_add_sub_w[1]), exp_adjustment2_add_sub_w[0]},
exp_res_not_zero_w = {(exp_res_not_zero_w[7] | exp_adjustment2_add_sub_w[8]), (exp_res_not_zero_w[6] | exp_adjustment2_add_sub_w[7]), (exp_res_not_zero_w[5] | exp_adjustment2_add_sub_w[6]), (exp_res_not_zero_w[4] | exp_adjustment2_add_sub_w[5]), (exp_res_not_zero_w[3] | exp_adjustment2_add_sub_w[4]), (exp_res_not_zero_w[2] | exp_adjustment2_add_sub_w[3]), (exp_res_not_zero_w[1] | exp_adjustment2_add_sub_w[2]), (exp_res_not_zero_w[0] | exp_adjustment2_add_sub_w[1]), exp_adjustment2_add_sub_w[0]},
exp_res_rounding_adder_dataa_w = {1'b0, exp_intermediate_res_dffe41_wo},
exp_res_rounding_adder_w = wire_add_sub6_result,
exp_rounded_res_infinity_w = exp_rounded_res_max_w[7],
exp_rounded_res_max_w = {(exp_rounded_res_max_w[6] & exp_rounded_res_w[7]), (exp_rounded_res_max_w[5] & exp_rounded_res_w[6]), (exp_rounded_res_max_w[4] & exp_rounded_res_w[5]), (exp_rounded_res_max_w[3] & exp_rounded_res_w[4]), (exp_rounded_res_max_w[2] & exp_rounded_res_w[3]), (exp_rounded_res_max_w[1] & exp_rounded_res_w[2]), (exp_rounded_res_max_w[0] & exp_rounded_res_w[1]), exp_rounded_res_w[0]},
exp_rounded_res_w = exp_res_rounding_adder_w[7:0],
exp_rounding_adjustment_w = {{8{1'b0}}, man_res_rounding_add_sub_w[24]},
exp_value = {1'b0, exp_res_dffe26_wo},
force_infinity_w = ((input_is_infinite_dffe4_wo | rounded_res_infinity_dffe4_wo) | infinite_res_dffe4_wo),
force_nan_w = (infinity_magnitude_sub_dffe4_wo | input_is_nan_dffe4_wo),
force_zero_w = (~ man_res_is_not_zero_dffe4_wo),
guard_bit_dffe3_wo = man_res_w3[0],
infinite_output_sign_dffe1_wi = (((~ input_datab_infinite_dffe15_wo) & aligned_dataa_sign_dffe15_wo) | (input_datab_infinite_dffe15_wo & aligned_datab_sign_dffe15_wo)),
infinite_output_sign_dffe1_wo = infinite_output_sign_dffe1,
infinite_output_sign_dffe21_wi = infinite_output_sign_dffe27_wo,
infinite_output_sign_dffe21_wo = infinite_output_sign_dffe21,
infinite_output_sign_dffe22_wi = infinite_output_sign_dffe2_wo,
infinite_output_sign_dffe22_wo = infinite_output_sign_dffe22_wi,
infinite_output_sign_dffe23_wi = infinite_output_sign_dffe21_wo,
infinite_output_sign_dffe23_wo = infinite_output_sign_dffe23_wi,
infinite_output_sign_dffe25_wi = infinite_output_sign_dffe1_wo,
infinite_output_sign_dffe25_wo = infinite_output_sign_dffe25_wi,
infinite_output_sign_dffe26_wi = infinite_output_sign_dffe23_wo,
infinite_output_sign_dffe26_wo = infinite_output_sign_dffe26_wi,
infinite_output_sign_dffe27_wi = infinite_output_sign_dffe22_wo,
infinite_output_sign_dffe27_wo = infinite_output_sign_dffe27_wi,
infinite_output_sign_dffe2_wi = infinite_output_sign_dffe25_wo,
infinite_output_sign_dffe2_wo = infinite_output_sign_dffe2,
infinite_output_sign_dffe31_wi = infinite_output_sign_dffe26_wo,
infinite_output_sign_dffe31_wo = infinite_output_sign_dffe31,
infinite_output_sign_dffe32_wi = infinite_output_sign_dffe31_wo,
infinite_output_sign_dffe32_wo = infinite_output_sign_dffe32_wi,
infinite_output_sign_dffe33_wi = infinite_output_sign_dffe32_wo,
infinite_output_sign_dffe33_wo = infinite_output_sign_dffe33_wi,
infinite_output_sign_dffe3_wi = infinite_output_sign_dffe33_wo,
infinite_output_sign_dffe3_wo = infinite_output_sign_dffe3,
infinite_output_sign_dffe41_wi = infinite_output_sign_dffe42_wo,
infinite_output_sign_dffe41_wo = infinite_output_sign_dffe41_wi,
infinite_output_sign_dffe42_wi = infinite_output_sign_dffe3_wo,
infinite_output_sign_dffe42_wo = infinite_output_sign_dffe42_wi,
infinite_output_sign_dffe4_wi = infinite_output_sign_dffe41_wo,
infinite_output_sign_dffe4_wo = infinite_output_sign_dffe4,
infinite_res_dff32_wi = (exp_res_max_w[7] & (~ exp_adjustment2_add_sub_w[8])),
infinite_res_dff32_wo = infinite_res_dff32_wi,
infinite_res_dff33_wi = infinite_res_dff32_wo,
infinite_res_dff33_wo = infinite_res_dff33_wi,
infinite_res_dffe3_wi = infinite_res_dff33_wo,
infinite_res_dffe3_wo = infinite_res_dffe3,
infinite_res_dffe41_wi = infinite_res_dffe42_wo,
infinite_res_dffe41_wo = infinite_res_dffe41_wi,
infinite_res_dffe42_wi = infinite_res_dffe3_wo,
infinite_res_dffe42_wo = infinite_res_dffe42_wi,
infinite_res_dffe4_wi = infinite_res_dffe41_wo,
infinite_res_dffe4_wo = infinite_res_dffe4,
infinity_magnitude_sub_dffe21_wi = infinity_magnitude_sub_dffe27_wo,
infinity_magnitude_sub_dffe21_wo = infinity_magnitude_sub_dffe21,
infinity_magnitude_sub_dffe22_wi = infinity_magnitude_sub_dffe2_wo,
infinity_magnitude_sub_dffe22_wo = infinity_magnitude_sub_dffe22_wi,
infinity_magnitude_sub_dffe23_wi = infinity_magnitude_sub_dffe21_wo,
infinity_magnitude_sub_dffe23_wo = infinity_magnitude_sub_dffe23_wi,
infinity_magnitude_sub_dffe26_wi = infinity_magnitude_sub_dffe23_wo,
infinity_magnitude_sub_dffe26_wo = infinity_magnitude_sub_dffe26_wi,
infinity_magnitude_sub_dffe27_wi = infinity_magnitude_sub_dffe22_wo,
infinity_magnitude_sub_dffe27_wo = infinity_magnitude_sub_dffe27_wi,
infinity_magnitude_sub_dffe2_wi = ((~ add_sub_dffe25_wo) & both_inputs_are_infinite_dffe25_wo),
infinity_magnitude_sub_dffe2_wo = infinity_magnitude_sub_dffe2,
infinity_magnitude_sub_dffe31_wi = infinity_magnitude_sub_dffe26_wo,
infinity_magnitude_sub_dffe31_wo = infinity_magnitude_sub_dffe31,
infinity_magnitude_sub_dffe32_wi = infinity_magnitude_sub_dffe31_wo,
infinity_magnitude_sub_dffe32_wo = infinity_magnitude_sub_dffe32_wi,
infinity_magnitude_sub_dffe33_wi = infinity_magnitude_sub_dffe32_wo,
infinity_magnitude_sub_dffe33_wo = infinity_magnitude_sub_dffe33_wi,
infinity_magnitude_sub_dffe3_wi = infinity_magnitude_sub_dffe33_wo,
infinity_magnitude_sub_dffe3_wo = infinity_magnitude_sub_dffe3,
infinity_magnitude_sub_dffe41_wi = infinity_magnitude_sub_dffe42_wo,
infinity_magnitude_sub_dffe41_wo = infinity_magnitude_sub_dffe41_wi,
infinity_magnitude_sub_dffe42_wi = infinity_magnitude_sub_dffe3_wo,
infinity_magnitude_sub_dffe42_wo = infinity_magnitude_sub_dffe42_wi,
infinity_magnitude_sub_dffe4_wi = infinity_magnitude_sub_dffe41_wo,
infinity_magnitude_sub_dffe4_wo = infinity_magnitude_sub_dffe4,
input_dataa_denormal_dffe11_wi = input_dataa_denormal_w,
input_dataa_denormal_dffe11_wo = input_dataa_denormal_dffe11_wi,
input_dataa_denormal_w = ((~ exp_a_not_zero_w[7]) & man_a_not_zero_w[22]),
input_dataa_infinite_dffe11_wi = input_dataa_infinite_w,
input_dataa_infinite_dffe11_wo = input_dataa_infinite_dffe11_wi,
input_dataa_infinite_dffe12_wi = input_dataa_infinite_dffe11_wo,
input_dataa_infinite_dffe12_wo = input_dataa_infinite_dffe12_wi,
input_dataa_infinite_dffe13_wi = input_dataa_infinite_dffe12_wo,
input_dataa_infinite_dffe13_wo = input_dataa_infinite_dffe13_wi,
input_dataa_infinite_dffe14_wi = input_dataa_infinite_dffe13_wo,
input_dataa_infinite_dffe14_wo = input_dataa_infinite_dffe14_wi,
input_dataa_infinite_dffe15_wi = input_dataa_infinite_dffe14_wo,
input_dataa_infinite_dffe15_wo = input_dataa_infinite_dffe15_wi,
input_dataa_infinite_w = (exp_a_all_one_w[7] & (~ man_a_not_zero_w[22])),
input_dataa_nan_dffe11_wi = input_dataa_nan_w,
input_dataa_nan_dffe11_wo = input_dataa_nan_dffe11_wi,
input_dataa_nan_dffe12_wi = input_dataa_nan_dffe11_wo,
input_dataa_nan_dffe12_wo = input_dataa_nan_dffe12_wi,
input_dataa_nan_w = (exp_a_all_one_w[7] & man_a_not_zero_w[22]),
input_dataa_zero_dffe11_wi = input_dataa_zero_w,
input_dataa_zero_dffe11_wo = input_dataa_zero_dffe11_wi,
input_dataa_zero_w = ((~ exp_a_not_zero_w[7]) & (~ man_a_not_zero_w[22])),
input_datab_denormal_dffe11_wi = input_datab_denormal_w,
input_datab_denormal_dffe11_wo = input_datab_denormal_dffe11_wi,
input_datab_denormal_w = ((~ exp_b_not_zero_w[7]) & man_b_not_zero_w[22]),
input_datab_infinite_dffe11_wi = input_datab_infinite_w,
input_datab_infinite_dffe11_wo = input_datab_infinite_dffe11_wi,
input_datab_infinite_dffe12_wi = input_datab_infinite_dffe11_wo,
input_datab_infinite_dffe12_wo = input_datab_infinite_dffe12_wi,
input_datab_infinite_dffe13_wi = input_datab_infinite_dffe12_wo,
input_datab_infinite_dffe13_wo = input_datab_infinite_dffe13_wi,
input_datab_infinite_dffe14_wi = input_datab_infinite_dffe13_wo,
input_datab_infinite_dffe14_wo = input_datab_infinite_dffe14_wi,
input_datab_infinite_dffe15_wi = input_datab_infinite_dffe14_wo,
input_datab_infinite_dffe15_wo = input_datab_infinite_dffe15_wi,
input_datab_infinite_w = (exp_b_all_one_w[7] & (~ man_b_not_zero_w[22])),
input_datab_nan_dffe11_wi = input_datab_nan_w,
input_datab_nan_dffe11_wo = input_datab_nan_dffe11_wi,
input_datab_nan_dffe12_wi = input_datab_nan_dffe11_wo,
input_datab_nan_dffe12_wo = input_datab_nan_dffe12_wi,
input_datab_nan_w = (exp_b_all_one_w[7] & man_b_not_zero_w[22]),
input_datab_zero_dffe11_wi = input_datab_zero_w,
input_datab_zero_dffe11_wo = input_datab_zero_dffe11_wi,
input_datab_zero_w = ((~ exp_b_not_zero_w[7]) & (~ man_b_not_zero_w[22])),
input_is_infinite_dffe1_wi = (input_dataa_infinite_dffe15_wo | input_datab_infinite_dffe15_wo),
input_is_infinite_dffe1_wo = input_is_infinite_dffe1,
input_is_infinite_dffe21_wi = input_is_infinite_dffe27_wo,
input_is_infinite_dffe21_wo = input_is_infinite_dffe21,
input_is_infinite_dffe22_wi = input_is_infinite_dffe2_wo,
input_is_infinite_dffe22_wo = input_is_infinite_dffe22_wi,
input_is_infinite_dffe23_wi = input_is_infinite_dffe21_wo,
input_is_infinite_dffe23_wo = input_is_infinite_dffe23_wi,
input_is_infinite_dffe25_wi = input_is_infinite_dffe1_wo,
input_is_infinite_dffe25_wo = input_is_infinite_dffe25_wi,
input_is_infinite_dffe26_wi = input_is_infinite_dffe23_wo,
input_is_infinite_dffe26_wo = input_is_infinite_dffe26_wi,
input_is_infinite_dffe27_wi = input_is_infinite_dffe22_wo,
input_is_infinite_dffe27_wo = input_is_infinite_dffe27_wi,
input_is_infinite_dffe2_wi = input_is_infinite_dffe25_wo,
input_is_infinite_dffe2_wo = input_is_infinite_dffe2,
input_is_infinite_dffe31_wi = input_is_infinite_dffe26_wo,
input_is_infinite_dffe31_wo = input_is_infinite_dffe31,
input_is_infinite_dffe32_wi = input_is_infinite_dffe31_wo,
input_is_infinite_dffe32_wo = input_is_infinite_dffe32_wi,
input_is_infinite_dffe33_wi = input_is_infinite_dffe32_wo,
input_is_infinite_dffe33_wo = input_is_infinite_dffe33_wi,
input_is_infinite_dffe3_wi = input_is_infinite_dffe33_wo,
input_is_infinite_dffe3_wo = input_is_infinite_dffe3,
input_is_infinite_dffe41_wi = input_is_infinite_dffe42_wo,
input_is_infinite_dffe41_wo = input_is_infinite_dffe41_wi,
input_is_infinite_dffe42_wi = input_is_infinite_dffe3_wo,
input_is_infinite_dffe42_wo = input_is_infinite_dffe42_wi,
input_is_infinite_dffe4_wi = input_is_infinite_dffe41_wo,
input_is_infinite_dffe4_wo = input_is_infinite_dffe4,
input_is_nan_dffe13_wi = (input_dataa_nan_dffe12_wo | input_datab_nan_dffe12_wo),
input_is_nan_dffe13_wo = input_is_nan_dffe13_wi,
input_is_nan_dffe14_wi = input_is_nan_dffe13_wo,
input_is_nan_dffe14_wo = input_is_nan_dffe14_wi,
input_is_nan_dffe15_wi = input_is_nan_dffe14_wo,
input_is_nan_dffe15_wo = input_is_nan_dffe15_wi,
input_is_nan_dffe1_wi = input_is_nan_dffe15_wo,
input_is_nan_dffe1_wo = input_is_nan_dffe1,
input_is_nan_dffe21_wi = input_is_nan_dffe27_wo,
input_is_nan_dffe21_wo = input_is_nan_dffe21,
input_is_nan_dffe22_wi = input_is_nan_dffe2_wo,
input_is_nan_dffe22_wo = input_is_nan_dffe22_wi,
input_is_nan_dffe23_wi = input_is_nan_dffe21_wo,
input_is_nan_dffe23_wo = input_is_nan_dffe23_wi,
input_is_nan_dffe25_wi = input_is_nan_dffe1_wo,
input_is_nan_dffe25_wo = input_is_nan_dffe25_wi,
input_is_nan_dffe26_wi = input_is_nan_dffe23_wo,
input_is_nan_dffe26_wo = input_is_nan_dffe26_wi,
input_is_nan_dffe27_wi = input_is_nan_dffe22_wo,
input_is_nan_dffe27_wo = input_is_nan_dffe27_wi,
input_is_nan_dffe2_wi = input_is_nan_dffe25_wo,
input_is_nan_dffe2_wo = input_is_nan_dffe2,
input_is_nan_dffe31_wi = input_is_nan_dffe26_wo,
input_is_nan_dffe31_wo = input_is_nan_dffe31,
input_is_nan_dffe32_wi = input_is_nan_dffe31_wo,
input_is_nan_dffe32_wo = input_is_nan_dffe32_wi,
input_is_nan_dffe33_wi = input_is_nan_dffe32_wo,
input_is_nan_dffe33_wo = input_is_nan_dffe33_wi,
input_is_nan_dffe3_wi = input_is_nan_dffe33_wo,
input_is_nan_dffe3_wo = input_is_nan_dffe3,
input_is_nan_dffe41_wi = input_is_nan_dffe42_wo,
input_is_nan_dffe41_wo = input_is_nan_dffe41_wi,
input_is_nan_dffe42_wi = input_is_nan_dffe3_wo,
input_is_nan_dffe42_wo = input_is_nan_dffe42_wi,
input_is_nan_dffe4_wi = input_is_nan_dffe41_wo,
input_is_nan_dffe4_wo = input_is_nan_dffe4,
man_2comp_res_dataa_w = {pos_sign_bit_ext, datab_man_dffe1_wo},
man_2comp_res_datab_w = {pos_sign_bit_ext, dataa_man_dffe1_wo},
man_2comp_res_w = {(({14{(~ wire_man_2comp_res_lower_cout)}} & wire_man_2comp_res_upper0_result) | ({14{wire_man_2comp_res_lower_cout}} & wire_man_2comp_res_upper1_result)), wire_man_2comp_res_lower_result},
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), (dataa[12] | man_a_not_zero_w[11]), (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_add_sub_dataa_w = {pos_sign_bit_ext, dataa_man_dffe1_wo},
man_add_sub_datab_w = {pos_sign_bit_ext, datab_man_dffe1_wo},
man_add_sub_res_mag_dffe21_wi = man_res_mag_w2,
man_add_sub_res_mag_dffe21_wo = man_add_sub_res_mag_dffe21,
man_add_sub_res_mag_dffe23_wi = man_add_sub_res_mag_dffe21_wo,
man_add_sub_res_mag_dffe23_wo = man_add_sub_res_mag_dffe23_wi,
man_add_sub_res_mag_dffe26_wi = man_add_sub_res_mag_dffe23_wo,
man_add_sub_res_mag_dffe26_wo = man_add_sub_res_mag_dffe26_wi,
man_add_sub_res_mag_dffe27_wi = man_add_sub_res_mag_w2,
man_add_sub_res_mag_dffe27_wo = man_add_sub_res_mag_dffe27_wi,
man_add_sub_res_mag_w2 = (({28{man_add_sub_w[27]}} & man_2comp_res_w) | ({28{(~ man_add_sub_w[27])}} & man_add_sub_w)),
man_add_sub_res_sign_dffe21_wo = man_add_sub_res_sign_dffe21,
man_add_sub_res_sign_dffe23_wi = man_add_sub_res_sign_dffe21_wo,
man_add_sub_res_sign_dffe23_wo = man_add_sub_res_sign_dffe23_wi,
man_add_sub_res_sign_dffe26_wi = man_add_sub_res_sign_dffe23_wo,
man_add_sub_res_sign_dffe26_wo = man_add_sub_res_sign_dffe26_wi,
man_add_sub_res_sign_dffe27_wi = man_add_sub_res_sign_w2,
man_add_sub_res_sign_dffe27_wo = man_add_sub_res_sign_dffe27_wi,
man_add_sub_res_sign_w2 = ((need_complement_dffe22_wo & (~ man_add_sub_w[27])) | ((~ need_complement_dffe22_wo) & man_add_sub_w[27])),
man_add_sub_w = {(({14{(~ wire_man_add_sub_lower_cout)}} & wire_man_add_sub_upper0_result) | ({14{wire_man_add_sub_lower_cout}} & wire_man_add_sub_upper1_result)), wire_man_add_sub_lower_result},
man_all_zeros_w = {23{1'b0}},
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), (datab[12] | man_b_not_zero_w[11]), (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
man_dffe31_wo = man_dffe31,
man_intermediate_res_w = {{2{1'b0}}, man_res_w3},
man_leading_zeros_cnt_w = man_leading_zeros_dffe31_wo,
man_leading_zeros_dffe31_wi = (~ wire_leading_zeroes_cnt_q),
man_leading_zeros_dffe31_wo = man_leading_zeros_dffe31,
man_nan_w = 23'b10000000000000000000000,
man_out_dffe5_wi = (({23{force_nan_w}} & man_nan_w) | ({23{(~ force_nan_w)}} & (({23{force_infinity_w}} & man_all_zeros_w) | ({23{(~ force_infinity_w)}} & (({23{(force_zero_w | denormal_flag_w)}} & man_all_zeros_w) | ({23{(~ (force_zero_w | denormal_flag_w))}} & man_res_dffe4_wo)))))),
man_out_dffe5_wo = man_out_dffe5,
man_res_dffe4_wi = man_rounded_res_w,
man_res_dffe4_wo = man_res_dffe4,
man_res_is_not_zero_dffe31_wi = man_res_not_zero_dffe26_wo,
man_res_is_not_zero_dffe31_wo = man_res_is_not_zero_dffe31,
man_res_is_not_zero_dffe32_wi = man_res_is_not_zero_dffe31_wo,
man_res_is_not_zero_dffe32_wo = man_res_is_not_zero_dffe32_wi,
man_res_is_not_zero_dffe33_wi = man_res_is_not_zero_dffe32_wo,
man_res_is_not_zero_dffe33_wo = man_res_is_not_zero_dffe33_wi,
man_res_is_not_zero_dffe3_wi = man_res_is_not_zero_dffe33_wo,
man_res_is_not_zero_dffe3_wo = man_res_is_not_zero_dffe3,
man_res_is_not_zero_dffe41_wi = man_res_is_not_zero_dffe42_wo,
man_res_is_not_zero_dffe41_wo = man_res_is_not_zero_dffe41_wi,
man_res_is_not_zero_dffe42_wi = man_res_is_not_zero_dffe3_wo,
man_res_is_not_zero_dffe42_wo = man_res_is_not_zero_dffe42_wi,
man_res_is_not_zero_dffe4_wi = man_res_is_not_zero_dffe41_wo,
man_res_is_not_zero_dffe4_wo = man_res_is_not_zero_dffe4,
man_res_mag_w2 = (({26{man_add_sub_res_mag_dffe27_wo[26]}} & man_add_sub_res_mag_dffe27_wo[26:1]) | ({26{(~ man_add_sub_res_mag_dffe27_wo[26])}} & man_add_sub_res_mag_dffe27_wo[25:0])),
man_res_not_zero_dffe23_wi = man_res_not_zero_w2[24],
man_res_not_zero_dffe23_wo = man_res_not_zero_dffe23_wi,
man_res_not_zero_dffe26_wi = man_res_not_zero_dffe23_wo,
man_res_not_zero_dffe26_wo = man_res_not_zero_dffe26_wi,
man_res_not_zero_w2 = {(man_res_not_zero_w2[23] | man_add_sub_res_mag_dffe21_wo[25]), (man_res_not_zero_w2[22] | man_add_sub_res_mag_dffe21_wo[24]), (man_res_not_zero_w2[21] | man_add_sub_res_mag_dffe21_wo[23]), (man_res_not_zero_w2[20] | man_add_sub_res_mag_dffe21_wo[22]), (man_res_not_zero_w2[19] | man_add_sub_res_mag_dffe21_wo[21]), (man_res_not_zero_w2[18] | man_add_sub_res_mag_dffe21_wo[20]), (man_res_not_zero_w2[17] | man_add_sub_res_mag_dffe21_wo[19]), (man_res_not_zero_w2[16] | man_add_sub_res_mag_dffe21_wo[18]), (man_res_not_zero_w2[15] | man_add_sub_res_mag_dffe21_wo[17]), (man_res_not_zero_w2[14] | man_add_sub_res_mag_dffe21_wo[16]), (man_res_not_zero_w2[13] | man_add_sub_res_mag_dffe21_wo[15]), (man_res_not_zero_w2[12] | man_add_sub_res_mag_dffe21_wo[14]), (man_res_not_zero_w2[11] | man_add_sub_res_mag_dffe21_wo[13]), (man_res_not_zero_w2[10] | man_add_sub_res_mag_dffe21_wo[12]), (man_res_not_zero_w2[9] | man_add_sub_res_mag_dffe21_wo[11]), (man_res_not_zero_w2[8] | man_add_sub_res_mag_dffe21_wo[10]), (man_res_not_zero_w2[7] | man_add_sub_res_mag_dffe21_wo[9]), (man_res_not_zero_w2[6] | man_add_sub_res_mag_dffe21_wo[8]), (man_res_not_zero_w2[5] | man_add_sub_res_mag_dffe21_wo[7]), (man_res_not_zero_w2[4] | man_add_sub_res_mag_dffe21_wo[6]), (man_res_not_zero_w2[3] | man_add_sub_res_mag_dffe21_wo[5]), (man_res_not_zero_w2[2] | man_add_sub_res_mag_dffe21_wo[4]), (man_res_not_zero_w2[1] | man_add_sub_res_mag_dffe21_wo[3]), (man_res_not_zero_w2[0] | man_add_sub_res_mag_dffe21_wo[2]), man_add_sub_res_mag_dffe21_wo[1]},
man_res_rounding_add_sub_datab_w = {{25{1'b0}}, man_rounding_add_value_w},
man_res_rounding_add_sub_w = {(({13{(~ wire_man_res_rounding_add_sub_lower_cout)}} & adder_upper_w) | ({13{wire_man_res_rounding_add_sub_lower_cout}} & wire_man_res_rounding_add_sub_upper1_result)), wire_man_res_rounding_add_sub_lower_result},
man_res_w3 = wire_lbarrel_shift_result[25:2],
man_rounded_res_w = (({23{man_res_rounding_add_sub_w[24]}} & man_res_rounding_add_sub_w[23:1]) | ({23{(~ man_res_rounding_add_sub_w[24])}} & man_res_rounding_add_sub_w[22:0])),
man_rounding_add_value_w = (round_bit_dffe3_wo & (sticky_bit_dffe3_wo | guard_bit_dffe3_wo)),
man_smaller_dffe13_wi = man_smaller_w,
man_smaller_dffe13_wo = man_smaller_dffe13_wi,
man_smaller_w = (({24{exp_amb_mux_w}} & aligned_dataa_man_dffe12_wo) | ({24{(~ exp_amb_mux_w)}} & aligned_datab_man_dffe12_wo)),
need_complement_dffe22_wi = need_complement_dffe2_wo,
need_complement_dffe22_wo = need_complement_dffe22_wi,
need_complement_dffe2_wi = dataa_sign_dffe25_wo,
need_complement_dffe2_wo = need_complement_dffe2,
overflow = overflow_flag_dffe5_wo,
overflow_flag_dffe5_wi = overflow_flag_w,
overflow_flag_dffe5_wo = overflow_flag_dffe5,
overflow_flag_w = (((~ force_nan_w) & force_infinity_w) & (~ input_is_infinite_dffe4_wo)),
pos_sign_bit_ext = {2{1'b0}},
priority_encoder_1pads_w = {4{1'b1}},
result = {sign_out_dffe5_wo, exp_out_dffe5_wo, man_out_dffe5_wo},
round_bit_dffe21_wi = round_bit_w,
round_bit_dffe21_wo = round_bit_dffe21,
round_bit_dffe23_wi = round_bit_dffe21_wo,
round_bit_dffe23_wo = round_bit_dffe23_wi,
round_bit_dffe26_wi = round_bit_dffe23_wo,
round_bit_dffe26_wo = round_bit_dffe26_wi,
round_bit_dffe31_wi = round_bit_dffe26_wo,
round_bit_dffe31_wo = round_bit_dffe31,
round_bit_dffe32_wi = round_bit_dffe31_wo,
round_bit_dffe32_wo = round_bit_dffe32_wi,
round_bit_dffe33_wi = round_bit_dffe32_wo,
round_bit_dffe33_wo = round_bit_dffe33_wi,
round_bit_dffe3_wi = round_bit_dffe33_wo,
round_bit_dffe3_wo = round_bit_dffe3,
round_bit_w = ((((((~ man_add_sub_res_mag_dffe27_wo[26]) & (~ man_add_sub_res_mag_dffe27_wo[25])) & man_add_sub_res_mag_dffe27_wo[0]) | (((~ man_add_sub_res_mag_dffe27_wo[26]) & man_add_sub_res_mag_dffe27_wo[25]) & man_add_sub_res_mag_dffe27_wo[1])) | ((man_add_sub_res_mag_dffe27_wo[26] & (~ man_add_sub_res_mag_dffe27_wo[25])) & man_add_sub_res_mag_dffe27_wo[2])) | ((man_add_sub_res_mag_dffe27_wo[26] & man_add_sub_res_mag_dffe27_wo[25]) & man_add_sub_res_mag_dffe27_wo[2])),
rounded_res_infinity_dffe4_wi = exp_rounded_res_infinity_w,
rounded_res_infinity_dffe4_wo = rounded_res_infinity_dffe4,
rshift_distance_dffe13_wi = rshift_distance_w,
rshift_distance_dffe13_wo = rshift_distance_dffe13_wi,
rshift_distance_dffe14_wi = rshift_distance_dffe13_wo,
rshift_distance_dffe14_wo = rshift_distance_dffe14_wi,
rshift_distance_dffe15_wi = rshift_distance_dffe14_wo,
rshift_distance_dffe15_wo = rshift_distance_dffe15_wi,
rshift_distance_w = (({5{exp_diff_abs_exceed_max_w[2]}} & exp_diff_abs_max_w) | ({5{(~ exp_diff_abs_exceed_max_w[2])}} & exp_diff_abs_w[4:0])),
sign_dffe31_wi = ((man_res_not_zero_dffe26_wo & man_add_sub_res_sign_dffe26_wo) | ((~ man_res_not_zero_dffe26_wo) & zero_man_sign_dffe26_wo)),
sign_dffe31_wo = sign_dffe31,
sign_dffe32_wi = sign_dffe31_wo,
sign_dffe32_wo = sign_dffe32_wi,
sign_dffe33_wi = sign_dffe32_wo,
sign_dffe33_wo = sign_dffe33_wi,
sign_out_dffe5_wi = ((~ force_nan_w) & ((force_infinity_w & infinite_output_sign_dffe4_wo) | ((~ force_infinity_w) & sign_res_dffe4_wo))),
sign_out_dffe5_wo = sign_out_dffe5,
sign_res_dffe3_wi = sign_dffe33_wo,
sign_res_dffe3_wo = sign_res_dffe3,
sign_res_dffe41_wi = sign_res_dffe42_wo,
sign_res_dffe41_wo = sign_res_dffe41_wi,
sign_res_dffe42_wi = sign_res_dffe3_wo,
sign_res_dffe42_wo = sign_res_dffe42_wi,
sign_res_dffe4_wi = sign_res_dffe41_wo,
sign_res_dffe4_wo = sign_res_dffe4,
sticky_bit_cnt_dataa_w = {1'b0, rshift_distance_dffe15_wo},
sticky_bit_cnt_datab_w = {1'b0, wire_trailing_zeros_cnt_q},
sticky_bit_cnt_res_w = wire_add_sub3_result,
sticky_bit_dffe1_wi = wire_trailing_zeros_limit_comparator_agb,
sticky_bit_dffe1_wo = sticky_bit_dffe1,
sticky_bit_dffe21_wi = sticky_bit_w,
sticky_bit_dffe21_wo = sticky_bit_dffe21,
sticky_bit_dffe22_wi = sticky_bit_dffe2_wo,
sticky_bit_dffe22_wo = sticky_bit_dffe22_wi,
sticky_bit_dffe23_wi = sticky_bit_dffe21_wo,
sticky_bit_dffe23_wo = sticky_bit_dffe23_wi,
sticky_bit_dffe25_wi = sticky_bit_dffe1_wo,
sticky_bit_dffe25_wo = sticky_bit_dffe25_wi,
sticky_bit_dffe26_wi = sticky_bit_dffe23_wo,
sticky_bit_dffe26_wo = sticky_bit_dffe26_wi,
sticky_bit_dffe27_wi = sticky_bit_dffe22_wo,
sticky_bit_dffe27_wo = sticky_bit_dffe27_wi,
sticky_bit_dffe2_wi = sticky_bit_dffe25_wo,
sticky_bit_dffe2_wo = sticky_bit_dffe2,
sticky_bit_dffe31_wi = sticky_bit_dffe26_wo,
sticky_bit_dffe31_wo = sticky_bit_dffe31,
sticky_bit_dffe32_wi = sticky_bit_dffe31_wo,
sticky_bit_dffe32_wo = sticky_bit_dffe32_wi,
sticky_bit_dffe33_wi = sticky_bit_dffe32_wo,
sticky_bit_dffe33_wo = sticky_bit_dffe33_wi,
sticky_bit_dffe3_wi = sticky_bit_dffe33_wo,
sticky_bit_dffe3_wo = sticky_bit_dffe3,
sticky_bit_w = ((((((~ man_add_sub_res_mag_dffe27_wo[26]) & (~ man_add_sub_res_mag_dffe27_wo[25])) & sticky_bit_dffe27_wo) | (((~ man_add_sub_res_mag_dffe27_wo[26]) & man_add_sub_res_mag_dffe27_wo[25]) & (sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]))) | ((man_add_sub_res_mag_dffe27_wo[26] & (~ man_add_sub_res_mag_dffe27_wo[25])) & ((sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]) | man_add_sub_res_mag_dffe27_wo[1]))) | ((man_add_sub_res_mag_dffe27_wo[26] & man_add_sub_res_mag_dffe27_wo[25]) & ((sticky_bit_dffe27_wo | man_add_sub_res_mag_dffe27_wo[0]) | man_add_sub_res_mag_dffe27_wo[1]))),
trailing_zeros_limit_w = 6'b000010,
zero_man_sign_dffe21_wi = zero_man_sign_dffe27_wo,
zero_man_sign_dffe21_wo = zero_man_sign_dffe21,
zero_man_sign_dffe22_wi = zero_man_sign_dffe2_wo,
zero_man_sign_dffe22_wo = zero_man_sign_dffe22_wi,
zero_man_sign_dffe23_wi = zero_man_sign_dffe21_wo,
zero_man_sign_dffe23_wo = zero_man_sign_dffe23_wi,
zero_man_sign_dffe26_wi = zero_man_sign_dffe23_wo,
zero_man_sign_dffe26_wo = zero_man_sign_dffe26_wi,
zero_man_sign_dffe27_wi = zero_man_sign_dffe22_wo,
zero_man_sign_dffe27_wo = zero_man_sign_dffe27_wi,
zero_man_sign_dffe2_wi = (dataa_sign_dffe25_wo & add_sub_dffe25_wo),
zero_man_sign_dffe2_wo = zero_man_sign_dffe2;
endmodule |
module float_add_sub (
clk_en,
clock,
dataa,
datab,
overflow,
result);
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
wire sub_wire0;
wire [31:0] sub_wire1;
wire overflow = sub_wire0;
wire [31:0] result = sub_wire1[31:0];
float_add_sub_altfp_add_sub_2jk float_add_sub_altfp_add_sub_2jk_component (
.clk_en (clk_en),
.clock (clock),
.datab (datab),
.dataa (dataa),
.overflow (sub_wire0),
.result (sub_wire1));
endmodule |
module D2STR_B#
(
parameter integer len = 16 // Symbols to show
)
(
output wire [127:0] str,
input wire [len-1:0] d
);
genvar i;
generate
for (i = 0; i < len; i = i + 1) begin
assign str[8*i+7:8*i] = d[i]? "1" : "0";
end
for (i = len; i < 16; i = i + 1) begin
assign str[8*i+7:8*i] = " ";
end
endgenerate
endmodule |
module D2STR_H#
(
parameter integer len = 16 // Symbols to show
)
(
input wire GCLK,
output reg [127:0] str = "????????????????",
input wire [4*len-1:0] d
);
genvar i;
generate
for (i = 0; i < len; i = i + 1) begin: test
always @(posedge GCLK) begin
case (d[4*i+3:4*i])
4'd0: str[8*i+7:8*i] <= "0";
4'd1: str[8*i+7:8*i] <= "1";
4'd2: str[8*i+7:8*i] <= "2";
4'd3: str[8*i+7:8*i] <= "3";
4'd4: str[8*i+7:8*i] <= "4";
4'd5: str[8*i+7:8*i] <= "5";
4'd6: str[8*i+7:8*i] <= "6";
4'd7: str[8*i+7:8*i] <= "7";
4'd8: str[8*i+7:8*i] <= "8";
4'd9: str[8*i+7:8*i] <= "9";
4'd10: str[8*i+7:8*i] <= "A";
4'd11: str[8*i+7:8*i] <= "B";
4'd12: str[8*i+7:8*i] <= "C";
4'd13: str[8*i+7:8*i] <= "D";
4'd14: str[8*i+7:8*i] <= "E";
4'd15: str[8*i+7:8*i] <= "F";
default: str[8*i+7:8*i] <= " ";
endcase
end
end
for (i = len; i < 16; i = i + 1) begin
always @(posedge GCLK) begin
str[8*i+7:8*i] <= " ";
end
end
endgenerate
endmodule |
module D2STR_D#
(
parameter integer len = 4 // Symbols to show
)
(
input wire GCLK,
output reg [127:0] str = "????????????????",
input wire [4*len-1:0] d
);
genvar i;
generate
for (i = 0; i < len; i = i + 1) begin: test
always @(posedge GCLK) begin
case (d[4*i+3:4*i])
4'd0: str[8*i+7:8*i] <= "0";
4'd1: str[8*i+7:8*i] <= "1";
4'd2: str[8*i+7:8*i] <= "2";
4'd3: str[8*i+7:8*i] <= "3";
4'd4: str[8*i+7:8*i] <= "4";
4'd5: str[8*i+7:8*i] <= "5";
4'd6: str[8*i+7:8*i] <= "6";
4'd7: str[8*i+7:8*i] <= "7";
4'd8: str[8*i+7:8*i] <= "8";
4'd9: str[8*i+7:8*i] <= "9";
4'd10: str[8*i+7:8*i] <= " ";
4'd11: str[8*i+7:8*i] <= " ";
4'd12: str[8*i+7:8*i] <= " ";
4'd13: str[8*i+7:8*i] <= " ";
4'd14: str[8*i+7:8*i] <= " ";
4'd15: str[8*i+7:8*i] <= "-";
default: str[8*i+7:8*i] <= " ";
endcase
end
end
for (i = len; i < 16; i = i + 1) begin
always @(posedge GCLK) begin
str[8*i+7:8*i] <= " ";
end
end
endgenerate
endmodule |
module LCD_DISPLAY_CTRL(PATTERN, CLEAR, CALLFORPATTERN, mole16bit, reset, clk);
input clk;
input reset, CLEAR, CALLFORPATTERN;
input [15:0] mole16bit;
output [255:0] PATTERN;
reg [255:0] PATTERN, next_PATTERN;
reg [4:0] counter, next_counter;
wire [255:0] MOLE_UPPER_PATTERN, MOLE_LOWER_PATTERN;
wire [255:0] MALE_UPPER_PATTERN, MALE_LOWER_PATTERN;
wire [255:0] EDGE_UPPER_PATTERN, EDGE_LOWER_PATTERN;
always @(negedge clk or negedge reset) begin
if (!reset) begin
PATTERN <= 256'd0;
counter <= 5'd31;
end else begin
if(!CLEAR)begin
PATTERN <= next_PATTERN;
counter <= next_counter;
end else begin
PATTERN <= 256'd0;
counter <= 5'd31;
end
end
end
always @(*)begin
case(counter)
5'd0 :
if(mole16bit[15]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd2 :
if(mole16bit[15]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd1 :
if(mole16bit[14]==1)next_PATTERN = MALE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd3 :
if(mole16bit[14]==1)next_PATTERN = MALE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd4 :
if(mole16bit[11]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd6 :
if(mole16bit[11]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd5 :
if(mole16bit[3]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd7 :
if(mole16bit[3]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd8 :
if(mole16bit[10]==1)next_PATTERN = MALE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd10:
if(mole16bit[10]==1)next_PATTERN = MALE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd9 :
if(mole16bit[2]==1)next_PATTERN = MALE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd11:
if(mole16bit[2]==1)next_PATTERN = MALE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd12:
if(mole16bit[0]==1)next_PATTERN = MALE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd14:
if(mole16bit[0]==1)next_PATTERN = MALE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd13:
if(mole16bit[1]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd15:
if(mole16bit[1]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd16:
if(mole16bit[13]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd18:
if(mole16bit[13]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd17:
if(mole16bit[12]==1)next_PATTERN = MALE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd19:
if(mole16bit[12]==1)next_PATTERN = MALE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd20:
if(mole16bit[6]==1)next_PATTERN = MALE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd22:
if(mole16bit[6]==1)next_PATTERN = MALE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd21:
if(mole16bit[9]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd23:
if(mole16bit[9]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd24:
if(mole16bit[5]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd26:
if(mole16bit[5]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd25:
if(mole16bit[8]==1)next_PATTERN = MALE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd27:
if(mole16bit[8]==1)next_PATTERN = MALE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd28:
if(mole16bit[4]==1)next_PATTERN = MALE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd30:
if(mole16bit[4]==1)next_PATTERN = MALE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd29:
if(mole16bit[7]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd31:
if(mole16bit[7]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
default:
next_PATTERN = PATTERN;
endcase
end
always @( * )begin
if(CALLFORPATTERN)next_counter = counter + 5'd1;
else next_counter = counter;
end
assign MOLE_UPPER_PATTERN[255:0] = 256'hFF01_0101_0101_0101_8141_2111_0905_0303_0303_0305_0911_2141_8101_0101_0101_01FF;
assign MOLE_LOWER_PATTERN[255:0] = 256'hFF80_8080_8080_8080_8182_8488_90A0_C0C0_C0C0_C0A0_9088_8482_8180_8080_8080_80FF;
assign MALE_UPPER_PATTERN[255:0] = 256'hFF01_0101_0101_0101_81C1_E1F1_0905_FFFF_FFFF_FF05_09F1_E1C1_8101_0101_0101_01FF;
assign MALE_LOWER_PATTERN[255:0] = 256'hFF808080808080808183878F90A0FFFFFFFFFFA0908F878381808080808080FF;
assign EDGE_UPPER_PATTERN[255:0] = 256'hFF01_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_01FF;
assign EDGE_LOWER_PATTERN[255:0] = 256'hFF80_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_80FF;
endmodule |
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