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module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule |
module bsg_cache_to_dram_ctrl_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_ctrl_burst_len_p)
, localparam mask_width_lp=(data_width_p>>3)
, localparam num_req_lp=(block_size_in_words_p/dram_ctrl_burst_len_p)
, localparam lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, localparam lg_dram_ctrl_burst_len_lp=`BSG_SAFE_CLOG2(dram_ctrl_burst_len_p)
)
(
input clk_i
, input reset_i
, input v_i
, input [lg_num_cache_lp-1:0] tag_i
, output logic ready_o
, input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
, output logic app_wdf_wren_o
, output logic [data_width_p-1:0] app_wdf_data_o
, output logic [mask_width_lp-1:0] app_wdf_mask_o
, output logic app_wdf_end_o
, input app_wdf_rdy_i
);
// tag FIFO
//
logic [lg_num_cache_lp-1:0] tag_fifo_data_lo;
logic tag_fifo_v_lo;
logic tag_fifo_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(num_cache_p*num_req_lp)
) tag_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.data_i(tag_i)
,.ready_o(ready_o)
,.v_o(tag_fifo_v_lo)
,.data_o(tag_fifo_data_lo)
,.yumi_i(tag_fifo_yumi_li)
);
// demux
//
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_fifo_data_lo)
,.v_i(tag_fifo_v_lo)
,.o(cache_sel)
);
assign dma_data_yumi_o = cache_sel & dma_data_v_i & {num_cache_p{app_wdf_rdy_i}};
assign app_wdf_wren_o = tag_fifo_v_lo & dma_data_v_i[tag_fifo_data_lo];
// burst counter
//
logic [lg_dram_ctrl_burst_len_lp-1:0] count_lo;
logic up_li;
logic clear_li;
bsg_counter_clear_up #(
.max_val_p(dram_ctrl_burst_len_p-1)
,.init_val_p(0)
) word_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(clear_li)
,.up_i(up_li)
,.count_o(count_lo)
);
logic take_word;
assign take_word = app_wdf_wren_o & app_wdf_rdy_i;
always_comb begin
if (count_lo == dram_ctrl_burst_len_p-1) begin
clear_li = take_word;
up_li = 1'b0;
app_wdf_end_o = take_word;
tag_fifo_yumi_li = take_word;
end
else begin
clear_li = 1'b0;
up_li = take_word;
app_wdf_end_o = 1'b0;
tag_fifo_yumi_li = 1'b0;
end
end
assign app_wdf_data_o = dma_data_i[tag_fifo_data_lo];
assign app_wdf_mask_o = '0; // negative active! we always write the whole word.
endmodule |
module sata_command_layer (
input rst, //reset
input linkup,
input clk,
input data_in_clk,
input data_in_clk_valid,
input data_out_clk,
input data_out_clk_valid,
//User Interface
output command_layer_ready,
output reg sata_busy,
input send_sync_escape,
input [15:0] user_features,
//XXX: New Stb
// input write_data_stb,
// input read_data_stb,
output hard_drive_error,
input execute_command_stb,
input command_layer_reset,
output reg pio_data_ready,
input [7:0] hard_drive_command,
input [15:0] sector_count,
input [47:0] sector_address,
input [31:0] user_din,
input user_din_stb,
output [1:0] user_din_ready,
input [1:0] user_din_activate,
output [23:0] user_din_size,
output user_din_empty,
output [31:0] user_dout,
output user_dout_ready,
input user_dout_activate,
input user_dout_stb,
output [23:0] user_dout_size,
//Transfer Layer Interface
input transport_layer_ready,
output reg sync_escape,
output t_send_command_stb,
output reg t_send_control_stb,
output t_send_data_stb,
input t_dma_activate_stb,
input t_d2h_reg_stb,
input t_pio_setup_stb,
input t_d2h_data_stb,
input t_dma_setup_stb,
input t_set_device_bits_stb,
input t_remote_abort,
input t_xmit_error,
input t_read_crc_error,
//PIO
input t_pio_response,
input t_pio_direction,
input [15:0] t_pio_transfer_count,
input [7:0] t_pio_e_status,
//Host to Device Register Values
output [7:0] h2d_command,
output reg [15:0] h2d_features,
output [7:0] h2d_control,
output [3:0] h2d_port_mult,
output [7:0] h2d_device,
output [47:0] h2d_lba,
output [15:0] h2d_sector_count,
//Device to Host Register Values
input d2h_interrupt,
input d2h_notification,
input [3:0] d2h_port_mult,
input [7:0] d2h_device,
input [47:0] d2h_lba,
input [15:0] d2h_sector_count,
input [7:0] d2h_status,
input [7:0] d2h_error,
output d2h_error_bbk, //Bad Block
output d2h_error_unc, //Uncorrectable Error
output d2h_error_mc, //Removable Media Error
output d2h_error_idnf, //request sector's ID Field could not be found
output d2h_error_mcr, //Removable Media Error
output d2h_error_abrt, //Abort (from invalid command, drive not ready, write fault)
output d2h_error_tk0nf, //Track 0 not found
output d2h_error_amnf, //Data Address Mark is not found after finding correct ID
output d2h_status_bsy, //Set to 1 when drive has access to command block, no other bits are valid when 1
// Set after reset
// Set after soft reset (srst)
// Set immediately after host writes to command register
output d2h_status_drdy, //Drive is ready to accept command
output d2h_status_dwf, //Drive Write Fault
output d2h_status_dsc, //Drive Seek Complete
output d2h_status_drq, //Data Request, Drive is ready to send data to the host
output d2h_status_corr, //Correctable Data bit (an error that was encountered but was corrected)
output d2h_status_idx, //once per disc revolution this bit is set to one then back to zero
output d2h_status_err, //error bit, if this bit is high check the error flags
//command layer data interface
input t_if_strobe,
output [31:0] t_if_data,
output t_if_ready,
input t_if_activate,
output [23:0] t_if_size,
input t_of_strobe,
input [31:0] t_of_data,
output [1:0] t_of_ready,
input [1:0] t_of_activate,
output [23:0] t_of_size,
//Debug
output [3:0] cl_c_state,
output [3:0] cl_w_state
);
//Parameters
parameter IDLE = 4'h0;
parameter PIO_WAIT_FOR_DATA = 4'h1;
parameter PIO_WRITE_DATA = 4'h2;
parameter WAIT_FOR_DMA_ACT = 4'h1;
parameter WAIT_FOR_WRITE_DATA = 4'h2;
parameter SEND_DATA = 4'h3;
//Registers/Wires
reg [3:0] cntrl_state;
reg srst;
reg [7:0] status;
wire idle;
reg cntrl_send_data_stb;
reg send_command_stb;
wire dev_busy;
wire dev_data_req;
//Write State Machine
reg [3:0] write_state;
reg dma_send_data_stb;
reg dma_act_detected_en;
reg enable_tl_data_ready;
//Ping Pong FIFOs
wire [1:0] if_write_ready;
wire [1:0] if_write_activate;
wire [23:0] if_write_size;
wire if_write_strobe;
wire [31:0] if_write_data;
wire if_read_strobe;
wire if_read_ready;
wire if_read_activate;
wire [23:0] if_read_size;
wire [31:0] if_read_data;
wire if_reset;
wire [31:0] of_write_data;
wire [1:0] of_write_ready;
wire [1:0] of_write_activate;
wire [23:0] of_read_size;
wire of_write_strobe;
wire out_fifo_starved;
wire of_read_ready;
wire [31:0] of_read_data;
wire of_read_activate;
wire [23:0] of_write_size;
wire of_read_strobe;
wire of_reset;
//ping pong FIFO
//Input FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
) fifo_in (
.reset (if_reset ), //XXX: Veify that new PPFIFO doesn't need an external reset
//write side
//XXX: This can be different clocks
.write_clock (data_in_clk ),
.write_data (if_write_data ),
.write_ready (if_write_ready ),
.write_activate (if_write_activate ),
.write_fifo_size (if_write_size ),
.write_strobe (if_write_strobe ),
//.starved (if_starved ),
.starved (user_din_empty ),
//read side
//XXX: This can be different clocks
.read_clock (clk ),
.read_strobe (if_read_strobe ),
.read_ready (if_read_ready ),
.read_activate (if_read_activate ),
.read_count (if_read_size ),
.read_data (if_read_data ),
.inactive ( )
);
//Output FIFO
ppfifo # (
.DATA_WIDTH (`DATA_SIZE ),
.ADDRESS_WIDTH (`FIFO_ADDRESS_WIDTH )
) fifo_out (
.reset (of_reset ),
//.reset (0),
//write side
//XXX: This can be different clocks
.write_clock (clk ),
.write_data (of_write_data ),
.write_ready (of_write_ready ),
.write_activate (of_write_activate ),
.write_fifo_size (of_write_size ),
.write_strobe (of_write_strobe ),
//.starved (out_fifo_starved ),
.starved ( ),
//read side
//XXX: This can be different clocks
.read_clock (data_out_clk ),
.read_strobe (of_read_strobe ),
.read_ready (of_read_ready ),
.read_activate (of_read_activate ),
.read_count (of_read_size ),
.read_data (of_read_data ),
.inactive ( )
);
//Asynchronous Logic
//Attach output of Input FIFO to TL
assign t_if_ready = if_read_ready && enable_tl_data_ready;
assign t_if_size = if_read_size;
assign t_if_data = if_read_data;
assign if_read_activate = t_if_activate;
assign if_read_strobe = t_if_strobe;
//Attach input of output FIFO to TL
assign t_of_ready = of_write_ready;
//assign t_of_size = of_write_size;
assign t_of_size = 24'h00800;
assign of_write_data = t_of_data;
assign of_write_activate = t_of_activate;
assign of_write_strobe = t_of_strobe;
assign of_reset = (rst && data_out_clk_valid);
assign if_reset = (rst && data_in_clk_valid);
assign if_write_data = user_din;
assign if_write_strobe = user_din_stb;
assign user_din_ready = if_write_ready;
assign if_write_activate = user_din_activate;
assign user_din_size = if_write_size;
assign user_dout = of_read_data;
assign user_dout_ready = of_read_ready;
assign of_read_activate = user_dout_activate;
assign user_dout_size = of_read_size;
assign of_read_strobe = user_dout_stb;
assign d2h_status_bsy = d2h_status[7];
assign d2h_status_drdy = d2h_status[6];
assign d2h_status_dwf = d2h_status[5];
assign d2h_status_dsc = d2h_status[4];
assign d2h_status_drq = d2h_status[3];
assign d2h_status_corr = d2h_status[2];
assign d2h_status_idx = d2h_status[1];
assign d2h_status_err = d2h_status[0];
assign d2h_error_bbk = d2h_error[7];
assign d2h_error_unc = d2h_error[6];
assign d2h_error_mc = d2h_error[5];
assign d2h_error_idnf = d2h_error[4];
assign d2h_error_mcr = d2h_error[3];
assign d2h_error_abrt = d2h_error[2];
assign d2h_error_tk0nf = d2h_error[1];
assign d2h_error_amnf = d2h_error[0];
//Strobes
//assign t_send_command_stb = read_data_stb || write_data_stb || execute_command_stb;
assign t_send_command_stb = execute_command_stb;
assign t_send_data_stb = dma_send_data_stb ||cntrl_send_data_stb;
//IDLE
assign idle = (cntrl_state == IDLE) &&
(write_state == IDLE) &&
transport_layer_ready;
assign command_layer_ready = idle;
assign h2d_command = hard_drive_command;
assign h2d_sector_count = sector_count;
assign h2d_lba = sector_address;
//XXX: The individual bits should be controlled directly
assign h2d_control = {5'h00, srst, 2'b00};
//XXX: This should be controlled from a higher level
assign h2d_port_mult = 4'h0;
//XXX: This should be controlled from a higher level
assign h2d_device = `D2H_REG_DEVICE;
assign dev_busy = status[`STATUS_BUSY_BIT];
assign dev_data_req = status[`STATUS_DRQ_BIT];
assign hard_drive_error = status[`STATUS_ERR_BIT];
assign cl_c_state = cntrl_state;
assign cl_w_state = write_state;
//Synchronous Logic
//Control State Machine
always @ (posedge clk) begin
if (rst || (!linkup)) begin
cntrl_state <= IDLE;
h2d_features <= `D2H_REG_FEATURES;
srst <= 0;
//Strobes
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
status <= 0;
sata_busy <= 0;
sync_escape <= 0;
end
else begin
t_send_control_stb <= 0;
cntrl_send_data_stb <= 0;
pio_data_ready <= 0;
//Reset Count
if (t_d2h_reg_stb) begin
//Receiving a register strobe from the device
sata_busy <= 0;
h2d_features <= `D2H_REG_FEATURES;
end
/*
if (t_send_command_stb || t_send_control_stb) begin
sata_busy <= 1;
end
*/
if (execute_command_stb) begin
h2d_features <= user_features;
sata_busy <= 1;
end
case (cntrl_state)
IDLE: begin
//Soft Reset will break out of any flow
if (command_layer_reset && !srst) begin
srst <= 1;
t_send_control_stb <= 1;
end
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//User Initiated commands
if (!command_layer_reset && srst) begin
srst <= 0;
t_send_control_stb <= 1;
end
end
//Device Initiated Transfers
if(t_pio_setup_stb) begin
if (t_pio_direction) begin
//Read from device
cntrl_state <= PIO_WAIT_FOR_DATA;
end
else begin
//Write to device
cntrl_state <= PIO_WRITE_DATA;
end
end
if (t_set_device_bits_stb) begin
status <= d2h_status;
//status register was updated
end
if (t_d2h_reg_stb) begin
status <= d2h_status;
end
end
PIO_WAIT_FOR_DATA: begin
if (t_d2h_data_stb) begin
//the next peice of data is related to the PIO
pio_data_ready <= 1;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
PIO_WRITE_DATA: begin
if (if_read_activate) begin
cntrl_send_data_stb <= 0;
cntrl_state <= IDLE;
status <= t_pio_e_status;
end
end
default: begin
cntrl_state <= IDLE;
end
endcase
if (send_sync_escape) begin
cntrl_state <= IDLE;
sync_escape <= 1;
sata_busy <= 0;
end
end
end
//Write State Machine
always @ (posedge clk) begin
if (rst || !linkup) begin
write_state <= IDLE;
dma_send_data_stb <= 0;
enable_tl_data_ready <= 0;
dma_act_detected_en <= 0;
end
else begin
dma_send_data_stb <= 0;
if (t_dma_activate_stb) begin
//Set an enable signal instead of a strobe so that there is no chance of missing this signal
dma_act_detected_en <= 1;
end
case (write_state)
IDLE: begin
enable_tl_data_ready <= 0;
if (idle) begin
//The only way to transition to another state is if CL is IDLE
//if (write_data_stb) begin
if (dma_act_detected_en) begin
//send a request to write data
write_state <= WAIT_FOR_DMA_ACT;
end
end
end
WAIT_FOR_DMA_ACT: begin
if (dma_act_detected_en) begin
dma_act_detected_en <= 0;
enable_tl_data_ready <= 1;
write_state <= WAIT_FOR_WRITE_DATA;
end
end
WAIT_FOR_WRITE_DATA: begin
if (if_read_activate) begin
enable_tl_data_ready <= 0;
write_state <= SEND_DATA;
end
end
SEND_DATA: begin
if (transport_layer_ready) begin
//Send the Data FIS
dma_send_data_stb <= 1;
dma_act_detected_en <= 0;
write_state <= IDLE;
end
end
default: begin
write_state <= IDLE;
end
endcase
//if (command_layer_reset || !reset_timeout) begin
if (command_layer_reset) begin
//Break out of the normal flow and return to IDLE
write_state <= IDLE;
end
if (t_d2h_reg_stb) begin
//Whenever I read a register transfer from the device I need to go back to IDLE
write_state <= IDLE;
end
if (send_sync_escape) begin
write_state <= IDLE;
end
end
end
endmodule |
module sky130_fd_sc_hs__and2b (
VPWR,
VGND,
X ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
// Local signals
wire X not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule |
module
$monitor ("pc: %b, pr: %b, s: %b, data: %b", w_bus_addr, w_bus_pr_out, w_sr_out, w_bus_data);
#2 r_reset = 1'b0; // wait 2s, reset all circuit elements
end
always #1 begin // every 1s:
r_clock = ~w_clock; // invert clock signal
if (w_hlt) begin
$display ("HLT call: Halting system.");
$finish; // halt simulation if hlt called
end
end
endmodule |
module sky130_fd_sc_ls__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module altera_mem_if_ddr3_phy_0001_qsys_sequencer (
input wire clock_clk, // clock.clk
input wire reset_reset_n, // reset.reset_n
input wire reset_n_scc_clk, // scc.reset_n_scc_clk
input wire scc_clk, // .scc_clk
output wire scc_data, // .scc_data
output wire [1:0] scc_dqs_ena, // .scc_dqs_ena
output wire [1:0] scc_dqs_io_ena, // .scc_dqs_io_ena
output wire [15:0] scc_dq_ena, // .scc_dq_ena
output wire [1:0] scc_dm_ena, // .scc_dm_ena
output wire scc_upd, // .scc_upd
input wire [1:0] capture_strobe_tracking, // .capture_strobe_tracking
input wire phy_clk, // phy.phy_clk
input wire phy_reset_n, // .phy_reset_n
output wire [4:0] phy_read_latency_counter, // .phy_read_latency_counter
output wire [1:0] phy_read_increment_vfifo_fr, // .phy_read_increment_vfifo_fr
output wire [1:0] phy_read_increment_vfifo_hr, // .phy_read_increment_vfifo_hr
output wire [1:0] phy_read_increment_vfifo_qr, // .phy_read_increment_vfifo_qr
output wire phy_reset_mem_stable, // .phy_reset_mem_stable
output wire [5:0] phy_afi_wlat, // .phy_afi_wlat
output wire [5:0] phy_afi_rlat, // .phy_afi_rlat
output wire phy_mux_sel, // .phy_mux_sel
output wire phy_cal_success, // .phy_cal_success
output wire phy_cal_fail, // .phy_cal_fail
output wire [31:0] phy_cal_debug_info, // .phy_cal_debug_info
output wire [1:0] phy_read_fifo_reset, // .phy_read_fifo_reset
output wire [1:0] phy_vfifo_rd_en_override, // .phy_vfifo_rd_en_override
input wire [7:0] calib_skip_steps, // calib.calib_skip_steps
input wire afi_clk, // afi.afi_clk
input wire afi_reset_n, // .afi_reset_n
output wire [25:0] afi_address, // .afi_address
output wire [5:0] afi_bank, // .afi_bank
output wire [1:0] afi_cs_n, // .afi_cs_n
output wire [1:0] afi_cke, // .afi_cke
output wire [1:0] afi_odt, // .afi_odt
output wire [1:0] afi_ras_n, // .afi_ras_n
output wire [1:0] afi_cas_n, // .afi_cas_n
output wire [1:0] afi_we_n, // .afi_we_n
output wire [3:0] afi_dqs_en, // .afi_dqs_en
output wire [1:0] afi_mem_reset_n, // .afi_mem_reset_n
output wire [63:0] afi_wdata, // .afi_wdata
output wire [3:0] afi_wdata_valid, // .afi_wdata_valid
output wire [7:0] afi_dm, // .afi_dm
output wire afi_rdata_en, // .afi_rdata_en
output wire afi_rdata_en_full, // .afi_rdata_en_full
input wire [63:0] afi_rdata, // .afi_rdata
input wire afi_rdata_valid // .afi_rdata_valid
);
wire cpu_inst_instruction_master_waitrequest; // cpu_inst_instruction_master_translator:av_waitrequest -> cpu_inst:i_waitrequest
wire [16:0] cpu_inst_instruction_master_address; // cpu_inst:i_address -> cpu_inst_instruction_master_translator:av_address
wire cpu_inst_instruction_master_read; // cpu_inst:i_read -> cpu_inst_instruction_master_translator:av_read
wire [31:0] cpu_inst_instruction_master_readdata; // cpu_inst_instruction_master_translator:av_readdata -> cpu_inst:i_readdata
wire cpu_inst_data_master_waitrequest; // cpu_inst_data_master_translator:av_waitrequest -> cpu_inst:d_waitrequest
wire [31:0] cpu_inst_data_master_writedata; // cpu_inst:d_writedata -> cpu_inst_data_master_translator:av_writedata
wire [18:0] cpu_inst_data_master_address; // cpu_inst:d_address -> cpu_inst_data_master_translator:av_address
wire cpu_inst_data_master_write; // cpu_inst:d_write -> cpu_inst_data_master_translator:av_write
wire cpu_inst_data_master_read; // cpu_inst:d_read -> cpu_inst_data_master_translator:av_read
wire [31:0] cpu_inst_data_master_readdata; // cpu_inst_data_master_translator:av_readdata -> cpu_inst:d_readdata
wire cpu_inst_data_master_debugaccess; // cpu_inst:jtag_debug_module_debugaccess_to_roms -> cpu_inst_data_master_translator:av_debugaccess
wire [3:0] cpu_inst_data_master_byteenable; // cpu_inst:d_byteenable -> cpu_inst_data_master_translator:av_byteenable
wire [31:0] sequencer_rom_s1_translator_avalon_anti_slave_0_writedata; // sequencer_rom_s1_translator:av_writedata -> sequencer_rom:writedata
wire [11:0] sequencer_rom_s1_translator_avalon_anti_slave_0_address; // sequencer_rom_s1_translator:av_address -> sequencer_rom:address
wire sequencer_rom_s1_translator_avalon_anti_slave_0_chipselect; // sequencer_rom_s1_translator:av_chipselect -> sequencer_rom:chipselect
wire sequencer_rom_s1_translator_avalon_anti_slave_0_clken; // sequencer_rom_s1_translator:av_clken -> sequencer_rom:clken
wire sequencer_rom_s1_translator_avalon_anti_slave_0_write; // sequencer_rom_s1_translator:av_write -> sequencer_rom:write
wire [31:0] sequencer_rom_s1_translator_avalon_anti_slave_0_readdata; // sequencer_rom:readdata -> sequencer_rom_s1_translator:av_readdata
wire sequencer_rom_s1_translator_avalon_anti_slave_0_debugaccess; // sequencer_rom_s1_translator:av_debugaccess -> sequencer_rom:debugaccess
wire [3:0] sequencer_rom_s1_translator_avalon_anti_slave_0_byteenable; // sequencer_rom_s1_translator:av_byteenable -> sequencer_rom:byteenable
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // cpu_inst_jtag_debug_module_translator:av_writedata -> cpu_inst:jtag_debug_module_writedata
wire [8:0] cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_address; // cpu_inst_jtag_debug_module_translator:av_address -> cpu_inst:jtag_debug_module_address
wire cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // cpu_inst_jtag_debug_module_translator:av_chipselect -> cpu_inst:jtag_debug_module_select
wire cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_write; // cpu_inst_jtag_debug_module_translator:av_write -> cpu_inst:jtag_debug_module_write
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // cpu_inst:jtag_debug_module_readdata -> cpu_inst_jtag_debug_module_translator:av_readdata
wire cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // cpu_inst_jtag_debug_module_translator:av_begintransfer -> cpu_inst:jtag_debug_module_begintransfer
wire cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // cpu_inst_jtag_debug_module_translator:av_debugaccess -> cpu_inst:jtag_debug_module_debugaccess
wire [3:0] cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // cpu_inst_jtag_debug_module_translator:av_byteenable -> cpu_inst:jtag_debug_module_byteenable
wire [31:0] sequencer_ram_s1_translator_avalon_anti_slave_0_writedata; // sequencer_ram_s1_translator:av_writedata -> sequencer_ram:writedata
wire [8:0] sequencer_ram_s1_translator_avalon_anti_slave_0_address; // sequencer_ram_s1_translator:av_address -> sequencer_ram:address
wire sequencer_ram_s1_translator_avalon_anti_slave_0_chipselect; // sequencer_ram_s1_translator:av_chipselect -> sequencer_ram:chipselect
wire sequencer_ram_s1_translator_avalon_anti_slave_0_clken; // sequencer_ram_s1_translator:av_clken -> sequencer_ram:clken
wire sequencer_ram_s1_translator_avalon_anti_slave_0_write; // sequencer_ram_s1_translator:av_write -> sequencer_ram:write
wire [31:0] sequencer_ram_s1_translator_avalon_anti_slave_0_readdata; // sequencer_ram:readdata -> sequencer_ram_s1_translator:av_readdata
wire [3:0] sequencer_ram_s1_translator_avalon_anti_slave_0_byteenable; // sequencer_ram_s1_translator:av_byteenable -> sequencer_ram:byteenable
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_rw_mgr_inst:avl_waitrequest -> sequencer_rw_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_rw_mgr_inst_avl_translator:av_writedata -> sequencer_rw_mgr_inst:avl_writedata
wire [12:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_rw_mgr_inst_avl_translator:av_address -> sequencer_rw_mgr_inst:avl_address
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_rw_mgr_inst_avl_translator:av_write -> sequencer_rw_mgr_inst:avl_write
wire sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_rw_mgr_inst_avl_translator:av_read -> sequencer_rw_mgr_inst:avl_read
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_rw_mgr_inst:avl_readdata -> sequencer_rw_mgr_inst_avl_translator:av_readdata
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_phy_mgr_inst:avl_waitrequest -> sequencer_phy_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_phy_mgr_inst_avl_translator:av_writedata -> sequencer_phy_mgr_inst:avl_writedata
wire [12:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_phy_mgr_inst_avl_translator:av_address -> sequencer_phy_mgr_inst:avl_address
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_phy_mgr_inst_avl_translator:av_write -> sequencer_phy_mgr_inst:avl_write
wire sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_phy_mgr_inst_avl_translator:av_read -> sequencer_phy_mgr_inst:avl_read
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_phy_mgr_inst:avl_readdata -> sequencer_phy_mgr_inst_avl_translator:av_readdata
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_data_mgr_inst:avl_waitrequest -> sequencer_data_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_data_mgr_inst_avl_translator:av_writedata -> sequencer_data_mgr_inst:avl_writedata
wire [12:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_data_mgr_inst_avl_translator:av_address -> sequencer_data_mgr_inst:avl_address
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_data_mgr_inst_avl_translator:av_write -> sequencer_data_mgr_inst:avl_write
wire sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_data_mgr_inst_avl_translator:av_read -> sequencer_data_mgr_inst:avl_read
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_data_mgr_inst:avl_readdata -> sequencer_data_mgr_inst_avl_translator:av_readdata
wire sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_ptr_mgr_inst:avl_waitrequest -> sequencer_ptr_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_ptr_mgr_inst_avl_translator:av_writedata -> sequencer_ptr_mgr_inst:avl_writedata
wire [12:0] sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_ptr_mgr_inst_avl_translator:av_address -> sequencer_ptr_mgr_inst:avl_address
wire sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_ptr_mgr_inst_avl_translator:av_write -> sequencer_ptr_mgr_inst:avl_write
wire sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_ptr_mgr_inst_avl_translator:av_read -> sequencer_ptr_mgr_inst:avl_read
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_ptr_mgr_inst:avl_readdata -> sequencer_ptr_mgr_inst_avl_translator:av_readdata
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest; // sequencer_scc_mgr_inst:avl_waitrequest -> sequencer_scc_mgr_inst_avl_translator:av_waitrequest
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata; // sequencer_scc_mgr_inst_avl_translator:av_writedata -> sequencer_scc_mgr_inst:avl_writedata
wire [12:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address; // sequencer_scc_mgr_inst_avl_translator:av_address -> sequencer_scc_mgr_inst:avl_address
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write; // sequencer_scc_mgr_inst_avl_translator:av_write -> sequencer_scc_mgr_inst:avl_write
wire sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read; // sequencer_scc_mgr_inst_avl_translator:av_read -> sequencer_scc_mgr_inst:avl_read
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata; // sequencer_scc_mgr_inst:avl_readdata -> sequencer_scc_mgr_inst_avl_translator:av_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [18:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address; // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_lock; // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_write; // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_read; // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
wire cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
wire [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount; // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata; // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [18:0] cpu_inst_data_master_translator_avalon_universal_master_0_address; // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_inst_data_master_translator_avalon_universal_master_0_lock; // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_inst_data_master_translator_avalon_universal_master_0_write; // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_inst_data_master_translator_avalon_universal_master_0_read; // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
wire cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable; // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_rom_s1_translator:uav_waitrequest -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_rom_s1_translator:uav_burstcount
wire [31:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_rom_s1_translator:uav_writedata
wire [18:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_rom_s1_translator:uav_address
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_rom_s1_translator:uav_write
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_rom_s1_translator:uav_lock
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_rom_s1_translator:uav_read
wire [31:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_rom_s1_translator:uav_readdata -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_rom_s1_translator:uav_readdatavalid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_rom_s1_translator:uav_debugaccess
wire [3:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_rom_s1_translator:uav_byteenable
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // cpu_inst_jtag_debug_module_translator:uav_waitrequest -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> cpu_inst_jtag_debug_module_translator:uav_burstcount
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> cpu_inst_jtag_debug_module_translator:uav_writedata
wire [18:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> cpu_inst_jtag_debug_module_translator:uav_address
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> cpu_inst_jtag_debug_module_translator:uav_write
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> cpu_inst_jtag_debug_module_translator:uav_lock
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> cpu_inst_jtag_debug_module_translator:uav_read
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // cpu_inst_jtag_debug_module_translator:uav_readdata -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // cpu_inst_jtag_debug_module_translator:uav_readdatavalid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> cpu_inst_jtag_debug_module_translator:uav_debugaccess
wire [3:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> cpu_inst_jtag_debug_module_translator:uav_byteenable
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_ram_s1_translator:uav_waitrequest -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_ram_s1_translator:uav_burstcount
wire [31:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_ram_s1_translator:uav_writedata
wire [18:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_ram_s1_translator:uav_address
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_ram_s1_translator:uav_write
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_ram_s1_translator:uav_lock
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_ram_s1_translator:uav_read
wire [31:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_ram_s1_translator:uav_readdata -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_ram_s1_translator:uav_readdatavalid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_ram_s1_translator:uav_debugaccess
wire [3:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_ram_s1_translator:uav_byteenable
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_data_mgr_inst_avl_translator:uav_waitrequest -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_data_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_data_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_data_mgr_inst_avl_translator:uav_address
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_data_mgr_inst_avl_translator:uav_write
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_data_mgr_inst_avl_translator:uav_lock
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_data_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_data_mgr_inst_avl_translator:uav_readdata -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_data_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_data_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_data_mgr_inst_avl_translator:uav_byteenable
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_ptr_mgr_inst_avl_translator:uav_waitrequest -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_ptr_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_ptr_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_ptr_mgr_inst_avl_translator:uav_address
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_ptr_mgr_inst_avl_translator:uav_write
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_ptr_mgr_inst_avl_translator:uav_lock
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_ptr_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_ptr_mgr_inst_avl_translator:uav_readdata -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_ptr_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_ptr_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_ptr_mgr_inst_avl_translator:uav_byteenable
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
wire [18:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata; // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
wire [3:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [76:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [76:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [75:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [75:0] cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [75:0] sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [75:0] cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [75:0] sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [75:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [75:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [75:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
wire [75:0] sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
wire sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
wire [75:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
wire sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [75:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [7:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [75:0] limiter_rsp_src_data; // limiter:rsp_src_data -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [75:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [7:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [75:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [7:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_001_rsp_src_ready; // cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cpu_inst:reset_n, cpu_inst_data_master_translator:reset, cpu_inst_data_master_translator_avalon_universal_master_0_agent:reset, cpu_inst_instruction_master_translator:reset, cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:reset, cpu_inst_jtag_debug_module_translator:reset, cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, irq_mapper:reset, limiter:reset, limiter_001:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sequencer_data_mgr_inst:avl_reset_n, sequencer_data_mgr_inst_avl_translator:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_phy_mgr_inst:avl_reset_n, sequencer_phy_mgr_inst_avl_translator:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_ptr_mgr_inst:avl_reset_n, sequencer_ptr_mgr_inst_avl_translator:reset, sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_ram:reset, sequencer_ram_s1_translator:reset, sequencer_ram_s1_translator_avalon_universal_slave_0_agent:reset, sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_rom:reset, sequencer_rom_s1_translator:reset, sequencer_rom_s1_translator_avalon_universal_slave_0_agent:reset, sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_rw_mgr_inst:avl_reset_n, sequencer_rw_mgr_inst_avl_translator:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_scc_mgr_inst:avl_reset_n, sequencer_scc_mgr_inst_avl_translator:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [75:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [7:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [75:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [7:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [75:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [7:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [75:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [7:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [75:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [7:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [75:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [7:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [75:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [7:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [75:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [7:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [75:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data
wire [7:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [75:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data
wire [7:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
wire [75:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
wire [7:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
wire [75:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
wire [7:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
wire [75:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
wire [7:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
wire [75:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
wire [7:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [75:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [7:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [75:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [7:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [75:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [7:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [75:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
wire [7:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // sequencer_rom_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [75:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [7:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [75:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [7:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_001_src_ready; // cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [75:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [7:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_demux_001_src2_ready; // sequencer_ram_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [75:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [7:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_demux_001_src3_ready; // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [75:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [7:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_demux_001_src4_ready; // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [75:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [7:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_001_src5_ready; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [75:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [7:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire cmd_xbar_demux_001_src6_ready; // sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
wire [75:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
wire [7:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
wire cmd_xbar_demux_001_src7_ready; // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
wire [75:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
wire [7:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
wire [7:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
wire [7:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
wire [31:0] cpu_inst_d_irq_irq; // irq_mapper:sender_irq -> cpu_inst:d_irq
sequencer_scc_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_READ_DQS_WIDTH (2),
.MEM_WRITE_DQS_WIDTH (2),
.MEM_DQ_WIDTH (16),
.MEM_DM_WIDTH (2),
.DLL_DELAY_CHAIN_LENGTH (8),
.FAMILY ("STRATIXIV"),
.DQS_TRK_ENABLED (0)
) sequencer_scc_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.reset_n_scc_clk (reset_n_scc_clk), // scc.reset_n_scc_clk
.scc_clk (scc_clk), // .scc_clk
.scc_data (scc_data), // .scc_data
.scc_dqs_ena (scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (scc_dm_ena), // .scc_dm_ena
.scc_upd (scc_upd), // .scc_upd
.capture_strobe_tracking (capture_strobe_tracking) // .capture_strobe_tracking
);
sequencer_ptr_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13)
) sequencer_ptr_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest) // .waitrequest
);
sequencer_phy_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MAX_LATENCY_COUNT_WIDTH (5),
.MEM_READ_DQS_WIDTH (2),
.AFI_DEBUG_INFO_WIDTH (32),
.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
.AFI_MAX_READ_LATENCY_COUNT_WIDTH (6),
.CALIB_VFIFO_OFFSET (14),
.CALIB_LFIFO_OFFSET (5),
.CALIB_SKIP_STEPS_WIDTH (8),
.READ_VALID_FIFO_SIZE (16),
.MEM_T_WL (5),
.MEM_T_RL (7),
.CTL_REGDIMM_ENABLED (0)
) sequencer_phy_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.phy_clk (phy_clk), // phy.phy_clk
.phy_reset_n (phy_reset_n), // .phy_reset_n
.phy_read_latency_counter (phy_read_latency_counter), // .phy_read_latency_counter
.phy_read_increment_vfifo_fr (phy_read_increment_vfifo_fr), // .phy_read_increment_vfifo_fr
.phy_read_increment_vfifo_hr (phy_read_increment_vfifo_hr), // .phy_read_increment_vfifo_hr
.phy_read_increment_vfifo_qr (phy_read_increment_vfifo_qr), // .phy_read_increment_vfifo_qr
.phy_reset_mem_stable (phy_reset_mem_stable), // .phy_reset_mem_stable
.phy_afi_wlat (phy_afi_wlat), // .phy_afi_wlat
.phy_afi_rlat (phy_afi_rlat), // .phy_afi_rlat
.phy_mux_sel (phy_mux_sel), // .phy_mux_sel
.phy_cal_success (phy_cal_success), // .phy_cal_success
.phy_cal_fail (phy_cal_fail), // .phy_cal_fail
.phy_cal_debug_info (phy_cal_debug_info), // .phy_cal_debug_info
.phy_read_fifo_reset (phy_read_fifo_reset), // .phy_read_fifo_reset
.phy_vfifo_rd_en_override (phy_vfifo_rd_en_override), // .phy_vfifo_rd_en_override
.calib_skip_steps (calib_skip_steps) // calib.calib_skip_steps
);
sequencer_data_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MAX_LATENCY_COUNT_WIDTH (5),
.MEM_READ_DQS_WIDTH (2),
.AFI_DEBUG_INFO_WIDTH (32),
.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
.AFI_MAX_READ_LATENCY_COUNT_WIDTH (6),
.CALIB_VFIFO_OFFSET (14),
.CALIB_LFIFO_OFFSET (5),
.CALIB_SKIP_STEPS_WIDTH (8),
.READ_VALID_FIFO_SIZE (16),
.MEM_T_WL (5),
.MEM_T_RL (7),
.CTL_REGDIMM_ENABLED (0),
.SEQUENCER_VERSION (0)
) sequencer_data_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest) // .waitrequest
);
rw_manager_ddr3 #(
.RATE ("Half"),
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_ADDRESS_WIDTH (13),
.MEM_CONTROL_WIDTH (1),
.MEM_DQ_WIDTH (16),
.MEM_DM_WIDTH (2),
.MEM_NUMBER_OF_RANKS (1),
.MEM_CLK_EN_WIDTH (1),
.MEM_BANK_WIDTH (3),
.MEM_ODT_WIDTH (1),
.MEM_CHIP_SELECT_WIDTH (1),
.MEM_READ_DQS_WIDTH (2),
.MEM_WRITE_DQS_WIDTH (2),
.AFI_RATIO (2),
.AC_BUS_WIDTH (27),
.HCX_COMPAT_MODE (0),
.DEVICE_FAMILY ("STRATIXIV"),
.AC_ROM_INIT_FILE_NAME ("altera_mem_if_ddr3_phy_0001_AC_ROM.hex"),
.INST_ROM_INIT_FILE_NAME ("altera_mem_if_ddr3_phy_0001_inst_ROM.hex")
) sequencer_rw_mgr_inst (
.avl_clk (clock_clk), // avl_clk.clk
.avl_reset_n (~rst_controller_reset_out_reset), // avl_reset.reset_n
.avl_address (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avl.address
.avl_write (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.avl_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_read (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.avl_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.afi_clk (afi_clk), // afi.afi_clk
.afi_reset_n (afi_reset_n), // .afi_reset_n
.afi_address (afi_address), // .afi_address
.afi_bank (afi_bank), // .afi_bank
.afi_cs_n (afi_cs_n), // .afi_cs_n
.afi_cke (afi_cke), // .afi_cke
.afi_odt (afi_odt), // .afi_odt
.afi_ras_n (afi_ras_n), // .afi_ras_n
.afi_cas_n (afi_cas_n), // .afi_cas_n
.afi_we_n (afi_we_n), // .afi_we_n
.afi_dqs_en (afi_dqs_en), // .afi_dqs_en
.afi_mem_reset_n (afi_mem_reset_n), // .afi_mem_reset_n
.afi_wdata (afi_wdata), // .afi_wdata
.afi_wdata_valid (afi_wdata_valid), // .afi_wdata_valid
.afi_dm (afi_dm), // .afi_dm
.afi_rdata_en (afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata (afi_rdata), // .afi_rdata
.afi_rdata_valid (afi_rdata_valid), // .afi_rdata_valid
.csr_clk (), // csr.csr_clk
.csr_ena (), // .csr_ena
.csr_dout_phy (), // .csr_dout_phy
.csr_dout () // .csr_dout
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_ram sequencer_ram (
.clk (clock_clk), // clk1.clk
.address (sequencer_ram_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (sequencer_ram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (sequencer_ram_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (sequencer_ram_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (sequencer_ram_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (sequencer_ram_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (sequencer_ram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset) // reset1.reset
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_rom sequencer_rom (
.clk (clock_clk), // clk1.clk
.address (sequencer_rom_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (sequencer_rom_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (sequencer_rom_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (sequencer_rom_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (sequencer_rom_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (sequencer_rom_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.debugaccess (sequencer_rom_s1_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.byteenable (sequencer_rom_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset) // reset1.reset
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst cpu_inst (
.clk (clock_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (cpu_inst_data_master_address), // data_master.address
.d_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.d_read (cpu_inst_data_master_read), // .read
.d_readdata (cpu_inst_data_master_readdata), // .readdata
.d_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.d_write (cpu_inst_data_master_write), // .write
.d_writedata (cpu_inst_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_inst_data_master_debugaccess), // .debugaccess
.i_address (cpu_inst_instruction_master_address), // instruction_master.address
.i_read (cpu_inst_instruction_master_read), // .read
.i_readdata (cpu_inst_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_inst_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (), // jtag_debug_module_reset.reset
.jtag_debug_module_address (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_begintransfer (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.jtag_debug_module_byteenable (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_readdata (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_select (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.jtag_debug_module_write (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (17),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_inst_instruction_master_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_inst_instruction_master_read), // .read
.av_readdata (cpu_inst_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_inst_data_master_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_inst_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.av_read (cpu_inst_data_master_read), // .read
.av_readdata (cpu_inst_data_master_readdata), // .readdata
.av_write (cpu_inst_data_master_write), // .write
.av_writedata (cpu_inst_data_master_writedata), // .writedata
.av_debugaccess (cpu_inst_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_rom_s1_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_rom_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_rom_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (sequencer_rom_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_rom_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sequencer_rom_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (sequencer_rom_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (sequencer_rom_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_debugaccess (sequencer_rom_s1_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_inst_jtag_debug_module_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_readdata (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.av_byteenable (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_debugaccess (cpu_inst_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_ram_s1_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_ram_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_ram_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (sequencer_ram_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_ram_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sequencer_ram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (sequencer_ram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (sequencer_ram_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_rw_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_phy_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_data_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_ptr_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_ptr_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sequencer_scc_mgr_inst_avl_translator (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.PKT_BEGIN_BURST (66),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.ST_DATA_W (76),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3)
) cpu_inst_instruction_master_translator_avalon_universal_master_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_inst_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.PKT_BEGIN_BURST (66),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.ST_DATA_W (76),
.ST_CHANNEL_W (8),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (7)
) cpu_inst_data_master_translator_avalon_universal_master_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_inst_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_inst_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_inst_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_inst_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_inst_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_inst_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_001_rsp_src_valid), // rp.valid
.rp_data (limiter_001_rsp_src_data), // .data
.rp_channel (limiter_001_rsp_src_channel), // .channel
.rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_001_rsp_src_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_rom_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_001_src_valid), // .valid
.cp_data (cmd_xbar_mux_001_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_001_src_channel), // .channel
.rf_sink_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_ram_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src2_valid), // .valid
.cp_data (cmd_xbar_demux_001_src2_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src2_channel), // .channel
.rf_sink_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src3_valid), // .valid
.cp_data (cmd_xbar_demux_001_src3_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src3_channel), // .channel
.rf_sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
.cp_data (cmd_xbar_demux_001_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
.rf_sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
.cp_data (cmd_xbar_demux_001_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
.rf_sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src6_valid), // .valid
.cp_data (cmd_xbar_demux_001_src6_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src6_channel), // .channel
.rf_sink_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (66),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_TRANS_LOCK (59),
.PKT_SRC_ID_H (70),
.PKT_SRC_ID_L (67),
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_BURSTWRAP_H (65),
.PKT_BURSTWRAP_L (63),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (75),
.ST_CHANNEL_W (8),
.ST_DATA_W (76),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
.cp_data (cmd_xbar_demux_001_src7_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
.rf_sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (77),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_addr_router addr_router (
.sink_ready (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_addr_router_001 addr_router_001 (
.sink_ready (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router id_router (
.sink_ready (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_rom_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router id_router_001 (
.sink_ready (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_inst_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_002 (
.sink_ready (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_ram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_003 (
.sink_ready (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_004 (
.sink_ready (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_005 (
.sink_ready (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_006 (
.sink_ready (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_ptr_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_006_src_ready), // src.ready
.src_valid (id_router_006_src_valid), // .valid
.src_data (id_router_006_src_data), // .data
.src_channel (id_router_006_src_channel), // .channel
.src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_id_router_002 id_router_007 (
.sink_ready (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_007_src_ready), // src.ready
.src_valid (id_router_007_src_valid), // .valid
.src_data (id_router_007_src_data), // .data
.src_channel (id_router_007_src_channel), // .channel
.src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_TRANS_POSTED (56),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (76),
.ST_CHANNEL_W (8),
.VALID_WIDTH (8),
.ENFORCE_ORDER (0),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (74),
.PKT_DEST_ID_L (71),
.PKT_TRANS_POSTED (56),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (76),
.ST_CHANNEL_W (8),
.VALID_WIDTH (8),
.ENFORCE_ORDER (0),
.PKT_BYTE_CNT_H (62),
.PKT_BYTE_CNT_L (60),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32)
) limiter_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clock_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cmd_xbar_demux cmd_xbar_demux (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
.sink_channel (limiter_001_cmd_src_channel), // .channel
.sink_data (limiter_001_cmd_src_data), // .data
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
.src4_data (cmd_xbar_demux_001_src4_data), // .data
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
.src5_data (cmd_xbar_demux_001_src5_data), // .data
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
.src6_data (cmd_xbar_demux_001_src6_data), // .data
.src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
.src7_data (cmd_xbar_demux_001_src7_data), // .data
.src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cmd_xbar_mux cmd_xbar_mux (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux rsp_xbar_demux (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_002 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_003 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_004 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_005 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_006 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_006_src_ready), // sink.ready
.sink_channel (id_router_006_src_channel), // .channel
.sink_data (id_router_006_src_data), // .data
.sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
.sink_valid (id_router_006_src_valid), // .valid
.src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
.src0_data (rsp_xbar_demux_006_src0_data), // .data
.src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_demux_002 rsp_xbar_demux_007 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_007_src_ready), // sink.ready
.sink_channel (id_router_007_src_channel), // .channel
.sink_data (id_router_007_src_data), // .data
.sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
.sink_valid (id_router_007_src_valid), // .valid
.src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
.src0_data (rsp_xbar_demux_007_src0_data), // .data
.src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_mux rsp_xbar_mux (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid
.sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel
.sink6_data (rsp_xbar_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid
.sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel
.sink7_data (rsp_xbar_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_irq_mapper irq_mapper (
.clk (clock_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sender_irq (cpu_inst_d_irq_irq) // sender.irq
);
endmodule |
module sky130_fd_sc_ls__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule |
module fifo
(
input wire clk,
input wire reset,
input wire rd,
input wire wr,
input wire [B-1:0] w_data,
output wire empty,
output wire full,
output wire [B-1:0] r_data
);
parameter B = 8; // number of bits
parameter W = 4; // number of address bits
reg [B-1:0] array_reg[2**W-1:0];
reg [W-1:0] w_ptr_reg, w_ptr_next;
reg [W-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire [W-1:0] w_ptr_succ, r_ptr_succ;
wire [1:0] wr_op;
wire wr_en;
integer i;
always @ (posedge clk, posedge reset) begin
if (reset) begin
for (i = 0; i <= 2**W-1; i = i+1)
array_reg[i] <= 0;
end
else begin
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
end
end
assign r_data = array_reg[r_ptr_reg];
assign wr_en = wr && !full_reg;
always @ (posedge clk, posedge reset) begin
if (reset) begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 0;
empty_reg <= 1;
end
else begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
assign w_ptr_succ = w_ptr_reg + 1;
assign r_ptr_succ = r_ptr_reg + 1;
// state machine works as follows
// READ:, it checks
// if the queue is empty, if it is not
// it will increment the queue, otherwise it does nothing
// WRITE: it checks if the queue is full before writing,
// if it is, then it will just be a nop waiting
// READ/WRITE: if read and write happens at the same time,
// we increment the counter for both of them, since it is assume
// they will get the same data
assign wr_op = {wr, rd};
always @ (w_ptr_reg, w_ptr_succ, r_ptr_reg, r_ptr_succ, wr_op, empty_reg, full_reg) begin
w_ptr_next <= w_ptr_reg;
r_ptr_next <= r_ptr_reg;
full_next <= full_reg;
empty_next <= empty_reg;
case (wr_op)
// nop
2'b00: begin
end
// read
2'b01: begin
if (!empty_reg) begin
r_ptr_next <= r_ptr_succ;
full_next <= 0;
if (r_ptr_succ == w_ptr_reg)
empty_next <= 1;
end
end
// write
2'b10: begin
if (!full_reg) begin
w_ptr_next <= w_ptr_succ;
empty_next <= 0;
if (w_ptr_succ == r_ptr_reg)
full_next <= 1;
end
end
// read/write
default: begin
w_ptr_next <= w_ptr_succ;
w_ptr_next <= r_ptr_succ;
end
endcase
end
assign full = full_reg;
assign empty = empty_reg;
endmodule |
module decode(/*AUTOARG*/
//Inputs
clk, ID_stall, inst_in, regrs_data, regrt_data, PCin,
//Outputs
PCout, ret_addr, aluc,op_a,op_b,op_sa,sign,nop, ssnop,jump, branch, rs, rt, rd,
load, store, move, load_op, store_op, move_op, regwrite, memread, memwrite, memaddr, memtoreg, regdst);
input clk;
input ID_stall;
input [31:0] inst_in;
reg [31:0] inst;
input [31:0] regrs_data, regrt_data;
input [31:0] PCin;
output reg [31:0] PCout, ret_addr;
//Alu
wire add, sub, mul, div, madd, msub;
wire [2:0] shift;
wire [3:0] _logic;
wire cmp;
wire [2:0] clzo;
output [20:0] aluc;
assign aluc = {add, sub, mul, div, madd, msub, shift, _logic, cmp, clzo};
output [31:0] op_a, op_b, op_sa;
output sign;
output reg [4:0] rs, rt, rd;
output nop, ssnop;
output jump;
output reg branch;
//output base, offset;
output load, store, move;
output wire [8:0] load_op;
output wire [5:0] store_op;
output wire [3:0] move_op;
output regwrite, memwrite, memread, memtoreg;
output [31:0] memaddr;
output [4:0] regdst;// write reg
wire [5:0] op = inst[31:26];
wire [5:0] func = inst[5:0];
wire cop0 = (op == 6'b010000);
wire imm_op = (op[5:3] == 3'b001);
wire regimm = (op == 6'b000001);
wire special = (op == 6'b000000);
wire special2 = (op == 6'b011100);
wire special3 = (op == 6'b011111);
//target_offset -> sign_extend(offset || 00)
//PC -> PC + target_offset
wire [15:0] offset = inst[15:0];
wire [31:0] target_offset = PCin + (offset[15] ? {14'h3fff, offset, 2'b00} : {14'h0000, offset, 2'b00});
assign memaddr = regrs_data + offset;
wire [31:0] immediate = inst[15] ? {16'hffff, inst[15:0]} : {16'b0, inst[15:0]};
assign op_a = (special | special2) ? regrt_data : immediate;
assign op_b = regrs_data;
assign op_sa = inst[10:6];
//PC -> PC[GPRLEN-1..28] || instr_index || 00
wire [25:0] inst_idx = inst[25:0];
assign add = (special && func[5:1]==5'b10000) || (op==5'b00100);
assign sub = (special && func[5:1]==5'b10001);
assign mul = (special2 & func == 6'b000010) || (special && func[5:1]==5'b01100);
assign div = (special && func[5:1]==5'b01101);
assign msub = (special2 && func[5:1]==5'b00010);
assign madd = (special2 && func[5:1]==5'b00000);
assign sign = (add && op[0]) || ((add | sub | mul | div| madd | msub)&&func[0]);
wire sll = (special && func == 6'b000000);
wire sllv = (special && func == 6'b000100);
wire sra = (special && func == 6'b000011);
wire srav = (special && func == 6'b000111);
wire srl = (special && func == 6'b000010);
wire srlv = (special && func == 6'b000110);
assign shift = {(sll|sllv), (sra|srav), (srl|srlv)};
wire _and = (special && func == 6'b100100);
wire _andi = (op == 6'b001100);
wire _or = (special && func == 6'b100101);
wire _ori = (op == 6'b001101);
wire _nor = (special && func == 6'b100111);
wire _xor = (special && func == 6'b100110);
wire _xori = (op == 6'b001110);
assign _logic = {_xor, _nor, (_and|_andi), (_or|_ori)};
// jump
wire j = op == 6'b000010;
wire jal = op == 6'b000011;
wire jalr = (special && func == 6'b001001);
wire jr = (special && func == 6'b001000);
//wire jump = (op[5:1] == 5'b00001) || (special && func[5:1] == 5'b00100);
//assign jump = {j, jal, jalr, jr};
assign jump = j | jal | jalr | jr;
// branch
wire b = (op == 6'b000100 && rs == 5'b00000 && rt == 5'b00000);
wire bal = (regimm && rs == 5'b00000 && rt == 5'b10001);
wire beq = op == 6'b000100;
wire beql = op == 6'b010100;
wire bgez = (regimm && rt == 5'b00001);
wire bgezal = (regimm && rt == 5'b10001);
wire bgezall = (regimm && rt == 5'b10011);
wire bgezl = (regimm && rt == 5'b00011);
wire bgtz = op == 6'b000111;
wire bgtzl = op == 6'b010111;
wire blez = op == 6'b000110;
wire blezl = op == 6'b010110;
wire bltz = (regimm && rt == 5'b00000);
wire bltzal = (regimm && rt == 5'b10000);
wire bltzall = (regimm && rt == 5'b10010);
wire bltzl = (regimm && rt == 5'b00010);
wire bne = op == 6'b000101;
wire bnel = op == 6'b010101;
//assign branch = b | bal | beq | beql | bgtz | bgtzl | blez | blezl | bne | bnel | regimm;
always @* begin
case ({b,bal,beq,beql,bgez,bgezal,bgezall,bgezl,bgtz,bgtzl,blez,blezl,bltz,bltzal,bltzall,bltzl,bne,bnel})
18'b10000000000000000 : branch <= 1; // b
18'b01000000000000000 : branch <= 1; // bal
// beq, beql
18'b00100000000000000 ,
18'b00010000000000000 : branch <= (regrs_data == regrt_data) ? 1 : 0;
// bgez,bgezal,bgezall,bgezl
18'b00001000000000000 , //begin branch <= (regrs_data >= 32'b0) ? 1 : 0; end
18'b00000100000000000 , //begin branch <= (regrs_data >= 32'b0) ? 1 : 0; end
18'b00000010000000000 , //begin branch <= (regrs_data >= 32'b0) ? 1 : 0; end
18'b00000001000000000 : begin branch <= (regrs_data >= 32'b0) ? 1 : 0; end
// blez,blezl
18'b00000000100000000 , //begin branch <= (regrs_data > 32'b0) ? 1 : 0; end
18'b00000000010000000 : begin branch <= (regrs_data > 32'b0) ? 1 : 0; end
// bltz,bltzal,bltzall,bltzl
18'b00000000001000000 , //begin branch <= (regrs_data <= 32'b0) ? 1 : 0; end
18'b00000000000100000 , //begin branch <= (regrs_data <= 32'b0) ? 1 : 0; end
18'b00000000000010000 , //begin branch <= (regrs_data < 32'b0) ? 1 : 0; end
18'b00000000000001000 , //begin branch <= (regrs_data < 32'b0) ? 1 : 0; end
18'b00000000000000100 : begin branch <= (regrs_data < 32'b0) ? 1 : 0; end
// bne, bnel
18'b00000000000000010 , //begin branch <= (regrs_data != regrt_data) ? 1 : 0; end
18'b00000000000000001 : begin branch <= (regrs_data != regrt_data) ? 1 : 0; end
endcase
end
wire break = (special && func == 6'b001101);
wire cache = op == 6'b101111;
wire clo = special2 && (func == 6'b100001);
wire clz = special2 && (func == 6'b100000);
assign cloz = {clz, clo};
// load
wire lb = (op == 6'b100000);
wire lbu = (op == 6'b100100);
wire lh = (op == 6'b100001);
wire lhu = (op == 6'b100101);
wire ll = (op == 6'b110000);
wire lui = (op == 6'b001111);
wire lw = (op == 6'b100011);
wire lwl = (op == 6'b100010);
wire lwr = (op == 6'b100110);
assign load = (lb | lbu | lh | lhu | ll | lui | lw | lwl | lwr);
assign load_op = {lb, lbu, lh, lhu, ll, lui, lw, lwl, lwr};
// store
wire sb = (op == 6'b101000);
wire sc = (op == 6'b111000);
wire sh = (op == 6'b101001);
wire sw = (op == 6'b101011);
wire swl = (op == 6'b101010);
wire swr = (op == 6'b101110);
assign store = (sb | sc | sh | sw | swl | swr);
assign store_op = {sb, sc, sh, sw, swl, swr};
// sync
wire sync = (special && func == 6'b001111);
wire stype = inst[10:6];
// trap
// teq teqi tge tgei tgeiu tgeu tlt tlti tltiu tltu tne tnei
wire teq = (special && func == 6'b110100);
wire teqi = (regimm && rt == 5'b01100);
wire tge = (special && func == 6'b110000);
wire tgei = (regimm && rt == 5'b01000);
wire tgeiu = (regimm && rt == 5'b01001);
wire tgeu = (special && func == 5'b11001);
wire tlt = (special && func == 6'b110010);
wire tlti = (regimm && rt == 5'b01010);
wire tltiu = (regimm && rt == 5'b01011);
wire tltu = (special && func == 6'b110011);
wire tne = (special && func == 6'b110110);
wire tnei = (regimm && rt == 5'b01110);
// wait
//wire _wait = (cop0 && co == 1 && func == 6'b100000);
// MFHI MFLO MOVN MOVZ MTHI MTLO
wire mfhi = (special && func == 6'b010000);
wire mflo = (special && func == 6'b010010);
wire movn = (special && func == 6'b001011);
wire movz = (special && func == 6'b001010);
assign move = (mfhi | mflo | movn | movz);
assign move_op = {mfhi, mflo, movn, movz};
// PREF PREFX to move data between memory and cache
// prefetch_memory(GPR[base] + offset)
// prefetch_memory(GPR[base] + GPR[index])
wire pref = (op == 6'b110011);
//wire prefx = (op == 6'b010011 && func == 6'b001111);
assign regwrite = (add|sub|(|shift)|(|_logic)|move|load|bal|bgezal|bgezall|bgezl|bltzal|bltzall|jal|jalr);
assign memwrite = store;
assign memread = load;
assign memtoreg = load;
assign regdst = (special && (op != 6'b001000)) ? rd : rt;
always @(posedge clk) begin
inst <= ID_stall ? inst : inst_in;
case ({ID_stall, j, jal, jalr, jr,branch})
6'b100000 : PCout <= PCin;
6'b010000 : PCout <= {PCin[31:28], inst_idx, 2'b00};
6'b001000 : PCout <= {PCin[31:28], inst_idx, 2'b00};
6'b000100 : PCout <= regrs_data;
6'b000010 : PCout <= regrs_data;
6'b000001 : PCout <= target_offset;
endcase
end
always @* begin
rs <= inst[25:21];
rt <= inst[20:16];
if (bal | bgezal | bgezall | bgezl | bltzal | bltzall | jal | jalr) begin
ret_addr <= PCin + 32'h0000008;
rd <= 5'b11111;
end else begin
rd <= inst[15:11];
end
end
endmodule |
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule |
module sky130_fd_sc_lp__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sha1_update(
input clk,
input start,
input [511:0] data_in,
input [159:0] hash_state_in,
output done,
output reg [159:0] hash_state_out
);
localparam IDLE = 2'd0;
localparam COMPRESSING = 2'd1;
localparam DONE = 2'd2;
reg [1:0] sm_state;
reg [1:0] sm_next_state;
reg [511:0] w;
wire [159:0] compression_state_loopback;
reg [ 31:0] w_roundi;
reg [ 6:0] round;
reg next_round;
wire [ 31:0] next_w;
initial begin
round = 7'd0;
w = 512'd0;
sm_state = IDLE;
end
sha1_compression rnd_compression(
.hash_state_in(hash_state_out),
.w(w_roundi),
.round(round),
.hash_state_out(compression_state_loopback)
);
assign next_w = w[511:480] ^ w[447:416] ^ w[255:224] ^ w[95:64];
assign done = sm_state == DONE;
always @ (*) begin
next_round = 1'b0;
case (sm_state)
IDLE : sm_next_state = start ? COMPRESSING : IDLE;
COMPRESSING : {sm_next_state, next_round} = round == 7'd79 ? {DONE, 1'b0} : {COMPRESSING, 1'b1};
DONE : sm_next_state = IDLE;
endcase
w_roundi = (round > 15) ? w[31:0] : w >> (10'd480 - (round << 5));
end
always @ (posedge clk) begin
if (start) begin
w <= data_in;
hash_state_out <= hash_state_in;
round <= 7'd0;
end
else begin
if (round >= 15) w <= {w[479:0], {next_w[30:0], next_w[31]}};
if (next_round) round <= round + 1'b1;
if (sm_next_state == DONE) begin
hash_state_out <= {
compression_state_loopback[159:128] + hash_state_in[159:128],
compression_state_loopback[127:96 ] + hash_state_in[127:96 ],
compression_state_loopback[ 95:64 ] + hash_state_in[ 95:64 ],
compression_state_loopback[ 63:32 ] + hash_state_in[ 63:32 ],
compression_state_loopback[ 31:0 ] + hash_state_in[ 31:0 ]
};
end
else hash_state_out <= compression_state_loopback;
end
sm_state <= sm_next_state;
end
endmodule |
module jt51_fir_ram
#(parameter data_width=8, parameter addr_width=7)
(
input [(data_width-1):0] data,
input [(addr_width-1):0] addr,
input we, clk,
output [(data_width-1):0] q
);
(* ramstyle = "no_rw_check" *) reg [data_width-1:0] ram[2**addr_width-1:0];
reg [addr_width-1:0] addr_reg;
always @ (posedge clk) begin
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
assign q = ram[addr_reg];
endmodule |
module PositiveReset (
IN_RST,
CLK,
OUT_RST
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST ;
output OUT_RST ;
//(* keep = "true" *)
reg [RSTDELAY:0] reset_hold ;
wire [RSTDELAY+1:0] next_reset = {reset_hold, 1'b0} ;
assign OUT_RST = reset_hold[RSTDELAY] ;
always @( posedge CLK ) // reset is read synchronous with clock
begin
if (IN_RST == `BSV_RESET_VALUE)
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY -1 ;
end
else
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY next_reset[RSTDELAY:0];
end
end // always @ ( posedge CLK )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = 0 ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule |
module udp_arb_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* UDP frame inputs
*/
input wire [S_COUNT-1:0] s_udp_hdr_valid,
output wire [S_COUNT-1:0] s_udp_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*4-1:0] s_ip_version,
input wire [S_COUNT*4-1:0] s_ip_ihl,
input wire [S_COUNT*6-1:0] s_ip_dscp,
input wire [S_COUNT*2-1:0] s_ip_ecn,
input wire [S_COUNT*16-1:0] s_ip_length,
input wire [S_COUNT*16-1:0] s_ip_identification,
input wire [S_COUNT*3-1:0] s_ip_flags,
input wire [S_COUNT*13-1:0] s_ip_fragment_offset,
input wire [S_COUNT*8-1:0] s_ip_ttl,
input wire [S_COUNT*8-1:0] s_ip_protocol,
input wire [S_COUNT*16-1:0] s_ip_header_checksum,
input wire [S_COUNT*32-1:0] s_ip_source_ip,
input wire [S_COUNT*32-1:0] s_ip_dest_ip,
input wire [S_COUNT*16-1:0] s_udp_source_port,
input wire [S_COUNT*16-1:0] s_udp_dest_port,
input wire [S_COUNT*16-1:0] s_udp_length,
input wire [S_COUNT*16-1:0] s_udp_checksum,
input wire [S_COUNT*DATA_WIDTH-1:0] s_udp_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_udp_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_udp_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_udp_payload_axis_tready,
input wire [S_COUNT-1:0] s_udp_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_udp_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_udp_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_udp_payload_axis_tuser,
/*
* UDP frame output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [DATA_WIDTH-1:0] m_udp_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_udp_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_udp_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_udp_payload_axis_tuser
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_udp_hdr_ready_reg = {S_COUNT{1'b0}}, s_udp_hdr_ready_next;
reg m_udp_hdr_valid_reg = 1'b0, m_udp_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
reg [3:0] m_ip_version_reg = 4'd0, m_ip_version_next;
reg [3:0] m_ip_ihl_reg = 4'd0, m_ip_ihl_next;
reg [5:0] m_ip_dscp_reg = 6'd0, m_ip_dscp_next;
reg [1:0] m_ip_ecn_reg = 2'd0, m_ip_ecn_next;
reg [15:0] m_ip_length_reg = 16'd0, m_ip_length_next;
reg [15:0] m_ip_identification_reg = 16'd0, m_ip_identification_next;
reg [2:0] m_ip_flags_reg = 3'd0, m_ip_flags_next;
reg [12:0] m_ip_fragment_offset_reg = 13'd0, m_ip_fragment_offset_next;
reg [7:0] m_ip_ttl_reg = 8'd0, m_ip_ttl_next;
reg [7:0] m_ip_protocol_reg = 8'd0, m_ip_protocol_next;
reg [15:0] m_ip_header_checksum_reg = 16'd0, m_ip_header_checksum_next;
reg [31:0] m_ip_source_ip_reg = 32'd0, m_ip_source_ip_next;
reg [31:0] m_ip_dest_ip_reg = 32'd0, m_ip_dest_ip_next;
reg [15:0] m_udp_source_port_reg = 16'd0, m_udp_source_port_next;
reg [15:0] m_udp_dest_port_reg = 16'd0, m_udp_dest_port_next;
reg [15:0] m_udp_length_reg = 16'd0, m_udp_length_next;
reg [15:0] m_udp_checksum_reg = 16'd0, m_udp_checksum_next;
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
// internal datapath
reg [DATA_WIDTH-1:0] m_udp_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep_int;
reg m_udp_payload_axis_tvalid_int;
reg m_udp_payload_axis_tready_int_reg = 1'b0;
reg m_udp_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_udp_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_int;
wire m_udp_payload_axis_tready_int_early;
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign s_udp_payload_axis_tready = (m_udp_payload_axis_tready_int_reg && grant_valid) << grant_encoded;
assign m_udp_hdr_valid = m_udp_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign m_udp_source_port = m_udp_source_port_reg;
assign m_udp_dest_port = m_udp_dest_port_reg;
assign m_udp_length = m_udp_length_reg;
assign m_udp_checksum = m_udp_checksum_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_udp_payload_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_udp_payload_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_udp_payload_axis_tvalid[grant_encoded];
wire current_s_tready = s_udp_payload_axis_tready[grant_encoded];
wire current_s_tlast = s_udp_payload_axis_tlast[grant_encoded];
wire [ID_WIDTH-1:0] current_s_tid = s_udp_payload_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_udp_payload_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_udp_payload_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
// arbiter instance
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = s_udp_hdr_valid & ~grant;
assign acknowledge = grant & s_udp_payload_axis_tvalid & s_udp_payload_axis_tready & s_udp_payload_axis_tlast;
always @* begin
frame_next = frame_reg;
s_udp_hdr_ready_next = {S_COUNT{1'b0}};
m_udp_hdr_valid_next = m_udp_hdr_valid_reg && !m_udp_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
m_ip_version_next = m_ip_version_reg;
m_ip_ihl_next = m_ip_ihl_reg;
m_ip_dscp_next = m_ip_dscp_reg;
m_ip_ecn_next = m_ip_ecn_reg;
m_ip_length_next = m_ip_length_reg;
m_ip_identification_next = m_ip_identification_reg;
m_ip_flags_next = m_ip_flags_reg;
m_ip_fragment_offset_next = m_ip_fragment_offset_reg;
m_ip_ttl_next = m_ip_ttl_reg;
m_ip_protocol_next = m_ip_protocol_reg;
m_ip_header_checksum_next = m_ip_header_checksum_reg;
m_ip_source_ip_next = m_ip_source_ip_reg;
m_ip_dest_ip_next = m_ip_dest_ip_reg;
m_udp_source_port_next = m_udp_source_port_reg;
m_udp_dest_port_next = m_udp_dest_port_reg;
m_udp_length_next = m_udp_length_reg;
m_udp_checksum_next = m_udp_checksum_reg;
if (s_udp_payload_axis_tvalid[grant_encoded] && s_udp_payload_axis_tready[grant_encoded]) begin
// end of frame detection
if (s_udp_payload_axis_tlast[grant_encoded]) begin
frame_next = 1'b0;
end
end
if (!frame_reg && grant_valid && (m_udp_hdr_ready || !m_udp_hdr_valid)) begin
// start of frame
frame_next = 1'b1;
s_udp_hdr_ready_next = grant;
m_udp_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[grant_encoded*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[grant_encoded*48 +: 48];
m_eth_type_next = s_eth_type[grant_encoded*16 +: 16];
m_ip_version_next = s_ip_version[grant_encoded*4 +: 4];
m_ip_ihl_next = s_ip_ihl[grant_encoded*4 +: 4];
m_ip_dscp_next = s_ip_dscp[grant_encoded*6 +: 6];
m_ip_ecn_next = s_ip_ecn[grant_encoded*2 +: 2];
m_ip_length_next = s_ip_length[grant_encoded*16 +: 16];
m_ip_identification_next = s_ip_identification[grant_encoded*16 +: 16];
m_ip_flags_next = s_ip_flags[grant_encoded*3 +: 3];
m_ip_fragment_offset_next = s_ip_fragment_offset[grant_encoded*13 +: 13];
m_ip_ttl_next = s_ip_ttl[grant_encoded*8 +: 8];
m_ip_protocol_next = s_ip_protocol[grant_encoded*8 +: 8];
m_ip_header_checksum_next = s_ip_header_checksum[grant_encoded*16 +: 16];
m_ip_source_ip_next = s_ip_source_ip[grant_encoded*32 +: 32];
m_ip_dest_ip_next = s_ip_dest_ip[grant_encoded*32 +: 32];
m_udp_source_port_next = s_udp_source_port[grant_encoded*16 +: 16];
m_udp_dest_port_next = s_udp_dest_port[grant_encoded*16 +: 16];
m_udp_length_next = s_udp_length[grant_encoded*16 +: 16];
m_udp_checksum_next = s_udp_checksum[grant_encoded*16 +: 16];
end
// pass through selected packet data
m_udp_payload_axis_tdata_int = current_s_tdata;
m_udp_payload_axis_tkeep_int = current_s_tkeep;
m_udp_payload_axis_tvalid_int = current_s_tvalid && m_udp_payload_axis_tready_int_reg && grant_valid;
m_udp_payload_axis_tlast_int = current_s_tlast;
m_udp_payload_axis_tid_int = current_s_tid;
m_udp_payload_axis_tdest_int = current_s_tdest;
m_udp_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
frame_reg <= frame_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
m_udp_hdr_valid_reg <= m_udp_hdr_valid_next;
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
m_ip_version_reg <= m_ip_version_next;
m_ip_ihl_reg <= m_ip_ihl_next;
m_ip_dscp_reg <= m_ip_dscp_next;
m_ip_ecn_reg <= m_ip_ecn_next;
m_ip_length_reg <= m_ip_length_next;
m_ip_identification_reg <= m_ip_identification_next;
m_ip_flags_reg <= m_ip_flags_next;
m_ip_fragment_offset_reg <= m_ip_fragment_offset_next;
m_ip_ttl_reg <= m_ip_ttl_next;
m_ip_protocol_reg <= m_ip_protocol_next;
m_ip_header_checksum_reg <= m_ip_header_checksum_next;
m_ip_source_ip_reg <= m_ip_source_ip_next;
m_ip_dest_ip_reg <= m_ip_dest_ip_next;
m_udp_source_port_reg <= m_udp_source_port_next;
m_udp_dest_port_reg <= m_udp_dest_port_next;
m_udp_length_reg <= m_udp_length_next;
m_udp_checksum_reg <= m_udp_checksum_next;
if (rst) begin
frame_reg <= 1'b0;
s_udp_hdr_ready_reg <= {S_COUNT{1'b0}};
m_udp_hdr_valid_reg <= 1'b0;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_udp_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_udp_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_udp_payload_axis_tvalid_reg = 1'b0, m_udp_payload_axis_tvalid_next;
reg m_udp_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_udp_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_udp_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_udp_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_udp_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_udp_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_udp_payload_axis_tvalid_reg = 1'b0, temp_m_udp_payload_axis_tvalid_next;
reg temp_m_udp_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_udp_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_udp_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_udp_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_udp_payload_axis_temp_to_output;
assign m_udp_payload_axis_tdata = m_udp_payload_axis_tdata_reg;
assign m_udp_payload_axis_tkeep = KEEP_ENABLE ? m_udp_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
assign m_udp_payload_axis_tid = ID_ENABLE ? m_udp_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_udp_payload_axis_tdest = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_udp_payload_axis_tuser = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b0;
if (m_udp_payload_axis_tready_int_reg) begin
// input is ready
if (m_udp_payload_axis_tready || !m_udp_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_udp_payload_axis_tvalid_next = m_udp_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_udp_payload_axis_tready) begin
// input is not ready, but output is ready
m_udp_payload_axis_tvalid_next = temp_m_udp_payload_axis_tvalid_reg;
temp_m_udp_payload_axis_tvalid_next = 1'b0;
store_udp_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_udp_payload_axis_tvalid_reg <= 1'b0;
m_udp_payload_axis_tready_int_reg <= 1'b0;
temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
m_udp_payload_axis_tid_reg <= m_udp_payload_axis_tid_int;
m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end else if (store_udp_payload_axis_temp_to_output) begin
m_udp_payload_axis_tdata_reg <= temp_m_udp_payload_axis_tdata_reg;
m_udp_payload_axis_tkeep_reg <= temp_m_udp_payload_axis_tkeep_reg;
m_udp_payload_axis_tlast_reg <= temp_m_udp_payload_axis_tlast_reg;
m_udp_payload_axis_tid_reg <= temp_m_udp_payload_axis_tid_reg;
m_udp_payload_axis_tdest_reg <= temp_m_udp_payload_axis_tdest_reg;
m_udp_payload_axis_tuser_reg <= temp_m_udp_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_udp_payload_axis_tdata_reg <= m_udp_payload_axis_tdata_int;
temp_m_udp_payload_axis_tkeep_reg <= m_udp_payload_axis_tkeep_int;
temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
temp_m_udp_payload_axis_tid_reg <= m_udp_payload_axis_tid_int;
temp_m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
end
end
endmodule |
module sky130_fd_sc_ls__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule |
module sky130_fd_sc_ls__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule |
module sky130_fd_sc_ms__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module pg_to_PG(
input [15:0] p,
input [15:0] g,
output [3:0] bp,
output [3:0] bg
);
assign bg[0]=g[3 ]|p[3 ]&g[2 ]|p[3 ]&p[2 ]&g[1 ]|p[3 ]&p[2 ]&p[1 ]&g[0 ],
bg[1]=g[7 ]|p[7 ]&g[6 ]|p[7 ]&p[6 ]&g[5 ]|p[7 ]&p[6 ]&p[5 ]&g[4 ],
bg[2]=g[11]|p[11]&g[10]|p[11]&p[10]&g[9 ]|p[11]&p[10]&p[9 ]&g[8 ],
bg[3]=g[15]|p[15]&g[14]|p[15]&p[14]&g[13]|p[15]&p[14]&p[13]&g[12];
assign bp[0]=p[3]&p[2]&p[1]&p[0],
bp[1]=p[7]&p[6]&p[5]&p[4],
bp[2]=p[11]&p[10]&p[9]&p[8],
bp[3]=p[15]&p[14]&p[13]&p[12];
endmodule |
module vga( input pxl_clk,
input reset_n,
output reg [9:0] hcount,
output reg [9:0] vcount,
output reg vsync,
output reg hsync );
always @ (posedge pxl_clk or negedge reset_n)
begin : hcounter
if (!reset_n) hcount <= 0;
else if (hcount <= 799) hcount <= hcount + 1'b1;
else hcount <= 0;
end
always @ (posedge pxl_clk or negedge reset_n)
begin : vcounter
if (!reset_n) vcount <= 0;
else if (hcount == 799 && vcount <= 521) vcount <= vcount + 1'b1;
else if (vcount <= 521) vcount <= vcount;
else vcount <= 0;
end
/********************************
640 pixels video
16 pixels front porch
96 pixels horizontal sync
48 pixels back porch
*********************************/
always @ (hcount)
begin : hsync_decoder
if (hcount >= 656 && hcount <= 752) hsync <= 0;
else hsync <= 1;
end
/********************************
480 lines video
2 lines front porch
10 lines vertical sync
29 lines back porch
*********************************/
always @ (vcount)
begin : vsync_decoder
if (vcount >= 482 && vcount <= 492) vsync <= 0;
else vsync <= 1;
end
endmodule |
module VICTIM_CACHE #(
parameter BLOCK_WIDTH = 512 ,
parameter TAG_WIDTH = 26 ,
parameter MEMORY_LATENCY = "HIGH_LATENCY" ,
localparam MEMORY_DEPTH = 4 ,
localparam ADDRESS_WIDTH = clog2(MEMORY_DEPTH-1)
) (
input CLK ,
input [TAG_WIDTH - 1 : 0] WRITE_TAG_ADDRESS ,
input [BLOCK_WIDTH - 1 : 0] WRITE_DATA ,
input WRITE_ENABLE ,
input [TAG_WIDTH - 1 : 0] READ_TAG_ADDRESS ,
input READ_ENBLE ,
output READ_HIT ,
output [BLOCK_WIDTH - 1 : 0] READ_DATA
);
reg [TAG_WIDTH - 1 : 0] tag [MEMORY_DEPTH - 1 : 0] ;
reg [BLOCK_WIDTH - 1 : 0] memory [MEMORY_DEPTH - 1 : 0] ;
reg valid [MEMORY_DEPTH - 1 : 0] ;
reg read_hit_out_reg_1 ;
reg [BLOCK_WIDTH - 1 : 0] data_out_reg_1 ;
reg [ADDRESS_WIDTH - 1 : 0] record_counter ;
wire full ;
wire empty ;
assign full = ( record_counter == (MEMORY_DEPTH - 1) ) ;
assign empty = ( record_counter == 0 ) ;
integer i;
initial
begin
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
tag [ i ] = {TAG_WIDTH{1'b0}};
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
memory [ i ] = {BLOCK_WIDTH{1'b0}};
for (i = 0; i < MEMORY_DEPTH; i = i + 1)
valid [ i ] = 1'b0;
record_counter = {ADDRESS_WIDTH{1'b0}} ;
read_hit_out_reg_1 = 1'b0 ;
data_out_reg_1 = {BLOCK_WIDTH{1'b0}} ;
end
always @(posedge CLK)
begin
if (WRITE_ENABLE & !full)
begin
tag [ record_counter ] <= WRITE_TAG_ADDRESS ;
memory [ record_counter ] <= WRITE_DATA ;
valid [ record_counter ] <= 1'b1 ;
record_counter <= record_counter + 1 ;
end
if (WRITE_ENABLE & full)
begin
for (i = 0; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
valid [ i ] <= valid [ i + 1 ] ;
end
tag [ record_counter ] <= WRITE_TAG_ADDRESS ;
memory [ record_counter ] <= WRITE_DATA ;
valid [ record_counter ] <= 1'b1 ;
end
if (READ_ENBLE & !empty)
begin
if( (tag [ 0 ] == READ_TAG_ADDRESS) & valid [ 0 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 0 ] ;
record_counter <= record_counter - 1 ;
for (i = 0; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 1 ] == READ_TAG_ADDRESS) & valid [ 1 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 1 ] ;
record_counter <= record_counter - 1 ;
for (i = 1; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 2 ] == READ_TAG_ADDRESS) & valid [ 2 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 2 ] ;
record_counter <= record_counter - 1 ;
for (i = 2; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else if( (tag [ 3 ] == READ_TAG_ADDRESS) & valid [ 3 ] )
begin
read_hit_out_reg_1 <= 1'b1 ;
data_out_reg_1 <= memory [ 3 ] ;
record_counter <= record_counter - 1 ;
for (i = 3; i < MEMORY_DEPTH - 1 ; i = i + 1)
begin
tag [ i ] <= tag [ i + 1 ] ;
memory [ i ] <= memory [ i + 1 ] ;
end
end
else
begin
read_hit_out_reg_1 <= 1'b0 ;
data_out_reg_1 <= {BLOCK_WIDTH{1'b0}} ;
end
end
if (READ_ENBLE & empty)
begin
read_hit_out_reg_1 <= 1'b0 ;
data_out_reg_1 <= {BLOCK_WIDTH{1'b0}} ;
end
end
generate
if (MEMORY_LATENCY == "LOW_LATENCY")
begin
assign READ_HIT = read_hit_out_reg_1 ;
assign READ_DATA = data_out_reg_1 ;
end
else
begin
reg read_hit_out_reg_2 = 1'b0 ;
reg [BLOCK_WIDTH - 1 :0] data_out_reg_2 = {BLOCK_WIDTH{1'b0}} ;
initial
begin
read_hit_out_reg_2 <= 1'b0 ;
data_out_reg_2 <= {BLOCK_WIDTH{1'b0}} ;
end
always @(posedge CLK)
begin
if (READ_ENBLE)
begin
read_hit_out_reg_2 <= read_hit_out_reg_1 ;
data_out_reg_2 <= data_out_reg_1 ;
end
end
assign READ_HIT = read_hit_out_reg_2 ;
assign READ_DATA = data_out_reg_2 ;
end
endgenerate
function integer clog2;
input integer depth;
for (clog2 = 0; depth > 0; clog2 = clog2 + 1)
depth = depth >> 1;
endfunction
endmodule |
module ZynqDesign_zbroji_0_0 (
s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB,
s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY,
s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA,
s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP,
s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID,
s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY,
interrupt,
aclk,
aresetn
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWADDR" *)
input wire [5 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS AWREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WDATA" *)
input wire [31 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WSTRB" *)
input wire [3 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS WREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BRESP" *)
output wire [1 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BVALID" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS BREADY" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARADDR" *)
input wire [5 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARVALID" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS ARREADY" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RDATA" *)
output wire [31 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RRESP" *)
output wire [1 : 0] s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RVALID" *)
output wire s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HLS_ZBROJI_PERIPH_BUS RREADY" *)
input wire s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aresetn RST" *)
input wire aresetn;
zbroji_top #(
.C_S_AXI_HLS_ZBROJI_PERIPH_BUS_ADDR_WIDTH(6),
.C_S_AXI_HLS_ZBROJI_PERIPH_BUS_DATA_WIDTH(32)
) inst (
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_AWADDR),
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_AWVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_AWREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_WDATA),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB(s_axi_HLS_ZBROJI_PERIPH_BUS_WSTRB),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_WVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_WREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_BRESP),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_BVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_BREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR(s_axi_HLS_ZBROJI_PERIPH_BUS_ARADDR),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_ARVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_ARREADY),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA(s_axi_HLS_ZBROJI_PERIPH_BUS_RDATA),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP(s_axi_HLS_ZBROJI_PERIPH_BUS_RRESP),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID(s_axi_HLS_ZBROJI_PERIPH_BUS_RVALID),
.s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY(s_axi_HLS_ZBROJI_PERIPH_BUS_RREADY),
.interrupt(interrupt),
.aclk(aclk),
.aresetn(aresetn)
);
endmodule |
module interrupt_control(
//System
input wire iCLOCK,
input wire inRESET,
//Interrupt Configlation Table
input wire iICT_VALID,
input wire [5:0] iICT_ENTRY,
input wire iICT_CONF_MASK,
input wire iICT_CONF_VALID,
input wire [1:0] iICT_CONF_LEVEL,
//Core Info
input wire [31:0] iSYSREGINFO_PSR,
//External
input wire iEXT_ACTIVE,
input wire [5:0] iEXT_NUM,
output wire oEXT_ACK,
//output oEXT_BUSY,
//Core-ALU
input wire iFAULT_ACTIVE,
input wire [6:0] iFAULT_NUM,
input wire [31:0] iFAULT_FI0R,
input wire [31:0] iFAULT_FI1R,
///To Exception Manager
input wire iEXCEPTION_LOCK,
output wire oEXCEPTION_ACTIVE,
output wire [6:0] oEXCEPTION_IRQ_NUM,
output wire [31:0] oEXCEPTION_IRQ_FI0R,
output wire [31:0] oEXCEPTION_IRQ_FI1R,
input wire iEXCEPTION_IRQ_ACK
);
localparam STT_IDLE = 2'h0;
localparam STT_COMP_WAIT = 2'h1;
/****************************************************
Register and Wire
***************************************************/
//Interrupt Valid
wire software_interrupt_valid;
wire hardware_interrupt_valid;
//Interrupt Config Table
reg ict_conf_mask[0:63];
reg ict_conf_valid[0:63];
reg [1:0] ict_conf_level[0:63];
//Instruction State
reg [1:0] b_state;
reg [6:0] b_irq_num;
reg b_irq_type;
reg b_irq_ack;
reg [31:0] b_irq_fi0r;
reg [31:0] b_irq_fi1r;
//Generate
integer i;
/****************************************************
Instruction Config Table
***************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 64; i = i + 1)begin
ict_conf_valid [i] = 1'b0;
end
if(`PROCESSOR_DATA_RESET_EN)begin
for(i = 0; i < 64; i = i + 1)begin
ict_conf_mask [i] = 1'b0;
ict_conf_level [i] = 2'h0;
end
end
end
else begin
if(iICT_VALID)begin
ict_conf_mask [iICT_ENTRY] <= iICT_CONF_MASK;
ict_conf_valid [iICT_ENTRY] <= iICT_CONF_VALID;
ict_conf_level [iICT_ENTRY] <= iICT_CONF_LEVEL;
end
end
end
assign software_interrupt_valid = !iEXCEPTION_LOCK/* && iSYSREGINFO_PSR[2]*/ && iFAULT_ACTIVE;
assign hardware_interrupt_valid = !iEXCEPTION_LOCK/* && iSYSREGINFO_PSR[2]*/ && iEXT_ACTIVE && (!ict_conf_valid[iEXT_NUM] || (ict_conf_valid[iEXT_NUM] && ict_conf_mask[iEXT_NUM]));
//Hardware Irq Latch
reg b_hw_irq_valid;
reg [6:0] b_hw_irq_num;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_hw_irq_valid <= 1'b0;
b_hw_irq_num <= 7'h0;
end
else begin
if(!b_hw_irq_valid)begin
if(iEXT_ACTIVE && (!ict_conf_valid[iEXT_NUM] || (ict_conf_valid[iEXT_NUM] && ict_conf_mask[iEXT_NUM])))begin
b_hw_irq_valid <= 1'b1;
b_hw_irq_num <= {1'b0, iEXT_NUM};
end
end
else begin
if(!software_interrupt_valid && b_state == STT_IDLE && !iEXCEPTION_LOCK)begin
b_hw_irq_valid <= 1'b0;
end
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= STT_IDLE;
b_irq_type <= 1'b0;
b_irq_ack <= 1'b0;
end
else begin
case(b_state)
STT_IDLE :
begin
if(software_interrupt_valid)begin
b_state <= STT_COMP_WAIT;
b_irq_type <= 1'b0;
b_irq_ack <= 1'b1;
end
else if(b_hw_irq_valid && !iEXCEPTION_LOCK)begin
b_state <= STT_COMP_WAIT;
b_irq_type <= 1'b1;
b_irq_ack <= 1'b1;
end
end
STT_COMP_WAIT :
begin
b_irq_ack <= 1'b0;
if(iEXCEPTION_IRQ_ACK)begin
b_state <= STT_IDLE;
end
end
default :
begin
b_state <= STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_irq_num <= {7{1'b0}};
b_irq_fi0r <= 32'h0;
b_irq_fi1r <= 32'h0;
end
else begin
case(b_state)
STT_IDLE :
begin
if(software_interrupt_valid)begin
b_irq_num <= iFAULT_NUM;
b_irq_fi0r <= iFAULT_FI0R;
b_irq_fi1r <= iFAULT_FI1R;
end
else if(b_hw_irq_valid && !iEXCEPTION_LOCK)begin
b_irq_num <= b_hw_irq_num;
b_irq_fi0r <= 32'h0;
b_irq_fi1r <= 32'h0;
end
end
default :
begin
b_irq_num <= b_irq_num;
b_irq_fi0r <= b_irq_fi0r;
b_irq_fi1r <= b_irq_fi1r;
end
endcase
end
end
assign oEXT_ACK = b_irq_ack && b_irq_type;//(b_state == `STT_COMP_WAIT && !software_interrupt_valid)? hardware_interrupt_valid : 1'b0;
assign oEXCEPTION_ACTIVE = (b_state == STT_COMP_WAIT)? !iEXCEPTION_IRQ_ACK : software_interrupt_valid || hardware_interrupt_valid || b_hw_irq_valid;//(b_state == `STT_COMP_WAIT)? !iFREE_IRQ_SETCONDITION : software_interrupt_valid || hardware_interrupt_valid;
assign oEXCEPTION_IRQ_NUM = (b_state == STT_COMP_WAIT)? b_irq_num : ((software_interrupt_valid)? iFAULT_NUM : {1'b0, iEXT_NUM});
assign oEXCEPTION_IRQ_FI0R = b_irq_fi0r;
assign oEXCEPTION_IRQ_FI1R = b_irq_fi1r;
endmodule |
module adc_pll_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 125,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 8,
pll1.clk0_phase_shift = "0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "no_compensation",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule |
module mfp_eic_core
(
input CLK,
input RESETn,
//signal inputs (should be synchronized!)
input [ `EIC_CHANNELS - 1 : 0 ] signal,
//register access
input [ `EIC_ADDR_WIDTH - 1 : 0 ] read_addr,
output reg [ 31 : 0 ] read_data,
input [ `EIC_ADDR_WIDTH - 1 : 0 ] write_addr,
input [ 31 : 0 ] write_data,
input write_enable,
//EIC processor interface
output [ 17 : 1 ] EIC_Offset,
output [ 3 : 0 ] EIC_ShadowSet,
output [ 7 : 0 ] EIC_Interrupt,
output [ 5 : 0 ] EIC_Vector,
output EIC_Present,
input EIC_IAck,
input [ 7 : 0 ] EIC_IPL,
input [ 5 : 0 ] EIC_IVN,
input [ 17 : 1 ] EIC_ION
);
//registers interface part
wire [ 31 : 0 ] EICR;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EIMSK;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EIFR;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EISMSK;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EIIPR;
wire [ `EIC_ALIGNED_WIDTH - 1 : 0 ] EIACM;
//register involved part
reg [ `EIC_EICR_WIDTH - 1 : 0 ] EICR_inv;
reg [ `EIC_CHANNELS - 1 : 0 ] EIMSK_inv;
reg [ 2*`EIC_SENSE_CHANNELS - 1 : 0 ] EISMSK_inv;
wire [ `EIC_CHANNELS - 1 : 0 ] EIFR_inv;
reg [ `EIC_CHANNELS - 1 : 0 ] EIACM_inv;
//register align and combination
assign EIMSK = { { `EIC_ALIGNED_WIDTH - `EIC_CHANNELS { 1'b0 } }, EIMSK_inv };
assign EISMSK = { { `EIC_ALIGNED_WIDTH - 2*`EIC_SENSE_CHANNELS { 1'b0 } }, EISMSK_inv};
assign EIFR = { { `EIC_ALIGNED_WIDTH - `EIC_CHANNELS { 1'b0 } }, EIFR_inv };
assign EIIPR = { { `EIC_ALIGNED_WIDTH - `EIC_CHANNELS { 1'b0 } }, signal };
assign EIACM = { { `EIC_ALIGNED_WIDTH - `EIC_CHANNELS { 1'b0 } }, EIACM_inv };
assign EICR = { { 32 - `EIC_EICR_WIDTH { 1'b0 } }, EICR_inv };
assign EIC_Present = EICR_inv[`EICR_EE];
//register read operations
always @ (*)
case(read_addr)
default : read_data = 32'b0;
`EIC_REG_EICR : read_data = EICR;
`EIC_REG_EIMSK_0 : read_data = EIMSK [ 31:0 ];
`EIC_REG_EIMSK_1 : read_data = EIMSK [ 63:32 ];
`EIC_REG_EIFR_0 : read_data = EIFR [ 31:0 ];
`EIC_REG_EIFR_1 : read_data = EIFR [ 63:32 ];
`EIC_REG_EIFRS_0 : read_data = 32'b0;
`EIC_REG_EIFRS_1 : read_data = 32'b0;
`EIC_REG_EIFRC_0 : read_data = 32'b0;
`EIC_REG_EIFRC_1 : read_data = 32'b0;
`EIC_REG_EISMSK_0 : read_data = EISMSK [ 31:0 ];
`EIC_REG_EISMSK_1 : read_data = EISMSK [ 63:32 ];
`EIC_REG_EIIPR_0 : read_data = EIIPR [ 31:0 ];
`EIC_REG_EIIPR_1 : read_data = EIIPR [ 63:32 ];
`EIC_REG_EIACM_0 : read_data = EIACM [ 31:0 ];
`EIC_REG_EIACM_1 : read_data = EIACM [ 63:32 ];
endcase
//register write operations
wire [ `EIC_CHANNELS - 1 : 0 ] EIFR_wr_data;
wire [ `EIC_CHANNELS - 1 : 0 ] EIFR_wr_enable;
wire [ `EIC_CHANNELS - 1 : 0 ] EIMSK_new;
wire [ `EIC_CHANNELS - 1 : 0 ] EISMSK_new;
wire [ `EIC_EICR_WIDTH - 1 : 0 ] EICR_new;
wire [ `EIC_CHANNELS - 1 : 0 ] EIACM_new;
reg [ 17 : 0 ] write_cmd;
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EIFR_dt (.in(EIFR_inv), .out(EIFR_wr_data), .word(write_data), .cmd(write_cmd[ 2:0 ]));
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EIFR_wr (.in(EIFR_inv), .out(EIFR_wr_enable), .word(write_data), .cmd(write_cmd[ 5:3 ]));
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EIMSK (.in(EIMSK_inv), .out(EIMSK_new), .word(write_data), .cmd(write_cmd[ 8:6 ]));
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EISMSK (.in(EISMSK_inv), .out(EISMSK_new), .word(write_data), .cmd(write_cmd[11:9 ]));
new_reg_value #(.USED(`EIC_EICR_WIDTH)) nrv_EICR (.in(EICR_inv), .out(EICR_new), .word(write_data), .cmd(write_cmd[14:12]));
new_reg_value #(.USED(`EIC_CHANNELS)) nrv_EIACM (.in(EIACM_inv), .out(EIACM_new), .word(write_data), .cmd(write_cmd[17:15]));
wire [ `EIC_ADDR_WIDTH - 1 : 0 ] __write_addr = write_enable ? write_addr : `EIC_REG_NONE;
always @ (*) begin
case(__write_addr)
default : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EICR : write_cmd = { `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIMSK_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIMSK_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL1, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIFR_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_SET0, `EIC_C_VAL0 };
`EIC_REG_EIFR_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_SET1, `EIC_C_VAL1 };
`EIC_REG_EIFRS_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_VAL0 };
`EIC_REG_EIFRS_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL1, `EIC_C_VAL1 };
`EIC_REG_EIFRC_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_CLR0 };
`EIC_REG_EIFRC_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL1, `EIC_C_CLR1 };
`EIC_REG_EISMSK_0 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL0, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EISMSK_1 : write_cmd = { `EIC_C_NONE, `EIC_C_NONE, `EIC_C_VAL1, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIACM_0 : write_cmd = { `EIC_C_VAL0, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
`EIC_REG_EIACM_1 : write_cmd = { `EIC_C_VAL1, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_NONE, `EIC_C_CLRA, `EIC_C_CLRA };
endcase
end
always @ (posedge CLK)
if(~RESETn) begin
EIMSK_inv <= { `EIC_CHANNELS { 1'b0 } };
EISMSK_inv <= { `EIC_CHANNELS { 1'b0 } };
EICR_inv <= { `EIC_EICR_WIDTH { 1'b0 } };
EIACM_inv <= { `EIC_CHANNELS { 1'b0 } };
end
else
case(__write_addr)
default : ;
`EIC_REG_EICR : EICR_inv <= EICR_new;
`EIC_REG_EIMSK_0 : EIMSK_inv <= EIMSK_new;
`EIC_REG_EIMSK_1 : EIMSK_inv <= EIMSK_new;
`EIC_REG_EISMSK_0 : EISMSK_inv <= EISMSK_new;
`EIC_REG_EISMSK_1 : EISMSK_inv <= EISMSK_new;
`EIC_REG_EIACM_0 : EIACM_inv <= EIACM_new;
`EIC_REG_EIACM_1 : EIACM_inv <= EIACM_new;
endcase
//current interrupt processing by CPU (EIC_IVN, EIC_ION -> irqNumberCur, irqFlagCur)
wire [ 7 : 0 ] irqNumberCur;
wire [ `EIC_CHANNELS - 1 : 0 ] irqFlagCur = (1 << irqNumberCur);
handler_params_decoder handler_params_decoder
(
.irqVector ( EIC_IVN ),
.irqOffset ( EIC_ION ),
.irqNumber ( irqNumberCur )
);
// auto clear flag logic
wire [ `EIC_CHANNELS - 1 : 0 ] requestWR = EIC_IAck ? EIFR_wr_enable | (EIACM_inv & irqFlagCur)
: EIFR_wr_enable;
wire [ `EIC_CHANNELS - 1 : 0 ] requestIn = EIC_IAck ? EIFR_wr_data & ~(EIACM_inv & irqFlagCur)
: EIFR_wr_data;
//interrupt input logic (signal -> request)
wire [ `EIC_SENSE_CHANNELS - 1 : 0 ] sensed;
wire [ `EIC_CHANNELS - 1 : 0 ] mask = EICR_inv[`EICR_EE] ? EIMSK_inv
: { `EIC_CHANNELS {1'b0}};
generate
genvar i, j;
for (i = 0; i < `EIC_SENSE_CHANNELS; i = i + 1)
begin : sirq
interrupt_sence sense
(
.CLK ( CLK ),
.RESETn ( RESETn ),
.senceMask ( EISMSK_inv [ (1+i*2):(i*2) ] ),
.signalIn ( signal [i] ),
.signalOut ( sensed [i] )
);
interrupt_channel channel
(
.CLK ( CLK ),
.RESETn ( RESETn ),
.signalMask ( mask [i] ),
.signalIn ( sensed [i] ),
.requestWR ( requestWR [i] ),
.requestIn ( requestIn [i] ),
.requestOut ( EIFR_inv [i] )
);
end
for (j = `EIC_SENSE_CHANNELS; j < `EIC_CHANNELS; j = j + 1)
begin : irq
interrupt_channel channel
(
.CLK ( CLK ),
.RESETn ( RESETn ),
.signalMask ( mask [j] ),
.signalIn ( signal [j] ),
.requestWR ( requestWR [j] ),
.requestIn ( requestIn [j] ),
.requestOut ( EIFR_inv [j] )
);
end
endgenerate
//interrupt priority decode (EIFR -> irqNumber)
wire irqDetected;
wire [ 5 : 0 ] irqNumberL;
wire [ 7 : 0 ] irqNumber = { 2'b0, irqNumberL };
priority_encoder64 priority_encoder //use priority_encoder255 for more interrupt inputs
(
.in ( EIFR ),
.detect ( irqDetected ),
.out ( irqNumberL )
);
//interrupt priority encode (irqNumber -> handler_params)
handler_params_encoder handler_params_encoder
(
.irqNumber ( irqNumber ),
.irqDetected ( irqDetected ),
.EIC_Offset ( EIC_Offset ),
.EIC_ShadowSet ( EIC_ShadowSet ),
.EIC_Interrupt ( EIC_Interrupt ),
.EIC_Vector ( EIC_Vector )
);
endmodule |
module new_reg_value
#(
parameter USED = 8
)
(
input [ USED - 1 : 0 ] in, //input value
output reg [ USED - 1 : 0 ] out, //output value
input [ 31 : 0 ] word, //new data value
input [ 2 : 0 ] cmd //update command (see EIC_C_* defines)
);
localparam BYTE1_SIZE = (USED > 32) ? (USED - 32) : 0;
localparam BYTE1_MAX = (BYTE1_SIZE > 0) ? (BYTE1_SIZE - 1) : 0;
localparam BYTE1_START = (BYTE1_SIZE > 0) ? 32 : 0;
localparam BYTE1_END = (BYTE1_SIZE > 0) ? (USED - 1) : 0;
always @ (*) begin
if(USED < 33)
case(cmd)
default : out = in;
`EIC_C_CLR0 : out = { USED {1'b0} };
`EIC_C_CLR1 : out = in;
`EIC_C_SET0 : out = { USED {1'b1} };
`EIC_C_SET1 : out = in;
`EIC_C_VAL0 : out = word [ USED - 1 : 0 ];
`EIC_C_VAL1 : out = in;
`EIC_C_CLRA : out = { USED {1'b0} };
endcase
else
case(cmd)
default : out = in;
`EIC_C_CLR0 : out = { in [ BYTE1_END : BYTE1_START ], 32'b0 };
`EIC_C_CLR1 : out = { { BYTE1_SIZE { 1'b0 } }, in [ 31 : 0 ] };
`EIC_C_SET0 : out = { in [ BYTE1_END : BYTE1_START ], ~32'b0 };
`EIC_C_SET1 : out = { { BYTE1_SIZE { 1'b1 } }, in [ 31 : 0 ] };
`EIC_C_VAL0 : out = { in [ BYTE1_END : BYTE1_START ], word };
`EIC_C_VAL1 : out = { word [ BYTE1_MAX : 0 ], in [ 31 : 0 ] };
`EIC_C_CLRA : out = { USED {1'b0} };
endcase
end
endmodule |
module interrupt_channel
(
input CLK,
input RESETn,
input signalMask, // Interrupt mask (0 - disabled, 1 - enabled)
input signalIn, // Interrupt intput signal
input requestWR, // forced interrupt flag change
input requestIn, // forced interrupt flag value
output reg requestOut // interrupt flag
);
wire request = requestWR ? requestIn :
(signalMask & signalIn | requestOut);
always @ (posedge CLK)
if(~RESETn)
requestOut <= 1'b0;
else
requestOut <= request;
endmodule |
module interrupt_sence
(
input CLK,
input RESETn,
input [1:0] senceMask,
input signalIn,
output reg signalOut
);
// senceMask:
parameter MASK_LOW = 2'b00, // The low level of signalIn generates an interrupt request
MASK_ANY = 2'b01, // Any logical change on signalIn generates an interrupt request
MASK_FALL = 2'b10, // The falling edge of signalIn generates an interrupt request
MASK_RIZE = 2'b11; // The rising edge of signalIn generates an interrupt request
parameter S_RESET = 0,
S_INIT0 = 1,
S_INIT1 = 2,
S_WORK = 3;
reg [ 1 : 0 ] State, Next;
reg [ 1 : 0 ] signal;
always @ (posedge CLK)
if(~RESETn)
State <= S_INIT0;
else
State <= Next;
always @ (posedge CLK)
case(State)
S_RESET : signal <= 2'b0;
default : signal <= { signal[0], signalIn };
endcase
always @ (*) begin
case (State)
S_RESET : Next = S_INIT0;
S_INIT0 : Next = S_INIT1;
default : Next = S_WORK;
endcase
case( { State, senceMask } )
{ S_WORK, MASK_LOW } : signalOut = ~signal[1] & ~signal[0];
{ S_WORK, MASK_ANY } : signalOut = signal[1] ^ signal[0];
{ S_WORK, MASK_FALL } : signalOut = signal[1] & ~signal[0];
{ S_WORK, MASK_RIZE } : signalOut = ~signal[1] & signal[0];
default : signalOut = 1'b0;
endcase
end
endmodule |
module drom32 (
address,
clock,
q);
input [11:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module that accesses the chip's oscillator
//"2.08" specifies the operating frequency, 2.03 MHz. Other clock frequencies can be found in the MachX02's documentation
OSCH #("2.08") osc_int (
.STDBY(1'b0), //Specifies active state
.OSC(clk), //Outputs clock signal to 'clk' net
.SEDSTDBY() //Leaves SEDSTDBY pin unconnected
);
clock_counter divider1 (
.reset_n(reset_n),
.clk_i(clk),
.clk_o(clk_slow)
);
ADCinterface ADC1 (
.clk(clk),
.reset_n(reset_n),
.CS_n(CS_o),
.RD_n(RD_o),
.WR_n(WR_o)
);
digit_state_machine DSM1 (
.units(units_place),
.tens(tens_place),
.hundreds(hundreds_place),
.thousands(thousands_place),
.reset_n(reset_n),
.clk(clk_slow),
.digit_select(digit),
.data(data_o),
.decimal_point(decimal_point)
);
decoder d1(
.data(data_o),
.segments(segments)
);
endmodule |
module IMG_TRI_BUFFER (
data,
rdaddress_a,
rdaddress_b,
rdclock,
wraddress,
wrclock,
wren,
qa,
qb);
input [7:0] data;
input [10:0] rdaddress_a;
input [10:0] rdaddress_b;
input rdclock;
input [10:0] wraddress;
input wrclock;
input wren;
output [7:0] qa;
output [7:0] qb;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module offset_flag_to_one_hot
#(
parameter C_WIDTH = 4
)
(
input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
input WR_FLAG,
output [C_WIDTH-1:0] RD_ONE_HOT
);
assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
endmodule |
module test_bsg
#(parameter width_p=4,
parameter output_width_p=2*width_p-1,
parameter cycle_time_p=10,
parameter reset_cycles_lo_p=-1,
parameter reset_cycles_hi_p=-1
);
wire clk_lo;
logic reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk_lo)
, .async_reset_o(reset)
);
logic [31:0] ctr;
always @(posedge clk_lo)
if (reset)
ctr <= '0;
else
ctr <= ctr + 1'b1;
wire [output_width_p-1:0] res;
bsg_adder_one_hot #(.width_p(width_p),.output_width_p(output_width_p))
foo (.a_i(1'b1 << ctr[1:0]), .b_i(1'b1 << ctr[3:2]), .o(res));
always @(negedge clk_lo)
begin
$display("%b %b -> %b\n", 1 << ctr[1:0], 1 << ctr[3:2], res);
if (ctr == 5'b10000)
$finish();
end
endmodule |
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_ls__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__o21ai_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule |
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br_table1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_table1_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#50
`assert(result, 3);
`assert(result_type, `i64);
`assert(result_empty, 0);
`assert(trap, `ENDED);
end
else begin
#24
`assert(trap, `NO_64B);
end
$finish;
end
endmodule |
module fifo
#(
B = 8, //Num of bits in data word
W = 4 //Num addr bits of FIFO
//Num words in FIFO=2^FIFO_W
)
(
input wire clk, reset,
input wire wr, rd,
input wire [B-1:0] w_data,
output wire full, empty,
output wire [B-1:0] r_data
);
//signal declaration
reg [B-1:0] array_reg [0:2**W-1]; //register array
reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
//body
//register file write operation
always @(posedge clk)
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
//register file read operation
assign r_data = array_reg[r_ptr_reg];
//write enable only when FIFO is not full
assign wr_en = wr & ~full_reg;
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset)
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next; //Indice para leer el sig bit
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
//next-state logic for read and write pointers
always @*
begin
//successive pointer values
w_ptr_succ = w_ptr_reg + 4'b0001;
r_ptr_succ = r_ptr_reg + 4'b0001;
// default: keep old values
w_ptr_next = w_ptr_reg;
r_ptr_next = r_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
// 2'b00: no op
2'b01: //read
if (~empty_reg) //not empty
begin
r_ptr_next = r_ptr_succ;
full_next = 1'b0;
if (r_ptr_succ==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: //write
if (~full_reg) //not full
begin
w_ptr_next = w_ptr_succ;
empty_next = 1'b0;
if (w_ptr_succ==r_ptr_reg)
full_next = 1'b1;
end
2'b11: //write and read
begin
w_ptr_next = w_ptr_succ;
r_ptr_next = r_ptr_succ;
end
endcase
end
//output
assign full = full_reg;
assign empty = empty_reg;
endmodule |
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam IDLE = 4'h0;
localparam EXECUTE = 4'h1;
localparam RESET = 4'h2;
localparam PING_RESPONSE = 4'h3;
localparam WRITE_DATA = 4'h4;
localparam WRITE_RESPONSE = 4'h5;
localparam GET_WRITE_DATA = 4'h6;
localparam READ_RESPONSE = 4'h7;
localparam READ_MORE_DATA = 4'h8;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_bram s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(2);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
$display ("");
end
else begin
$display ("Error unrecognized line: %h" % ch);
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
$display ("Sleep for %h Clock cycles", r_in_data_count);
`SLEEP_CLK(r_in_data_count);
$display ("");
end
else begin
$display ("Error: read_count = %h != 4", read_count);
$display ("Character: %h", ch);
end
end
else begin
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
$display ("TB: reading a new double word: %h", r_in_data);
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
execute_command <= 1;
end //while command is not finished
while (command_finished) begin
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
$display ("TB: finished command");
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count > 0) begin
timeout_count <= timeout_count - 1;
end
if (execute_command && timeout_count == 0) begin
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
state <= IDLE;
command_finished <= 1;
timeout_count <= `TIMEOUT_COUNT;
data_write_count <= 1;
end //end reached the end of a timeout
case (state)
IDLE: begin
if (execute_command & ~command_finished) begin
$display ("TB: #:C:A:D = %h:%h:%h:%h", r_in_data_count, r_in_command, r_in_address, r_in_data);
timeout_count <= `TIMEOUT_COUNT;
state <= EXECUTE;
end
end
EXECUTE: begin
if (w_master_ready) begin
//send the command over
r_in_ready <= 1;
case (r_in_command & 32'h0000FFFF)
0: begin
//ping
state <= PING_RESPONSE;
end
1: begin
//write
if (r_in_data_count > 1) begin
$display ("TB: \tWrote double word %d: %h", data_write_count, r_in_data);
state <= WRITE_DATA;
timeout_count <= `TIMEOUT_COUNT;
data_write_count <= data_write_count + 1;
end
else begin
if (data_write_count > 1) begin
$display ("TB: \tWrote double word %d: %h", data_write_count, r_in_data);
end
state <= WRITE_RESPONSE;
end
end
2: begin
//read
state <= READ_RESPONSE;
end
3: begin
//reset
state <= RESET;
end
endcase
end
end
RESET: begin
//reset the system
r_ih_reset <= 1;
command_finished <= 1;
state <= IDLE;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000000))) begin
$display ("TB: Read a successful ping reponse");
end
else begin
$display ("TB: Ping response is incorrect!");
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
command_finished <= 1;
state <= IDLE;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000001))) begin
$display ("TB: Read a successful write reponse");
end
else begin
$display ("TB: Write response is incorrect!");
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= IDLE;
command_finished <= 1;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
//XXX: should request more data be a strobe?
request_more_data <= 0;
r_in_ready <= 1;
r_in_data_count <= r_in_data_count -1;
state <= EXECUTE;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status == (~(32'h00000002))) begin
$display ("TB: Read a successful read response");
if (w_out_data_count > 0) begin
state <= READ_MORE_DATA;
//reset the NACK timeout
timeout_count <= `TIMEOUT_COUNT;
end
else begin
state <= IDLE;
command_finished <= 1;
end
end
else begin
$display ("TB: Read response is incorrect");
command_finished <= 1;
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
r_out_ready <= 0;
if (w_out_status == (~(32'h00000002))) begin
$display ("TB: Read a 32bit data packet");
$display ("Tb: \tRead Data: %h", w_out_data);
end
else begin
$display ("TB: Read reponse is incorrect");
end
//read the output data count to determine if there is more data
if (w_out_data_count == 0) begin
state <= IDLE;
command_finished <= 1;
end
end
end
default: begin
$display ("TB: state is wrong");
state <= IDLE;
end //somethine wrong here
endcase //state machine
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
$display("TB: Output Handler Recieved interrupt");
$display("TB:\tcommand: %h", w_out_status);
$display("TB:\taddress: %h", w_out_address);
$display("TB:\tdata: %h", w_out_data);
end
end//not reset
end
endmodule |
module muladd_wrap (
input ck,
input rst,
input [63:0] i_a, i_b, i_c, //a + b * c
input i_vld,
output o_rdy,
output [63:0] o_res,
output o_vld
);
parameter ENTRY_DEPTH = 32;
wire ef_afull;
wire ef_pop;
wire ef_empty;
wire [63:0] ef_a, ef_b, ef_c;
fifo #(
.WIDTH(64+64+64),
.DEPTH(ENTRY_DEPTH),
.PIPE(1),
.AFULLCNT(ENTRY_DEPTH - 2)
) entry_fifo (
.clk(ck),
.reset(rst),
.push(i_vld),
.din({i_a, i_b, i_c}),
.afull(ef_afull),
.oclk(ck),
.pop(ef_pop),
.dout({ef_a, ef_b, ef_c}),
.empty(ef_empty)
);
wire mult_rdy;
wire [63:0] mult_res;
wire mult_vld;
assign ef_pop = !ef_empty & mult_rdy;
// Black box instantiation
mul_64b_dp multiplier (.clk(ck), .a(ef_b), .b(ef_c), .operation_nd(ef_pop), .operation_rfd(mult_rdy), .result(mult_res), .rdy(mult_vld));
reg [63:0] r_t2_a, r_t3_a, r_t4_a, r_t5_a, r_t6_a, r_t7_a;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
if (ef_pop) begin
r_t2_a <= ef_a;
end else begin
r_t2_a <= r_t2_a;
end
r_t3_a <= r_t2_a;
r_t4_a <= r_t3_a;
r_t5_a <= r_t4_a;
r_t6_a <= r_t5_a;
r_t7_a <= r_t6_a;
end
parameter MID_DEPTH = 32;
wire mf_afull;
wire mf_pop;
wire mf_empty;
wire [63:0] mf_a, mf_bc;
fifo #(
.WIDTH(64+64),
.DEPTH(MID_DEPTH),
.PIPE(1),
.AFULLCNT(MID_DEPTH - 2)
) mid_fifo (
.clk(ck),
.reset(rst),
.push(mult_vld),
.din({r_t7_a, mult_res}),
.afull(mf_afull),
.oclk(ck),
.pop(mf_pop),
.dout({mf_a, mf_bc}),
.empty(mf_empty)
);
wire add_rdy;
wire [63:0] add_res;
wire add_vld;
assign mf_pop = !mf_empty & add_rdy;
// Black box instantiation
add_64b_dp adder (.clk(ck), .a(mf_a), .b(mf_bc), .operation_nd(mf_pop), .operation_rfd(add_rdy), .result(add_res), .rdy(add_vld));
// Outputs
assign o_rdy = !ef_afull;
assign o_res = add_res;
assign o_vld = add_vld;
endmodule |
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X, nor0_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule |
module to the block ram for the cache data. Port A is the byte port and
// port B is the word port, so the address lines are one bit bigger on the A port
cache_d cache_inst (
// The byte address is Way, then row, then index, and switch the LSB to give correct byte order
.address_a ( {hit_way,calc_row,calc_index[3:1],~calc_index[0] } ),
// Way is MSB, then Row, then Index
.address_b ( {hit_way,calc_row,block_ptr} ),
// Both clocks are the same, but could be independent
.clock_a ( clock_i ),
.clock_b ( clock_i ),
// Port A data comes from the byte port
.data_a ( bdati ),
// Port B data comes from the SDRAM port
.data_b ( mem_dat_alt/*wdat_i TODO: Check */),
// Port A is write then the byte port requests it
.wren_a ( write_ctl ),
// Port B is write when we're in a read mode (write enable signalled) and the SDRAM signals it's outputting data
.wren_b ( wvalid_i & wwe ),
// Output ports for A+B
.q_a ( bdato_wire ),
.q_b ( wdato_wire )
);
// Simulation branches and control ============================================================
// Other logic ================================================================================
// Main finite state machine, positive clock edge logic
always @(posedge clock_i)
if( reset_i ) state <= INIT1;
else case( state )
// Clear out key variables. Note the cache data is not cleared
INIT1: begin
wenable <= 1'b0; wrd <= 1'b0; wwr <= 1'b0; bvalid <= 1'b0;
wadr <= 23'd0; bdato <= 8'd0;
state <= INIT2;
end
// Clear out flags array and MRU - if these are clean, then the tags and cache don't need to be 0'd
INIT2: begin
way0_flags[general_cntr] <= 2'd0;
way1_flags[general_cntr] <= 2'd0;
mru[general_cntr] <= 1'b0;
if( ~general_cntr[6:0] == 7'd0 ) state <= IDLE; // Last byte 7f
end
// Wait for a command, note that the byte port is the master port. No requests appear on the word port
IDLE: begin
// If we were advancing the counter, then it's no longer necessary here
advance_cntr <= 1'b0;
// Disable the write enable flag for the cache memory, to prevent overwriting if another port causes valid_i
wwe <= 1'b0;
if( benable_i & (brd_i | bwr_i))
begin
// Store instruction parameters for later as the command will cease after one clock cycle
brd <= brd_i;
bwr <= bwr_i;
badr <= badr_i;
bdati <= bdat_i;
bvalid <= 1'b0; // Reset valid from last operation
// Point to next state
state <= SEARCH;
end
end
// Try to locate the correct cache row, if it's in the cache
SEARCH : begin
// Not empty way and tag hit (address matched) - cache hit!
if( ( way0_flag != 2'd0 ) && (way0_tag == calc_tag) )
begin
// Indicate this was WAY0
hit_way <= 1'b0;
// Update the most recently used flag
mru[calc_row] <= 1'b0;
$display("Cache HIT! Way 0"); // Debug messages
// If we're reading from cache, go straight to output
if( brd ) state <= OUTPUT1;
else
// Otherwise store the data received on the byte port
if( bwr ) state <= WRITE1;
// Fail safe - if we somehow get here, then go back to idle
else state <= IDLE;
end
else
// Not empty way and tag hit (address matched) - cache hit!
if( ( way1_flag != 2'd0 ) && (way1_tag == calc_tag) )
begin
// Indicate this was WAY1
hit_way <= 1'b1;
// Update the most recently used flag
mru[calc_row] <= 1'b1;
$display("Cache HIT! Way 1"); // Debug messages
// If we're reading from cache, go straight to output
if( brd ) state <= OUTPUT1;
else
// Otherwise store the data received on the byte port
if( bwr ) state <= WRITE1;
// Fail safe - if we somehow get here, then go back to idle
else state <= IDLE;
end
// Otherwise it's a cache miss, so select a victim cache way/line
else begin
// If way 0 or way 1 is empty, just read/write to that way
if( way0_flag == 2'd0 )
begin
hit_way <= 1'b0;
state <= READ1;
end
else
if ( way1_flag == 2'd0 )
begin
hit_way <= 1'b1;
state <= READ1;
end
// Otherwise both ways full, so select a row for replacement
else begin
// Calculate victim way
hit_way <= ~mru[calc_row]; // Select the way least recently used (not (~) most recent used)
$display("At %08d Row replacement for %d, 0x%06x, victim way %d, victim tag: 0x%04x", $time, calc_row, badr, ~mru[calc_row], ~mru[calc_row] ? way1_tags[calc_row] : way0_tags[calc_row]);
// If way is clean (no writes, so way is consistent with underlying SDRAM) then just discard way data
if( ( way0_flag == 2'b01 ) && mru[calc_row] ) state <= READ1;
else
if( ( way1_flag == 2'b01 ) && ~mru[calc_row] ) state <= READ1;
// Otherwise, if the way is dirty (has a write added to it since reading from SDRAM), flush it to memory first
else begin
$display("At %08d dirty flush for %d, 0x%06x, victim way %d", $time, calc_row, badr, ~mru[calc_row]);
state = FLUSH1;
end
end
end
end
// Reading from memory is a multi-state operation, first set the word (SDRAM) read signals
// This work in conjunction with the 2-clock R-C delay in the SDRAM
READ1 : begin
if( ~wack_i ) // If ACK is high then still ACKing a previous cycle(such as a flush), so wait
begin
wenable <= 1'b1; // Enable the word port
// wwe <= 1'b1; // Write enable the cache data block ram
wrd <= 1'b1; // Signal a read from the word port
// Discard LSB because we're reading words not bytes, but start from the first address needed,
// so we can immediately output the required byte after the first word is read from the SDRAM
wadr <= badr[23:1];
state <= READ2;
end
end
// Wait for the arbiter ack signal. If the SDRAM bus is in use, then we have to wait for the operation to complete
// before we can assert our request. The ACK input from the arbiter gives us that signal
READ2 : begin
if( wack_i ) begin
wwe <= 1'b1; // Write enable the cache data block ram
wenable <= 1'b0; // Deassert the word enable signal
wrd <= 1'b0; // and the read signal - the SDRAM controller has recorded the operation already
advance_cntr <= 0; // This signal ensures we don't advance the counter until ready
state <= READ3;
end
end
// Wait for the valid signal from the SDRAM controller, indicating data is available on the word input port
READ3 : if( wvalid_i ) begin
$display("Read %04x in to cache word memory location %x", mem_dat_alt/*wdat_i*/, block_ptr);
// Return the first byte immediately, for performance reasons
if( general_cntr == 3'd7 ) begin
// bdato <= badr[0] ? wdat_i[7:0] : wdat_i[15:8]; // Return the correct byte from the word
bdato <= badr[0] ? mem_dat_alt[7:0] : mem_dat_alt[15:8]; // Return the correct byte from the word
if( brd ) bvalid <= 1'b1; // Signal to the byte port that the data on the output is valid
end
// Update the flags and tag with the read data upon completion
if( general_cntr == 0 ) begin
// Update the flags + tag
if( hit_way == 1'b0 )
begin
way0_flags[calc_row] <= 2'b01;
way0_tags[calc_row] <= calc_tag;
end
else
begin
way1_flags[calc_row] <= 2'b01;
way1_tags[calc_row] <= calc_tag;
end
// Mark the way recently used
mru[calc_row] <= hit_way;
// If read, then we're done
if( ~bwr ) state <= IDLE;
// Otherwise go write to the cache ram from the byte port
else state <= WRITE1;
end
// Signal that we start to advance the counter every clock now (on the falling edge, next)
else advance_cntr <= 1;
end
// The data requested from the byte port is in the cache, so simply return that
// Give the cache ram 1 cycle to retrieve the data, then output
OUTPUT1 : state <= OUTPUT2;
// The cache ram itself is clocked constantly, so it always presents data on its output port, one clock delayed
OUTPUT2 : begin
// This data is transferred to the output ports on the falling edge of the clock, see the negedge block below
bdato <= bdato_wire[7:0];
bvalid <= 1;
state <= IDLE;
end
// Cache holds the correct memory line, so now just write data into the cache data memory
WRITE1 : begin
// Indicate cached write is complete (early indicator)
bvalid <= 1'b1;
// Update the flags with the dirty bit for either way 0 or 1
if( hit_way == 1'b0 ) way0_flags[calc_row] <= 2'b11;
else way1_flags[calc_row] <= 2'b11;
// Finished write to cache data, so return idle
state <= IDLE;
end
// This state flushes a dirty cache (written) back to the SDRAM
FLUSH1 : begin
// Stop the valid signal overwriting the cache, by disabling the write enable flag
wwe <= 1'b0;
// Enable the word port
wenable <= 1'b1;
// Indicate it's a write operation
wwr <= 1'b1;
// Output the address to the SDRAM port
wadr <= {(hit_way) ? way1_tag : way0_tag, calc_row, block_ptr }; // 23 bits of word address
// Move to the next step
state <= FLUSH2;
end
// This state waits for the SDRAM controller to indicate it's accepted the command
FLUSH2 : begin
if( wack_i ) begin
// Deassert the enable and write signals, but even while we're waiting,
// the data is being queued through the FIFO
wenable <= 1'b0;
wwr <= 1'b0;
advance_cntr <= 1'b0;
state <= FLUSH3;
end
end
// By now two bytes are queued in the FIFO, we wait for the valid signal before queuing any more
FLUSH3 : begin
advance_cntr <= wvalid_i; // Advance the counter if the SDRAM is ready
if( general_cntr == 7'd0 ) state <= READ1; // Flushed finished, go to read process
end
// Default operation just in case of a corruption - default is to reinitialise controller
default: state <= INIT1; // Self reset on unknown
endcase
// Update output signals on falling edge
always @(negedge clock_i)
begin
// Store memory line state for reading
mem_dat_alt <= wdat_i;
// Take action based on state
case( state )
// This state prepares to fill the arrays
INIT1: general_cntr <= ~8'd0;
// This state points to the next array location
INIT2: general_cntr <= general_cntr + 1'b1;
// Idle / wait processing
IDLE: begin
// Stop the write to the byte cache ram
write_ctl <= 1'b0;
end
// This state prepares to read 8 words
READ1: begin
general_cntr <= 3'd7;
// Move data through the FIFO - just in case the last operation was a flush - takes an extra clock cycle to output
wdat_fifo[0] <= wdat_fifo[1];
end
// This state prepares the cache line pointer
READ2: block_ptr <= wadr[2:0];
// This state will advance the counter if the SDRAM has signalled it's ready
READ3: begin
if( advance_cntr ) begin
// Adjust the address to the next location - this wraps if reading from a the middle of 16 byte block
block_ptr <= block_ptr + 1'b1;
general_cntr <= general_cntr - 1'b1;
end
end
// Write signal for the byte cache memory, it's reset automatically on idle
WRITE1 : write_ctl <= 1'b1;
// Flush 8 words, 2 is pre-loaded in FLUSH2 state, so counter is 6 rather than 8
FLUSH1 : begin
general_cntr <= 3'd6;
block_ptr <= 0;
end
// Fill top of cache, BUT only 2 bytes - if WACK takes a while we dont want to overflow the fifo!
FLUSH2 : if(block_ptr != 3'd2) begin
{wdat_fifo[0],wdat_fifo[1]} <= {wdat_fifo[1], wdato_wire};
block_ptr <= block_ptr + 1'b1;
end
// If the advance cntr flag is set, then we can continue to fill the FIFO
FLUSH3 : if( advance_cntr ) begin
// fill the fifo from the top
{wdat_fifo[0],wdat_fifo[1]} <= {wdat_fifo[1], wdato_wire};
// Adjust the address to the next location - this wraps if reading from a the middle of 8 word block
block_ptr <= block_ptr + 1'b1;
// Count down from 7 to 0
general_cntr <= general_cntr - 1'b1;
end
endcase
// Always update these output state signals for the word port
wenable_o <= wenable;
wrd_o <= wrd;
wwr_o <= wwr;
wadr_o <= wadr;
// Always update these output state signals for the byte port
bvalid_o <= bvalid;
bdat_o <= bdato;
end
endmodule |
module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule |
module sky130_fd_sc_lp__a211oi_m (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__a211oi_m (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule |
module TimeHoldOver_Qsys_mm_interconnect_0 (
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire nios2_gen2_0_reset_reset_bridge_in_reset_reset, // nios2_gen2_0_reset_reset_bridge_in_reset.reset
input wire [23:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
output wire nios2_gen2_0_data_master_readdatavalid, // .readdatavalid
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [23:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire nios2_gen2_0_instruction_master_readdatavalid, // .readdatavalid
output wire [4:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_address, // avalon_mapped_timer_reg_buf_0_avalon_slave_0.address
output wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_write, // .write
output wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_read, // .read
input wire [31:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata, // .readdata
output wire [31:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata, // .writedata
output wire [1:0] io_update_s1_address, // io_update_s1.address
output wire io_update_s1_write, // .write
input wire [31:0] io_update_s1_readdata, // .readdata
output wire [31:0] io_update_s1_writedata, // .writedata
output wire io_update_s1_chipselect, // .chipselect
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [9:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [1:0] pps_interrupt_s1_address, // pps_interrupt_s1.address
output wire pps_interrupt_s1_write, // .write
input wire [31:0] pps_interrupt_s1_readdata, // .readdata
output wire [31:0] pps_interrupt_s1_writedata, // .writedata
output wire pps_interrupt_s1_chipselect, // .chipselect
output wire [21:0] sdram_tri_controller_0_s1_address, // sdram_tri_controller_0_s1.address
output wire sdram_tri_controller_0_s1_write, // .write
output wire sdram_tri_controller_0_s1_read, // .read
input wire [15:0] sdram_tri_controller_0_s1_readdata, // .readdata
output wire [15:0] sdram_tri_controller_0_s1_writedata, // .writedata
output wire [1:0] sdram_tri_controller_0_s1_byteenable, // .byteenable
input wire sdram_tri_controller_0_s1_readdatavalid, // .readdatavalid
input wire sdram_tri_controller_0_s1_waitrequest, // .waitrequest
output wire [2:0] uart_0_s1_address, // uart_0_s1.address
output wire uart_0_s1_write, // .write
output wire uart_0_s1_read, // .read
input wire [15:0] uart_0_s1_readdata, // .readdata
output wire [15:0] uart_0_s1_writedata, // .writedata
output wire uart_0_s1_begintransfer, // .begintransfer
output wire uart_0_s1_chipselect, // .chipselect
output wire [2:0] uart_1_s1_address, // uart_1_s1.address
output wire uart_1_s1_write, // .write
output wire uart_1_s1_read, // .read
input wire [15:0] uart_1_s1_readdata, // .readdata
output wire [15:0] uart_1_s1_writedata, // .writedata
output wire uart_1_s1_begintransfer, // .begintransfer
output wire uart_1_s1_chipselect, // .chipselect
output wire [2:0] uart_2_s1_address, // uart_2_s1.address
output wire uart_2_s1_write, // .write
output wire uart_2_s1_read, // .read
input wire [15:0] uart_2_s1_readdata, // .readdata
output wire [15:0] uart_2_s1_writedata, // .writedata
output wire uart_2_s1_begintransfer, // .begintransfer
output wire uart_2_s1_chipselect, // .chipselect
output wire [2:0] uart_3_s1_address, // uart_3_s1.address
output wire uart_3_s1_write, // .write
output wire uart_3_s1_read, // .read
input wire [15:0] uart_3_s1_readdata, // .readdata
output wire [15:0] uart_3_s1_writedata, // .writedata
output wire uart_3_s1_begintransfer, // .begintransfer
output wire uart_3_s1_chipselect, // .chipselect
output wire [7:0] vic_0_csr_access_address, // vic_0_csr_access.address
output wire vic_0_csr_access_write, // .write
output wire vic_0_csr_access_read, // .read
input wire [31:0] vic_0_csr_access_readdata, // .readdata
output wire [31:0] vic_0_csr_access_writedata // .writedata
);
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [23:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [23:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire [31:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdata; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_readdata -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_readdata
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_waitrequest; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_waitrequest -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_waitrequest
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_debugaccess; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_debugaccess -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_debugaccess
wire [23:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_address; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_address -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_address
wire [3:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_byteenable; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_byteenable -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_byteenable
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_read; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_read -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_read
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdatavalid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_readdatavalid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_readdatavalid
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_lock; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_lock -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_lock
wire [31:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_writedata; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_writedata -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_writedata
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_write; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_write -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_write
wire [2:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_burstcount; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:m0_burstcount -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator:uav_burstcount
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_valid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_valid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [102:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_data; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_data -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_data
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_ready; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_ready -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_ready
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_startofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_startofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_endofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_source_endofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_valid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_valid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_valid
wire [102:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_data; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_data -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_data
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_ready; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_ready -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_startofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_valid
wire [101:0] cmd_mux_src_data; // cmd_mux:src_data -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_data
wire cmd_mux_src_ready; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_ready -> cmd_mux:src_ready
wire [10:0] cmd_mux_src_channel; // cmd_mux:src_channel -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:cp_endofpacket
wire [31:0] vic_0_csr_access_agent_m0_readdata; // vic_0_csr_access_translator:uav_readdata -> vic_0_csr_access_agent:m0_readdata
wire vic_0_csr_access_agent_m0_waitrequest; // vic_0_csr_access_translator:uav_waitrequest -> vic_0_csr_access_agent:m0_waitrequest
wire vic_0_csr_access_agent_m0_debugaccess; // vic_0_csr_access_agent:m0_debugaccess -> vic_0_csr_access_translator:uav_debugaccess
wire [23:0] vic_0_csr_access_agent_m0_address; // vic_0_csr_access_agent:m0_address -> vic_0_csr_access_translator:uav_address
wire [3:0] vic_0_csr_access_agent_m0_byteenable; // vic_0_csr_access_agent:m0_byteenable -> vic_0_csr_access_translator:uav_byteenable
wire vic_0_csr_access_agent_m0_read; // vic_0_csr_access_agent:m0_read -> vic_0_csr_access_translator:uav_read
wire vic_0_csr_access_agent_m0_readdatavalid; // vic_0_csr_access_translator:uav_readdatavalid -> vic_0_csr_access_agent:m0_readdatavalid
wire vic_0_csr_access_agent_m0_lock; // vic_0_csr_access_agent:m0_lock -> vic_0_csr_access_translator:uav_lock
wire [31:0] vic_0_csr_access_agent_m0_writedata; // vic_0_csr_access_agent:m0_writedata -> vic_0_csr_access_translator:uav_writedata
wire vic_0_csr_access_agent_m0_write; // vic_0_csr_access_agent:m0_write -> vic_0_csr_access_translator:uav_write
wire [2:0] vic_0_csr_access_agent_m0_burstcount; // vic_0_csr_access_agent:m0_burstcount -> vic_0_csr_access_translator:uav_burstcount
wire vic_0_csr_access_agent_rf_source_valid; // vic_0_csr_access_agent:rf_source_valid -> vic_0_csr_access_agent_rsp_fifo:in_valid
wire [102:0] vic_0_csr_access_agent_rf_source_data; // vic_0_csr_access_agent:rf_source_data -> vic_0_csr_access_agent_rsp_fifo:in_data
wire vic_0_csr_access_agent_rf_source_ready; // vic_0_csr_access_agent_rsp_fifo:in_ready -> vic_0_csr_access_agent:rf_source_ready
wire vic_0_csr_access_agent_rf_source_startofpacket; // vic_0_csr_access_agent:rf_source_startofpacket -> vic_0_csr_access_agent_rsp_fifo:in_startofpacket
wire vic_0_csr_access_agent_rf_source_endofpacket; // vic_0_csr_access_agent:rf_source_endofpacket -> vic_0_csr_access_agent_rsp_fifo:in_endofpacket
wire vic_0_csr_access_agent_rsp_fifo_out_valid; // vic_0_csr_access_agent_rsp_fifo:out_valid -> vic_0_csr_access_agent:rf_sink_valid
wire [102:0] vic_0_csr_access_agent_rsp_fifo_out_data; // vic_0_csr_access_agent_rsp_fifo:out_data -> vic_0_csr_access_agent:rf_sink_data
wire vic_0_csr_access_agent_rsp_fifo_out_ready; // vic_0_csr_access_agent:rf_sink_ready -> vic_0_csr_access_agent_rsp_fifo:out_ready
wire vic_0_csr_access_agent_rsp_fifo_out_startofpacket; // vic_0_csr_access_agent_rsp_fifo:out_startofpacket -> vic_0_csr_access_agent:rf_sink_startofpacket
wire vic_0_csr_access_agent_rsp_fifo_out_endofpacket; // vic_0_csr_access_agent_rsp_fifo:out_endofpacket -> vic_0_csr_access_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> vic_0_csr_access_agent:cp_valid
wire [101:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> vic_0_csr_access_agent:cp_data
wire cmd_mux_001_src_ready; // vic_0_csr_access_agent:cp_ready -> cmd_mux_001:src_ready
wire [10:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> vic_0_csr_access_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> vic_0_csr_access_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> vic_0_csr_access_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [23:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [102:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [102:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [101:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_002_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire [10:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] uart_0_s1_agent_m0_readdata; // uart_0_s1_translator:uav_readdata -> uart_0_s1_agent:m0_readdata
wire uart_0_s1_agent_m0_waitrequest; // uart_0_s1_translator:uav_waitrequest -> uart_0_s1_agent:m0_waitrequest
wire uart_0_s1_agent_m0_debugaccess; // uart_0_s1_agent:m0_debugaccess -> uart_0_s1_translator:uav_debugaccess
wire [23:0] uart_0_s1_agent_m0_address; // uart_0_s1_agent:m0_address -> uart_0_s1_translator:uav_address
wire [3:0] uart_0_s1_agent_m0_byteenable; // uart_0_s1_agent:m0_byteenable -> uart_0_s1_translator:uav_byteenable
wire uart_0_s1_agent_m0_read; // uart_0_s1_agent:m0_read -> uart_0_s1_translator:uav_read
wire uart_0_s1_agent_m0_readdatavalid; // uart_0_s1_translator:uav_readdatavalid -> uart_0_s1_agent:m0_readdatavalid
wire uart_0_s1_agent_m0_lock; // uart_0_s1_agent:m0_lock -> uart_0_s1_translator:uav_lock
wire [31:0] uart_0_s1_agent_m0_writedata; // uart_0_s1_agent:m0_writedata -> uart_0_s1_translator:uav_writedata
wire uart_0_s1_agent_m0_write; // uart_0_s1_agent:m0_write -> uart_0_s1_translator:uav_write
wire [2:0] uart_0_s1_agent_m0_burstcount; // uart_0_s1_agent:m0_burstcount -> uart_0_s1_translator:uav_burstcount
wire uart_0_s1_agent_rf_source_valid; // uart_0_s1_agent:rf_source_valid -> uart_0_s1_agent_rsp_fifo:in_valid
wire [102:0] uart_0_s1_agent_rf_source_data; // uart_0_s1_agent:rf_source_data -> uart_0_s1_agent_rsp_fifo:in_data
wire uart_0_s1_agent_rf_source_ready; // uart_0_s1_agent_rsp_fifo:in_ready -> uart_0_s1_agent:rf_source_ready
wire uart_0_s1_agent_rf_source_startofpacket; // uart_0_s1_agent:rf_source_startofpacket -> uart_0_s1_agent_rsp_fifo:in_startofpacket
wire uart_0_s1_agent_rf_source_endofpacket; // uart_0_s1_agent:rf_source_endofpacket -> uart_0_s1_agent_rsp_fifo:in_endofpacket
wire uart_0_s1_agent_rsp_fifo_out_valid; // uart_0_s1_agent_rsp_fifo:out_valid -> uart_0_s1_agent:rf_sink_valid
wire [102:0] uart_0_s1_agent_rsp_fifo_out_data; // uart_0_s1_agent_rsp_fifo:out_data -> uart_0_s1_agent:rf_sink_data
wire uart_0_s1_agent_rsp_fifo_out_ready; // uart_0_s1_agent:rf_sink_ready -> uart_0_s1_agent_rsp_fifo:out_ready
wire uart_0_s1_agent_rsp_fifo_out_startofpacket; // uart_0_s1_agent_rsp_fifo:out_startofpacket -> uart_0_s1_agent:rf_sink_startofpacket
wire uart_0_s1_agent_rsp_fifo_out_endofpacket; // uart_0_s1_agent_rsp_fifo:out_endofpacket -> uart_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> uart_0_s1_agent:cp_valid
wire [101:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> uart_0_s1_agent:cp_data
wire cmd_mux_003_src_ready; // uart_0_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [10:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> uart_0_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> uart_0_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> uart_0_s1_agent:cp_endofpacket
wire [31:0] uart_1_s1_agent_m0_readdata; // uart_1_s1_translator:uav_readdata -> uart_1_s1_agent:m0_readdata
wire uart_1_s1_agent_m0_waitrequest; // uart_1_s1_translator:uav_waitrequest -> uart_1_s1_agent:m0_waitrequest
wire uart_1_s1_agent_m0_debugaccess; // uart_1_s1_agent:m0_debugaccess -> uart_1_s1_translator:uav_debugaccess
wire [23:0] uart_1_s1_agent_m0_address; // uart_1_s1_agent:m0_address -> uart_1_s1_translator:uav_address
wire [3:0] uart_1_s1_agent_m0_byteenable; // uart_1_s1_agent:m0_byteenable -> uart_1_s1_translator:uav_byteenable
wire uart_1_s1_agent_m0_read; // uart_1_s1_agent:m0_read -> uart_1_s1_translator:uav_read
wire uart_1_s1_agent_m0_readdatavalid; // uart_1_s1_translator:uav_readdatavalid -> uart_1_s1_agent:m0_readdatavalid
wire uart_1_s1_agent_m0_lock; // uart_1_s1_agent:m0_lock -> uart_1_s1_translator:uav_lock
wire [31:0] uart_1_s1_agent_m0_writedata; // uart_1_s1_agent:m0_writedata -> uart_1_s1_translator:uav_writedata
wire uart_1_s1_agent_m0_write; // uart_1_s1_agent:m0_write -> uart_1_s1_translator:uav_write
wire [2:0] uart_1_s1_agent_m0_burstcount; // uart_1_s1_agent:m0_burstcount -> uart_1_s1_translator:uav_burstcount
wire uart_1_s1_agent_rf_source_valid; // uart_1_s1_agent:rf_source_valid -> uart_1_s1_agent_rsp_fifo:in_valid
wire [102:0] uart_1_s1_agent_rf_source_data; // uart_1_s1_agent:rf_source_data -> uart_1_s1_agent_rsp_fifo:in_data
wire uart_1_s1_agent_rf_source_ready; // uart_1_s1_agent_rsp_fifo:in_ready -> uart_1_s1_agent:rf_source_ready
wire uart_1_s1_agent_rf_source_startofpacket; // uart_1_s1_agent:rf_source_startofpacket -> uart_1_s1_agent_rsp_fifo:in_startofpacket
wire uart_1_s1_agent_rf_source_endofpacket; // uart_1_s1_agent:rf_source_endofpacket -> uart_1_s1_agent_rsp_fifo:in_endofpacket
wire uart_1_s1_agent_rsp_fifo_out_valid; // uart_1_s1_agent_rsp_fifo:out_valid -> uart_1_s1_agent:rf_sink_valid
wire [102:0] uart_1_s1_agent_rsp_fifo_out_data; // uart_1_s1_agent_rsp_fifo:out_data -> uart_1_s1_agent:rf_sink_data
wire uart_1_s1_agent_rsp_fifo_out_ready; // uart_1_s1_agent:rf_sink_ready -> uart_1_s1_agent_rsp_fifo:out_ready
wire uart_1_s1_agent_rsp_fifo_out_startofpacket; // uart_1_s1_agent_rsp_fifo:out_startofpacket -> uart_1_s1_agent:rf_sink_startofpacket
wire uart_1_s1_agent_rsp_fifo_out_endofpacket; // uart_1_s1_agent_rsp_fifo:out_endofpacket -> uart_1_s1_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> uart_1_s1_agent:cp_valid
wire [101:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> uart_1_s1_agent:cp_data
wire cmd_mux_004_src_ready; // uart_1_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [10:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> uart_1_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> uart_1_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> uart_1_s1_agent:cp_endofpacket
wire [31:0] uart_2_s1_agent_m0_readdata; // uart_2_s1_translator:uav_readdata -> uart_2_s1_agent:m0_readdata
wire uart_2_s1_agent_m0_waitrequest; // uart_2_s1_translator:uav_waitrequest -> uart_2_s1_agent:m0_waitrequest
wire uart_2_s1_agent_m0_debugaccess; // uart_2_s1_agent:m0_debugaccess -> uart_2_s1_translator:uav_debugaccess
wire [23:0] uart_2_s1_agent_m0_address; // uart_2_s1_agent:m0_address -> uart_2_s1_translator:uav_address
wire [3:0] uart_2_s1_agent_m0_byteenable; // uart_2_s1_agent:m0_byteenable -> uart_2_s1_translator:uav_byteenable
wire uart_2_s1_agent_m0_read; // uart_2_s1_agent:m0_read -> uart_2_s1_translator:uav_read
wire uart_2_s1_agent_m0_readdatavalid; // uart_2_s1_translator:uav_readdatavalid -> uart_2_s1_agent:m0_readdatavalid
wire uart_2_s1_agent_m0_lock; // uart_2_s1_agent:m0_lock -> uart_2_s1_translator:uav_lock
wire [31:0] uart_2_s1_agent_m0_writedata; // uart_2_s1_agent:m0_writedata -> uart_2_s1_translator:uav_writedata
wire uart_2_s1_agent_m0_write; // uart_2_s1_agent:m0_write -> uart_2_s1_translator:uav_write
wire [2:0] uart_2_s1_agent_m0_burstcount; // uart_2_s1_agent:m0_burstcount -> uart_2_s1_translator:uav_burstcount
wire uart_2_s1_agent_rf_source_valid; // uart_2_s1_agent:rf_source_valid -> uart_2_s1_agent_rsp_fifo:in_valid
wire [102:0] uart_2_s1_agent_rf_source_data; // uart_2_s1_agent:rf_source_data -> uart_2_s1_agent_rsp_fifo:in_data
wire uart_2_s1_agent_rf_source_ready; // uart_2_s1_agent_rsp_fifo:in_ready -> uart_2_s1_agent:rf_source_ready
wire uart_2_s1_agent_rf_source_startofpacket; // uart_2_s1_agent:rf_source_startofpacket -> uart_2_s1_agent_rsp_fifo:in_startofpacket
wire uart_2_s1_agent_rf_source_endofpacket; // uart_2_s1_agent:rf_source_endofpacket -> uart_2_s1_agent_rsp_fifo:in_endofpacket
wire uart_2_s1_agent_rsp_fifo_out_valid; // uart_2_s1_agent_rsp_fifo:out_valid -> uart_2_s1_agent:rf_sink_valid
wire [102:0] uart_2_s1_agent_rsp_fifo_out_data; // uart_2_s1_agent_rsp_fifo:out_data -> uart_2_s1_agent:rf_sink_data
wire uart_2_s1_agent_rsp_fifo_out_ready; // uart_2_s1_agent:rf_sink_ready -> uart_2_s1_agent_rsp_fifo:out_ready
wire uart_2_s1_agent_rsp_fifo_out_startofpacket; // uart_2_s1_agent_rsp_fifo:out_startofpacket -> uart_2_s1_agent:rf_sink_startofpacket
wire uart_2_s1_agent_rsp_fifo_out_endofpacket; // uart_2_s1_agent_rsp_fifo:out_endofpacket -> uart_2_s1_agent:rf_sink_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> uart_2_s1_agent:cp_valid
wire [101:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> uart_2_s1_agent:cp_data
wire cmd_mux_005_src_ready; // uart_2_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [10:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> uart_2_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> uart_2_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> uart_2_s1_agent:cp_endofpacket
wire [31:0] uart_3_s1_agent_m0_readdata; // uart_3_s1_translator:uav_readdata -> uart_3_s1_agent:m0_readdata
wire uart_3_s1_agent_m0_waitrequest; // uart_3_s1_translator:uav_waitrequest -> uart_3_s1_agent:m0_waitrequest
wire uart_3_s1_agent_m0_debugaccess; // uart_3_s1_agent:m0_debugaccess -> uart_3_s1_translator:uav_debugaccess
wire [23:0] uart_3_s1_agent_m0_address; // uart_3_s1_agent:m0_address -> uart_3_s1_translator:uav_address
wire [3:0] uart_3_s1_agent_m0_byteenable; // uart_3_s1_agent:m0_byteenable -> uart_3_s1_translator:uav_byteenable
wire uart_3_s1_agent_m0_read; // uart_3_s1_agent:m0_read -> uart_3_s1_translator:uav_read
wire uart_3_s1_agent_m0_readdatavalid; // uart_3_s1_translator:uav_readdatavalid -> uart_3_s1_agent:m0_readdatavalid
wire uart_3_s1_agent_m0_lock; // uart_3_s1_agent:m0_lock -> uart_3_s1_translator:uav_lock
wire [31:0] uart_3_s1_agent_m0_writedata; // uart_3_s1_agent:m0_writedata -> uart_3_s1_translator:uav_writedata
wire uart_3_s1_agent_m0_write; // uart_3_s1_agent:m0_write -> uart_3_s1_translator:uav_write
wire [2:0] uart_3_s1_agent_m0_burstcount; // uart_3_s1_agent:m0_burstcount -> uart_3_s1_translator:uav_burstcount
wire uart_3_s1_agent_rf_source_valid; // uart_3_s1_agent:rf_source_valid -> uart_3_s1_agent_rsp_fifo:in_valid
wire [102:0] uart_3_s1_agent_rf_source_data; // uart_3_s1_agent:rf_source_data -> uart_3_s1_agent_rsp_fifo:in_data
wire uart_3_s1_agent_rf_source_ready; // uart_3_s1_agent_rsp_fifo:in_ready -> uart_3_s1_agent:rf_source_ready
wire uart_3_s1_agent_rf_source_startofpacket; // uart_3_s1_agent:rf_source_startofpacket -> uart_3_s1_agent_rsp_fifo:in_startofpacket
wire uart_3_s1_agent_rf_source_endofpacket; // uart_3_s1_agent:rf_source_endofpacket -> uart_3_s1_agent_rsp_fifo:in_endofpacket
wire uart_3_s1_agent_rsp_fifo_out_valid; // uart_3_s1_agent_rsp_fifo:out_valid -> uart_3_s1_agent:rf_sink_valid
wire [102:0] uart_3_s1_agent_rsp_fifo_out_data; // uart_3_s1_agent_rsp_fifo:out_data -> uart_3_s1_agent:rf_sink_data
wire uart_3_s1_agent_rsp_fifo_out_ready; // uart_3_s1_agent:rf_sink_ready -> uart_3_s1_agent_rsp_fifo:out_ready
wire uart_3_s1_agent_rsp_fifo_out_startofpacket; // uart_3_s1_agent_rsp_fifo:out_startofpacket -> uart_3_s1_agent:rf_sink_startofpacket
wire uart_3_s1_agent_rsp_fifo_out_endofpacket; // uart_3_s1_agent_rsp_fifo:out_endofpacket -> uart_3_s1_agent:rf_sink_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> uart_3_s1_agent:cp_valid
wire [101:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> uart_3_s1_agent:cp_data
wire cmd_mux_006_src_ready; // uart_3_s1_agent:cp_ready -> cmd_mux_006:src_ready
wire [10:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> uart_3_s1_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> uart_3_s1_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> uart_3_s1_agent:cp_endofpacket
wire [15:0] sdram_tri_controller_0_s1_agent_m0_readdata; // sdram_tri_controller_0_s1_translator:uav_readdata -> sdram_tri_controller_0_s1_agent:m0_readdata
wire sdram_tri_controller_0_s1_agent_m0_waitrequest; // sdram_tri_controller_0_s1_translator:uav_waitrequest -> sdram_tri_controller_0_s1_agent:m0_waitrequest
wire sdram_tri_controller_0_s1_agent_m0_debugaccess; // sdram_tri_controller_0_s1_agent:m0_debugaccess -> sdram_tri_controller_0_s1_translator:uav_debugaccess
wire [23:0] sdram_tri_controller_0_s1_agent_m0_address; // sdram_tri_controller_0_s1_agent:m0_address -> sdram_tri_controller_0_s1_translator:uav_address
wire [1:0] sdram_tri_controller_0_s1_agent_m0_byteenable; // sdram_tri_controller_0_s1_agent:m0_byteenable -> sdram_tri_controller_0_s1_translator:uav_byteenable
wire sdram_tri_controller_0_s1_agent_m0_read; // sdram_tri_controller_0_s1_agent:m0_read -> sdram_tri_controller_0_s1_translator:uav_read
wire sdram_tri_controller_0_s1_agent_m0_readdatavalid; // sdram_tri_controller_0_s1_translator:uav_readdatavalid -> sdram_tri_controller_0_s1_agent:m0_readdatavalid
wire sdram_tri_controller_0_s1_agent_m0_lock; // sdram_tri_controller_0_s1_agent:m0_lock -> sdram_tri_controller_0_s1_translator:uav_lock
wire [15:0] sdram_tri_controller_0_s1_agent_m0_writedata; // sdram_tri_controller_0_s1_agent:m0_writedata -> sdram_tri_controller_0_s1_translator:uav_writedata
wire sdram_tri_controller_0_s1_agent_m0_write; // sdram_tri_controller_0_s1_agent:m0_write -> sdram_tri_controller_0_s1_translator:uav_write
wire [1:0] sdram_tri_controller_0_s1_agent_m0_burstcount; // sdram_tri_controller_0_s1_agent:m0_burstcount -> sdram_tri_controller_0_s1_translator:uav_burstcount
wire sdram_tri_controller_0_s1_agent_rf_source_valid; // sdram_tri_controller_0_s1_agent:rf_source_valid -> sdram_tri_controller_0_s1_agent_rsp_fifo:in_valid
wire [84:0] sdram_tri_controller_0_s1_agent_rf_source_data; // sdram_tri_controller_0_s1_agent:rf_source_data -> sdram_tri_controller_0_s1_agent_rsp_fifo:in_data
wire sdram_tri_controller_0_s1_agent_rf_source_ready; // sdram_tri_controller_0_s1_agent_rsp_fifo:in_ready -> sdram_tri_controller_0_s1_agent:rf_source_ready
wire sdram_tri_controller_0_s1_agent_rf_source_startofpacket; // sdram_tri_controller_0_s1_agent:rf_source_startofpacket -> sdram_tri_controller_0_s1_agent_rsp_fifo:in_startofpacket
wire sdram_tri_controller_0_s1_agent_rf_source_endofpacket; // sdram_tri_controller_0_s1_agent:rf_source_endofpacket -> sdram_tri_controller_0_s1_agent_rsp_fifo:in_endofpacket
wire sdram_tri_controller_0_s1_agent_rsp_fifo_out_valid; // sdram_tri_controller_0_s1_agent_rsp_fifo:out_valid -> sdram_tri_controller_0_s1_agent:rf_sink_valid
wire [84:0] sdram_tri_controller_0_s1_agent_rsp_fifo_out_data; // sdram_tri_controller_0_s1_agent_rsp_fifo:out_data -> sdram_tri_controller_0_s1_agent:rf_sink_data
wire sdram_tri_controller_0_s1_agent_rsp_fifo_out_ready; // sdram_tri_controller_0_s1_agent:rf_sink_ready -> sdram_tri_controller_0_s1_agent_rsp_fifo:out_ready
wire sdram_tri_controller_0_s1_agent_rsp_fifo_out_startofpacket; // sdram_tri_controller_0_s1_agent_rsp_fifo:out_startofpacket -> sdram_tri_controller_0_s1_agent:rf_sink_startofpacket
wire sdram_tri_controller_0_s1_agent_rsp_fifo_out_endofpacket; // sdram_tri_controller_0_s1_agent_rsp_fifo:out_endofpacket -> sdram_tri_controller_0_s1_agent:rf_sink_endofpacket
wire sdram_tri_controller_0_s1_agent_rdata_fifo_src_valid; // sdram_tri_controller_0_s1_agent:rdata_fifo_src_valid -> sdram_tri_controller_0_s1_agent_rdata_fifo:in_valid
wire [17:0] sdram_tri_controller_0_s1_agent_rdata_fifo_src_data; // sdram_tri_controller_0_s1_agent:rdata_fifo_src_data -> sdram_tri_controller_0_s1_agent_rdata_fifo:in_data
wire sdram_tri_controller_0_s1_agent_rdata_fifo_src_ready; // sdram_tri_controller_0_s1_agent_rdata_fifo:in_ready -> sdram_tri_controller_0_s1_agent:rdata_fifo_src_ready
wire [31:0] io_update_s1_agent_m0_readdata; // io_update_s1_translator:uav_readdata -> io_update_s1_agent:m0_readdata
wire io_update_s1_agent_m0_waitrequest; // io_update_s1_translator:uav_waitrequest -> io_update_s1_agent:m0_waitrequest
wire io_update_s1_agent_m0_debugaccess; // io_update_s1_agent:m0_debugaccess -> io_update_s1_translator:uav_debugaccess
wire [23:0] io_update_s1_agent_m0_address; // io_update_s1_agent:m0_address -> io_update_s1_translator:uav_address
wire [3:0] io_update_s1_agent_m0_byteenable; // io_update_s1_agent:m0_byteenable -> io_update_s1_translator:uav_byteenable
wire io_update_s1_agent_m0_read; // io_update_s1_agent:m0_read -> io_update_s1_translator:uav_read
wire io_update_s1_agent_m0_readdatavalid; // io_update_s1_translator:uav_readdatavalid -> io_update_s1_agent:m0_readdatavalid
wire io_update_s1_agent_m0_lock; // io_update_s1_agent:m0_lock -> io_update_s1_translator:uav_lock
wire [31:0] io_update_s1_agent_m0_writedata; // io_update_s1_agent:m0_writedata -> io_update_s1_translator:uav_writedata
wire io_update_s1_agent_m0_write; // io_update_s1_agent:m0_write -> io_update_s1_translator:uav_write
wire [2:0] io_update_s1_agent_m0_burstcount; // io_update_s1_agent:m0_burstcount -> io_update_s1_translator:uav_burstcount
wire io_update_s1_agent_rf_source_valid; // io_update_s1_agent:rf_source_valid -> io_update_s1_agent_rsp_fifo:in_valid
wire [102:0] io_update_s1_agent_rf_source_data; // io_update_s1_agent:rf_source_data -> io_update_s1_agent_rsp_fifo:in_data
wire io_update_s1_agent_rf_source_ready; // io_update_s1_agent_rsp_fifo:in_ready -> io_update_s1_agent:rf_source_ready
wire io_update_s1_agent_rf_source_startofpacket; // io_update_s1_agent:rf_source_startofpacket -> io_update_s1_agent_rsp_fifo:in_startofpacket
wire io_update_s1_agent_rf_source_endofpacket; // io_update_s1_agent:rf_source_endofpacket -> io_update_s1_agent_rsp_fifo:in_endofpacket
wire io_update_s1_agent_rsp_fifo_out_valid; // io_update_s1_agent_rsp_fifo:out_valid -> io_update_s1_agent:rf_sink_valid
wire [102:0] io_update_s1_agent_rsp_fifo_out_data; // io_update_s1_agent_rsp_fifo:out_data -> io_update_s1_agent:rf_sink_data
wire io_update_s1_agent_rsp_fifo_out_ready; // io_update_s1_agent:rf_sink_ready -> io_update_s1_agent_rsp_fifo:out_ready
wire io_update_s1_agent_rsp_fifo_out_startofpacket; // io_update_s1_agent_rsp_fifo:out_startofpacket -> io_update_s1_agent:rf_sink_startofpacket
wire io_update_s1_agent_rsp_fifo_out_endofpacket; // io_update_s1_agent_rsp_fifo:out_endofpacket -> io_update_s1_agent:rf_sink_endofpacket
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> io_update_s1_agent:cp_valid
wire [101:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> io_update_s1_agent:cp_data
wire cmd_mux_008_src_ready; // io_update_s1_agent:cp_ready -> cmd_mux_008:src_ready
wire [10:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> io_update_s1_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> io_update_s1_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> io_update_s1_agent:cp_endofpacket
wire [31:0] pps_interrupt_s1_agent_m0_readdata; // pps_interrupt_s1_translator:uav_readdata -> pps_interrupt_s1_agent:m0_readdata
wire pps_interrupt_s1_agent_m0_waitrequest; // pps_interrupt_s1_translator:uav_waitrequest -> pps_interrupt_s1_agent:m0_waitrequest
wire pps_interrupt_s1_agent_m0_debugaccess; // pps_interrupt_s1_agent:m0_debugaccess -> pps_interrupt_s1_translator:uav_debugaccess
wire [23:0] pps_interrupt_s1_agent_m0_address; // pps_interrupt_s1_agent:m0_address -> pps_interrupt_s1_translator:uav_address
wire [3:0] pps_interrupt_s1_agent_m0_byteenable; // pps_interrupt_s1_agent:m0_byteenable -> pps_interrupt_s1_translator:uav_byteenable
wire pps_interrupt_s1_agent_m0_read; // pps_interrupt_s1_agent:m0_read -> pps_interrupt_s1_translator:uav_read
wire pps_interrupt_s1_agent_m0_readdatavalid; // pps_interrupt_s1_translator:uav_readdatavalid -> pps_interrupt_s1_agent:m0_readdatavalid
wire pps_interrupt_s1_agent_m0_lock; // pps_interrupt_s1_agent:m0_lock -> pps_interrupt_s1_translator:uav_lock
wire [31:0] pps_interrupt_s1_agent_m0_writedata; // pps_interrupt_s1_agent:m0_writedata -> pps_interrupt_s1_translator:uav_writedata
wire pps_interrupt_s1_agent_m0_write; // pps_interrupt_s1_agent:m0_write -> pps_interrupt_s1_translator:uav_write
wire [2:0] pps_interrupt_s1_agent_m0_burstcount; // pps_interrupt_s1_agent:m0_burstcount -> pps_interrupt_s1_translator:uav_burstcount
wire pps_interrupt_s1_agent_rf_source_valid; // pps_interrupt_s1_agent:rf_source_valid -> pps_interrupt_s1_agent_rsp_fifo:in_valid
wire [102:0] pps_interrupt_s1_agent_rf_source_data; // pps_interrupt_s1_agent:rf_source_data -> pps_interrupt_s1_agent_rsp_fifo:in_data
wire pps_interrupt_s1_agent_rf_source_ready; // pps_interrupt_s1_agent_rsp_fifo:in_ready -> pps_interrupt_s1_agent:rf_source_ready
wire pps_interrupt_s1_agent_rf_source_startofpacket; // pps_interrupt_s1_agent:rf_source_startofpacket -> pps_interrupt_s1_agent_rsp_fifo:in_startofpacket
wire pps_interrupt_s1_agent_rf_source_endofpacket; // pps_interrupt_s1_agent:rf_source_endofpacket -> pps_interrupt_s1_agent_rsp_fifo:in_endofpacket
wire pps_interrupt_s1_agent_rsp_fifo_out_valid; // pps_interrupt_s1_agent_rsp_fifo:out_valid -> pps_interrupt_s1_agent:rf_sink_valid
wire [102:0] pps_interrupt_s1_agent_rsp_fifo_out_data; // pps_interrupt_s1_agent_rsp_fifo:out_data -> pps_interrupt_s1_agent:rf_sink_data
wire pps_interrupt_s1_agent_rsp_fifo_out_ready; // pps_interrupt_s1_agent:rf_sink_ready -> pps_interrupt_s1_agent_rsp_fifo:out_ready
wire pps_interrupt_s1_agent_rsp_fifo_out_startofpacket; // pps_interrupt_s1_agent_rsp_fifo:out_startofpacket -> pps_interrupt_s1_agent:rf_sink_startofpacket
wire pps_interrupt_s1_agent_rsp_fifo_out_endofpacket; // pps_interrupt_s1_agent_rsp_fifo:out_endofpacket -> pps_interrupt_s1_agent:rf_sink_endofpacket
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> pps_interrupt_s1_agent:cp_valid
wire [101:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> pps_interrupt_s1_agent:cp_data
wire cmd_mux_009_src_ready; // pps_interrupt_s1_agent:cp_ready -> cmd_mux_009:src_ready
wire [10:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> pps_interrupt_s1_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> pps_interrupt_s1_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> pps_interrupt_s1_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [23:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [102:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [102:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_010_src_valid; // cmd_mux_010:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [101:0] cmd_mux_010_src_data; // cmd_mux_010:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_010_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_010:src_ready
wire [10:0] cmd_mux_010_src_channel; // cmd_mux_010:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_010_src_startofpacket; // cmd_mux_010:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_010_src_endofpacket; // cmd_mux_010:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router:sink_valid
wire [101:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [101:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_valid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_valid -> router_002:sink_valid
wire [101:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_data; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_data -> router_002:sink_data
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_ready; // router_002:sink_ready -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_ready
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_startofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_startofpacket -> router_002:sink_startofpacket
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_endofpacket; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [101:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [10:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire vic_0_csr_access_agent_rp_valid; // vic_0_csr_access_agent:rp_valid -> router_003:sink_valid
wire [101:0] vic_0_csr_access_agent_rp_data; // vic_0_csr_access_agent:rp_data -> router_003:sink_data
wire vic_0_csr_access_agent_rp_ready; // router_003:sink_ready -> vic_0_csr_access_agent:rp_ready
wire vic_0_csr_access_agent_rp_startofpacket; // vic_0_csr_access_agent:rp_startofpacket -> router_003:sink_startofpacket
wire vic_0_csr_access_agent_rp_endofpacket; // vic_0_csr_access_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [101:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [10:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_004:sink_valid
wire [101:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_004:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_004:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [101:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [10:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire uart_0_s1_agent_rp_valid; // uart_0_s1_agent:rp_valid -> router_005:sink_valid
wire [101:0] uart_0_s1_agent_rp_data; // uart_0_s1_agent:rp_data -> router_005:sink_data
wire uart_0_s1_agent_rp_ready; // router_005:sink_ready -> uart_0_s1_agent:rp_ready
wire uart_0_s1_agent_rp_startofpacket; // uart_0_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire uart_0_s1_agent_rp_endofpacket; // uart_0_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [101:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [10:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire uart_1_s1_agent_rp_valid; // uart_1_s1_agent:rp_valid -> router_006:sink_valid
wire [101:0] uart_1_s1_agent_rp_data; // uart_1_s1_agent:rp_data -> router_006:sink_data
wire uart_1_s1_agent_rp_ready; // router_006:sink_ready -> uart_1_s1_agent:rp_ready
wire uart_1_s1_agent_rp_startofpacket; // uart_1_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire uart_1_s1_agent_rp_endofpacket; // uart_1_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [101:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [10:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire uart_2_s1_agent_rp_valid; // uart_2_s1_agent:rp_valid -> router_007:sink_valid
wire [101:0] uart_2_s1_agent_rp_data; // uart_2_s1_agent:rp_data -> router_007:sink_data
wire uart_2_s1_agent_rp_ready; // router_007:sink_ready -> uart_2_s1_agent:rp_ready
wire uart_2_s1_agent_rp_startofpacket; // uart_2_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire uart_2_s1_agent_rp_endofpacket; // uart_2_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [101:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [10:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire uart_3_s1_agent_rp_valid; // uart_3_s1_agent:rp_valid -> router_008:sink_valid
wire [101:0] uart_3_s1_agent_rp_data; // uart_3_s1_agent:rp_data -> router_008:sink_data
wire uart_3_s1_agent_rp_ready; // router_008:sink_ready -> uart_3_s1_agent:rp_ready
wire uart_3_s1_agent_rp_startofpacket; // uart_3_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
wire uart_3_s1_agent_rp_endofpacket; // uart_3_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [101:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [10:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire sdram_tri_controller_0_s1_agent_rp_valid; // sdram_tri_controller_0_s1_agent:rp_valid -> router_009:sink_valid
wire [83:0] sdram_tri_controller_0_s1_agent_rp_data; // sdram_tri_controller_0_s1_agent:rp_data -> router_009:sink_data
wire sdram_tri_controller_0_s1_agent_rp_ready; // router_009:sink_ready -> sdram_tri_controller_0_s1_agent:rp_ready
wire sdram_tri_controller_0_s1_agent_rp_startofpacket; // sdram_tri_controller_0_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire sdram_tri_controller_0_s1_agent_rp_endofpacket; // sdram_tri_controller_0_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire io_update_s1_agent_rp_valid; // io_update_s1_agent:rp_valid -> router_010:sink_valid
wire [101:0] io_update_s1_agent_rp_data; // io_update_s1_agent:rp_data -> router_010:sink_data
wire io_update_s1_agent_rp_ready; // router_010:sink_ready -> io_update_s1_agent:rp_ready
wire io_update_s1_agent_rp_startofpacket; // io_update_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire io_update_s1_agent_rp_endofpacket; // io_update_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_008:sink_valid
wire [101:0] router_010_src_data; // router_010:src_data -> rsp_demux_008:sink_data
wire router_010_src_ready; // rsp_demux_008:sink_ready -> router_010:src_ready
wire [10:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_008:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire pps_interrupt_s1_agent_rp_valid; // pps_interrupt_s1_agent:rp_valid -> router_011:sink_valid
wire [101:0] pps_interrupt_s1_agent_rp_data; // pps_interrupt_s1_agent:rp_data -> router_011:sink_data
wire pps_interrupt_s1_agent_rp_ready; // router_011:sink_ready -> pps_interrupt_s1_agent:rp_ready
wire pps_interrupt_s1_agent_rp_startofpacket; // pps_interrupt_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
wire pps_interrupt_s1_agent_rp_endofpacket; // pps_interrupt_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_009:sink_valid
wire [101:0] router_011_src_data; // router_011:src_data -> rsp_demux_009:sink_data
wire router_011_src_ready; // rsp_demux_009:sink_ready -> router_011:src_ready
wire [10:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_009:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_012:sink_valid
wire [101:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_012:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_012:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
wire router_012_src_valid; // router_012:src_valid -> rsp_demux_010:sink_valid
wire [101:0] router_012_src_data; // router_012:src_data -> rsp_demux_010:sink_data
wire router_012_src_ready; // rsp_demux_010:sink_ready -> router_012:src_ready
wire [10:0] router_012_src_channel; // router_012:src_channel -> rsp_demux_010:sink_channel
wire router_012_src_startofpacket; // router_012:src_startofpacket -> rsp_demux_010:sink_startofpacket
wire router_012_src_endofpacket; // router_012:src_endofpacket -> rsp_demux_010:sink_endofpacket
wire router_src_valid; // router:src_valid -> nios2_gen2_0_data_master_limiter:cmd_sink_valid
wire [101:0] router_src_data; // router:src_data -> nios2_gen2_0_data_master_limiter:cmd_sink_data
wire router_src_ready; // nios2_gen2_0_data_master_limiter:cmd_sink_ready -> router:src_ready
wire [10:0] router_src_channel; // router:src_channel -> nios2_gen2_0_data_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> nios2_gen2_0_data_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> nios2_gen2_0_data_master_limiter:cmd_sink_endofpacket
wire [101:0] nios2_gen2_0_data_master_limiter_cmd_src_data; // nios2_gen2_0_data_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire nios2_gen2_0_data_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> nios2_gen2_0_data_master_limiter:cmd_src_ready
wire [10:0] nios2_gen2_0_data_master_limiter_cmd_src_channel; // nios2_gen2_0_data_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire nios2_gen2_0_data_master_limiter_cmd_src_startofpacket; // nios2_gen2_0_data_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire nios2_gen2_0_data_master_limiter_cmd_src_endofpacket; // nios2_gen2_0_data_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_gen2_0_data_master_limiter:rsp_sink_valid
wire [101:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_gen2_0_data_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // nios2_gen2_0_data_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [10:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_gen2_0_data_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_gen2_0_data_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_gen2_0_data_master_limiter:rsp_sink_endofpacket
wire nios2_gen2_0_data_master_limiter_rsp_src_valid; // nios2_gen2_0_data_master_limiter:rsp_src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [101:0] nios2_gen2_0_data_master_limiter_rsp_src_data; // nios2_gen2_0_data_master_limiter:rsp_src_data -> nios2_gen2_0_data_master_agent:rp_data
wire nios2_gen2_0_data_master_limiter_rsp_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> nios2_gen2_0_data_master_limiter:rsp_src_ready
wire [10:0] nios2_gen2_0_data_master_limiter_rsp_src_channel; // nios2_gen2_0_data_master_limiter:rsp_src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire nios2_gen2_0_data_master_limiter_rsp_src_startofpacket; // nios2_gen2_0_data_master_limiter:rsp_src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire nios2_gen2_0_data_master_limiter_rsp_src_endofpacket; // nios2_gen2_0_data_master_limiter:rsp_src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> nios2_gen2_0_instruction_master_limiter:cmd_sink_valid
wire [101:0] router_001_src_data; // router_001:src_data -> nios2_gen2_0_instruction_master_limiter:cmd_sink_data
wire router_001_src_ready; // nios2_gen2_0_instruction_master_limiter:cmd_sink_ready -> router_001:src_ready
wire [10:0] router_001_src_channel; // router_001:src_channel -> nios2_gen2_0_instruction_master_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> nios2_gen2_0_instruction_master_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> nios2_gen2_0_instruction_master_limiter:cmd_sink_endofpacket
wire [101:0] nios2_gen2_0_instruction_master_limiter_cmd_src_data; // nios2_gen2_0_instruction_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire nios2_gen2_0_instruction_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> nios2_gen2_0_instruction_master_limiter:cmd_src_ready
wire [10:0] nios2_gen2_0_instruction_master_limiter_cmd_src_channel; // nios2_gen2_0_instruction_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket; // nios2_gen2_0_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket; // nios2_gen2_0_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_instruction_master_limiter:rsp_sink_valid
wire [101:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_instruction_master_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_instruction_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [10:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_instruction_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_instruction_master_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_instruction_master_limiter:rsp_sink_endofpacket
wire nios2_gen2_0_instruction_master_limiter_rsp_src_valid; // nios2_gen2_0_instruction_master_limiter:rsp_src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [101:0] nios2_gen2_0_instruction_master_limiter_rsp_src_data; // nios2_gen2_0_instruction_master_limiter:rsp_src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire nios2_gen2_0_instruction_master_limiter_rsp_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> nios2_gen2_0_instruction_master_limiter:rsp_src_ready
wire [10:0] nios2_gen2_0_instruction_master_limiter_rsp_src_channel; // nios2_gen2_0_instruction_master_limiter:rsp_src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket; // nios2_gen2_0_instruction_master_limiter:rsp_src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket; // nios2_gen2_0_instruction_master_limiter:rsp_src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire sdram_tri_controller_0_s1_burst_adapter_source0_valid; // sdram_tri_controller_0_s1_burst_adapter:source0_valid -> sdram_tri_controller_0_s1_agent:cp_valid
wire [83:0] sdram_tri_controller_0_s1_burst_adapter_source0_data; // sdram_tri_controller_0_s1_burst_adapter:source0_data -> sdram_tri_controller_0_s1_agent:cp_data
wire sdram_tri_controller_0_s1_burst_adapter_source0_ready; // sdram_tri_controller_0_s1_agent:cp_ready -> sdram_tri_controller_0_s1_burst_adapter:source0_ready
wire [10:0] sdram_tri_controller_0_s1_burst_adapter_source0_channel; // sdram_tri_controller_0_s1_burst_adapter:source0_channel -> sdram_tri_controller_0_s1_agent:cp_channel
wire sdram_tri_controller_0_s1_burst_adapter_source0_startofpacket; // sdram_tri_controller_0_s1_burst_adapter:source0_startofpacket -> sdram_tri_controller_0_s1_agent:cp_startofpacket
wire sdram_tri_controller_0_s1_burst_adapter_source0_endofpacket; // sdram_tri_controller_0_s1_burst_adapter:source0_endofpacket -> sdram_tri_controller_0_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [101:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [10:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [101:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [10:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [101:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [10:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [101:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [10:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [101:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [10:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [101:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [10:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire [101:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire [10:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [101:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [10:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_src8_valid; // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
wire [101:0] cmd_demux_src8_data; // cmd_demux:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
wire [10:0] cmd_demux_src8_channel; // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_src8_startofpacket; // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_src8_endofpacket; // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_src9_valid; // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
wire [101:0] cmd_demux_src9_data; // cmd_demux:src9_data -> cmd_mux_009:sink0_data
wire cmd_demux_src9_ready; // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
wire [10:0] cmd_demux_src9_channel; // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_src9_startofpacket; // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_src9_endofpacket; // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
wire cmd_demux_src10_valid; // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
wire [101:0] cmd_demux_src10_data; // cmd_demux:src10_data -> cmd_mux_010:sink0_data
wire cmd_demux_src10_ready; // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
wire [10:0] cmd_demux_src10_channel; // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
wire cmd_demux_src10_startofpacket; // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
wire cmd_demux_src10_endofpacket; // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [101:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [10:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire [101:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire [10:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
wire [101:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
wire [10:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink1_valid
wire [101:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink1_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink1_ready -> cmd_demux_001:src3_ready
wire [10:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink1_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink1_valid
wire [101:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink1_data
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink1_ready -> cmd_demux_001:src4_ready
wire [10:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink1_channel
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink1_startofpacket
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink1_endofpacket
wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> cmd_mux_005:sink1_valid
wire [101:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> cmd_mux_005:sink1_data
wire cmd_demux_001_src5_ready; // cmd_mux_005:sink1_ready -> cmd_demux_001:src5_ready
wire [10:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> cmd_mux_005:sink1_channel
wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink1_startofpacket
wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink1_endofpacket
wire cmd_demux_001_src6_valid; // cmd_demux_001:src6_valid -> cmd_mux_006:sink1_valid
wire [101:0] cmd_demux_001_src6_data; // cmd_demux_001:src6_data -> cmd_mux_006:sink1_data
wire cmd_demux_001_src6_ready; // cmd_mux_006:sink1_ready -> cmd_demux_001:src6_ready
wire [10:0] cmd_demux_001_src6_channel; // cmd_demux_001:src6_channel -> cmd_mux_006:sink1_channel
wire cmd_demux_001_src6_startofpacket; // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink1_startofpacket
wire cmd_demux_001_src6_endofpacket; // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink1_endofpacket
wire cmd_demux_001_src7_valid; // cmd_demux_001:src7_valid -> cmd_mux_007:sink1_valid
wire [101:0] cmd_demux_001_src7_data; // cmd_demux_001:src7_data -> cmd_mux_007:sink1_data
wire cmd_demux_001_src7_ready; // cmd_mux_007:sink1_ready -> cmd_demux_001:src7_ready
wire [10:0] cmd_demux_001_src7_channel; // cmd_demux_001:src7_channel -> cmd_mux_007:sink1_channel
wire cmd_demux_001_src7_startofpacket; // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink1_startofpacket
wire cmd_demux_001_src7_endofpacket; // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink1_endofpacket
wire cmd_demux_001_src8_valid; // cmd_demux_001:src8_valid -> cmd_mux_008:sink1_valid
wire [101:0] cmd_demux_001_src8_data; // cmd_demux_001:src8_data -> cmd_mux_008:sink1_data
wire cmd_demux_001_src8_ready; // cmd_mux_008:sink1_ready -> cmd_demux_001:src8_ready
wire [10:0] cmd_demux_001_src8_channel; // cmd_demux_001:src8_channel -> cmd_mux_008:sink1_channel
wire cmd_demux_001_src8_startofpacket; // cmd_demux_001:src8_startofpacket -> cmd_mux_008:sink1_startofpacket
wire cmd_demux_001_src8_endofpacket; // cmd_demux_001:src8_endofpacket -> cmd_mux_008:sink1_endofpacket
wire cmd_demux_001_src9_valid; // cmd_demux_001:src9_valid -> cmd_mux_009:sink1_valid
wire [101:0] cmd_demux_001_src9_data; // cmd_demux_001:src9_data -> cmd_mux_009:sink1_data
wire cmd_demux_001_src9_ready; // cmd_mux_009:sink1_ready -> cmd_demux_001:src9_ready
wire [10:0] cmd_demux_001_src9_channel; // cmd_demux_001:src9_channel -> cmd_mux_009:sink1_channel
wire cmd_demux_001_src9_startofpacket; // cmd_demux_001:src9_startofpacket -> cmd_mux_009:sink1_startofpacket
wire cmd_demux_001_src9_endofpacket; // cmd_demux_001:src9_endofpacket -> cmd_mux_009:sink1_endofpacket
wire cmd_demux_001_src10_valid; // cmd_demux_001:src10_valid -> cmd_mux_010:sink1_valid
wire [101:0] cmd_demux_001_src10_data; // cmd_demux_001:src10_data -> cmd_mux_010:sink1_data
wire cmd_demux_001_src10_ready; // cmd_mux_010:sink1_ready -> cmd_demux_001:src10_ready
wire [10:0] cmd_demux_001_src10_channel; // cmd_demux_001:src10_channel -> cmd_mux_010:sink1_channel
wire cmd_demux_001_src10_startofpacket; // cmd_demux_001:src10_startofpacket -> cmd_mux_010:sink1_startofpacket
wire cmd_demux_001_src10_endofpacket; // cmd_demux_001:src10_endofpacket -> cmd_mux_010:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [101:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [10:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [101:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [10:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [101:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [10:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire [101:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire [10:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [101:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [10:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
wire [101:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
wire [10:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [101:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [10:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_001:sink3_valid
wire [101:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src1_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src1_ready
wire [10:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [101:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [10:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src1_valid; // rsp_demux_004:src1_valid -> rsp_mux_001:sink4_valid
wire [101:0] rsp_demux_004_src1_data; // rsp_demux_004:src1_data -> rsp_mux_001:sink4_data
wire rsp_demux_004_src1_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src1_ready
wire [10:0] rsp_demux_004_src1_channel; // rsp_demux_004:src1_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src1_startofpacket; // rsp_demux_004:src1_startofpacket -> rsp_mux_001:sink4_startofpacket
wire rsp_demux_004_src1_endofpacket; // rsp_demux_004:src1_endofpacket -> rsp_mux_001:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [101:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [10:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> rsp_mux_001:sink5_valid
wire [101:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> rsp_mux_001:sink5_data
wire rsp_demux_005_src1_ready; // rsp_mux_001:sink5_ready -> rsp_demux_005:src1_ready
wire [10:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> rsp_mux_001:sink5_channel
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> rsp_mux_001:sink5_startofpacket
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> rsp_mux_001:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire [101:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire [10:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src1_valid; // rsp_demux_006:src1_valid -> rsp_mux_001:sink6_valid
wire [101:0] rsp_demux_006_src1_data; // rsp_demux_006:src1_data -> rsp_mux_001:sink6_data
wire rsp_demux_006_src1_ready; // rsp_mux_001:sink6_ready -> rsp_demux_006:src1_ready
wire [10:0] rsp_demux_006_src1_channel; // rsp_demux_006:src1_channel -> rsp_mux_001:sink6_channel
wire rsp_demux_006_src1_startofpacket; // rsp_demux_006:src1_startofpacket -> rsp_mux_001:sink6_startofpacket
wire rsp_demux_006_src1_endofpacket; // rsp_demux_006:src1_endofpacket -> rsp_mux_001:sink6_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [101:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [10:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_007_src1_valid; // rsp_demux_007:src1_valid -> rsp_mux_001:sink7_valid
wire [101:0] rsp_demux_007_src1_data; // rsp_demux_007:src1_data -> rsp_mux_001:sink7_data
wire rsp_demux_007_src1_ready; // rsp_mux_001:sink7_ready -> rsp_demux_007:src1_ready
wire [10:0] rsp_demux_007_src1_channel; // rsp_demux_007:src1_channel -> rsp_mux_001:sink7_channel
wire rsp_demux_007_src1_startofpacket; // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink7_startofpacket
wire rsp_demux_007_src1_endofpacket; // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink7_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
wire [101:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
wire [10:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
wire rsp_demux_008_src1_valid; // rsp_demux_008:src1_valid -> rsp_mux_001:sink8_valid
wire [101:0] rsp_demux_008_src1_data; // rsp_demux_008:src1_data -> rsp_mux_001:sink8_data
wire rsp_demux_008_src1_ready; // rsp_mux_001:sink8_ready -> rsp_demux_008:src1_ready
wire [10:0] rsp_demux_008_src1_channel; // rsp_demux_008:src1_channel -> rsp_mux_001:sink8_channel
wire rsp_demux_008_src1_startofpacket; // rsp_demux_008:src1_startofpacket -> rsp_mux_001:sink8_startofpacket
wire rsp_demux_008_src1_endofpacket; // rsp_demux_008:src1_endofpacket -> rsp_mux_001:sink8_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
wire [101:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux:sink9_data
wire rsp_demux_009_src0_ready; // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
wire [10:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
wire rsp_demux_009_src1_valid; // rsp_demux_009:src1_valid -> rsp_mux_001:sink9_valid
wire [101:0] rsp_demux_009_src1_data; // rsp_demux_009:src1_data -> rsp_mux_001:sink9_data
wire rsp_demux_009_src1_ready; // rsp_mux_001:sink9_ready -> rsp_demux_009:src1_ready
wire [10:0] rsp_demux_009_src1_channel; // rsp_demux_009:src1_channel -> rsp_mux_001:sink9_channel
wire rsp_demux_009_src1_startofpacket; // rsp_demux_009:src1_startofpacket -> rsp_mux_001:sink9_startofpacket
wire rsp_demux_009_src1_endofpacket; // rsp_demux_009:src1_endofpacket -> rsp_mux_001:sink9_endofpacket
wire rsp_demux_010_src0_valid; // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
wire [101:0] rsp_demux_010_src0_data; // rsp_demux_010:src0_data -> rsp_mux:sink10_data
wire rsp_demux_010_src0_ready; // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
wire [10:0] rsp_demux_010_src0_channel; // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
wire rsp_demux_010_src0_startofpacket; // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
wire rsp_demux_010_src0_endofpacket; // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
wire rsp_demux_010_src1_valid; // rsp_demux_010:src1_valid -> rsp_mux_001:sink10_valid
wire [101:0] rsp_demux_010_src1_data; // rsp_demux_010:src1_data -> rsp_mux_001:sink10_data
wire rsp_demux_010_src1_ready; // rsp_mux_001:sink10_ready -> rsp_demux_010:src1_ready
wire [10:0] rsp_demux_010_src1_channel; // rsp_demux_010:src1_channel -> rsp_mux_001:sink10_channel
wire rsp_demux_010_src1_startofpacket; // rsp_demux_010:src1_startofpacket -> rsp_mux_001:sink10_startofpacket
wire rsp_demux_010_src1_endofpacket; // rsp_demux_010:src1_endofpacket -> rsp_mux_001:sink10_endofpacket
wire router_009_src_valid; // router_009:src_valid -> sdram_tri_controller_0_s1_rsp_width_adapter:in_valid
wire [83:0] router_009_src_data; // router_009:src_data -> sdram_tri_controller_0_s1_rsp_width_adapter:in_data
wire router_009_src_ready; // sdram_tri_controller_0_s1_rsp_width_adapter:in_ready -> router_009:src_ready
wire [10:0] router_009_src_channel; // router_009:src_channel -> sdram_tri_controller_0_s1_rsp_width_adapter:in_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> sdram_tri_controller_0_s1_rsp_width_adapter:in_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> sdram_tri_controller_0_s1_rsp_width_adapter:in_endofpacket
wire sdram_tri_controller_0_s1_rsp_width_adapter_src_valid; // sdram_tri_controller_0_s1_rsp_width_adapter:out_valid -> rsp_demux_007:sink_valid
wire [101:0] sdram_tri_controller_0_s1_rsp_width_adapter_src_data; // sdram_tri_controller_0_s1_rsp_width_adapter:out_data -> rsp_demux_007:sink_data
wire sdram_tri_controller_0_s1_rsp_width_adapter_src_ready; // rsp_demux_007:sink_ready -> sdram_tri_controller_0_s1_rsp_width_adapter:out_ready
wire [10:0] sdram_tri_controller_0_s1_rsp_width_adapter_src_channel; // sdram_tri_controller_0_s1_rsp_width_adapter:out_channel -> rsp_demux_007:sink_channel
wire sdram_tri_controller_0_s1_rsp_width_adapter_src_startofpacket; // sdram_tri_controller_0_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_007:sink_startofpacket
wire sdram_tri_controller_0_s1_rsp_width_adapter_src_endofpacket; // sdram_tri_controller_0_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_007:sink_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> sdram_tri_controller_0_s1_cmd_width_adapter:in_valid
wire [101:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> sdram_tri_controller_0_s1_cmd_width_adapter:in_data
wire cmd_mux_007_src_ready; // sdram_tri_controller_0_s1_cmd_width_adapter:in_ready -> cmd_mux_007:src_ready
wire [10:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> sdram_tri_controller_0_s1_cmd_width_adapter:in_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> sdram_tri_controller_0_s1_cmd_width_adapter:in_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> sdram_tri_controller_0_s1_cmd_width_adapter:in_endofpacket
wire sdram_tri_controller_0_s1_cmd_width_adapter_src_valid; // sdram_tri_controller_0_s1_cmd_width_adapter:out_valid -> sdram_tri_controller_0_s1_burst_adapter:sink0_valid
wire [83:0] sdram_tri_controller_0_s1_cmd_width_adapter_src_data; // sdram_tri_controller_0_s1_cmd_width_adapter:out_data -> sdram_tri_controller_0_s1_burst_adapter:sink0_data
wire sdram_tri_controller_0_s1_cmd_width_adapter_src_ready; // sdram_tri_controller_0_s1_burst_adapter:sink0_ready -> sdram_tri_controller_0_s1_cmd_width_adapter:out_ready
wire [10:0] sdram_tri_controller_0_s1_cmd_width_adapter_src_channel; // sdram_tri_controller_0_s1_cmd_width_adapter:out_channel -> sdram_tri_controller_0_s1_burst_adapter:sink0_channel
wire sdram_tri_controller_0_s1_cmd_width_adapter_src_startofpacket; // sdram_tri_controller_0_s1_cmd_width_adapter:out_startofpacket -> sdram_tri_controller_0_s1_burst_adapter:sink0_startofpacket
wire sdram_tri_controller_0_s1_cmd_width_adapter_src_endofpacket; // sdram_tri_controller_0_s1_cmd_width_adapter:out_endofpacket -> sdram_tri_controller_0_s1_burst_adapter:sink0_endofpacket
wire [10:0] nios2_gen2_0_data_master_limiter_cmd_valid_data; // nios2_gen2_0_data_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [10:0] nios2_gen2_0_instruction_master_limiter_cmd_valid_data; // nios2_gen2_0_instruction_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_valid; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_data; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent:rdata_fifo_sink_error
wire vic_0_csr_access_agent_rdata_fifo_src_valid; // vic_0_csr_access_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] vic_0_csr_access_agent_rdata_fifo_src_data; // vic_0_csr_access_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire vic_0_csr_access_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> vic_0_csr_access_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> vic_0_csr_access_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> vic_0_csr_access_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // vic_0_csr_access_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> vic_0_csr_access_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
wire uart_0_s1_agent_rdata_fifo_src_valid; // uart_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] uart_0_s1_agent_rdata_fifo_src_data; // uart_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire uart_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> uart_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> uart_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> uart_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // uart_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> uart_0_s1_agent:rdata_fifo_sink_error
wire uart_1_s1_agent_rdata_fifo_src_valid; // uart_1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] uart_1_s1_agent_rdata_fifo_src_data; // uart_1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire uart_1_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> uart_1_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> uart_1_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> uart_1_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // uart_1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> uart_1_s1_agent:rdata_fifo_sink_error
wire uart_2_s1_agent_rdata_fifo_src_valid; // uart_2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] uart_2_s1_agent_rdata_fifo_src_data; // uart_2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire uart_2_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> uart_2_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> uart_2_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> uart_2_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // uart_2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> uart_2_s1_agent:rdata_fifo_sink_error
wire uart_3_s1_agent_rdata_fifo_src_valid; // uart_3_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
wire [33:0] uart_3_s1_agent_rdata_fifo_src_data; // uart_3_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
wire uart_3_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_006:in_0_ready -> uart_3_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> uart_3_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> uart_3_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // uart_3_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> uart_3_s1_agent:rdata_fifo_sink_error
wire sdram_tri_controller_0_s1_agent_rdata_fifo_out_valid; // sdram_tri_controller_0_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_007:in_0_valid
wire [17:0] sdram_tri_controller_0_s1_agent_rdata_fifo_out_data; // sdram_tri_controller_0_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_007:in_0_data
wire sdram_tri_controller_0_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter_007:in_0_ready -> sdram_tri_controller_0_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> sdram_tri_controller_0_s1_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> sdram_tri_controller_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_007_out_0_ready; // sdram_tri_controller_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> sdram_tri_controller_0_s1_agent:rdata_fifo_sink_error
wire io_update_s1_agent_rdata_fifo_src_valid; // io_update_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
wire [33:0] io_update_s1_agent_rdata_fifo_src_data; // io_update_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
wire io_update_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_008:in_0_ready -> io_update_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_008_out_0_valid; // avalon_st_adapter_008:out_0_valid -> io_update_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_008_out_0_data; // avalon_st_adapter_008:out_0_data -> io_update_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_008_out_0_ready; // io_update_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
wire [0:0] avalon_st_adapter_008_out_0_error; // avalon_st_adapter_008:out_0_error -> io_update_s1_agent:rdata_fifo_sink_error
wire pps_interrupt_s1_agent_rdata_fifo_src_valid; // pps_interrupt_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
wire [33:0] pps_interrupt_s1_agent_rdata_fifo_src_data; // pps_interrupt_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
wire pps_interrupt_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_009:in_0_ready -> pps_interrupt_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_009_out_0_valid; // avalon_st_adapter_009:out_0_valid -> pps_interrupt_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_009_out_0_data; // avalon_st_adapter_009:out_0_data -> pps_interrupt_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_009_out_0_ready; // pps_interrupt_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
wire [0:0] avalon_st_adapter_009_out_0_error; // avalon_st_adapter_009:out_0_error -> pps_interrupt_s1_agent:rdata_fifo_sink_error
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_010:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_010:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_010:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_010_out_0_valid; // avalon_st_adapter_010:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_010_out_0_data; // avalon_st_adapter_010:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_010_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_010:out_0_ready
wire [0:0] avalon_st_adapter_010_out_0_error; // avalon_st_adapter_010:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_data_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_readdatavalid (nios2_gen2_0_data_master_readdatavalid), // .readdatavalid
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_readdatavalid (nios2_gen2_0_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (5),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) avalon_mapped_timer_reg_buf_0_avalon_slave_0_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (avalon_mapped_timer_reg_buf_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (avalon_mapped_timer_reg_buf_0_avalon_slave_0_write), // .write
.av_read (avalon_mapped_timer_reg_buf_0_avalon_slave_0_read), // .read
.av_readdata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_readdata), // .readdata
.av_writedata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) vic_0_csr_access_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (vic_0_csr_access_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (vic_0_csr_access_agent_m0_burstcount), // .burstcount
.uav_read (vic_0_csr_access_agent_m0_read), // .read
.uav_write (vic_0_csr_access_agent_m0_write), // .write
.uav_waitrequest (vic_0_csr_access_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (vic_0_csr_access_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (vic_0_csr_access_agent_m0_byteenable), // .byteenable
.uav_readdata (vic_0_csr_access_agent_m0_readdata), // .readdata
.uav_writedata (vic_0_csr_access_agent_m0_writedata), // .writedata
.uav_lock (vic_0_csr_access_agent_m0_lock), // .lock
.uav_debugaccess (vic_0_csr_access_agent_m0_debugaccess), // .debugaccess
.av_address (vic_0_csr_access_address), // avalon_anti_slave_0.address
.av_write (vic_0_csr_access_write), // .write
.av_read (vic_0_csr_access_read), // .read
.av_readdata (vic_0_csr_access_readdata), // .readdata
.av_writedata (vic_0_csr_access_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_0_s1_agent_m0_read), // .read
.uav_write (uart_0_s1_agent_m0_write), // .write
.uav_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_0_s1_address), // avalon_anti_slave_0.address
.av_write (uart_0_s1_write), // .write
.av_read (uart_0_s1_read), // .read
.av_readdata (uart_0_s1_readdata), // .readdata
.av_writedata (uart_0_s1_writedata), // .writedata
.av_begintransfer (uart_0_s1_begintransfer), // .begintransfer
.av_chipselect (uart_0_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_1_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_1_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_1_s1_agent_m0_read), // .read
.uav_write (uart_1_s1_agent_m0_write), // .write
.uav_waitrequest (uart_1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_1_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_1_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_1_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_1_s1_address), // avalon_anti_slave_0.address
.av_write (uart_1_s1_write), // .write
.av_read (uart_1_s1_read), // .read
.av_readdata (uart_1_s1_readdata), // .readdata
.av_writedata (uart_1_s1_writedata), // .writedata
.av_begintransfer (uart_1_s1_begintransfer), // .begintransfer
.av_chipselect (uart_1_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_2_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_2_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_2_s1_agent_m0_read), // .read
.uav_write (uart_2_s1_agent_m0_write), // .write
.uav_waitrequest (uart_2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_2_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_2_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_2_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_2_s1_address), // avalon_anti_slave_0.address
.av_write (uart_2_s1_write), // .write
.av_read (uart_2_s1_read), // .read
.av_readdata (uart_2_s1_readdata), // .readdata
.av_writedata (uart_2_s1_writedata), // .writedata
.av_begintransfer (uart_2_s1_begintransfer), // .begintransfer
.av_chipselect (uart_2_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_3_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_3_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_3_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_3_s1_agent_m0_read), // .read
.uav_write (uart_3_s1_agent_m0_write), // .write
.uav_waitrequest (uart_3_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_3_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_3_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_3_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_3_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_3_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_3_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_3_s1_address), // avalon_anti_slave_0.address
.av_write (uart_3_s1_write), // .write
.av_read (uart_3_s1_read), // .read
.av_readdata (uart_3_s1_readdata), // .readdata
.av_writedata (uart_3_s1_writedata), // .writedata
.av_begintransfer (uart_3_s1_begintransfer), // .begintransfer
.av_chipselect (uart_3_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_tri_controller_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_tri_controller_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_tri_controller_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_tri_controller_0_s1_agent_m0_read), // .read
.uav_write (sdram_tri_controller_0_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_tri_controller_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_tri_controller_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_tri_controller_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_tri_controller_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_tri_controller_0_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_tri_controller_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_tri_controller_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_tri_controller_0_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_tri_controller_0_s1_write), // .write
.av_read (sdram_tri_controller_0_s1_read), // .read
.av_readdata (sdram_tri_controller_0_s1_readdata), // .readdata
.av_writedata (sdram_tri_controller_0_s1_writedata), // .writedata
.av_byteenable (sdram_tri_controller_0_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_tri_controller_0_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_tri_controller_0_s1_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) io_update_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (io_update_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (io_update_s1_agent_m0_burstcount), // .burstcount
.uav_read (io_update_s1_agent_m0_read), // .read
.uav_write (io_update_s1_agent_m0_write), // .write
.uav_waitrequest (io_update_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (io_update_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (io_update_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (io_update_s1_agent_m0_readdata), // .readdata
.uav_writedata (io_update_s1_agent_m0_writedata), // .writedata
.uav_lock (io_update_s1_agent_m0_lock), // .lock
.uav_debugaccess (io_update_s1_agent_m0_debugaccess), // .debugaccess
.av_address (io_update_s1_address), // avalon_anti_slave_0.address
.av_write (io_update_s1_write), // .write
.av_readdata (io_update_s1_readdata), // .readdata
.av_writedata (io_update_s1_writedata), // .writedata
.av_chipselect (io_update_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pps_interrupt_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pps_interrupt_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pps_interrupt_s1_agent_m0_burstcount), // .burstcount
.uav_read (pps_interrupt_s1_agent_m0_read), // .read
.uav_write (pps_interrupt_s1_agent_m0_write), // .write
.uav_waitrequest (pps_interrupt_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pps_interrupt_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pps_interrupt_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (pps_interrupt_s1_agent_m0_readdata), // .readdata
.uav_writedata (pps_interrupt_s1_agent_m0_writedata), // .writedata
.uav_lock (pps_interrupt_s1_agent_m0_lock), // .lock
.uav_debugaccess (pps_interrupt_s1_agent_m0_debugaccess), // .debugaccess
.av_address (pps_interrupt_s1_address), // avalon_anti_slave_0.address
.av_write (pps_interrupt_s1_write), // .write
.av_readdata (pps_interrupt_s1_readdata), // .readdata
.av_writedata (pps_interrupt_s1_writedata), // .writedata
.av_chipselect (pps_interrupt_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (24),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_QOS_H (80),
.PKT_QOS_L (80),
.PKT_DATA_SIDEBAND_H (78),
.PKT_DATA_SIDEBAND_L (78),
.PKT_ADDR_SIDEBAND_H (77),
.PKT_ADDR_SIDEBAND_L (77),
.PKT_BURST_TYPE_H (76),
.PKT_BURST_TYPE_L (75),
.PKT_CACHE_H (96),
.PKT_CACHE_L (93),
.PKT_THREAD_ID_H (89),
.PKT_THREAD_ID_L (89),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_EXCLUSIVE (65),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.ST_DATA_W (102),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (nios2_gen2_0_data_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_gen2_0_data_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_gen2_0_data_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_gen2_0_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_gen2_0_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_gen2_0_data_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_QOS_H (80),
.PKT_QOS_L (80),
.PKT_DATA_SIDEBAND_H (78),
.PKT_DATA_SIDEBAND_L (78),
.PKT_ADDR_SIDEBAND_H (77),
.PKT_ADDR_SIDEBAND_L (77),
.PKT_BURST_TYPE_H (76),
.PKT_BURST_TYPE_L (75),
.PKT_CACHE_H (96),
.PKT_CACHE_L (93),
.PKT_THREAD_ID_H (89),
.PKT_THREAD_ID_L (89),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_EXCLUSIVE (65),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.ST_DATA_W (102),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (nios2_gen2_0_instruction_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_gen2_0_instruction_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_gen2_0_instruction_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_gen2_0_instruction_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) vic_0_csr_access_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (vic_0_csr_access_agent_m0_address), // m0.address
.m0_burstcount (vic_0_csr_access_agent_m0_burstcount), // .burstcount
.m0_byteenable (vic_0_csr_access_agent_m0_byteenable), // .byteenable
.m0_debugaccess (vic_0_csr_access_agent_m0_debugaccess), // .debugaccess
.m0_lock (vic_0_csr_access_agent_m0_lock), // .lock
.m0_readdata (vic_0_csr_access_agent_m0_readdata), // .readdata
.m0_readdatavalid (vic_0_csr_access_agent_m0_readdatavalid), // .readdatavalid
.m0_read (vic_0_csr_access_agent_m0_read), // .read
.m0_waitrequest (vic_0_csr_access_agent_m0_waitrequest), // .waitrequest
.m0_writedata (vic_0_csr_access_agent_m0_writedata), // .writedata
.m0_write (vic_0_csr_access_agent_m0_write), // .write
.rp_endofpacket (vic_0_csr_access_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (vic_0_csr_access_agent_rp_ready), // .ready
.rp_valid (vic_0_csr_access_agent_rp_valid), // .valid
.rp_data (vic_0_csr_access_agent_rp_data), // .data
.rp_startofpacket (vic_0_csr_access_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (vic_0_csr_access_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (vic_0_csr_access_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (vic_0_csr_access_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (vic_0_csr_access_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (vic_0_csr_access_agent_rsp_fifo_out_data), // .data
.rf_source_ready (vic_0_csr_access_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (vic_0_csr_access_agent_rf_source_valid), // .valid
.rf_source_startofpacket (vic_0_csr_access_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (vic_0_csr_access_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (vic_0_csr_access_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (vic_0_csr_access_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (vic_0_csr_access_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (vic_0_csr_access_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) vic_0_csr_access_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (vic_0_csr_access_agent_rf_source_data), // in.data
.in_valid (vic_0_csr_access_agent_rf_source_valid), // .valid
.in_ready (vic_0_csr_access_agent_rf_source_ready), // .ready
.in_startofpacket (vic_0_csr_access_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (vic_0_csr_access_agent_rf_source_endofpacket), // .endofpacket
.out_data (vic_0_csr_access_agent_rsp_fifo_out_data), // out.data
.out_valid (vic_0_csr_access_agent_rsp_fifo_out_valid), // .valid
.out_ready (vic_0_csr_access_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (vic_0_csr_access_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (vic_0_csr_access_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_0_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_0_s1_agent_m0_lock), // .lock
.m0_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_0_s1_agent_m0_read), // .read
.m0_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.m0_write (uart_0_s1_agent_m0_write), // .write
.rp_endofpacket (uart_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_0_s1_agent_rp_ready), // .ready
.rp_valid (uart_0_s1_agent_rp_valid), // .valid
.rp_data (uart_0_s1_agent_rp_data), // .data
.rp_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (uart_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (uart_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_0_s1_agent_rf_source_data), // in.data
.in_valid (uart_0_s1_agent_rf_source_valid), // .valid
.in_ready (uart_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_1_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_1_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_1_s1_agent_m0_lock), // .lock
.m0_readdata (uart_1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_1_s1_agent_m0_read), // .read
.m0_waitrequest (uart_1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_1_s1_agent_m0_writedata), // .writedata
.m0_write (uart_1_s1_agent_m0_write), // .write
.rp_endofpacket (uart_1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_1_s1_agent_rp_ready), // .ready
.rp_valid (uart_1_s1_agent_rp_valid), // .valid
.rp_data (uart_1_s1_agent_rp_data), // .data
.rp_startofpacket (uart_1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (uart_1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (uart_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_1_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_1_s1_agent_rf_source_data), // in.data
.in_valid (uart_1_s1_agent_rf_source_valid), // .valid
.in_ready (uart_1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_2_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_2_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_2_s1_agent_m0_lock), // .lock
.m0_readdata (uart_2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_2_s1_agent_m0_read), // .read
.m0_waitrequest (uart_2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_2_s1_agent_m0_writedata), // .writedata
.m0_write (uart_2_s1_agent_m0_write), // .write
.rp_endofpacket (uart_2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_2_s1_agent_rp_ready), // .ready
.rp_valid (uart_2_s1_agent_rp_valid), // .valid
.rp_data (uart_2_s1_agent_rp_data), // .data
.rp_startofpacket (uart_2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (uart_2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (uart_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_2_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_2_s1_agent_rf_source_data), // in.data
.in_valid (uart_2_s1_agent_rf_source_valid), // .valid
.in_ready (uart_2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_3_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_3_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_3_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_3_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_3_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_3_s1_agent_m0_lock), // .lock
.m0_readdata (uart_3_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_3_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_3_s1_agent_m0_read), // .read
.m0_waitrequest (uart_3_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_3_s1_agent_m0_writedata), // .writedata
.m0_write (uart_3_s1_agent_m0_write), // .write
.rp_endofpacket (uart_3_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_3_s1_agent_rp_ready), // .ready
.rp_valid (uart_3_s1_agent_rp_valid), // .valid
.rp_data (uart_3_s1_agent_rp_data), // .data
.rp_startofpacket (uart_3_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (uart_3_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_3_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_3_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_3_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_3_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_3_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_3_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_3_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (uart_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_3_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_3_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_3_s1_agent_rf_source_data), // in.data
.in_valid (uart_3_s1_agent_rf_source_valid), // .valid
.in_ready (uart_3_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_3_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_3_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_3_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_3_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_3_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (83),
.PKT_ORI_BURST_SIZE_L (81),
.PKT_RESPONSE_STATUS_H (80),
.PKT_RESPONSE_STATUS_L (79),
.PKT_BURST_SIZE_H (56),
.PKT_BURST_SIZE_L (54),
.PKT_TRANS_LOCK (46),
.PKT_BEGIN_BURST (61),
.PKT_PROTECTION_H (74),
.PKT_PROTECTION_L (72),
.PKT_BURSTWRAP_H (53),
.PKT_BURSTWRAP_L (51),
.PKT_BYTE_CNT_H (50),
.PKT_BYTE_CNT_L (48),
.PKT_ADDR_H (41),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (42),
.PKT_TRANS_POSTED (43),
.PKT_TRANS_WRITE (44),
.PKT_TRANS_READ (45),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (66),
.PKT_SRC_ID_L (63),
.PKT_DEST_ID_H (70),
.PKT_DEST_ID_L (67),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (84),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sdram_tri_controller_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_tri_controller_0_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_tri_controller_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_tri_controller_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_tri_controller_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_tri_controller_0_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_tri_controller_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_tri_controller_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_tri_controller_0_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_tri_controller_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_tri_controller_0_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_tri_controller_0_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_tri_controller_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_tri_controller_0_s1_agent_rp_ready), // .ready
.rp_valid (sdram_tri_controller_0_s1_agent_rp_valid), // .valid
.rp_data (sdram_tri_controller_0_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_tri_controller_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sdram_tri_controller_0_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sdram_tri_controller_0_s1_burst_adapter_source0_valid), // .valid
.cp_data (sdram_tri_controller_0_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sdram_tri_controller_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sdram_tri_controller_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sdram_tri_controller_0_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_tri_controller_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_tri_controller_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_tri_controller_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_tri_controller_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_tri_controller_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_tri_controller_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_tri_controller_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_tri_controller_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_tri_controller_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_tri_controller_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error
.rdata_fifo_src_ready (sdram_tri_controller_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_tri_controller_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_tri_controller_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (85),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_tri_controller_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_tri_controller_0_s1_agent_rf_source_data), // in.data
.in_valid (sdram_tri_controller_0_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_tri_controller_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_tri_controller_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_tri_controller_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_tri_controller_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_tri_controller_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_tri_controller_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_tri_controller_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_tri_controller_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_tri_controller_0_s1_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_tri_controller_0_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_tri_controller_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_tri_controller_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_tri_controller_0_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_tri_controller_0_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_tri_controller_0_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) io_update_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (io_update_s1_agent_m0_address), // m0.address
.m0_burstcount (io_update_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (io_update_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (io_update_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (io_update_s1_agent_m0_lock), // .lock
.m0_readdata (io_update_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (io_update_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (io_update_s1_agent_m0_read), // .read
.m0_waitrequest (io_update_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (io_update_s1_agent_m0_writedata), // .writedata
.m0_write (io_update_s1_agent_m0_write), // .write
.rp_endofpacket (io_update_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (io_update_s1_agent_rp_ready), // .ready
.rp_valid (io_update_s1_agent_rp_valid), // .valid
.rp_data (io_update_s1_agent_rp_data), // .data
.rp_startofpacket (io_update_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (io_update_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (io_update_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (io_update_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (io_update_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (io_update_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (io_update_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (io_update_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (io_update_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (io_update_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (io_update_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_008_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_008_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_008_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_008_out_0_error), // .error
.rdata_fifo_src_ready (io_update_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (io_update_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (io_update_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) io_update_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (io_update_s1_agent_rf_source_data), // in.data
.in_valid (io_update_s1_agent_rf_source_valid), // .valid
.in_ready (io_update_s1_agent_rf_source_ready), // .ready
.in_startofpacket (io_update_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (io_update_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (io_update_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (io_update_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (io_update_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (io_update_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (io_update_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) pps_interrupt_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pps_interrupt_s1_agent_m0_address), // m0.address
.m0_burstcount (pps_interrupt_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (pps_interrupt_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pps_interrupt_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (pps_interrupt_s1_agent_m0_lock), // .lock
.m0_readdata (pps_interrupt_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (pps_interrupt_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pps_interrupt_s1_agent_m0_read), // .read
.m0_waitrequest (pps_interrupt_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pps_interrupt_s1_agent_m0_writedata), // .writedata
.m0_write (pps_interrupt_s1_agent_m0_write), // .write
.rp_endofpacket (pps_interrupt_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pps_interrupt_s1_agent_rp_ready), // .ready
.rp_valid (pps_interrupt_s1_agent_rp_valid), // .valid
.rp_data (pps_interrupt_s1_agent_rp_data), // .data
.rp_startofpacket (pps_interrupt_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (pps_interrupt_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pps_interrupt_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pps_interrupt_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pps_interrupt_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pps_interrupt_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pps_interrupt_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pps_interrupt_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pps_interrupt_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pps_interrupt_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pps_interrupt_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_009_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_009_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_009_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_009_out_0_error), // .error
.rdata_fifo_src_ready (pps_interrupt_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pps_interrupt_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pps_interrupt_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pps_interrupt_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pps_interrupt_s1_agent_rf_source_data), // in.data
.in_valid (pps_interrupt_s1_agent_rf_source_valid), // .valid
.in_ready (pps_interrupt_s1_agent_rf_source_ready), // .ready
.in_startofpacket (pps_interrupt_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pps_interrupt_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (pps_interrupt_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (pps_interrupt_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (pps_interrupt_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pps_interrupt_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pps_interrupt_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (64),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (69),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_ADDR_H (59),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (60),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.PKT_TRANS_READ (63),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (11),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_010_src_ready), // cp.ready
.cp_valid (cmd_mux_010_src_valid), // .valid
.cp_data (cmd_mux_010_src_data), // .data
.cp_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_010_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_010_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_010_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_010_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_010_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
TimeHoldOver_Qsys_mm_interconnect_0_router router (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router router_001 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_002 (
.sink_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_003 (
.sink_ready (vic_0_csr_access_agent_rp_ready), // sink.ready
.sink_valid (vic_0_csr_access_agent_rp_valid), // .valid
.sink_data (vic_0_csr_access_agent_rp_data), // .data
.sink_startofpacket (vic_0_csr_access_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (vic_0_csr_access_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_004 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_005 (
.sink_ready (uart_0_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_0_s1_agent_rp_valid), // .valid
.sink_data (uart_0_s1_agent_rp_data), // .data
.sink_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_006 (
.sink_ready (uart_1_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_1_s1_agent_rp_valid), // .valid
.sink_data (uart_1_s1_agent_rp_data), // .data
.sink_startofpacket (uart_1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_1_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_007 (
.sink_ready (uart_2_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_2_s1_agent_rp_valid), // .valid
.sink_data (uart_2_s1_agent_rp_data), // .data
.sink_startofpacket (uart_2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_2_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_008 (
.sink_ready (uart_3_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_3_s1_agent_rp_valid), // .valid
.sink_data (uart_3_s1_agent_rp_data), // .data
.sink_startofpacket (uart_3_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_3_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_009 router_009 (
.sink_ready (sdram_tri_controller_0_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_tri_controller_0_s1_agent_rp_valid), // .valid
.sink_data (sdram_tri_controller_0_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_tri_controller_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_tri_controller_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_010 (
.sink_ready (io_update_s1_agent_rp_ready), // sink.ready
.sink_valid (io_update_s1_agent_rp_valid), // .valid
.sink_data (io_update_s1_agent_rp_data), // .data
.sink_startofpacket (io_update_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (io_update_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_011 (
.sink_ready (pps_interrupt_s1_agent_rp_ready), // sink.ready
.sink_valid (pps_interrupt_s1_agent_rp_valid), // .valid
.sink_data (pps_interrupt_s1_agent_rp_data), // .data
.sink_startofpacket (pps_interrupt_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pps_interrupt_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_router_002 router_012 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_012_src_ready), // src.ready
.src_valid (router_012_src_valid), // .valid
.src_data (router_012_src_data), // .data
.src_channel (router_012_src_channel), // .channel
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (102),
.ST_CHANNEL_W (11),
.VALID_WIDTH (11),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) nios2_gen2_0_data_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_gen2_0_data_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_gen2_0_data_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_gen2_0_data_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_gen2_0_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_gen2_0_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_gen2_0_data_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_gen2_0_data_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_gen2_0_data_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_gen2_0_data_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_gen2_0_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_gen2_0_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_gen2_0_data_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_BYTE_CNT_H (68),
.PKT_BYTE_CNT_L (66),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (61),
.PKT_TRANS_WRITE (62),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (102),
.ST_CHANNEL_W (11),
.VALID_WIDTH (11),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) nios2_gen2_0_instruction_master_limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_gen2_0_instruction_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_gen2_0_instruction_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_gen2_0_instruction_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_gen2_0_instruction_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_gen2_0_instruction_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_gen2_0_instruction_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_gen2_0_instruction_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_gen2_0_instruction_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (41),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (61),
.PKT_BYTE_CNT_H (50),
.PKT_BYTE_CNT_L (48),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (56),
.PKT_BURST_SIZE_L (54),
.PKT_BURST_TYPE_H (58),
.PKT_BURST_TYPE_L (57),
.PKT_BURSTWRAP_H (53),
.PKT_BURSTWRAP_L (51),
.PKT_TRANS_COMPRESSED_READ (42),
.PKT_TRANS_WRITE (44),
.PKT_TRANS_READ (45),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (84),
.ST_CHANNEL_W (11),
.OUT_BYTE_CNT_H (49),
.OUT_BURSTWRAP_H (53),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3),
.ADAPTER_VERSION ("13.1")
) sdram_tri_controller_0_s1_burst_adapter (
.clk (clk_0_clk_clk), // cr0.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (sdram_tri_controller_0_s1_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (sdram_tri_controller_0_s1_cmd_width_adapter_src_data), // .data
.sink0_channel (sdram_tri_controller_0_s1_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (sdram_tri_controller_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (sdram_tri_controller_0_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (sdram_tri_controller_0_s1_cmd_width_adapter_src_ready), // .ready
.source0_valid (sdram_tri_controller_0_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sdram_tri_controller_0_s1_burst_adapter_source0_data), // .data
.source0_channel (sdram_tri_controller_0_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sdram_tri_controller_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sdram_tri_controller_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sdram_tri_controller_0_s1_burst_adapter_source0_ready) // .ready
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_gen2_0_data_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_gen2_0_data_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_gen2_0_data_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_gen2_0_data_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_src8_ready), // src8.ready
.src8_valid (cmd_demux_src8_valid), // .valid
.src8_data (cmd_demux_src8_data), // .data
.src8_channel (cmd_demux_src8_channel), // .channel
.src8_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_src9_ready), // src9.ready
.src9_valid (cmd_demux_src9_valid), // .valid
.src9_data (cmd_demux_src9_data), // .data
.src9_channel (cmd_demux_src9_channel), // .channel
.src9_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
.src10_ready (cmd_demux_src10_ready), // src10.ready
.src10_valid (cmd_demux_src10_valid), // .valid
.src10_data (cmd_demux_src10_data), // .data
.src10_channel (cmd_demux_src10_channel), // .channel
.src10_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_demux_src10_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_gen2_0_instruction_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_gen2_0_instruction_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_gen2_0_instruction_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_gen2_0_instruction_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_demux_001_src5_valid), // .valid
.src5_data (cmd_demux_001_src5_data), // .data
.src5_channel (cmd_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_demux_001_src6_valid), // .valid
.src6_data (cmd_demux_001_src6_data), // .data
.src6_channel (cmd_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_demux_001_src7_valid), // .valid
.src7_data (cmd_demux_001_src7_data), // .data
.src7_channel (cmd_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_001_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_001_src8_ready), // src8.ready
.src8_valid (cmd_demux_001_src8_valid), // .valid
.src8_data (cmd_demux_001_src8_data), // .data
.src8_channel (cmd_demux_001_src8_channel), // .channel
.src8_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_001_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_001_src9_ready), // src9.ready
.src9_valid (cmd_demux_001_src9_valid), // .valid
.src9_data (cmd_demux_001_src9_data), // .data
.src9_channel (cmd_demux_001_src9_channel), // .channel
.src9_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_001_src9_endofpacket), // .endofpacket
.src10_ready (cmd_demux_001_src10_ready), // src10.ready
.src10_valid (cmd_demux_001_src10_valid), // .valid
.src10_data (cmd_demux_001_src10_data), // .data
.src10_channel (cmd_demux_001_src10_channel), // .channel
.src10_startofpacket (cmd_demux_001_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_demux_001_src10_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src3_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src3_valid), // .valid
.sink1_channel (cmd_demux_001_src3_channel), // .channel
.sink1_data (cmd_demux_001_src3_data), // .data
.sink1_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src4_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src4_valid), // .valid
.sink1_channel (cmd_demux_001_src4_channel), // .channel
.sink1_data (cmd_demux_001_src4_data), // .data
.sink1_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src5_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src5_valid), // .valid
.sink1_channel (cmd_demux_001_src5_channel), // .channel
.sink1_data (cmd_demux_001_src5_data), // .data
.sink1_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src6_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src6_valid), // .valid
.sink1_channel (cmd_demux_001_src6_channel), // .channel
.sink1_data (cmd_demux_001_src6_data), // .data
.sink1_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src6_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src7_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src7_valid), // .valid
.sink1_channel (cmd_demux_001_src7_channel), // .channel
.sink1_data (cmd_demux_001_src7_data), // .data
.sink1_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src7_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_src8_valid), // .valid
.sink0_channel (cmd_demux_src8_channel), // .channel
.sink0_data (cmd_demux_src8_data), // .data
.sink0_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src8_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src8_valid), // .valid
.sink1_channel (cmd_demux_001_src8_channel), // .channel
.sink1_data (cmd_demux_001_src8_data), // .data
.sink1_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src8_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src9_ready), // sink0.ready
.sink0_valid (cmd_demux_src9_valid), // .valid
.sink0_channel (cmd_demux_src9_channel), // .channel
.sink0_data (cmd_demux_src9_data), // .data
.sink0_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src9_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src9_valid), // .valid
.sink1_channel (cmd_demux_001_src9_channel), // .channel
.sink1_data (cmd_demux_001_src9_data), // .data
.sink1_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src9_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_cmd_mux cmd_mux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_010_src_ready), // src.ready
.src_valid (cmd_mux_010_src_valid), // .valid
.src_data (cmd_mux_010_src_data), // .data
.src_channel (cmd_mux_010_src_channel), // .channel
.src_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src10_ready), // sink0.ready
.sink0_valid (cmd_demux_src10_valid), // .valid
.sink0_channel (cmd_demux_src10_channel), // .channel
.sink0_data (cmd_demux_src10_data), // .data
.sink0_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src10_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src10_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src10_valid), // .valid
.sink1_channel (cmd_demux_001_src10_channel), // .channel
.sink1_data (cmd_demux_001_src10_data), // .data
.sink1_startofpacket (cmd_demux_001_src10_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src10_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_004_src1_ready), // src1.ready
.src1_valid (rsp_demux_004_src1_valid), // .valid
.src1_data (rsp_demux_004_src1_data), // .data
.src1_channel (rsp_demux_004_src1_channel), // .channel
.src1_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_004_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_006_src1_ready), // src1.ready
.src1_valid (rsp_demux_006_src1_valid), // .valid
.src1_data (rsp_demux_006_src1_data), // .data
.src1_channel (rsp_demux_006_src1_channel), // .channel
.src1_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_006_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sdram_tri_controller_0_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sdram_tri_controller_0_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sdram_tri_controller_0_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sdram_tri_controller_0_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sdram_tri_controller_0_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sdram_tri_controller_0_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_007_src1_ready), // src1.ready
.src1_valid (rsp_demux_007_src1_valid), // .valid
.src1_data (rsp_demux_007_src1_data), // .data
.src1_channel (rsp_demux_007_src1_channel), // .channel
.src1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_008_src1_ready), // src1.ready
.src1_valid (rsp_demux_008_src1_valid), // .valid
.src1_data (rsp_demux_008_src1_data), // .data
.src1_channel (rsp_demux_008_src1_channel), // .channel
.src1_startofpacket (rsp_demux_008_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_008_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_009_src1_ready), // src1.ready
.src1_valid (rsp_demux_009_src1_valid), // .valid
.src1_data (rsp_demux_009_src1_data), // .data
.src1_channel (rsp_demux_009_src1_channel), // .channel
.src1_startofpacket (rsp_demux_009_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_009_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_demux rsp_demux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_012_src_ready), // sink.ready
.sink_channel (router_012_src_channel), // .channel
.sink_data (router_012_src_data), // .data
.sink_startofpacket (router_012_src_startofpacket), // .startofpacket
.sink_endofpacket (router_012_src_endofpacket), // .endofpacket
.sink_valid (router_012_src_valid), // .valid
.src0_ready (rsp_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_demux_010_src0_valid), // .valid
.src0_data (rsp_demux_010_src0_data), // .data
.src0_channel (rsp_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_010_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_010_src1_ready), // src1.ready
.src1_valid (rsp_demux_010_src1_valid), // .valid
.src1_data (rsp_demux_010_src1_data), // .data
.src1_channel (rsp_demux_010_src1_channel), // .channel
.src1_startofpacket (rsp_demux_010_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_010_src1_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src0_valid), // .valid
.sink9_channel (rsp_demux_009_src0_channel), // .channel
.sink9_data (rsp_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.sink10_ready (rsp_demux_010_src0_ready), // sink10.ready
.sink10_valid (rsp_demux_010_src0_valid), // .valid
.sink10_channel (rsp_demux_010_src0_channel), // .channel
.sink10_data (rsp_demux_010_src0_data), // .data
.sink10_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_demux_010_src0_endofpacket) // .endofpacket
);
TimeHoldOver_Qsys_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src1_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src1_valid), // .valid
.sink3_channel (rsp_demux_003_src1_channel), // .channel
.sink3_data (rsp_demux_003_src1_data), // .data
.sink3_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src1_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src1_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src1_valid), // .valid
.sink4_channel (rsp_demux_004_src1_channel), // .channel
.sink4_data (rsp_demux_004_src1_data), // .data
.sink4_startofpacket (rsp_demux_004_src1_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src1_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src1_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src1_valid), // .valid
.sink5_channel (rsp_demux_005_src1_channel), // .channel
.sink5_data (rsp_demux_005_src1_data), // .data
.sink5_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src1_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src1_valid), // .valid
.sink6_channel (rsp_demux_006_src1_channel), // .channel
.sink6_data (rsp_demux_006_src1_data), // .data
.sink6_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src1_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src1_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src1_valid), // .valid
.sink7_channel (rsp_demux_007_src1_channel), // .channel
.sink7_data (rsp_demux_007_src1_data), // .data
.sink7_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src1_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src1_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src1_valid), // .valid
.sink8_channel (rsp_demux_008_src1_channel), // .channel
.sink8_data (rsp_demux_008_src1_data), // .data
.sink8_startofpacket (rsp_demux_008_src1_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src1_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src1_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src1_valid), // .valid
.sink9_channel (rsp_demux_009_src1_channel), // .channel
.sink9_data (rsp_demux_009_src1_data), // .data
.sink9_startofpacket (rsp_demux_009_src1_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src1_endofpacket), // .endofpacket
.sink10_ready (rsp_demux_010_src1_ready), // sink10.ready
.sink10_valid (rsp_demux_010_src1_valid), // .valid
.sink10_channel (rsp_demux_010_src1_channel), // .channel
.sink10_data (rsp_demux_010_src1_data), // .data
.sink10_startofpacket (rsp_demux_010_src1_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_demux_010_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (41),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (50),
.IN_PKT_BYTE_CNT_L (48),
.IN_PKT_TRANS_COMPRESSED_READ (42),
.IN_PKT_TRANS_WRITE (44),
.IN_PKT_BURSTWRAP_H (53),
.IN_PKT_BURSTWRAP_L (51),
.IN_PKT_BURST_SIZE_H (56),
.IN_PKT_BURST_SIZE_L (54),
.IN_PKT_RESPONSE_STATUS_H (80),
.IN_PKT_RESPONSE_STATUS_L (79),
.IN_PKT_TRANS_EXCLUSIVE (47),
.IN_PKT_BURST_TYPE_H (58),
.IN_PKT_BURST_TYPE_L (57),
.IN_PKT_ORI_BURST_SIZE_L (81),
.IN_PKT_ORI_BURST_SIZE_H (83),
.IN_ST_DATA_W (84),
.OUT_PKT_ADDR_H (59),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (68),
.OUT_PKT_BYTE_CNT_L (66),
.OUT_PKT_TRANS_COMPRESSED_READ (60),
.OUT_PKT_BURST_SIZE_H (74),
.OUT_PKT_BURST_SIZE_L (72),
.OUT_PKT_RESPONSE_STATUS_H (98),
.OUT_PKT_RESPONSE_STATUS_L (97),
.OUT_PKT_TRANS_EXCLUSIVE (65),
.OUT_PKT_BURST_TYPE_H (76),
.OUT_PKT_BURST_TYPE_L (75),
.OUT_PKT_ORI_BURST_SIZE_L (99),
.OUT_PKT_ORI_BURST_SIZE_H (101),
.OUT_ST_DATA_W (102),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_tri_controller_0_s1_rsp_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_009_src_valid), // sink.valid
.in_channel (router_009_src_channel), // .channel
.in_startofpacket (router_009_src_startofpacket), // .startofpacket
.in_endofpacket (router_009_src_endofpacket), // .endofpacket
.in_ready (router_009_src_ready), // .ready
.in_data (router_009_src_data), // .data
.out_endofpacket (sdram_tri_controller_0_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_tri_controller_0_s1_rsp_width_adapter_src_data), // .data
.out_channel (sdram_tri_controller_0_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sdram_tri_controller_0_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sdram_tri_controller_0_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_tri_controller_0_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (59),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (68),
.IN_PKT_BYTE_CNT_L (66),
.IN_PKT_TRANS_COMPRESSED_READ (60),
.IN_PKT_TRANS_WRITE (62),
.IN_PKT_BURSTWRAP_H (71),
.IN_PKT_BURSTWRAP_L (69),
.IN_PKT_BURST_SIZE_H (74),
.IN_PKT_BURST_SIZE_L (72),
.IN_PKT_RESPONSE_STATUS_H (98),
.IN_PKT_RESPONSE_STATUS_L (97),
.IN_PKT_TRANS_EXCLUSIVE (65),
.IN_PKT_BURST_TYPE_H (76),
.IN_PKT_BURST_TYPE_L (75),
.IN_PKT_ORI_BURST_SIZE_L (99),
.IN_PKT_ORI_BURST_SIZE_H (101),
.IN_ST_DATA_W (102),
.OUT_PKT_ADDR_H (41),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (50),
.OUT_PKT_BYTE_CNT_L (48),
.OUT_PKT_TRANS_COMPRESSED_READ (42),
.OUT_PKT_BURST_SIZE_H (56),
.OUT_PKT_BURST_SIZE_L (54),
.OUT_PKT_RESPONSE_STATUS_H (80),
.OUT_PKT_RESPONSE_STATUS_L (79),
.OUT_PKT_TRANS_EXCLUSIVE (47),
.OUT_PKT_BURST_TYPE_H (58),
.OUT_PKT_BURST_TYPE_L (57),
.OUT_PKT_ORI_BURST_SIZE_L (81),
.OUT_PKT_ORI_BURST_SIZE_H (83),
.OUT_ST_DATA_W (84),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_tri_controller_0_s1_cmd_width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_007_src_valid), // sink.valid
.in_channel (cmd_mux_007_src_channel), // .channel
.in_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_007_src_ready), // .ready
.in_data (cmd_mux_007_src_data), // .data
.out_endofpacket (sdram_tri_controller_0_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_tri_controller_0_s1_cmd_width_adapter_src_data), // .data
.out_channel (sdram_tri_controller_0_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sdram_tri_controller_0_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sdram_tri_controller_0_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_tri_controller_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (avalon_mapped_timer_reg_buf_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (vic_0_csr_access_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (vic_0_csr_access_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (vic_0_csr_access_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_1_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_1_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_1_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_2_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_2_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_2_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_3_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_3_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_3_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_007 #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_007 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sdram_tri_controller_0_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (sdram_tri_controller_0_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (sdram_tri_controller_0_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_007_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_008 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (io_update_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (io_update_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (io_update_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_008_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_008_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_008_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_008_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_009 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (pps_interrupt_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (pps_interrupt_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (pps_interrupt_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_009_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_009_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_009_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_009_out_0_error) // .error
);
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_010 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_010_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_010_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_010_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_010_out_0_error) // .error
);
endmodule |
module axi_mc_controller
(
input ref_clk, // 100 MHz
input ctrl_data_clk,
// physical interface
output fmc_en_o,
output pwm_ah_o,
output pwm_al_o,
output pwm_bh_o,
output pwm_bl_o,
output pwm_ch_o,
output pwm_cl_o,
output [3:0] gpo_o,
// controller connections
input pwm_a_i,
input pwm_b_i,
input pwm_c_i,
input ctrl_data_valid_i,
input [31:0] ctrl_data0_i,
input [31:0] ctrl_data1_i,
input [31:0] ctrl_data2_i,
input [31:0] ctrl_data3_i,
input [31:0] ctrl_data4_i,
input [31:0] ctrl_data5_i,
input [31:0] ctrl_data6_i,
input [31:0] ctrl_data7_i,
// interconnection with other modules
output[1:0] sensors_o,
input [2:0] position_i,
// channel interface
output adc_clk_o,
output adc_enable_c0,
output adc_enable_c1,
output adc_enable_c2,
output adc_enable_c3,
output adc_enable_c4,
output adc_enable_c5,
output adc_enable_c6,
output adc_enable_c7,
output adc_valid_c0,
output adc_valid_c1,
output adc_valid_c2,
output adc_valid_c3,
output adc_valid_c4,
output adc_valid_c5,
output adc_valid_c6,
output adc_valid_c7,
output [31:0] adc_data_c0,
output [31:0] adc_data_c1,
output [31:0] adc_data_c2,
output [31:0] adc_data_c3,
output [31:0] adc_data_c4,
output [31:0] adc_data_c5,
output [31:0] adc_data_c6,
output [31:0] adc_data_c7,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_wack = 'd0;
reg up_rack = 'd0;
reg pwm_gen_clk = 'd0;
//------------------------------------------------------------------------------
//----------- Wires Declarations -----------------------------------------------
//------------------------------------------------------------------------------
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire up_rreq_s;
wire up_wreq_s;
wire [13:0] up_raddr_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire [31:0] up_control_rdata_s;
wire [31:0] rdata_c0_s;
wire [31:0] rdata_c1_s;
wire [31:0] rdata_c2_s;
wire [31:0] rdata_c3_s;
wire [31:0] rdata_c4_s;
wire [31:0] rdata_c5_s;
wire [31:0] rdata_c6_s;
wire [31:0] rdata_c7_s;
wire up_adc_common_wack_s;
wire up_adc_common_rack_s;
wire up_control_wack_s;
wire up_control_rack_s;
wire wack_c0_s;
wire rack_c0_s;
wire wack_c1_s;
wire rack_c1_s;
wire wack_c2_s;
wire rack_c2_s;
wire wack_c3_s;
wire rack_c3_s;
wire wack_c4_s;
wire rack_c4_s;
wire wack_c5_s;
wire rack_c5_s;
wire wack_c6_s;
wire rack_c6_s;
wire wack_c7_s;
wire rack_c7_s;
wire run_s;
wire star_delta_s;
wire dir_s;
wire [10:0] pwm_open_s;
wire [10:0] pwm_s;
wire dpwm_ah_s;
wire dpwm_al_s;
wire dpwm_bh_s;
wire dpwm_bl_s;
wire dpwm_ch_s;
wire dpwm_cl_s;
wire foc_ctrl_s;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk_o = ctrl_data_clk;
assign adc_valid_c0 = ctrl_data_valid_i;
assign adc_valid_c1 = ctrl_data_valid_i;
assign adc_valid_c2 = ctrl_data_valid_i;
assign adc_valid_c3 = ctrl_data_valid_i;
assign adc_valid_c4 = ctrl_data_valid_i;
assign adc_valid_c5 = ctrl_data_valid_i;
assign adc_valid_c6 = ctrl_data_valid_i;
assign adc_valid_c7 = ctrl_data_valid_i;
assign adc_data_c0 = ctrl_data0_i;
assign adc_data_c1 = ctrl_data1_i;
assign adc_data_c2 = ctrl_data2_i;
assign adc_data_c3 = ctrl_data3_i;
assign adc_data_c4 = ctrl_data4_i;
assign adc_data_c5 = ctrl_data5_i;
assign adc_data_c6 = ctrl_data6_i;
assign adc_data_c7 = ctrl_data7_i;
assign ctrl_rst_o = !run_s;
// monitor signals
assign fmc_en_o = run_s;
assign pwm_s = pwm_open_s ;
assign pwm_ah_o = foc_ctrl_s ? !pwm_a_i : dpwm_ah_s;
assign pwm_al_o = foc_ctrl_s ? pwm_a_i : dpwm_al_s;
assign pwm_bh_o = foc_ctrl_s ? !pwm_b_i : dpwm_bh_s;
assign pwm_bl_o = foc_ctrl_s ? pwm_b_i : dpwm_bl_s;
assign pwm_ch_o = foc_ctrl_s ? !pwm_c_i : dpwm_ch_s;
assign pwm_cl_o = foc_ctrl_s ? pwm_c_i : dpwm_cl_s;
// clock generation
always @(posedge ref_clk)
begin
pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if(up_rstn == 0) begin
up_rdata <= 'd0;
up_wack <= 'd0;
up_rack <= 'd0;
end else begin
up_rdata <= up_control_rdata_s | up_adc_common_rdata_s | rdata_c0_s | rdata_c1_s | rdata_c2_s | rdata_c3_s | rdata_c4_s | rdata_c5_s | rdata_c6_s | rdata_c7_s;
up_rack <= up_control_rack_s | up_adc_common_rack_s | rack_c0_s | rack_c1_s | rack_c2_s | rack_c3_s | rack_c4_s | rack_c5_s | rack_c6_s | rack_c7_s;
up_wack <= up_control_wack_s | up_adc_common_wack_s | wack_c0_s | wack_c1_s | wack_c2_s | wack_c3_s | wack_c4_s | wack_c5_s | wack_c6_s | wack_c7_s;
end
end
// main (device interface)
motor_driver
#( .PWM_BITS(11))
motor_driver_inst(
.clk_i(ctrl_data_clk),
.pwm_clk_i(pwm_gen_clk),
.rst_n_i(up_rstn) ,
.run_i(run_s),
.star_delta_i(star_delta_s),
.dir_i(dir_s),
.position_i(position_i),
.pwm_duty_i(pwm_s),
.AH_o(dpwm_ah_s),
.BH_o(dpwm_bh_s),
.CH_o(dpwm_ch_s),
.AL_o(dpwm_al_s),
.BL_o(dpwm_bl_s),
.CL_o(dpwm_cl_s));
control_registers control_reg_inst(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_control_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_control_rdata_s),
.up_rack (up_control_rack_s),
.run_o(run_s),
.break_o(),
.dir_o(dir_s),
.star_delta_o(star_delta_s),
.sensors_o(sensors_o),
.kp_o(),
.ki_o(),
.kd_o(),
.kp1_o(),
.ki1_o(),
.kd1_o(),
.gpo_o(gpo_o),
.reference_speed_o(),
.oloop_matlab_o(foc_ctrl_s),
.err_i(32'h0),
.calibrate_adcs_o(),
.pwm_open_o(pwm_open_s));
up_adc_channel #(.PCORE_ADC_CHID(0)) adc_channel0(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c0),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c0_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c0_s),
.up_rack (rack_c0_s));
up_adc_channel #(.PCORE_ADC_CHID(1)) adc_channel1(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c1),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c1_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c1_s),
.up_rack (rack_c1_s));
up_adc_channel #(.PCORE_ADC_CHID(2)) adc_channel2(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c2),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c2_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c2_s),
.up_rack (rack_c2_s));
up_adc_channel #(.PCORE_ADC_CHID(3)) adc_channel3(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c3),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c3_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c3_s),
.up_rack (rack_c3_s));
up_adc_channel #(.PCORE_ADC_CHID(4)) adc_channel4(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c4),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c4_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c4_s),
.up_rack (rack_c4_s));
up_adc_channel #(.PCORE_ADC_CHID(5)) adc_channel5(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c5),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c5_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c5_s),
.up_rack (rack_c5_s));
up_adc_channel #(.PCORE_ADC_CHID(6)) adc_channel6(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c6),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c6_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c6_s),
.up_rack (rack_c6_s));
up_adc_channel #(.PCORE_ADC_CHID(7)) adc_channel7(
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_enable(adc_enable_c7),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(),
.adc_dfmt_type(),
.adc_dfmt_enable(),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(),
.adc_data_sel(),
.adc_pn_err(1'b0),
.adc_pn_oos(1'b0),
.adc_or(1'b0),
.up_adc_pn_err(),
.up_adc_pn_oos(),
.up_adc_or(),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (wack_c7_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (rdata_c7_s),
.up_rack (rack_c7_s));
// common processor control
up_adc_common i_up_adc_common(
.mmcm_rst(),
.adc_clk(ref_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(1'b1),
.adc_sync_status(1'b1),
.adc_status_ovf(1'b0),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd1),
.adc_start_code(),
.adc_sync(),
.up_status_pn_err(1'b0),
.up_status_pn_oos(1'b0),
.up_status_or(1'b0),
.up_drp_sel(),
.up_drp_wr(),
.up_drp_addr(),
.up_drp_wdata(),
.up_drp_rdata(16'd0),
.up_drp_ready(1'b0),
.up_drp_locked(1'b0),
.up_usr_chanmax(),
.adc_usr_chanmax(8'd7),
.up_adc_gpio_in(32'h0),
.up_adc_gpio_out(),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_adc_common_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_adc_common_rdata_s),
.up_rack (up_adc_common_rack_s));
// up bus interface
up_axi i_up_axi(
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule |
module CESR_MUX(input CE, SR, output CE_OUT, SR_OUT);
parameter _TECHMAP_CONSTMSK_CE_ = 0;
parameter _TECHMAP_CONSTVAL_CE_ = 0;
parameter _TECHMAP_CONSTMSK_SR_ = 0;
parameter _TECHMAP_CONSTVAL_SR_ = 0;
localparam CEUSED = _TECHMAP_CONSTMSK_CE_ == 0 || _TECHMAP_CONSTVAL_CE_ == 0;
localparam SRUSED = _TECHMAP_CONSTMSK_SR_ == 0 || _TECHMAP_CONSTVAL_SR_ == 1;
if(CEUSED) begin
assign CE_OUT = CE;
end else begin
CE_VCC ce(
.VCC(CE_OUT)
);
end
if(SRUSED) begin
assign SR_OUT = SR;
end else begin
SR_GND sr(
.GND(SR_OUT)
);
end
endmodule |
module FD (output reg Q, input C, D);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(1'b1),
.SR(1'b0),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDRE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .R(SR_SIG));
endmodule |
module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(R),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDRE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .R(SR_SIG));
endmodule |
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(S),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDSE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .S(SR_SIG));
endmodule |
module FDCE (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(CLR),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDCE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .CLR(SR_SIG));
endmodule |
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(PRE),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDPE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|0))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .PRE(SR_SIG));
endmodule |
module FDRE_1 (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(R),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDRE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|1))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .R(SR_SIG));
endmodule |
module FDSE_1 (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b1;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(S),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDSE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|1))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .S(SR_SIG));
endmodule |
module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(CLR),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDCE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|1))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .CLR(SR_SIG));
endmodule |
module FDPE_1 (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b1;
wire CE_SIG;
wire SR_SIG;
CESR_MUX cesr_mux(
.CE(CE),
.SR(PRE),
.CE_OUT(CE_SIG),
.SR_OUT(SR_SIG)
);
FDPE_ZINI #(.ZINI(!|INIT), .IS_C_INVERTED(|1))
_TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE_SIG), .PRE(SR_SIG));
endmodule |
module LUT1(output O, input I0);
parameter [1:0] INIT = 0;
\$lut #(
.WIDTH(1),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A(I0),
.Y(O)
);
endmodule |
module LUT2(output O, input I0, I1);
parameter [3:0] INIT = 0;
\$lut #(
.WIDTH(2),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I1, I0}),
.Y(O)
);
endmodule |
module LUT3(output O, input I0, I1, I2);
parameter [7:0] INIT = 0;
\$lut #(
.WIDTH(3),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I2, I1, I0}),
.Y(O)
);
endmodule |
module LUT4(output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
\$lut #(
.WIDTH(4),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I3, I2, I1, I0}),
.Y(O)
);
endmodule |
module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [31:0] INIT = 0;
\$lut #(
.WIDTH(5),
.LUT(INIT)
) _TECHMAP_REPLACE_ (
.A({I4, I3, I2, I1, I0}),
.Y(O)
);
endmodule |
module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
wire T0, T1;
\$lut #(
.WIDTH(5),
.LUT(INIT[31:0])
) fpga_lut_0 (
.A({I4, I3, I2, I1, I0}),
.Y(T0)
);
\$lut #(
.WIDTH(5),
.LUT(INIT[63:32])
) fpga_lut_1 (
.A({I4, I3, I2, I1, I0}),
.Y(T1)
);
MUXF6 fpga_mux_0 (.O(O), .I0(T0), .I1(T1), .S(I5));
endmodule |
module RAM128X1S (
output O,
input D, WCLK, WE,
input A6, A5, A4, A3, A2, A1, A0
);
parameter [127:0] INIT = 128'bx;
parameter IS_WCLK_INVERTED = 0;
wire low_lut_o6;
wire high_lut_o6;
wire [5:0] A = {A5, A4, A3, A2, A1, A0};
// DPRAM64_for_RAM128X1D is used here because RAM128X1S only consumes half of the
// slice, but WA7USED is slice wide. The packer should be able to pack two
// RAM128X1S in a slice, but it should not be able to pack RAM128X1S and
// a RAM64X1[SD]. It is unclear if RAM32X1[SD] or RAM32X2S can be packed
// with a RAM128X1S, so for now it is forbidden.
//
// Note that a RAM128X1D does not require [SD]PRAM128 because it consumes
// the entire slice.
DPRAM64_for_RAM128X1D #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
) ram0 (
.DI(D),
.A(A),
.WA(A),
.WA7(A6),
.CLK(WCLK),
.WE(WE),
.O(low_lut_o6)
);
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(1)
) ram1 (
.DI(D),
.A(A),
.WA(A),
.WA7(A6),
.CLK(WCLK),
.WE(WE),
.O(high_lut_o6)
);
MUXF7 ram_f7_mux (.O(O), .I0(low_lut_o6), .I1(high_lut_o6), .S(A6));
endmodule |
module RAM128X1D (
output DPO, SPO,
input D, WCLK, WE,
input [6:0] A, DPRA
);
parameter [127:0] INIT = 128'bx;
parameter IS_WCLK_INVERTED = 0;
wire dlut_o6;
wire clut_o6;
wire blut_o6;
wire alut_o6;
DPRAM64_for_RAM128X1D #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
) ram0 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.CLK(WCLK),
.WE(WE),
.O(dlut_o6)
);
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(1)
) ram1 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.CLK(WCLK),
.WE(WE),
.O(clut_o6)
);
DPRAM64_for_RAM128X1D #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
) ram2 (
.DI(D),
.A(DPRA[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.CLK(WCLK),
.WE(WE),
.O(blut_o6)
);
DPRAM64_for_RAM128X1D #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.HIGH_WA7_SELECT(0)
) ram3 (
.DI(D),
.A(DPRA[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.CLK(WCLK),
.WE(WE),
.O(alut_o6)
);
wire SPO_FORCE;
wire DPO_FORCE;
MUXF7 f7b_mux (.O(SPO_FORCE), .I0(dlut_o6), .I1(clut_o6), .S(A[6]));
MUXF7 f7a_mux (.O(DPO_FORCE), .I0(blut_o6), .I1(alut_o6), .S(DPRA[6]));
DRAM_2_OUTPUT_STUB stub (
.SPO(SPO_FORCE), .DPO(DPO_FORCE),
.SPO_OUT(SPO), .DPO_OUT(DPO));
endmodule |
module RAM256X1S (
output O,
input D, WCLK, WE,
input [7:0] A
);
parameter [256:0] INIT = 256'bx;
parameter IS_WCLK_INVERTED = 0;
wire dlut_o6;
wire clut_o6;
wire blut_o6;
wire alut_o6;
wire f7b_o;
wire f7a_o;
DPRAM64 #(
.INIT(INIT[63:0]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.WA7USED(1),
.WA8USED(1),
.HIGH_WA7_SELECT(0),
.HIGH_WA8_SELECT(0)
) ram0 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.WA8(A[7]),
.CLK(WCLK),
.WE(WE),
.O(dlut_o6)
);
DPRAM64 #(
.INIT(INIT[127:64]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.WA7USED(1),
.WA8USED(1),
.HIGH_WA7_SELECT(1),
.HIGH_WA8_SELECT(0)
) ram1 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.WA8(A[7]),
.CLK(WCLK),
.WE(WE),
.O(clut_o6)
);
DPRAM64 #(
.INIT(INIT[191:128]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.WA7USED(1),
.WA8USED(1),
.HIGH_WA7_SELECT(0),
.HIGH_WA8_SELECT(1)
) ram2 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.WA8(A[7]),
.CLK(WCLK),
.WE(WE),
.O(blut_o6)
);
DPRAM64 #(
.INIT(INIT[255:192]),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED),
.WA7USED(1),
.WA8USED(1),
.HIGH_WA7_SELECT(1),
.HIGH_WA8_SELECT(1)
) ram3 (
.DI(D),
.A(A[5:0]),
.WA(A[5:0]),
.WA7(A[6]),
.WA8(A[7]),
.CLK(WCLK),
.WE(WE),
.O(alut_o6)
);
MUXF7 f7b_mux (.O(f7b_o), .I0(dlut_o6), .I1(clut_o6), .S(A[6]));
MUXF7 f7a_mux (.O(f7a_o), .I0(blut_o6), .I1(alut_o6), .S(A[6]));
MUXF8 f8_mux (.O(O), .I0(f7b_o), .I1(f7a_o), .S(A[7]));
endmodule |
module RAM32X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter [31:0] INIT = 32'bx;
parameter IS_WCLK_INVERTED = 0;
wire [4:0] WA = {A4, A3, A2, A1, A0};
wire [4:0] DPRA = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
wire SPO_FORCE, DPO_FORCE;
DPRAM32 #(
.INIT_00(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram0 (
.DI(D),
.A(WA),
.WA(WA),
.CLK(WCLK),
.WE(WE),
.O(SPO_FORCE)
);
DPRAM32 #(
.INIT_00(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram1 (
.DI(D),
.A(DPRA),
.WA(WA),
.CLK(WCLK),
.WE(WE),
.O(DPO_FORCE)
);
DRAM_2_OUTPUT_STUB stub (
.SPO(SPO_FORCE), .DPO(DPO_FORCE),
.SPO_OUT(SPO), .DPO_OUT(DPO));
endmodule |
module RAM32X1S (
output O,
input D, WCLK, WE,
input A0, A1, A2, A3, A4
);
parameter [31:0] INIT = 32'bx;
parameter IS_WCLK_INVERTED = 0;
SPRAM32 #(
.INIT_00(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_S (
.DI(D),
.A({A4, A3, A2, A1, A0}),
.WA({A4, A3, A2, A1, A0}),
.CLK(WCLK),
.WE(WE),
.O(O)
);
endmodule |
module RAM32X2S (
output O0, O1,
input D0, D1, WCLK, WE,
input A0, A1, A2, A3, A4
);
parameter [31:0] INIT_00 = 32'bx;
parameter [31:0] INIT_01 = 32'bx;
parameter IS_WCLK_INVERTED = 0;
DPRAM32 #(
.INIT_00(INIT_00),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram0 (
.DI(D0),
.A({A4, A3, A2, A1, A0}),
.WA({A4, A3, A2, A1, A0}),
.CLK(WCLK),
.WE(WE),
.O(O0)
);
DPRAM32 #(
.INIT_00(INIT_01),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram1 (
.DI(D1),
.A({A4, A3, A2, A1, A0}),
.WA({A4, A3, A2, A1, A0}),
.CLK(WCLK),
.WE(WE),
.O(O1),
);
endmodule |
module RAM32M (
output [1:0] DOA, DOB, DOC, DOD,
input [1:0] DIA, DIB, DIC, DID,
input [4:0] ADDRA, ADDRB, ADDRC, ADDRD,
input WE, WCLK
);
parameter [63:0] INIT_A = 64'bx;
parameter [63:0] INIT_B = 64'bx;
parameter [63:0] INIT_C = 64'bx;
parameter [63:0] INIT_D = 64'bx;
parameter IS_WCLK_INVERTED = 0;
wire [1:0] DOD_TO_STUB;
wire [1:0] DOC_TO_STUB;
wire [1:0] DOB_TO_STUB;
wire [1:0] DOA_TO_STUB;
function [31:0] every_other_bit_32;
input [63:0] in;
input odd;
integer i;
for (i = 0; i < 32; i = i + 1) begin
every_other_bit_32[i] = in[i * 2 + odd];
end
endfunction
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_A, 1'b1)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_a1 (
.DI(DIA[1]),
.A(ADDRA),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOA_TO_STUB[1])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_A, 1'b0)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_a0 (
.DI(DIA[0]),
.A(ADDRA),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOA_TO_STUB[0])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_B, 1'b1)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_b1 (
.DI(DIB[1]),
.A(ADDRB),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOB_TO_STUB[1])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_B, 1'b0)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_b0 (
.DI(DIB[0]),
.A(ADDRB),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOB_TO_STUB[0])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_C, 1'b1)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_c1 (
.DI(DIC[1]),
.A(ADDRC),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOC_TO_STUB[1])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_C, 1'b0)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_c0 (
.DI(DIC[0]),
.A(ADDRC),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOC_TO_STUB[0])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_D, 1'b1)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_d1 (
.DI(DID[1]),
.A(ADDRD),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOD_TO_STUB[1])
);
DPRAM32 #(
.INIT_00(every_other_bit_32(INIT_D, 0)),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) ram_d0 (
.DI(DID[0]),
.A(ADDRD),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOD_TO_STUB[0])
);
DRAM_8_OUTPUT_STUB stub (
.DOD1(DOD_TO_STUB[1]), .DOD1_OUT(DOD[1]),
.DOC1(DOC_TO_STUB[1]), .DOC1_OUT(DOC[1]),
.DOB1(DOB_TO_STUB[1]), .DOB1_OUT(DOB[1]),
.DOA1(DOA_TO_STUB[1]), .DOA1_OUT(DOA[1]),
.DOD0(DOD_TO_STUB[0]), .DOD0_OUT(DOD[0]),
.DOC0(DOC_TO_STUB[0]), .DOC0_OUT(DOC[0]),
.DOB0(DOB_TO_STUB[0]), .DOB0_OUT(DOB[0]),
.DOA0(DOA_TO_STUB[0]), .DOA0_OUT(DOA[0])
);
endmodule |
module RAM64M (
output DOA, DOB, DOC, DOD,
input DIA, DIB, DIC, DID,
input [5:0] ADDRA, ADDRB, ADDRC, ADDRD,
input WE, WCLK
);
parameter [63:0] INIT_A = 64'bx;
parameter [63:0] INIT_B = 64'bx;
parameter [63:0] INIT_C = 64'bx;
parameter [63:0] INIT_D = 64'bx;
parameter IS_WCLK_INVERTED = 0;
wire DOD_TO_STUB;
wire DOC_TO_STUB;
wire DOB_TO_STUB;
wire DOA_TO_STUB;
DPRAM64 #(
.INIT(INIT_D),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_d (
.DI(DID),
.A(ADDRD),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOD_TO_STUB)
);
DPRAM64 #(
.INIT(INIT_C),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_c (
.DI(DIC),
.A(ADDRC),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOC_TO_STUB)
);
DPRAM64 #(
.INIT(INIT_B),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_b (
.DI(DIB),
.A(ADDRB),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOB_TO_STUB)
);
DPRAM64 #(
.INIT(INIT_A),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram_a (
.DI(DIA),
.A(ADDRA),
.WA(ADDRD),
.CLK(WCLK),
.WE(WE),
.O(DOA_TO_STUB)
);
DRAM_4_OUTPUT_STUB stub (
.DOD(DOD_TO_STUB), .DOD_OUT(DOD),
.DOC(DOC_TO_STUB), .DOC_OUT(DOC),
.DOB(DOB_TO_STUB), .DOB_OUT(DOB),
.DOA(DOA_TO_STUB), .DOA_OUT(DOA)
);
endmodule |
module RAM64X1D (
output DPO, SPO,
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter [63:0] INIT = 64'bx;
parameter IS_WCLK_INVERTED = 0;
wire [5:0] WA = {A5, A4, A3, A2, A1, A0};
wire [5:0] DPRA = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
wire SPO_FORCE, DPO_FORCE;
DPRAM64 #(
.INIT(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram1 (
.DI(D),
.A(WA),
.WA(WA),
.CLK(WCLK),
.WE(WE),
.O(SPO_FORCE)
);
wire Dstub;
DI64_STUB stub1 (
.DI(D),
.DO(Dstub)
);
DPRAM64 #(
.INIT(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram0 (
.DI(Dstub),
.A(DPRA),
.WA(WA),
.CLK(WCLK),
.WE(WE),
.O(DPO_FORCE)
);
DRAM_2_OUTPUT_STUB stub (
.SPO(SPO_FORCE), .DPO(DPO_FORCE),
.SPO_OUT(SPO), .DPO_OUT(DPO));
endmodule |
module RAM64X1S (
output O,
input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5
);
parameter [63:0] INIT = 64'bx;
parameter IS_WCLK_INVERTED = 0;
DPRAM64 #(
.INIT(INIT),
.IS_WCLK_INVERTED(IS_WCLK_INVERTED)
) dram0 (
.DI(D),
.A({A5, A4, A3, A2, A1, A0}),
.WA({A5, A4, A3, A2, A1, A0}),
.CLK(WCLK),
.WE(WE),
.O(O)
);
endmodule |
module RAMB18E1 (
input CLKARDCLK,
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input [13:0] ADDRARDADDR,
input [13:0] ADDRBWRADDR,
input [15:0] DIADI,
input [15:0] DIBDI,
input [1:0] DIPADIP,
input [1:0] DIPBDIP,
input [1:0] WEA,
input [3:0] WEBWE,
output [15:0] DOADO,
output [15:0] DOBDO,
output [1:0] DOPADOP,
output [1:0] DOPBDOP
);
parameter INIT_A = 18'h0;
parameter INIT_B = 18'h0;
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 18'h0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter _TECHMAP_CONSTMSK_CLKARDCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKARDCLK_ = 0;
parameter _TECHMAP_CONSTMSK_CLKBWRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKBWRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_REGCLKARDRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_REGCLKARDRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_RSTRAMARSTRAM_ = 0;
parameter _TECHMAP_CONSTVAL_RSTRAMARSTRAM_ = 0;
parameter _TECHMAP_CONSTMSK_RSTRAMB_ = 0;
parameter _TECHMAP_CONSTVAL_RSTRAMB_ = 0;
parameter _TECHMAP_CONSTMSK_RSTREGARSTREG_ = 0;
parameter _TECHMAP_CONSTVAL_RSTREGARSTREG_ = 0;
parameter _TECHMAP_CONSTMSK_RSTREGB_ = 0;
parameter _TECHMAP_CONSTVAL_RSTREGB_ = 0;
parameter RAM_MODE = "TDP";
parameter SIM_DEVICE = "7SERIES";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
reg _TECHMAP_FAIL_;
reg GENERATE_ERROR;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
localparam INV_CLKARDCLK = (_TECHMAP_CONSTMSK_CLKARDCLK_ == 1) ? !_TECHMAP_CONSTVAL_CLKARDCLK_ ^ IS_CLKARDCLK_INVERTED :
(_TECHMAP_CONSTVAL_CLKARDCLK_ === 0) ? ~IS_CLKARDCLK_INVERTED : IS_CLKARDCLK_INVERTED;
wire clkardclk = (_TECHMAP_CONSTMSK_CLKARDCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKARDCLK_ === 0) ? 1'b1 : CLKARDCLK;
localparam INV_CLKBWRCLK = (_TECHMAP_CONSTMSK_CLKBWRCLK_ == 1) ? !_TECHMAP_CONSTVAL_CLKBWRCLK_ ^ IS_CLKBWRCLK_INVERTED :
(_TECHMAP_CONSTVAL_CLKBWRCLK_ === 0) ? ~IS_CLKBWRCLK_INVERTED : IS_CLKBWRCLK_INVERTED;
wire clkbwrclk = (_TECHMAP_CONSTMSK_CLKBWRCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKBWRCLK_ === 0) ? 1'b1 : CLKBWRCLK;
localparam INV_RSTRAMARSTRAM = (_TECHMAP_CONSTMSK_RSTRAMARSTRAM_ == 1) ? !_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ ^ IS_RSTRAMARSTRAM_INVERTED :
(_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ === 0) ? ~IS_RSTRAMARSTRAM_INVERTED : IS_RSTRAMARSTRAM_INVERTED;
wire rstramarstram = (_TECHMAP_CONSTMSK_RSTRAMARSTRAM_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ === 0) ? 1'b1 : RSTRAMARSTRAM;
localparam INV_RSTRAMB = (_TECHMAP_CONSTMSK_RSTRAMB_ == 1) ? !_TECHMAP_CONSTVAL_RSTRAMB_ ^ IS_RSTRAMB_INVERTED :
(_TECHMAP_CONSTVAL_RSTRAMB_ === 0) ? ~IS_RSTRAMB_INVERTED : IS_RSTRAMB_INVERTED;
wire rstramb = (_TECHMAP_CONSTMSK_RSTRAMB_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTRAMB_ === 0) ? 1'b1 : RSTRAMB;
localparam INV_RSTREGARSTREG = (_TECHMAP_CONSTMSK_RSTREGARSTREG_ == 1) ? !_TECHMAP_CONSTVAL_RSTREGARSTREG_ ^ IS_RSTREGARSTREG_INVERTED :
(_TECHMAP_CONSTVAL_RSTREGARSTREG_ === 0) ? ~IS_RSTREGARSTREG_INVERTED : IS_RSTREGARSTREG_INVERTED;
wire rstregarstreg = (_TECHMAP_CONSTMSK_RSTREGARSTREG_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTREGARSTREG_ === 0) ? 1'b1 : RSTREGARSTREG;
localparam INV_RSTREGB = (_TECHMAP_CONSTMSK_RSTREGB_ == 1) ? !_TECHMAP_CONSTVAL_RSTREGB_ ^ IS_RSTREGB_INVERTED :
(_TECHMAP_CONSTVAL_RSTREGB_ === 0) ? ~IS_RSTREGB_INVERTED : IS_RSTREGB_INVERTED;
wire rstregb = (_TECHMAP_CONSTMSK_RSTREGB_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTREGB_ === 0) ? 1'b1 : RSTREGB;
initial begin
_TECHMAP_FAIL_ <= 0;
if(READ_WIDTH_A != 0
&& READ_WIDTH_A != 1
&& READ_WIDTH_A != 2
&& READ_WIDTH_A != 4
&& READ_WIDTH_A != 9
&& READ_WIDTH_A != 18
&& READ_WIDTH_A != 36)
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(READ_WIDTH_B != 0
&& READ_WIDTH_B != 1
&& READ_WIDTH_B != 2
&& READ_WIDTH_B != 4
&& READ_WIDTH_B != 9
&& READ_WIDTH_B != 18)
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(WRITE_WIDTH_A != 0
&& WRITE_WIDTH_A != 1
&& WRITE_WIDTH_A != 2
&& WRITE_WIDTH_A != 4
&& WRITE_WIDTH_A != 9
&& WRITE_WIDTH_A != 18)
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(WRITE_WIDTH_B != 0
&& WRITE_WIDTH_B != 1
&& WRITE_WIDTH_B != 2
&& WRITE_WIDTH_B != 4
&& WRITE_WIDTH_B != 9
&& WRITE_WIDTH_B != 18
&& WRITE_WIDTH_B != 36)
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(READ_WIDTH_A > 18 && RAM_MODE != "SDP") begin
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
if(WRITE_WIDTH_B > 18 && RAM_MODE != "SDP") begin
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
if(WRITE_MODE_A != "WRITE_FIRST" && WRITE_MODE_A != "NO_CHANGE" && WRITE_MODE_A != "READ_FIRST")
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(WRITE_MODE_B != "WRITE_FIRST" && WRITE_MODE_B != "NO_CHANGE" && WRITE_MODE_B != "READ_FIRST")
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
localparam EFF_READ_WIDTH_A = (RAM_MODE == "SDP" && READ_WIDTH_A == 36) ? 18 : READ_WIDTH_A;
localparam EFF_READ_WIDTH_B = (RAM_MODE == "SDP" && READ_WIDTH_A == 36) ? 18 : READ_WIDTH_B;
localparam EFF_WRITE_WIDTH_A = (RAM_MODE == "SDP" && WRITE_WIDTH_B == 36) ? 18 : WRITE_WIDTH_A;
localparam EFF_WRITE_WIDTH_B = (RAM_MODE == "SDP" && WRITE_WIDTH_B == 36) ? 18 : WRITE_WIDTH_B;
wire REGCLKA;
wire REGCLKB;
wire [7:0] WEBWE_WIDE;
wire [3:0] WEA_WIDE;
if(WRITE_WIDTH_A < 18) begin
assign WEA_WIDE[3] = WEA[0];
assign WEA_WIDE[2] = WEA[0];
assign WEA_WIDE[1] = WEA[0];
assign WEA_WIDE[0] = WEA[0];
end else if(WRITE_WIDTH_A == 18) begin
assign WEA_WIDE[3] = WEA[1];
assign WEA_WIDE[2] = WEA[1];
assign WEA_WIDE[1] = WEA[0];
assign WEA_WIDE[0] = WEA[0];
end
if(WRITE_WIDTH_B < 18) begin
assign WEBWE_WIDE[7:4] = 4'b0;
assign WEBWE_WIDE[3] = WEBWE[0];
assign WEBWE_WIDE[2] = WEBWE[0];
assign WEBWE_WIDE[1] = WEBWE[0];
assign WEBWE_WIDE[0] = WEBWE[0];
end else if(WRITE_WIDTH_B == 18) begin
assign WEBWE_WIDE[7:4] = 4'b0;
assign WEBWE_WIDE[3] = WEBWE[1];
assign WEBWE_WIDE[2] = WEBWE[1];
assign WEBWE_WIDE[1] = WEBWE[0];
assign WEBWE_WIDE[0] = WEBWE[0];
end else begin
assign WEA_WIDE[3:0] = 4'b0;
assign WEBWE_WIDE[7] = WEBWE[3];
assign WEBWE_WIDE[6] = WEBWE[3];
assign WEBWE_WIDE[5] = WEBWE[2];
assign WEBWE_WIDE[4] = WEBWE[2];
assign WEBWE_WIDE[3] = WEBWE[1];
assign WEBWE_WIDE[2] = WEBWE[1];
assign WEBWE_WIDE[1] = WEBWE[0];
assign WEBWE_WIDE[0] = WEBWE[0];
end
assign REGCLKA = DOA_REG ? CLKARDCLK : 1'b1;
localparam ZINV_REGCLKARDRCLK = (DOA_REG && !IS_CLKARDCLK_INVERTED);
assign REGCLKB = DOB_REG ? CLKBWRCLK : 1'b1;
localparam ZINV_REGCLKB = (DOB_REG && !IS_CLKBWRCLK_INVERTED);
RAMB18E1_VPR #(
.IN_USE(READ_WIDTH_A != 0 || READ_WIDTH_B != 0 || WRITE_WIDTH_A != 0 || WRITE_WIDTH_B != 0),
.ZINIT_A(INIT_A ^ {18{1'b1}}),
.ZINIT_B(INIT_B ^ {18{1'b1}}),
.ZSRVAL_A(SRVAL_A ^ {18{1'b1}}),
.ZSRVAL_B(SRVAL_B ^ {18{1'b1}}),
.INITP_00(INITP_00),
.INITP_01(INITP_01),
.INITP_02(INITP_02),
.INITP_03(INITP_03),
.INITP_04(INITP_04),
.INITP_05(INITP_05),
.INITP_06(INITP_06),
.INITP_07(INITP_07),
.INIT_00(INIT_00),
.INIT_01(INIT_01),
.INIT_02(INIT_02),
.INIT_03(INIT_03),
.INIT_04(INIT_04),
.INIT_05(INIT_05),
.INIT_06(INIT_06),
.INIT_07(INIT_07),
.INIT_08(INIT_08),
.INIT_09(INIT_09),
.INIT_0A(INIT_0A),
.INIT_0B(INIT_0B),
.INIT_0C(INIT_0C),
.INIT_0D(INIT_0D),
.INIT_0E(INIT_0E),
.INIT_0F(INIT_0F),
.INIT_10(INIT_10),
.INIT_11(INIT_11),
.INIT_12(INIT_12),
.INIT_13(INIT_13),
.INIT_14(INIT_14),
.INIT_15(INIT_15),
.INIT_16(INIT_16),
.INIT_17(INIT_17),
.INIT_18(INIT_18),
.INIT_19(INIT_19),
.INIT_1A(INIT_1A),
.INIT_1B(INIT_1B),
.INIT_1C(INIT_1C),
.INIT_1D(INIT_1D),
.INIT_1E(INIT_1E),
.INIT_1F(INIT_1F),
.INIT_20(INIT_20),
.INIT_21(INIT_21),
.INIT_22(INIT_22),
.INIT_23(INIT_23),
.INIT_24(INIT_24),
.INIT_25(INIT_25),
.INIT_26(INIT_26),
.INIT_27(INIT_27),
.INIT_28(INIT_28),
.INIT_29(INIT_29),
.INIT_2A(INIT_2A),
.INIT_2B(INIT_2B),
.INIT_2C(INIT_2C),
.INIT_2D(INIT_2D),
.INIT_2E(INIT_2E),
.INIT_2F(INIT_2F),
.INIT_30(INIT_30),
.INIT_31(INIT_31),
.INIT_32(INIT_32),
.INIT_33(INIT_33),
.INIT_34(INIT_34),
.INIT_35(INIT_35),
.INIT_36(INIT_36),
.INIT_37(INIT_37),
.INIT_38(INIT_38),
.INIT_39(INIT_39),
.INIT_3A(INIT_3A),
.INIT_3B(INIT_3B),
.INIT_3C(INIT_3C),
.INIT_3D(INIT_3D),
.INIT_3E(INIT_3E),
.INIT_3F(INIT_3F),
.ZINV_CLKARDCLK(!IS_CLKARDCLK_INVERTED ^ INV_CLKARDCLK),
.ZINV_CLKBWRCLK(!IS_CLKBWRCLK_INVERTED ^ INV_CLKBWRCLK),
.ZINV_ENARDEN(!IS_ENARDEN_INVERTED),
.ZINV_ENBWREN(!IS_ENBWREN_INVERTED),
.ZINV_RSTRAMARSTRAM(!IS_RSTRAMARSTRAM_INVERTED ^ INV_RSTRAMARSTRAM),
.ZINV_RSTRAMB(!IS_RSTRAMB_INVERTED ^ INV_RSTRAMB),
.ZINV_RSTREGARSTREG(!IS_RSTREGARSTREG_INVERTED ^ INV_RSTREGARSTREG),
.ZINV_RSTREGB(!IS_RSTREGB_INVERTED ^ INV_RSTREGB),
.ZINV_REGCLKARDRCLK(ZINV_REGCLKARDRCLK),
.ZINV_REGCLKB(ZINV_REGCLKB),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
// Assign special parameters relative to the RAMB site location.
// These is needed after the findings gathered with https://github.com/SymbiFlow/prjxray/pull/1263
// The rules to assign the correct READ_WIDTH_A parameter are the following:
// - Y0 RAMB18 and SDP mode: READ_WIDTH_A must be 1
// - Y1 RAMB18 and SDP mode: READ_WIDTH_A must be 18
// - No SDP: READ_WIDTH_A assumes the right value based on EFF_READ_WIDTH_A
.Y0_READ_WIDTH_A_1(READ_WIDTH_A == 36 || EFF_READ_WIDTH_A == 1 || EFF_READ_WIDTH_A == 0),
.Y1_READ_WIDTH_A_1(READ_WIDTH_A != 36 && (EFF_READ_WIDTH_A == 1 || EFF_READ_WIDTH_A == 0)),
.Y0_READ_WIDTH_A_18(READ_WIDTH_A != 36 && EFF_READ_WIDTH_A == 18),
.Y1_READ_WIDTH_A_18(READ_WIDTH_A == 36 || EFF_READ_WIDTH_A == 18),
.READ_WIDTH_A_1(EFF_READ_WIDTH_A == 1 || EFF_READ_WIDTH_A == 0),
.READ_WIDTH_A_2(EFF_READ_WIDTH_A == 2),
.READ_WIDTH_A_4(EFF_READ_WIDTH_A == 4),
.READ_WIDTH_A_9(EFF_READ_WIDTH_A == 9),
.READ_WIDTH_A_18(EFF_READ_WIDTH_A == 18),
.SDP_READ_WIDTH_36(READ_WIDTH_A == 36),
.READ_WIDTH_B_1(EFF_READ_WIDTH_B == 1 || EFF_READ_WIDTH_B == 0),
.READ_WIDTH_B_2(EFF_READ_WIDTH_B == 2),
.READ_WIDTH_B_4(EFF_READ_WIDTH_B == 4),
.READ_WIDTH_B_9(EFF_READ_WIDTH_B == 9),
.READ_WIDTH_B_18(EFF_READ_WIDTH_B == 18),
.WRITE_WIDTH_A_1(EFF_WRITE_WIDTH_A == 1 || EFF_WRITE_WIDTH_A == 0),
.WRITE_WIDTH_A_2(EFF_WRITE_WIDTH_A == 2),
.WRITE_WIDTH_A_4(EFF_WRITE_WIDTH_A == 4),
.WRITE_WIDTH_A_9(EFF_WRITE_WIDTH_A == 9),
.WRITE_WIDTH_A_18(EFF_WRITE_WIDTH_A == 18),
.WRITE_WIDTH_B_1(EFF_WRITE_WIDTH_B == 1 || EFF_WRITE_WIDTH_B == 0),
.WRITE_WIDTH_B_2(EFF_WRITE_WIDTH_B == 2),
.WRITE_WIDTH_B_4(EFF_WRITE_WIDTH_B == 4),
.WRITE_WIDTH_B_9(EFF_WRITE_WIDTH_B == 9),
.WRITE_WIDTH_B_18(EFF_WRITE_WIDTH_B == 18 || EFF_WRITE_WIDTH_B == 36),
.SDP_WRITE_WIDTH_36(WRITE_WIDTH_B == 36),
.WRITE_MODE_A_NO_CHANGE(WRITE_MODE_A == "NO_CHANGE" || (WRITE_MODE_A == "WRITE_FIRST" && RAM_MODE == "SDP")),
.WRITE_MODE_A_READ_FIRST(WRITE_MODE_A == "READ_FIRST"),
.WRITE_MODE_B_NO_CHANGE(WRITE_MODE_B == "NO_CHANGE" || (WRITE_MODE_B == "WRITE_FIRST" && RAM_MODE == "SDP")),
.WRITE_MODE_B_READ_FIRST(WRITE_MODE_B == "READ_FIRST")
) _TECHMAP_REPLACE_ (
.CLKARDCLK(clkardclk),
.REGCLKARDRCLK(REGCLKA),
.CLKBWRCLK(clkbwrclk),
.REGCLKB(REGCLKB),
.ENARDEN(ENARDEN),
.ENBWREN(ENBWREN),
.REGCEAREGCE(REGCEAREGCE),
.REGCEB(REGCEB),
.RSTRAMARSTRAM(rstramarstram),
.RSTRAMB(rstramb),
.RSTREGARSTREG(rstregarstreg),
.RSTREGB(rstregb),
.ADDRATIEHIGH(2'b11),
.ADDRARDADDR(ADDRARDADDR),
.ADDRBTIEHIGH(2'b11),
.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIBDI(DIBDI),
.DIPADIP(DIPADIP),
.DIPBDIP(DIPBDIP),
.WEA(WEA_WIDE),
.WEBWE(WEBWE_WIDE),
.DOADO(DOADO),
.DOBDO(DOBDO),
.DOPADOP(DOPADOP),
.DOPBDOP(DOPBDOP)
);
endmodule |
module RAMB36E1 (
input CLKARDCLK,
input CLKBWRCLK,
input ENARDEN,
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
input RSTRAMARSTRAM,
input RSTRAMB,
input RSTREGARSTREG,
input RSTREGB,
input [14:0] ADDRARDADDR,
input [14:0] ADDRBWRADDR,
input [31:0] DIADI,
input [31:0] DIBDI,
input [3:0] DIPADIP,
input [3:0] DIPBDIP,
input [3:0] WEA,
input [7:0] WEBWE,
output [31:0] DOADO,
output [31:0] DOBDO,
output [3:0] DOPADOP,
output [3:0] DOPBDOP
);
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
`define INIT_BLOCK(pre) \
parameter ``pre``0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``A = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``B = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``C = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``D = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``E = 256'h0000000000000000000000000000000000000000000000000000000000000000; \
parameter ``pre``F = 256'h0000000000000000000000000000000000000000000000000000000000000000
`INIT_BLOCK(INITP_0);
`INIT_BLOCK(INIT_0);
`INIT_BLOCK(INIT_1);
`INIT_BLOCK(INIT_2);
`INIT_BLOCK(INIT_3);
`INIT_BLOCK(INIT_4);
`INIT_BLOCK(INIT_5);
`INIT_BLOCK(INIT_6);
`INIT_BLOCK(INIT_7);
`undef INIT_BLOCK
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter _TECHMAP_CONSTMSK_CLKARDCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKARDCLK_ = 0;
parameter _TECHMAP_CONSTMSK_CLKBWRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKBWRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_REGCLKARDRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_REGCLKARDRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_RSTRAMARSTRAM_ = 0;
parameter _TECHMAP_CONSTVAL_RSTRAMARSTRAM_ = 0;
parameter _TECHMAP_CONSTMSK_RSTRAMB_ = 0;
parameter _TECHMAP_CONSTVAL_RSTRAMB_ = 0;
parameter _TECHMAP_CONSTMSK_RSTREGARSTREG_ = 0;
parameter _TECHMAP_CONSTVAL_RSTREGARSTREG_ = 0;
parameter _TECHMAP_CONSTMSK_RSTREGB_ = 0;
parameter _TECHMAP_CONSTVAL_RSTREGB_ = 0;
parameter RAM_MODE = "TDP";
parameter SIM_DEVICE = "7SERIES";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
reg _TECHMAP_FAIL_;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
localparam INV_CLKARDCLK = (_TECHMAP_CONSTMSK_CLKARDCLK_ == 1) ? !_TECHMAP_CONSTVAL_CLKARDCLK_ ^ IS_CLKARDCLK_INVERTED :
(_TECHMAP_CONSTVAL_CLKARDCLK_ === 0) ? ~IS_CLKARDCLK_INVERTED : IS_CLKARDCLK_INVERTED;
wire clkardclk = (_TECHMAP_CONSTMSK_CLKARDCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKARDCLK_ === 0) ? 1'b1 : CLKARDCLK;
localparam INV_CLKBWRCLK = (_TECHMAP_CONSTMSK_CLKBWRCLK_ == 1) ? !_TECHMAP_CONSTVAL_CLKBWRCLK_ ^ IS_CLKBWRCLK_INVERTED :
(_TECHMAP_CONSTVAL_CLKBWRCLK_ === 0) ? ~IS_CLKBWRCLK_INVERTED : IS_CLKBWRCLK_INVERTED;
wire clkbwrclk = (_TECHMAP_CONSTMSK_CLKBWRCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKBWRCLK_ === 0) ? 1'b1 : CLKBWRCLK;
localparam INV_RSTRAMARSTRAM = (_TECHMAP_CONSTMSK_RSTRAMARSTRAM_ == 1) ? !_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ ^ IS_RSTRAMARSTRAM_INVERTED :
(_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ === 0) ? ~IS_RSTRAMARSTRAM_INVERTED : IS_RSTRAMARSTRAM_INVERTED;
wire rstramarstram = (_TECHMAP_CONSTMSK_RSTRAMARSTRAM_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTRAMARSTRAM_ === 0) ? 1'b1 : RSTRAMARSTRAM;
localparam INV_RSTRAMB = (_TECHMAP_CONSTMSK_RSTRAMB_ == 1) ? !_TECHMAP_CONSTVAL_RSTRAMB_ ^ IS_RSTRAMB_INVERTED :
(_TECHMAP_CONSTVAL_RSTRAMB_ === 0) ? ~IS_RSTRAMB_INVERTED : IS_RSTRAMB_INVERTED;
wire rstramb = (_TECHMAP_CONSTMSK_RSTRAMB_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTRAMB_ === 0) ? 1'b1 : RSTRAMB;
localparam INV_RSTREGARSTREG = (_TECHMAP_CONSTMSK_RSTREGARSTREG_ == 1) ? !_TECHMAP_CONSTVAL_RSTREGARSTREG_ ^ IS_RSTREGARSTREG_INVERTED :
(_TECHMAP_CONSTVAL_RSTREGARSTREG_ === 0) ? ~IS_RSTREGARSTREG_INVERTED : IS_RSTREGARSTREG_INVERTED;
wire rstregarstreg = (_TECHMAP_CONSTMSK_RSTREGARSTREG_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTREGARSTREG_ === 0) ? 1'b1 : RSTREGARSTREG;
localparam INV_RSTREGB = (_TECHMAP_CONSTMSK_RSTREGB_ == 1) ? !_TECHMAP_CONSTVAL_RSTREGB_ ^ IS_RSTREGB_INVERTED :
(_TECHMAP_CONSTVAL_RSTREGB_ === 0) ? ~IS_RSTREGB_INVERTED : IS_RSTREGB_INVERTED;
wire rstregb = (_TECHMAP_CONSTMSK_RSTREGB_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RSTREGB_ === 0) ? 1'b1 : RSTREGB;
initial begin
_TECHMAP_FAIL_ <= 0;
`define INVALID_WIDTH(x) \
((x) != 0 \
&& (x) != 1 \
&& (x) != 2 \
&& (x) != 4 \
&& (x) != 9 \
&& (x) != 18 \
&& (x) != 36)
`define INVALID_WIDTH_WIDE(x) \
(`INVALID_WIDTH(x) \
&& (x) != 72)
if(`INVALID_WIDTH_WIDE(READ_WIDTH_A))
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(`INVALID_WIDTH(READ_WIDTH_B))
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(`INVALID_WIDTH(WRITE_WIDTH_A))
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(`INVALID_WIDTH_WIDE(WRITE_WIDTH_B))
_TECHMAP_FAIL_ <= GENERATE_ERROR;
`undef INVALID_WIDTH
`undef INVALID_WIDTH_WIDE
if(READ_WIDTH_A > 36 && RAM_MODE != "SDP") begin
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
if(WRITE_WIDTH_B > 36 && RAM_MODE != "SDP") begin
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
if(WRITE_MODE_A != "WRITE_FIRST" && WRITE_MODE_A != "NO_CHANGE" && WRITE_MODE_A != "READ_FIRST")
_TECHMAP_FAIL_ <= GENERATE_ERROR;
if(WRITE_MODE_B != "WRITE_FIRST" && WRITE_MODE_B != "NO_CHANGE" && WRITE_MODE_B != "READ_FIRST")
_TECHMAP_FAIL_ <= GENERATE_ERROR;
end
localparam EFF_READ_WIDTH_A = (RAM_MODE == "SDP" && READ_WIDTH_A > 36) ? 36 : READ_WIDTH_A;
localparam EFF_READ_WIDTH_B = (RAM_MODE == "SDP" && READ_WIDTH_A > 36) ? 36 : READ_WIDTH_B;
localparam EFF_WRITE_WIDTH_A = (RAM_MODE == "SDP" && WRITE_WIDTH_B > 36) ? 36 : WRITE_WIDTH_A;
localparam EFF_WRITE_WIDTH_B = (RAM_MODE == "SDP" && WRITE_WIDTH_B > 36) ? 36 : WRITE_WIDTH_B;
wire REGCLKA;
wire REGCLKB;
assign REGCLKA = DOA_REG ? CLKARDCLK : 1'b1;
localparam ZINV_REGCLKARDRCLK = (DOA_REG && !IS_CLKARDCLK_INVERTED);
assign REGCLKB = DOB_REG ? CLKBWRCLK : 1'b1;
localparam ZINV_REGCLKB = (DOB_REG && !IS_CLKBWRCLK_INVERTED);
wire [7:0] WEBWE_WIDE;
wire [3:0] WEA_WIDE;
wire [3:0] DIPADIP_MAPPED;
wire [3:0] DIPBDIP_MAPPED;
wire [31:0] DIADI_MAPPED;
wire [31:0] DIBDI_MAPPED;
if(WRITE_WIDTH_A == 1) begin
assign DIADI_MAPPED[31:2] = DIADI[31:2];
assign DIADI_MAPPED[1] = DIADI[0];
assign DIADI_MAPPED[0] = DIADI[0];
end else begin
assign DIADI_MAPPED = DIADI;
end
if(WRITE_WIDTH_B == 1) begin
assign DIBDI_MAPPED[31:2] = DIBDI[31:2];
assign DIBDI_MAPPED[1] = DIBDI[0];
assign DIBDI_MAPPED[0] = DIBDI[0];
end else begin
assign DIBDI_MAPPED = DIBDI;
end
if(WRITE_WIDTH_A < 18) begin
assign WEA_WIDE = {4{WEA[0]}};
assign DIPADIP_MAPPED[3:2] = DIPADIP[3:2];
assign DIPADIP_MAPPED[1] = DIPADIP[0];
assign DIPADIP_MAPPED[0] = DIPADIP[0];
end else if(WRITE_WIDTH_A == 18) begin
assign WEA_WIDE[3] = WEA[1];
assign WEA_WIDE[1] = WEA[1];
assign WEA_WIDE[2] = WEA[0];
assign WEA_WIDE[0] = WEA[0];
assign DIPADIP_MAPPED = DIPADIP;
end else if(WRITE_WIDTH_A == 36) begin
assign WEA_WIDE = WEA;
assign DIPADIP_MAPPED = DIPADIP;
end
if(WRITE_WIDTH_B < 18) begin
assign WEBWE_WIDE[7:4] = 4'b0;
assign WEBWE_WIDE[3:0] = {4{WEBWE[0]}};
assign DIPBDIP_MAPPED[3:2] = DIPBDIP[3:2];
assign DIPBDIP_MAPPED[1] = DIPBDIP[0];
assign DIPBDIP_MAPPED[0] = DIPBDIP[0];
end else if(WRITE_WIDTH_B == 18) begin
assign WEBWE_WIDE[7:4] = 4'b0;
assign WEBWE_WIDE[3] = WEBWE[1];
assign WEBWE_WIDE[1] = WEBWE[1];
assign WEBWE_WIDE[2] = WEBWE[0];
assign WEBWE_WIDE[0] = WEBWE[0];
assign DIPBDIP_MAPPED = DIPBDIP;
end else if(WRITE_WIDTH_B == 36) begin
assign WEBWE_WIDE = WEBWE;
assign DIPBDIP_MAPPED = DIPBDIP;
end else if(WRITE_WIDTH_B == 72) begin
assign WEA_WIDE = 4'b0;
assign WEBWE_WIDE = WEBWE;
assign DIPBDIP_MAPPED = DIPBDIP;
end
RAMB36E1_PRIM #(
.IN_USE(READ_WIDTH_A != 0 || READ_WIDTH_B != 0 || WRITE_WIDTH_A != 0 || WRITE_WIDTH_B != 0),
.ZINIT_A(INIT_A ^ {36{1'b1}}),
.ZINIT_B(INIT_B ^ {36{1'b1}}),
.ZSRVAL_A(SRVAL_A ^ {36{1'b1}}),
.ZSRVAL_B(SRVAL_B ^ {36{1'b1}}),
`define INIT_PARAM_BLOCK_L(pre, n, d, upper) \
.``pre``_``n``0(every_other_bit_256({``pre``_``d``1, ``pre``_``d``0}, upper)), \
.``pre``_``n``1(every_other_bit_256({``pre``_``d``3, ``pre``_``d``2}, upper)), \
.``pre``_``n``2(every_other_bit_256({``pre``_``d``5, ``pre``_``d``4}, upper)), \
.``pre``_``n``3(every_other_bit_256({``pre``_``d``7, ``pre``_``d``6}, upper)), \
.``pre``_``n``4(every_other_bit_256({``pre``_``d``9, ``pre``_``d``8}, upper)), \
.``pre``_``n``5(every_other_bit_256({``pre``_``d``B, ``pre``_``d``A}, upper)), \
.``pre``_``n``6(every_other_bit_256({``pre``_``d``D, ``pre``_``d``C}, upper)), \
.``pre``_``n``7(every_other_bit_256({``pre``_``d``F, ``pre``_``d``E}, upper))
`define INIT_PARAM_BLOCK_H(pre, n, d, upper) \
.``pre``_``n``8(every_other_bit_256({``pre``_``d``1, ``pre``_``d``0}, upper)), \
.``pre``_``n``9(every_other_bit_256({``pre``_``d``3, ``pre``_``d``2}, upper)), \
.``pre``_``n``A(every_other_bit_256({``pre``_``d``5, ``pre``_``d``4}, upper)), \
.``pre``_``n``B(every_other_bit_256({``pre``_``d``7, ``pre``_``d``6}, upper)), \
.``pre``_``n``C(every_other_bit_256({``pre``_``d``9, ``pre``_``d``8}, upper)), \
.``pre``_``n``D(every_other_bit_256({``pre``_``d``B, ``pre``_``d``A}, upper)), \
.``pre``_``n``E(every_other_bit_256({``pre``_``d``D, ``pre``_``d``C}, upper)), \
.``pre``_``n``F(every_other_bit_256({``pre``_``d``F, ``pre``_``d``E}, upper))
`define INIT_PARAM_BLOCK(pre, n, lo, hi, upper) \
`INIT_PARAM_BLOCK_L(pre, n, lo, upper), \
`INIT_PARAM_BLOCK_H(pre, n, hi, upper)
`INIT_PARAM_BLOCK_L(INITP, 0, 0, 0),
`INIT_PARAM_BLOCK_H(INITP, 0, 0, 1),
`INIT_PARAM_BLOCK(INIT, 0, 0, 1, 0),
`INIT_PARAM_BLOCK(INIT, 1, 2, 3, 0),
`INIT_PARAM_BLOCK(INIT, 2, 4, 5, 0),
`INIT_PARAM_BLOCK(INIT, 3, 6, 7, 0),
`INIT_PARAM_BLOCK(INIT, 4, 0, 1, 1),
`INIT_PARAM_BLOCK(INIT, 5, 2, 3, 1),
`INIT_PARAM_BLOCK(INIT, 6, 4, 5, 1),
`INIT_PARAM_BLOCK(INIT, 7, 6, 7, 1),
`undef INIT_PARAM_BLOCK_L
`undef INIT_PARAM_BLOCK_H
`undef INIT_PARAM_BLOCK
.ZINV_CLKARDCLK(!IS_CLKARDCLK_INVERTED ^ INV_CLKARDCLK),
.ZINV_CLKBWRCLK(!IS_CLKBWRCLK_INVERTED ^ INV_CLKBWRCLK),
.ZINV_ENARDEN(!IS_ENARDEN_INVERTED),
.ZINV_ENBWREN(!IS_ENBWREN_INVERTED),
.ZINV_RSTRAMARSTRAM(!IS_RSTRAMARSTRAM_INVERTED ^ INV_RSTRAMARSTRAM),
.ZINV_RSTRAMB(!IS_RSTRAMB_INVERTED ^ INV_RSTRAMB),
.ZINV_RSTREGARSTREG(!IS_RSTREGARSTREG_INVERTED ^ INV_RSTREGARSTREG),
.ZINV_RSTREGB(!IS_RSTREGB_INVERTED ^ INV_RSTREGB),
.ZINV_REGCLKARDRCLK(ZINV_REGCLKARDRCLK),
.ZINV_REGCLKB(ZINV_REGCLKB),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
`define WIDTH_PARAM(name) \
.``name``_1(EFF_``name`` == 2 || EFF_``name`` == 1 || EFF_``name`` == 0), \
.``name``_2(EFF_``name`` == 4), \
.``name``_4(EFF_``name`` == 9), \
.``name``_9(EFF_``name`` == 18), \
.``name``_18(EFF_``name`` == 36)
`WIDTH_PARAM(READ_WIDTH_A),
.SDP_READ_WIDTH_36(READ_WIDTH_A > 36),
`WIDTH_PARAM(READ_WIDTH_B),
`WIDTH_PARAM(WRITE_WIDTH_A),
`WIDTH_PARAM(WRITE_WIDTH_B),
`undef WIDTH_PARAM
.BRAM36_READ_WIDTH_A_1(EFF_READ_WIDTH_A == 1 || EFF_READ_WIDTH_A == 9),
.BRAM36_READ_WIDTH_B_1(EFF_READ_WIDTH_B == 1 || EFF_READ_WIDTH_B == 9),
.BRAM36_WRITE_WIDTH_A_1(EFF_WRITE_WIDTH_A == 1 || EFF_WRITE_WIDTH_A == 9),
.BRAM36_WRITE_WIDTH_B_1(EFF_WRITE_WIDTH_B == 1 || EFF_WRITE_WIDTH_B == 9),
.SDP_WRITE_WIDTH_36(WRITE_WIDTH_B > 36),
.WRITE_MODE_A_NO_CHANGE(WRITE_MODE_A == "NO_CHANGE" || (WRITE_MODE_A == "WRITE_FIRST" && RAM_MODE == "SDP")),
.WRITE_MODE_A_READ_FIRST(WRITE_MODE_A == "READ_FIRST"),
.WRITE_MODE_B_NO_CHANGE(WRITE_MODE_B == "NO_CHANGE" || (WRITE_MODE_B == "WRITE_FIRST" && RAM_MODE == "SDP")),
.WRITE_MODE_B_READ_FIRST(WRITE_MODE_B == "READ_FIRST"),
.RSTREG_PRIORITY_A_RSTREG(1'b1),
.RSTREG_PRIORITY_B_RSTREG(1'b1),
.RAM_EXTENSION_A_NONE_OR_UPPER(1'b1),
.RAM_EXTENSION_B_NONE_OR_UPPER(1'b1),
.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE(1'b1),
.ZALMOST_EMPTY_OFFSET(13'b1111111111111),
.ZALMOST_FULL_OFFSET(13'b1111111111111)
) _TECHMAP_REPLACE_ (
`define DUP(pre, in) .``pre``U(in), .``pre``L(in)
`DUP(CLKARDCLK, clkardclk),
`DUP(REGCLKARDRCLK, REGCLKA),
`DUP(CLKBWRCLK, clkbwrclk),
`DUP(REGCLKB, REGCLKB),
`DUP(ENARDEN, ENARDEN),
`DUP(ENBWREN, ENBWREN),
`DUP(REGCEAREGCE, REGCEAREGCE),
`DUP(REGCEB, REGCEB),
.RSTRAMARSTRAMU(rstramarstram),
.RSTRAMARSTRAMLRST(rstramarstram),
`DUP(RSTRAMB, rstramb),
`DUP(RSTREGARSTREG, rstregarstreg),
`DUP(RSTREGB, rstregb),
.ADDRARDADDRU(ADDRARDADDR),
.ADDRARDADDRL({1'b1, ADDRARDADDR}),
.ADDRBWRADDRU(ADDRBWRADDR),
.ADDRBWRADDRL({1'b1, ADDRBWRADDR}),
.DIADI(DIADI_MAPPED),
.DIBDI(DIBDI_MAPPED),
.DIPADIP(DIPADIP_MAPPED),
.DIPBDIP(DIPBDIP_MAPPED),
`DUP(WEA, WEA_WIDE),
`DUP(WEBWE, WEBWE_WIDE),
.DOADO(DOADO),
.DOBDO(DOBDO),
.DOPADOP(DOPADOP),
.DOPBDOP(DOPBDOP)
`undef DUP
);
endmodule |
module SRLC32E (
output Q,
output Q31,
input [4:0] A,
input CE, CLK, D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
// Duplicate bits of the init parameter to match the actual INIT data
// representation.
function [63:0] duplicate_bits;
input [31:0] bits;
integer i;
begin
for (i=0; i<32; i=i+1) begin
duplicate_bits[2*i+0] = bits[i];
duplicate_bits[2*i+1] = bits[i];
end
end
endfunction
localparam [63:0] INIT_VPR = duplicate_bits(INIT);
// Substitute
SRLC32E_VPR #
(
.INIT(INIT_VPR)
)
_TECHMAP_REPLACE_
(
.CLK(CLK),
.CE(CE),
.A(A),
.D(D),
.Q(Q),
.Q31(Q31)
);
endmodule |
module SRLC16E (
output Q, Q15,
input A0, A1, A2, A3,
input CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [ 0:0] IS_CLK_INVERTED = 1'b0;
// Duplicate bits of the init parameter to match the actual INIT data
// representation.
function [31:0] duplicate_bits;
input [15:0] bits;
integer i;
begin
for (i=0; i<15; i=i+1) begin
duplicate_bits[2*i+0] = bits[i];
duplicate_bits[2*i+1] = bits[i];
end
end
endfunction
localparam [31:0] INIT_VPR = duplicate_bits(INIT);
// Substitute
SRLC16E_VPR #
(
.INIT(INIT_VPR)
)
_TECHMAP_REPLACE_
(
.CLK(CLK),
.CE(CE),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.D(D),
.Q(Q),
.Q15(Q15)
);
endmodule |
module SRL16E (
output Q,
input A0, A1, A2, A3,
input CE, CLK, D
);
parameter [15:0] INIT = 16'h0000;
parameter [ 0:0] IS_CLK_INVERTED = 1'b0;
// Substitute with Q15 disconnected.
SRLC16E #
(
.INIT(INIT),
.IS_CLK_INVERTED(IS_CLK_INVERTED)
)
_TECHMAP_REPLACE_
(
.CLK(CLK),
.CE(CE),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.D(D),
.Q(Q),
.Q15()
);
endmodule |
module IBUF (
input I,
output O
);
parameter IOSTANDARD = "LVCMOS33";
parameter IBUF_LOW_PWR = 0; // TODO: Map this to fasm
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
IBUF_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_IN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SLEW_FAST(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "LVCMOS25") ||
(IOSTANDARD == "LVCMOS33") ||
(IOSTANDARD == "LVTTL") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVDS_25_LVTTL_SSTL135_SSTL15_TMDS_33_IN_ONLY(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "LVCMOS25") ||
(IOSTANDARD == "LVCMOS33") ||
(IOSTANDARD == "LVTTL") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS25_LVCMOS33_LVTTL_IN(
(IOSTANDARD == "LVCMOS25") ||
(IOSTANDARD == "LVCMOS33") ||
(IOSTANDARD == "LVTTL")
),
.SSTL135_SSTL15_IN(
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) _TECHMAP_REPLACE_ (
.I(I),
.O(O)
);
endmodule |
module OBUF (
input I,
output O
);
parameter IOSTANDARD = "LVCMOS33";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
OBUFT # (
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.DRIVE(DRIVE),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) _TECHMAP_REPLACE_ (
.I(I),
.T(1'b0),
.O(O)
);
endmodule |
module OBUFT (
input I,
input T,
output O
);
parameter IOSTANDARD = "LVCMOS33";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
parameter _TECHMAP_CONSTMSK_T_ = 1'bx;
parameter _TECHMAP_CONSTVAL_T_ = 1'bx;
wire t;
// When T=1'b0 Vivado routes it to const1 and enables an inverter in OLOGIC.
// To mimic this behavior insert a specialized inverter that will go to the
// OLOGIC site.
generate if (_TECHMAP_CONSTMSK_T_ == 1'b1 && _TECHMAP_CONSTVAL_T_ == 1'b0) begin
T_INV t_inv (
.TI (1'b1),
.TO (t)
);
end else begin
assign t = T;
end endgenerate
OBUFT_VPR # (
.LVCMOS12_DRIVE_I12(
(IOSTANDARD == "LVCMOS12" && DRIVE == 12)
),
.LVCMOS12_DRIVE_I4(
(IOSTANDARD == "LVCMOS12" && DRIVE == 4)
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SLEW_FAST(
(IOSTANDARD == "LVCMOS12" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS15" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS18" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS25" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS33" && SLEW == "FAST") ||
(IOSTANDARD == "LVTTL" && SLEW == "FAST")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "LVCMOS12" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS15" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS18" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS25" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS33" && SLEW == "SLOW") ||
(IOSTANDARD == "LVTTL" && SLEW == "SLOW") ||
(IOSTANDARD == "SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS12_LVCMOS25_DRIVE_I8(
(IOSTANDARD == "LVCMOS12" && DRIVE == 8) ||
(IOSTANDARD == "LVCMOS25" && DRIVE == 8)
),
.LVCMOS15_DRIVE_I12(
(IOSTANDARD == "LVCMOS15" && DRIVE == 12)
),
.LVCMOS15_DRIVE_I8(
(IOSTANDARD == "LVCMOS15" && DRIVE == 8)
),
.LVCMOS15_LVCMOS18_LVCMOS25_DRIVE_I4(
(IOSTANDARD == "LVCMOS15" && DRIVE == 4) ||
(IOSTANDARD == "LVCMOS18" && DRIVE == 4) ||
(IOSTANDARD == "LVCMOS25" && DRIVE == 4)
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "LVCMOS15" && DRIVE == 16) ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS18_DRIVE_I12_I8(
(IOSTANDARD == "LVCMOS18" && DRIVE == 12) ||
(IOSTANDARD == "LVCMOS18" && DRIVE == 8)
),
.LVCMOS18_DRIVE_I16(
(IOSTANDARD == "LVCMOS18" && DRIVE == 16)
),
.LVCMOS18_DRIVE_I24(
(IOSTANDARD == "LVCMOS18" && DRIVE == 24)
),
.LVCMOS25_DRIVE_I12(
(IOSTANDARD == "LVCMOS25" && DRIVE == 12)
),
.LVCMOS25_DRIVE_I16(
(IOSTANDARD == "LVCMOS25" && DRIVE == 16)
),
.LVCMOS33_DRIVE_I16(
(IOSTANDARD == "LVCMOS33" && DRIVE == 16)
),
.LVCMOS33_LVTTL_DRIVE_I12_I16(
(IOSTANDARD == "LVCMOS33" && DRIVE == 12) ||
(IOSTANDARD == "LVTTL" && DRIVE == 16)
),
.LVCMOS33_LVTTL_DRIVE_I12_I8(
(IOSTANDARD == "LVCMOS33" && DRIVE == 8) ||
(IOSTANDARD == "LVTTL" && DRIVE == 12) ||
(IOSTANDARD == "LVTTL" && DRIVE == 8)
),
.LVCMOS33_LVTTL_DRIVE_I4(
(IOSTANDARD == "LVCMOS33" && DRIVE == 4) ||
(IOSTANDARD == "LVTTL" && DRIVE == 4)
),
.LVTTL_DRIVE_I24(
(IOSTANDARD == "LVTTL" && DRIVE == 24)
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "SSTL135")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "SSTL15" && SLEW == "FAST")
),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.DRIVE(DRIVE),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) obuft (
.I(I),
.T(t),
.O(O)
);
endmodule |
module IOBUF (
input I,
input T,
output O,
inout IO
);
parameter IOSTANDARD = "LVCMOS33";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
parameter IBUF_LOW_PWR = 0; // TODO: Map this to fasm
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
IOBUF_VPR # (
.LVCMOS12_DRIVE_I12(
(IOSTANDARD == "LVCMOS12" && DRIVE == 12)
),
.LVCMOS12_DRIVE_I4(
(IOSTANDARD == "LVCMOS12" && DRIVE == 4)
),
.LVCMOS12_LVCMOS15_LVCMOS18_IN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SLEW_FAST(
(IOSTANDARD == "LVCMOS12" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS15" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS18" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS25" && SLEW == "FAST") ||
(IOSTANDARD == "LVCMOS33" && SLEW == "FAST") ||
(IOSTANDARD == "LVTTL" && SLEW == "FAST")
),
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "LVCMOS12" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS15" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS18" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS25" && SLEW == "SLOW") ||
(IOSTANDARD == "LVCMOS33" && SLEW == "SLOW") ||
(IOSTANDARD == "LVTTL" && SLEW == "SLOW") ||
(IOSTANDARD == "SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "LVCMOS12") ||
(IOSTANDARD == "LVCMOS15") ||
(IOSTANDARD == "LVCMOS18") ||
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS12_LVCMOS25_DRIVE_I8(
(IOSTANDARD == "LVCMOS12" && DRIVE == 8) ||
(IOSTANDARD == "LVCMOS25" && DRIVE == 8)
),
.LVCMOS15_DRIVE_I12(
(IOSTANDARD == "LVCMOS15" && DRIVE == 12)
),
.LVCMOS15_DRIVE_I8(
(IOSTANDARD == "LVCMOS15" && DRIVE == 8)
),
.LVCMOS15_LVCMOS18_LVCMOS25_DRIVE_I4(
(IOSTANDARD == "LVCMOS15" && DRIVE == 4) ||
(IOSTANDARD == "LVCMOS18" && DRIVE == 4) ||
(IOSTANDARD == "LVCMOS25" && DRIVE == 4)
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "LVCMOS15" && DRIVE == 16) ||
(IOSTANDARD == "SSTL15")
),
.LVCMOS18_DRIVE_I12_I8(
(IOSTANDARD == "LVCMOS18" && DRIVE == 12) ||
(IOSTANDARD == "LVCMOS18" && DRIVE == 8)
),
.LVCMOS18_DRIVE_I16(
(IOSTANDARD == "LVCMOS18" && DRIVE == 16)
),
.LVCMOS18_DRIVE_I24(
(IOSTANDARD == "LVCMOS18" && DRIVE == 24)
),
.LVCMOS25_DRIVE_I12(
(IOSTANDARD == "LVCMOS25" && DRIVE == 12)
),
.LVCMOS25_DRIVE_I16(
(IOSTANDARD == "LVCMOS25" && DRIVE == 16)
),
.LVCMOS25_LVCMOS33_LVTTL_IN(
(IOSTANDARD == "LVCMOS25") ||
(IOSTANDARD == "LVCMOS33") ||
(IOSTANDARD == "LVTTL")
),
.LVCMOS33_DRIVE_I16(
(IOSTANDARD == "LVCMOS33" && DRIVE == 16)
),
.LVCMOS33_LVTTL_DRIVE_I12_I16(
(IOSTANDARD == "LVCMOS33" && DRIVE == 12) ||
(IOSTANDARD == "LVTTL" && DRIVE == 16)
),
.LVCMOS33_LVTTL_DRIVE_I12_I8(
(IOSTANDARD == "LVCMOS33" && DRIVE == 8) ||
(IOSTANDARD == "LVTTL" && DRIVE == 12) ||
(IOSTANDARD == "LVTTL" && DRIVE == 8)
),
.LVCMOS33_LVTTL_DRIVE_I4(
(IOSTANDARD == "LVCMOS33" && DRIVE == 4) ||
(IOSTANDARD == "LVTTL" && DRIVE == 4)
),
.LVTTL_DRIVE_I24(
(IOSTANDARD == "LVTTL" && DRIVE == 24)
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "SSTL135")
),
.SSTL135_SSTL15_IN(
(IOSTANDARD == "SSTL135") ||
(IOSTANDARD == "SSTL15")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "SSTL15" && SLEW == "FAST")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.IBUF_LOW_PWR(IBUF_LOW_PWR),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.DRIVE(DRIVE),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) _TECHMAP_REPLACE_ (
.I(I),
.T(T),
.O(O),
.IOPAD_$inp(IO),
.IOPAD_$out(IO)
);
endmodule |
module OBUFTDS (
input I,
input T,
output O,
output OB
);
parameter IOSTANDARD = "DIFF_SSTL135"; // TODO: Is this the default ?
parameter SLEW = "FAST";
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
parameter HAS_OSERDES = 0; // Set inside yosys/synth.tcl
parameter _TECHMAP_CONSTMSK_T_ = 1'bx;
parameter _TECHMAP_CONSTVAL_T_ = 1'bx;
wire t;
// When T=1'b0 Vivado routes it to const1 and enables an inverter in OLOGIC.
// BUT, that happens only when there is an OSERDES with "TQ.BUF" mode.
//
// Presence of an OSERDES is detected in the sytnesis script and the parameter
// HAS_OSERDES is set.
generate if (_TECHMAP_CONSTMSK_T_ == 1'b1 && _TECHMAP_CONSTVAL_T_ == 1'b0 && HAS_OSERDES == 1) begin
T_INV t_inv (
.TI (1'b1),
.TO (t)
);
end else begin
assign t = T;
end endgenerate
wire complementary;
OBUFTDS_M_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15")
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "DIFF_SSTL15")
),
.LVDS_25_DRIVE_I_FIXED(
(IOSTANDARD == "LVDS_25")
),
.LVDS_25_OUT(
(IOSTANDARD == "LVDS_25")
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "DIFF_SSTL135")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "FAST")
),
.TMDS_33_DRIVE_I_FIXED(
(IOSTANDARD == "TMDS_33")
),
.TMDS_33_OUT(
(IOSTANDARD == "TMDS_33")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) obuftds_m (
.I(I),
.T(t),
.O(O),
.OB(complementary)
);
OBUFTDS_S_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15")
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "DIFF_SSTL15")
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "DIFF_SSTL135")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "FAST")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) obuftds_s (
.IB(complementary),
.OB(OB)
);
endmodule |
module OBUFDS (
input I,
output O,
output OB
);
parameter IOSTANDARD = "DIFF_SSTL135"; // TODO: Is this the default ?
parameter SLEW = "FAST";
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
parameter HAS_OSERDES = 0; // Set inside yosys/synth.tcl
OBUFTDS # (
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.HAS_OSERDES(HAS_OSERDES),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) _TECHMAP_REPLACE_ (
.I(I),
.T(1'b0),
.O(O),
.OB(OB)
);
endmodule |
module IOBUFDS (
input I,
input T,
output O,
inout IO,
inout IOB
);
parameter IOSTANDARD = "DIFF_SSTL135"; // TODO: Is this the default ?
parameter SLEW = "SLOW";
parameter IN_TERM = "NONE"; // Not supported by Vivado ?
parameter PULLTYPE = "NONE"; // Not supported by Vivado ?
parameter IO_LOC_PAIRS = "NONE";
wire complementary_o;
wire complementary_i;
IOBUFDS_M_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15")
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "DIFF_SSTL15")
),
.LVDS_25_DRIVE_I_FIXED(
(IOSTANDARD == "LVDS_25")
),
.LVDS_25_OUT(
(IOSTANDARD == "LVDS_25")
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "DIFF_SSTL135")
),
.LVDS_25_SSTL135_SSTL15_IN_DIFF(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15") ||
(IOSTANDARD == "LVDS_25")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "FAST")
),
.TMDS_33_IN_DIFF(
(IOSTANDARD == "TMDS_33")
),
.TMDS_33_DRIVE_I_FIXED(
(IOSTANDARD == "TMDS_33")
),
.TMDS_33_OUT(
(IOSTANDARD == "TMDS_33")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) iobufds_m (
.I(I),
.T(T),
.O(O),
.IOPAD_$inp(IO),
.IOPAD_$out(IO),
.IB(complementary_i),
.OB(complementary_o)
);
IOBUFDS_S_VPR # (
.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135_SSTL15_SLEW_SLOW(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "SLOW") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "SLOW")
),
.LVCMOS12_LVCMOS15_LVCMOS18_SSTL135_SSTL15_STEPDOWN(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15")
),
.LVCMOS15_SSTL15_DRIVE_I16_I_FIXED(
(IOSTANDARD == "DIFF_SSTL15")
),
.SSTL135_DRIVE_I_FIXED(
(IOSTANDARD == "DIFF_SSTL135")
),
.LVDS_25_SSTL135_SSTL15_IN_DIFF(
(IOSTANDARD == "DIFF_SSTL135") ||
(IOSTANDARD == "DIFF_SSTL15") ||
(IOSTANDARD == "LVDS_25")
),
.SSTL135_SSTL15_SLEW_FAST(
(IOSTANDARD == "DIFF_SSTL135" && SLEW == "FAST") ||
(IOSTANDARD == "DIFF_SSTL15" && SLEW == "FAST")
),
.IN_TERM_UNTUNED_SPLIT_40 (IN_TERM == "UNTUNED_SPLIT_40"),
.IN_TERM_UNTUNED_SPLIT_50 (IN_TERM == "UNTUNED_SPLIT_50"),
.IN_TERM_UNTUNED_SPLIT_60 (IN_TERM == "UNTUNED_SPLIT_60"),
.PULLTYPE_PULLUP(PULLTYPE == "PULLUP"),
.PULLTYPE_PULLDOWN(PULLTYPE == "PULLDOWN"),
.PULLTYPE_NONE(PULLTYPE == "NONE"),
.PULLTYPE_KEEPER(PULLTYPE == "KEEPER"),
.PULLTYPE(PULLTYPE),
.IOSTANDARD(IOSTANDARD),
.SLEW(SLEW),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) iobufds_s (
.IB(complementary_o),
.OB(complementary_i),
.IOPAD_$inp(IOB),
.IOPAD_$out(IOB)
);
endmodule |
module OSERDESE2 (
input CLK,
input CLKDIV,
input D1,
input D2,
input D3,
input D4,
input D5,
input D6,
input D7,
input D8,
input OCE,
input RST,
input T1,
input T2,
input T3,
input T4,
input TCE,
output OFB,
output OQ,
output TFB,
output TQ
);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter DATA_WIDTH = 4;
parameter SERDES_MODE = "MASTER";
parameter TRISTATE_WIDTH = 4;
parameter IO_LOC_PAIRS = "NONE";
if (DATA_RATE_OQ == "DDR" &&
!(DATA_WIDTH == 4 || DATA_WIDTH == 6 || DATA_WIDTH == 8)) begin
wire _TECHMAP_FAIL_;
end
if (DATA_RATE_OQ == "SDR" &&
!(DATA_WIDTH >= 2 || DATA_WIDTH <= 8)) begin
wire _TECHMAP_FAIL_;
end
if ((DATA_RATE_TQ == "SDR" || DATA_RATE_TQ == "BUF") &&
TRISTATE_WIDTH != 1) begin
wire _TECHMAP_FAIL_;
end
if (DATA_RATE_OQ == "SDR" && DATA_RATE_TQ == "DDR") begin
wire _TECHMAP_FAIL_;
end
if (TRISTATE_WIDTH != 1 && TRISTATE_WIDTH != 4) begin
wire _TECHMAP_FAIL_;
end
// Inverter parameters
parameter [0:0] IS_D1_INVERTED = 1'b0;
parameter [0:0] IS_D2_INVERTED = 1'b0;
parameter [0:0] IS_D3_INVERTED = 1'b0;
parameter [0:0] IS_D4_INVERTED = 1'b0;
parameter [0:0] IS_D5_INVERTED = 1'b0;
parameter [0:0] IS_D6_INVERTED = 1'b0;
parameter [0:0] IS_D7_INVERTED = 1'b0;
parameter [0:0] IS_D8_INVERTED = 1'b0;
parameter [0:0] IS_CLKDIV_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
parameter [0:0] IS_T1_INVERTED = 1'b0;
parameter [0:0] IS_T2_INVERTED = 1'b0;
parameter [0:0] IS_T3_INVERTED = 1'b0;
parameter [0:0] IS_T4_INVERTED = 1'b0;
localparam [0:0] INIT_OQ = 1'b0;
localparam [0:0] INIT_TQ = 1'b0;
localparam [0:0] SRVAL_OQ = 1'b0;
localparam [0:0] SRVAL_TQ = 1'b0;
parameter _TECHMAP_CONSTMSK_D1_ = 0;
parameter _TECHMAP_CONSTVAL_D1_ = 0;
parameter _TECHMAP_CONSTMSK_D2_ = 0;
parameter _TECHMAP_CONSTVAL_D2_ = 0;
parameter _TECHMAP_CONSTMSK_D3_ = 0;
parameter _TECHMAP_CONSTVAL_D3_ = 0;
parameter _TECHMAP_CONSTMSK_D4_ = 0;
parameter _TECHMAP_CONSTVAL_D4_ = 0;
parameter _TECHMAP_CONSTMSK_D5_ = 0;
parameter _TECHMAP_CONSTVAL_D5_ = 0;
parameter _TECHMAP_CONSTMSK_D6_ = 0;
parameter _TECHMAP_CONSTVAL_D6_ = 0;
parameter _TECHMAP_CONSTMSK_D7_ = 0;
parameter _TECHMAP_CONSTVAL_D7_ = 0;
parameter _TECHMAP_CONSTMSK_D8_ = 0;
parameter _TECHMAP_CONSTVAL_D8_ = 0;
parameter _TECHMAP_CONSTMSK_TQ_ = 1'bx;
parameter _TECHMAP_CONSTVAL_TQ_ = 1'bx;
localparam INV_D1 = (_TECHMAP_CONSTMSK_D1_ == 1) ? !_TECHMAP_CONSTVAL_D1_ ^ IS_D1_INVERTED :
(_TECHMAP_CONSTVAL_D1_ === 0) ? ~IS_D1_INVERTED : IS_D1_INVERTED;
wire d1 = (_TECHMAP_CONSTMSK_D1_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D1_ === 0) ? 1'b1 : D1;
localparam INV_D2 = (_TECHMAP_CONSTMSK_D2_ == 1) ? !_TECHMAP_CONSTVAL_D2_ ^ IS_D2_INVERTED :
(_TECHMAP_CONSTVAL_D2_ === 0) ? ~IS_D2_INVERTED : IS_D2_INVERTED;
wire d2 = (_TECHMAP_CONSTMSK_D2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D2_ === 0) ? 1'b1 : D2;
localparam INV_D3 = (_TECHMAP_CONSTMSK_D3_ == 1) ? !_TECHMAP_CONSTVAL_D3_ ^ IS_D3_INVERTED :
(_TECHMAP_CONSTVAL_D3_ === 0) ? ~IS_D3_INVERTED : IS_D3_INVERTED;
wire d3 = (_TECHMAP_CONSTMSK_D3_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D3_ === 0) ? 1'b1 : D3;
localparam INV_D4 = (_TECHMAP_CONSTMSK_D4_ == 1) ? !_TECHMAP_CONSTVAL_D4_ ^ IS_D4_INVERTED :
(_TECHMAP_CONSTVAL_D4_ === 0) ? ~IS_D4_INVERTED : IS_D4_INVERTED;
wire d4 = (_TECHMAP_CONSTMSK_D4_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D4_ === 0) ? 1'b1 : D4;
localparam INV_D5 = (_TECHMAP_CONSTMSK_D5_ == 1) ? !_TECHMAP_CONSTVAL_D5_ ^ IS_D5_INVERTED :
(_TECHMAP_CONSTVAL_D5_ === 0) ? ~IS_D5_INVERTED : IS_D5_INVERTED;
wire d5 = (_TECHMAP_CONSTMSK_D5_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D5_ === 0) ? 1'b1 : D5;
localparam INV_D6 = (_TECHMAP_CONSTMSK_D6_ == 1) ? !_TECHMAP_CONSTVAL_D6_ ^ IS_D6_INVERTED :
(_TECHMAP_CONSTVAL_D6_ === 0) ? ~IS_D6_INVERTED : IS_D6_INVERTED;
wire d6 = (_TECHMAP_CONSTMSK_D6_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D6_ === 0) ? 1'b1 : D6;
localparam INV_D7 = (_TECHMAP_CONSTMSK_D7_ == 1) ? !_TECHMAP_CONSTVAL_D7_ ^ IS_D7_INVERTED :
(_TECHMAP_CONSTVAL_D7_ === 0) ? ~IS_D7_INVERTED : IS_D7_INVERTED;
wire d7 = (_TECHMAP_CONSTMSK_D7_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D7_ === 0) ? 1'b1 : D7;
localparam INV_D8 = (_TECHMAP_CONSTMSK_D8_ == 1) ? !_TECHMAP_CONSTVAL_D8_ ^ IS_D8_INVERTED :
(_TECHMAP_CONSTVAL_D8_ === 0) ? ~IS_D8_INVERTED : IS_D8_INVERTED;
wire d8 = (_TECHMAP_CONSTMSK_D8_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D8_ === 0) ? 1'b1 : D8;
localparam TQ_USED = (_TECHMAP_CONSTVAL_TQ_ === 1'bx && (DATA_RATE_TQ == "DDR" || DATA_RATE_TQ == "SDR")) ? 1'b1 : 1'b0;
parameter _TECHMAP_CONSTMSK_T1_ = 0;
parameter _TECHMAP_CONSTVAL_T1_ = 0;
parameter _TECHMAP_CONSTMSK_T2_ = 0;
parameter _TECHMAP_CONSTVAL_T2_ = 0;
parameter _TECHMAP_CONSTMSK_T3_ = 0;
parameter _TECHMAP_CONSTVAL_T3_ = 0;
parameter _TECHMAP_CONSTMSK_T4_ = 0;
parameter _TECHMAP_CONSTVAL_T4_ = 0;
localparam INV_T1 = (_TECHMAP_CONSTMSK_T1_ == 1) ? !_TECHMAP_CONSTVAL_T1_ ^ IS_T1_INVERTED :
(_TECHMAP_CONSTVAL_T1_ === 0) ? ~IS_T1_INVERTED : IS_T1_INVERTED;
wire t1 = (_TECHMAP_CONSTMSK_T1_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_T1_ === 0) ? 1'b1 : T1;
localparam INV_T2 = (_TECHMAP_CONSTMSK_T2_ == 1) ? !_TECHMAP_CONSTVAL_T2_ ^ IS_T2_INVERTED :
(_TECHMAP_CONSTVAL_T2_ === 0) ? ~IS_T2_INVERTED : IS_T2_INVERTED;
wire t2 = (_TECHMAP_CONSTMSK_T2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_T2_ === 0) ? 1'b1 : T2;
localparam INV_T3 = (_TECHMAP_CONSTMSK_T3_ == 1) ? !_TECHMAP_CONSTVAL_T3_ ^ IS_T3_INVERTED :
(_TECHMAP_CONSTVAL_T3_ === 0) ? ~IS_T3_INVERTED : IS_T3_INVERTED;
wire t3 = (_TECHMAP_CONSTMSK_T3_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_T3_ === 0) ? 1'b1 : T3;
localparam INV_T4 = (_TECHMAP_CONSTMSK_T4_ == 1) ? !_TECHMAP_CONSTVAL_T4_ ^ IS_T4_INVERTED :
(_TECHMAP_CONSTVAL_T4_ === 0) ? ~IS_T4_INVERTED : IS_T4_INVERTED;
wire t4 = (_TECHMAP_CONSTMSK_T4_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_T4_ === 0) ? 1'b1 : T4;
OSERDESE2_VPR #(
.SERDES_MODE_SLAVE (SERDES_MODE == "SLAVE"),
.TRISTATE_WIDTH_W4 (TRISTATE_WIDTH == 4),
.DATA_RATE_OQ_DDR (DATA_RATE_OQ == "DDR"),
.DATA_RATE_OQ_SDR (DATA_RATE_OQ == "SDR"),
.DATA_RATE_TQ_BUF (DATA_RATE_TQ == "BUF"),
.DATA_RATE_TQ_DDR (DATA_RATE_TQ == "DDR"),
.DATA_RATE_TQ_SDR (DATA_RATE_TQ == "SDR"),
.DATA_WIDTH_DDR_W4 (DATA_RATE_OQ == "DDR" && DATA_WIDTH == 4),
.DATA_WIDTH_DDR_W6 (DATA_RATE_OQ == "DDR" && DATA_WIDTH == 6),
.DATA_WIDTH_DDR_W8 (DATA_RATE_OQ == "DDR" && DATA_WIDTH == 8),
.DATA_WIDTH_SDR_W2 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 2),
.DATA_WIDTH_SDR_W3 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 3),
.DATA_WIDTH_SDR_W4 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 4),
.DATA_WIDTH_SDR_W5 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 5),
.DATA_WIDTH_SDR_W6 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 6),
.DATA_WIDTH_SDR_W7 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 7),
.DATA_WIDTH_SDR_W8 (DATA_RATE_OQ == "SDR" && DATA_WIDTH == 8),
.ZINIT_OQ (!INIT_OQ),
.ZINIT_TQ (!INIT_TQ),
.ZSRVAL_OQ (!SRVAL_OQ),
.ZSRVAL_TQ (!SRVAL_TQ),
.IS_CLKDIV_INVERTED (IS_CLKDIV_INVERTED),
.IS_D1_INVERTED (INV_D1),
.IS_D2_INVERTED (INV_D2),
.IS_D3_INVERTED (INV_D3),
.IS_D4_INVERTED (INV_D4),
.IS_D5_INVERTED (INV_D5),
.IS_D6_INVERTED (INV_D6),
.IS_D7_INVERTED (INV_D7),
.IS_D8_INVERTED (INV_D8),
.ZINV_CLK (!IS_CLK_INVERTED),
.ZINV_T1 (!INV_T1),
.ZINV_T2 (!INV_T2),
.ZINV_T3 (!INV_T3),
.ZINV_T4 (!INV_T4),
.TQ_USED (TQ_USED)
) _TECHMAP_REPLACE_ (
.CLK (CLK),
.CLKDIV (CLKDIV),
.D1 (d1),
.D2 (d2),
.D3 (d3),
.D4 (d4),
.D5 (d5),
.D6 (d6),
.D7 (d7),
.D8 (d8),
.OCE (OCE),
.RST (RST),
.T1 (t1),
.T2 (t2),
.T3 (t3),
.T4 (t4),
.TCE (TCE),
.OFB (OFB),
.OQ (OQ),
.TFB (TFB),
.TQ (TQ)
);
endmodule |
module ISERDESE2 (
input BITSLIP,
input CE1,
input CE2,
input CLK,
input CLKB,
input CLKDIV,
input RST,
input D,
input DDLY,
output Q1,
output Q2,
output Q3,
output Q4,
output Q5,
output Q6,
output Q7,
output Q8
);
parameter DATA_RATE = "DDR";
parameter DATA_WIDTH = 4;
parameter NUM_CE = 2;
parameter DYN_CLKDIV_INV_EN = "FALSE";
parameter DYN_CLK_INV_EN = "FALSE";
parameter INTERFACE_TYPE = "MEMORY";
parameter IOBDELAY = "NONE";
parameter SERDES_MODE = "MASTER";
parameter [0:0] INIT_Q1 = 1'b0;
parameter [0:0] INIT_Q2 = 1'b0;
parameter [0:0] INIT_Q3 = 1'b0;
parameter [0:0] INIT_Q4 = 1'b0;
parameter [0:0] SRVAL_Q1 = 1'b0;
parameter [0:0] SRVAL_Q2 = 1'b0;
parameter [0:0] SRVAL_Q3 = 1'b0;
parameter [0:0] SRVAL_Q4 = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
if (INTERFACE_TYPE == "NETWORKING") begin
if (DATA_RATE == "DDR" &&
(DATA_WIDTH != 4 &&
DATA_WIDTH != 6 &&
DATA_WIDTH != 8)) begin
wire _TECHMAP_FAIL_;
end
if (DATA_RATE == "SDR" &&
(DATA_WIDTH < 2 ||
DATA_WIDTH > 8)) begin
wire _TECHMAP_FAIL_;
end
end
if (INTERFACE_TYPE == "MEMORY" ||
INTERFACE_TYPE == "MEMORY_DDR3" ||
INTERFACE_TYPE == "MEMORY_QDR") begin
if (DATA_RATE == "SDR") begin
wire _TECHMAP_FAIL_;
end
if (DATA_RATE == "DDR" &&
(DATA_WIDTH != 4 &&
DATA_WIDTH != 6 &&
DATA_WIDTH != 8)) begin
wire _TECHMAP_FAIL_;
end
end
if (NUM_CE != 1 && NUM_CE != 2) begin
wire _TECHMAP_FAIL_ = 1'b1;
end
parameter _TECHMAP_CONSTMSK_D_ = 1'b1;
parameter _TECHMAP_CONSTVAL_D_ = 1'bx;
parameter _TECHMAP_CONSTMSK_DDLY_ = 1'b1;
parameter _TECHMAP_CONSTVAL_DDLY_ = 1'bx;
localparam [0:0] MEMORY_DDR3_4 = (INTERFACE_TYPE == "MEMORY_DDR3" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
localparam [0:0] MEMORY_DDR_4 = (INTERFACE_TYPE == "MEMORY" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
localparam [0:0] MEMORY_QDR_4 = (INTERFACE_TYPE == "MEMORY_QDR" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
localparam [0:0] NETWORKING_SDR_2 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 2);
localparam [0:0] NETWORKING_SDR_3 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 3);
localparam [0:0] NETWORKING_SDR_4 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 4);
localparam [0:0] NETWORKING_SDR_5 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 5);
localparam [0:0] NETWORKING_SDR_6 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 6);
localparam [0:0] NETWORKING_SDR_7 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 7);
localparam [0:0] NETWORKING_SDR_8 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "SDR" && DATA_WIDTH == 8);
localparam [0:0] NETWORKING_DDR_4 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
localparam [0:0] NETWORKING_DDR_6 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 6);
localparam [0:0] NETWORKING_DDR_8 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 8);
localparam [0:0] NETWORKING_DDR_10 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 10);
localparam [0:0] NETWORKING_DDR_14 = (INTERFACE_TYPE == "NETWORKING" && DATA_RATE == "DDR" && DATA_WIDTH == 14);
localparam [0:0] OVERSAMPLE_DDR_4 = (INTERFACE_TYPE == "OVERSAMPLE" && DATA_RATE == "DDR" && DATA_WIDTH == 4);
if (_TECHMAP_CONSTMSK_D_ == 1'b1) begin
ISERDESE2_IDELAY_VPR #(
.MEMORY_DDR3_4 (MEMORY_DDR3_4),
.MEMORY_DDR_4 (MEMORY_DDR_4),
.MEMORY_QDR_4 (MEMORY_QDR_4),
.NETWORKING_SDR_2 (NETWORKING_SDR_2),
.NETWORKING_SDR_3 (NETWORKING_SDR_3),
.NETWORKING_SDR_4 (NETWORKING_SDR_4),
.NETWORKING_SDR_5 (NETWORKING_SDR_5),
.NETWORKING_SDR_6 (NETWORKING_SDR_6),
.NETWORKING_SDR_7 (NETWORKING_SDR_7),
.NETWORKING_SDR_8 (NETWORKING_SDR_8),
.NETWORKING_DDR_4 (NETWORKING_DDR_4),
.NETWORKING_DDR_6 (NETWORKING_DDR_6),
.NETWORKING_DDR_8 (NETWORKING_DDR_8),
.NETWORKING_DDR_10 (NETWORKING_DDR_10),
.NETWORKING_DDR_14 (NETWORKING_DDR_14),
.OVERSAMPLE_DDR_4 (OVERSAMPLE_DDR_4),
.NUM_CE_N1 (NUM_CE == 1),
.NUM_CE_N2 (NUM_CE == 2),
.IOBDELAY_IFD (IOBDELAY == "IFD" || IOBDELAY == "BOTH"),
.IOBDELAY_IBUF (IOBDELAY == "IBUF" || IOBDELAY == "BOTH"),
// Inverters
.ZINIT_Q1 (!INIT_Q1),
.ZINIT_Q2 (!INIT_Q2),
.ZINIT_Q3 (!INIT_Q3),
.ZINIT_Q4 (!INIT_Q4),
.ZSRVAL_Q1 (!SRVAL_Q1),
.ZSRVAL_Q2 (!SRVAL_Q2),
.ZSRVAL_Q3 (!SRVAL_Q3),
.ZSRVAL_Q4 (!SRVAL_Q4),
.ZINV_C (!IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.BITSLIP (BITSLIP),
.CE1 (CE1),
.CE2 (CE2),
.CLK (CLK),
.CLKB (CLKB),
.CLKDIV (CLKDIV),
.RST (RST),
.DDLY (DDLY),
.Q1 (Q1),
.Q2 (Q2),
.Q3 (Q3),
.Q4 (Q4),
.Q5 (Q5),
.Q6 (Q6),
.Q7 (Q7),
.Q8 (Q8)
);
end else if (_TECHMAP_CONSTMSK_DDLY_ == 1'b1) begin
ISERDESE2_NO_IDELAY_VPR #(
.MEMORY_DDR3_4 (MEMORY_DDR3_4),
.MEMORY_DDR_4 (MEMORY_DDR_4),
.MEMORY_QDR_4 (MEMORY_QDR_4),
.NETWORKING_SDR_2 (NETWORKING_SDR_2),
.NETWORKING_SDR_3 (NETWORKING_SDR_3),
.NETWORKING_SDR_4 (NETWORKING_SDR_4),
.NETWORKING_SDR_5 (NETWORKING_SDR_5),
.NETWORKING_SDR_6 (NETWORKING_SDR_6),
.NETWORKING_SDR_7 (NETWORKING_SDR_7),
.NETWORKING_SDR_8 (NETWORKING_SDR_8),
.NETWORKING_DDR_4 (NETWORKING_DDR_4),
.NETWORKING_DDR_6 (NETWORKING_DDR_6),
.NETWORKING_DDR_8 (NETWORKING_DDR_8),
.NETWORKING_DDR_10 (NETWORKING_DDR_10),
.NETWORKING_DDR_14 (NETWORKING_DDR_14),
.OVERSAMPLE_DDR_4 (OVERSAMPLE_DDR_4),
.NUM_CE_N1 (NUM_CE == 1),
.NUM_CE_N2 (NUM_CE == 2),
.IOBDELAY_IFD (IOBDELAY == "IFD" || IOBDELAY == "BOTH"),
.IOBDELAY_IBUF (IOBDELAY == "IBUF" || IOBDELAY == "BOTH"),
// Inverters
.ZINIT_Q1 (!INIT_Q1),
.ZINIT_Q2 (!INIT_Q2),
.ZINIT_Q3 (!INIT_Q3),
.ZINIT_Q4 (!INIT_Q4),
.ZSRVAL_Q1 (!SRVAL_Q1),
.ZSRVAL_Q2 (!SRVAL_Q2),
.ZSRVAL_Q3 (!SRVAL_Q3),
.ZSRVAL_Q4 (!SRVAL_Q4),
.ZINV_D (!IS_D_INVERTED),
.ZINV_C (!IS_CLK_INVERTED)
) _TECHMAP_REPLACE_ (
.BITSLIP (BITSLIP),
.CE1 (CE1),
.CE2 (CE2),
.CLK (CLK),
.CLKB (CLKB),
.CLKDIV (CLKDIV),
.RST (RST),
.D (D),
.Q1 (Q1),
.Q2 (Q2),
.Q3 (Q3),
.Q4 (Q4),
.Q5 (Q5),
.Q6 (Q6),
.Q7 (Q7),
.Q8 (Q8)
);
end else begin
wire _TECHMAP_FAIL_;
end
endmodule |
module IDDR_2CLK (
output Q1,
output Q2,
input C,
input CB,
input CE,
input D,
input R,
input S,
);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_CB_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
parameter _TECHMAP_CONSTMSK_R_ = 1'b1;
parameter _TECHMAP_CONSTVAL_R_ = 1'bx;
parameter _TECHMAP_CONSTMSK_S_ = 1'b1;
parameter _TECHMAP_CONSTVAL_S_ = 1'bx;
localparam [0:0] R_USED = (_TECHMAP_CONSTMSK_R_ != 1'b1);
localparam [0:0] S_USED = (_TECHMAP_CONSTMSK_S_ != 1'b1);
wire SR;
localparam SRVAL = (!R_USED) ? 1'b1 : 1'b0;
localparam SRUSED = 1'b1;
generate if (!R_USED && !S_USED) begin
assign SR = 1'b0;
end else if (R_USED && !S_USED) begin
assign SR = R;
end else if (!R_USED && S_USED) begin
assign SR = S;
end else begin
assign SR = 1'bx;
$error("Both S and R cannot be used simultaneously");
end endgenerate
localparam INIT_Q3 = (DDR_CLK_EDGE != "OPPOSITE_EDGE") ? INIT_Q1 : 1'b1;
localparam INIT_Q4 = (DDR_CLK_EDGE != "OPPOSITE_EDGE") ? INIT_Q2 : 1'b1;
localparam SRVAL34 = (DDR_CLK_EDGE != "OPPOSITE_EDGE") ? SRVAL : 1'b1;
IDDR_VPR #(
.ZINV_D (!IS_D_INVERTED),
.ZINV_C (!IS_C_INVERTED),
.SRTYPE_SYNC (SRTYPE == "SYNC"),
.SAME_EDGE (DDR_CLK_EDGE == "SAME_EDGE"),
.OPPOSITE_EDGE (DDR_CLK_EDGE == "OPPOSITE_EDGE"),
.ZINIT_Q1 (!INIT_Q1),
.ZINIT_Q2 (!INIT_Q2),
.ZINIT_Q3 (!INIT_Q3),
.ZINIT_Q4 (!INIT_Q4),
.ZSRVAL_Q12 (!SRVAL),
.ZSRVAL_Q34 (!SRVAL34)
) _TECHMAP_REPLACE_ (
.CK (C),
.CKB (CB),
.CE (CE),
.SR (SR),
.D (D),
.Q1 (Q1),
.Q2 (Q2)
);
endmodule |
module IDDR (
output Q1,
output Q2,
input C,
input CE,
input D,
input R,
input S,
);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT_Q1 = 1'b0;
parameter INIT_Q2 = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
IDDR_2CLK # (
.DDR_CLK_EDGE (DDR_CLK_EDGE),
.SRTYPE (SRTYPE),
.INIT_Q1 (INIT_Q1),
.INIT_Q2 (INIT_Q2),
.IS_C_INVERTED (IS_C_INVERTED),
.IS_CB_INVERTED (!IS_C_INVERTED),
.IS_D_INVERTED (IS_D_INVERTED)
) _TECHMAP_REPLACE_ (
.C (C),
.CB (C),
.CE (CE),
.S (S),
.R (R),
.D (D),
.Q1 (Q1),
.Q2 (Q2)
);
endmodule |
module ODDR (
input C,
input CE,
input R,
input S,
input D1,
input D2,
output Q
);
parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
parameter INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D1_INVERTED = 1'b0;
parameter [0:0] IS_D2_INVERTED = 1'b0;
parameter SRTYPE = "SYNC";
parameter _TECHMAP_CONSTMSK_R_ = 1'b1;
parameter _TECHMAP_CONSTVAL_R_ = 1'bx;
parameter _TECHMAP_CONSTMSK_S_ = 1'b1;
parameter _TECHMAP_CONSTVAL_S_ = 1'bx;
localparam [0:0] R_USED = (_TECHMAP_CONSTMSK_R_ != 1'b1);
localparam [0:0] S_USED = (_TECHMAP_CONSTMSK_S_ != 1'b1);
wire SR;
localparam SRVAL = (!R_USED) ? 1'b1 : 1'b0;
generate if (!R_USED && !S_USED) begin
assign SR = 1'b0;
end else if (R_USED && !S_USED) begin
assign SR = R;
end else if (!R_USED && S_USED) begin
assign SR = S;
end else begin
assign SR = 1'bx;
$error("Both S and R cannot be used simultaneously");
end endgenerate
parameter _TECHMAP_CONSTMSK_D1_ = 0;
parameter _TECHMAP_CONSTVAL_D1_ = 0;
parameter _TECHMAP_CONSTMSK_D2_ = 0;
parameter _TECHMAP_CONSTVAL_D2_ = 0;
localparam INV_D1 = (_TECHMAP_CONSTMSK_D1_ == 1) ? !_TECHMAP_CONSTVAL_D1_ ^ IS_D1_INVERTED :
(_TECHMAP_CONSTVAL_D1_ === 0) ? IS_D1_INVERTED : !IS_D1_INVERTED;
wire d1 = (_TECHMAP_CONSTMSK_D1_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D1_ === 0) ? 1'b1 : D1;
localparam INV_D2 = (_TECHMAP_CONSTMSK_D2_ == 1) ? !_TECHMAP_CONSTVAL_D2_ ^ IS_D2_INVERTED :
(_TECHMAP_CONSTVAL_D2_ === 0) ? IS_D2_INVERTED : !IS_D2_INVERTED;
wire d2 = (_TECHMAP_CONSTMSK_D2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_D2_ === 0) ? 1'b1 : D2;
ODDR_VPR # (
.ZINV_CLK (!IS_C_INVERTED),
.INV_D1 (INV_D1),
.INV_D2 (INV_D2),
.ZINV_D1 (!INV_D1),
.ZINV_D2 (!INV_D2),
.SRTYPE_SYNC ( SRTYPE == "SYNC"),
.SAME_EDGE ( (DDR_CLK_EDGE != "OPPOSITE_EDGE") ^ IS_C_INVERTED),
.ZINIT_Q (!INIT),
.ZSRVAL_Q (!SRVAL)
) _TECHMAP_REPLACE_ (
.CK (C),
.CE (CE),
.SR (SR),
.D1 (d1),
.D2 (d2),
.Q (Q)
);
endmodule |
module IDELAYE2 (
input C,
input CE,
input CINVCTRL,
input CNTVALUEIN0,
input CNTVALUEIN1,
input CNTVALUEIN2,
input CNTVALUEIN3,
input CNTVALUEIN4,
input DATAIN,
input IDATAIN,
input INC,
input LD,
input LDPIPEEN,
input REGRST,
output CNTVALUEOUT0,
output CNTVALUEOUT1,
output CNTVALUEOUT2,
output CNTVALUEOUT3,
output CNTVALUEOUT4,
output DATAOUT
);
parameter CINVCTRL_SEL = "FALSE";
parameter DELAY_SRC = "IDATAIN";
parameter HIGH_PERFORMANCE_MODE = "FALSE";
parameter IDELAY_TYPE = "FIXED";
parameter PIPE_SEL = "FALSE";
parameter REFCLK_FREQUENCY = 200.0;
parameter SIGNAL_PATTERN = "DATA";
parameter [4:0] IDELAY_VALUE = 5'b00000;
parameter [0:0] IS_DATAIN_INVERTED = 1'b0;
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0;
localparam [4:0] ZIDELAY_VALUE = ~IDELAY_VALUE;
localparam [0:0] NOT_USING_CNTVALUEIN = (IDELAY_TYPE == "FIXED" || IDELAY_TYPE == "VARIABLE");
parameter _TECHMAP_CONSTMSK_IDATAIN_ = 1'b1;
parameter _TECHMAP_CONSTVAL_IDATAIN_ = 1'bx;
parameter _TECHMAP_CONSTMSK_DATAIN_ = 1'b1;
parameter _TECHMAP_CONSTVAL_DATAIN_ = 1'bx;
localparam [0:0] IDATAIN_USED = _TECHMAP_CONSTMSK_IDATAIN_ == 1'b0;
localparam [0:0] DATAIN_USED = _TECHMAP_CONSTMSK_DATAIN_ == 1'b0;
IDELAYE2_VPR #(
.IN_USE (IDATAIN_USED | DATAIN_USED),
.IDELAY_VALUE (IDELAY_VALUE),
.ZIDELAY_VALUE (ZIDELAY_VALUE),
.PIPE_SEL (PIPE_SEL == "TRUE"),
.CINVCTRL_SEL (CINVCTRL_SEL == "TRUE"),
.DELAY_SRC_DATAIN (DELAY_SRC == "DATAIN"),
.DELAY_SRC_IDATAIN (DELAY_SRC == "IDATAIN"),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE == "TRUE"),
.IDELAY_TYPE_FIXED (IDELAY_TYPE == "FIXED"),
.IDELAY_TYPE_VAR_LOAD (IDELAY_TYPE == "VAR_LOAD"),
.IDELAY_TYPE_VARIABLE (IDELAY_TYPE == "VARIABLE"),
// Inverters
.IS_DATAIN_INVERTED (IS_DATAIN_INVERTED),
.IS_IDATAIN_INVERTED (IS_IDATAIN_INVERTED)
) _TECHMAP_REPLACE_ (
.C (C),
.CE (CE),
.CINVCTRL (CINVCTRL),
// CNTVALUEIN0-4 should be 1 if unused
.CNTVALUEIN0 (CNTVALUEIN0 | NOT_USING_CNTVALUEIN),
.CNTVALUEIN1 (CNTVALUEIN1 | NOT_USING_CNTVALUEIN),
.CNTVALUEIN2 (CNTVALUEIN2 | NOT_USING_CNTVALUEIN),
.CNTVALUEIN3 (CNTVALUEIN3 | NOT_USING_CNTVALUEIN),
.CNTVALUEIN4 (CNTVALUEIN4 | NOT_USING_CNTVALUEIN),
.DATAIN (DATAIN | ~DATAIN_USED),
.IDATAIN (IDATAIN | ~IDATAIN_USED),
.INC (INC),
.LD (LD),
.LDPIPEEN (LDPIPEEN),
.REGRST (REGRST),
.CNTVALUEOUT0 (CNTVALUEOUT0),
.CNTVALUEOUT1 (CNTVALUEOUT1),
.CNTVALUEOUT2 (CNTVALUEOUT2),
.CNTVALUEOUT3 (CNTVALUEOUT3),
.CNTVALUEOUT4 (CNTVALUEOUT4),
.DATAOUT (DATAOUT)
);
endmodule |
module BUFG (
input I,
output O
);
BUFGCTRL _TECHMAP_REPLACE_ (
.O(O),
.CE0(1'b1),
.CE1(1'b0),
.I0(I),
.I1(1'b1),
.IGNORE0(1'b0),
.IGNORE1(1'b1),
.S0(1'b1),
.S1(1'b0)
);
endmodule |
module BUFGCE (
input I,
input CE,
output O,
);
BUFGCTRL _TECHMAP_REPLACE_ (
.O(O),
.CE0(CE),
.CE1(1'b0),
.I0(I),
.I1(1'b1),
.IGNORE0(1'b0),
.IGNORE1(1'b1),
.S0(1'b1),
.S1(1'b0)
);
endmodule |
module BUFGMUX (
input I0,
input I1,
input S,
output O
);
BUFGCTRL #(
.IS_CE0_INVERTED(1'b1)
)_TECHMAP_REPLACE_ (
.O(O),
.CE0(S),
.CE1(S),
.I0(I0),
.I1(I1),
.IGNORE0(1'b0),
.IGNORE1(1'b0),
.S0(1'b1),
.S1(1'b1)
);
endmodule |
module BUFGCTRL (
output O,
input I0, input I1,
input S0, input S1,
input CE0, input CE1,
input IGNORE0, input IGNORE1
);
parameter [0:0] INIT_OUT = 1'b0;
parameter [0:0] PRESELECT_I0 = 1'b0;
parameter [0:0] PRESELECT_I1 = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter _TECHMAP_CONSTMSK_IGNORE0_ = 0;
parameter _TECHMAP_CONSTVAL_IGNORE0_ = 0;
parameter _TECHMAP_CONSTMSK_IGNORE1_ = 0;
parameter _TECHMAP_CONSTVAL_IGNORE1_ = 0;
parameter _TECHMAP_CONSTMSK_CE0_ = 0;
parameter _TECHMAP_CONSTVAL_CE0_ = 0;
parameter _TECHMAP_CONSTMSK_CE1_ = 0;
parameter _TECHMAP_CONSTVAL_CE1_ = 0;
parameter _TECHMAP_CONSTMSK_S0_ = 0;
parameter _TECHMAP_CONSTVAL_S0_ = 0;
parameter _TECHMAP_CONSTMSK_S1_ = 0;
parameter _TECHMAP_CONSTVAL_S1_ = 0;
localparam [0:0] INV_IGNORE0 = (
_TECHMAP_CONSTMSK_IGNORE0_ == 1 &&
_TECHMAP_CONSTVAL_IGNORE0_ == 0 &&
IS_IGNORE0_INVERTED == 0);
localparam [0:0] INV_IGNORE1 = (
_TECHMAP_CONSTMSK_IGNORE1_ == 1 &&
_TECHMAP_CONSTVAL_IGNORE1_ == 0 &&
IS_IGNORE1_INVERTED == 0);
localparam [0:0] INV_CE0 = (
_TECHMAP_CONSTMSK_CE0_ == 1 &&
_TECHMAP_CONSTVAL_CE0_ == 0 &&
IS_CE0_INVERTED == 0);
localparam [0:0] INV_CE1 = (
_TECHMAP_CONSTMSK_CE1_ == 1 &&
_TECHMAP_CONSTVAL_CE1_ == 0 &&
IS_CE1_INVERTED == 0);
localparam [0:0] INV_S0 = (
_TECHMAP_CONSTMSK_S0_ == 1 &&
_TECHMAP_CONSTVAL_S0_ == 0 &&
IS_S0_INVERTED == 0);
localparam [0:0] INV_S1 = (
_TECHMAP_CONSTMSK_S1_ == 1 &&
_TECHMAP_CONSTVAL_S1_ == 0 &&
IS_S1_INVERTED == 0);
BUFGCTRL_VPR #(
.INIT_OUT(INIT_OUT),
.ZPRESELECT_I0(PRESELECT_I0),
.ZPRESELECT_I1(PRESELECT_I1),
.IS_IGNORE0_INVERTED(!IS_IGNORE0_INVERTED ^ INV_IGNORE0),
.IS_IGNORE1_INVERTED(!IS_IGNORE1_INVERTED ^ INV_IGNORE1),
.ZINV_CE0(!IS_CE0_INVERTED ^ INV_CE0),
.ZINV_CE1(!IS_CE1_INVERTED ^ INV_CE1),
.ZINV_S0(!IS_S0_INVERTED ^ INV_S0),
.ZINV_S1(!IS_S1_INVERTED ^ INV_S1)
) _TECHMAP_REPLACE_ (
.O(O),
.CE0(CE0 ^ INV_CE0),
.CE1(CE1 ^ INV_CE1),
.I0(I0),
.I1(I1),
.IGNORE0(IGNORE0 ^ INV_IGNORE0),
.IGNORE1(IGNORE1 ^ INV_IGNORE1),
.S0(S0 ^ INV_S0),
.S1(S1 ^ INV_S1)
);
endmodule |
module BUFH (
input I,
output O
);
BUFHCE _TECHMAP_REPLACE_ (
.O(O),
.I(I),
.CE(1)
);
endmodule |
module BUFHCE (
input I,
input CE,
output O
);
parameter [0:0] INIT_OUT = 1'b0;
parameter [0:0] IS_CE_INVERTED = 1'b0;
parameter [0:0] _TECHMAP_CONSTMSK_CE_ = 0;
parameter [0:0] _TECHMAP_CONSTVAL_CE_ = 0;
localparam [0:0] INV_CE = (
_TECHMAP_CONSTMSK_CE_ == 1 &&
_TECHMAP_CONSTVAL_CE_ == 0 &&
IS_CE_INVERTED == 0);
BUFHCE_VPR #(
.INIT_OUT(INIT_OUT),
.ZINV_CE(!IS_CE_INVERTED ^ INV_CE)
) _TECHMAP_REPLACE_ (
.O(O),
.I(I),
.CE(CE)
);
endmodule |
module PLLE2_ADV
(
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
input PWRDWN,
input RST,
output LOCKED,
input DCLK,
input DEN,
input DWE,
output DRDY,
input [ 6:0] DADDR,
input [15:0] DI,
output [15:0] DO
);
parameter _TECHMAP_CONSTMSK_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTVAL_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTMSK_RST_ = 0;
parameter _TECHMAP_CONSTVAL_RST_ = 0;
parameter _TECHMAP_CONSTMSK_PWRDWN_ = 0;
parameter _TECHMAP_CONSTVAL_PWRDWN_ = 0;
parameter _TECHMAP_CONSTMSK_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTVAL_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTMSK_DCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DEN_ = 0;
parameter _TECHMAP_CONSTVAL_DEN_ = 0;
parameter _TECHMAP_CONSTMSK_DWE_ = 0;
parameter _TECHMAP_CONSTVAL_DWE_ = 0;
parameter IS_CLKINSEL_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter IS_PWRDWN_INVERTED = 1'b0;
parameter BANDWIDTH = "OPTIMIZED";
parameter STARTUP_WAIT = "FALSE";
parameter COMPENSATION = "ZHOLD";
parameter CLKIN1_PERIOD = 0.0;
parameter REF_JITTER1 = 0.01;
parameter CLKIN2_PERIOD = 0.0;
parameter REF_JITTER2 = 0.01;
parameter [5:0] DIVCLK_DIVIDE = 1;
parameter [5:0] CLKFBOUT_MULT = 1;
parameter CLKFBOUT_PHASE = 0;
parameter [6:0] CLKOUT0_DIVIDE = 1;
parameter CLKOUT0_DUTY_CYCLE = 50000;
parameter signed CLKOUT0_PHASE = 0;
parameter [6:0] CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 50000;
parameter signed CLKOUT1_PHASE = 0;
parameter [6:0] CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 50000;
parameter signed CLKOUT2_PHASE = 0;
parameter [6:0] CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 50000;
parameter signed CLKOUT3_PHASE = 0;
parameter [6:0] CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 50000;
parameter signed CLKOUT4_PHASE = 0;
parameter [6:0] CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 50000;
parameter signed CLKOUT5_PHASE = 0;
// Compute PLL's registers content
localparam CLKFBOUT_REGS = pll_clkregs(CLKFBOUT_MULT, 50000, CLKFBOUT_PHASE);
localparam DIVCLK_REGS = pll_clkregs(DIVCLK_DIVIDE, 50000, 0);
localparam CLKOUT0_REGS = pll_clkregs(CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, CLKOUT0_PHASE);
localparam CLKOUT1_REGS = pll_clkregs(CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, CLKOUT1_PHASE);
localparam CLKOUT2_REGS = pll_clkregs(CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, CLKOUT2_PHASE);
localparam CLKOUT3_REGS = pll_clkregs(CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, CLKOUT3_PHASE);
localparam CLKOUT4_REGS = pll_clkregs(CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, CLKOUT4_PHASE);
localparam CLKOUT5_REGS = pll_clkregs(CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, CLKOUT5_PHASE);
// Handle inputs that should have certain logic levels when left unconnected
// If unconnected, CLKINSEL should be set to VCC by default
localparam INV_CLKINSEL = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? !_TECHMAP_CONSTVAL_CLKINSEL_ ^ IS_CLKINSEL_INVERTED:
(_TECHMAP_CONSTVAL_CLKINSEL_ === 0) ? IS_CLKINSEL_INVERTED : IS_CLKINSEL_INVERTED;
wire clkinsel = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKINSEL_ === 0) ? 1'b1 : CLKINSEL;
localparam INV_PWRDWN = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? !_TECHMAP_CONSTVAL_PWRDWN_ ^ IS_PWRDWN_INVERTED:
(_TECHMAP_CONSTVAL_PWRDWN_ === 0) ? ~IS_PWRDWN_INVERTED : IS_PWRDWN_INVERTED;
wire pwrdwn = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PWRDWN_ === 0) ? 1'b1 : PWRDWN;
localparam INV_RST = (_TECHMAP_CONSTMSK_RST_ == 1) ? !_TECHMAP_CONSTVAL_RST_ ^ IS_RST_INVERTED:
(_TECHMAP_CONSTVAL_RST_ === 0) ? ~IS_RST_INVERTED : IS_RST_INVERTED;
wire rst = (_TECHMAP_CONSTMSK_RST_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RST_ === 0) ? 1'b1 : RST;
wire dclk = (_TECHMAP_CONSTMSK_DCLK_ == 1) ? _TECHMAP_CONSTVAL_DCLK_ :
(_TECHMAP_CONSTVAL_DCLK_ == 0) ? 1'b0 : DCLK;
wire den = (_TECHMAP_CONSTMSK_DEN_ == 1) ? _TECHMAP_CONSTVAL_DEN_ :
(_TECHMAP_CONSTVAL_DEN_ == 0) ? 1'b0 : DEN;
wire dwe = (_TECHMAP_CONSTMSK_DWE_ == 1) ? _TECHMAP_CONSTVAL_DWE_ :
(_TECHMAP_CONSTVAL_DWE_ == 0) ? 1'b0 : DWE;
// The substituted cell
PLLE2_ADV_VPR #
(
// Inverters
.INV_CLKINSEL(INV_CLKINSEL),
.ZINV_PWRDWN (INV_PWRDWN),
.ZINV_RST (INV_RST),
// Straight mapped parameters
.STARTUP_WAIT(STARTUP_WAIT == "TRUE"),
// Lookup tables
.LKTABLE(pll_lktable_lookup(CLKFBOUT_MULT)),
.TABLE(pll_table_lookup(CLKFBOUT_MULT, BANDWIDTH)),
// FIXME: How to compute values the two below ?
.FILTREG1_RESERVED(12'b0000_00001000),
.LOCKREG3_RESERVED(1'b1),
// Clock feedback settings
.CLKFBOUT_CLKOUT1_HIGH_TIME (CLKFBOUT_REGS[11:6]),
.CLKFBOUT_CLKOUT1_LOW_TIME (CLKFBOUT_REGS[5:0]),
.CLKFBOUT_CLKOUT1_PHASE_MUX (CLKFBOUT_REGS[15:13]),
.CLKFBOUT_CLKOUT2_DELAY_TIME (CLKFBOUT_REGS[21:16]),
.CLKFBOUT_CLKOUT2_EDGE (CLKFBOUT_REGS[23]),
.CLKFBOUT_CLKOUT2_NO_COUNT (CLKFBOUT_REGS[22]),
// Internal VCO divider settings
.DIVCLK_DIVCLK_HIGH_TIME (DIVCLK_REGS[11:6]),
.DIVCLK_DIVCLK_LOW_TIME (DIVCLK_REGS[5:0]),
.DIVCLK_DIVCLK_NO_COUNT (DIVCLK_REGS[22]),
.DIVCLK_DIVCLK_EDGE (DIVCLK_REGS[23]),
// CLKOUT0
.CLKOUT0_CLKOUT1_HIGH_TIME (CLKOUT0_REGS[11:6]),
.CLKOUT0_CLKOUT1_LOW_TIME (CLKOUT0_REGS[5:0]),
.CLKOUT0_CLKOUT1_PHASE_MUX (CLKOUT0_REGS[15:13]),
.CLKOUT0_CLKOUT2_DELAY_TIME (CLKOUT0_REGS[21:16]),
.CLKOUT0_CLKOUT2_EDGE (CLKOUT0_REGS[23]),
.CLKOUT0_CLKOUT2_NO_COUNT (CLKOUT0_REGS[22]),
// CLKOUT1
.CLKOUT1_CLKOUT1_HIGH_TIME (CLKOUT1_REGS[11:6]),
.CLKOUT1_CLKOUT1_LOW_TIME (CLKOUT1_REGS[5:0]),
.CLKOUT1_CLKOUT1_PHASE_MUX (CLKOUT1_REGS[15:13]),
.CLKOUT1_CLKOUT2_DELAY_TIME (CLKOUT1_REGS[21:16]),
.CLKOUT1_CLKOUT2_EDGE (CLKOUT1_REGS[23]),
.CLKOUT1_CLKOUT2_NO_COUNT (CLKOUT1_REGS[22]),
// CLKOUT2
.CLKOUT2_CLKOUT1_HIGH_TIME (CLKOUT2_REGS[11:6]),
.CLKOUT2_CLKOUT1_LOW_TIME (CLKOUT2_REGS[5:0]),
.CLKOUT2_CLKOUT1_PHASE_MUX (CLKOUT2_REGS[15:13]),
.CLKOUT2_CLKOUT2_DELAY_TIME (CLKOUT2_REGS[21:16]),
.CLKOUT2_CLKOUT2_EDGE (CLKOUT2_REGS[23]),
.CLKOUT2_CLKOUT2_NO_COUNT (CLKOUT2_REGS[22]),
// CLKOUT3
.CLKOUT3_CLKOUT1_HIGH_TIME (CLKOUT3_REGS[11:6]),
.CLKOUT3_CLKOUT1_LOW_TIME (CLKOUT3_REGS[5:0]),
.CLKOUT3_CLKOUT1_PHASE_MUX (CLKOUT3_REGS[15:13]),
.CLKOUT3_CLKOUT2_DELAY_TIME (CLKOUT3_REGS[21:16]),
.CLKOUT3_CLKOUT2_EDGE (CLKOUT3_REGS[23]),
.CLKOUT3_CLKOUT2_NO_COUNT (CLKOUT3_REGS[22]),
// CLKOUT4
.CLKOUT4_CLKOUT1_HIGH_TIME (CLKOUT4_REGS[11:6]),
.CLKOUT4_CLKOUT1_LOW_TIME (CLKOUT4_REGS[5:0]),
.CLKOUT4_CLKOUT1_PHASE_MUX (CLKOUT4_REGS[15:13]),
.CLKOUT4_CLKOUT2_DELAY_TIME (CLKOUT4_REGS[21:16]),
.CLKOUT4_CLKOUT2_EDGE (CLKOUT4_REGS[23]),
.CLKOUT4_CLKOUT2_NO_COUNT (CLKOUT4_REGS[22]),
// CLKOUT5
.CLKOUT5_CLKOUT1_HIGH_TIME (CLKOUT5_REGS[11:6]),
.CLKOUT5_CLKOUT1_LOW_TIME (CLKOUT5_REGS[5:0]),
.CLKOUT5_CLKOUT1_PHASE_MUX (CLKOUT5_REGS[15:13]),
.CLKOUT5_CLKOUT2_DELAY_TIME (CLKOUT5_REGS[21:16]),
.CLKOUT5_CLKOUT2_EDGE (CLKOUT5_REGS[23]),
.CLKOUT5_CLKOUT2_NO_COUNT (CLKOUT5_REGS[22]),
// Clock output enable controls
.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKFBOUT_ === 1'bX),
.CLKOUT0_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT0_ === 1'bX),
.CLKOUT1_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT1_ === 1'bX),
.CLKOUT2_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT2_ === 1'bX),
.CLKOUT3_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT3_ === 1'bX),
.CLKOUT4_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT4_ === 1'bX),
.CLKOUT5_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT5_ === 1'bX)
)
_TECHMAP_REPLACE_
(
.CLKFBIN(CLKFBIN),
.CLKIN1(CLKIN1),
.CLKIN2(CLKIN2),
.CLKFBOUT(CLKFBOUT),
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.CLKINSEL (clkinsel),
.PWRDWN (pwrdwn),
.RST (rst),
.LOCKED (LOCKED),
.DCLK (dclk),
.DEN (den),
.DWE (dwe),
.DRDY (DRDY),
.DADDR(DADDR),
.DI (DI),
.DO (DO)
);
endmodule |
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