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module PLLE2_BASE
(
input CLKFBIN,
input CLKIN,
output CLKFBOUT,
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
input RST,
output LOCKED
);
parameter IS_CLKINSEL_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter BANDWIDTH = "OPTIMIZED";
parameter STARTUP_WAIT = "FALSE";
parameter CLKIN1_PERIOD = 0.0;
parameter REF_JITTER1 = 0.1;
parameter [5:0] DIVCLK_DIVIDE = 1;
parameter [5:0] CLKFBOUT_MULT = 1;
parameter signed CLKFBOUT_PHASE = 0;
parameter [6:0] CLKOUT0_DIVIDE = 1;
parameter CLKOUT0_DUTY_CYCLE = 50000;
parameter signed CLKOUT0_PHASE = 0;
parameter [6:0] CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 50000;
parameter signed CLKOUT1_PHASE = 0;
parameter [6:0] CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 50000;
parameter signed CLKOUT2_PHASE = 0;
parameter [6:0] CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 50000;
parameter signed CLKOUT3_PHASE = 0;
parameter [6:0] CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 50000;
parameter signed CLKOUT4_PHASE = 0;
parameter [6:0] CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 50000;
parameter signed CLKOUT5_PHASE = 0;
// The substituted cell
PLLE2_ADV #
(
.IS_CLKINSEL_INVERTED(IS_CLKINSEL_INVERTED),
.IS_RST_INVERTED(IS_RST_INVERTED),
.IS_PWRDWN_INVERTED(1'b0),
.BANDWIDTH(BANDWIDTH),
.STARTUP_WAIT(STARTUP_WAIT),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.REF_JITTER1(REF_JITTER1),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE)
)
_TECHMAP_REPLACE_
(
.CLKFBIN(CLKFBIN),
.CLKIN1(CLKIN),
.CLKINSEL(1'b1),
.CLKFBOUT(CLKFBOUT),
.CLKOUT0(CLKOUT0),
.CLKOUT1(CLKOUT1),
.CLKOUT2(CLKOUT2),
.CLKOUT3(CLKOUT3),
.CLKOUT4(CLKOUT4),
.CLKOUT5(CLKOUT5),
.PWRDWN(1'b0),
.RST(RST),
.LOCKED(LOCKED),
.DCLK(1'b0),
.DEN(1'b0),
.DWE(1'b0),
.DRDY(),
.DADDR(7'd0),
.DI(16'd0),
.DO()
);
endmodule |
module MMCME2_ADV
(
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
output CLKFBOUT,
output CLKFBOUTB,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output CLKINSTOPPED,
output CLKFBSTOPPED,
input PWRDWN,
input RST,
output LOCKED,
input PSCLK,
input PSEN,
input PSINCDEC,
output PSDONE,
input DCLK,
input DEN,
input DWE,
output DRDY,
input [ 6:0] DADDR,
input [15:0] DI,
output [15:0] DO
);
parameter _TECHMAP_CONSTMSK_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTVAL_CLKINSEL_ = 0;
parameter _TECHMAP_CONSTMSK_RST_ = 0;
parameter _TECHMAP_CONSTVAL_RST_ = 0;
parameter _TECHMAP_CONSTMSK_PWRDWN_ = 0;
parameter _TECHMAP_CONSTVAL_PWRDWN_ = 0;
parameter _TECHMAP_CONSTMSK_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTVAL_CLKFBOUT_ = 0;
parameter _TECHMAP_CONSTMSK_CLKFBOUTB_= 0;
parameter _TECHMAP_CONSTVAL_CLKFBOUTB_= 0;
parameter _TECHMAP_CONSTMSK_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT0_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT0B_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT0B_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT1_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT1B_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT1B_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT2_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT2B_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT2B_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT3_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT3B_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT3B_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT4_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT5_ = 0;
parameter _TECHMAP_CONSTMSK_CLKOUT6_ = 0;
parameter _TECHMAP_CONSTVAL_CLKOUT6_ = 0;
parameter _TECHMAP_CONSTMSK_PSCLK_ = 0;
parameter _TECHMAP_CONSTVAL_PSCLK_ = 0;
parameter _TECHMAP_CONSTMSK_PSEN_ = 0;
parameter _TECHMAP_CONSTVAL_PSEN_ = 0;
parameter _TECHMAP_CONSTMSK_PSINCDEC_ = 0;
parameter _TECHMAP_CONSTVAL_PSINCDEC_ = 0;
parameter _TECHMAP_CONSTMSK_DCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DEN_ = 0;
parameter _TECHMAP_CONSTVAL_DEN_ = 0;
parameter _TECHMAP_CONSTMSK_DWE_ = 0;
parameter _TECHMAP_CONSTVAL_DWE_ = 0;
parameter IS_CLKINSEL_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter IS_PWRDWN_INVERTED = 1'b0;
parameter IS_PSEN_INVERTED = 1'b0;
parameter IS_PSINCDEC_INVERTED = 1'b0;
parameter BANDWIDTH = "OPTIMIZED";
parameter STARTUP_WAIT = "FALSE";
// Previously, the default COMPENSATION value was ZHOLD, resulting in non-functional
// bitstreams when the feedback loop is closed on-chip.
// Setting it to INTERNAL as the default creates working bitstreams for that case.
// This bug was not previously uncovered since the MMCM tests all explicitly
// specified a COMPENSATION value so the ZHOLD default was never used.
// Setting it here in the techmapper means that existing code using on-chip
// MMCM feedback without specifying a COMPENSATION value can be ported
// unmodified into the toolflow and will result in functional bitstreams.
// A test was added to test the case when relying on the default COMPENSATION value.
parameter COMPENSATION = "INTERNAL";
parameter CLKIN1_PERIOD = 0.0;
parameter REF_JITTER1 = 0.01;
parameter CLKIN2_PERIOD = 0.0;
parameter REF_JITTER2 = 0.01;
parameter [5:0] DIVCLK_DIVIDE = 1;
parameter CLKFBOUT_MULT_F = 5000;
parameter signed [31:0] CLKFBOUT_PHASE = 0;
parameter CLKFBOUT_USE_FINE_PS = "FALSE";
parameter CLKOUT0_DIVIDE_F = 1000;
parameter CLKOUT0_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT0_PHASE = 0;
parameter CLKOUT0_USE_FINE_PS = "FALSE";
parameter CLKOUT1_DIVIDE = 1;
parameter CLKOUT1_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT1_PHASE = 0;
parameter CLKOUT1_USE_FINE_PS = "FALSE";
parameter CLKOUT2_DIVIDE = 1;
parameter CLKOUT2_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT2_PHASE = 0;
parameter CLKOUT2_USE_FINE_PS = "FALSE";
parameter CLKOUT3_DIVIDE = 1;
parameter CLKOUT3_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT3_PHASE = 0;
parameter CLKOUT3_USE_FINE_PS = "FALSE";
parameter CLKOUT4_DIVIDE = 1;
parameter CLKOUT4_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT4_PHASE = 0;
parameter CLKOUT4_USE_FINE_PS = "FALSE";
parameter CLKOUT5_DIVIDE = 1;
parameter CLKOUT5_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT5_PHASE = 0;
parameter CLKOUT5_USE_FINE_PS = "FALSE";
parameter CLKOUT6_DIVIDE = 1;
parameter CLKOUT6_DUTY_CYCLE = 50000;
parameter signed [31:0] CLKOUT6_PHASE = 0;
parameter CLKOUT6_USE_FINE_PS = "FALSE";
parameter CLKOUT4_CASCADE = 0;
parameter SS_EN = "FALSE";
parameter SS_MODE = "CENTER_HIGH";
parameter SS_MOD_PERIOD = 10000;
// Sanity check parameters
if (BANDWIDTH != "HIGH" && BANDWIDTH != "LOW" && BANDWIDTH != "OPTIMIZED") begin
wire _TECHMAP_FAIL_;
$error("BANDWIDTH must be one of: 'HIGH', 'LOW', 'OPTIMIZED'");
end
if (COMPENSATION != "ZHOLD" && COMPENSATION != "EXTERNAL" && COMPENSATION != "INTERNAL" && COMPENSATION != "BUF_IN") begin
wire _TECHMAP_FAIL_;
$error("COMPENSATION must be one of: 'ZHOLD', 'EXTERNAL', 'INTERNAL', 'BUF_IN'");
end
if (DIVCLK_DIVIDE < 1 || DIVCLK_DIVIDE > 106) begin
wire _TECHMAP_FAIL_;
$error("DIVCLK_DIVIDE must range from 1 to 106");
end
if (CLKFBOUT_MULT_F < 2000 || CLKFBOUT_MULT_F > 64000) begin
wire _TECHMAP_FAIL_;
$error("CLKFBOUT_MULT_F must range from 2000 to 64000");
end
if (CLKFBOUT_PHASE < -32'sd360000 || CLKFBOUT_PHASE > 32'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKFBOUT_PHASE must range from -360000 to 360000");
end
if (CLKOUT0_DIVIDE_F < 1000 || CLKOUT0_DIVIDE_F > 128000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT0_DIVIDE_F must range from 1000 to 128000");
end
if (CLKOUT1_DIVIDE < 1 || CLKOUT1_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT1_DIVIDE must range from 1 to 128");
end
if (CLKOUT2_DIVIDE < 1 || CLKOUT2_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT2_DIVIDE must range from 1 to 128");
end
if (CLKOUT3_DIVIDE < 1 || CLKOUT3_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT3_DIVIDE must range from 1 to 128");
end
if (CLKOUT4_DIVIDE < 1 || CLKOUT4_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT4_DIVIDE must range from 1 to 128");
end
if (CLKOUT5_DIVIDE < 1 || CLKOUT5_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT5_DIVIDE must range from 1 to 128");
end
if (CLKOUT6_DIVIDE < 1 || CLKOUT6_DIVIDE > 128) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT6_DIVIDE must range from 1 to 128");
end
if (CLKOUT0_PHASE < -'sd360000 || CLKOUT0_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT0_PHASE must range from -360000 to 360000");
end
if (CLKOUT1_PHASE < -'sd360000 || CLKOUT1_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT1_PHASE must range from -360000 to 360000");
end
if (CLKOUT2_PHASE < -'sd360000 || CLKOUT2_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT2_PHASE must range from -360000 to 360000");
end
if (CLKOUT3_PHASE < -'sd360000 || CLKOUT3_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT3_PHASE must range from -360000 to 360000");
end
if (CLKOUT4_PHASE < -'sd360000 || CLKOUT4_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT4_PHASE must range from -360000 to 360000");
end
if (CLKOUT5_PHASE < -'sd360000 || CLKOUT5_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT5_PHASE must range from -360000 to 360000");
end
if (CLKOUT6_PHASE < -'sd360000 || CLKOUT6_PHASE > 'sd360000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT6_PHASE must range from -360000 to 360000");
end
if (CLKOUT0_DUTY_CYCLE < 1000 || CLKOUT0_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT0_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT1_DUTY_CYCLE < 1000 || CLKOUT1_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT1_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT2_DUTY_CYCLE < 1000 || CLKOUT2_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT2_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT3_DUTY_CYCLE < 1000 || CLKOUT3_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT3_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT4_DUTY_CYCLE < 1000 || CLKOUT4_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT4_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT5_DUTY_CYCLE < 1000 || CLKOUT5_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT5_DUTY_CYCLE must range from 1000 to 99000");
end
if (CLKOUT6_DUTY_CYCLE < 1000 || CLKOUT6_DUTY_CYCLE > 99000) begin
wire _TECHMAP_FAIL_;
$error("CLKOUT6_DUTY_CYCLE must range from 1000 to 99000");
end
if (SS_EN != "TRUE" && SS_EN != "FALSE") begin
wire _TECHMAP_FAIL_;
$error("SS_EN must be either 'TRUE' or 'FALSE'");
end
if (SS_MODE != "DOWN_LOW" && SS_MODE != "DOWN_HIGH" && SS_MODE != "CENTER_LOW" && SS_MODE != "CENTER_HIGH") begin
wire _TECHMAP_FAIL_;
$error("SS_MODE must be one of: 'DOWN_LOW', 'DOWN_HIGH', 'CENTER_LOW', 'CENTER_HIGH'");
end
if (SS_MOD_PERIOD < 4000 || SS_MOD_PERIOD > 40000) begin
wire _TECHMAP_FAIL_;
$error("SS_MOD_PERIOD must range from 4000 to 40000");
end
// Round fractional dividers to multiples of 1/8.
// (125 / 2 = 62.5)
localparam CLKFBOUT_MULT_R = ((CLKFBOUT_MULT_F + 62) / 125) * 125;
localparam CLKOUT0_DIVIDE_R = ((CLKOUT0_DIVIDE_F + 62) / 125) * 125;
// Compute integer multipliers needed later for look-up tables
localparam CLKFBOUT_MULT = CLKFBOUT_MULT_R / 1000;
localparam CLKOUT0_DIVIDE = CLKOUT0_DIVIDE_R / 1000;
// Check whether fractional divider needs to be enabled on CLKFBOUT and
// CLKOUT0
localparam CLKFBOUT_FRAC_EN = (CLKFBOUT_MULT_R % 1000) != 0;
localparam CLKOUT0_FRAC_EN = (CLKOUT0_DIVIDE_R % 1000) != 0;
if (CLKOUT0_FRAC_EN && CLKOUT0_DUTY_CYCLE != 50000) begin
wire _TECHMAP_FAIL_;
$error("When CLKOUT0 uses fractional divider the duty cycle must be 50%");
end
// Check whether phase shift of CLKFBOUT and CLKOUT0 is a multiple of 45 deg.
// This is needed for determining content of POWER_REG.
localparam CLKFBOUT_PHASE_45 = (CLKFBOUT_PHASE % 45000) == 0;
localparam CLKOUT0_PHASE_45 = (CLKOUT0_PHASE % 45000) == 0;
// Handle registers controling fractional dividers
localparam CLKFBOUT_CALC = mmcm_clkregs(CLKFBOUT_MULT, 50000, CLKFBOUT_PHASE);
localparam CLKOUT0_CALC = mmcm_clkregs(CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, CLKOUT0_PHASE);
localparam CLKOUT5_CALC = mmcm_clkregs(CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, CLKOUT5_PHASE);
localparam CLKOUT6_CALC = mmcm_clkregs(CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE, CLKOUT6_PHASE);
localparam CLKFBOUT_FRAC_CALC = mmcm_clkregs_frac(CLKFBOUT_MULT_R, 50000, CLKFBOUT_PHASE);
localparam CLKOUT0_FRAC_CALC = mmcm_clkregs_frac(CLKOUT0_DIVIDE_R, 50000, CLKOUT0_PHASE);
// Compute PLL's registers content
//
// When no fractional divider is enabled use the *_CALC content.
// For fractional divider use *_FRAC_CALC content but tak the "EDGE" bit
// from *_CALC. This is not documented in XAPP888 but has been observed in
// vendor tools.
//
// Additional part of *_FRAC_CALC data needs to end up in bits of
// CLKOUT5_REGS and CLKOUT6_REGS.
localparam CLKFBOUT_REGS = (CLKFBOUT_FRAC_EN) ? (CLKFBOUT_FRAC_CALC[31:0] | (CLKFBOUT_CALC[23] << 23)): CLKFBOUT_CALC;
localparam DIVCLK_REGS = mmcm_clkregs(DIVCLK_DIVIDE, 50000, 0);
localparam CLKOUT0_REGS = (CLKOUT0_FRAC_EN) ? (CLKOUT0_FRAC_CALC[31:0] | (CLKOUT0_CALC[23] << 23)): CLKOUT0_CALC;
localparam CLKOUT1_REGS = mmcm_clkregs(CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, CLKOUT1_PHASE);
localparam CLKOUT2_REGS = mmcm_clkregs(CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, CLKOUT2_PHASE);
localparam CLKOUT3_REGS = mmcm_clkregs(CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, CLKOUT3_PHASE);
localparam CLKOUT4_REGS = mmcm_clkregs(CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, CLKOUT4_PHASE);
// Substitute the shared part of CLKOUT5 and CLKOUT6 regs with data for
// CLKOUT0 and CLKFBOUT when factional divider is used for either of them.
//
// Additionaly copy the PHASE_MUX field to the PHASE_MUX_F fiels when
// fractional divider is not used. This behavior is not documented in
// XAPP888 but has been observed.
localparam CLKOUT5_REGS = (CLKOUT0_FRAC_EN) ? {CLKOUT5_CALC[31:30], CLKOUT0_FRAC_CALC[35:32], CLKOUT5_CALC[25:0]} :
{CLKOUT5_CALC[31:30], CLKOUT0_CALC[15:13], CLKOUT5_CALC[26:0]};
localparam CLKOUT6_REGS = (CLKFBOUT_FRAC_EN) ? {CLKOUT6_CALC[31:30], CLKFBOUT_FRAC_CALC[35:32], CLKOUT6_CALC[25:0]} :
{CLKOUT6_CALC[31:30], CLKFBOUT_CALC[15:13], CLKOUT6_CALC[26:0]};
// Handle inputs that should have certain logic levels when left unconnected
localparam INV_CLKINSEL = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? !_TECHMAP_CONSTVAL_CLKINSEL_ : IS_CLKINSEL_INVERTED;
wire clkinsel = (_TECHMAP_CONSTMSK_CLKINSEL_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKINSEL_ == 0) ? 1'b1 :
CLKINSEL;
localparam INV_PWRDWN = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? !_TECHMAP_CONSTVAL_PWRDWN_ :
(_TECHMAP_CONSTVAL_PWRDWN_ == 0) ? ~IS_PWRDWN_INVERTED :
IS_PWRDWN_INVERTED;
wire pwrdwn = (_TECHMAP_CONSTMSK_PWRDWN_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PWRDWN_ == 0) ? 1'b1 : PWRDWN;
localparam INV_RST = (_TECHMAP_CONSTMSK_RST_ == 1) ? !_TECHMAP_CONSTVAL_RST_ :
(_TECHMAP_CONSTVAL_RST_ == 0) ? ~IS_RST_INVERTED :
IS_RST_INVERTED;
wire rst = (_TECHMAP_CONSTMSK_RST_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RST_ == 0) ? 1'b1 : RST;
wire dclk = (_TECHMAP_CONSTMSK_DCLK_ == 1) ? _TECHMAP_CONSTVAL_DCLK_ :
(_TECHMAP_CONSTVAL_DCLK_ == 0) ? 1'b0 : DCLK;
wire den = (_TECHMAP_CONSTMSK_DEN_ == 1) ? _TECHMAP_CONSTVAL_DEN_ :
(_TECHMAP_CONSTVAL_DEN_ == 0) ? 1'b0 : DEN;
wire dwe = (_TECHMAP_CONSTMSK_DWE_ == 1) ? _TECHMAP_CONSTVAL_DWE_ :
(_TECHMAP_CONSTVAL_DWE_ == 0) ? 1'b0 : DWE;
wire psclk = (_TECHMAP_CONSTMSK_PSCLK_ == 1) ? _TECHMAP_CONSTVAL_PSCLK_ :
(_TECHMAP_CONSTVAL_PSCLK_ == 0) ? 1'b0 : PSCLK;
localparam INV_PSEN = (_TECHMAP_CONSTMSK_PSEN_ == 1) ? !_TECHMAP_CONSTVAL_PSEN_ :
(_TECHMAP_CONSTVAL_PSEN_ == 0) ? ~IS_PSEN_INVERTED :
IS_PSEN_INVERTED;
wire psen = (_TECHMAP_CONSTMSK_PSEN_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PSEN_ == 0) ? 1'b1 : PSEN;
localparam INV_PSINCDEC = (_TECHMAP_CONSTMSK_PSINCDEC_ == 1) ? !_TECHMAP_CONSTVAL_PSINCDEC_ :
(_TECHMAP_CONSTVAL_PSINCDEC_ == 0) ? ~IS_PSINCDEC_INVERTED :
IS_PSINCDEC_INVERTED;
wire psincdec = (_TECHMAP_CONSTMSK_PSINCDEC_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PSINCDEC_ == 0) ? 1'b1 : PSINCDEC;
// The substituted cell
MMCME2_ADV_VPR #
(
// Inverters
.INV_CLKINSEL (INV_CLKINSEL),
.ZINV_PWRDWN (INV_PWRDWN),
.ZINV_RST (INV_RST),
.ZINV_PSEN (INV_PSEN),
.ZINV_PSINCDEC (INV_PSINCDEC),
// Compensation
.COMP_ZHOLD (COMPENSATION == "ZHOLD"),
.COMP_Z_ZHOLD (COMPENSATION != "ZHOLD"),
// Spread spectrum
.SS_EN (1'b0), // TODO: Disable for now
// Straight mapped parameters
.STARTUP_WAIT(STARTUP_WAIT == "TRUE"),
// Lookup tables
.LKTABLE(mmcm_lktable_lookup(CLKFBOUT_MULT)),
.TABLE(mmcm_table_lookup(CLKFBOUT_MULT, BANDWIDTH, (SS_EN == "TRUE"))),
// FIXME: How to compute values the two below ?
.FILTREG1_RESERVED(12'b0000_00001000),
.LOCKREG3_RESERVED(1'b1),
// Clock feedback settings
.CLKFBOUT_CLKOUT1_HIGH_TIME (CLKFBOUT_REGS[11:6]),
.CLKFBOUT_CLKOUT1_LOW_TIME (CLKFBOUT_REGS[5:0]),
.CLKFBOUT_CLKOUT1_PHASE_MUX (CLKFBOUT_REGS[15:13]),
.CLKFBOUT_CLKOUT2_DELAY_TIME (CLKFBOUT_REGS[21:16]),
.CLKFBOUT_CLKOUT2_EDGE (CLKFBOUT_REGS[23]),
.CLKFBOUT_CLKOUT2_FRAC (CLKFBOUT_REGS[30:28]),
.CLKFBOUT_CLKOUT2_FRAC_EN (CLKFBOUT_REGS[27]),
.CLKFBOUT_CLKOUT2_FRAC_WF_R (CLKFBOUT_REGS[26]),
.CLKFBOUT_CLKOUT2_NO_COUNT (CLKFBOUT_REGS[22]),
// Internal VCO divider settings
.DIVCLK_DIVCLK_HIGH_TIME (DIVCLK_REGS[11:6]),
.DIVCLK_DIVCLK_LOW_TIME (DIVCLK_REGS[5:0]),
.DIVCLK_DIVCLK_NO_COUNT (DIVCLK_REGS[22]),
.DIVCLK_DIVCLK_EDGE (DIVCLK_REGS[23]),
// CLKOUT0
.CLKOUT0_CLKOUT1_HIGH_TIME (CLKOUT0_REGS[11:6]),
.CLKOUT0_CLKOUT1_LOW_TIME (CLKOUT0_REGS[5:0]),
.CLKOUT0_CLKOUT1_PHASE_MUX (CLKOUT0_REGS[15:13]),
.CLKOUT0_CLKOUT2_DELAY_TIME (CLKOUT0_REGS[21:16]),
.CLKOUT0_CLKOUT2_EDGE (CLKOUT0_REGS[23]),
.CLKOUT0_CLKOUT2_FRAC (CLKOUT0_REGS[30:28]),
.CLKOUT0_CLKOUT2_FRAC_EN (CLKOUT0_REGS[27]),
.CLKOUT0_CLKOUT2_FRAC_WF_R (CLKOUT0_REGS[26]),
.CLKOUT0_CLKOUT2_NO_COUNT (CLKOUT0_REGS[22]),
// CLKOUT1
.CLKOUT1_CLKOUT1_HIGH_TIME (CLKOUT1_REGS[11:6]),
.CLKOUT1_CLKOUT1_LOW_TIME (CLKOUT1_REGS[5:0]),
.CLKOUT1_CLKOUT1_PHASE_MUX (CLKOUT1_REGS[15:13]),
.CLKOUT1_CLKOUT2_DELAY_TIME (CLKOUT1_REGS[21:16]),
.CLKOUT1_CLKOUT2_EDGE (CLKOUT1_REGS[23]),
.CLKOUT1_CLKOUT2_NO_COUNT (CLKOUT1_REGS[22]),
// CLKOUT2
.CLKOUT2_CLKOUT1_HIGH_TIME (CLKOUT2_REGS[11:6]),
.CLKOUT2_CLKOUT1_LOW_TIME (CLKOUT2_REGS[5:0]),
.CLKOUT2_CLKOUT1_PHASE_MUX (CLKOUT2_REGS[15:13]),
.CLKOUT2_CLKOUT2_DELAY_TIME (CLKOUT2_REGS[21:16]),
.CLKOUT2_CLKOUT2_EDGE (CLKOUT2_REGS[23]),
.CLKOUT2_CLKOUT2_NO_COUNT (CLKOUT2_REGS[22]),
// CLKOUT3
.CLKOUT3_CLKOUT1_HIGH_TIME (CLKOUT3_REGS[11:6]),
.CLKOUT3_CLKOUT1_LOW_TIME (CLKOUT3_REGS[5:0]),
.CLKOUT3_CLKOUT1_PHASE_MUX (CLKOUT3_REGS[15:13]),
.CLKOUT3_CLKOUT2_DELAY_TIME (CLKOUT3_REGS[21:16]),
.CLKOUT3_CLKOUT2_EDGE (CLKOUT3_REGS[23]),
.CLKOUT3_CLKOUT2_NO_COUNT (CLKOUT3_REGS[22]),
// CLKOUT4
.CLKOUT4_CLKOUT1_HIGH_TIME (CLKOUT4_REGS[11:6]),
.CLKOUT4_CLKOUT1_LOW_TIME (CLKOUT4_REGS[5:0]),
.CLKOUT4_CLKOUT1_PHASE_MUX (CLKOUT4_REGS[15:13]),
.CLKOUT4_CLKOUT2_DELAY_TIME (CLKOUT4_REGS[21:16]),
.CLKOUT4_CLKOUT2_EDGE (CLKOUT4_REGS[23]),
.CLKOUT4_CLKOUT2_NO_COUNT (CLKOUT4_REGS[22]),
// CLKOUT5
.CLKOUT5_CLKOUT1_HIGH_TIME (CLKOUT5_REGS[11:6]),
.CLKOUT5_CLKOUT1_LOW_TIME (CLKOUT5_REGS[5:0]),
.CLKOUT5_CLKOUT1_PHASE_MUX (CLKOUT5_REGS[15:13]),
.CLKOUT5_CLKOUT2_FRACTIONAL_DELAY_TIME (CLKOUT5_REGS[21:16]),
.CLKOUT5_CLKOUT2_FRACTIONAL_EDGE (CLKOUT5_REGS[23]),
.CLKOUT5_CLKOUT2_FRACTIONAL_NO_COUNT (CLKOUT5_REGS[22]),
.CLKOUT5_CLKOUT2_FRACTIONAL_PHASE_MUX_F (CLKOUT5_REGS[29:27]),
.CLKOUT5_CLKOUT2_FRACTIONAL_FRAC_WF_F (CLKOUT5_REGS[26]),
// CLKOUT6
.CLKOUT6_CLKOUT1_HIGH_TIME (CLKOUT6_REGS[11:6]),
.CLKOUT6_CLKOUT1_LOW_TIME (CLKOUT6_REGS[5:0]),
.CLKOUT6_CLKOUT1_PHASE_MUX (CLKOUT6_REGS[15:13]),
.CLKOUT6_CLKOUT2_FRACTIONAL_DELAY_TIME (CLKOUT6_REGS[21:16]),
.CLKOUT6_CLKOUT2_FRACTIONAL_EDGE (CLKOUT6_REGS[23]),
.CLKOUT6_CLKOUT2_FRACTIONAL_NO_COUNT (CLKOUT6_REGS[22]),
.CLKOUT6_CLKOUT2_FRACTIONAL_PHASE_MUX_F (CLKOUT6_REGS[29:27]),
.CLKOUT6_CLKOUT2_FRACTIONAL_FRAC_WF_F (CLKOUT6_REGS[26]),
// POWER_REG
// FIXME: Check whether this is always thar same content. XAPP888 says that
// "all the bits should be set when performing DRP". The values below has
// been observed to be used by vendor tools in some circumstances.
.POWER_REG ((CLKFBOUT_FRAC_EN || CLKOUT0_FRAC_EN || !CLKOUT0_PHASE_45) ? 16'b10011001_00000000 :
16'b00000001_00000000),
// Clock output enable controls
.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKFBOUT_ === 1'bX || _TECHMAP_CONSTVAL_CLKFBOUTB_ === 1'bX),
.CLKOUT0_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT0_ === 1'bX || _TECHMAP_CONSTVAL_CLKOUT0B_ === 1'bX),
.CLKOUT1_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT1_ === 1'bX || _TECHMAP_CONSTVAL_CLKOUT1B_ === 1'bX),
.CLKOUT2_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT2_ === 1'bX || _TECHMAP_CONSTVAL_CLKOUT2B_ === 1'bX),
.CLKOUT3_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT3_ === 1'bX || _TECHMAP_CONSTVAL_CLKOUT3B_ === 1'bX),
.CLKOUT4_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT4_ === 1'bX),
.CLKOUT5_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT5_ === 1'bX),
.CLKOUT6_CLKOUT1_OUTPUT_ENABLE(_TECHMAP_CONSTVAL_CLKOUT6_ === 1'bX)
)
_TECHMAP_REPLACE_
(
.CLKFBIN (CLKFBIN),
.CLKIN1 (CLKIN1),
.CLKIN2 (CLKIN2),
.CLKINSEL (clkinsel),
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.CLKINSTOPPED (CLKINSTOPPED),
.CLKFBSTOPPED (CLKFBSTOPPED),
.PWRDWN (pwrdwn),
.RST (rst),
.LOCKED (LOCKED),
.PSCLK (psclk),
.PSEN (psen),
.PSINCDEC (psincdec),
.PSDONE (PSDONE),
.DCLK (dclk),
.DEN (den),
.DWE (dwe),
.DRDY (DRDY),
.DADDR0 (DADDR[0]),
.DADDR1 (DADDR[1]),
.DADDR2 (DADDR[2]),
.DADDR3 (DADDR[3]),
.DADDR4 (DADDR[4]),
.DADDR5 (DADDR[5]),
.DADDR6 (DADDR[6]),
.DI0 (DI[0]),
.DI1 (DI[1]),
.DI2 (DI[2]),
.DI3 (DI[3]),
.DI4 (DI[4]),
.DI5 (DI[5]),
.DI6 (DI[6]),
.DI7 (DI[7]),
.DI8 (DI[8]),
.DI9 (DI[9]),
.DI10 (DI[10]),
.DI11 (DI[11]),
.DI12 (DI[12]),
.DI13 (DI[13]),
.DI14 (DI[14]),
.DI15 (DI[15]),
.DO0 (DO[0]),
.DO1 (DO[1]),
.DO2 (DO[2]),
.DO3 (DO[3]),
.DO4 (DO[4]),
.DO5 (DO[5]),
.DO6 (DO[6]),
.DO7 (DO[7]),
.DO8 (DO[8]),
.DO9 (DO[9]),
.DO10 (DO[10]),
.DO11 (DO[11]),
.DO12 (DO[12]),
.DO13 (DO[13]),
.DO14 (DO[14]),
.DO15 (DO[15])
);
endmodule |
module INV(
output O,
input I
);
LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.O(O), .I0(I));
endmodule |
module PS7 (
inout [14: 0] DDRA,
input [ 3: 0] DDRARB,
inout [ 2: 0] DDRBA,
inout DDRCASB,
inout DDRCKE,
inout DDRCKN,
inout DDRCKP,
inout DDRCSB,
inout [ 3: 0] DDRDM,
inout [31: 0] DDRDQ,
inout [ 3: 0] DDRDQSN,
inout [ 3: 0] DDRDQSP,
inout DDRDRSTB,
inout DDRODT,
inout DDRRASB,
inout DDRVRN,
inout DDRVRP,
inout DDRWEB,
input DMA0ACLK,
input DMA0DAREADY,
output [ 1: 0] DMA0DATYPE,
output DMA0DAVALID,
input DMA0DRLAST,
output DMA0DRREADY,
input [ 1: 0] DMA0DRTYPE,
input DMA0DRVALID,
output DMA0RSTN,
input DMA1ACLK,
input DMA1DAREADY,
output [ 1: 0] DMA1DATYPE,
output DMA1DAVALID,
input DMA1DRLAST,
output DMA1DRREADY,
input [ 1: 0] DMA1DRTYPE,
input DMA1DRVALID,
output DMA1RSTN,
input DMA2ACLK,
input DMA2DAREADY,
output [ 1: 0] DMA2DATYPE,
output DMA2DAVALID,
input DMA2DRLAST,
output DMA2DRREADY,
input [ 1: 0] DMA2DRTYPE,
input DMA2DRVALID,
output DMA2RSTN,
input DMA3ACLK,
input DMA3DAREADY,
output [ 1: 0] DMA3DATYPE,
output DMA3DAVALID,
input DMA3DRLAST,
output DMA3DRREADY,
input [ 1: 0] DMA3DRTYPE,
input DMA3DRVALID,
output DMA3RSTN,
input EMIOCAN0PHYRX,
output EMIOCAN0PHYTX,
input EMIOCAN1PHYRX,
output EMIOCAN1PHYTX,
input EMIOENET0EXTINTIN,
input EMIOENET0GMIICOL,
input EMIOENET0GMIICRS,
input EMIOENET0GMIIRXCLK,
input [ 7: 0] EMIOENET0GMIIRXD,
input EMIOENET0GMIIRXDV,
input EMIOENET0GMIIRXER,
input EMIOENET0GMIITXCLK,
output [ 7: 0] EMIOENET0GMIITXD,
output EMIOENET0GMIITXEN,
output EMIOENET0GMIITXER,
input EMIOENET0MDIOI,
output EMIOENET0MDIOMDC,
output EMIOENET0MDIOO,
output EMIOENET0MDIOTN,
output EMIOENET0PTPDELAYREQRX,
output EMIOENET0PTPDELAYREQTX,
output EMIOENET0PTPPDELAYREQRX,
output EMIOENET0PTPPDELAYREQTX,
output EMIOENET0PTPPDELAYRESPRX,
output EMIOENET0PTPPDELAYRESPTX,
output EMIOENET0PTPSYNCFRAMERX,
output EMIOENET0PTPSYNCFRAMETX,
output EMIOENET0SOFRX,
output EMIOENET0SOFTX,
input EMIOENET1EXTINTIN,
input EMIOENET1GMIICOL,
input EMIOENET1GMIICRS,
input EMIOENET1GMIIRXCLK,
input [ 7: 0] EMIOENET1GMIIRXD,
input EMIOENET1GMIIRXDV,
input EMIOENET1GMIIRXER,
input EMIOENET1GMIITXCLK,
output [ 7: 0] EMIOENET1GMIITXD,
output EMIOENET1GMIITXEN,
output EMIOENET1GMIITXER,
input EMIOENET1MDIOI,
output EMIOENET1MDIOMDC,
output EMIOENET1MDIOO,
output EMIOENET1MDIOTN,
output EMIOENET1PTPDELAYREQRX,
output EMIOENET1PTPDELAYREQTX,
output EMIOENET1PTPPDELAYREQRX,
output EMIOENET1PTPPDELAYREQTX,
output EMIOENET1PTPPDELAYRESPRX,
output EMIOENET1PTPPDELAYRESPTX,
output EMIOENET1PTPSYNCFRAMERX,
output EMIOENET1PTPSYNCFRAMETX,
output EMIOENET1SOFRX,
output EMIOENET1SOFTX,
input [63: 0] EMIOGPIOI,
output [63: 0] EMIOGPIOO,
output [63: 0] EMIOGPIOTN,
input EMIOI2C0SCLI,
output EMIOI2C0SCLO,
output EMIOI2C0SCLTN,
input EMIOI2C0SDAI,
output EMIOI2C0SDAO,
output EMIOI2C0SDATN,
input EMIOI2C1SCLI,
output EMIOI2C1SCLO,
output EMIOI2C1SCLTN,
input EMIOI2C1SDAI,
output EMIOI2C1SDAO,
output EMIOI2C1SDATN,
input EMIOPJTAGTCK,
input EMIOPJTAGTDI,
output EMIOPJTAGTDO,
output EMIOPJTAGTDTN,
input EMIOPJTAGTMS,
output EMIOSDIO0BUSPOW,
output [ 2: 0] EMIOSDIO0BUSVOLT,
input EMIOSDIO0CDN,
output EMIOSDIO0CLK,
input EMIOSDIO0CLKFB,
input EMIOSDIO0CMDI,
output EMIOSDIO0CMDO,
output EMIOSDIO0CMDTN,
input [ 3: 0] EMIOSDIO0DATAI,
output [ 3: 0] EMIOSDIO0DATAO,
output [ 3: 0] EMIOSDIO0DATATN,
output EMIOSDIO0LED,
input EMIOSDIO0WP,
output EMIOSDIO1BUSPOW,
output [ 2: 0] EMIOSDIO1BUSVOLT,
input EMIOSDIO1CDN,
output EMIOSDIO1CLK,
input EMIOSDIO1CLKFB,
input EMIOSDIO1CMDI,
output EMIOSDIO1CMDO,
output EMIOSDIO1CMDTN,
input [ 3: 0] EMIOSDIO1DATAI,
output [ 3: 0] EMIOSDIO1DATAO,
output [ 3: 0] EMIOSDIO1DATATN,
output EMIOSDIO1LED,
input EMIOSDIO1WP,
input EMIOSPI0MI,
output EMIOSPI0MO,
output EMIOSPI0MOTN,
input EMIOSPI0SCLKI,
output EMIOSPI0SCLKO,
output EMIOSPI0SCLKTN,
input EMIOSPI0SI,
output EMIOSPI0SO,
input EMIOSPI0SSIN,
output EMIOSPI0SSNTN,
output [ 2: 0] EMIOSPI0SSON,
output EMIOSPI0STN,
input EMIOSPI1MI,
output EMIOSPI1MO,
output EMIOSPI1MOTN,
input EMIOSPI1SCLKI,
output EMIOSPI1SCLKO,
output EMIOSPI1SCLKTN,
input EMIOSPI1SI,
output EMIOSPI1SO,
input EMIOSPI1SSIN,
output EMIOSPI1SSNTN,
output [ 2: 0] EMIOSPI1SSON,
output EMIOSPI1STN,
input EMIOSRAMINTIN,
input EMIOTRACECLK,
output EMIOTRACECTL,
output [31: 0] EMIOTRACEDATA,
input [ 2: 0] EMIOTTC0CLKI,
output [ 2: 0] EMIOTTC0WAVEO,
input [ 2: 0] EMIOTTC1CLKI,
output [ 2: 0] EMIOTTC1WAVEO,
input EMIOUART0CTSN,
input EMIOUART0DCDN,
input EMIOUART0DSRN,
output EMIOUART0DTRN,
input EMIOUART0RIN,
output EMIOUART0RTSN,
input EMIOUART0RX,
output EMIOUART0TX,
input EMIOUART1CTSN,
input EMIOUART1DCDN,
input EMIOUART1DSRN,
output EMIOUART1DTRN,
input EMIOUART1RIN,
output EMIOUART1RTSN,
input EMIOUART1RX,
output EMIOUART1TX,
output [ 1: 0] EMIOUSB0PORTINDCTL,
input EMIOUSB0VBUSPWRFAULT,
output EMIOUSB0VBUSPWRSELECT,
output [ 1: 0] EMIOUSB1PORTINDCTL,
input EMIOUSB1VBUSPWRFAULT,
output EMIOUSB1VBUSPWRSELECT,
input EMIOWDTCLKI,
output EMIOWDTRSTO,
input EVENTEVENTI,
output EVENTEVENTO,
output [ 1: 0] EVENTSTANDBYWFE,
output [ 1: 0] EVENTSTANDBYWFI,
output [ 3: 0] FCLKCLK,
input [ 3: 0] FCLKCLKTRIGN,
output [ 3: 0] FCLKRESETN,
input FPGAIDLEN,
input [ 3: 0] FTMDTRACEINATID,
input FTMDTRACEINCLOCK,
input [31: 0] FTMDTRACEINDATA,
input FTMDTRACEINVALID,
input [31: 0] FTMTF2PDEBUG,
input [ 3: 0] FTMTF2PTRIG,
output [ 3: 0] FTMTF2PTRIGACK,
output [31: 0] FTMTP2FDEBUG,
output [ 3: 0] FTMTP2FTRIG,
input [ 3: 0] FTMTP2FTRIGACK,
input [19: 0] IRQF2P,
output [28: 0] IRQP2F,
input MAXIGP0ACLK,
output [31: 0] MAXIGP0ARADDR,
output [ 1: 0] MAXIGP0ARBURST,
output [ 3: 0] MAXIGP0ARCACHE,
output MAXIGP0ARESETN,
output [11: 0] MAXIGP0ARID,
output [ 3: 0] MAXIGP0ARLEN,
output [ 1: 0] MAXIGP0ARLOCK,
output [ 2: 0] MAXIGP0ARPROT,
output [ 3: 0] MAXIGP0ARQOS,
input MAXIGP0ARREADY,
output [ 1: 0] MAXIGP0ARSIZE,
output MAXIGP0ARVALID,
output [31: 0] MAXIGP0AWADDR,
output [ 1: 0] MAXIGP0AWBURST,
output [ 3: 0] MAXIGP0AWCACHE,
output [11: 0] MAXIGP0AWID,
output [ 3: 0] MAXIGP0AWLEN,
output [ 1: 0] MAXIGP0AWLOCK,
output [ 2: 0] MAXIGP0AWPROT,
output [ 3: 0] MAXIGP0AWQOS,
input MAXIGP0AWREADY,
output [ 1: 0] MAXIGP0AWSIZE,
output MAXIGP0AWVALID,
input [11: 0] MAXIGP0BID,
output MAXIGP0BREADY,
input [ 1: 0] MAXIGP0BRESP,
input MAXIGP0BVALID,
input [31: 0] MAXIGP0RDATA,
input [11: 0] MAXIGP0RID,
input MAXIGP0RLAST,
output MAXIGP0RREADY,
input [ 1: 0] MAXIGP0RRESP,
input MAXIGP0RVALID,
output [31: 0] MAXIGP0WDATA,
output [11: 0] MAXIGP0WID,
output MAXIGP0WLAST,
input MAXIGP0WREADY,
output [ 3: 0] MAXIGP0WSTRB,
output MAXIGP0WVALID,
input MAXIGP1ACLK,
output [31: 0] MAXIGP1ARADDR,
output [ 1: 0] MAXIGP1ARBURST,
output [ 3: 0] MAXIGP1ARCACHE,
output MAXIGP1ARESETN,
output [11: 0] MAXIGP1ARID,
output [ 3: 0] MAXIGP1ARLEN,
output [ 1: 0] MAXIGP1ARLOCK,
output [ 2: 0] MAXIGP1ARPROT,
output [ 3: 0] MAXIGP1ARQOS,
input MAXIGP1ARREADY,
output [ 1: 0] MAXIGP1ARSIZE,
output MAXIGP1ARVALID,
output [31: 0] MAXIGP1AWADDR,
output [ 1: 0] MAXIGP1AWBURST,
output [ 3: 0] MAXIGP1AWCACHE,
output [11: 0] MAXIGP1AWID,
output [ 3: 0] MAXIGP1AWLEN,
output [ 1: 0] MAXIGP1AWLOCK,
output [ 2: 0] MAXIGP1AWPROT,
output [ 3: 0] MAXIGP1AWQOS,
input MAXIGP1AWREADY,
output [ 1: 0] MAXIGP1AWSIZE,
output MAXIGP1AWVALID,
input [11: 0] MAXIGP1BID,
output MAXIGP1BREADY,
input [ 1: 0] MAXIGP1BRESP,
input MAXIGP1BVALID,
input [31: 0] MAXIGP1RDATA,
input [11: 0] MAXIGP1RID,
input MAXIGP1RLAST,
output MAXIGP1RREADY,
input [ 1: 0] MAXIGP1RRESP,
input MAXIGP1RVALID,
output [31: 0] MAXIGP1WDATA,
output [11: 0] MAXIGP1WID,
output MAXIGP1WLAST,
input MAXIGP1WREADY,
output [ 3: 0] MAXIGP1WSTRB,
output MAXIGP1WVALID,
inout [53: 0] MIO,
inout PSCLK,
inout PSPORB,
inout PSSRSTB,
input SAXIACPACLK,
input [31: 0] SAXIACPARADDR,
input [ 1: 0] SAXIACPARBURST,
input [ 3: 0] SAXIACPARCACHE,
output SAXIACPARESETN,
input [ 2: 0] SAXIACPARID,
input [ 3: 0] SAXIACPARLEN,
input [ 1: 0] SAXIACPARLOCK,
input [ 2: 0] SAXIACPARPROT,
input [ 3: 0] SAXIACPARQOS,
output SAXIACPARREADY,
input [ 1: 0] SAXIACPARSIZE,
input [ 4: 0] SAXIACPARUSER,
input SAXIACPARVALID,
input [31: 0] SAXIACPAWADDR,
input [ 1: 0] SAXIACPAWBURST,
input [ 3: 0] SAXIACPAWCACHE,
input [ 2: 0] SAXIACPAWID,
input [ 3: 0] SAXIACPAWLEN,
input [ 1: 0] SAXIACPAWLOCK,
input [ 2: 0] SAXIACPAWPROT,
input [ 3: 0] SAXIACPAWQOS,
output SAXIACPAWREADY,
input [ 1: 0] SAXIACPAWSIZE,
input [ 4: 0] SAXIACPAWUSER,
input SAXIACPAWVALID,
output [ 2: 0] SAXIACPBID,
input SAXIACPBREADY,
output [ 1: 0] SAXIACPBRESP,
output SAXIACPBVALID,
output [63: 0] SAXIACPRDATA,
output [ 2: 0] SAXIACPRID,
output SAXIACPRLAST,
input SAXIACPRREADY,
output [ 1: 0] SAXIACPRRESP,
output SAXIACPRVALID,
input [63: 0] SAXIACPWDATA,
input [ 2: 0] SAXIACPWID,
input SAXIACPWLAST,
output SAXIACPWREADY,
input [ 7: 0] SAXIACPWSTRB,
input SAXIACPWVALID,
input SAXIGP0ACLK,
input [31: 0] SAXIGP0ARADDR,
input [ 1: 0] SAXIGP0ARBURST,
input [ 3: 0] SAXIGP0ARCACHE,
output SAXIGP0ARESETN,
input [ 5: 0] SAXIGP0ARID,
input [ 3: 0] SAXIGP0ARLEN,
input [ 1: 0] SAXIGP0ARLOCK,
input [ 2: 0] SAXIGP0ARPROT,
input [ 3: 0] SAXIGP0ARQOS,
output SAXIGP0ARREADY,
input [ 1: 0] SAXIGP0ARSIZE,
input SAXIGP0ARVALID,
input [31: 0] SAXIGP0AWADDR,
input [ 1: 0] SAXIGP0AWBURST,
input [ 3: 0] SAXIGP0AWCACHE,
input [ 5: 0] SAXIGP0AWID,
input [ 3: 0] SAXIGP0AWLEN,
input [ 1: 0] SAXIGP0AWLOCK,
input [ 2: 0] SAXIGP0AWPROT,
input [ 3: 0] SAXIGP0AWQOS,
output SAXIGP0AWREADY,
input [ 1: 0] SAXIGP0AWSIZE,
input SAXIGP0AWVALID,
output [ 5: 0] SAXIGP0BID,
input SAXIGP0BREADY,
output [ 1: 0] SAXIGP0BRESP,
output SAXIGP0BVALID,
output [31: 0] SAXIGP0RDATA,
output [ 5: 0] SAXIGP0RID,
output SAXIGP0RLAST,
input SAXIGP0RREADY,
output [ 1: 0] SAXIGP0RRESP,
output SAXIGP0RVALID,
input [31: 0] SAXIGP0WDATA,
input [ 5: 0] SAXIGP0WID,
input SAXIGP0WLAST,
output SAXIGP0WREADY,
input [ 3: 0] SAXIGP0WSTRB,
input SAXIGP0WVALID,
input SAXIGP1ACLK,
input [31: 0] SAXIGP1ARADDR,
input [ 1: 0] SAXIGP1ARBURST,
input [ 3: 0] SAXIGP1ARCACHE,
output SAXIGP1ARESETN,
input [ 5: 0] SAXIGP1ARID,
input [ 3: 0] SAXIGP1ARLEN,
input [ 1: 0] SAXIGP1ARLOCK,
input [ 2: 0] SAXIGP1ARPROT,
input [ 3: 0] SAXIGP1ARQOS,
output SAXIGP1ARREADY,
input [ 1: 0] SAXIGP1ARSIZE,
input SAXIGP1ARVALID,
input [31: 0] SAXIGP1AWADDR,
input [ 1: 0] SAXIGP1AWBURST,
input [ 3: 0] SAXIGP1AWCACHE,
input [ 5: 0] SAXIGP1AWID,
input [ 3: 0] SAXIGP1AWLEN,
input [ 1: 0] SAXIGP1AWLOCK,
input [ 2: 0] SAXIGP1AWPROT,
input [ 3: 0] SAXIGP1AWQOS,
output SAXIGP1AWREADY,
input [ 1: 0] SAXIGP1AWSIZE,
input SAXIGP1AWVALID,
output [ 5: 0] SAXIGP1BID,
input SAXIGP1BREADY,
output [ 1: 0] SAXIGP1BRESP,
output SAXIGP1BVALID,
output [31: 0] SAXIGP1RDATA,
output [ 5: 0] SAXIGP1RID,
output SAXIGP1RLAST,
input SAXIGP1RREADY,
output [ 1: 0] SAXIGP1RRESP,
output SAXIGP1RVALID,
input [31: 0] SAXIGP1WDATA,
input [ 5: 0] SAXIGP1WID,
input SAXIGP1WLAST,
output SAXIGP1WREADY,
input [ 3: 0] SAXIGP1WSTRB,
input SAXIGP1WVALID,
input SAXIHP0ACLK,
input [31: 0] SAXIHP0ARADDR,
input [ 1: 0] SAXIHP0ARBURST,
input [ 3: 0] SAXIHP0ARCACHE,
output SAXIHP0ARESETN,
input [ 5: 0] SAXIHP0ARID,
input [ 3: 0] SAXIHP0ARLEN,
input [ 1: 0] SAXIHP0ARLOCK,
input [ 2: 0] SAXIHP0ARPROT,
input [ 3: 0] SAXIHP0ARQOS,
output SAXIHP0ARREADY,
input [ 1: 0] SAXIHP0ARSIZE,
input SAXIHP0ARVALID,
input [31: 0] SAXIHP0AWADDR,
input [ 1: 0] SAXIHP0AWBURST,
input [ 3: 0] SAXIHP0AWCACHE,
input [ 5: 0] SAXIHP0AWID,
input [ 3: 0] SAXIHP0AWLEN,
input [ 1: 0] SAXIHP0AWLOCK,
input [ 2: 0] SAXIHP0AWPROT,
input [ 3: 0] SAXIHP0AWQOS,
output SAXIHP0AWREADY,
input [ 1: 0] SAXIHP0AWSIZE,
input SAXIHP0AWVALID,
output [ 5: 0] SAXIHP0BID,
input SAXIHP0BREADY,
output [ 1: 0] SAXIHP0BRESP,
output SAXIHP0BVALID,
output [ 2: 0] SAXIHP0RACOUNT,
output [ 7: 0] SAXIHP0RCOUNT,
output [63: 0] SAXIHP0RDATA,
input SAXIHP0RDISSUECAP1EN,
output [ 5: 0] SAXIHP0RID,
output SAXIHP0RLAST,
input SAXIHP0RREADY,
output [ 1: 0] SAXIHP0RRESP,
output SAXIHP0RVALID,
output [ 5: 0] SAXIHP0WACOUNT,
output [ 7: 0] SAXIHP0WCOUNT,
input [63: 0] SAXIHP0WDATA,
input [ 5: 0] SAXIHP0WID,
input SAXIHP0WLAST,
output SAXIHP0WREADY,
input SAXIHP0WRISSUECAP1EN,
input [ 7: 0] SAXIHP0WSTRB,
input SAXIHP0WVALID,
input SAXIHP1ACLK,
input [31: 0] SAXIHP1ARADDR,
input [ 1: 0] SAXIHP1ARBURST,
input [ 3: 0] SAXIHP1ARCACHE,
output SAXIHP1ARESETN,
input [ 5: 0] SAXIHP1ARID,
input [ 3: 0] SAXIHP1ARLEN,
input [ 1: 0] SAXIHP1ARLOCK,
input [ 2: 0] SAXIHP1ARPROT,
input [ 3: 0] SAXIHP1ARQOS,
output SAXIHP1ARREADY,
input [ 1: 0] SAXIHP1ARSIZE,
input SAXIHP1ARVALID,
input [31: 0] SAXIHP1AWADDR,
input [ 1: 0] SAXIHP1AWBURST,
input [ 3: 0] SAXIHP1AWCACHE,
input [ 5: 0] SAXIHP1AWID,
input [ 3: 0] SAXIHP1AWLEN,
input [ 1: 0] SAXIHP1AWLOCK,
input [ 2: 0] SAXIHP1AWPROT,
input [ 3: 0] SAXIHP1AWQOS,
output SAXIHP1AWREADY,
input [ 1: 0] SAXIHP1AWSIZE,
input SAXIHP1AWVALID,
output [ 5: 0] SAXIHP1BID,
input SAXIHP1BREADY,
output [ 1: 0] SAXIHP1BRESP,
output SAXIHP1BVALID,
output [ 2: 0] SAXIHP1RACOUNT,
output [ 7: 0] SAXIHP1RCOUNT,
output [63: 0] SAXIHP1RDATA,
input SAXIHP1RDISSUECAP1EN,
output [ 5: 0] SAXIHP1RID,
output SAXIHP1RLAST,
input SAXIHP1RREADY,
output [ 1: 0] SAXIHP1RRESP,
output SAXIHP1RVALID,
output [ 5: 0] SAXIHP1WACOUNT,
output [ 7: 0] SAXIHP1WCOUNT,
input [63: 0] SAXIHP1WDATA,
input [ 5: 0] SAXIHP1WID,
input SAXIHP1WLAST,
output SAXIHP1WREADY,
input SAXIHP1WRISSUECAP1EN,
input [ 7: 0] SAXIHP1WSTRB,
input SAXIHP1WVALID,
input SAXIHP2ACLK,
input [31: 0] SAXIHP2ARADDR,
input [ 1: 0] SAXIHP2ARBURST,
input [ 3: 0] SAXIHP2ARCACHE,
output SAXIHP2ARESETN,
input [ 5: 0] SAXIHP2ARID,
input [ 3: 0] SAXIHP2ARLEN,
input [ 1: 0] SAXIHP2ARLOCK,
input [ 2: 0] SAXIHP2ARPROT,
input [ 3: 0] SAXIHP2ARQOS,
output SAXIHP2ARREADY,
input [ 1: 0] SAXIHP2ARSIZE,
input SAXIHP2ARVALID,
input [31: 0] SAXIHP2AWADDR,
input [ 1: 0] SAXIHP2AWBURST,
input [ 3: 0] SAXIHP2AWCACHE,
input [ 5: 0] SAXIHP2AWID,
input [ 3: 0] SAXIHP2AWLEN,
input [ 1: 0] SAXIHP2AWLOCK,
input [ 2: 0] SAXIHP2AWPROT,
input [ 3: 0] SAXIHP2AWQOS,
output SAXIHP2AWREADY,
input [ 1: 0] SAXIHP2AWSIZE,
input SAXIHP2AWVALID,
output [ 5: 0] SAXIHP2BID,
input SAXIHP2BREADY,
output [ 1: 0] SAXIHP2BRESP,
output SAXIHP2BVALID,
output [ 2: 0] SAXIHP2RACOUNT,
output [ 7: 0] SAXIHP2RCOUNT,
output [63: 0] SAXIHP2RDATA,
input SAXIHP2RDISSUECAP1EN,
output [ 5: 0] SAXIHP2RID,
output SAXIHP2RLAST,
input SAXIHP2RREADY,
output [ 1: 0] SAXIHP2RRESP,
output SAXIHP2RVALID,
output [ 5: 0] SAXIHP2WACOUNT,
output [ 7: 0] SAXIHP2WCOUNT,
input [63: 0] SAXIHP2WDATA,
input [ 5: 0] SAXIHP2WID,
input SAXIHP2WLAST,
output SAXIHP2WREADY,
input SAXIHP2WRISSUECAP1EN,
input [ 7: 0] SAXIHP2WSTRB,
input SAXIHP2WVALID,
input SAXIHP3ACLK,
input [31: 0] SAXIHP3ARADDR,
input [ 1: 0] SAXIHP3ARBURST,
input [ 3: 0] SAXIHP3ARCACHE,
output SAXIHP3ARESETN,
input [ 5: 0] SAXIHP3ARID,
input [ 3: 0] SAXIHP3ARLEN,
input [ 1: 0] SAXIHP3ARLOCK,
input [ 2: 0] SAXIHP3ARPROT,
input [ 3: 0] SAXIHP3ARQOS,
output SAXIHP3ARREADY,
input [ 1: 0] SAXIHP3ARSIZE,
input SAXIHP3ARVALID,
input [31: 0] SAXIHP3AWADDR,
input [ 1: 0] SAXIHP3AWBURST,
input [ 3: 0] SAXIHP3AWCACHE,
input [ 5: 0] SAXIHP3AWID,
input [ 3: 0] SAXIHP3AWLEN,
input [ 1: 0] SAXIHP3AWLOCK,
input [ 2: 0] SAXIHP3AWPROT,
input [ 3: 0] SAXIHP3AWQOS,
output SAXIHP3AWREADY,
input [ 1: 0] SAXIHP3AWSIZE,
input SAXIHP3AWVALID,
output [ 5: 0] SAXIHP3BID,
input SAXIHP3BREADY,
output [ 1: 0] SAXIHP3BRESP,
output SAXIHP3BVALID,
output [ 2: 0] SAXIHP3RACOUNT,
output [ 7: 0] SAXIHP3RCOUNT,
output [63: 0] SAXIHP3RDATA,
input SAXIHP3RDISSUECAP1EN,
output [ 5: 0] SAXIHP3RID,
output SAXIHP3RLAST,
input SAXIHP3RREADY,
output [ 1: 0] SAXIHP3RRESP,
output SAXIHP3RVALID,
output [ 5: 0] SAXIHP3WACOUNT,
output [ 7: 0] SAXIHP3WCOUNT,
input [63: 0] SAXIHP3WDATA,
input [ 5: 0] SAXIHP3WID,
input SAXIHP3WLAST,
output SAXIHP3WREADY,
input SAXIHP3WRISSUECAP1EN,
input [ 7: 0] SAXIHP3WSTRB,
input SAXIHP3WVALID
);
// Techmap specific parameters.
parameter _TECHMAP_CONSTMSK_DDRARB_ = 0;
parameter _TECHMAP_CONSTVAL_DDRARB_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0DAREADY_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0DAREADY_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0DRLAST_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0DRLAST_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0DRTYPE_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0DRTYPE_ = 0;
parameter _TECHMAP_CONSTMSK_DMA0DRVALID_ = 0;
parameter _TECHMAP_CONSTVAL_DMA0DRVALID_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1DAREADY_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1DAREADY_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1DRLAST_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1DRLAST_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1DRTYPE_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1DRTYPE_ = 0;
parameter _TECHMAP_CONSTMSK_DMA1DRVALID_ = 0;
parameter _TECHMAP_CONSTVAL_DMA1DRVALID_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2DAREADY_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2DAREADY_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2DRLAST_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2DRLAST_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2DRTYPE_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2DRTYPE_ = 0;
parameter _TECHMAP_CONSTMSK_DMA2DRVALID_ = 0;
parameter _TECHMAP_CONSTVAL_DMA2DRVALID_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3DAREADY_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3DAREADY_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3DRLAST_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3DRLAST_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3DRTYPE_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3DRTYPE_ = 0;
parameter _TECHMAP_CONSTMSK_DMA3DRVALID_ = 0;
parameter _TECHMAP_CONSTVAL_DMA3DRVALID_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOCAN0PHYRX_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOCAN0PHYRX_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOCAN1PHYRX_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOCAN1PHYRX_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0EXTINTIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0EXTINTIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIICOL_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIICOL_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIICRS_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIICRS_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIIRXCLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIIRXCLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIIRXD_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIIRXD_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIIRXDV_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIIRXDV_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIIRXER_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIIRXER_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0GMIITXCLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0GMIITXCLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET0MDIOI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET0MDIOI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1EXTINTIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1EXTINTIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIICOL_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIICOL_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIICRS_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIICRS_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIIRXCLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIIRXCLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIIRXD_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIIRXD_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIIRXDV_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIIRXDV_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIIRXER_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIIRXER_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1GMIITXCLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1GMIITXCLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOENET1MDIOI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOENET1MDIOI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOGPIOI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOGPIOI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOI2C0SCLI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOI2C0SCLI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOI2C0SDAI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOI2C0SDAI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOI2C1SCLI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOI2C1SCLI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOI2C1SDAI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOI2C1SDAI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOPJTAGTCK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOPJTAGTCK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOPJTAGTDI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOPJTAGTDI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOPJTAGTMS_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOPJTAGTMS_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0CDN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0CDN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0CLKFB_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0CLKFB_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0CMDI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0CMDI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0DATAI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0DATAI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO0WP_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO0WP_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1CDN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1CDN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1CLKFB_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1CLKFB_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1CMDI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1CMDI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1DATAI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1DATAI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSDIO1WP_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSDIO1WP_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI0MI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI0MI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI0SCLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI0SCLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI0SI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI0SI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI0SSIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI0SSIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI1MI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI1MI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI1SCLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI1SCLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI1SI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI1SI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSPI1SSIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSPI1SSIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOSRAMINTIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOSRAMINTIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOTRACECLK_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOTRACECLK_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOTTC0CLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOTTC0CLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOTTC1CLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOTTC1CLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0CTSN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0CTSN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0DCDN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0DCDN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0DSRN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0DSRN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0RIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0RIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART0RX_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART0RX_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1CTSN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1CTSN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1DCDN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1DCDN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1DSRN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1DSRN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1RIN_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1RIN_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUART1RX_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUART1RX_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUSB0VBUSPWRFAULT_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUSB0VBUSPWRFAULT_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOUSB1VBUSPWRFAULT_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOUSB1VBUSPWRFAULT_ = 0;
parameter _TECHMAP_CONSTMSK_EMIOWDTCLKI_ = 0;
parameter _TECHMAP_CONSTVAL_EMIOWDTCLKI_ = 0;
parameter _TECHMAP_CONSTMSK_EVENTEVENTI_ = 0;
parameter _TECHMAP_CONSTVAL_EVENTEVENTI_ = 0;
parameter _TECHMAP_CONSTMSK_FCLKCLKTRIGN_ = 0;
parameter _TECHMAP_CONSTVAL_FCLKCLKTRIGN_ = 0;
parameter _TECHMAP_CONSTMSK_FPGAIDLEN_ = 0;
parameter _TECHMAP_CONSTVAL_FPGAIDLEN_ = 0;
parameter _TECHMAP_CONSTMSK_FTMDTRACEINATID_ = 0;
parameter _TECHMAP_CONSTVAL_FTMDTRACEINATID_ = 0;
parameter _TECHMAP_CONSTMSK_FTMDTRACEINCLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_FTMDTRACEINCLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_FTMDTRACEINDATA_ = 0;
parameter _TECHMAP_CONSTVAL_FTMDTRACEINDATA_ = 0;
parameter _TECHMAP_CONSTMSK_FTMDTRACEINVALID_ = 0;
parameter _TECHMAP_CONSTVAL_FTMDTRACEINVALID_ = 0;
parameter _TECHMAP_CONSTMSK_FTMTF2PDEBUG_ = 0;
parameter _TECHMAP_CONSTVAL_FTMTF2PDEBUG_ = 0;
parameter _TECHMAP_CONSTMSK_FTMTF2PTRIG_ = 0;
parameter _TECHMAP_CONSTVAL_FTMTF2PTRIG_ = 0;
parameter _TECHMAP_CONSTMSK_FTMTP2FTRIGACK_ = 0;
parameter _TECHMAP_CONSTVAL_FTMTP2FTRIGACK_ = 0;
parameter _TECHMAP_CONSTMSK_IRQF2P_ = 0;
parameter _TECHMAP_CONSTVAL_IRQF2P_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0ARREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0ARREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0AWREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0AWREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0BID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0BID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0BRESP_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0BRESP_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0BVALID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0BVALID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RDATA_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RDATA_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RLAST_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RLAST_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RRESP_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RRESP_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0RVALID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0RVALID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP0WREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP0WREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1ARREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1ARREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1AWREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1AWREADY_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1BID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1BID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1BRESP_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1BRESP_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1BVALID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1BVALID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RDATA_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RDATA_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RLAST_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RLAST_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RRESP_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RRESP_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1RVALID_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1RVALID_ = 0;
parameter _TECHMAP_CONSTMSK_MAXIGP1WREADY_ = 0;
parameter _TECHMAP_CONSTVAL_MAXIGP1WREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARUSER_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARUSER_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWUSER_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWUSER_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPAWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPAWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPBREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPBREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPRREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPRREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIACPWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIACPWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP0WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP0WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIGP1WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIGP1WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP0WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP0WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP1WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP1WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP2WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP2WVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ACLK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ACLK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3ARVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3ARVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWADDR_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWADDR_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWBURST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWBURST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWCACHE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWCACHE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWLEN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWLEN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWLOCK_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWLOCK_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWPROT_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWPROT_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWQOS_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWQOS_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWSIZE_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWSIZE_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3AWVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3AWVALID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3BREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3BREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3RDISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3RREADY_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3RREADY_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WDATA_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WDATA_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WID_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WLAST_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WLAST_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WRISSUECAP1EN_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WSTRB_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WSTRB_ = 0;
parameter _TECHMAP_CONSTMSK_SAXIHP3WVALID_ = 0;
parameter _TECHMAP_CONSTVAL_SAXIHP3WVALID_ = 0;
// Detect all unconnected inputs and tie them to 0.
wire [3:0] ddrarb = (_TECHMAP_CONSTMSK_DDRARB_ == 4'd0 && _TECHMAP_CONSTVAL_DDRARB_ === 4'd0) ? 4'b0 : DDRARB;
wire [0:0] dma0aclk = (_TECHMAP_CONSTMSK_DMA0ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_DMA0ACLK_ === 1'd0) ? 1'b0 : DMA0ACLK;
wire [0:0] dma0daready = (_TECHMAP_CONSTMSK_DMA0DAREADY_ == 1'd0 && _TECHMAP_CONSTVAL_DMA0DAREADY_ === 1'd0) ? 1'b0 : DMA0DAREADY;
wire [0:0] dma0drlast = (_TECHMAP_CONSTMSK_DMA0DRLAST_ == 1'd0 && _TECHMAP_CONSTVAL_DMA0DRLAST_ === 1'd0) ? 1'b0 : DMA0DRLAST;
wire [1:0] dma0drtype = (_TECHMAP_CONSTMSK_DMA0DRTYPE_ == 2'd0 && _TECHMAP_CONSTVAL_DMA0DRTYPE_ === 2'd0) ? 2'b0 : DMA0DRTYPE;
wire [0:0] dma0drvalid = (_TECHMAP_CONSTMSK_DMA0DRVALID_ == 1'd0 && _TECHMAP_CONSTVAL_DMA0DRVALID_ === 1'd0) ? 1'b0 : DMA0DRVALID;
wire [0:0] dma1aclk = (_TECHMAP_CONSTMSK_DMA1ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_DMA1ACLK_ === 1'd0) ? 1'b0 : DMA1ACLK;
wire [0:0] dma1daready = (_TECHMAP_CONSTMSK_DMA1DAREADY_ == 1'd0 && _TECHMAP_CONSTVAL_DMA1DAREADY_ === 1'd0) ? 1'b0 : DMA1DAREADY;
wire [0:0] dma1drlast = (_TECHMAP_CONSTMSK_DMA1DRLAST_ == 1'd0 && _TECHMAP_CONSTVAL_DMA1DRLAST_ === 1'd0) ? 1'b0 : DMA1DRLAST;
wire [1:0] dma1drtype = (_TECHMAP_CONSTMSK_DMA1DRTYPE_ == 2'd0 && _TECHMAP_CONSTVAL_DMA1DRTYPE_ === 2'd0) ? 2'b0 : DMA1DRTYPE;
wire [0:0] dma1drvalid = (_TECHMAP_CONSTMSK_DMA1DRVALID_ == 1'd0 && _TECHMAP_CONSTVAL_DMA1DRVALID_ === 1'd0) ? 1'b0 : DMA1DRVALID;
wire [0:0] dma2aclk = (_TECHMAP_CONSTMSK_DMA2ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_DMA2ACLK_ === 1'd0) ? 1'b0 : DMA2ACLK;
wire [0:0] dma2daready = (_TECHMAP_CONSTMSK_DMA2DAREADY_ == 1'd0 && _TECHMAP_CONSTVAL_DMA2DAREADY_ === 1'd0) ? 1'b0 : DMA2DAREADY;
wire [0:0] dma2drlast = (_TECHMAP_CONSTMSK_DMA2DRLAST_ == 1'd0 && _TECHMAP_CONSTVAL_DMA2DRLAST_ === 1'd0) ? 1'b0 : DMA2DRLAST;
wire [1:0] dma2drtype = (_TECHMAP_CONSTMSK_DMA2DRTYPE_ == 2'd0 && _TECHMAP_CONSTVAL_DMA2DRTYPE_ === 2'd0) ? 2'b0 : DMA2DRTYPE;
wire [0:0] dma2drvalid = (_TECHMAP_CONSTMSK_DMA2DRVALID_ == 1'd0 && _TECHMAP_CONSTVAL_DMA2DRVALID_ === 1'd0) ? 1'b0 : DMA2DRVALID;
wire [0:0] dma3aclk = (_TECHMAP_CONSTMSK_DMA3ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_DMA3ACLK_ === 1'd0) ? 1'b0 : DMA3ACLK;
wire [0:0] dma3daready = (_TECHMAP_CONSTMSK_DMA3DAREADY_ == 1'd0 && _TECHMAP_CONSTVAL_DMA3DAREADY_ === 1'd0) ? 1'b0 : DMA3DAREADY;
wire [0:0] dma3drlast = (_TECHMAP_CONSTMSK_DMA3DRLAST_ == 1'd0 && _TECHMAP_CONSTVAL_DMA3DRLAST_ === 1'd0) ? 1'b0 : DMA3DRLAST;
wire [1:0] dma3drtype = (_TECHMAP_CONSTMSK_DMA3DRTYPE_ == 2'd0 && _TECHMAP_CONSTVAL_DMA3DRTYPE_ === 2'd0) ? 2'b0 : DMA3DRTYPE;
wire [0:0] dma3drvalid = (_TECHMAP_CONSTMSK_DMA3DRVALID_ == 1'd0 && _TECHMAP_CONSTVAL_DMA3DRVALID_ === 1'd0) ? 1'b0 : DMA3DRVALID;
wire [0:0] emiocan0phyrx = (_TECHMAP_CONSTMSK_EMIOCAN0PHYRX_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOCAN0PHYRX_ === 1'd0) ? 1'b0 : EMIOCAN0PHYRX;
wire [0:0] emiocan1phyrx = (_TECHMAP_CONSTMSK_EMIOCAN1PHYRX_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOCAN1PHYRX_ === 1'd0) ? 1'b0 : EMIOCAN1PHYRX;
wire [0:0] emioenet0extintin = (_TECHMAP_CONSTMSK_EMIOENET0EXTINTIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0EXTINTIN_ === 1'd0) ? 1'b0 : EMIOENET0EXTINTIN;
wire [0:0] emioenet0gmiicol = (_TECHMAP_CONSTMSK_EMIOENET0GMIICOL_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIICOL_ === 1'd0) ? 1'b0 : EMIOENET0GMIICOL;
wire [0:0] emioenet0gmiicrs = (_TECHMAP_CONSTMSK_EMIOENET0GMIICRS_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIICRS_ === 1'd0) ? 1'b0 : EMIOENET0GMIICRS;
wire [0:0] emioenet0gmiirxclk = (_TECHMAP_CONSTMSK_EMIOENET0GMIIRXCLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIIRXCLK_ === 1'd0) ? 1'b0 : EMIOENET0GMIIRXCLK;
wire [7:0] emioenet0gmiirxd = (_TECHMAP_CONSTMSK_EMIOENET0GMIIRXD_ == 8'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIIRXD_ === 8'd0) ? 8'b0 : EMIOENET0GMIIRXD;
wire [0:0] emioenet0gmiirxdv = (_TECHMAP_CONSTMSK_EMIOENET0GMIIRXDV_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIIRXDV_ === 1'd0) ? 1'b0 : EMIOENET0GMIIRXDV;
wire [0:0] emioenet0gmiirxer = (_TECHMAP_CONSTMSK_EMIOENET0GMIIRXER_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIIRXER_ === 1'd0) ? 1'b0 : EMIOENET0GMIIRXER;
wire [0:0] emioenet0gmiitxclk = (_TECHMAP_CONSTMSK_EMIOENET0GMIITXCLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0GMIITXCLK_ === 1'd0) ? 1'b0 : EMIOENET0GMIITXCLK;
wire [0:0] emioenet0mdioi = (_TECHMAP_CONSTMSK_EMIOENET0MDIOI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET0MDIOI_ === 1'd0) ? 1'b0 : EMIOENET0MDIOI;
wire [0:0] emioenet1extintin = (_TECHMAP_CONSTMSK_EMIOENET1EXTINTIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1EXTINTIN_ === 1'd0) ? 1'b0 : EMIOENET1EXTINTIN;
wire [0:0] emioenet1gmiicol = (_TECHMAP_CONSTMSK_EMIOENET1GMIICOL_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIICOL_ === 1'd0) ? 1'b0 : EMIOENET1GMIICOL;
wire [0:0] emioenet1gmiicrs = (_TECHMAP_CONSTMSK_EMIOENET1GMIICRS_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIICRS_ === 1'd0) ? 1'b0 : EMIOENET1GMIICRS;
wire [0:0] emioenet1gmiirxclk = (_TECHMAP_CONSTMSK_EMIOENET1GMIIRXCLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIIRXCLK_ === 1'd0) ? 1'b0 : EMIOENET1GMIIRXCLK;
wire [7:0] emioenet1gmiirxd = (_TECHMAP_CONSTMSK_EMIOENET1GMIIRXD_ == 8'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIIRXD_ === 8'd0) ? 8'b0 : EMIOENET1GMIIRXD;
wire [0:0] emioenet1gmiirxdv = (_TECHMAP_CONSTMSK_EMIOENET1GMIIRXDV_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIIRXDV_ === 1'd0) ? 1'b0 : EMIOENET1GMIIRXDV;
wire [0:0] emioenet1gmiirxer = (_TECHMAP_CONSTMSK_EMIOENET1GMIIRXER_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIIRXER_ === 1'd0) ? 1'b0 : EMIOENET1GMIIRXER;
wire [0:0] emioenet1gmiitxclk = (_TECHMAP_CONSTMSK_EMIOENET1GMIITXCLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1GMIITXCLK_ === 1'd0) ? 1'b0 : EMIOENET1GMIITXCLK;
wire [0:0] emioenet1mdioi = (_TECHMAP_CONSTMSK_EMIOENET1MDIOI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOENET1MDIOI_ === 1'd0) ? 1'b0 : EMIOENET1MDIOI;
wire [63:0] emiogpioi = (_TECHMAP_CONSTMSK_EMIOGPIOI_ == 64'd0 && _TECHMAP_CONSTVAL_EMIOGPIOI_ === 64'd0) ? 64'b0 : EMIOGPIOI;
wire [0:0] emioi2c0scli = (_TECHMAP_CONSTMSK_EMIOI2C0SCLI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOI2C0SCLI_ === 1'd0) ? 1'b0 : EMIOI2C0SCLI;
wire [0:0] emioi2c0sdai = (_TECHMAP_CONSTMSK_EMIOI2C0SDAI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOI2C0SDAI_ === 1'd0) ? 1'b0 : EMIOI2C0SDAI;
wire [0:0] emioi2c1scli = (_TECHMAP_CONSTMSK_EMIOI2C1SCLI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOI2C1SCLI_ === 1'd0) ? 1'b0 : EMIOI2C1SCLI;
wire [0:0] emioi2c1sdai = (_TECHMAP_CONSTMSK_EMIOI2C1SDAI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOI2C1SDAI_ === 1'd0) ? 1'b0 : EMIOI2C1SDAI;
wire [0:0] emiopjtagtck = (_TECHMAP_CONSTMSK_EMIOPJTAGTCK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOPJTAGTCK_ === 1'd0) ? 1'b0 : EMIOPJTAGTCK;
wire [0:0] emiopjtagtdi = (_TECHMAP_CONSTMSK_EMIOPJTAGTDI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOPJTAGTDI_ === 1'd0) ? 1'b0 : EMIOPJTAGTDI;
wire [0:0] emiopjtagtms = (_TECHMAP_CONSTMSK_EMIOPJTAGTMS_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOPJTAGTMS_ === 1'd0) ? 1'b0 : EMIOPJTAGTMS;
wire [0:0] emiosdio0cdn = (_TECHMAP_CONSTMSK_EMIOSDIO0CDN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0CDN_ === 1'd0) ? 1'b0 : EMIOSDIO0CDN;
wire [0:0] emiosdio0clkfb = (_TECHMAP_CONSTMSK_EMIOSDIO0CLKFB_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0CLKFB_ === 1'd0) ? 1'b0 : EMIOSDIO0CLKFB;
wire [0:0] emiosdio0cmdi = (_TECHMAP_CONSTMSK_EMIOSDIO0CMDI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0CMDI_ === 1'd0) ? 1'b0 : EMIOSDIO0CMDI;
wire [3:0] emiosdio0datai = (_TECHMAP_CONSTMSK_EMIOSDIO0DATAI_ == 4'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0DATAI_ === 4'd0) ? 4'b0 : EMIOSDIO0DATAI;
wire [0:0] emiosdio0wp = (_TECHMAP_CONSTMSK_EMIOSDIO0WP_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO0WP_ === 1'd0) ? 1'b0 : EMIOSDIO0WP;
wire [0:0] emiosdio1cdn = (_TECHMAP_CONSTMSK_EMIOSDIO1CDN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1CDN_ === 1'd0) ? 1'b0 : EMIOSDIO1CDN;
wire [0:0] emiosdio1clkfb = (_TECHMAP_CONSTMSK_EMIOSDIO1CLKFB_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1CLKFB_ === 1'd0) ? 1'b0 : EMIOSDIO1CLKFB;
wire [0:0] emiosdio1cmdi = (_TECHMAP_CONSTMSK_EMIOSDIO1CMDI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1CMDI_ === 1'd0) ? 1'b0 : EMIOSDIO1CMDI;
wire [3:0] emiosdio1datai = (_TECHMAP_CONSTMSK_EMIOSDIO1DATAI_ == 4'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1DATAI_ === 4'd0) ? 4'b0 : EMIOSDIO1DATAI;
wire [0:0] emiosdio1wp = (_TECHMAP_CONSTMSK_EMIOSDIO1WP_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSDIO1WP_ === 1'd0) ? 1'b0 : EMIOSDIO1WP;
wire [0:0] emiospi0mi = (_TECHMAP_CONSTMSK_EMIOSPI0MI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI0MI_ === 1'd0) ? 1'b0 : EMIOSPI0MI;
wire [0:0] emiospi0sclki = (_TECHMAP_CONSTMSK_EMIOSPI0SCLKI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI0SCLKI_ === 1'd0) ? 1'b0 : EMIOSPI0SCLKI;
wire [0:0] emiospi0si = (_TECHMAP_CONSTMSK_EMIOSPI0SI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI0SI_ === 1'd0) ? 1'b0 : EMIOSPI0SI;
wire [0:0] emiospi0ssin = (_TECHMAP_CONSTMSK_EMIOSPI0SSIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI0SSIN_ === 1'd0) ? 1'b0 : EMIOSPI0SSIN;
wire [0:0] emiospi1mi = (_TECHMAP_CONSTMSK_EMIOSPI1MI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI1MI_ === 1'd0) ? 1'b0 : EMIOSPI1MI;
wire [0:0] emiospi1sclki = (_TECHMAP_CONSTMSK_EMIOSPI1SCLKI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI1SCLKI_ === 1'd0) ? 1'b0 : EMIOSPI1SCLKI;
wire [0:0] emiospi1si = (_TECHMAP_CONSTMSK_EMIOSPI1SI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI1SI_ === 1'd0) ? 1'b0 : EMIOSPI1SI;
wire [0:0] emiospi1ssin = (_TECHMAP_CONSTMSK_EMIOSPI1SSIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSPI1SSIN_ === 1'd0) ? 1'b0 : EMIOSPI1SSIN;
wire [0:0] emiosramintin = (_TECHMAP_CONSTMSK_EMIOSRAMINTIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOSRAMINTIN_ === 1'd0) ? 1'b0 : EMIOSRAMINTIN;
wire [0:0] emiotraceclk = (_TECHMAP_CONSTMSK_EMIOTRACECLK_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOTRACECLK_ === 1'd0) ? 1'b0 : EMIOTRACECLK;
wire [2:0] emiottc0clki = (_TECHMAP_CONSTMSK_EMIOTTC0CLKI_ == 3'd0 && _TECHMAP_CONSTVAL_EMIOTTC0CLKI_ === 3'd0) ? 3'b0 : EMIOTTC0CLKI;
wire [2:0] emiottc1clki = (_TECHMAP_CONSTMSK_EMIOTTC1CLKI_ == 3'd0 && _TECHMAP_CONSTVAL_EMIOTTC1CLKI_ === 3'd0) ? 3'b0 : EMIOTTC1CLKI;
wire [0:0] emiouart0ctsn = (_TECHMAP_CONSTMSK_EMIOUART0CTSN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0CTSN_ === 1'd0) ? 1'b0 : EMIOUART0CTSN;
wire [0:0] emiouart0dcdn = (_TECHMAP_CONSTMSK_EMIOUART0DCDN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0DCDN_ === 1'd0) ? 1'b0 : EMIOUART0DCDN;
wire [0:0] emiouart0dsrn = (_TECHMAP_CONSTMSK_EMIOUART0DSRN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0DSRN_ === 1'd0) ? 1'b0 : EMIOUART0DSRN;
wire [0:0] emiouart0rin = (_TECHMAP_CONSTMSK_EMIOUART0RIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0RIN_ === 1'd0) ? 1'b0 : EMIOUART0RIN;
wire [0:0] emiouart0rx = (_TECHMAP_CONSTMSK_EMIOUART0RX_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART0RX_ === 1'd0) ? 1'b0 : EMIOUART0RX;
wire [0:0] emiouart1ctsn = (_TECHMAP_CONSTMSK_EMIOUART1CTSN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1CTSN_ === 1'd0) ? 1'b0 : EMIOUART1CTSN;
wire [0:0] emiouart1dcdn = (_TECHMAP_CONSTMSK_EMIOUART1DCDN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1DCDN_ === 1'd0) ? 1'b0 : EMIOUART1DCDN;
wire [0:0] emiouart1dsrn = (_TECHMAP_CONSTMSK_EMIOUART1DSRN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1DSRN_ === 1'd0) ? 1'b0 : EMIOUART1DSRN;
wire [0:0] emiouart1rin = (_TECHMAP_CONSTMSK_EMIOUART1RIN_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1RIN_ === 1'd0) ? 1'b0 : EMIOUART1RIN;
wire [0:0] emiouart1rx = (_TECHMAP_CONSTMSK_EMIOUART1RX_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUART1RX_ === 1'd0) ? 1'b0 : EMIOUART1RX;
wire [0:0] emiousb0vbuspwrfault = (_TECHMAP_CONSTMSK_EMIOUSB0VBUSPWRFAULT_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUSB0VBUSPWRFAULT_ === 1'd0) ? 1'b0 : EMIOUSB0VBUSPWRFAULT;
wire [0:0] emiousb1vbuspwrfault = (_TECHMAP_CONSTMSK_EMIOUSB1VBUSPWRFAULT_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOUSB1VBUSPWRFAULT_ === 1'd0) ? 1'b0 : EMIOUSB1VBUSPWRFAULT;
wire [0:0] emiowdtclki = (_TECHMAP_CONSTMSK_EMIOWDTCLKI_ == 1'd0 && _TECHMAP_CONSTVAL_EMIOWDTCLKI_ === 1'd0) ? 1'b0 : EMIOWDTCLKI;
wire [0:0] eventeventi = (_TECHMAP_CONSTMSK_EVENTEVENTI_ == 1'd0 && _TECHMAP_CONSTVAL_EVENTEVENTI_ === 1'd0) ? 1'b0 : EVENTEVENTI;
wire [3:0] fclkclktrign = (_TECHMAP_CONSTMSK_FCLKCLKTRIGN_ == 4'd0 && _TECHMAP_CONSTVAL_FCLKCLKTRIGN_ === 4'd0) ? 4'b0 : FCLKCLKTRIGN;
wire [0:0] fpgaidlen = (_TECHMAP_CONSTMSK_FPGAIDLEN_ == 1'd0 && _TECHMAP_CONSTVAL_FPGAIDLEN_ === 1'd0) ? 1'b0 : FPGAIDLEN;
wire [3:0] ftmdtraceinatid = (_TECHMAP_CONSTMSK_FTMDTRACEINATID_ == 4'd0 && _TECHMAP_CONSTVAL_FTMDTRACEINATID_ === 4'd0) ? 4'b0 : FTMDTRACEINATID;
wire [0:0] ftmdtraceinclock = (_TECHMAP_CONSTMSK_FTMDTRACEINCLOCK_ == 1'd0 && _TECHMAP_CONSTVAL_FTMDTRACEINCLOCK_ === 1'd0) ? 1'b0 : FTMDTRACEINCLOCK;
wire [31:0] ftmdtraceindata = (_TECHMAP_CONSTMSK_FTMDTRACEINDATA_ == 32'd0 && _TECHMAP_CONSTVAL_FTMDTRACEINDATA_ === 32'd0) ? 32'b0 : FTMDTRACEINDATA;
wire [0:0] ftmdtraceinvalid = (_TECHMAP_CONSTMSK_FTMDTRACEINVALID_ == 1'd0 && _TECHMAP_CONSTVAL_FTMDTRACEINVALID_ === 1'd0) ? 1'b0 : FTMDTRACEINVALID;
wire [31:0] ftmtf2pdebug = (_TECHMAP_CONSTMSK_FTMTF2PDEBUG_ == 32'd0 && _TECHMAP_CONSTVAL_FTMTF2PDEBUG_ === 32'd0) ? 32'b0 : FTMTF2PDEBUG;
wire [3:0] ftmtf2ptrig = (_TECHMAP_CONSTMSK_FTMTF2PTRIG_ == 4'd0 && _TECHMAP_CONSTVAL_FTMTF2PTRIG_ === 4'd0) ? 4'b0 : FTMTF2PTRIG;
wire [3:0] ftmtp2ftrigack = (_TECHMAP_CONSTMSK_FTMTP2FTRIGACK_ == 4'd0 && _TECHMAP_CONSTVAL_FTMTP2FTRIGACK_ === 4'd0) ? 4'b0 : FTMTP2FTRIGACK;
wire [19:0] irqf2p = (_TECHMAP_CONSTMSK_IRQF2P_ == 20'd0 && _TECHMAP_CONSTVAL_IRQF2P_ === 20'd0) ? 20'b0 : IRQF2P;
wire [0:0] maxigp0aclk = (_TECHMAP_CONSTMSK_MAXIGP0ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0ACLK_ === 1'd0) ? 1'b0 : MAXIGP0ACLK;
wire [0:0] maxigp0arready = (_TECHMAP_CONSTMSK_MAXIGP0ARREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0ARREADY_ === 1'd0) ? 1'b0 : MAXIGP0ARREADY;
wire [0:0] maxigp0awready = (_TECHMAP_CONSTMSK_MAXIGP0AWREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0AWREADY_ === 1'd0) ? 1'b0 : MAXIGP0AWREADY;
wire [11:0] maxigp0bid = (_TECHMAP_CONSTMSK_MAXIGP0BID_ == 12'd0 && _TECHMAP_CONSTVAL_MAXIGP0BID_ === 12'd0) ? 12'b0 : MAXIGP0BID;
wire [1:0] maxigp0bresp = (_TECHMAP_CONSTMSK_MAXIGP0BRESP_ == 2'd0 && _TECHMAP_CONSTVAL_MAXIGP0BRESP_ === 2'd0) ? 2'b0 : MAXIGP0BRESP;
wire [0:0] maxigp0bvalid = (_TECHMAP_CONSTMSK_MAXIGP0BVALID_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0BVALID_ === 1'd0) ? 1'b0 : MAXIGP0BVALID;
wire [31:0] maxigp0rdata = (_TECHMAP_CONSTMSK_MAXIGP0RDATA_ == 32'd0 && _TECHMAP_CONSTVAL_MAXIGP0RDATA_ === 32'd0) ? 32'b0 : MAXIGP0RDATA;
wire [11:0] maxigp0rid = (_TECHMAP_CONSTMSK_MAXIGP0RID_ == 12'd0 && _TECHMAP_CONSTVAL_MAXIGP0RID_ === 12'd0) ? 12'b0 : MAXIGP0RID;
wire [0:0] maxigp0rlast = (_TECHMAP_CONSTMSK_MAXIGP0RLAST_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0RLAST_ === 1'd0) ? 1'b0 : MAXIGP0RLAST;
wire [1:0] maxigp0rresp = (_TECHMAP_CONSTMSK_MAXIGP0RRESP_ == 2'd0 && _TECHMAP_CONSTVAL_MAXIGP0RRESP_ === 2'd0) ? 2'b0 : MAXIGP0RRESP;
wire [0:0] maxigp0rvalid = (_TECHMAP_CONSTMSK_MAXIGP0RVALID_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0RVALID_ === 1'd0) ? 1'b0 : MAXIGP0RVALID;
wire [0:0] maxigp0wready = (_TECHMAP_CONSTMSK_MAXIGP0WREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP0WREADY_ === 1'd0) ? 1'b0 : MAXIGP0WREADY;
wire [0:0] maxigp1aclk = (_TECHMAP_CONSTMSK_MAXIGP1ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1ACLK_ === 1'd0) ? 1'b0 : MAXIGP1ACLK;
wire [0:0] maxigp1arready = (_TECHMAP_CONSTMSK_MAXIGP1ARREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1ARREADY_ === 1'd0) ? 1'b0 : MAXIGP1ARREADY;
wire [0:0] maxigp1awready = (_TECHMAP_CONSTMSK_MAXIGP1AWREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1AWREADY_ === 1'd0) ? 1'b0 : MAXIGP1AWREADY;
wire [11:0] maxigp1bid = (_TECHMAP_CONSTMSK_MAXIGP1BID_ == 12'd0 && _TECHMAP_CONSTVAL_MAXIGP1BID_ === 12'd0) ? 12'b0 : MAXIGP1BID;
wire [1:0] maxigp1bresp = (_TECHMAP_CONSTMSK_MAXIGP1BRESP_ == 2'd0 && _TECHMAP_CONSTVAL_MAXIGP1BRESP_ === 2'd0) ? 2'b0 : MAXIGP1BRESP;
wire [0:0] maxigp1bvalid = (_TECHMAP_CONSTMSK_MAXIGP1BVALID_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1BVALID_ === 1'd0) ? 1'b0 : MAXIGP1BVALID;
wire [31:0] maxigp1rdata = (_TECHMAP_CONSTMSK_MAXIGP1RDATA_ == 32'd0 && _TECHMAP_CONSTVAL_MAXIGP1RDATA_ === 32'd0) ? 32'b0 : MAXIGP1RDATA;
wire [11:0] maxigp1rid = (_TECHMAP_CONSTMSK_MAXIGP1RID_ == 12'd0 && _TECHMAP_CONSTVAL_MAXIGP1RID_ === 12'd0) ? 12'b0 : MAXIGP1RID;
wire [0:0] maxigp1rlast = (_TECHMAP_CONSTMSK_MAXIGP1RLAST_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1RLAST_ === 1'd0) ? 1'b0 : MAXIGP1RLAST;
wire [1:0] maxigp1rresp = (_TECHMAP_CONSTMSK_MAXIGP1RRESP_ == 2'd0 && _TECHMAP_CONSTVAL_MAXIGP1RRESP_ === 2'd0) ? 2'b0 : MAXIGP1RRESP;
wire [0:0] maxigp1rvalid = (_TECHMAP_CONSTMSK_MAXIGP1RVALID_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1RVALID_ === 1'd0) ? 1'b0 : MAXIGP1RVALID;
wire [0:0] maxigp1wready = (_TECHMAP_CONSTMSK_MAXIGP1WREADY_ == 1'd0 && _TECHMAP_CONSTVAL_MAXIGP1WREADY_ === 1'd0) ? 1'b0 : MAXIGP1WREADY;
wire [0:0] saxiacpaclk = (_TECHMAP_CONSTMSK_SAXIACPACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPACLK_ === 1'd0) ? 1'b0 : SAXIACPACLK;
wire [31:0] saxiacparaddr = (_TECHMAP_CONSTMSK_SAXIACPARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIACPARADDR_ === 32'd0) ? 32'b0 : SAXIACPARADDR;
wire [1:0] saxiacparburst = (_TECHMAP_CONSTMSK_SAXIACPARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPARBURST_ === 2'd0) ? 2'b0 : SAXIACPARBURST;
wire [3:0] saxiacparcache = (_TECHMAP_CONSTMSK_SAXIACPARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPARCACHE_ === 4'd0) ? 4'b0 : SAXIACPARCACHE;
wire [2:0] saxiacparid = (_TECHMAP_CONSTMSK_SAXIACPARID_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPARID_ === 3'd0) ? 3'b0 : SAXIACPARID;
wire [3:0] saxiacparlen = (_TECHMAP_CONSTMSK_SAXIACPARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPARLEN_ === 4'd0) ? 4'b0 : SAXIACPARLEN;
wire [1:0] saxiacparlock = (_TECHMAP_CONSTMSK_SAXIACPARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPARLOCK_ === 2'd0) ? 2'b0 : SAXIACPARLOCK;
wire [2:0] saxiacparprot = (_TECHMAP_CONSTMSK_SAXIACPARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPARPROT_ === 3'd0) ? 3'b0 : SAXIACPARPROT;
wire [3:0] saxiacparqos = (_TECHMAP_CONSTMSK_SAXIACPARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPARQOS_ === 4'd0) ? 4'b0 : SAXIACPARQOS;
wire [1:0] saxiacparsize = (_TECHMAP_CONSTMSK_SAXIACPARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPARSIZE_ === 2'd0) ? 2'b0 : SAXIACPARSIZE;
wire [4:0] saxiacparuser = (_TECHMAP_CONSTMSK_SAXIACPARUSER_ == 5'd0 && _TECHMAP_CONSTVAL_SAXIACPARUSER_ === 5'd0) ? 5'b0 : SAXIACPARUSER;
wire [0:0] saxiacparvalid = (_TECHMAP_CONSTMSK_SAXIACPARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPARVALID_ === 1'd0) ? 1'b0 : SAXIACPARVALID;
wire [31:0] saxiacpawaddr = (_TECHMAP_CONSTMSK_SAXIACPAWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIACPAWADDR_ === 32'd0) ? 32'b0 : SAXIACPAWADDR;
wire [1:0] saxiacpawburst = (_TECHMAP_CONSTMSK_SAXIACPAWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPAWBURST_ === 2'd0) ? 2'b0 : SAXIACPAWBURST;
wire [3:0] saxiacpawcache = (_TECHMAP_CONSTMSK_SAXIACPAWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPAWCACHE_ === 4'd0) ? 4'b0 : SAXIACPAWCACHE;
wire [2:0] saxiacpawid = (_TECHMAP_CONSTMSK_SAXIACPAWID_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPAWID_ === 3'd0) ? 3'b0 : SAXIACPAWID;
wire [3:0] saxiacpawlen = (_TECHMAP_CONSTMSK_SAXIACPAWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPAWLEN_ === 4'd0) ? 4'b0 : SAXIACPAWLEN;
wire [1:0] saxiacpawlock = (_TECHMAP_CONSTMSK_SAXIACPAWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPAWLOCK_ === 2'd0) ? 2'b0 : SAXIACPAWLOCK;
wire [2:0] saxiacpawprot = (_TECHMAP_CONSTMSK_SAXIACPAWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPAWPROT_ === 3'd0) ? 3'b0 : SAXIACPAWPROT;
wire [3:0] saxiacpawqos = (_TECHMAP_CONSTMSK_SAXIACPAWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIACPAWQOS_ === 4'd0) ? 4'b0 : SAXIACPAWQOS;
wire [1:0] saxiacpawsize = (_TECHMAP_CONSTMSK_SAXIACPAWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIACPAWSIZE_ === 2'd0) ? 2'b0 : SAXIACPAWSIZE;
wire [4:0] saxiacpawuser = (_TECHMAP_CONSTMSK_SAXIACPAWUSER_ == 5'd0 && _TECHMAP_CONSTVAL_SAXIACPAWUSER_ === 5'd0) ? 5'b0 : SAXIACPAWUSER;
wire [0:0] saxiacpawvalid = (_TECHMAP_CONSTMSK_SAXIACPAWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPAWVALID_ === 1'd0) ? 1'b0 : SAXIACPAWVALID;
wire [0:0] saxiacpbready = (_TECHMAP_CONSTMSK_SAXIACPBREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPBREADY_ === 1'd0) ? 1'b0 : SAXIACPBREADY;
wire [0:0] saxiacprready = (_TECHMAP_CONSTMSK_SAXIACPRREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPRREADY_ === 1'd0) ? 1'b0 : SAXIACPRREADY;
wire [63:0] saxiacpwdata = (_TECHMAP_CONSTMSK_SAXIACPWDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIACPWDATA_ === 64'd0) ? 64'b0 : SAXIACPWDATA;
wire [2:0] saxiacpwid = (_TECHMAP_CONSTMSK_SAXIACPWID_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIACPWID_ === 3'd0) ? 3'b0 : SAXIACPWID;
wire [0:0] saxiacpwlast = (_TECHMAP_CONSTMSK_SAXIACPWLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPWLAST_ === 1'd0) ? 1'b0 : SAXIACPWLAST;
wire [7:0] saxiacpwstrb = (_TECHMAP_CONSTMSK_SAXIACPWSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIACPWSTRB_ === 8'd0) ? 8'b0 : SAXIACPWSTRB;
wire [0:0] saxiacpwvalid = (_TECHMAP_CONSTMSK_SAXIACPWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIACPWVALID_ === 1'd0) ? 1'b0 : SAXIACPWVALID;
wire [0:0] saxigp0aclk = (_TECHMAP_CONSTMSK_SAXIGP0ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0ACLK_ === 1'd0) ? 1'b0 : SAXIGP0ACLK;
wire [31:0] saxigp0araddr = (_TECHMAP_CONSTMSK_SAXIGP0ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARADDR_ === 32'd0) ? 32'b0 : SAXIGP0ARADDR;
wire [1:0] saxigp0arburst = (_TECHMAP_CONSTMSK_SAXIGP0ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARBURST_ === 2'd0) ? 2'b0 : SAXIGP0ARBURST;
wire [3:0] saxigp0arcache = (_TECHMAP_CONSTMSK_SAXIGP0ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARCACHE_ === 4'd0) ? 4'b0 : SAXIGP0ARCACHE;
wire [5:0] saxigp0arid = (_TECHMAP_CONSTMSK_SAXIGP0ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARID_ === 6'd0) ? 6'b0 : SAXIGP0ARID;
wire [3:0] saxigp0arlen = (_TECHMAP_CONSTMSK_SAXIGP0ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARLEN_ === 4'd0) ? 4'b0 : SAXIGP0ARLEN;
wire [1:0] saxigp0arlock = (_TECHMAP_CONSTMSK_SAXIGP0ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARLOCK_ === 2'd0) ? 2'b0 : SAXIGP0ARLOCK;
wire [2:0] saxigp0arprot = (_TECHMAP_CONSTMSK_SAXIGP0ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARPROT_ === 3'd0) ? 3'b0 : SAXIGP0ARPROT;
wire [3:0] saxigp0arqos = (_TECHMAP_CONSTMSK_SAXIGP0ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARQOS_ === 4'd0) ? 4'b0 : SAXIGP0ARQOS;
wire [1:0] saxigp0arsize = (_TECHMAP_CONSTMSK_SAXIGP0ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARSIZE_ === 2'd0) ? 2'b0 : SAXIGP0ARSIZE;
wire [0:0] saxigp0arvalid = (_TECHMAP_CONSTMSK_SAXIGP0ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0ARVALID_ === 1'd0) ? 1'b0 : SAXIGP0ARVALID;
wire [31:0] saxigp0awaddr = (_TECHMAP_CONSTMSK_SAXIGP0AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWADDR_ === 32'd0) ? 32'b0 : SAXIGP0AWADDR;
wire [1:0] saxigp0awburst = (_TECHMAP_CONSTMSK_SAXIGP0AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWBURST_ === 2'd0) ? 2'b0 : SAXIGP0AWBURST;
wire [3:0] saxigp0awcache = (_TECHMAP_CONSTMSK_SAXIGP0AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWCACHE_ === 4'd0) ? 4'b0 : SAXIGP0AWCACHE;
wire [5:0] saxigp0awid = (_TECHMAP_CONSTMSK_SAXIGP0AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWID_ === 6'd0) ? 6'b0 : SAXIGP0AWID;
wire [3:0] saxigp0awlen = (_TECHMAP_CONSTMSK_SAXIGP0AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWLEN_ === 4'd0) ? 4'b0 : SAXIGP0AWLEN;
wire [1:0] saxigp0awlock = (_TECHMAP_CONSTMSK_SAXIGP0AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWLOCK_ === 2'd0) ? 2'b0 : SAXIGP0AWLOCK;
wire [2:0] saxigp0awprot = (_TECHMAP_CONSTMSK_SAXIGP0AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWPROT_ === 3'd0) ? 3'b0 : SAXIGP0AWPROT;
wire [3:0] saxigp0awqos = (_TECHMAP_CONSTMSK_SAXIGP0AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWQOS_ === 4'd0) ? 4'b0 : SAXIGP0AWQOS;
wire [1:0] saxigp0awsize = (_TECHMAP_CONSTMSK_SAXIGP0AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWSIZE_ === 2'd0) ? 2'b0 : SAXIGP0AWSIZE;
wire [0:0] saxigp0awvalid = (_TECHMAP_CONSTMSK_SAXIGP0AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0AWVALID_ === 1'd0) ? 1'b0 : SAXIGP0AWVALID;
wire [0:0] saxigp0bready = (_TECHMAP_CONSTMSK_SAXIGP0BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0BREADY_ === 1'd0) ? 1'b0 : SAXIGP0BREADY;
wire [0:0] saxigp0rready = (_TECHMAP_CONSTMSK_SAXIGP0RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0RREADY_ === 1'd0) ? 1'b0 : SAXIGP0RREADY;
wire [31:0] saxigp0wdata = (_TECHMAP_CONSTMSK_SAXIGP0WDATA_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP0WDATA_ === 32'd0) ? 32'b0 : SAXIGP0WDATA;
wire [5:0] saxigp0wid = (_TECHMAP_CONSTMSK_SAXIGP0WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP0WID_ === 6'd0) ? 6'b0 : SAXIGP0WID;
wire [0:0] saxigp0wlast = (_TECHMAP_CONSTMSK_SAXIGP0WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0WLAST_ === 1'd0) ? 1'b0 : SAXIGP0WLAST;
wire [3:0] saxigp0wstrb = (_TECHMAP_CONSTMSK_SAXIGP0WSTRB_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP0WSTRB_ === 4'd0) ? 4'b0 : SAXIGP0WSTRB;
wire [0:0] saxigp0wvalid = (_TECHMAP_CONSTMSK_SAXIGP0WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP0WVALID_ === 1'd0) ? 1'b0 : SAXIGP0WVALID;
wire [0:0] saxigp1aclk = (_TECHMAP_CONSTMSK_SAXIGP1ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1ACLK_ === 1'd0) ? 1'b0 : SAXIGP1ACLK;
wire [31:0] saxigp1araddr = (_TECHMAP_CONSTMSK_SAXIGP1ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARADDR_ === 32'd0) ? 32'b0 : SAXIGP1ARADDR;
wire [1:0] saxigp1arburst = (_TECHMAP_CONSTMSK_SAXIGP1ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARBURST_ === 2'd0) ? 2'b0 : SAXIGP1ARBURST;
wire [3:0] saxigp1arcache = (_TECHMAP_CONSTMSK_SAXIGP1ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARCACHE_ === 4'd0) ? 4'b0 : SAXIGP1ARCACHE;
wire [5:0] saxigp1arid = (_TECHMAP_CONSTMSK_SAXIGP1ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARID_ === 6'd0) ? 6'b0 : SAXIGP1ARID;
wire [3:0] saxigp1arlen = (_TECHMAP_CONSTMSK_SAXIGP1ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARLEN_ === 4'd0) ? 4'b0 : SAXIGP1ARLEN;
wire [1:0] saxigp1arlock = (_TECHMAP_CONSTMSK_SAXIGP1ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARLOCK_ === 2'd0) ? 2'b0 : SAXIGP1ARLOCK;
wire [2:0] saxigp1arprot = (_TECHMAP_CONSTMSK_SAXIGP1ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARPROT_ === 3'd0) ? 3'b0 : SAXIGP1ARPROT;
wire [3:0] saxigp1arqos = (_TECHMAP_CONSTMSK_SAXIGP1ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARQOS_ === 4'd0) ? 4'b0 : SAXIGP1ARQOS;
wire [1:0] saxigp1arsize = (_TECHMAP_CONSTMSK_SAXIGP1ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARSIZE_ === 2'd0) ? 2'b0 : SAXIGP1ARSIZE;
wire [0:0] saxigp1arvalid = (_TECHMAP_CONSTMSK_SAXIGP1ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1ARVALID_ === 1'd0) ? 1'b0 : SAXIGP1ARVALID;
wire [31:0] saxigp1awaddr = (_TECHMAP_CONSTMSK_SAXIGP1AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWADDR_ === 32'd0) ? 32'b0 : SAXIGP1AWADDR;
wire [1:0] saxigp1awburst = (_TECHMAP_CONSTMSK_SAXIGP1AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWBURST_ === 2'd0) ? 2'b0 : SAXIGP1AWBURST;
wire [3:0] saxigp1awcache = (_TECHMAP_CONSTMSK_SAXIGP1AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWCACHE_ === 4'd0) ? 4'b0 : SAXIGP1AWCACHE;
wire [5:0] saxigp1awid = (_TECHMAP_CONSTMSK_SAXIGP1AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWID_ === 6'd0) ? 6'b0 : SAXIGP1AWID;
wire [3:0] saxigp1awlen = (_TECHMAP_CONSTMSK_SAXIGP1AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWLEN_ === 4'd0) ? 4'b0 : SAXIGP1AWLEN;
wire [1:0] saxigp1awlock = (_TECHMAP_CONSTMSK_SAXIGP1AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWLOCK_ === 2'd0) ? 2'b0 : SAXIGP1AWLOCK;
wire [2:0] saxigp1awprot = (_TECHMAP_CONSTMSK_SAXIGP1AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWPROT_ === 3'd0) ? 3'b0 : SAXIGP1AWPROT;
wire [3:0] saxigp1awqos = (_TECHMAP_CONSTMSK_SAXIGP1AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWQOS_ === 4'd0) ? 4'b0 : SAXIGP1AWQOS;
wire [1:0] saxigp1awsize = (_TECHMAP_CONSTMSK_SAXIGP1AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWSIZE_ === 2'd0) ? 2'b0 : SAXIGP1AWSIZE;
wire [0:0] saxigp1awvalid = (_TECHMAP_CONSTMSK_SAXIGP1AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1AWVALID_ === 1'd0) ? 1'b0 : SAXIGP1AWVALID;
wire [0:0] saxigp1bready = (_TECHMAP_CONSTMSK_SAXIGP1BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1BREADY_ === 1'd0) ? 1'b0 : SAXIGP1BREADY;
wire [0:0] saxigp1rready = (_TECHMAP_CONSTMSK_SAXIGP1RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1RREADY_ === 1'd0) ? 1'b0 : SAXIGP1RREADY;
wire [31:0] saxigp1wdata = (_TECHMAP_CONSTMSK_SAXIGP1WDATA_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIGP1WDATA_ === 32'd0) ? 32'b0 : SAXIGP1WDATA;
wire [5:0] saxigp1wid = (_TECHMAP_CONSTMSK_SAXIGP1WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIGP1WID_ === 6'd0) ? 6'b0 : SAXIGP1WID;
wire [0:0] saxigp1wlast = (_TECHMAP_CONSTMSK_SAXIGP1WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1WLAST_ === 1'd0) ? 1'b0 : SAXIGP1WLAST;
wire [3:0] saxigp1wstrb = (_TECHMAP_CONSTMSK_SAXIGP1WSTRB_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIGP1WSTRB_ === 4'd0) ? 4'b0 : SAXIGP1WSTRB;
wire [0:0] saxigp1wvalid = (_TECHMAP_CONSTMSK_SAXIGP1WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIGP1WVALID_ === 1'd0) ? 1'b0 : SAXIGP1WVALID;
wire [0:0] saxihp0aclk = (_TECHMAP_CONSTMSK_SAXIHP0ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0ACLK_ === 1'd0) ? 1'b0 : SAXIHP0ACLK;
wire [31:0] saxihp0araddr = (_TECHMAP_CONSTMSK_SAXIHP0ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARADDR_ === 32'd0) ? 32'b0 : SAXIHP0ARADDR;
wire [1:0] saxihp0arburst = (_TECHMAP_CONSTMSK_SAXIHP0ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARBURST_ === 2'd0) ? 2'b0 : SAXIHP0ARBURST;
wire [3:0] saxihp0arcache = (_TECHMAP_CONSTMSK_SAXIHP0ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARCACHE_ === 4'd0) ? 4'b0 : SAXIHP0ARCACHE;
wire [5:0] saxihp0arid = (_TECHMAP_CONSTMSK_SAXIHP0ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARID_ === 6'd0) ? 6'b0 : SAXIHP0ARID;
wire [3:0] saxihp0arlen = (_TECHMAP_CONSTMSK_SAXIHP0ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARLEN_ === 4'd0) ? 4'b0 : SAXIHP0ARLEN;
wire [1:0] saxihp0arlock = (_TECHMAP_CONSTMSK_SAXIHP0ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARLOCK_ === 2'd0) ? 2'b0 : SAXIHP0ARLOCK;
wire [2:0] saxihp0arprot = (_TECHMAP_CONSTMSK_SAXIHP0ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARPROT_ === 3'd0) ? 3'b0 : SAXIHP0ARPROT;
wire [3:0] saxihp0arqos = (_TECHMAP_CONSTMSK_SAXIHP0ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARQOS_ === 4'd0) ? 4'b0 : SAXIHP0ARQOS;
wire [1:0] saxihp0arsize = (_TECHMAP_CONSTMSK_SAXIHP0ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARSIZE_ === 2'd0) ? 2'b0 : SAXIHP0ARSIZE;
wire [0:0] saxihp0arvalid = (_TECHMAP_CONSTMSK_SAXIHP0ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0ARVALID_ === 1'd0) ? 1'b0 : SAXIHP0ARVALID;
wire [31:0] saxihp0awaddr = (_TECHMAP_CONSTMSK_SAXIHP0AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWADDR_ === 32'd0) ? 32'b0 : SAXIHP0AWADDR;
wire [1:0] saxihp0awburst = (_TECHMAP_CONSTMSK_SAXIHP0AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWBURST_ === 2'd0) ? 2'b0 : SAXIHP0AWBURST;
wire [3:0] saxihp0awcache = (_TECHMAP_CONSTMSK_SAXIHP0AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWCACHE_ === 4'd0) ? 4'b0 : SAXIHP0AWCACHE;
wire [5:0] saxihp0awid = (_TECHMAP_CONSTMSK_SAXIHP0AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWID_ === 6'd0) ? 6'b0 : SAXIHP0AWID;
wire [3:0] saxihp0awlen = (_TECHMAP_CONSTMSK_SAXIHP0AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWLEN_ === 4'd0) ? 4'b0 : SAXIHP0AWLEN;
wire [1:0] saxihp0awlock = (_TECHMAP_CONSTMSK_SAXIHP0AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWLOCK_ === 2'd0) ? 2'b0 : SAXIHP0AWLOCK;
wire [2:0] saxihp0awprot = (_TECHMAP_CONSTMSK_SAXIHP0AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWPROT_ === 3'd0) ? 3'b0 : SAXIHP0AWPROT;
wire [3:0] saxihp0awqos = (_TECHMAP_CONSTMSK_SAXIHP0AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWQOS_ === 4'd0) ? 4'b0 : SAXIHP0AWQOS;
wire [1:0] saxihp0awsize = (_TECHMAP_CONSTMSK_SAXIHP0AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWSIZE_ === 2'd0) ? 2'b0 : SAXIHP0AWSIZE;
wire [0:0] saxihp0awvalid = (_TECHMAP_CONSTMSK_SAXIHP0AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0AWVALID_ === 1'd0) ? 1'b0 : SAXIHP0AWVALID;
wire [0:0] saxihp0bready = (_TECHMAP_CONSTMSK_SAXIHP0BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0BREADY_ === 1'd0) ? 1'b0 : SAXIHP0BREADY;
wire [0:0] saxihp0rdissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP0RDISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0RDISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP0RDISSUECAP1EN;
wire [0:0] saxihp0rready = (_TECHMAP_CONSTMSK_SAXIHP0RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0RREADY_ === 1'd0) ? 1'b0 : SAXIHP0RREADY;
wire [63:0] saxihp0wdata = (_TECHMAP_CONSTMSK_SAXIHP0WDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIHP0WDATA_ === 64'd0) ? 64'b0 : SAXIHP0WDATA;
wire [5:0] saxihp0wid = (_TECHMAP_CONSTMSK_SAXIHP0WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP0WID_ === 6'd0) ? 6'b0 : SAXIHP0WID;
wire [0:0] saxihp0wlast = (_TECHMAP_CONSTMSK_SAXIHP0WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0WLAST_ === 1'd0) ? 1'b0 : SAXIHP0WLAST;
wire [0:0] saxihp0wrissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP0WRISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0WRISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP0WRISSUECAP1EN;
wire [7:0] saxihp0wstrb = (_TECHMAP_CONSTMSK_SAXIHP0WSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIHP0WSTRB_ === 8'd0) ? 8'b0 : SAXIHP0WSTRB;
wire [0:0] saxihp0wvalid = (_TECHMAP_CONSTMSK_SAXIHP0WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP0WVALID_ === 1'd0) ? 1'b0 : SAXIHP0WVALID;
wire [0:0] saxihp1aclk = (_TECHMAP_CONSTMSK_SAXIHP1ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1ACLK_ === 1'd0) ? 1'b0 : SAXIHP1ACLK;
wire [31:0] saxihp1araddr = (_TECHMAP_CONSTMSK_SAXIHP1ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARADDR_ === 32'd0) ? 32'b0 : SAXIHP1ARADDR;
wire [1:0] saxihp1arburst = (_TECHMAP_CONSTMSK_SAXIHP1ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARBURST_ === 2'd0) ? 2'b0 : SAXIHP1ARBURST;
wire [3:0] saxihp1arcache = (_TECHMAP_CONSTMSK_SAXIHP1ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARCACHE_ === 4'd0) ? 4'b0 : SAXIHP1ARCACHE;
wire [5:0] saxihp1arid = (_TECHMAP_CONSTMSK_SAXIHP1ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARID_ === 6'd0) ? 6'b0 : SAXIHP1ARID;
wire [3:0] saxihp1arlen = (_TECHMAP_CONSTMSK_SAXIHP1ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARLEN_ === 4'd0) ? 4'b0 : SAXIHP1ARLEN;
wire [1:0] saxihp1arlock = (_TECHMAP_CONSTMSK_SAXIHP1ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARLOCK_ === 2'd0) ? 2'b0 : SAXIHP1ARLOCK;
wire [2:0] saxihp1arprot = (_TECHMAP_CONSTMSK_SAXIHP1ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARPROT_ === 3'd0) ? 3'b0 : SAXIHP1ARPROT;
wire [3:0] saxihp1arqos = (_TECHMAP_CONSTMSK_SAXIHP1ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARQOS_ === 4'd0) ? 4'b0 : SAXIHP1ARQOS;
wire [1:0] saxihp1arsize = (_TECHMAP_CONSTMSK_SAXIHP1ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARSIZE_ === 2'd0) ? 2'b0 : SAXIHP1ARSIZE;
wire [0:0] saxihp1arvalid = (_TECHMAP_CONSTMSK_SAXIHP1ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1ARVALID_ === 1'd0) ? 1'b0 : SAXIHP1ARVALID;
wire [31:0] saxihp1awaddr = (_TECHMAP_CONSTMSK_SAXIHP1AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWADDR_ === 32'd0) ? 32'b0 : SAXIHP1AWADDR;
wire [1:0] saxihp1awburst = (_TECHMAP_CONSTMSK_SAXIHP1AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWBURST_ === 2'd0) ? 2'b0 : SAXIHP1AWBURST;
wire [3:0] saxihp1awcache = (_TECHMAP_CONSTMSK_SAXIHP1AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWCACHE_ === 4'd0) ? 4'b0 : SAXIHP1AWCACHE;
wire [5:0] saxihp1awid = (_TECHMAP_CONSTMSK_SAXIHP1AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWID_ === 6'd0) ? 6'b0 : SAXIHP1AWID;
wire [3:0] saxihp1awlen = (_TECHMAP_CONSTMSK_SAXIHP1AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWLEN_ === 4'd0) ? 4'b0 : SAXIHP1AWLEN;
wire [1:0] saxihp1awlock = (_TECHMAP_CONSTMSK_SAXIHP1AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWLOCK_ === 2'd0) ? 2'b0 : SAXIHP1AWLOCK;
wire [2:0] saxihp1awprot = (_TECHMAP_CONSTMSK_SAXIHP1AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWPROT_ === 3'd0) ? 3'b0 : SAXIHP1AWPROT;
wire [3:0] saxihp1awqos = (_TECHMAP_CONSTMSK_SAXIHP1AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWQOS_ === 4'd0) ? 4'b0 : SAXIHP1AWQOS;
wire [1:0] saxihp1awsize = (_TECHMAP_CONSTMSK_SAXIHP1AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWSIZE_ === 2'd0) ? 2'b0 : SAXIHP1AWSIZE;
wire [0:0] saxihp1awvalid = (_TECHMAP_CONSTMSK_SAXIHP1AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1AWVALID_ === 1'd0) ? 1'b0 : SAXIHP1AWVALID;
wire [0:0] saxihp1bready = (_TECHMAP_CONSTMSK_SAXIHP1BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1BREADY_ === 1'd0) ? 1'b0 : SAXIHP1BREADY;
wire [0:0] saxihp1rdissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP1RDISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1RDISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP1RDISSUECAP1EN;
wire [0:0] saxihp1rready = (_TECHMAP_CONSTMSK_SAXIHP1RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1RREADY_ === 1'd0) ? 1'b0 : SAXIHP1RREADY;
wire [63:0] saxihp1wdata = (_TECHMAP_CONSTMSK_SAXIHP1WDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIHP1WDATA_ === 64'd0) ? 64'b0 : SAXIHP1WDATA;
wire [5:0] saxihp1wid = (_TECHMAP_CONSTMSK_SAXIHP1WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP1WID_ === 6'd0) ? 6'b0 : SAXIHP1WID;
wire [0:0] saxihp1wlast = (_TECHMAP_CONSTMSK_SAXIHP1WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1WLAST_ === 1'd0) ? 1'b0 : SAXIHP1WLAST;
wire [0:0] saxihp1wrissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP1WRISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1WRISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP1WRISSUECAP1EN;
wire [7:0] saxihp1wstrb = (_TECHMAP_CONSTMSK_SAXIHP1WSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIHP1WSTRB_ === 8'd0) ? 8'b0 : SAXIHP1WSTRB;
wire [0:0] saxihp1wvalid = (_TECHMAP_CONSTMSK_SAXIHP1WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP1WVALID_ === 1'd0) ? 1'b0 : SAXIHP1WVALID;
wire [0:0] saxihp2aclk = (_TECHMAP_CONSTMSK_SAXIHP2ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2ACLK_ === 1'd0) ? 1'b0 : SAXIHP2ACLK;
wire [31:0] saxihp2araddr = (_TECHMAP_CONSTMSK_SAXIHP2ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARADDR_ === 32'd0) ? 32'b0 : SAXIHP2ARADDR;
wire [1:0] saxihp2arburst = (_TECHMAP_CONSTMSK_SAXIHP2ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARBURST_ === 2'd0) ? 2'b0 : SAXIHP2ARBURST;
wire [3:0] saxihp2arcache = (_TECHMAP_CONSTMSK_SAXIHP2ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARCACHE_ === 4'd0) ? 4'b0 : SAXIHP2ARCACHE;
wire [5:0] saxihp2arid = (_TECHMAP_CONSTMSK_SAXIHP2ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARID_ === 6'd0) ? 6'b0 : SAXIHP2ARID;
wire [3:0] saxihp2arlen = (_TECHMAP_CONSTMSK_SAXIHP2ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARLEN_ === 4'd0) ? 4'b0 : SAXIHP2ARLEN;
wire [1:0] saxihp2arlock = (_TECHMAP_CONSTMSK_SAXIHP2ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARLOCK_ === 2'd0) ? 2'b0 : SAXIHP2ARLOCK;
wire [2:0] saxihp2arprot = (_TECHMAP_CONSTMSK_SAXIHP2ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARPROT_ === 3'd0) ? 3'b0 : SAXIHP2ARPROT;
wire [3:0] saxihp2arqos = (_TECHMAP_CONSTMSK_SAXIHP2ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARQOS_ === 4'd0) ? 4'b0 : SAXIHP2ARQOS;
wire [1:0] saxihp2arsize = (_TECHMAP_CONSTMSK_SAXIHP2ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARSIZE_ === 2'd0) ? 2'b0 : SAXIHP2ARSIZE;
wire [0:0] saxihp2arvalid = (_TECHMAP_CONSTMSK_SAXIHP2ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2ARVALID_ === 1'd0) ? 1'b0 : SAXIHP2ARVALID;
wire [31:0] saxihp2awaddr = (_TECHMAP_CONSTMSK_SAXIHP2AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWADDR_ === 32'd0) ? 32'b0 : SAXIHP2AWADDR;
wire [1:0] saxihp2awburst = (_TECHMAP_CONSTMSK_SAXIHP2AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWBURST_ === 2'd0) ? 2'b0 : SAXIHP2AWBURST;
wire [3:0] saxihp2awcache = (_TECHMAP_CONSTMSK_SAXIHP2AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWCACHE_ === 4'd0) ? 4'b0 : SAXIHP2AWCACHE;
wire [5:0] saxihp2awid = (_TECHMAP_CONSTMSK_SAXIHP2AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWID_ === 6'd0) ? 6'b0 : SAXIHP2AWID;
wire [3:0] saxihp2awlen = (_TECHMAP_CONSTMSK_SAXIHP2AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWLEN_ === 4'd0) ? 4'b0 : SAXIHP2AWLEN;
wire [1:0] saxihp2awlock = (_TECHMAP_CONSTMSK_SAXIHP2AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWLOCK_ === 2'd0) ? 2'b0 : SAXIHP2AWLOCK;
wire [2:0] saxihp2awprot = (_TECHMAP_CONSTMSK_SAXIHP2AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWPROT_ === 3'd0) ? 3'b0 : SAXIHP2AWPROT;
wire [3:0] saxihp2awqos = (_TECHMAP_CONSTMSK_SAXIHP2AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWQOS_ === 4'd0) ? 4'b0 : SAXIHP2AWQOS;
wire [1:0] saxihp2awsize = (_TECHMAP_CONSTMSK_SAXIHP2AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWSIZE_ === 2'd0) ? 2'b0 : SAXIHP2AWSIZE;
wire [0:0] saxihp2awvalid = (_TECHMAP_CONSTMSK_SAXIHP2AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2AWVALID_ === 1'd0) ? 1'b0 : SAXIHP2AWVALID;
wire [0:0] saxihp2bready = (_TECHMAP_CONSTMSK_SAXIHP2BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2BREADY_ === 1'd0) ? 1'b0 : SAXIHP2BREADY;
wire [0:0] saxihp2rdissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP2RDISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2RDISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP2RDISSUECAP1EN;
wire [0:0] saxihp2rready = (_TECHMAP_CONSTMSK_SAXIHP2RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2RREADY_ === 1'd0) ? 1'b0 : SAXIHP2RREADY;
wire [63:0] saxihp2wdata = (_TECHMAP_CONSTMSK_SAXIHP2WDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIHP2WDATA_ === 64'd0) ? 64'b0 : SAXIHP2WDATA;
wire [5:0] saxihp2wid = (_TECHMAP_CONSTMSK_SAXIHP2WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP2WID_ === 6'd0) ? 6'b0 : SAXIHP2WID;
wire [0:0] saxihp2wlast = (_TECHMAP_CONSTMSK_SAXIHP2WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2WLAST_ === 1'd0) ? 1'b0 : SAXIHP2WLAST;
wire [0:0] saxihp2wrissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP2WRISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2WRISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP2WRISSUECAP1EN;
wire [7:0] saxihp2wstrb = (_TECHMAP_CONSTMSK_SAXIHP2WSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIHP2WSTRB_ === 8'd0) ? 8'b0 : SAXIHP2WSTRB;
wire [0:0] saxihp2wvalid = (_TECHMAP_CONSTMSK_SAXIHP2WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP2WVALID_ === 1'd0) ? 1'b0 : SAXIHP2WVALID;
wire [0:0] saxihp3aclk = (_TECHMAP_CONSTMSK_SAXIHP3ACLK_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3ACLK_ === 1'd0) ? 1'b0 : SAXIHP3ACLK;
wire [31:0] saxihp3araddr = (_TECHMAP_CONSTMSK_SAXIHP3ARADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARADDR_ === 32'd0) ? 32'b0 : SAXIHP3ARADDR;
wire [1:0] saxihp3arburst = (_TECHMAP_CONSTMSK_SAXIHP3ARBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARBURST_ === 2'd0) ? 2'b0 : SAXIHP3ARBURST;
wire [3:0] saxihp3arcache = (_TECHMAP_CONSTMSK_SAXIHP3ARCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARCACHE_ === 4'd0) ? 4'b0 : SAXIHP3ARCACHE;
wire [5:0] saxihp3arid = (_TECHMAP_CONSTMSK_SAXIHP3ARID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARID_ === 6'd0) ? 6'b0 : SAXIHP3ARID;
wire [3:0] saxihp3arlen = (_TECHMAP_CONSTMSK_SAXIHP3ARLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARLEN_ === 4'd0) ? 4'b0 : SAXIHP3ARLEN;
wire [1:0] saxihp3arlock = (_TECHMAP_CONSTMSK_SAXIHP3ARLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARLOCK_ === 2'd0) ? 2'b0 : SAXIHP3ARLOCK;
wire [2:0] saxihp3arprot = (_TECHMAP_CONSTMSK_SAXIHP3ARPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARPROT_ === 3'd0) ? 3'b0 : SAXIHP3ARPROT;
wire [3:0] saxihp3arqos = (_TECHMAP_CONSTMSK_SAXIHP3ARQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARQOS_ === 4'd0) ? 4'b0 : SAXIHP3ARQOS;
wire [1:0] saxihp3arsize = (_TECHMAP_CONSTMSK_SAXIHP3ARSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARSIZE_ === 2'd0) ? 2'b0 : SAXIHP3ARSIZE;
wire [0:0] saxihp3arvalid = (_TECHMAP_CONSTMSK_SAXIHP3ARVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3ARVALID_ === 1'd0) ? 1'b0 : SAXIHP3ARVALID;
wire [31:0] saxihp3awaddr = (_TECHMAP_CONSTMSK_SAXIHP3AWADDR_ == 32'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWADDR_ === 32'd0) ? 32'b0 : SAXIHP3AWADDR;
wire [1:0] saxihp3awburst = (_TECHMAP_CONSTMSK_SAXIHP3AWBURST_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWBURST_ === 2'd0) ? 2'b0 : SAXIHP3AWBURST;
wire [3:0] saxihp3awcache = (_TECHMAP_CONSTMSK_SAXIHP3AWCACHE_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWCACHE_ === 4'd0) ? 4'b0 : SAXIHP3AWCACHE;
wire [5:0] saxihp3awid = (_TECHMAP_CONSTMSK_SAXIHP3AWID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWID_ === 6'd0) ? 6'b0 : SAXIHP3AWID;
wire [3:0] saxihp3awlen = (_TECHMAP_CONSTMSK_SAXIHP3AWLEN_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWLEN_ === 4'd0) ? 4'b0 : SAXIHP3AWLEN;
wire [1:0] saxihp3awlock = (_TECHMAP_CONSTMSK_SAXIHP3AWLOCK_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWLOCK_ === 2'd0) ? 2'b0 : SAXIHP3AWLOCK;
wire [2:0] saxihp3awprot = (_TECHMAP_CONSTMSK_SAXIHP3AWPROT_ == 3'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWPROT_ === 3'd0) ? 3'b0 : SAXIHP3AWPROT;
wire [3:0] saxihp3awqos = (_TECHMAP_CONSTMSK_SAXIHP3AWQOS_ == 4'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWQOS_ === 4'd0) ? 4'b0 : SAXIHP3AWQOS;
wire [1:0] saxihp3awsize = (_TECHMAP_CONSTMSK_SAXIHP3AWSIZE_ == 2'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWSIZE_ === 2'd0) ? 2'b0 : SAXIHP3AWSIZE;
wire [0:0] saxihp3awvalid = (_TECHMAP_CONSTMSK_SAXIHP3AWVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3AWVALID_ === 1'd0) ? 1'b0 : SAXIHP3AWVALID;
wire [0:0] saxihp3bready = (_TECHMAP_CONSTMSK_SAXIHP3BREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3BREADY_ === 1'd0) ? 1'b0 : SAXIHP3BREADY;
wire [0:0] saxihp3rdissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP3RDISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3RDISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP3RDISSUECAP1EN;
wire [0:0] saxihp3rready = (_TECHMAP_CONSTMSK_SAXIHP3RREADY_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3RREADY_ === 1'd0) ? 1'b0 : SAXIHP3RREADY;
wire [63:0] saxihp3wdata = (_TECHMAP_CONSTMSK_SAXIHP3WDATA_ == 64'd0 && _TECHMAP_CONSTVAL_SAXIHP3WDATA_ === 64'd0) ? 64'b0 : SAXIHP3WDATA;
wire [5:0] saxihp3wid = (_TECHMAP_CONSTMSK_SAXIHP3WID_ == 6'd0 && _TECHMAP_CONSTVAL_SAXIHP3WID_ === 6'd0) ? 6'b0 : SAXIHP3WID;
wire [0:0] saxihp3wlast = (_TECHMAP_CONSTMSK_SAXIHP3WLAST_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3WLAST_ === 1'd0) ? 1'b0 : SAXIHP3WLAST;
wire [0:0] saxihp3wrissuecap1en = (_TECHMAP_CONSTMSK_SAXIHP3WRISSUECAP1EN_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3WRISSUECAP1EN_ === 1'd0) ? 1'b0 : SAXIHP3WRISSUECAP1EN;
wire [7:0] saxihp3wstrb = (_TECHMAP_CONSTMSK_SAXIHP3WSTRB_ == 8'd0 && _TECHMAP_CONSTVAL_SAXIHP3WSTRB_ === 8'd0) ? 8'b0 : SAXIHP3WSTRB;
wire [0:0] saxihp3wvalid = (_TECHMAP_CONSTMSK_SAXIHP3WVALID_ == 1'd0 && _TECHMAP_CONSTVAL_SAXIHP3WVALID_ === 1'd0) ? 1'b0 : SAXIHP3WVALID;
// Replacement cell.
PS7_VPR _TECHMAP_REPLACE_ (
.DDRARB (ddrarb),
.DMA0ACLK (dma0aclk),
.DMA0DAREADY (dma0daready),
.DMA0DATYPE (DMA0DATYPE),
.DMA0DAVALID (DMA0DAVALID),
.DMA0DRLAST (dma0drlast),
.DMA0DRREADY (DMA0DRREADY),
.DMA0DRTYPE (dma0drtype),
.DMA0DRVALID (dma0drvalid),
.DMA0RSTN (DMA0RSTN),
.DMA1ACLK (dma1aclk),
.DMA1DAREADY (dma1daready),
.DMA1DATYPE (DMA1DATYPE),
.DMA1DAVALID (DMA1DAVALID),
.DMA1DRLAST (dma1drlast),
.DMA1DRREADY (DMA1DRREADY),
.DMA1DRTYPE (dma1drtype),
.DMA1DRVALID (dma1drvalid),
.DMA1RSTN (DMA1RSTN),
.DMA2ACLK (dma2aclk),
.DMA2DAREADY (dma2daready),
.DMA2DATYPE (DMA2DATYPE),
.DMA2DAVALID (DMA2DAVALID),
.DMA2DRLAST (dma2drlast),
.DMA2DRREADY (DMA2DRREADY),
.DMA2DRTYPE (dma2drtype),
.DMA2DRVALID (dma2drvalid),
.DMA2RSTN (DMA2RSTN),
.DMA3ACLK (dma3aclk),
.DMA3DAREADY (dma3daready),
.DMA3DATYPE (DMA3DATYPE),
.DMA3DAVALID (DMA3DAVALID),
.DMA3DRLAST (dma3drlast),
.DMA3DRREADY (DMA3DRREADY),
.DMA3DRTYPE (dma3drtype),
.DMA3DRVALID (dma3drvalid),
.DMA3RSTN (DMA3RSTN),
.EMIOCAN0PHYRX (emiocan0phyrx),
.EMIOCAN0PHYTX (EMIOCAN0PHYTX),
.EMIOCAN1PHYRX (emiocan1phyrx),
.EMIOCAN1PHYTX (EMIOCAN1PHYTX),
.EMIOENET0EXTINTIN (emioenet0extintin),
.EMIOENET0GMIICOL (emioenet0gmiicol),
.EMIOENET0GMIICRS (emioenet0gmiicrs),
.EMIOENET0GMIIRXCLK (emioenet0gmiirxclk),
.EMIOENET0GMIIRXD (emioenet0gmiirxd),
.EMIOENET0GMIIRXDV (emioenet0gmiirxdv),
.EMIOENET0GMIIRXER (emioenet0gmiirxer),
.EMIOENET0GMIITXCLK (emioenet0gmiitxclk),
.EMIOENET0GMIITXD (EMIOENET0GMIITXD),
.EMIOENET0GMIITXEN (EMIOENET0GMIITXEN),
.EMIOENET0GMIITXER (EMIOENET0GMIITXER),
.EMIOENET0MDIOI (emioenet0mdioi),
.EMIOENET0MDIOMDC (EMIOENET0MDIOMDC),
.EMIOENET0MDIOO (EMIOENET0MDIOO),
.EMIOENET0MDIOTN (EMIOENET0MDIOTN),
.EMIOENET0PTPDELAYREQRX (EMIOENET0PTPDELAYREQRX),
.EMIOENET0PTPDELAYREQTX (EMIOENET0PTPDELAYREQTX),
.EMIOENET0PTPPDELAYREQRX (EMIOENET0PTPPDELAYREQRX),
.EMIOENET0PTPPDELAYREQTX (EMIOENET0PTPPDELAYREQTX),
.EMIOENET0PTPPDELAYRESPRX (EMIOENET0PTPPDELAYRESPRX),
.EMIOENET0PTPPDELAYRESPTX (EMIOENET0PTPPDELAYRESPTX),
.EMIOENET0PTPSYNCFRAMERX (EMIOENET0PTPSYNCFRAMERX),
.EMIOENET0PTPSYNCFRAMETX (EMIOENET0PTPSYNCFRAMETX),
.EMIOENET0SOFRX (EMIOENET0SOFRX),
.EMIOENET0SOFTX (EMIOENET0SOFTX),
.EMIOENET1EXTINTIN (emioenet1extintin),
.EMIOENET1GMIICOL (emioenet1gmiicol),
.EMIOENET1GMIICRS (emioenet1gmiicrs),
.EMIOENET1GMIIRXCLK (emioenet1gmiirxclk),
.EMIOENET1GMIIRXD (emioenet1gmiirxd),
.EMIOENET1GMIIRXDV (emioenet1gmiirxdv),
.EMIOENET1GMIIRXER (emioenet1gmiirxer),
.EMIOENET1GMIITXCLK (emioenet1gmiitxclk),
.EMIOENET1GMIITXD (EMIOENET1GMIITXD),
.EMIOENET1GMIITXEN (EMIOENET1GMIITXEN),
.EMIOENET1GMIITXER (EMIOENET1GMIITXER),
.EMIOENET1MDIOI (emioenet1mdioi),
.EMIOENET1MDIOMDC (EMIOENET1MDIOMDC),
.EMIOENET1MDIOO (EMIOENET1MDIOO),
.EMIOENET1MDIOTN (EMIOENET1MDIOTN),
.EMIOENET1PTPDELAYREQRX (EMIOENET1PTPDELAYREQRX),
.EMIOENET1PTPDELAYREQTX (EMIOENET1PTPDELAYREQTX),
.EMIOENET1PTPPDELAYREQRX (EMIOENET1PTPPDELAYREQRX),
.EMIOENET1PTPPDELAYREQTX (EMIOENET1PTPPDELAYREQTX),
.EMIOENET1PTPPDELAYRESPRX (EMIOENET1PTPPDELAYRESPRX),
.EMIOENET1PTPPDELAYRESPTX (EMIOENET1PTPPDELAYRESPTX),
.EMIOENET1PTPSYNCFRAMERX (EMIOENET1PTPSYNCFRAMERX),
.EMIOENET1PTPSYNCFRAMETX (EMIOENET1PTPSYNCFRAMETX),
.EMIOENET1SOFRX (EMIOENET1SOFRX),
.EMIOENET1SOFTX (EMIOENET1SOFTX),
.EMIOGPIOI (emiogpioi),
.EMIOGPIOO (EMIOGPIOO),
.EMIOGPIOTN (EMIOGPIOTN),
.EMIOI2C0SCLI (emioi2c0scli),
.EMIOI2C0SCLO (EMIOI2C0SCLO),
.EMIOI2C0SCLTN (EMIOI2C0SCLTN),
.EMIOI2C0SDAI (emioi2c0sdai),
.EMIOI2C0SDAO (EMIOI2C0SDAO),
.EMIOI2C0SDATN (EMIOI2C0SDATN),
.EMIOI2C1SCLI (emioi2c1scli),
.EMIOI2C1SCLO (EMIOI2C1SCLO),
.EMIOI2C1SCLTN (EMIOI2C1SCLTN),
.EMIOI2C1SDAI (emioi2c1sdai),
.EMIOI2C1SDAO (EMIOI2C1SDAO),
.EMIOI2C1SDATN (EMIOI2C1SDATN),
.EMIOPJTAGTCK (emiopjtagtck),
.EMIOPJTAGTDI (emiopjtagtdi),
.EMIOPJTAGTDO (EMIOPJTAGTDO),
.EMIOPJTAGTDTN (EMIOPJTAGTDTN),
.EMIOPJTAGTMS (emiopjtagtms),
.EMIOSDIO0BUSPOW (EMIOSDIO0BUSPOW),
.EMIOSDIO0BUSVOLT (EMIOSDIO0BUSVOLT),
.EMIOSDIO0CDN (emiosdio0cdn),
.EMIOSDIO0CLK (EMIOSDIO0CLK),
.EMIOSDIO0CLKFB (emiosdio0clkfb),
.EMIOSDIO0CMDI (emiosdio0cmdi),
.EMIOSDIO0CMDO (EMIOSDIO0CMDO),
.EMIOSDIO0CMDTN (EMIOSDIO0CMDTN),
.EMIOSDIO0DATAI (emiosdio0datai),
.EMIOSDIO0DATAO (EMIOSDIO0DATAO),
.EMIOSDIO0DATATN (EMIOSDIO0DATATN),
.EMIOSDIO0LED (EMIOSDIO0LED),
.EMIOSDIO0WP (emiosdio0wp),
.EMIOSDIO1BUSPOW (EMIOSDIO1BUSPOW),
.EMIOSDIO1BUSVOLT (EMIOSDIO1BUSVOLT),
.EMIOSDIO1CDN (emiosdio1cdn),
.EMIOSDIO1CLK (EMIOSDIO1CLK),
.EMIOSDIO1CLKFB (emiosdio1clkfb),
.EMIOSDIO1CMDI (emiosdio1cmdi),
.EMIOSDIO1CMDO (EMIOSDIO1CMDO),
.EMIOSDIO1CMDTN (EMIOSDIO1CMDTN),
.EMIOSDIO1DATAI (emiosdio1datai),
.EMIOSDIO1DATAO (EMIOSDIO1DATAO),
.EMIOSDIO1DATATN (EMIOSDIO1DATATN),
.EMIOSDIO1LED (EMIOSDIO1LED),
.EMIOSDIO1WP (emiosdio1wp),
.EMIOSPI0MI (emiospi0mi),
.EMIOSPI0MO (EMIOSPI0MO),
.EMIOSPI0MOTN (EMIOSPI0MOTN),
.EMIOSPI0SCLKI (emiospi0sclki),
.EMIOSPI0SCLKO (EMIOSPI0SCLKO),
.EMIOSPI0SCLKTN (EMIOSPI0SCLKTN),
.EMIOSPI0SI (emiospi0si),
.EMIOSPI0SO (EMIOSPI0SO),
.EMIOSPI0SSIN (emiospi0ssin),
.EMIOSPI0SSNTN (EMIOSPI0SSNTN),
.EMIOSPI0SSON (EMIOSPI0SSON),
.EMIOSPI0STN (EMIOSPI0STN),
.EMIOSPI1MI (emiospi1mi),
.EMIOSPI1MO (EMIOSPI1MO),
.EMIOSPI1MOTN (EMIOSPI1MOTN),
.EMIOSPI1SCLKI (emiospi1sclki),
.EMIOSPI1SCLKO (EMIOSPI1SCLKO),
.EMIOSPI1SCLKTN (EMIOSPI1SCLKTN),
.EMIOSPI1SI (emiospi1si),
.EMIOSPI1SO (EMIOSPI1SO),
.EMIOSPI1SSIN (emiospi1ssin),
.EMIOSPI1SSNTN (EMIOSPI1SSNTN),
.EMIOSPI1SSON (EMIOSPI1SSON),
.EMIOSPI1STN (EMIOSPI1STN),
.EMIOSRAMINTIN (emiosramintin),
.EMIOTRACECLK (emiotraceclk),
.EMIOTRACECTL (EMIOTRACECTL),
.EMIOTRACEDATA (EMIOTRACEDATA),
.EMIOTTC0CLKI (emiottc0clki),
.EMIOTTC0WAVEO (EMIOTTC0WAVEO),
.EMIOTTC1CLKI (emiottc1clki),
.EMIOTTC1WAVEO (EMIOTTC1WAVEO),
.EMIOUART0CTSN (emiouart0ctsn),
.EMIOUART0DCDN (emiouart0dcdn),
.EMIOUART0DSRN (emiouart0dsrn),
.EMIOUART0DTRN (EMIOUART0DTRN),
.EMIOUART0RIN (emiouart0rin),
.EMIOUART0RTSN (EMIOUART0RTSN),
.EMIOUART0RX (emiouart0rx),
.EMIOUART0TX (EMIOUART0TX),
.EMIOUART1CTSN (emiouart1ctsn),
.EMIOUART1DCDN (emiouart1dcdn),
.EMIOUART1DSRN (emiouart1dsrn),
.EMIOUART1DTRN (EMIOUART1DTRN),
.EMIOUART1RIN (emiouart1rin),
.EMIOUART1RTSN (EMIOUART1RTSN),
.EMIOUART1RX (emiouart1rx),
.EMIOUART1TX (EMIOUART1TX),
.EMIOUSB0PORTINDCTL (EMIOUSB0PORTINDCTL),
.EMIOUSB0VBUSPWRFAULT (emiousb0vbuspwrfault),
.EMIOUSB0VBUSPWRSELECT (EMIOUSB0VBUSPWRSELECT),
.EMIOUSB1PORTINDCTL (EMIOUSB1PORTINDCTL),
.EMIOUSB1VBUSPWRFAULT (emiousb1vbuspwrfault),
.EMIOUSB1VBUSPWRSELECT (EMIOUSB1VBUSPWRSELECT),
.EMIOWDTCLKI (emiowdtclki),
.EMIOWDTRSTO (EMIOWDTRSTO),
.EVENTEVENTI (eventeventi),
.EVENTEVENTO (EVENTEVENTO),
.EVENTSTANDBYWFE (EVENTSTANDBYWFE),
.EVENTSTANDBYWFI (EVENTSTANDBYWFI),
.FCLKCLK (FCLKCLK),
.FCLKCLKTRIGN (fclkclktrign),
.FCLKRESETN (FCLKRESETN),
.FPGAIDLEN (fpgaidlen),
.FTMDTRACEINATID (ftmdtraceinatid),
.FTMDTRACEINCLOCK (ftmdtraceinclock),
.FTMDTRACEINDATA (ftmdtraceindata),
.FTMDTRACEINVALID (ftmdtraceinvalid),
.FTMTF2PDEBUG (ftmtf2pdebug),
.FTMTF2PTRIG (ftmtf2ptrig),
.FTMTF2PTRIGACK (FTMTF2PTRIGACK),
.FTMTP2FDEBUG (FTMTP2FDEBUG),
.FTMTP2FTRIG (FTMTP2FTRIG),
.FTMTP2FTRIGACK (ftmtp2ftrigack),
.IRQF2P (irqf2p),
.IRQP2F (IRQP2F),
.MAXIGP0ACLK (maxigp0aclk),
.MAXIGP0ARADDR (MAXIGP0ARADDR),
.MAXIGP0ARBURST (MAXIGP0ARBURST),
.MAXIGP0ARCACHE (MAXIGP0ARCACHE),
.MAXIGP0ARESETN (MAXIGP0ARESETN),
.MAXIGP0ARID (MAXIGP0ARID),
.MAXIGP0ARLEN (MAXIGP0ARLEN),
.MAXIGP0ARLOCK (MAXIGP0ARLOCK),
.MAXIGP0ARPROT (MAXIGP0ARPROT),
.MAXIGP0ARQOS (MAXIGP0ARQOS),
.MAXIGP0ARREADY (maxigp0arready),
.MAXIGP0ARSIZE (MAXIGP0ARSIZE),
.MAXIGP0ARVALID (MAXIGP0ARVALID),
.MAXIGP0AWADDR (MAXIGP0AWADDR),
.MAXIGP0AWBURST (MAXIGP0AWBURST),
.MAXIGP0AWCACHE (MAXIGP0AWCACHE),
.MAXIGP0AWID (MAXIGP0AWID),
.MAXIGP0AWLEN (MAXIGP0AWLEN),
.MAXIGP0AWLOCK (MAXIGP0AWLOCK),
.MAXIGP0AWPROT (MAXIGP0AWPROT),
.MAXIGP0AWQOS (MAXIGP0AWQOS),
.MAXIGP0AWREADY (maxigp0awready),
.MAXIGP0AWSIZE (MAXIGP0AWSIZE),
.MAXIGP0AWVALID (MAXIGP0AWVALID),
.MAXIGP0BID (maxigp0bid),
.MAXIGP0BREADY (MAXIGP0BREADY),
.MAXIGP0BRESP (maxigp0bresp),
.MAXIGP0BVALID (maxigp0bvalid),
.MAXIGP0RDATA (maxigp0rdata),
.MAXIGP0RID (maxigp0rid),
.MAXIGP0RLAST (maxigp0rlast),
.MAXIGP0RREADY (MAXIGP0RREADY),
.MAXIGP0RRESP (maxigp0rresp),
.MAXIGP0RVALID (maxigp0rvalid),
.MAXIGP0WDATA (MAXIGP0WDATA),
.MAXIGP0WID (MAXIGP0WID),
.MAXIGP0WLAST (MAXIGP0WLAST),
.MAXIGP0WREADY (maxigp0wready),
.MAXIGP0WSTRB (MAXIGP0WSTRB),
.MAXIGP0WVALID (MAXIGP0WVALID),
.MAXIGP1ACLK (maxigp1aclk),
.MAXIGP1ARADDR (MAXIGP1ARADDR),
.MAXIGP1ARBURST (MAXIGP1ARBURST),
.MAXIGP1ARCACHE (MAXIGP1ARCACHE),
.MAXIGP1ARESETN (MAXIGP1ARESETN),
.MAXIGP1ARID (MAXIGP1ARID),
.MAXIGP1ARLEN (MAXIGP1ARLEN),
.MAXIGP1ARLOCK (MAXIGP1ARLOCK),
.MAXIGP1ARPROT (MAXIGP1ARPROT),
.MAXIGP1ARQOS (MAXIGP1ARQOS),
.MAXIGP1ARREADY (maxigp1arready),
.MAXIGP1ARSIZE (MAXIGP1ARSIZE),
.MAXIGP1ARVALID (MAXIGP1ARVALID),
.MAXIGP1AWADDR (MAXIGP1AWADDR),
.MAXIGP1AWBURST (MAXIGP1AWBURST),
.MAXIGP1AWCACHE (MAXIGP1AWCACHE),
.MAXIGP1AWID (MAXIGP1AWID),
.MAXIGP1AWLEN (MAXIGP1AWLEN),
.MAXIGP1AWLOCK (MAXIGP1AWLOCK),
.MAXIGP1AWPROT (MAXIGP1AWPROT),
.MAXIGP1AWQOS (MAXIGP1AWQOS),
.MAXIGP1AWREADY (maxigp1awready),
.MAXIGP1AWSIZE (MAXIGP1AWSIZE),
.MAXIGP1AWVALID (MAXIGP1AWVALID),
.MAXIGP1BID (maxigp1bid),
.MAXIGP1BREADY (MAXIGP1BREADY),
.MAXIGP1BRESP (maxigp1bresp),
.MAXIGP1BVALID (maxigp1bvalid),
.MAXIGP1RDATA (maxigp1rdata),
.MAXIGP1RID (maxigp1rid),
.MAXIGP1RLAST (maxigp1rlast),
.MAXIGP1RREADY (MAXIGP1RREADY),
.MAXIGP1RRESP (maxigp1rresp),
.MAXIGP1RVALID (maxigp1rvalid),
.MAXIGP1WDATA (MAXIGP1WDATA),
.MAXIGP1WID (MAXIGP1WID),
.MAXIGP1WLAST (MAXIGP1WLAST),
.MAXIGP1WREADY (maxigp1wready),
.MAXIGP1WSTRB (MAXIGP1WSTRB),
.MAXIGP1WVALID (MAXIGP1WVALID),
.SAXIACPACLK (saxiacpaclk),
.SAXIACPARADDR (saxiacparaddr),
.SAXIACPARBURST (saxiacparburst),
.SAXIACPARCACHE (saxiacparcache),
.SAXIACPARESETN (SAXIACPARESETN),
.SAXIACPARID (saxiacparid),
.SAXIACPARLEN (saxiacparlen),
.SAXIACPARLOCK (saxiacparlock),
.SAXIACPARPROT (saxiacparprot),
.SAXIACPARQOS (saxiacparqos),
.SAXIACPARREADY (SAXIACPARREADY),
.SAXIACPARSIZE (saxiacparsize),
.SAXIACPARUSER (saxiacparuser),
.SAXIACPARVALID (saxiacparvalid),
.SAXIACPAWADDR (saxiacpawaddr),
.SAXIACPAWBURST (saxiacpawburst),
.SAXIACPAWCACHE (saxiacpawcache),
.SAXIACPAWID (saxiacpawid),
.SAXIACPAWLEN (saxiacpawlen),
.SAXIACPAWLOCK (saxiacpawlock),
.SAXIACPAWPROT (saxiacpawprot),
.SAXIACPAWQOS (saxiacpawqos),
.SAXIACPAWREADY (SAXIACPAWREADY),
.SAXIACPAWSIZE (saxiacpawsize),
.SAXIACPAWUSER (saxiacpawuser),
.SAXIACPAWVALID (saxiacpawvalid),
.SAXIACPBID (SAXIACPBID),
.SAXIACPBREADY (saxiacpbready),
.SAXIACPBRESP (SAXIACPBRESP),
.SAXIACPBVALID (SAXIACPBVALID),
.SAXIACPRDATA (SAXIACPRDATA),
.SAXIACPRID (SAXIACPRID),
.SAXIACPRLAST (SAXIACPRLAST),
.SAXIACPRREADY (saxiacprready),
.SAXIACPRRESP (SAXIACPRRESP),
.SAXIACPRVALID (SAXIACPRVALID),
.SAXIACPWDATA (saxiacpwdata),
.SAXIACPWID (saxiacpwid),
.SAXIACPWLAST (saxiacpwlast),
.SAXIACPWREADY (SAXIACPWREADY),
.SAXIACPWSTRB (saxiacpwstrb),
.SAXIACPWVALID (saxiacpwvalid),
.SAXIGP0ACLK (saxigp0aclk),
.SAXIGP0ARADDR (saxigp0araddr),
.SAXIGP0ARBURST (saxigp0arburst),
.SAXIGP0ARCACHE (saxigp0arcache),
.SAXIGP0ARESETN (SAXIGP0ARESETN),
.SAXIGP0ARID (saxigp0arid),
.SAXIGP0ARLEN (saxigp0arlen),
.SAXIGP0ARLOCK (saxigp0arlock),
.SAXIGP0ARPROT (saxigp0arprot),
.SAXIGP0ARQOS (saxigp0arqos),
.SAXIGP0ARREADY (SAXIGP0ARREADY),
.SAXIGP0ARSIZE (saxigp0arsize),
.SAXIGP0ARVALID (saxigp0arvalid),
.SAXIGP0AWADDR (saxigp0awaddr),
.SAXIGP0AWBURST (saxigp0awburst),
.SAXIGP0AWCACHE (saxigp0awcache),
.SAXIGP0AWID (saxigp0awid),
.SAXIGP0AWLEN (saxigp0awlen),
.SAXIGP0AWLOCK (saxigp0awlock),
.SAXIGP0AWPROT (saxigp0awprot),
.SAXIGP0AWQOS (saxigp0awqos),
.SAXIGP0AWREADY (SAXIGP0AWREADY),
.SAXIGP0AWSIZE (saxigp0awsize),
.SAXIGP0AWVALID (saxigp0awvalid),
.SAXIGP0BID (SAXIGP0BID),
.SAXIGP0BREADY (saxigp0bready),
.SAXIGP0BRESP (SAXIGP0BRESP),
.SAXIGP0BVALID (SAXIGP0BVALID),
.SAXIGP0RDATA (SAXIGP0RDATA),
.SAXIGP0RID (SAXIGP0RID),
.SAXIGP0RLAST (SAXIGP0RLAST),
.SAXIGP0RREADY (saxigp0rready),
.SAXIGP0RRESP (SAXIGP0RRESP),
.SAXIGP0RVALID (SAXIGP0RVALID),
.SAXIGP0WDATA (saxigp0wdata),
.SAXIGP0WID (saxigp0wid),
.SAXIGP0WLAST (saxigp0wlast),
.SAXIGP0WREADY (SAXIGP0WREADY),
.SAXIGP0WSTRB (saxigp0wstrb),
.SAXIGP0WVALID (saxigp0wvalid),
.SAXIGP1ACLK (saxigp1aclk),
.SAXIGP1ARADDR (saxigp1araddr),
.SAXIGP1ARBURST (saxigp1arburst),
.SAXIGP1ARCACHE (saxigp1arcache),
.SAXIGP1ARESETN (SAXIGP1ARESETN),
.SAXIGP1ARID (saxigp1arid),
.SAXIGP1ARLEN (saxigp1arlen),
.SAXIGP1ARLOCK (saxigp1arlock),
.SAXIGP1ARPROT (saxigp1arprot),
.SAXIGP1ARQOS (saxigp1arqos),
.SAXIGP1ARREADY (SAXIGP1ARREADY),
.SAXIGP1ARSIZE (saxigp1arsize),
.SAXIGP1ARVALID (saxigp1arvalid),
.SAXIGP1AWADDR (saxigp1awaddr),
.SAXIGP1AWBURST (saxigp1awburst),
.SAXIGP1AWCACHE (saxigp1awcache),
.SAXIGP1AWID (saxigp1awid),
.SAXIGP1AWLEN (saxigp1awlen),
.SAXIGP1AWLOCK (saxigp1awlock),
.SAXIGP1AWPROT (saxigp1awprot),
.SAXIGP1AWQOS (saxigp1awqos),
.SAXIGP1AWREADY (SAXIGP1AWREADY),
.SAXIGP1AWSIZE (saxigp1awsize),
.SAXIGP1AWVALID (saxigp1awvalid),
.SAXIGP1BID (SAXIGP1BID),
.SAXIGP1BREADY (saxigp1bready),
.SAXIGP1BRESP (SAXIGP1BRESP),
.SAXIGP1BVALID (SAXIGP1BVALID),
.SAXIGP1RDATA (SAXIGP1RDATA),
.SAXIGP1RID (SAXIGP1RID),
.SAXIGP1RLAST (SAXIGP1RLAST),
.SAXIGP1RREADY (saxigp1rready),
.SAXIGP1RRESP (SAXIGP1RRESP),
.SAXIGP1RVALID (SAXIGP1RVALID),
.SAXIGP1WDATA (saxigp1wdata),
.SAXIGP1WID (saxigp1wid),
.SAXIGP1WLAST (saxigp1wlast),
.SAXIGP1WREADY (SAXIGP1WREADY),
.SAXIGP1WSTRB (saxigp1wstrb),
.SAXIGP1WVALID (saxigp1wvalid),
.SAXIHP0ACLK (saxihp0aclk),
.SAXIHP0ARADDR (saxihp0araddr),
.SAXIHP0ARBURST (saxihp0arburst),
.SAXIHP0ARCACHE (saxihp0arcache),
.SAXIHP0ARESETN (SAXIHP0ARESETN),
.SAXIHP0ARID (saxihp0arid),
.SAXIHP0ARLEN (saxihp0arlen),
.SAXIHP0ARLOCK (saxihp0arlock),
.SAXIHP0ARPROT (saxihp0arprot),
.SAXIHP0ARQOS (saxihp0arqos),
.SAXIHP0ARREADY (SAXIHP0ARREADY),
.SAXIHP0ARSIZE (saxihp0arsize),
.SAXIHP0ARVALID (saxihp0arvalid),
.SAXIHP0AWADDR (saxihp0awaddr),
.SAXIHP0AWBURST (saxihp0awburst),
.SAXIHP0AWCACHE (saxihp0awcache),
.SAXIHP0AWID (saxihp0awid),
.SAXIHP0AWLEN (saxihp0awlen),
.SAXIHP0AWLOCK (saxihp0awlock),
.SAXIHP0AWPROT (saxihp0awprot),
.SAXIHP0AWQOS (saxihp0awqos),
.SAXIHP0AWREADY (SAXIHP0AWREADY),
.SAXIHP0AWSIZE (saxihp0awsize),
.SAXIHP0AWVALID (saxihp0awvalid),
.SAXIHP0BID (SAXIHP0BID),
.SAXIHP0BREADY (saxihp0bready),
.SAXIHP0BRESP (SAXIHP0BRESP),
.SAXIHP0BVALID (SAXIHP0BVALID),
.SAXIHP0RACOUNT (SAXIHP0RACOUNT),
.SAXIHP0RCOUNT (SAXIHP0RCOUNT),
.SAXIHP0RDATA (SAXIHP0RDATA),
.SAXIHP0RDISSUECAP1EN (saxihp0rdissuecap1en),
.SAXIHP0RID (SAXIHP0RID),
.SAXIHP0RLAST (SAXIHP0RLAST),
.SAXIHP0RREADY (saxihp0rready),
.SAXIHP0RRESP (SAXIHP0RRESP),
.SAXIHP0RVALID (SAXIHP0RVALID),
.SAXIHP0WACOUNT (SAXIHP0WACOUNT),
.SAXIHP0WCOUNT (SAXIHP0WCOUNT),
.SAXIHP0WDATA (saxihp0wdata),
.SAXIHP0WID (saxihp0wid),
.SAXIHP0WLAST (saxihp0wlast),
.SAXIHP0WREADY (SAXIHP0WREADY),
.SAXIHP0WRISSUECAP1EN (saxihp0wrissuecap1en),
.SAXIHP0WSTRB (saxihp0wstrb),
.SAXIHP0WVALID (saxihp0wvalid),
.SAXIHP1ACLK (saxihp1aclk),
.SAXIHP1ARADDR (saxihp1araddr),
.SAXIHP1ARBURST (saxihp1arburst),
.SAXIHP1ARCACHE (saxihp1arcache),
.SAXIHP1ARESETN (SAXIHP1ARESETN),
.SAXIHP1ARID (saxihp1arid),
.SAXIHP1ARLEN (saxihp1arlen),
.SAXIHP1ARLOCK (saxihp1arlock),
.SAXIHP1ARPROT (saxihp1arprot),
.SAXIHP1ARQOS (saxihp1arqos),
.SAXIHP1ARREADY (SAXIHP1ARREADY),
.SAXIHP1ARSIZE (saxihp1arsize),
.SAXIHP1ARVALID (saxihp1arvalid),
.SAXIHP1AWADDR (saxihp1awaddr),
.SAXIHP1AWBURST (saxihp1awburst),
.SAXIHP1AWCACHE (saxihp1awcache),
.SAXIHP1AWID (saxihp1awid),
.SAXIHP1AWLEN (saxihp1awlen),
.SAXIHP1AWLOCK (saxihp1awlock),
.SAXIHP1AWPROT (saxihp1awprot),
.SAXIHP1AWQOS (saxihp1awqos),
.SAXIHP1AWREADY (SAXIHP1AWREADY),
.SAXIHP1AWSIZE (saxihp1awsize),
.SAXIHP1AWVALID (saxihp1awvalid),
.SAXIHP1BID (SAXIHP1BID),
.SAXIHP1BREADY (saxihp1bready),
.SAXIHP1BRESP (SAXIHP1BRESP),
.SAXIHP1BVALID (SAXIHP1BVALID),
.SAXIHP1RACOUNT (SAXIHP1RACOUNT),
.SAXIHP1RCOUNT (SAXIHP1RCOUNT),
.SAXIHP1RDATA (SAXIHP1RDATA),
.SAXIHP1RDISSUECAP1EN (saxihp1rdissuecap1en),
.SAXIHP1RID (SAXIHP1RID),
.SAXIHP1RLAST (SAXIHP1RLAST),
.SAXIHP1RREADY (saxihp1rready),
.SAXIHP1RRESP (SAXIHP1RRESP),
.SAXIHP1RVALID (SAXIHP1RVALID),
.SAXIHP1WACOUNT (SAXIHP1WACOUNT),
.SAXIHP1WCOUNT (SAXIHP1WCOUNT),
.SAXIHP1WDATA (saxihp1wdata),
.SAXIHP1WID (saxihp1wid),
.SAXIHP1WLAST (saxihp1wlast),
.SAXIHP1WREADY (SAXIHP1WREADY),
.SAXIHP1WRISSUECAP1EN (saxihp1wrissuecap1en),
.SAXIHP1WSTRB (saxihp1wstrb),
.SAXIHP1WVALID (saxihp1wvalid),
.SAXIHP2ACLK (saxihp2aclk),
.SAXIHP2ARADDR (saxihp2araddr),
.SAXIHP2ARBURST (saxihp2arburst),
.SAXIHP2ARCACHE (saxihp2arcache),
.SAXIHP2ARESETN (SAXIHP2ARESETN),
.SAXIHP2ARID (saxihp2arid),
.SAXIHP2ARLEN (saxihp2arlen),
.SAXIHP2ARLOCK (saxihp2arlock),
.SAXIHP2ARPROT (saxihp2arprot),
.SAXIHP2ARQOS (saxihp2arqos),
.SAXIHP2ARREADY (SAXIHP2ARREADY),
.SAXIHP2ARSIZE (saxihp2arsize),
.SAXIHP2ARVALID (saxihp2arvalid),
.SAXIHP2AWADDR (saxihp2awaddr),
.SAXIHP2AWBURST (saxihp2awburst),
.SAXIHP2AWCACHE (saxihp2awcache),
.SAXIHP2AWID (saxihp2awid),
.SAXIHP2AWLEN (saxihp2awlen),
.SAXIHP2AWLOCK (saxihp2awlock),
.SAXIHP2AWPROT (saxihp2awprot),
.SAXIHP2AWQOS (saxihp2awqos),
.SAXIHP2AWREADY (SAXIHP2AWREADY),
.SAXIHP2AWSIZE (saxihp2awsize),
.SAXIHP2AWVALID (saxihp2awvalid),
.SAXIHP2BID (SAXIHP2BID),
.SAXIHP2BREADY (saxihp2bready),
.SAXIHP2BRESP (SAXIHP2BRESP),
.SAXIHP2BVALID (SAXIHP2BVALID),
.SAXIHP2RACOUNT (SAXIHP2RACOUNT),
.SAXIHP2RCOUNT (SAXIHP2RCOUNT),
.SAXIHP2RDATA (SAXIHP2RDATA),
.SAXIHP2RDISSUECAP1EN (saxihp2rdissuecap1en),
.SAXIHP2RID (SAXIHP2RID),
.SAXIHP2RLAST (SAXIHP2RLAST),
.SAXIHP2RREADY (saxihp2rready),
.SAXIHP2RRESP (SAXIHP2RRESP),
.SAXIHP2RVALID (SAXIHP2RVALID),
.SAXIHP2WACOUNT (SAXIHP2WACOUNT),
.SAXIHP2WCOUNT (SAXIHP2WCOUNT),
.SAXIHP2WDATA (saxihp2wdata),
.SAXIHP2WID (saxihp2wid),
.SAXIHP2WLAST (saxihp2wlast),
.SAXIHP2WREADY (SAXIHP2WREADY),
.SAXIHP2WRISSUECAP1EN (saxihp2wrissuecap1en),
.SAXIHP2WSTRB (saxihp2wstrb),
.SAXIHP2WVALID (saxihp2wvalid),
.SAXIHP3ACLK (saxihp3aclk),
.SAXIHP3ARADDR (saxihp3araddr),
.SAXIHP3ARBURST (saxihp3arburst),
.SAXIHP3ARCACHE (saxihp3arcache),
.SAXIHP3ARESETN (SAXIHP3ARESETN),
.SAXIHP3ARID (saxihp3arid),
.SAXIHP3ARLEN (saxihp3arlen),
.SAXIHP3ARLOCK (saxihp3arlock),
.SAXIHP3ARPROT (saxihp3arprot),
.SAXIHP3ARQOS (saxihp3arqos),
.SAXIHP3ARREADY (SAXIHP3ARREADY),
.SAXIHP3ARSIZE (saxihp3arsize),
.SAXIHP3ARVALID (saxihp3arvalid),
.SAXIHP3AWADDR (saxihp3awaddr),
.SAXIHP3AWBURST (saxihp3awburst),
.SAXIHP3AWCACHE (saxihp3awcache),
.SAXIHP3AWID (saxihp3awid),
.SAXIHP3AWLEN (saxihp3awlen),
.SAXIHP3AWLOCK (saxihp3awlock),
.SAXIHP3AWPROT (saxihp3awprot),
.SAXIHP3AWQOS (saxihp3awqos),
.SAXIHP3AWREADY (SAXIHP3AWREADY),
.SAXIHP3AWSIZE (saxihp3awsize),
.SAXIHP3AWVALID (saxihp3awvalid),
.SAXIHP3BID (SAXIHP3BID),
.SAXIHP3BREADY (saxihp3bready),
.SAXIHP3BRESP (SAXIHP3BRESP),
.SAXIHP3BVALID (SAXIHP3BVALID),
.SAXIHP3RACOUNT (SAXIHP3RACOUNT),
.SAXIHP3RCOUNT (SAXIHP3RCOUNT),
.SAXIHP3RDATA (SAXIHP3RDATA),
.SAXIHP3RDISSUECAP1EN (saxihp3rdissuecap1en),
.SAXIHP3RID (SAXIHP3RID),
.SAXIHP3RLAST (SAXIHP3RLAST),
.SAXIHP3RREADY (saxihp3rready),
.SAXIHP3RRESP (SAXIHP3RRESP),
.SAXIHP3RVALID (SAXIHP3RVALID),
.SAXIHP3WACOUNT (SAXIHP3WACOUNT),
.SAXIHP3WCOUNT (SAXIHP3WCOUNT),
.SAXIHP3WDATA (saxihp3wdata),
.SAXIHP3WID (saxihp3wid),
.SAXIHP3WLAST (saxihp3wlast),
.SAXIHP3WREADY (SAXIHP3WREADY),
.SAXIHP3WRISSUECAP1EN (saxihp3wrissuecap1en),
.SAXIHP3WSTRB (saxihp3wstrb),
.SAXIHP3WVALID (saxihp3wvalid)
);
endmodule |
module CARRY4_FIX(output O0, O1, O2, O3, CO0, CO1, CO2, CO3, input CYINIT, CIN, DI0, DI1, DI2, DI3, S0, S1, S2, S3);
parameter CYINIT_AX = 1'b0;
parameter CYINIT_C0 = 1'b0;
parameter CYINIT_C1 = 1'b0;
if(CYINIT_AX) begin
CARRY4_VPR #(
.CYINIT_AX(1'b1),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO0),
.CO1(CO1),
.CO2(CO2),
.CO3(CO3),
.CYINIT(CYINIT),
.O0(O0),
.O1(O1),
.O2(O2),
.O3(O3),
.DI0(DI0),
.DI1(DI1),
.DI2(DI2),
.DI3(DI3),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3)
);
end else if(CYINIT_C0 || CYINIT_C1) begin
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(CYINIT_C0),
.CYINIT_C1(CYINIT_C1)
) _TECHMAP_REPLACE_ (
.CO0(CO0),
.CO1(CO1),
.CO2(CO2),
.CO3(CO3),
.O0(O0),
.O1(O1),
.O2(O2),
.O3(O3),
.DI0(DI0),
.DI1(DI1),
.DI2(DI2),
.DI3(DI3),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3)
);
end else begin
CARRY4_VPR #(
.CYINIT_AX(1'b0),
.CYINIT_C0(1'b0),
.CYINIT_C1(1'b0)
) _TECHMAP_REPLACE_ (
.CO0(CO0),
.CO1(CO1),
.CO2(CO2),
.CO3(CO3),
.O0(O0),
.O1(O1),
.O2(O2),
.O3(O3),
.DI0(DI0),
.DI1(DI1),
.DI2(DI2),
.DI3(DI3),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3),
.CIN(CIN)
);
end
endmodule |
module IBUFDS_GTE2 (
output O,
output ODIV2,
input CEB,
input I,
input IB
);
parameter CLKCM_CFG = "TRUE";
parameter CLKRCV_TRST = "TRUE";
parameter [1:0] CLKSWING_CFG = 2'b11;
parameter IO_LOC_PAIRS = "NONE";
wire ipad_p_O, ipad_n_O;
IPAD_GTP_VPR IPAD_P (
.I(I),
.O(ipad_p_O)
);
IPAD_GTP_VPR IPAD_N (
.I(IB),
.O(ipad_n_O)
);
IBUFDS_GTE2_VPR #(
.CLKCM_CFG(CLKCM_CFG == "TRUE"),
.CLKRCV_TRST(CLKRCV_TRST == "TRUE"),
.CLKSWING_CFG(CLKSWING_CFG),
.IO_LOC_PAIRS(IO_LOC_PAIRS)
) IBUFDS_GTE2_INST (
.O(O),
.ODIV2(ODIV2),
.CEB(CEB),
.I(ipad_p_O),
.IB(ipad_n_O)
);
endmodule |
module GTPE2_COMMON (
output DRPRDY,
output PLL0FBCLKLOST,
output PLL0LOCK,
output PLL0OUTCLK,
output PLL0OUTREFCLK,
output PLL0REFCLKLOST,
output PLL1FBCLKLOST,
output PLL1LOCK,
output PLL1OUTCLK,
output PLL1OUTREFCLK,
output PLL1REFCLKLOST,
output REFCLKOUTMONITOR0,
output REFCLKOUTMONITOR1,
output [15:0] DRPDO,
output [15:0] PMARSVDOUT,
output [7:0] DMONITOROUT,
input BGBYPASSB,
input BGMONITORENB,
input BGPDB,
input BGRCALOVRDENB,
input DRPCLK,
input DRPEN,
input DRPWE,
input GTREFCLK0,
input GTREFCLK1,
input GTGREFCLK0,
input GTGREFCLK1,
input PLL0LOCKDETCLK,
input PLL0LOCKEN,
input PLL0PD,
input PLL0RESET,
input PLL1LOCKDETCLK,
input PLL1LOCKEN,
input PLL1PD,
input PLL1RESET,
input RCALENB,
input [15:0] DRPDI,
input [2:0] PLL0REFCLKSEL,
input [2:0] PLL1REFCLKSEL,
input [4:0] BGRCALOVRD,
input [7:0] DRPADDR,
input [7:0] PMARSVD
);
parameter [63:0] BIAS_CFG = 64'h0000000000000000;
parameter [31:0] COMMON_CFG = 32'h00000000;
parameter [26:0] PLL0_CFG = 27'h01F03DC;
parameter [0:0] PLL0_DMON_CFG = 1'b0;
parameter [23:0] PLL0_INIT_CFG = 24'h00001E;
parameter [8:0] PLL0_LOCK_CFG = 9'h1E8;
parameter [26:0] PLL1_CFG = 27'h01F03DC;
parameter [0:0] PLL1_DMON_CFG = 1'b0;
parameter [23:0] PLL1_INIT_CFG = 24'h00001E;
parameter [8:0] PLL1_LOCK_CFG = 9'h1E8;
parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000;
parameter [15:0] RSVD_ATTR0 = 16'h0000;
parameter [15:0] RSVD_ATTR1 = 16'h0000;
parameter integer PLL0_REFCLK_DIV = 1;
parameter integer PLL0_FBDIV = 4;
parameter integer PLL0_FBDIV_45 = 5;
parameter integer PLL1_REFCLK_DIV = 1;
parameter integer PLL1_FBDIV = 4;
parameter integer PLL1_FBDIV_45 = 5;
localparam [4:0] PLL0_REFCLK_DIV_BIN = PLL0_REFCLK_DIV == 1 ? 5'b10000 : 5'b00000;
localparam [4:0] PLL1_REFCLK_DIV_BIN = PLL1_REFCLK_DIV == 1 ? 5'b10000 : 5'b00000;
localparam [5:0] PLL0_FBDIV_BIN = PLL0_FBDIV == 1 ? 6'b010000 :
PLL0_FBDIV == 2 ? 6'b000000 :
PLL0_FBDIV == 3 ? 6'b000001 :
PLL0_FBDIV == 4 ? 6'b000010 :
/*PLL0_FBDIV == 5*/ 6'b000011;
localparam [5:0] PLL1_FBDIV_BIN = PLL1_FBDIV == 1 ? 6'b010000 :
PLL1_FBDIV == 2 ? 6'b000000 :
PLL1_FBDIV == 3 ? 6'b000001 :
PLL1_FBDIV == 4 ? 6'b000010 :
/*PLL1_FBDIV == 5*/ 6'b000011;
localparam PLL0_FBDIV_45_BIN = PLL0_FBDIV_45 == 4 ? 1'b0 : 1'b1;
localparam PLL1_FBDIV_45_BIN = PLL1_FBDIV_45 == 4 ? 1'b0 : 1'b1;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0;
parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0;
parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0;
parameter _TECHMAP_CONSTMSK_DRPCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DRPCLK_ = 0;
parameter _TECHMAP_CONSTMSK_PLL0LOCKDETCLK_ = 0;
parameter _TECHMAP_CONSTVAL_PLL0LOCKDETCLK_ = 0;
parameter _TECHMAP_CONSTMSK_PLL1LOCKDETCLK_ = 0;
parameter _TECHMAP_CONSTVAL_PLL1LOCKDETCLK_ = 0;
localparam [0:0] INV_DRPCLK = (_TECHMAP_CONSTMSK_DRPCLK_ == 1) ? !_TECHMAP_CONSTVAL_DRPCLK_ ^ IS_DRPCLK_INVERTED :
(_TECHMAP_CONSTVAL_DRPCLK_ == 0) ? ~IS_DRPCLK_INVERTED : IS_DRPCLK_INVERTED;
wire drpclk = (_TECHMAP_CONSTMSK_DRPCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_DRPCLK_ == 0) ? 1'b1 : DRPCLK;
localparam [0:0] INV_PLL0LOCKDETCLK = (_TECHMAP_CONSTMSK_PLL0LOCKDETCLK_ == 1) ? !_TECHMAP_CONSTVAL_PLL0LOCKDETCLK_ ^ IS_PLL0LOCKDETCLK_INVERTED :
(_TECHMAP_CONSTVAL_PLL0LOCKDETCLK_ == 0) ? ~IS_PLL0LOCKDETCLK_INVERTED : IS_PLL0LOCKDETCLK_INVERTED;
wire pll0lockdetclk = (_TECHMAP_CONSTMSK_PLL0LOCKDETCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PLL0LOCKDETCLK_ == 0) ? 1'b1 : PLL0LOCKDETCLK;
localparam [0:0] INV_PLL1LOCKDETCLK = (_TECHMAP_CONSTMSK_PLL1LOCKDETCLK_ == 1) ? !_TECHMAP_CONSTVAL_PLL1LOCKDETCLK_ ^ IS_PLL1LOCKDETCLK_INVERTED :
(_TECHMAP_CONSTVAL_PLL1LOCKDETCLK_ == 0) ? ~IS_PLL1LOCKDETCLK_INVERTED : IS_PLL1LOCKDETCLK_INVERTED;
wire pll1lockdetclk = (_TECHMAP_CONSTMSK_PLL1LOCKDETCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_PLL1LOCKDETCLK_ == 0) ? 1'b1 : PLL1LOCKDETCLK;
parameter _TECHMAP_CONSTMSK_GTREFCLK0_ = 0;
parameter _TECHMAP_CONSTVAL_GTREFCLK0_ = 0;
parameter _TECHMAP_CONSTMSK_GTREFCLK1_ = 0;
parameter _TECHMAP_CONSTVAL_GTREFCLK1_ = 0;
localparam [0:0] GTREFCLK0_USED = (_TECHMAP_CONSTMSK_GTREFCLK0_ == 1) ? 1'b0 :
(_TECHMAP_CONSTVAL_GTREFCLK0_ === 0) ? 1'b0 : 1'b1;
localparam [0:0] GTREFCLK1_USED = (_TECHMAP_CONSTMSK_GTREFCLK1_ == 1) ? 1'b0 :
(_TECHMAP_CONSTVAL_GTREFCLK1_ === 0) ? 1'b0 : 1'b1;
localparam [0:0] BOTH_GTREFCLK_USED = GTREFCLK0_USED && GTREFCLK1_USED;
localparam [0:0] NONE_GTREFCLK_USED = !(GTREFCLK0_USED || GTREFCLK1_USED);
if (NONE_GTREFCLK_USED) begin
wire _TECHMAP_FAIL_ = 1'b1;
end
if (BOTH_GTREFCLK_USED) begin
GTPE2_COMMON_VPR #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.PLL0_CFG (PLL0_CFG),
.PLL0_DMON_CFG (PLL0_DMON_CFG),
.PLL0_FBDIV (PLL0_FBDIV_BIN),
.PLL0_FBDIV_45 (PLL0_FBDIV_45_BIN),
.PLL0_INIT_CFG (PLL0_INIT_CFG),
.PLL0_LOCK_CFG (PLL0_LOCK_CFG),
.PLL0_REFCLK_DIV (PLL0_REFCLK_DIV_BIN),
.PLL1_CFG (PLL1_CFG),
.PLL1_DMON_CFG (PLL1_DMON_CFG),
.PLL1_FBDIV (PLL1_FBDIV_BIN),
.PLL1_FBDIV_45 (PLL1_FBDIV_45_BIN),
.PLL1_INIT_CFG (PLL1_INIT_CFG),
.PLL1_LOCK_CFG (PLL1_LOCK_CFG),
.PLL1_REFCLK_DIV (PLL1_REFCLK_DIV_BIN),
.PLL_CLKOUT_CFG (PLL_CLKOUT_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.INV_DRPCLK (INV_DRPCLK),
.INV_PLL0LOCKDETCLK (INV_PLL0LOCKDETCLK),
.INV_PLL1LOCKDETCLK (INV_PLL1LOCKDETCLK),
.GTREFCLK0_USED (GTREFCLK0_USED == 1'b1),
.GTREFCLK1_USED (GTREFCLK1_USED == 1'b1),
.BOTH_GTREFCLK_USED (BOTH_GTREFCLK_USED),
.ENABLE_DRP (1'b1),
.IBUFDS_GTE2_CLKSWING_CFG (2'b11)
) _TECHMAP_REPLACE_ (
.DRPRDY (DRPRDY),
.PLL0FBCLKLOST (PLL0FBCLKLOST),
.PLL0LOCK (PLL0LOCK),
.PLL0OUTCLK (PLL0OUTCLK),
.PLL0OUTREFCLK (PLL0OUTREFCLK),
.PLL0REFCLKLOST (PLL0REFCLKLOST),
.PLL1FBCLKLOST (PLL1FBCLKLOST),
.PLL1LOCK (PLL1LOCK),
.PLL1OUTCLK (PLL1OUTCLK),
.PLL1OUTREFCLK (PLL1OUTREFCLK),
.PLL1REFCLKLOST (PLL1REFCLKLOST),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1),
.DRPDO (DRPDO),
.PMARSVDOUT (PMARSVDOUT),
.DMONITOROUT (DMONITOROUT),
.BGBYPASSB (BGBYPASSB),
.BGMONITORENB (BGMONITORENB),
.BGPDB (BGPDB),
.BGRCALOVRDENB (BGRCALOVRDENB),
.DRPCLK (drpclk),
.DRPEN (DRPEN),
.DRPWE (DRPWE),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.PLL0LOCKDETCLK (pll0lockdetclk),
.PLL0LOCKEN (PLL0LOCKEN),
.PLL0PD (PLL0PD),
.PLL0RESET (PLL0RESET),
.PLL1LOCKDETCLK (pll1lockdetclk),
.PLL1LOCKEN (PLL1LOCKEN),
.PLL1PD (PLL1PD),
.PLL1RESET (PLL1RESET),
.RCALENB (RCALENB),
.DRPDI (DRPDI),
.PLL0REFCLKSEL (PLL0REFCLKSEL),
.PLL1REFCLKSEL (PLL1REFCLKSEL),
.BGRCALOVRD (BGRCALOVRD),
.DRPADDR (DRPADDR),
.PMARSVD (PMARSVD)
);
end else if (GTREFCLK0_USED) begin
GTPE2_COMMON_VPR #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.PLL0_CFG (PLL0_CFG),
.PLL0_DMON_CFG (PLL0_DMON_CFG),
.PLL0_FBDIV (PLL0_FBDIV_BIN),
.PLL0_FBDIV_45 (PLL0_FBDIV_45_BIN),
.PLL0_INIT_CFG (PLL0_INIT_CFG),
.PLL0_LOCK_CFG (PLL0_LOCK_CFG),
.PLL0_REFCLK_DIV (PLL0_REFCLK_DIV_BIN),
.PLL1_CFG (PLL1_CFG),
.PLL1_DMON_CFG (PLL1_DMON_CFG),
.PLL1_FBDIV (PLL1_FBDIV_BIN),
.PLL1_FBDIV_45 (PLL1_FBDIV_45_BIN),
.PLL1_INIT_CFG (PLL1_INIT_CFG),
.PLL1_LOCK_CFG (PLL1_LOCK_CFG),
.PLL1_REFCLK_DIV (PLL1_REFCLK_DIV_BIN),
.PLL_CLKOUT_CFG (PLL_CLKOUT_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.INV_DRPCLK (INV_DRPCLK),
.INV_PLL0LOCKDETCLK (INV_PLL0LOCKDETCLK),
.INV_PLL1LOCKDETCLK (INV_PLL1LOCKDETCLK),
.GTREFCLK0_USED (GTREFCLK0_USED == 1'b1),
.GTREFCLK1_USED (GTREFCLK1_USED == 1'b1),
.BOTH_GTREFCLK_USED (BOTH_GTREFCLK_USED),
.ENABLE_DRP (1'b1),
.IBUFDS_GTE2_CLKSWING_CFG (2'b11)
) _TECHMAP_REPLACE_ (
.DRPRDY (DRPRDY),
.PLL0FBCLKLOST (PLL0FBCLKLOST),
.PLL0LOCK (PLL0LOCK),
.PLL0OUTCLK (PLL0OUTCLK),
.PLL0OUTREFCLK (PLL0OUTREFCLK),
.PLL0REFCLKLOST (PLL0REFCLKLOST),
.PLL1FBCLKLOST (PLL1FBCLKLOST),
.PLL1LOCK (PLL1LOCK),
.PLL1OUTCLK (PLL1OUTCLK),
.PLL1OUTREFCLK (PLL1OUTREFCLK),
.PLL1REFCLKLOST (PLL1REFCLKLOST),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1),
.DRPDO (DRPDO),
.PMARSVDOUT (PMARSVDOUT),
.DMONITOROUT (DMONITOROUT),
.BGBYPASSB (BGBYPASSB),
.BGMONITORENB (BGMONITORENB),
.BGPDB (BGPDB),
.BGRCALOVRDENB (BGRCALOVRDENB),
.DRPCLK (drpclk),
.DRPEN (DRPEN),
.DRPWE (DRPWE),
.GTREFCLK0 (GTREFCLK0),
.PLL0LOCKDETCLK (pll0lockdetclk),
.PLL0LOCKEN (PLL0LOCKEN),
.PLL0PD (PLL0PD),
.PLL0RESET (PLL0RESET),
.PLL1LOCKDETCLK (pll1lockdetclk),
.PLL1LOCKEN (PLL1LOCKEN),
.PLL1PD (PLL1PD),
.PLL1RESET (PLL1RESET),
.RCALENB (RCALENB),
.DRPDI (DRPDI),
.PLL0REFCLKSEL (PLL0REFCLKSEL),
.PLL1REFCLKSEL (PLL1REFCLKSEL),
.BGRCALOVRD (BGRCALOVRD),
.DRPADDR (DRPADDR),
.PMARSVD (PMARSVD)
);
end else begin
GTPE2_COMMON_VPR #(
.BIAS_CFG (BIAS_CFG),
.COMMON_CFG (COMMON_CFG),
.PLL0_CFG (PLL0_CFG),
.PLL0_DMON_CFG (PLL0_DMON_CFG),
.PLL0_FBDIV (PLL0_FBDIV_BIN),
.PLL0_FBDIV_45 (PLL0_FBDIV_45_BIN),
.PLL0_INIT_CFG (PLL0_INIT_CFG),
.PLL0_LOCK_CFG (PLL0_LOCK_CFG),
.PLL0_REFCLK_DIV (PLL0_REFCLK_DIV_BIN),
.PLL1_CFG (PLL1_CFG),
.PLL1_DMON_CFG (PLL1_DMON_CFG),
.PLL1_FBDIV (PLL1_FBDIV_BIN),
.PLL1_FBDIV_45 (PLL1_FBDIV_45_BIN),
.PLL1_INIT_CFG (PLL1_INIT_CFG),
.PLL1_LOCK_CFG (PLL1_LOCK_CFG),
.PLL1_REFCLK_DIV (PLL1_REFCLK_DIV_BIN),
.PLL_CLKOUT_CFG (PLL_CLKOUT_CFG),
.RSVD_ATTR0 (RSVD_ATTR0),
.RSVD_ATTR1 (RSVD_ATTR1),
.INV_DRPCLK (INV_DRPCLK),
.INV_PLL0LOCKDETCLK (INV_PLL0LOCKDETCLK),
.INV_PLL1LOCKDETCLK (INV_PLL1LOCKDETCLK),
.GTREFCLK0_USED (GTREFCLK0_USED == 1'b1),
.GTREFCLK1_USED (GTREFCLK1_USED == 1'b1),
.BOTH_GTREFCLK_USED (BOTH_GTREFCLK_USED),
.ENABLE_DRP (1'b1),
.IBUFDS_GTE2_CLKSWING_CFG (2'b11)
) _TECHMAP_REPLACE_ (
.DRPRDY (DRPRDY),
.PLL0FBCLKLOST (PLL0FBCLKLOST),
.PLL0LOCK (PLL0LOCK),
.PLL0OUTCLK (PLL0OUTCLK),
.PLL0OUTREFCLK (PLL0OUTREFCLK),
.PLL0REFCLKLOST (PLL0REFCLKLOST),
.PLL1FBCLKLOST (PLL1FBCLKLOST),
.PLL1LOCK (PLL1LOCK),
.PLL1OUTCLK (PLL1OUTCLK),
.PLL1OUTREFCLK (PLL1OUTREFCLK),
.PLL1REFCLKLOST (PLL1REFCLKLOST),
.REFCLKOUTMONITOR0 (REFCLKOUTMONITOR0),
.REFCLKOUTMONITOR1 (REFCLKOUTMONITOR1),
.DRPDO (DRPDO),
.PMARSVDOUT (PMARSVDOUT),
.DMONITOROUT (DMONITOROUT),
.BGBYPASSB (BGBYPASSB),
.BGMONITORENB (BGMONITORENB),
.BGPDB (BGPDB),
.BGRCALOVRDENB (BGRCALOVRDENB),
.DRPCLK (drpclk),
.DRPEN (DRPEN),
.DRPWE (DRPWE),
.GTREFCLK1 (GTREFCLK1),
.PLL0LOCKDETCLK (pll0lockdetclk),
.PLL0LOCKEN (PLL0LOCKEN),
.PLL0PD (PLL0PD),
.PLL0RESET (PLL0RESET),
.PLL1LOCKDETCLK (pll1lockdetclk),
.PLL1LOCKEN (PLL1LOCKEN),
.PLL1PD (PLL1PD),
.PLL1RESET (PLL1RESET),
.RCALENB (RCALENB),
.DRPDI (DRPDI),
.PLL0REFCLKSEL (PLL0REFCLKSEL),
.PLL1REFCLKSEL (PLL1REFCLKSEL),
.BGRCALOVRD (BGRCALOVRD),
.DRPADDR (DRPADDR),
.PMARSVD (PMARSVD)
);
end
endmodule |
module GTPE2_CHANNEL (
output DRPRDY,
output EYESCANDATAERROR,
output GTPTXN,
output GTPTXP,
output PHYSTATUS,
output PMARSVDOUT0,
output PMARSVDOUT1,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output RXDLYSRESETDONE,
output RXELECIDLE,
output RXHEADERVALID,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPMARESETDONE,
output RXPRBSERR,
output RXRATEDONE,
output RXRESETDONE,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output TXCOMFINISH,
output TXDLYSRESETDONE,
output TXGEARBOXREADY,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
output [14:0] DMONITOROUT,
output [15:0] DRPDO,
output [15:0] PCSRSVDOUT,
output [1:0] RXCLKCORCNT,
output [1:0] RXDATAVALID,
output [1:0] RXSTARTOFSEQ,
output [1:0] TXBUFSTATUS,
output [2:0] RXBUFSTATUS,
output [2:0] RXHEADER,
output [2:0] RXSTATUS,
output [31:0] RXDATA,
output [3:0] RXCHARISCOMMA,
output [3:0] RXCHARISK,
output [3:0] RXCHBONDO,
output [3:0] RXDISPERR,
output [3:0] RXNOTINTABLE,
output [4:0] RXPHMONITOR,
output [4:0] RXPHSLIPMONITOR,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input DMONFIFORESET,
input DMONITORCLK,
input DRPCLK,
input DRPEN,
input DRPWE,
input EYESCANMODE,
input EYESCANRESET,
input EYESCANTRIGGER,
input GTPRXN,
input GTPRXP,
input GTRESETSEL,
input GTRXRESET,
input GTTXRESET,
input PLL0CLK,
input PLL0REFCLK,
input PLL1CLK,
input PLL1REFCLK,
input PMARSVDIN0,
input PMARSVDIN1,
input PMARSVDIN2,
input PMARSVDIN3,
input PMARSVDIN4,
input RESETOVRD,
input RX8B10BEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCDRRESETRSV,
input RXCHBONDEN,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCOMMADETEN,
input RXDDIEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input RXGEARBOXSLIP,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFOVRDEN,
input RXLPMOSINTNTRLEN,
input RXLPMRESET,
input RXMCOMMAALIGNEN,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input RXOSINTEN,
input RXOSINTHOLD,
input RXOSINTNTRLEN,
input RXOSINTOVRDEN,
input RXOSINTPD,
input RXOSINTSTROBE,
input RXOSINTTESTOVRDEN,
input RXOSOVRDEN,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input RXRATEMODE,
input RXSLIDE,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input RXUSERRDY,
input RXUSRCLK2,
input RXUSRCLK,
input SETERRSTATUS,
input SIGVALIDCLK,
input TX8B10BEN,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input TXDEEMPH,
input TXDETECTRX,
input TXDIFFPD,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input TXINHIBIT,
input TXPCSRESET,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input TXPISOPD,
input TXPMARESET,
input TXPOLARITY,
input TXPOSTCURSORINV,
input TXPRBSFORCEERR,
input TXPRECURSORINV,
input TXRATEMODE,
input TXSTARTSEQ,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input TXUSERRDY,
input TXUSRCLK2,
input TXUSRCLK,
input [13:0] RXADAPTSELTEST,
input [15:0] DRPDI,
input [15:0] GTRSVD,
input [15:0] PCSRSVDIN,
input [19:0] TSTIN,
input [1:0] RXELECIDLEMODE,
input [1:0] RXPD,
input [1:0] RXSYSCLKSEL,
input [1:0] TXPD,
input [1:0] TXSYSCLKSEL,
input [2:0] LOOPBACK,
input [2:0] RXCHBONDLEVEL,
input [2:0] RXOUTCLKSEL,
input [2:0] RXPRBSSEL,
input [2:0] RXRATE,
input [2:0] TXBUFDIFFCTRL,
input [2:0] TXHEADER,
input [2:0] TXMARGIN,
input [2:0] TXOUTCLKSEL,
input [2:0] TXPRBSSEL,
input [2:0] TXRATE,
input [31:0] TXDATA,
input [3:0] RXCHBONDI,
input [3:0] RXOSINTCFG,
input [3:0] RXOSINTID0,
input [3:0] TX8B10BBYPASS,
input [3:0] TXCHARDISPMODE,
input [3:0] TXCHARDISPVAL,
input [3:0] TXCHARISK,
input [3:0] TXDIFFCTRL,
input [4:0] TXPIPPMSTEPSIZE,
input [4:0] TXPOSTCURSOR,
input [4:0] TXPRECURSOR,
input [6:0] TXMAINCURSOR,
input [6:0] TXSEQUENCE,
input [8:0] DRPADDR
);
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0;
parameter [0:0] ACJTAG_MODE = 1'b0;
parameter [0:0] ACJTAG_RESET = 1'b0;
parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111;
parameter [1:0] ALIGN_COMMA_WORD = 1;
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000;
parameter [6:0] CFOK_CFG2 = 7'b0100000;
parameter [6:0] CFOK_CFG3 = 7'b0100000;
parameter [0:0] CFOK_CFG4 = 1'b0;
parameter [1:0] CFOK_CFG5 = 2'b00;
parameter [3:0] CFOK_CFG6 = 4'b0000;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter [3:0] CHAN_BOND_MAX_SKEW = 7;
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100;
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter [0:0] CLK_COMMON_SWING = 1'b0;
parameter CLK_CORRECT_USE = "TRUE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter [5:0] CLK_COR_MAX_LAT = 20;
parameter [5:0] CLK_COR_MIN_LAT = 18;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter [4:0] CLK_COR_REPEAT_WAIT = 0;
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100;
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000;
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000;
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000;
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000;
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter integer CLK_COR_SEQ_LEN = 1;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter [23:0] DMONITOR_CFG = 24'h000A00;
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0;
parameter [5:0] ES_CONTROL = 6'b000000;
parameter ES_ERRDET_EN = "FALSE";
parameter ES_EYE_SCAN_EN = "FALSE";
parameter [11:0] ES_HORZ_OFFSET = 12'h010;
parameter [9:0] ES_PMA_CFG = 10'b0000000000;
parameter [4:0] ES_PRESCALE = 5'b00000;
parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000;
parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000;
parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000;
parameter [8:0] ES_VERT_OFFSET = 9'b000000000;
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter [2:0] GEARBOX_MODE = 3'b000;
parameter [0:0] LOOPBACK_CFG = 1'b0;
parameter [1:0] OUTREFCLK_SEL_INV = 2'b11;
parameter PCS_PCIE_EN = "FALSE";
parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000;
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C;
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19;
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64;
parameter [0:0] PMA_LOOPBACK_CFG = 1'b0;
parameter [31:0] PMA_RSV = 32'h00000333;
parameter [31:0] PMA_RSV2 = 32'h00002050;
parameter [1:0] PMA_RSV3 = 2'b00;
parameter [3:0] PMA_RSV4 = 4'b0000;
parameter [0:0] PMA_RSV5 = 1'b0;
parameter [0:0] PMA_RSV6 = 1'b0;
parameter [0:0] PMA_RSV7 = 1'b0;
parameter [4:0] RXBUFRESET_TIME = 5'b00001;
parameter RXBUF_ADDR_MODE = "FULL";
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000;
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000;
parameter RXBUF_EN = "TRUE";
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
parameter [5:0] RXBUF_THRESH_OVFLW = 61;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter [5:0] RXBUF_THRESH_UNDFLW = 4;
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001;
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001;
parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010;
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter [5:0] RXCDR_LOCK_CFG = 6'b001001;
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0;
parameter [15:0] RXDLY_CFG = 16'h0010;
parameter [8:0] RXDLY_LCFG = 9'h020;
parameter [15:0] RXDLY_TAP_CFG = 16'h0000;
parameter RXGEARBOX_EN = "FALSE";
parameter [4:0] RXISCANRESET_TIME = 5'b00001;
parameter [6:0] RXLPMRESET_TIME = 7'b0001111;
parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0;
parameter [3:0] RXLPM_CFG = 4'b0110;
parameter [0:0] RXLPM_CFG1 = 1'b0;
parameter [0:0] RXLPM_CM_CFG = 1'b0;
parameter [8:0] RXLPM_GC_CFG = 9'b111100010;
parameter [2:0] RXLPM_GC_CFG2 = 3'b001;
parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000;
parameter [4:0] RXLPM_HF_CFG2 = 5'b01010;
parameter [3:0] RXLPM_HF_CFG3 = 4'b0000;
parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0;
parameter [0:0] RXLPM_INCM_CFG = 1'b0;
parameter [0:0] RXLPM_IPCM_CFG = 1'b0;
parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000;
parameter [4:0] RXLPM_LF_CFG2 = 5'b01010;
parameter [2:0] RXLPM_OSINT_CFG = 3'b100;
parameter [6:0] RXOOB_CFG = 7'b0000110;
parameter RXOOB_CLK_CFG = "PMA";
parameter [4:0] RXOSCALRESET_TIME = 5'b00011;
parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000;
parameter integer RXOUT_DIV = 2;
parameter [4:0] RXPCSRESET_TIME = 5'b00001;
parameter [23:0] RXPHDLY_CFG = 24'h084000;
parameter [23:0] RXPH_CFG = 24'hC00002;
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000;
parameter [2:0] RXPI_CFG0 = 3'b000;
parameter [0:0] RXPI_CFG1 = 1'b0;
parameter [0:0] RXPI_CFG2 = 1'b0;
parameter [4:0] RXPMARESET_TIME = 5'b00011;
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0;
parameter [3:0] RXSLIDE_AUTO_WAIT = 7;
parameter RXSLIDE_MODE = "OFF";
parameter [0:0] RXSYNC_MULTILANE = 1'b0;
parameter [0:0] RXSYNC_OVRD = 1'b0;
parameter [0:0] RXSYNC_SKIP_DA = 1'b0;
parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011;
parameter [5:0] RX_BUFFER_CFG = 6'b000000;
parameter integer RX_CLK25_DIV = 7;
parameter [0:0] RX_CLKMUX_EN = 1'b1;
parameter [1:0] RX_CM_SEL = 2'b11;
parameter [3:0] RX_CM_TRIM = 4'b0100;
parameter integer RX_DATA_WIDTH = 20;
parameter [5:0] RX_DDI_SEL = 6'b000000;
parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter [12:0] RX_OS_CFG = 13'b0001111110000;
parameter integer RX_SIG_VALID_DLY = 10;
parameter RX_XCLK_SEL = "RXREC";
parameter [6:0] SAS_MAX_COM = 64;
parameter [5:0] SAS_MIN_COM = 36;
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111;
parameter [2:0] SATA_BURST_VAL = 3'b100;
parameter [2:0] SATA_EIDLE_VAL = 3'b100;
parameter [5:0] SATA_MAX_BURST = 8;
parameter [5:0] SATA_MAX_INIT = 21;
parameter [5:0] SATA_MAX_WAKE = 7;
parameter [5:0] SATA_MIN_BURST = 4;
parameter [5:0] SATA_MIN_INIT = 12;
parameter [5:0] SATA_MIN_WAKE = 4;
parameter SATA_PLL_CFG = "VCO_3000MHZ";
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000;
parameter [2:0] TERM_RCAL_OVRD = 3'b000;
parameter [7:0] TRANS_TIME_RATE = 8'h0E;
parameter [31:0] TST_RSV = 32'h00000000;
parameter TXBUF_EN = "TRUE";
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE";
parameter [15:0] TXDLY_CFG = 16'h0010;
parameter [8:0] TXDLY_LCFG = 9'h020;
parameter [15:0] TXDLY_TAP_CFG = 16'h0000;
parameter TXGEARBOX_EN = "FALSE";
parameter [0:0] TXOOB_CFG = 1'b0;
parameter integer TXOUT_DIV = 2;
parameter [4:0] TXPCSRESET_TIME = 5'b00001;
parameter [23:0] TXPHDLY_CFG = 24'h084000;
parameter [15:0] TXPH_CFG = 16'h0400;
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000;
parameter [1:0] TXPI_CFG0 = 2'b00;
parameter [1:0] TXPI_CFG1 = 2'b00;
parameter [1:0] TXPI_CFG2 = 2'b00;
parameter [0:0] TXPI_CFG3 = 1'b0;
parameter [0:0] TXPI_CFG4 = 1'b0;
parameter [2:0] TXPI_CFG5 = 3'b000;
parameter [0:0] TXPI_GREY_SEL = 1'b0;
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2";
parameter [7:0] TXPI_PPM_CFG = 8'b00000000;
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000;
parameter [4:0] TXPMARESET_TIME = 5'b00001;
parameter [0:0] TXSYNC_MULTILANE = 1'b0;
parameter [0:0] TXSYNC_OVRD = 1'b0;
parameter [0:0] TXSYNC_SKIP_DA = 1'b0;
parameter integer TX_CLK25_DIV = 7;
parameter [0:0] TX_CLKMUX_EN = 1'b1;
parameter integer TX_DATA_WIDTH = 20;
parameter [5:0] TX_DEEMPH0 = 6'b000000;
parameter [5:0] TX_DEEMPH1 = 6'b000000;
parameter TX_DRIVE_MODE = "DIRECT";
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0;
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110;
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001;
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101;
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010;
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110;
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100;
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010;
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000;
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000;
parameter [0:0] TX_PREDRIVER_MODE = 1'b0;
parameter [13:0] TX_RXDETECT_CFG = 14'h1832;
parameter [2:0] TX_RXDETECT_REF = 3'b100;
parameter TX_XCLK_SEL = "TXUSR";
parameter [0:0] UCODEER_CLR = 1'b0;
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0;
parameter IO_LOC_PAIRS = "NONE";
localparam [1:0] CHAN_BOND_SEQ_LEN_BIN = CHAN_BOND_SEQ_LEN - 1;
localparam [1:0] CLK_COR_SEQ_LEN_BIN = CLK_COR_SEQ_LEN - 1;
localparam [4:0] RX_CLK25_DIV_BIN = RX_CLK25_DIV - 1;
localparam [4:0] TX_CLK25_DIV_BIN = TX_CLK25_DIV - 1;
localparam [4:0] RX_SIG_VALID_DLY_BIN = RX_SIG_VALID_DLY - 1;
localparam [2:0] RX_DATA_WIDTH_BIN = RX_DATA_WIDTH == 16 ? 3'b010 :
RX_DATA_WIDTH == 20 ? 3'b011 :
RX_DATA_WIDTH == 32 ? 3'b100 :
/*RX_DATA_WIDTH == 40*/ 3'b101;
localparam [2:0] TX_DATA_WIDTH_BIN = TX_DATA_WIDTH == 16 ? 3'b010 :
TX_DATA_WIDTH == 20 ? 3'b011 :
TX_DATA_WIDTH == 32 ? 3'b100 :
/*TX_DATA_WIDTH == 40*/ 3'b101;
localparam [1:0] RXOUT_DIV_BIN = RXOUT_DIV == 1 ? 2'b00 :
RXOUT_DIV == 2 ? 2'b01 :
RXOUT_DIV == 4 ? 2'b10 :
/*RXOUT_DIV == 8*/ 2'b11;
localparam [1:0] TXOUT_DIV_BIN = TXOUT_DIV == 1 ? 2'b00 :
TXOUT_DIV == 2 ? 2'b01 :
TXOUT_DIV == 4 ? 2'b10 :
/*TXOUT_DIV == 8*/ 2'b11;
parameter _TECHMAP_CONSTMSK_TXUSRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_TXUSRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_TXUSRCLK2_ = 0;
parameter _TECHMAP_CONSTVAL_TXUSRCLK2_ = 0;
parameter _TECHMAP_CONSTMSK_TXPHDLYTSTCLK_ = 0;
parameter _TECHMAP_CONSTVAL_TXPHDLYTSTCLK_ = 0;
parameter _TECHMAP_CONSTMSK_SIGVALIDCLK_ = 0;
parameter _TECHMAP_CONSTVAL_SIGVALIDCLK_ = 0;
parameter _TECHMAP_CONSTMSK_RXUSRCLK_ = 0;
parameter _TECHMAP_CONSTVAL_RXUSRCLK_ = 0;
parameter _TECHMAP_CONSTMSK_RXUSRCLK2_ = 0;
parameter _TECHMAP_CONSTVAL_RXUSRCLK2_ = 0;
parameter _TECHMAP_CONSTVAL_DRPCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DRPCLK_ = 0;
parameter _TECHMAP_CONSTVAL_DMONITORCLK_ = 0;
parameter _TECHMAP_CONSTMSK_DMONITORCLK_ = 0;
parameter _TECHMAP_CONSTVAL_CLKRSVD0_ = 0;
parameter _TECHMAP_CONSTMSK_CLKRSVD0_ = 0;
parameter _TECHMAP_CONSTVAL_CLKRSVD1_ = 0;
parameter _TECHMAP_CONSTMSK_CLKRSVD1_ = 0;
parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0;
parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0;
parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0;
parameter [0:0] IS_DRPCLK_INVERTED = 1'b0;
parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0;
parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0;
parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0;
localparam [0:0] INV_TXUSRCLK = (_TECHMAP_CONSTMSK_TXUSRCLK_ == 1) ? !_TECHMAP_CONSTVAL_TXUSRCLK_ ^ IS_TXUSRCLK_INVERTED :
(_TECHMAP_CONSTVAL_TXUSRCLK_ == 0) ? ~IS_TXUSRCLK_INVERTED : IS_TXUSRCLK_INVERTED;
wire txusrclk = (_TECHMAP_CONSTMSK_TXUSRCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_TXUSRCLK_ == 0) ? 1'b1 : TXUSRCLK;
localparam [0:0] INV_TXUSRCLK2 = (_TECHMAP_CONSTMSK_TXUSRCLK2_ == 1) ? !_TECHMAP_CONSTVAL_TXUSRCLK2_ ^ IS_TXUSRCLK2_INVERTED :
(_TECHMAP_CONSTVAL_TXUSRCLK2_ == 0) ? ~IS_TXUSRCLK2_INVERTED : IS_TXUSRCLK2_INVERTED;
wire txusrclk2 = (_TECHMAP_CONSTMSK_TXUSRCLK2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_TXUSRCLK2_ == 0) ? 1'b1 : TXUSRCLK2;
localparam [0:0] INV_TXPHDLYTSTCLK = (_TECHMAP_CONSTMSK_TXPHDLYTSTCLK_ == 1) ? !_TECHMAP_CONSTVAL_TXPHDLYTSTCLK_ ^ IS_TXPHDLYTSTCLK_INVERTED :
(_TECHMAP_CONSTVAL_TXPHDLYTSTCLK_ == 0) ? ~IS_TXPHDLYTSTCLK_INVERTED : IS_TXPHDLYTSTCLK_INVERTED;
wire txphdlytstclk = (_TECHMAP_CONSTMSK_TXPHDLYTSTCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_TXPHDLYTSTCLK_ == 0) ? 1'b1 : TXPHDLYTSTCLK;
localparam [0:0] INV_SIGVALIDCLK = (_TECHMAP_CONSTMSK_SIGVALIDCLK_ == 1) ? !_TECHMAP_CONSTVAL_SIGVALIDCLK_ ^ IS_SIGVALIDCLK_INVERTED :
(_TECHMAP_CONSTVAL_SIGVALIDCLK_ == 0) ? ~IS_SIGVALIDCLK_INVERTED : IS_SIGVALIDCLK_INVERTED;
wire sigvalidclk = (_TECHMAP_CONSTMSK_SIGVALIDCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_SIGVALIDCLK_ == 0) ? 1'b1 : SIGVALIDCLK;
localparam [0:0] INV_RXUSRCLK = (_TECHMAP_CONSTMSK_RXUSRCLK_ == 1) ? !_TECHMAP_CONSTVAL_RXUSRCLK_ ^ IS_RXUSRCLK_INVERTED :
(_TECHMAP_CONSTVAL_RXUSRCLK_ == 0) ? ~IS_RXUSRCLK_INVERTED : IS_RXUSRCLK_INVERTED;
wire rxusrclk = (_TECHMAP_CONSTMSK_RXUSRCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RXUSRCLK_ == 0) ? 1'b1 : RXUSRCLK;
localparam [0:0] INV_RXUSRCLK2 = (_TECHMAP_CONSTMSK_RXUSRCLK2_ == 1) ? !_TECHMAP_CONSTVAL_RXUSRCLK2_ ^ IS_RXUSRCLK2_INVERTED :
(_TECHMAP_CONSTVAL_RXUSRCLK2_ == 0) ? ~IS_RXUSRCLK2_INVERTED : IS_RXUSRCLK2_INVERTED;
wire rxusrclk2 = (_TECHMAP_CONSTMSK_RXUSRCLK2_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_RXUSRCLK2_ == 0) ? 1'b1 : RXUSRCLK2;
localparam [0:0] INV_DRPCLK = (_TECHMAP_CONSTMSK_DRPCLK_ == 1) ? !_TECHMAP_CONSTVAL_DRPCLK_ ^ IS_DRPCLK_INVERTED :
(_TECHMAP_CONSTVAL_DRPCLK_ == 0) ? ~IS_DRPCLK_INVERTED : IS_DRPCLK_INVERTED;
wire drpclk = (_TECHMAP_CONSTMSK_DRPCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_DRPCLK_ == 0) ? 1'b1 : DRPCLK;
localparam [0:0] INV_DMONITORCLK = (_TECHMAP_CONSTMSK_DMONITORCLK_ == 1) ? !_TECHMAP_CONSTVAL_DMONITORCLK_ ^ IS_DMONITORCLK_INVERTED :
(_TECHMAP_CONSTVAL_DMONITORCLK_ == 0) ? ~IS_DMONITORCLK_INVERTED : IS_DMONITORCLK_INVERTED;
wire dmonitorclk = (_TECHMAP_CONSTMSK_DMONITORCLK_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_DMONITORCLK_ == 0) ? 1'b1 : DMONITORCLK;
localparam [0:0] INV_CLKRSVD0 = (_TECHMAP_CONSTMSK_CLKRSVD0_ == 1) ? !_TECHMAP_CONSTVAL_CLKRSVD0_ ^ IS_CLKRSVD0_INVERTED :
(_TECHMAP_CONSTVAL_CLKRSVD0_ == 0) ? ~IS_CLKRSVD0_INVERTED : IS_CLKRSVD0_INVERTED;
wire clkrsvd0 = (_TECHMAP_CONSTMSK_CLKRSVD0_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKRSVD0_ == 0) ? 1'b1 : CLKRSVD0;
localparam [0:0] INV_CLKRSVD1 = (_TECHMAP_CONSTMSK_CLKRSVD1_ == 1) ? !_TECHMAP_CONSTVAL_CLKRSVD1_ ^ IS_CLKRSVD1_INVERTED :
(_TECHMAP_CONSTVAL_CLKRSVD1_ == 0) ? ~IS_CLKRSVD1_INVERTED : IS_CLKRSVD1_INVERTED;
wire clkrsvd1 = (_TECHMAP_CONSTMSK_CLKRSVD1_ == 1) ? 1'b1 :
(_TECHMAP_CONSTVAL_CLKRSVD1_ == 0) ? 1'b1 : CLKRSVD1;
parameter IN_USE = 1'b0;
wire gtprxn, gtprxp;
IPAD_GTP_VPR ibuf_rx_n (.I(GTPRXN), .O(gtprxn));
IPAD_GTP_VPR ibuf_rx_p (.I(GTPRXP), .O(gtprxp));
wire gtptxn, gtptxp;
OPAD_GTP_VPR obuf_tx_n (.I(gtptxn), .O(GTPTXN));
OPAD_GTP_VPR obuf_tx_p (.I(gtptxp), .O(GTPTXP));
GTPE2_CHANNEL_VPR #(
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE),
.ACJTAG_MODE (ACJTAG_MODE),
.ACJTAG_RESET (ACJTAG_RESET),
.ADAPT_CFG0 (ADAPT_CFG0),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE == "TRUE"),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET == "TRUE"),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET == "TRUE"),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.CBCC_DATA_SOURCE_SEL_DECODED (CBCC_DATA_SOURCE_SEL == "DECODED"),
.CFOK_CFG (CFOK_CFG),
.CFOK_CFG2 (CFOK_CFG2),
.CFOK_CFG3 (CFOK_CFG3),
.CFOK_CFG4 (CFOK_CFG4),
.CFOK_CFG5 (CFOK_CFG5),
.CFOK_CFG6 (CFOK_CFG6),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN == "TRUE"),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE == "TRUE"),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_BIN),
.CLK_COMMON_SWING (CLK_COMMON_SWING),
.CLK_CORRECT_USE (CLK_CORRECT_USE == "TRUE"),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE == "TRUE"),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE == "TRUE"),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE == "TRUE"),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_BIN),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT == "TRUE"),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT == "TRUE"),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY == "TRUE"),
.DMONITOR_CFG (DMONITOR_CFG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL),
.ES_CONTROL (ES_CONTROL),
.ES_ERRDET_EN (ES_ERRDET_EN == "TRUE"),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN == "TRUE"),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET),
.ES_PMA_CFG (ES_PMA_CFG),
.ES_PRESCALE (ES_PRESCALE),
.ES_QUALIFIER (ES_QUALIFIER),
.ES_QUAL_MASK (ES_QUAL_MASK),
.ES_SDATA_MASK (ES_SDATA_MASK),
.ES_VERT_OFFSET (ES_VERT_OFFSET),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN == "TRUE"),
.GEARBOX_MODE (GEARBOX_MODE),
.LOOPBACK_CFG (LOOPBACK_CFG),
.OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV),
.PCS_PCIE_EN (PCS_PCIE_EN == "TRUE"),
.PCS_RSVD_ATTR (PCS_RSVD_ATTR),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2),
.PMA_LOOPBACK_CFG (PMA_LOOPBACK_CFG),
.PMA_RSV (PMA_RSV),
.PMA_RSV2 (PMA_RSV2),
.PMA_RSV3 (PMA_RSV3),
.PMA_RSV4 (PMA_RSV4),
.PMA_RSV5 (PMA_RSV5),
.PMA_RSV6 (PMA_RSV6),
.PMA_RSV7 (PMA_RSV7),
.RXBUFRESET_TIME (RXBUFRESET_TIME),
.RXBUF_ADDR_MODE_FAST (RXBUF_ADDR_MODE == "FAST"),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT),
.RXBUF_EN (RXBUF_EN == "TRUE"),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE == "TRUE"),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN == "TRUE"),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE == "TRUE"),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE == "TRUE"),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD == "TRUE"),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDR_CFG (RXCDR_CFG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE),
.RXCDR_LOCK_CFG (RXCDR_LOCK_CFG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE),
.RXDLY_CFG (RXDLY_CFG),
.RXDLY_LCFG (RXDLY_LCFG),
.RXDLY_TAP_CFG (RXDLY_TAP_CFG),
.RXGEARBOX_EN (RXGEARBOX_EN == "TRUE"),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXLPMRESET_TIME (RXLPMRESET_TIME),
.RXLPM_BIAS_STARTUP_DISABLE (RXLPM_BIAS_STARTUP_DISABLE),
.RXLPM_CFG (RXLPM_CFG),
.RXLPM_CFG1 (RXLPM_CFG1),
.RXLPM_CM_CFG (RXLPM_CM_CFG),
.RXLPM_GC_CFG (RXLPM_GC_CFG),
.RXLPM_GC_CFG2 (RXLPM_GC_CFG2),
.RXLPM_HF_CFG (RXLPM_HF_CFG),
.RXLPM_HF_CFG2 (RXLPM_HF_CFG2),
.RXLPM_HF_CFG3 (RXLPM_HF_CFG3),
.RXLPM_HOLD_DURING_EIDLE (RXLPM_HOLD_DURING_EIDLE),
.RXLPM_INCM_CFG (RXLPM_INCM_CFG),
.RXLPM_IPCM_CFG (RXLPM_IPCM_CFG),
.RXLPM_LF_CFG (RXLPM_LF_CFG),
.RXLPM_LF_CFG2 (RXLPM_LF_CFG2),
.RXLPM_OSINT_CFG (RXLPM_OSINT_CFG),
.RXOOB_CFG (RXOOB_CFG),
.RXOOB_CLK_CFG_FABRIC (RXOOB_CLK_CFG == "FABRIC"),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME),
.RXOSCALRESET_TIMEOUT (RXOSCALRESET_TIMEOUT),
.RXOUT_DIV (RXOUT_DIV_BIN),
.RXPCSRESET_TIME (RXPCSRESET_TIME),
.RXPHDLY_CFG (RXPHDLY_CFG),
.RXPH_CFG (RXPH_CFG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL),
.RXPI_CFG0 (RXPI_CFG0),
.RXPI_CFG1 (RXPI_CFG1),
.RXPI_CFG2 (RXPI_CFG2),
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RXSLIDE_MODE_AUTO (RXSLIDE_MODE == "AUTO"),
.RXSLIDE_MODE_PCS (RXSLIDE_MODE == "PCS"),
.RXSLIDE_MODE_PMA (RXSLIDE_MODE == "PMA"),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE),
.RXSYNC_OVRD (RXSYNC_OVRD),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA),
.RX_BIAS_CFG (RX_BIAS_CFG),
.RX_BUFFER_CFG (RX_BUFFER_CFG),
.RX_CLK25_DIV (RX_CLK25_DIV_BIN),
.RX_CLKMUX_EN (RX_CLKMUX_EN),
.RX_CM_SEL (RX_CM_SEL),
.RX_CM_TRIM (RX_CM_TRIM),
.RX_DATA_WIDTH (RX_DATA_WIDTH_BIN),
.RX_DDI_SEL (RX_DDI_SEL),
.RX_DEBUG_CFG (RX_DEBUG_CFG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN == "TRUE"),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH == "TRUE"),
.RX_OS_CFG (RX_OS_CFG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_BIN),
.RX_XCLK_SEL_RXUSR (RX_XCLK_SEL == "RXUSR"),
.SAS_MAX_COM (SAS_MAX_COM),
.SAS_MIN_COM (SAS_MIN_COM),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
.SATA_BURST_VAL (SATA_BURST_VAL),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL),
.SATA_MAX_BURST (SATA_MAX_BURST),
.SATA_MAX_INIT (SATA_MAX_INIT),
.SATA_MAX_WAKE (SATA_MAX_WAKE),
.SATA_MIN_BURST (SATA_MIN_BURST),
.SATA_MIN_INIT (SATA_MIN_INIT),
.SATA_MIN_WAKE (SATA_MIN_WAKE),
.SATA_PLL_CFG_VCO_1500MHZ (SATA_PLL_CFG == "VCO_1500MHZ"),
.SATA_PLL_CFG_VCO_750MHZ (SATA_PLL_CFG == "VCO_750MHZ"),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA == "TRUE"),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION),
.TERM_RCAL_CFG (TERM_RCAL_CFG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD),
.TRANS_TIME_RATE (TRANS_TIME_RATE),
.TST_RSV (TST_RSV),
.TXBUF_EN (TXBUF_EN == "TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE == "TRUE"),
.TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG),
.TXGEARBOX_EN (TXGEARBOX_EN == "TRUE"),
.TXOOB_CFG (TXOOB_CFG),
.TXOUT_DIV (TXOUT_DIV_BIN),
.TXPCSRESET_TIME (TXPCSRESET_TIME),
.TXPHDLY_CFG (TXPHDLY_CFG),
.TXPH_CFG (TXPH_CFG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL),
.TXPI_CFG0 (TXPI_CFG0),
.TXPI_CFG1 (TXPI_CFG1),
.TXPI_CFG2 (TXPI_CFG2),
.TXPI_CFG3 (TXPI_CFG3),
.TXPI_CFG4 (TXPI_CFG4),
.TXPI_CFG5 (TXPI_CFG5),
.TXPI_GREY_SEL (TXPI_GREY_SEL),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL),
.TXPI_PPMCLK_SEL_TXUSRCLK2 (TXPI_PPMCLK_SEL == "TXUSRCLK2"),
.TXPI_PPM_CFG (TXPI_PPM_CFG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM),
.TXPMARESET_TIME (TXPMARESET_TIME),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE),
.TXSYNC_OVRD (TXSYNC_OVRD),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA),
.TX_CLK25_DIV (TX_CLK25_DIV_BIN),
.TX_CLKMUX_EN (TX_CLKMUX_EN),
.TX_DATA_WIDTH (TX_DATA_WIDTH_BIN),
.TX_DEEMPH0 (TX_DEEMPH0),
.TX_DEEMPH1 (TX_DEEMPH1),
.TX_DRIVE_MODE_PIPE (TX_DRIVE_MODE == "PIPE"),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ == "TRUE"),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.TX_PREDRIVER_MODE (TX_PREDRIVER_MODE),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
.TX_RXDETECT_REF (TX_RXDETECT_REF),
.TX_XCLK_SEL_TXUSR (TX_XCLK_SEL == "TXUSR"),
.UCODEER_CLR (UCODEER_CLR),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL),
.INV_TXUSRCLK (INV_TXUSRCLK),
.INV_TXUSRCLK2 (INV_TXUSRCLK2),
.INV_TXPHDLYTSTCLK (INV_TXPHDLYTSTCLK),
.INV_SIGVALIDCLK (INV_SIGVALIDCLK),
.INV_RXUSRCLK (INV_RXUSRCLK),
.INV_RXUSRCLK2 (INV_RXUSRCLK2),
.INV_DRPCLK (INV_DRPCLK),
.INV_DMONITORCLK (INV_DMONITORCLK),
.INV_CLKRSVD0 (INV_CLKRSVD0),
.INV_CLKRSVD1 (INV_CLKRSVD1),
.IO_LOC_PAIRS (IO_LOC_PAIRS)
) gtp_channel (
.GTPRXN (gtprxn),
.GTPRXP (gtprxp),
.GTPTXN (gtptxn),
.GTPTXP (gtptxp),
.DRPRDY (DRPRDY),
.EYESCANDATAERROR (EYESCANDATAERROR),
.PHYSTATUS (PHYSTATUS),
.PMARSVDOUT0 (PMARSVDOUT0),
.PMARSVDOUT1 (PMARSVDOUT1),
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCDRLOCK (RXCDRLOCK),
.RXCHANBONDSEQ (RXCHANBONDSEQ),
.RXCHANISALIGNED (RXCHANISALIGNED),
.RXCHANREALIGN (RXCHANREALIGN),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMMADET (RXCOMMADET),
.RXCOMSASDET (RXCOMSASDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
.RXDLYSRESETDONE (RXDLYSRESETDONE),
.RXELECIDLE (RXELECIDLE),
.RXHEADERVALID (RXHEADERVALID),
.RXOSINTDONE (RXOSINTDONE),
.RXOSINTSTARTED (RXOSINTSTARTED),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXPHALIGNDONE (RXPHALIGNDONE),
.RXPMARESETDONE (RXPMARESETDONE),
.RXPRBSERR (RXPRBSERR),
.RXRATEDONE (RXRATEDONE),
.RXRESETDONE (RXRESETDONE),
.RXSYNCDONE (RXSYNCDONE),
.RXSYNCOUT (RXSYNCOUT),
.RXVALID (RXVALID),
.TXCOMFINISH (TXCOMFINISH),
.TXDLYSRESETDONE (TXDLYSRESETDONE),
.TXGEARBOXREADY (TXGEARBOXREADY),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXPHALIGNDONE (TXPHALIGNDONE),
.TXPHINITDONE (TXPHINITDONE),
.TXPMARESETDONE (TXPMARESETDONE),
.TXRATEDONE (TXRATEDONE),
.TXRESETDONE (TXRESETDONE),
.TXSYNCDONE (TXSYNCDONE),
.TXSYNCOUT (TXSYNCOUT),
.DMONITOROUT (DMONITOROUT),
.DRPDO (DRPDO),
.PCSRSVDOUT (PCSRSVDOUT),
.RXCLKCORCNT (RXCLKCORCNT),
.RXDATAVALID (RXDATAVALID),
.RXSTARTOFSEQ (RXSTARTOFSEQ),
.TXBUFSTATUS (TXBUFSTATUS),
.RXBUFSTATUS (RXBUFSTATUS),
.RXHEADER (RXHEADER),
.RXSTATUS (RXSTATUS),
.RXDATA (RXDATA),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXCHBONDO (RXCHBONDO),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.RXPHMONITOR (RXPHMONITOR),
.RXPHSLIPMONITOR (RXPHSLIPMONITOR),
.CFGRESET (CFGRESET),
.CLKRSVD0 (clkrsvd0),
.CLKRSVD1 (clkrsvd1),
.DMONFIFORESET (DMONFIFORESET),
.DMONITORCLK (dmonitorclk),
.DRPCLK (drpclk),
.DRPEN (DRPEN),
.DRPWE (DRPWE),
.EYESCANMODE (EYESCANMODE),
.EYESCANRESET (EYESCANRESET),
.EYESCANTRIGGER (EYESCANTRIGGER),
.GTRESETSEL (GTRESETSEL),
.GTRXRESET (GTRXRESET),
.GTTXRESET (GTTXRESET),
.PMARSVDIN0 (PMARSVDIN0),
.PMARSVDIN1 (PMARSVDIN1),
.PMARSVDIN2 (PMARSVDIN2),
.PMARSVDIN3 (PMARSVDIN3),
.PMARSVDIN4 (PMARSVDIN4),
.RESETOVRD (RESETOVRD),
.RX8B10BEN (RX8B10BEN),
.RXBUFRESET (RXBUFRESET),
.RXCDRFREQRESET (RXCDRFREQRESET),
.RXCDRHOLD (RXCDRHOLD),
.RXCDROVRDEN (RXCDROVRDEN),
.RXCDRRESET (RXCDRRESET),
.RXCDRRESETRSV (RXCDRRESETRSV),
.RXCHBONDEN (RXCHBONDEN),
.RXCHBONDMASTER (RXCHBONDMASTER),
.RXCHBONDSLAVE (RXCHBONDSLAVE),
.RXCOMMADETEN (RXCOMMADETEN),
.RXDDIEN (RXDDIEN),
.RXDFEXYDEN (RXDFEXYDEN),
.RXDLYBYPASS (RXDLYBYPASS),
.RXDLYEN (RXDLYEN),
.RXDLYOVRDEN (RXDLYOVRDEN),
.RXDLYSRESET (RXDLYSRESET),
.RXGEARBOXSLIP (RXGEARBOXSLIP),
.RXLPMHFHOLD (RXLPMHFHOLD),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN),
.RXLPMLFHOLD (RXLPMLFHOLD),
.RXLPMLFOVRDEN (RXLPMLFOVRDEN),
.RXLPMOSINTNTRLEN (RXLPMOSINTNTRLEN),
.RXLPMRESET (RXLPMRESET),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RXOOBRESET (RXOOBRESET),
.RXOSCALRESET (RXOSCALRESET),
.RXOSHOLD (RXOSHOLD),
.RXOSINTEN (RXOSINTEN),
.RXOSINTHOLD (RXOSINTHOLD),
.RXOSINTNTRLEN (RXOSINTNTRLEN),
.RXOSINTOVRDEN (RXOSINTOVRDEN),
.RXOSINTPD (RXOSINTPD),
.RXOSINTSTROBE (RXOSINTSTROBE),
.RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN),
.RXOSOVRDEN (RXOSOVRDEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXPCSRESET (RXPCSRESET),
.RXPHALIGN (RXPHALIGN),
.RXPHALIGNEN (RXPHALIGNEN),
.RXPHDLYPD (RXPHDLYPD),
.RXPHDLYRESET (RXPHDLYRESET),
.RXPHOVRDEN (RXPHOVRDEN),
.RXPMARESET (RXPMARESET),
.RXPOLARITY (RXPOLARITY),
.RXPRBSCNTRESET (RXPRBSCNTRESET),
.RXRATEMODE (RXRATEMODE),
.RXSLIDE (RXSLIDE),
.RXSYNCALLIN (RXSYNCALLIN),
.RXSYNCIN (RXSYNCIN),
.RXSYNCMODE (RXSYNCMODE),
.RXUSERRDY (RXUSERRDY),
.RXUSRCLK2 (rxusrclk2),
.RXUSRCLK (rxusrclk),
.SETERRSTATUS (SETERRSTATUS),
.SIGVALIDCLK (sigvalidclk),
.TX8B10BEN (TX8B10BEN),
.TXCOMINIT (TXCOMINIT),
.TXCOMSAS (TXCOMSAS),
.TXCOMWAKE (TXCOMWAKE),
.TXDEEMPH (TXDEEMPH),
.TXDETECTRX (TXDETECTRX),
.TXDIFFPD (TXDIFFPD),
.TXDLYBYPASS (TXDLYBYPASS),
.TXDLYEN (TXDLYEN),
.TXDLYHOLD (TXDLYHOLD),
.TXDLYOVRDEN (TXDLYOVRDEN),
.TXDLYSRESET (TXDLYSRESET),
.TXDLYUPDOWN (TXDLYUPDOWN),
.TXELECIDLE (TXELECIDLE),
.TXINHIBIT (TXINHIBIT),
.TXPCSRESET (TXPCSRESET),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE),
.TXPHALIGN (TXPHALIGN),
.TXPHALIGNEN (TXPHALIGNEN),
.TXPHDLYPD (TXPHDLYPD),
.TXPHDLYRESET (TXPHDLYRESET),
.TXPHDLYTSTCLK (txphdlytstclk),
.TXPHINIT (TXPHINIT),
.TXPHOVRDEN (TXPHOVRDEN),
.TXPIPPMEN (TXPIPPMEN),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN),
.TXPIPPMPD (TXPIPPMPD),
.TXPIPPMSEL (TXPIPPMSEL),
.TXPISOPD (TXPISOPD),
.TXPMARESET (TXPMARESET),
.TXPOLARITY (TXPOLARITY),
.TXPOSTCURSORINV (TXPOSTCURSORINV),
.TXPRBSFORCEERR (TXPRBSFORCEERR),
.TXPRECURSORINV (TXPRECURSORINV),
.TXRATEMODE (TXRATEMODE),
.TXSTARTSEQ (TXSTARTSEQ),
.TXSWING (TXSWING),
.TXSYNCALLIN (TXSYNCALLIN),
.TXSYNCIN (TXSYNCIN),
.TXSYNCMODE (TXSYNCMODE),
.TXUSERRDY (TXUSERRDY),
.TXUSRCLK2 (txusrclk2),
.TXUSRCLK (txusrclk),
.RXADAPTSELTEST (RXADAPTSELTEST),
.DRPDI (DRPDI),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
.TSTIN (TSTIN),
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXPD (RXPD),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXPD (TXPD),
.TXSYSCLKSEL (TXSYSCLKSEL),
.LOOPBACK (LOOPBACK),
.RXCHBONDLEVEL (RXCHBONDLEVEL),
.RXOUTCLKSEL (RXOUTCLKSEL),
.RXPRBSSEL (RXPRBSSEL),
.RXRATE (RXRATE),
.TXBUFDIFFCTRL (TXBUFDIFFCTRL),
.TXHEADER (TXHEADER),
.TXMARGIN (TXMARGIN),
.TXOUTCLKSEL (TXOUTCLKSEL),
.TXPRBSSEL (TXPRBSSEL),
.TXRATE (TXRATE),
.TXDATA (TXDATA),
.RXCHBONDI (RXCHBONDI),
.RXOSINTCFG (RXOSINTCFG),
.RXOSINTID0 (RXOSINTID0),
.TX8B10BBYPASS (TX8B10BBYPASS),
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXCHARISK (TXCHARISK),
.TXDIFFCTRL (TXDIFFCTRL),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE),
.TXPOSTCURSOR (TXPOSTCURSOR),
.TXPRECURSOR (TXPRECURSOR),
.TXMAINCURSOR (TXMAINCURSOR),
.TXSEQUENCE (TXSEQUENCE),
.DRPADDR (DRPADDR)
);
endmodule |
module PCIE_2_1 (
output CFGAERECRCCHECKEN,
output CFGAERECRCGENEN,
input [4:0] CFGAERINTERRUPTMSGNUM,
output CFGAERROOTERRCORRERRRECEIVED,
output CFGAERROOTERRCORRERRREPORTINGEN,
output CFGAERROOTERRFATALERRRECEIVED,
output CFGAERROOTERRFATALERRREPORTINGEN,
output CFGAERROOTERRNONFATALERRRECEIVED,
output CFGAERROOTERRNONFATALERRREPORTINGEN,
output CFGBRIDGESERREN,
output CFGCOMMANDBUSMASTERENABLE,
output CFGCOMMANDINTERRUPTDISABLE,
output CFGCOMMANDIOENABLE,
output CFGCOMMANDMEMENABLE,
output CFGCOMMANDSERREN,
output CFGDEVCONTROL2ARIFORWARDEN,
output CFGDEVCONTROL2ATOMICEGRESSBLOCK,
output CFGDEVCONTROL2ATOMICREQUESTEREN,
output CFGDEVCONTROL2CPLTIMEOUTDIS,
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL,
output CFGDEVCONTROL2IDOCPLEN,
output CFGDEVCONTROL2IDOREQEN,
output CFGDEVCONTROL2LTREN,
output CFGDEVCONTROL2TLPPREFIXBLOCK,
output CFGDEVCONTROLAUXPOWEREN,
output CFGDEVCONTROLCORRERRREPORTINGEN,
output CFGDEVCONTROLENABLERO,
output CFGDEVCONTROLEXTTAGEN,
output CFGDEVCONTROLFATALERRREPORTINGEN,
output [2:0] CFGDEVCONTROLMAXPAYLOAD,
output [2:0] CFGDEVCONTROLMAXREADREQ,
output CFGDEVCONTROLNONFATALREPORTINGEN,
output CFGDEVCONTROLNOSNOOPEN,
output CFGDEVCONTROLPHANTOMEN,
output CFGDEVCONTROLURERRREPORTINGEN,
input [15:0] CFGDEVID,
output CFGDEVSTATUSCORRERRDETECTED,
output CFGDEVSTATUSFATALERRDETECTED,
output CFGDEVSTATUSNONFATALERRDETECTED,
output CFGDEVSTATUSURDETECTED,
input [7:0] CFGDSBUSNUMBER,
input [4:0] CFGDSDEVICENUMBER,
input [2:0] CFGDSFUNCTIONNUMBER,
input [63:0] CFGDSN,
input CFGERRACSN,
input [127:0] CFGERRAERHEADERLOG,
output CFGERRAERHEADERLOGSETN,
input CFGERRATOMICEGRESSBLOCKEDN,
input CFGERRCORN,
input CFGERRCPLABORTN,
output CFGERRCPLRDYN,
input CFGERRCPLTIMEOUTN,
input CFGERRCPLUNEXPECTN,
input CFGERRECRCN,
input CFGERRINTERNALCORN,
input CFGERRINTERNALUNCORN,
input CFGERRLOCKEDN,
input CFGERRMALFORMEDN,
input CFGERRMCBLOCKEDN,
input CFGERRNORECOVERYN,
input CFGERRPOISONEDN,
input CFGERRPOSTEDN,
input [47:0] CFGERRTLPCPLHEADER,
input CFGERRURN,
input CFGFORCECOMMONCLOCKOFF,
input CFGFORCEEXTENDEDSYNCON,
input [2:0] CFGFORCEMPS,
input CFGINTERRUPTASSERTN,
input [7:0] CFGINTERRUPTDI,
output [7:0] CFGINTERRUPTDO,
output [2:0] CFGINTERRUPTMMENABLE,
output CFGINTERRUPTMSIENABLE,
output CFGINTERRUPTMSIXENABLE,
output CFGINTERRUPTMSIXFM,
input CFGINTERRUPTN,
output CFGINTERRUPTRDYN,
input CFGINTERRUPTSTATN,
output [1:0] CFGLINKCONTROLASPMCONTROL,
output CFGLINKCONTROLAUTOBANDWIDTHINTEN,
output CFGLINKCONTROLBANDWIDTHINTEN,
output CFGLINKCONTROLCLOCKPMEN,
output CFGLINKCONTROLCOMMONCLOCK,
output CFGLINKCONTROLEXTENDEDSYNC,
output CFGLINKCONTROLHWAUTOWIDTHDIS,
output CFGLINKCONTROLLINKDISABLE,
output CFGLINKCONTROLRCB,
output CFGLINKCONTROLRETRAINLINK,
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS,
output CFGLINKSTATUSBANDWIDTHSTATUS,
output [1:0] CFGLINKSTATUSCURRENTSPEED,
output CFGLINKSTATUSDLLACTIVE,
output CFGLINKSTATUSLINKTRAINING,
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH,
input [3:0] CFGMGMTBYTEENN,
input [31:0] CFGMGMTDI,
output [31:0] CFGMGMTDO,
input [9:0] CFGMGMTDWADDR,
input CFGMGMTRDENN,
output CFGMGMTRDWRDONEN,
input CFGMGMTWRENN,
input CFGMGMTWRREADONLYN,
input CFGMGMTWRRW1CASRWN,
output [15:0] CFGMSGDATA,
output CFGMSGRECEIVED,
output CFGMSGRECEIVEDASSERTINTA,
output CFGMSGRECEIVEDASSERTINTB,
output CFGMSGRECEIVEDASSERTINTC,
output CFGMSGRECEIVEDASSERTINTD,
output CFGMSGRECEIVEDDEASSERTINTA,
output CFGMSGRECEIVEDDEASSERTINTB,
output CFGMSGRECEIVEDDEASSERTINTC,
output CFGMSGRECEIVEDDEASSERTINTD,
output CFGMSGRECEIVEDERRCOR,
output CFGMSGRECEIVEDERRFATAL,
output CFGMSGRECEIVEDERRNONFATAL,
output CFGMSGRECEIVEDPMASNAK,
output CFGMSGRECEIVEDPMETO,
output CFGMSGRECEIVEDPMETOACK,
output CFGMSGRECEIVEDPMPME,
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT,
output CFGMSGRECEIVEDUNLOCK,
input [4:0] CFGPCIECAPINTERRUPTMSGNUM,
output [2:0] CFGPCIELINKSTATE,
output CFGPMCSRPMEEN,
output CFGPMCSRPMESTATUS,
output [1:0] CFGPMCSRPOWERSTATE,
input [1:0] CFGPMFORCESTATE,
input CFGPMFORCESTATEENN,
input CFGPMHALTASPML0SN,
input CFGPMHALTASPML1N,
output CFGPMRCVASREQL1N,
output CFGPMRCVENTERL1N,
output CFGPMRCVENTERL23N,
output CFGPMRCVREQACKN,
input CFGPMSENDPMETON,
input CFGPMTURNOFFOKN,
input CFGPMWAKEN,
input [7:0] CFGPORTNUMBER,
input [7:0] CFGREVID,
output CFGROOTCONTROLPMEINTEN,
output CFGROOTCONTROLSYSERRCORRERREN,
output CFGROOTCONTROLSYSERRFATALERREN,
output CFGROOTCONTROLSYSERRNONFATALERREN,
output CFGSLOTCONTROLELECTROMECHILCTLPULSE,
input [15:0] CFGSUBSYSID,
input [15:0] CFGSUBSYSVENDID,
output CFGTRANSACTION,
output [6:0] CFGTRANSACTIONADDR,
output CFGTRANSACTIONTYPE,
input CFGTRNPENDINGN,
output [6:0] CFGVCTCVCMAP,
input [15:0] CFGVENDID,
input CMRSTN,
input CMSTICKYRSTN,
input [1:0] DBGMODE,
output DBGSCLRA,
output DBGSCLRB,
output DBGSCLRC,
output DBGSCLRD,
output DBGSCLRE,
output DBGSCLRF,
output DBGSCLRG,
output DBGSCLRH,
output DBGSCLRI,
output DBGSCLRJ,
output DBGSCLRK,
input DBGSUBMODE,
output [63:0] DBGVECA,
output [63:0] DBGVECB,
output [11:0] DBGVECC,
input DLRSTN,
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
output [15:0] DRPDO,
input DRPEN,
output DRPRDY,
input DRPWE,
input FUNCLVLRSTN,
output LL2BADDLLPERR,
output LL2BADTLPERR,
output [4:0] LL2LINKSTATUS,
output LL2PROTOCOLERR,
output LL2RECEIVERERR,
output LL2REPLAYROERR,
output LL2REPLAYTOERR,
input LL2SENDASREQL1,
input LL2SENDENTERL1,
input LL2SENDENTERL23,
input LL2SENDPMACK,
input LL2SUSPENDNOW,
output LL2SUSPENDOK,
output LL2TFCINIT1SEQ,
output LL2TFCINIT2SEQ,
input LL2TLPRCV,
output LL2TXIDLE,
output LNKCLKEN,
output [12:0] MIMRXRADDR,
input [67:0] MIMRXRDATA,
output MIMRXREN,
output [12:0] MIMRXWADDR,
output [67:0] MIMRXWDATA,
output MIMRXWEN,
output [12:0] MIMTXRADDR,
input [68:0] MIMTXRDATA,
output MIMTXREN,
output [12:0] MIMTXWADDR,
output [68:0] MIMTXWDATA,
output MIMTXWEN,
input PIPECLK,
input PIPERX0CHANISALIGNED,
input [1:0] PIPERX0CHARISK,
input [15:0] PIPERX0DATA,
input PIPERX0ELECIDLE,
input PIPERX0PHYSTATUS,
output PIPERX0POLARITY,
input [2:0] PIPERX0STATUS,
input PIPERX0VALID,
input PIPERX1CHANISALIGNED,
input [1:0] PIPERX1CHARISK,
input [15:0] PIPERX1DATA,
input PIPERX1ELECIDLE,
input PIPERX1PHYSTATUS,
output PIPERX1POLARITY,
input [2:0] PIPERX1STATUS,
input PIPERX1VALID,
input PIPERX2CHANISALIGNED,
input [1:0] PIPERX2CHARISK,
input [15:0] PIPERX2DATA,
input PIPERX2ELECIDLE,
input PIPERX2PHYSTATUS,
output PIPERX2POLARITY,
input [2:0] PIPERX2STATUS,
input PIPERX2VALID,
input PIPERX3CHANISALIGNED,
input [1:0] PIPERX3CHARISK,
input [15:0] PIPERX3DATA,
input PIPERX3ELECIDLE,
input PIPERX3PHYSTATUS,
output PIPERX3POLARITY,
input [2:0] PIPERX3STATUS,
input PIPERX3VALID,
input PIPERX4CHANISALIGNED,
input [1:0] PIPERX4CHARISK,
input [15:0] PIPERX4DATA,
input PIPERX4ELECIDLE,
input PIPERX4PHYSTATUS,
output PIPERX4POLARITY,
input [2:0] PIPERX4STATUS,
input PIPERX4VALID,
input PIPERX5CHANISALIGNED,
input [1:0] PIPERX5CHARISK,
input [15:0] PIPERX5DATA,
input PIPERX5ELECIDLE,
input PIPERX5PHYSTATUS,
output PIPERX5POLARITY,
input [2:0] PIPERX5STATUS,
input PIPERX5VALID,
input PIPERX6CHANISALIGNED,
input [1:0] PIPERX6CHARISK,
input [15:0] PIPERX6DATA,
input PIPERX6ELECIDLE,
input PIPERX6PHYSTATUS,
output PIPERX6POLARITY,
input [2:0] PIPERX6STATUS,
input PIPERX6VALID,
input PIPERX7CHANISALIGNED,
input [1:0] PIPERX7CHARISK,
input [15:0] PIPERX7DATA,
input PIPERX7ELECIDLE,
input PIPERX7PHYSTATUS,
output PIPERX7POLARITY,
input [2:0] PIPERX7STATUS,
input PIPERX7VALID,
output [1:0] PIPETX0CHARISK,
output PIPETX0COMPLIANCE,
output [15:0] PIPETX0DATA,
output PIPETX0ELECIDLE,
output [1:0] PIPETX0POWERDOWN,
output [1:0] PIPETX1CHARISK,
output PIPETX1COMPLIANCE,
output [15:0] PIPETX1DATA,
output PIPETX1ELECIDLE,
output [1:0] PIPETX1POWERDOWN,
output [1:0] PIPETX2CHARISK,
output PIPETX2COMPLIANCE,
output [15:0] PIPETX2DATA,
output PIPETX2ELECIDLE,
output [1:0] PIPETX2POWERDOWN,
output [1:0] PIPETX3CHARISK,
output PIPETX3COMPLIANCE,
output [15:0] PIPETX3DATA,
output PIPETX3ELECIDLE,
output [1:0] PIPETX3POWERDOWN,
output [1:0] PIPETX4CHARISK,
output PIPETX4COMPLIANCE,
output [15:0] PIPETX4DATA,
output PIPETX4ELECIDLE,
output [1:0] PIPETX4POWERDOWN,
output [1:0] PIPETX5CHARISK,
output PIPETX5COMPLIANCE,
output [15:0] PIPETX5DATA,
output PIPETX5ELECIDLE,
output [1:0] PIPETX5POWERDOWN,
output [1:0] PIPETX6CHARISK,
output PIPETX6COMPLIANCE,
output [15:0] PIPETX6DATA,
output PIPETX6ELECIDLE,
output [1:0] PIPETX6POWERDOWN,
output [1:0] PIPETX7CHARISK,
output PIPETX7COMPLIANCE,
output [15:0] PIPETX7DATA,
output PIPETX7ELECIDLE,
output [1:0] PIPETX7POWERDOWN,
output PIPETXDEEMPH,
output [2:0] PIPETXMARGIN,
output PIPETXRATE,
output PIPETXRCVRDET,
output PIPETXRESET,
input [4:0] PL2DIRECTEDLSTATE,
output PL2L0REQ,
output PL2LINKUP,
output PL2RECEIVERERR,
output PL2RECOVERY,
output PL2RXELECIDLE,
output [1:0] PL2RXPMSTATE,
output PL2SUSPENDOK,
input [2:0] PLDBGMODE,
output [11:0] PLDBGVEC,
output PLDIRECTEDCHANGEDONE,
input PLDIRECTEDLINKAUTON,
input [1:0] PLDIRECTEDLINKCHANGE,
input PLDIRECTEDLINKSPEED,
input [1:0] PLDIRECTEDLINKWIDTH,
input [5:0] PLDIRECTEDLTSSMNEW,
input PLDIRECTEDLTSSMNEWVLD,
input PLDIRECTEDLTSSMSTALL,
input PLDOWNSTREAMDEEMPHSOURCE,
output [2:0] PLINITIALLINKWIDTH,
output [1:0] PLLANEREVERSALMODE,
output PLLINKGEN2CAP,
output PLLINKPARTNERGEN2SUPPORTED,
output PLLINKUPCFGCAP,
output [5:0] PLLTSSMSTATE,
output PLPHYLNKUPN,
output PLRECEIVEDHOTRST,
input PLRSTN,
output [1:0] PLRXPMSTATE,
output PLSELLNKRATE,
output [1:0] PLSELLNKWIDTH,
input PLTRANSMITHOTRST,
output [2:0] PLTXPMSTATE,
input PLUPSTREAMPREFERDEEMPH,
output RECEIVEDFUNCLVLRSTN,
input SYSRSTN,
input TL2ASPMSUSPENDCREDITCHECK,
output TL2ASPMSUSPENDCREDITCHECKOK,
output TL2ASPMSUSPENDREQ,
output TL2ERRFCPE,
output [63:0] TL2ERRHDR,
output TL2ERRMALFORMED,
output TL2ERRRXOVERFLOW,
output TL2PPMSUSPENDOK,
input TL2PPMSUSPENDREQ,
input TLRSTN,
output [11:0] TRNFCCPLD,
output [7:0] TRNFCCPLH,
output [11:0] TRNFCNPD,
output [7:0] TRNFCNPH,
output [11:0] TRNFCPD,
output [7:0] TRNFCPH,
input [2:0] TRNFCSEL,
output TRNLNKUP,
output [7:0] TRNRBARHIT,
output [127:0] TRNRD,
output [63:0] TRNRDLLPDATA,
output [1:0] TRNRDLLPSRCRDY,
input TRNRDSTRDY,
output TRNRECRCERR,
output TRNREOF,
output TRNRERRFWD,
input TRNRFCPRET,
input TRNRNPOK,
input TRNRNPREQ,
output [1:0] TRNRREM,
output TRNRSOF,
output TRNRSRCDSC,
output TRNRSRCRDY,
output [5:0] TRNTBUFAV,
input TRNTCFGGNT,
output TRNTCFGREQ,
input [127:0] TRNTD,
input [31:0] TRNTDLLPDATA,
output TRNTDLLPDSTRDY,
input TRNTDLLPSRCRDY,
output [3:0] TRNTDSTRDY,
input TRNTECRCGEN,
input TRNTEOF,
output TRNTERRDROP,
input TRNTERRFWD,
input [1:0] TRNTREM,
input TRNTSOF,
input TRNTSRCDSC,
input TRNTSRCRDY,
input TRNTSTR,
input USERCLK,
input USERCLK2,
output USERRSTN
);
parameter [11:0] AER_BASE_PTR = 12'd0;
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
parameter [15:0] AER_CAP_ID = 16'd0;
parameter AER_CAP_MULTIHEADER = "FALSE";
parameter [11:0] AER_CAP_NEXTPTR = 12'd0;
parameter AER_CAP_ON = "FALSE";
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'd0;
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "FALSE";
parameter [3:0] AER_CAP_VERSION = 4'd0;
parameter ALLOW_X8_GEN2 = "FALSE";
parameter [31:0] BAR0 = 32'd0;
parameter [31:0] BAR1 = 32'd0;
parameter [31:0] BAR2 = 32'd0;
parameter [31:0] BAR3 = 32'd0;
parameter [31:0] BAR4 = 32'd0;
parameter [31:0] BAR5 = 32'd0;
parameter [7:0] CAPABILITIES_PTR = 8'd0;
parameter [31:0] CARDBUS_CIS_POINTER = 32'd0;
parameter [23:0] CLASS_CODE = 24'd0;
parameter CMD_INTX_IMPLEMENTED = "FALSE";
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'd0;
parameter [6:0] CRM_MODULE_RSTS = 7'd0;
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE";
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE";
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE";
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE";
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'd0;
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE";
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'd0;
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "FALSE";
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "FALSE";
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE";
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
parameter [2:0] DEV_CAP_MAX_PAYLOAD_SUPPORTED = 3'd0;
parameter DEV_CAP_ROLE_BASED_ERROR = "FALSE";
parameter [2:0] DEV_CAP_RSVD_14_12 = 3'd0;
parameter [1:0] DEV_CAP_RSVD_17_16 = 2'd0;
parameter [2:0] DEV_CAP_RSVD_31_29 = 3'd0;
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE";
parameter DISABLE_ASPM_L1_TIMER = "FALSE";
parameter DISABLE_BAR_FILTERING = "FALSE";
parameter DISABLE_ERR_MSG = "FALSE";
parameter DISABLE_ID_CHECK = "FALSE";
parameter DISABLE_LANE_REVERSAL = "FALSE";
parameter DISABLE_LOCKED_FILTER = "FALSE";
parameter DISABLE_PPM_FILTER = "FALSE";
parameter DISABLE_RX_POISONED_RESP = "FALSE";
parameter DISABLE_RX_TC_FILTER = "FALSE";
parameter DISABLE_SCRAMBLING = "FALSE";
parameter [7:0] DNSTREAM_LINK_NUM = 8'd0;
parameter [11:0] DSN_BASE_PTR = 12'd0;
parameter [15:0] DSN_CAP_ID = 16'd0;
parameter [11:0] DSN_CAP_NEXTPTR = 12'd0;
parameter DSN_CAP_ON = "FALSE";
parameter [3:0] DSN_CAP_VERSION = 4'd0;
parameter [10:0] ENABLE_MSG_ROUTE = 11'd0;
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE";
parameter ENTER_RVRY_EI_L0 = "FALSE";
parameter EXIT_LOOPBACK_ON_EI = "FALSE";
parameter [31:0] EXPANSION_ROM = 32'd0;
parameter [5:0] EXT_CFG_CAP_PTR = 6'd0;
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'd0;
parameter [7:0] HEADER_TYPE = 8'd0;
parameter [4:0] INFER_EI = 5'd0;
parameter [7:0] INTERRUPT_PIN = 8'd0;
parameter INTERRUPT_STAT_AUTO = "FALSE";
parameter IS_SWITCH = "FALSE";
parameter [9:0] LAST_CONFIG_DWORD = 10'd0;
parameter LINK_CAP_ASPM_OPTIONALITY = "FALSE";
parameter [1:0] LINK_CAP_ASPM_SUPPORT = 2'd0;
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'd0;
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'd0;
parameter [0:0] LINK_CAP_RSVD_23 = 1'd0;
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'd0;
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE";
parameter [14:0] LL_ACK_TIMEOUT = 15'd0;
parameter LL_ACK_TIMEOUT_EN = "FALSE";
parameter [1:0] LL_ACK_TIMEOUT_FUNC = 2'd0;
parameter [14:0] LL_REPLAY_TIMEOUT = 15'd0;
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
parameter [1:0] LL_REPLAY_TIMEOUT_FUNC = 2'd0;
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'd0;
parameter MPS_FORCE = "FALSE";
parameter [7:0] MSIX_BASE_PTR = 8'd0;
parameter [7:0] MSIX_CAP_ID = 8'd0;
parameter [7:0] MSIX_CAP_NEXTPTR = 8'd0;
parameter MSIX_CAP_ON = "FALSE";
parameter [2:0] MSIX_CAP_PBA_BIR = 3'd0;
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'd0;
parameter [2:0] MSIX_CAP_TABLE_BIR = 3'd0;
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'd0;
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'd0;
parameter [7:0] MSI_BASE_PTR = 8'd0;
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "FALSE";
parameter [7:0] MSI_CAP_ID = 8'd0;
parameter [2:0] MSI_CAP_MULTIMSGCAP = 3'd0;
parameter [7:0] MSI_CAP_NEXTPTR = 8'd0;
parameter MSI_CAP_ON = "FALSE";
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE";
parameter [7:0] N_FTS_COMCLK_GEN1 = 8'd255;
parameter [7:0] N_FTS_COMCLK_GEN2 = 8'd255;
parameter [7:0] N_FTS_GEN1 = 8'd255;
parameter [7:0] N_FTS_GEN2 = 8'd255;
parameter [7:0] PCIE_BASE_PTR = 8'd0;
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'd0;
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'd0;
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'd0;
parameter [7:0] PCIE_CAP_NEXTPTR = 8'd0;
parameter PCIE_CAP_ON = "FALSE";
parameter [1:0] PCIE_CAP_RSVD_15_14 = 2'd0;
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
parameter [3:0] PCIE_REVISION = 4'd2;
parameter PL_FAST_TRAIN = "FALSE";
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'd0;
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE";
parameter [1:0] PM_ASPML0S_TIMEOUT_FUNC = 2'd0;
parameter PM_ASPM_FASTEXIT = "FALSE";
parameter [7:0] PM_BASE_PTR = 8'd0;
parameter PM_CAP_D1SUPPORT = "FALSE";
parameter PM_CAP_D2SUPPORT = "FALSE";
parameter PM_CAP_DSI = "FALSE";
parameter [7:0] PM_CAP_ID = 8'd0;
parameter [7:0] PM_CAP_NEXTPTR = 8'd0;
parameter PM_CAP_ON = "FALSE";
parameter [4:0] PM_CAP_PMESUPPORT = 5'd0;
parameter PM_CAP_PME_CLOCK = "FALSE";
parameter [0:0] PM_CAP_RSVD_04 = 1'd0;
parameter [2:0] PM_CAP_VERSION = 3'd3;
parameter PM_CSR_B2B3 = "FALSE";
parameter PM_CSR_BPCCEN = "FALSE";
parameter PM_CSR_NOSOFTRST = "FALSE";
parameter [7:0] PM_DATA0 = 8'd0;
parameter [7:0] PM_DATA1 = 8'd0;
parameter [7:0] PM_DATA2 = 8'd0;
parameter [7:0] PM_DATA3 = 8'd0;
parameter [7:0] PM_DATA4 = 8'd0;
parameter [7:0] PM_DATA5 = 8'd0;
parameter [7:0] PM_DATA6 = 8'd0;
parameter [7:0] PM_DATA7 = 8'd0;
parameter [1:0] PM_DATA_SCALE0 = 2'd0;
parameter [1:0] PM_DATA_SCALE1 = 2'd0;
parameter [1:0] PM_DATA_SCALE2 = 2'd0;
parameter [1:0] PM_DATA_SCALE3 = 2'd0;
parameter [1:0] PM_DATA_SCALE4 = 2'd0;
parameter [1:0] PM_DATA_SCALE5 = 2'd0;
parameter [1:0] PM_DATA_SCALE6 = 2'd0;
parameter [1:0] PM_DATA_SCALE7 = 2'd0;
parameter PM_MF = "FALSE";
parameter [11:0] RBAR_BASE_PTR = 12'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'd0;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'd0;
parameter [15:0] RBAR_CAP_ID = 16'd0;
parameter [2:0] RBAR_CAP_INDEX0 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX1 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX2 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX3 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX4 = 3'd0;
parameter [2:0] RBAR_CAP_INDEX5 = 3'd0;
parameter [11:0] RBAR_CAP_NEXTPTR = 12'd0;
parameter RBAR_CAP_ON = "FALSE";
parameter [31:0] RBAR_CAP_SUP0 = 32'd0;
parameter [31:0] RBAR_CAP_SUP1 = 32'd0;
parameter [31:0] RBAR_CAP_SUP2 = 32'd0;
parameter [31:0] RBAR_CAP_SUP3 = 32'd0;
parameter [31:0] RBAR_CAP_SUP4 = 32'd0;
parameter [31:0] RBAR_CAP_SUP5 = 32'd0;
parameter [3:0] RBAR_CAP_VERSION = 4'd0;
parameter [2:0] RBAR_NUM = 3'd0;
parameter [1:0] RECRC_CHK = 2'd0;
parameter RECRC_CHK_TRIM = "FALSE";
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
parameter [1:0] RP_AUTO_SPD = 2'd0;
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'd0;
parameter SELECT_DLL_IF = "FALSE";
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'd0;
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'd0;
parameter [0:0] SPARE_BIT0 = 1'd0;
parameter [0:0] SPARE_BIT1 = 1'd0;
parameter [0:0] SPARE_BIT2 = 1'd0;
parameter [0:0] SPARE_BIT3 = 1'd0;
parameter [0:0] SPARE_BIT4 = 1'd0;
parameter [0:0] SPARE_BIT5 = 1'd0;
parameter [0:0] SPARE_BIT6 = 1'd0;
parameter [0:0] SPARE_BIT7 = 1'd0;
parameter [0:0] SPARE_BIT8 = 1'd0;
parameter [7:0] SPARE_BYTE0 = 8'd0;
parameter [7:0] SPARE_BYTE1 = 8'd0;
parameter [7:0] SPARE_BYTE2 = 8'd0;
parameter [7:0] SPARE_BYTE3 = 8'd0;
parameter [31:0] SPARE_WORD0 = 32'd0;
parameter [31:0] SPARE_WORD1 = 32'd0;
parameter [31:0] SPARE_WORD2 = 32'd0;
parameter [31:0] SPARE_WORD3 = 32'd0;
parameter SSL_MESSAGE_AUTO = "FALSE";
parameter TECRC_EP_INV = "FALSE";
parameter TL_RBYPASS = "FALSE";
parameter [1:0] TL_RX_RAM_RDATA_LATENCY = 2'd1;
parameter TL_TFC_DISABLE = "FALSE";
parameter TL_TX_CHECKS_DISABLE = "FALSE";
parameter [1:0] TL_TX_RAM_RDATA_LATENCY = 2'd1;
parameter TRN_DW = "FALSE";
parameter TRN_NP_FC = "FALSE";
parameter UPCONFIG_CAPABLE = "FALSE";
parameter UPSTREAM_FACING = "FALSE";
parameter UR_ATOMIC = "FALSE";
parameter UR_CFG1 = "FALSE";
parameter UR_INV_REQ = "FALSE";
parameter UR_PRS_RESPONSE = "FALSE";
parameter USER_CLK2_DIV2 = "FALSE";
parameter USE_RID_PINS = "FALSE";
parameter VC0_CPL_INFINITE = "FALSE";
parameter [12:0] VC0_RX_RAM_LIMIT = 13'd0;
parameter [6:0] VC0_TOTAL_CREDITS_CH = 7'd36;
parameter [6:0] VC0_TOTAL_CREDITS_NPH = 7'd12;
parameter [6:0] VC0_TOTAL_CREDITS_PH = 7'd32;
parameter [11:0] VC_BASE_PTR = 12'd0;
parameter [15:0] VC_CAP_ID = 16'd0;
parameter [11:0] VC_CAP_NEXTPTR = 12'd0;
parameter VC_CAP_ON = "FALSE";
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
parameter [3:0] VC_CAP_VERSION = 4'd0;
parameter [11:0] VSEC_BASE_PTR = 12'd0;
parameter [15:0] VSEC_CAP_HDR_ID = 16'd0;
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'd0;
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'd0;
parameter [15:0] VSEC_CAP_ID = 16'd0;
parameter VSEC_CAP_IS_LINK_VISIBLE = "FALSE";
parameter [11:0] VSEC_CAP_NEXTPTR = 12'd0;
parameter VSEC_CAP_ON = "FALSE";
parameter [3:0] VSEC_CAP_VERSION = 4'd0;
parameter [2:0] DEV_CAP_ENDPOINT_L0S_LATENCY = 3'd0;
parameter [2:0] DEV_CAP_ENDPOINT_L1_LATENCY = 3'd0;
parameter [1:0] DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 2'd0;
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 3'd0;
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 3'd0;
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 3'd0;
parameter [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 3'd0;
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 3'd0;
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 3'd0;
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN1 = 3'd0;
parameter [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN2 = 3'd0;
parameter [0:0] LINK_CONTROL_RCB = 1'd0;
parameter [0:0] MSI_CAP_MULTIMSG_EXTENSION = 1'd0;
parameter [2:0] PM_CAP_AUXCURRENT = 3'd0;
parameter [1:0] SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 2'd0;
parameter [2:0] USER_CLK_FREQ = 3'd0;
parameter [2:0] PL_AUTO_CONFIG = 3'd0;
parameter [0:0] TL_RX_RAM_RADDR_LATENCY = 1'd0;
parameter [0:0] TL_RX_RAM_WRITE_LATENCY = 1'd0;
parameter [0:0] TL_TX_RAM_RADDR_LATENCY = 1'd0;
parameter [0:0] TL_TX_RAM_WRITE_LATENCY = 1'd0;
parameter [10:0] VC0_TOTAL_CREDITS_CD = 11'd0;
parameter [10:0] VC0_TOTAL_CREDITS_NPD = 11'd0;
parameter [10:0] VC0_TOTAL_CREDITS_PD = 11'd0;
parameter [4:0] VC0_TX_LASTPACKET = 5'd0;
parameter [1:0] CFG_ECRC_ERR_CPLSTAT = 2'd0;
PCIE_2_1_VPR #(
.AER_BASE_PTR(AER_BASE_PTR),
.AER_CAP_ECRC_CHECK_CAPABLE(AER_CAP_ECRC_CHECK_CAPABLE == "TRUE"),
.AER_CAP_ECRC_GEN_CAPABLE(AER_CAP_ECRC_GEN_CAPABLE == "TRUE"),
.AER_CAP_ID(AER_CAP_ID),
.AER_CAP_MULTIHEADER(AER_CAP_MULTIHEADER == "TRUE"),
.AER_CAP_NEXTPTR(AER_CAP_NEXTPTR),
.AER_CAP_ON(AER_CAP_ON == "TRUE"),
.AER_CAP_OPTIONAL_ERR_SUPPORT(AER_CAP_OPTIONAL_ERR_SUPPORT),
.AER_CAP_PERMIT_ROOTERR_UPDATE(AER_CAP_PERMIT_ROOTERR_UPDATE == "TRUE"),
.AER_CAP_VERSION(AER_CAP_VERSION),
.ALLOW_X8_GEN2(ALLOW_X8_GEN2 == "TRUE"),
.BAR0(BAR0),
.BAR1(BAR1),
.BAR2(BAR2),
.BAR3(BAR3),
.BAR4(BAR4),
.BAR5(BAR5),
.CAPABILITIES_PTR(CAPABILITIES_PTR),
.CARDBUS_CIS_POINTER(CARDBUS_CIS_POINTER),
.CLASS_CODE(CLASS_CODE),
.CMD_INTX_IMPLEMENTED(CMD_INTX_IMPLEMENTED == "TRUE"),
.CPL_TIMEOUT_DISABLE_SUPPORTED(CPL_TIMEOUT_DISABLE_SUPPORTED == "TRUE"),
.CPL_TIMEOUT_RANGES_SUPPORTED(CPL_TIMEOUT_RANGES_SUPPORTED),
.CRM_MODULE_RSTS(CRM_MODULE_RSTS),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED(DEV_CAP2_ARI_FORWARDING_SUPPORTED == "TRUE"),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED(DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED == "TRUE"),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED(DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED == "TRUE"),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED(DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED == "TRUE"),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED(DEV_CAP2_CAS128_COMPLETER_SUPPORTED == "TRUE"),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED(DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED == "TRUE"),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED(DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED == "TRUE"),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED(DEV_CAP2_LTR_MECHANISM_SUPPORTED == "TRUE"),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES(DEV_CAP2_MAX_ENDEND_TLP_PREFIXES),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING(DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING == "TRUE"),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED(DEV_CAP2_TPH_COMPLETER_SUPPORTED),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE(DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE == "TRUE"),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE(DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE == "TRUE"),
.DEV_CAP_EXT_TAG_SUPPORTED(DEV_CAP_EXT_TAG_SUPPORTED == "TRUE"),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE(DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE == "TRUE"),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(DEV_CAP_MAX_PAYLOAD_SUPPORTED),
.DEV_CAP_ROLE_BASED_ERROR(DEV_CAP_ROLE_BASED_ERROR == "TRUE"),
.DEV_CAP_RSVD_14_12(DEV_CAP_RSVD_14_12),
.DEV_CAP_RSVD_17_16(DEV_CAP_RSVD_17_16),
.DEV_CAP_RSVD_31_29(DEV_CAP_RSVD_31_29),
.DEV_CONTROL_AUX_POWER_SUPPORTED(DEV_CONTROL_AUX_POWER_SUPPORTED == "TRUE"),
.DEV_CONTROL_EXT_TAG_DEFAULT(DEV_CONTROL_EXT_TAG_DEFAULT == "TRUE"),
.DISABLE_ASPM_L1_TIMER(DISABLE_ASPM_L1_TIMER == "TRUE"),
.DISABLE_BAR_FILTERING(DISABLE_BAR_FILTERING == "TRUE"),
.DISABLE_ERR_MSG(DISABLE_ERR_MSG == "TRUE"),
.DISABLE_ID_CHECK(DISABLE_ID_CHECK == "TRUE"),
.DISABLE_LANE_REVERSAL(DISABLE_LANE_REVERSAL == "TRUE"),
.DISABLE_LOCKED_FILTER(DISABLE_LOCKED_FILTER == "TRUE"),
.DISABLE_PPM_FILTER(DISABLE_PPM_FILTER == "TRUE"),
.DISABLE_RX_POISONED_RESP(DISABLE_RX_POISONED_RESP == "TRUE"),
.DISABLE_RX_TC_FILTER(DISABLE_RX_TC_FILTER == "TRUE"),
.DISABLE_SCRAMBLING(DISABLE_SCRAMBLING == "TRUE"),
.DNSTREAM_LINK_NUM(DNSTREAM_LINK_NUM),
.DSN_BASE_PTR(DSN_BASE_PTR),
.DSN_CAP_ID(DSN_CAP_ID),
.DSN_CAP_NEXTPTR(DSN_CAP_NEXTPTR),
.DSN_CAP_ON(DSN_CAP_ON == "TRUE"),
.DSN_CAP_VERSION(DSN_CAP_VERSION),
.ENABLE_MSG_ROUTE(ENABLE_MSG_ROUTE),
.ENABLE_RX_TD_ECRC_TRIM(ENABLE_RX_TD_ECRC_TRIM == "TRUE"),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED(ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED == "TRUE"),
.ENTER_RVRY_EI_L0(ENTER_RVRY_EI_L0 == "TRUE"),
.EXIT_LOOPBACK_ON_EI(EXIT_LOOPBACK_ON_EI == "TRUE"),
.EXPANSION_ROM(EXPANSION_ROM),
.EXT_CFG_CAP_PTR(EXT_CFG_CAP_PTR),
.EXT_CFG_XP_CAP_PTR(EXT_CFG_XP_CAP_PTR),
.HEADER_TYPE(HEADER_TYPE),
.INFER_EI(INFER_EI),
.INTERRUPT_PIN(INTERRUPT_PIN),
.INTERRUPT_STAT_AUTO(INTERRUPT_STAT_AUTO == "TRUE"),
.IS_SWITCH(IS_SWITCH == "TRUE"),
.LAST_CONFIG_DWORD(LAST_CONFIG_DWORD),
.LINK_CAP_ASPM_OPTIONALITY(LINK_CAP_ASPM_OPTIONALITY == "TRUE"),
.LINK_CAP_ASPM_SUPPORT(LINK_CAP_ASPM_SUPPORT),
.LINK_CAP_CLOCK_POWER_MANAGEMENT(LINK_CAP_CLOCK_POWER_MANAGEMENT == "TRUE"),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP(LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP == "TRUE"),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP(LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP == "TRUE"),
.LINK_CAP_MAX_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.LINK_CAP_MAX_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_RSVD_23(LINK_CAP_RSVD_23),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE(LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE == "TRUE"),
.LINK_CTRL2_DEEMPHASIS(LINK_CTRL2_DEEMPHASIS == "TRUE"),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE(LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE == "TRUE"),
.LINK_CTRL2_TARGET_LINK_SPEED(LINK_CTRL2_TARGET_LINK_SPEED),
.LINK_STATUS_SLOT_CLOCK_CONFIG(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE"),
.LL_ACK_TIMEOUT(LL_ACK_TIMEOUT),
.LL_ACK_TIMEOUT_EN(LL_ACK_TIMEOUT_EN == "TRUE"),
.LL_ACK_TIMEOUT_FUNC(LL_ACK_TIMEOUT_FUNC),
.LL_REPLAY_TIMEOUT(LL_REPLAY_TIMEOUT),
.LL_REPLAY_TIMEOUT_EN(LL_REPLAY_TIMEOUT_EN == "TRUE"),
.LL_REPLAY_TIMEOUT_FUNC(LL_REPLAY_TIMEOUT_FUNC),
.LTSSM_MAX_LINK_WIDTH(LTSSM_MAX_LINK_WIDTH),
.MPS_FORCE(MPS_FORCE == "TRUE"),
.MSIX_BASE_PTR(MSIX_BASE_PTR),
.MSIX_CAP_ID(MSIX_CAP_ID),
.MSIX_CAP_NEXTPTR(MSIX_CAP_NEXTPTR),
.MSIX_CAP_ON(MSIX_CAP_ON == "TRUE"),
.MSIX_CAP_PBA_BIR(MSIX_CAP_PBA_BIR),
.MSIX_CAP_PBA_OFFSET(MSIX_CAP_PBA_OFFSET),
.MSIX_CAP_TABLE_BIR(MSIX_CAP_TABLE_BIR),
.MSIX_CAP_TABLE_OFFSET(MSIX_CAP_TABLE_OFFSET),
.MSIX_CAP_TABLE_SIZE(MSIX_CAP_TABLE_SIZE),
.MSI_BASE_PTR(MSI_BASE_PTR),
.MSI_CAP_64_BIT_ADDR_CAPABLE(MSI_CAP_64_BIT_ADDR_CAPABLE == "TRUE"),
.MSI_CAP_ID(MSI_CAP_ID),
.MSI_CAP_MULTIMSGCAP(MSI_CAP_MULTIMSGCAP),
.MSI_CAP_NEXTPTR(MSI_CAP_NEXTPTR),
.MSI_CAP_ON(MSI_CAP_ON == "TRUE"),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE(MSI_CAP_PER_VECTOR_MASKING_CAPABLE == "TRUE"),
.N_FTS_COMCLK_GEN1(N_FTS_COMCLK_GEN1),
.N_FTS_COMCLK_GEN2(N_FTS_COMCLK_GEN2),
.N_FTS_GEN1(N_FTS_GEN1),
.N_FTS_GEN2(N_FTS_GEN2),
.PCIE_BASE_PTR(PCIE_BASE_PTR),
.PCIE_CAP_CAPABILITY_ID(PCIE_CAP_CAPABILITY_ID),
.PCIE_CAP_CAPABILITY_VERSION(PCIE_CAP_CAPABILITY_VERSION),
.PCIE_CAP_DEVICE_PORT_TYPE(PCIE_CAP_DEVICE_PORT_TYPE),
.PCIE_CAP_NEXTPTR(PCIE_CAP_NEXTPTR),
.PCIE_CAP_ON(PCIE_CAP_ON == "TRUE"),
.PCIE_CAP_RSVD_15_14(PCIE_CAP_RSVD_15_14),
.PCIE_CAP_SLOT_IMPLEMENTED(PCIE_CAP_SLOT_IMPLEMENTED == "TRUE"),
.PCIE_REVISION(PCIE_REVISION),
.PL_FAST_TRAIN(PL_FAST_TRAIN == "TRUE"),
.PM_ASPML0S_TIMEOUT(PM_ASPML0S_TIMEOUT),
.PM_ASPML0S_TIMEOUT_EN(PM_ASPML0S_TIMEOUT_EN == "TRUE"),
.PM_ASPML0S_TIMEOUT_FUNC(PM_ASPML0S_TIMEOUT_FUNC),
.PM_ASPM_FASTEXIT(PM_ASPM_FASTEXIT == "TRUE"),
.PM_BASE_PTR(PM_BASE_PTR),
.PM_CAP_D1SUPPORT(PM_CAP_D1SUPPORT == "TRUE"),
.PM_CAP_D2SUPPORT(PM_CAP_D2SUPPORT == "TRUE"),
.PM_CAP_DSI(PM_CAP_DSI == "TRUE"),
.PM_CAP_ID(PM_CAP_ID),
.PM_CAP_NEXTPTR(PM_CAP_NEXTPTR),
.PM_CAP_ON(PM_CAP_ON == "TRUE"),
.PM_CAP_PMESUPPORT(PM_CAP_PMESUPPORT),
.PM_CAP_PME_CLOCK(PM_CAP_PME_CLOCK == "TRUE"),
.PM_CAP_RSVD_04(PM_CAP_RSVD_04),
.PM_CAP_VERSION(PM_CAP_VERSION),
.PM_CSR_B2B3(PM_CSR_B2B3 == "TRUE"),
.PM_CSR_BPCCEN(PM_CSR_BPCCEN == "TRUE"),
.PM_CSR_NOSOFTRST(PM_CSR_NOSOFTRST == "TRUE"),
.PM_DATA0(PM_DATA0),
.PM_DATA1(PM_DATA1),
.PM_DATA2(PM_DATA2),
.PM_DATA3(PM_DATA3),
.PM_DATA4(PM_DATA4),
.PM_DATA5(PM_DATA5),
.PM_DATA6(PM_DATA6),
.PM_DATA7(PM_DATA7),
.PM_DATA_SCALE0(PM_DATA_SCALE0),
.PM_DATA_SCALE1(PM_DATA_SCALE1),
.PM_DATA_SCALE2(PM_DATA_SCALE2),
.PM_DATA_SCALE3(PM_DATA_SCALE3),
.PM_DATA_SCALE4(PM_DATA_SCALE4),
.PM_DATA_SCALE5(PM_DATA_SCALE5),
.PM_DATA_SCALE6(PM_DATA_SCALE6),
.PM_DATA_SCALE7(PM_DATA_SCALE7),
.PM_MF(PM_MF == "TRUE"),
.RBAR_BASE_PTR(RBAR_BASE_PTR),
.RBAR_CAP_CONTROL_ENCODEDBAR0(RBAR_CAP_CONTROL_ENCODEDBAR0),
.RBAR_CAP_CONTROL_ENCODEDBAR1(RBAR_CAP_CONTROL_ENCODEDBAR1),
.RBAR_CAP_CONTROL_ENCODEDBAR2(RBAR_CAP_CONTROL_ENCODEDBAR2),
.RBAR_CAP_CONTROL_ENCODEDBAR3(RBAR_CAP_CONTROL_ENCODEDBAR3),
.RBAR_CAP_CONTROL_ENCODEDBAR4(RBAR_CAP_CONTROL_ENCODEDBAR4),
.RBAR_CAP_CONTROL_ENCODEDBAR5(RBAR_CAP_CONTROL_ENCODEDBAR5),
.RBAR_CAP_ID(RBAR_CAP_ID),
.RBAR_CAP_INDEX0(RBAR_CAP_INDEX0),
.RBAR_CAP_INDEX1(RBAR_CAP_INDEX1),
.RBAR_CAP_INDEX2(RBAR_CAP_INDEX2),
.RBAR_CAP_INDEX3(RBAR_CAP_INDEX3),
.RBAR_CAP_INDEX4(RBAR_CAP_INDEX4),
.RBAR_CAP_INDEX5(RBAR_CAP_INDEX5),
.RBAR_CAP_NEXTPTR(RBAR_CAP_NEXTPTR),
.RBAR_CAP_ON(RBAR_CAP_ON == "TRUE"),
.RBAR_CAP_SUP0(RBAR_CAP_SUP0),
.RBAR_CAP_SUP1(RBAR_CAP_SUP1),
.RBAR_CAP_SUP2(RBAR_CAP_SUP2),
.RBAR_CAP_SUP3(RBAR_CAP_SUP3),
.RBAR_CAP_SUP4(RBAR_CAP_SUP4),
.RBAR_CAP_SUP5(RBAR_CAP_SUP5),
.RBAR_CAP_VERSION(RBAR_CAP_VERSION),
.RBAR_NUM(RBAR_NUM),
.RECRC_CHK(RECRC_CHK),
.RECRC_CHK_TRIM(RECRC_CHK_TRIM == "TRUE"),
.ROOT_CAP_CRS_SW_VISIBILITY(ROOT_CAP_CRS_SW_VISIBILITY == "TRUE"),
.RP_AUTO_SPD(RP_AUTO_SPD),
.RP_AUTO_SPD_LOOPCNT(RP_AUTO_SPD_LOOPCNT),
.SELECT_DLL_IF(SELECT_DLL_IF == "TRUE"),
.SLOT_CAP_ATT_BUTTON_PRESENT(SLOT_CAP_ATT_BUTTON_PRESENT == "TRUE"),
.SLOT_CAP_ATT_INDICATOR_PRESENT(SLOT_CAP_ATT_INDICATOR_PRESENT == "TRUE"),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT(SLOT_CAP_ELEC_INTERLOCK_PRESENT == "TRUE"),
.SLOT_CAP_HOTPLUG_CAPABLE(SLOT_CAP_HOTPLUG_CAPABLE == "TRUE"),
.SLOT_CAP_HOTPLUG_SURPRISE(SLOT_CAP_HOTPLUG_SURPRISE == "TRUE"),
.SLOT_CAP_MRL_SENSOR_PRESENT(SLOT_CAP_MRL_SENSOR_PRESENT == "TRUE"),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT(SLOT_CAP_NO_CMD_COMPLETED_SUPPORT == "TRUE"),
.SLOT_CAP_PHYSICAL_SLOT_NUM(SLOT_CAP_PHYSICAL_SLOT_NUM),
.SLOT_CAP_POWER_CONTROLLER_PRESENT(SLOT_CAP_POWER_CONTROLLER_PRESENT == "TRUE"),
.SLOT_CAP_POWER_INDICATOR_PRESENT(SLOT_CAP_POWER_INDICATOR_PRESENT == "TRUE"),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE(SLOT_CAP_SLOT_POWER_LIMIT_VALUE),
.SPARE_BIT0(SPARE_BIT0),
.SPARE_BIT1(SPARE_BIT1),
.SPARE_BIT2(SPARE_BIT2),
.SPARE_BIT3(SPARE_BIT3),
.SPARE_BIT4(SPARE_BIT4),
.SPARE_BIT5(SPARE_BIT5),
.SPARE_BIT6(SPARE_BIT6),
.SPARE_BIT7(SPARE_BIT7),
.SPARE_BIT8(SPARE_BIT8),
.SPARE_BYTE0(SPARE_BYTE0),
.SPARE_BYTE1(SPARE_BYTE1),
.SPARE_BYTE2(SPARE_BYTE2),
.SPARE_BYTE3(SPARE_BYTE3),
.SPARE_WORD0(SPARE_WORD0),
.SPARE_WORD1(SPARE_WORD1),
.SPARE_WORD2(SPARE_WORD2),
.SPARE_WORD3(SPARE_WORD3),
.SSL_MESSAGE_AUTO(SSL_MESSAGE_AUTO == "TRUE"),
.TECRC_EP_INV(TECRC_EP_INV == "TRUE"),
.TL_RBYPASS(TL_RBYPASS == "TRUE"),
.TL_RX_RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.TL_TFC_DISABLE(TL_TFC_DISABLE == "TRUE"),
.TL_TX_CHECKS_DISABLE(TL_TX_CHECKS_DISABLE == "TRUE"),
.TL_TX_RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.TRN_DW(TRN_DW == "TRUE"),
.TRN_NP_FC(TRN_NP_FC == "TRUE"),
.UPCONFIG_CAPABLE(UPCONFIG_CAPABLE == "TRUE"),
.UPSTREAM_FACING(UPSTREAM_FACING == "TRUE"),
.UR_ATOMIC(UR_ATOMIC == "TRUE"),
.UR_CFG1(UR_CFG1 == "TRUE"),
.UR_INV_REQ(UR_INV_REQ == "TRUE"),
.UR_PRS_RESPONSE(UR_PRS_RESPONSE == "TRUE"),
.USER_CLK2_DIV2(USER_CLK2_DIV2 == "TRUE"),
.USE_RID_PINS(USE_RID_PINS == "TRUE"),
.VC0_CPL_INFINITE(VC0_CPL_INFINITE == "TRUE"),
.VC0_RX_RAM_LIMIT(VC0_RX_RAM_LIMIT),
.VC0_TOTAL_CREDITS_CH(VC0_TOTAL_CREDITS_CH),
.VC0_TOTAL_CREDITS_NPH(VC0_TOTAL_CREDITS_NPH),
.VC0_TOTAL_CREDITS_PH(VC0_TOTAL_CREDITS_PH),
.VC_BASE_PTR(VC_BASE_PTR),
.VC_CAP_ID(VC_CAP_ID),
.VC_CAP_NEXTPTR(VC_CAP_NEXTPTR),
.VC_CAP_ON(VC_CAP_ON == "TRUE"),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS(VC_CAP_REJECT_SNOOP_TRANSACTIONS == "TRUE"),
.VC_CAP_VERSION(VC_CAP_VERSION),
.VSEC_BASE_PTR(VSEC_BASE_PTR),
.VSEC_CAP_HDR_ID(VSEC_CAP_HDR_ID),
.VSEC_CAP_HDR_LENGTH(VSEC_CAP_HDR_LENGTH),
.VSEC_CAP_HDR_REVISION(VSEC_CAP_HDR_REVISION),
.VSEC_CAP_ID(VSEC_CAP_ID),
.VSEC_CAP_IS_LINK_VISIBLE(VSEC_CAP_IS_LINK_VISIBLE == "TRUE"),
.VSEC_CAP_NEXTPTR(VSEC_CAP_NEXTPTR),
.VSEC_CAP_ON(VSEC_CAP_ON == "TRUE"),
.VSEC_CAP_VERSION(VSEC_CAP_VERSION),
.DEV_CAP_ENDPOINT_L0S_LATENCY(DEV_CAP_ENDPOINT_L0S_LATENCY),
.DEV_CAP_ENDPOINT_L1_LATENCY(DEV_CAP_ENDPOINT_L1_LATENCY),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT(DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1(LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2(LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1(LINK_CAP_L0S_EXIT_LATENCY_GEN1),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2(LINK_CAP_L0S_EXIT_LATENCY_GEN2),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1(LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2(LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2),
.LINK_CAP_L1_EXIT_LATENCY_GEN1(LINK_CAP_L1_EXIT_LATENCY_GEN1),
.LINK_CAP_L1_EXIT_LATENCY_GEN2(LINK_CAP_L1_EXIT_LATENCY_GEN2),
.LINK_CONTROL_RCB(LINK_CONTROL_RCB),
.MSI_CAP_MULTIMSG_EXTENSION(MSI_CAP_MULTIMSG_EXTENSION),
.PM_CAP_AUXCURRENT(PM_CAP_AUXCURRENT),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE(SLOT_CAP_SLOT_POWER_LIMIT_SCALE),
.USER_CLK_FREQ(USER_CLK_FREQ),
.PL_AUTO_CONFIG(PL_AUTO_CONFIG),
.TL_RX_RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.TL_RX_RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY),
.TL_TX_RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.TL_TX_RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY),
.VC0_TOTAL_CREDITS_CD(VC0_TOTAL_CREDITS_CD),
.VC0_TOTAL_CREDITS_NPD(VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_PD(VC0_TOTAL_CREDITS_PD),
.VC0_TX_LASTPACKET(VC0_TX_LASTPACKET),
.CFG_ECRC_ERR_CPLSTAT(CFG_ECRC_ERR_CPLSTAT)
) _TECHMAP_REPLACE_ (
.CFGAERECRCCHECKEN(CFGAERECRCCHECKEN),
.CFGAERECRCGENEN(CFGAERECRCGENEN),
.CFGAERINTERRUPTMSGNUM(CFGAERINTERRUPTMSGNUM),
.CFGAERROOTERRCORRERRRECEIVED(CFGAERROOTERRCORRERRRECEIVED),
.CFGAERROOTERRCORRERRREPORTINGEN(CFGAERROOTERRCORRERRREPORTINGEN),
.CFGAERROOTERRFATALERRRECEIVED(CFGAERROOTERRFATALERRRECEIVED),
.CFGAERROOTERRFATALERRREPORTINGEN(CFGAERROOTERRFATALERRREPORTINGEN),
.CFGAERROOTERRNONFATALERRRECEIVED(CFGAERROOTERRNONFATALERRRECEIVED),
.CFGAERROOTERRNONFATALERRREPORTINGEN(CFGAERROOTERRNONFATALERRREPORTINGEN),
.CFGBRIDGESERREN(CFGBRIDGESERREN),
.CFGCOMMANDBUSMASTERENABLE(CFGCOMMANDBUSMASTERENABLE),
.CFGCOMMANDINTERRUPTDISABLE(CFGCOMMANDINTERRUPTDISABLE),
.CFGCOMMANDIOENABLE(CFGCOMMANDIOENABLE),
.CFGCOMMANDMEMENABLE(CFGCOMMANDMEMENABLE),
.CFGCOMMANDSERREN(CFGCOMMANDSERREN),
.CFGDEVCONTROL2ARIFORWARDEN(CFGDEVCONTROL2ARIFORWARDEN),
.CFGDEVCONTROL2ATOMICEGRESSBLOCK(CFGDEVCONTROL2ATOMICEGRESSBLOCK),
.CFGDEVCONTROL2ATOMICREQUESTEREN(CFGDEVCONTROL2ATOMICREQUESTEREN),
.CFGDEVCONTROL2CPLTIMEOUTDIS(CFGDEVCONTROL2CPLTIMEOUTDIS),
.CFGDEVCONTROL2CPLTIMEOUTVAL(CFGDEVCONTROL2CPLTIMEOUTVAL),
.CFGDEVCONTROL2IDOCPLEN(CFGDEVCONTROL2IDOCPLEN),
.CFGDEVCONTROL2IDOREQEN(CFGDEVCONTROL2IDOREQEN),
.CFGDEVCONTROL2LTREN(CFGDEVCONTROL2LTREN),
.CFGDEVCONTROL2TLPPREFIXBLOCK(CFGDEVCONTROL2TLPPREFIXBLOCK),
.CFGDEVCONTROLAUXPOWEREN(CFGDEVCONTROLAUXPOWEREN),
.CFGDEVCONTROLCORRERRREPORTINGEN(CFGDEVCONTROLCORRERRREPORTINGEN),
.CFGDEVCONTROLENABLERO(CFGDEVCONTROLENABLERO),
.CFGDEVCONTROLEXTTAGEN(CFGDEVCONTROLEXTTAGEN),
.CFGDEVCONTROLFATALERRREPORTINGEN(CFGDEVCONTROLFATALERRREPORTINGEN),
.CFGDEVCONTROLMAXPAYLOAD(CFGDEVCONTROLMAXPAYLOAD),
.CFGDEVCONTROLMAXREADREQ(CFGDEVCONTROLMAXREADREQ),
.CFGDEVCONTROLNONFATALREPORTINGEN(CFGDEVCONTROLNONFATALREPORTINGEN),
.CFGDEVCONTROLNOSNOOPEN(CFGDEVCONTROLNOSNOOPEN),
.CFGDEVCONTROLPHANTOMEN(CFGDEVCONTROLPHANTOMEN),
.CFGDEVCONTROLURERRREPORTINGEN(CFGDEVCONTROLURERRREPORTINGEN),
.CFGDEVID(CFGDEVID),
.CFGDEVSTATUSCORRERRDETECTED(CFGDEVSTATUSCORRERRDETECTED),
.CFGDEVSTATUSFATALERRDETECTED(CFGDEVSTATUSFATALERRDETECTED),
.CFGDEVSTATUSNONFATALERRDETECTED(CFGDEVSTATUSNONFATALERRDETECTED),
.CFGDEVSTATUSURDETECTED(CFGDEVSTATUSURDETECTED),
.CFGDSBUSNUMBER(CFGDSBUSNUMBER),
.CFGDSDEVICENUMBER(CFGDSDEVICENUMBER),
.CFGDSFUNCTIONNUMBER(CFGDSFUNCTIONNUMBER),
.CFGDSN(CFGDSN),
.CFGERRACSN(CFGERRACSN),
.CFGERRAERHEADERLOG(CFGERRAERHEADERLOG),
.CFGERRAERHEADERLOGSETN(CFGERRAERHEADERLOGSETN),
.CFGERRATOMICEGRESSBLOCKEDN(CFGERRATOMICEGRESSBLOCKEDN),
.CFGERRCORN(CFGERRCORN),
.CFGERRCPLABORTN(CFGERRCPLABORTN),
.CFGERRCPLRDYN(CFGERRCPLRDYN),
.CFGERRCPLTIMEOUTN(CFGERRCPLTIMEOUTN),
.CFGERRCPLUNEXPECTN(CFGERRCPLUNEXPECTN),
.CFGERRECRCN(CFGERRECRCN),
.CFGERRINTERNALCORN(CFGERRINTERNALCORN),
.CFGERRINTERNALUNCORN(CFGERRINTERNALUNCORN),
.CFGERRLOCKEDN(CFGERRLOCKEDN),
.CFGERRMALFORMEDN(CFGERRMALFORMEDN),
.CFGERRMCBLOCKEDN(CFGERRMCBLOCKEDN),
.CFGERRNORECOVERYN(CFGERRNORECOVERYN),
.CFGERRPOISONEDN(CFGERRPOISONEDN),
.CFGERRPOSTEDN(CFGERRPOSTEDN),
.CFGERRTLPCPLHEADER(CFGERRTLPCPLHEADER),
.CFGERRURN(CFGERRURN),
.CFGFORCECOMMONCLOCKOFF(CFGFORCECOMMONCLOCKOFF),
.CFGFORCEEXTENDEDSYNCON(CFGFORCEEXTENDEDSYNCON),
.CFGFORCEMPS(CFGFORCEMPS),
.CFGINTERRUPTASSERTN(CFGINTERRUPTASSERTN),
.CFGINTERRUPTDI(CFGINTERRUPTDI),
.CFGINTERRUPTDO(CFGINTERRUPTDO),
.CFGINTERRUPTMMENABLE(CFGINTERRUPTMMENABLE),
.CFGINTERRUPTMSIENABLE(CFGINTERRUPTMSIENABLE),
.CFGINTERRUPTMSIXENABLE(CFGINTERRUPTMSIXENABLE),
.CFGINTERRUPTMSIXFM(CFGINTERRUPTMSIXFM),
.CFGINTERRUPTN(CFGINTERRUPTN),
.CFGINTERRUPTRDYN(CFGINTERRUPTRDYN),
.CFGINTERRUPTSTATN(CFGINTERRUPTSTATN),
.CFGLINKCONTROLASPMCONTROL(CFGLINKCONTROLASPMCONTROL),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN(CFGLINKCONTROLAUTOBANDWIDTHINTEN),
.CFGLINKCONTROLBANDWIDTHINTEN(CFGLINKCONTROLBANDWIDTHINTEN),
.CFGLINKCONTROLCLOCKPMEN(CFGLINKCONTROLCLOCKPMEN),
.CFGLINKCONTROLCOMMONCLOCK(CFGLINKCONTROLCOMMONCLOCK),
.CFGLINKCONTROLEXTENDEDSYNC(CFGLINKCONTROLEXTENDEDSYNC),
.CFGLINKCONTROLHWAUTOWIDTHDIS(CFGLINKCONTROLHWAUTOWIDTHDIS),
.CFGLINKCONTROLLINKDISABLE(CFGLINKCONTROLLINKDISABLE),
.CFGLINKCONTROLRCB(CFGLINKCONTROLRCB),
.CFGLINKCONTROLRETRAINLINK(CFGLINKCONTROLRETRAINLINK),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS(CFGLINKSTATUSAUTOBANDWIDTHSTATUS),
.CFGLINKSTATUSBANDWIDTHSTATUS(CFGLINKSTATUSBANDWIDTHSTATUS),
.CFGLINKSTATUSCURRENTSPEED(CFGLINKSTATUSCURRENTSPEED),
.CFGLINKSTATUSDLLACTIVE(CFGLINKSTATUSDLLACTIVE),
.CFGLINKSTATUSLINKTRAINING(CFGLINKSTATUSLINKTRAINING),
.CFGLINKSTATUSNEGOTIATEDWIDTH(CFGLINKSTATUSNEGOTIATEDWIDTH),
.CFGMGMTBYTEENN(CFGMGMTBYTEENN),
.CFGMGMTDI(CFGMGMTDI),
.CFGMGMTDO(CFGMGMTDO),
.CFGMGMTDWADDR(CFGMGMTDWADDR),
.CFGMGMTRDENN(CFGMGMTRDENN),
.CFGMGMTRDWRDONEN(CFGMGMTRDWRDONEN),
.CFGMGMTWRENN(CFGMGMTWRENN),
.CFGMGMTWRREADONLYN(CFGMGMTWRREADONLYN),
.CFGMGMTWRRW1CASRWN(CFGMGMTWRRW1CASRWN),
.CFGMSGDATA(CFGMSGDATA),
.CFGMSGRECEIVED(CFGMSGRECEIVED),
.CFGMSGRECEIVEDASSERTINTA(CFGMSGRECEIVEDASSERTINTA),
.CFGMSGRECEIVEDASSERTINTB(CFGMSGRECEIVEDASSERTINTB),
.CFGMSGRECEIVEDASSERTINTC(CFGMSGRECEIVEDASSERTINTC),
.CFGMSGRECEIVEDASSERTINTD(CFGMSGRECEIVEDASSERTINTD),
.CFGMSGRECEIVEDDEASSERTINTA(CFGMSGRECEIVEDDEASSERTINTA),
.CFGMSGRECEIVEDDEASSERTINTB(CFGMSGRECEIVEDDEASSERTINTB),
.CFGMSGRECEIVEDDEASSERTINTC(CFGMSGRECEIVEDDEASSERTINTC),
.CFGMSGRECEIVEDDEASSERTINTD(CFGMSGRECEIVEDDEASSERTINTD),
.CFGMSGRECEIVEDERRCOR(CFGMSGRECEIVEDERRCOR),
.CFGMSGRECEIVEDERRFATAL(CFGMSGRECEIVEDERRFATAL),
.CFGMSGRECEIVEDERRNONFATAL(CFGMSGRECEIVEDERRNONFATAL),
.CFGMSGRECEIVEDPMASNAK(CFGMSGRECEIVEDPMASNAK),
.CFGMSGRECEIVEDPMETO(CFGMSGRECEIVEDPMETO),
.CFGMSGRECEIVEDPMETOACK(CFGMSGRECEIVEDPMETOACK),
.CFGMSGRECEIVEDPMPME(CFGMSGRECEIVEDPMPME),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT(CFGMSGRECEIVEDSETSLOTPOWERLIMIT),
.CFGMSGRECEIVEDUNLOCK(CFGMSGRECEIVEDUNLOCK),
.CFGPCIECAPINTERRUPTMSGNUM(CFGPCIECAPINTERRUPTMSGNUM),
.CFGPCIELINKSTATE(CFGPCIELINKSTATE),
.CFGPMCSRPMEEN(CFGPMCSRPMEEN),
.CFGPMCSRPMESTATUS(CFGPMCSRPMESTATUS),
.CFGPMCSRPOWERSTATE(CFGPMCSRPOWERSTATE),
.CFGPMFORCESTATE(CFGPMFORCESTATE),
.CFGPMFORCESTATEENN(CFGPMFORCESTATEENN),
.CFGPMHALTASPML0SN(CFGPMHALTASPML0SN),
.CFGPMHALTASPML1N(CFGPMHALTASPML1N),
.CFGPMRCVASREQL1N(CFGPMRCVASREQL1N),
.CFGPMRCVENTERL1N(CFGPMRCVENTERL1N),
.CFGPMRCVENTERL23N(CFGPMRCVENTERL23N),
.CFGPMRCVREQACKN(CFGPMRCVREQACKN),
.CFGPMSENDPMETON(CFGPMSENDPMETON),
.CFGPMTURNOFFOKN(CFGPMTURNOFFOKN),
.CFGPMWAKEN(CFGPMWAKEN),
.CFGPORTNUMBER(CFGPORTNUMBER),
.CFGREVID(CFGREVID),
.CFGROOTCONTROLPMEINTEN(CFGROOTCONTROLPMEINTEN),
.CFGROOTCONTROLSYSERRCORRERREN(CFGROOTCONTROLSYSERRCORRERREN),
.CFGROOTCONTROLSYSERRFATALERREN(CFGROOTCONTROLSYSERRFATALERREN),
.CFGROOTCONTROLSYSERRNONFATALERREN(CFGROOTCONTROLSYSERRNONFATALERREN),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE(CFGSLOTCONTROLELECTROMECHILCTLPULSE),
.CFGSUBSYSID(CFGSUBSYSID),
.CFGSUBSYSVENDID(CFGSUBSYSVENDID),
.CFGTRANSACTION(CFGTRANSACTION),
.CFGTRANSACTIONADDR(CFGTRANSACTIONADDR),
.CFGTRANSACTIONTYPE(CFGTRANSACTIONTYPE),
.CFGTRNPENDINGN(CFGTRNPENDINGN),
.CFGVCTCVCMAP(CFGVCTCVCMAP),
.CFGVENDID(CFGVENDID),
.CMRSTN(CMRSTN),
.CMSTICKYRSTN(CMSTICKYRSTN),
.DBGMODE(DBGMODE),
.DBGSCLRA(DBGSCLRA),
.DBGSCLRB(DBGSCLRB),
.DBGSCLRC(DBGSCLRC),
.DBGSCLRD(DBGSCLRD),
.DBGSCLRE(DBGSCLRE),
.DBGSCLRF(DBGSCLRF),
.DBGSCLRG(DBGSCLRG),
.DBGSCLRH(DBGSCLRH),
.DBGSCLRI(DBGSCLRI),
.DBGSCLRJ(DBGSCLRJ),
.DBGSCLRK(DBGSCLRK),
.DBGSUBMODE(DBGSUBMODE),
.DBGVECA(DBGVECA),
.DBGVECB(DBGVECB),
.DBGVECC(DBGVECC),
.DLRSTN(DLRSTN),
.DRPADDR(DRPADDR),
.DRPCLK(DRPCLK),
.DRPDI(DRPDI),
.DRPDO(DRPDO),
.DRPEN(DRPEN),
.DRPRDY(DRPRDY),
.DRPWE(DRPWE),
.FUNCLVLRSTN(FUNCLVLRSTN),
.LL2BADDLLPERR(LL2BADDLLPERR),
.LL2BADTLPERR(LL2BADTLPERR),
.LL2LINKSTATUS(LL2LINKSTATUS),
.LL2PROTOCOLERR(LL2PROTOCOLERR),
.LL2RECEIVERERR(LL2RECEIVERERR),
.LL2REPLAYROERR(LL2REPLAYROERR),
.LL2REPLAYTOERR(LL2REPLAYTOERR),
.LL2SENDASREQL1(LL2SENDASREQL1),
.LL2SENDENTERL1(LL2SENDENTERL1),
.LL2SENDENTERL23(LL2SENDENTERL23),
.LL2SENDPMACK(LL2SENDPMACK),
.LL2SUSPENDNOW(LL2SUSPENDNOW),
.LL2SUSPENDOK(LL2SUSPENDOK),
.LL2TFCINIT1SEQ(LL2TFCINIT1SEQ),
.LL2TFCINIT2SEQ(LL2TFCINIT2SEQ),
.LL2TLPRCV(LL2TLPRCV),
.LL2TXIDLE(LL2TXIDLE),
.LNKCLKEN(LNKCLKEN),
.MIMRXRADDR(MIMRXRADDR),
.MIMRXRDATA(MIMRXRDATA),
.MIMRXREN(MIMRXREN),
.MIMRXWADDR(MIMRXWADDR),
.MIMRXWDATA(MIMRXWDATA),
.MIMRXWEN(MIMRXWEN),
.MIMTXRADDR(MIMTXRADDR),
.MIMTXRDATA(MIMTXRDATA),
.MIMTXREN(MIMTXREN),
.MIMTXWADDR(MIMTXWADDR),
.MIMTXWDATA(MIMTXWDATA),
.MIMTXWEN(MIMTXWEN),
.PIPECLK(PIPECLK),
.PIPERX0CHANISALIGNED(PIPERX0CHANISALIGNED),
.PIPERX0CHARISK(PIPERX0CHARISK),
.PIPERX0DATA(PIPERX0DATA),
.PIPERX0ELECIDLE(PIPERX0ELECIDLE),
.PIPERX0PHYSTATUS(PIPERX0PHYSTATUS),
.PIPERX0POLARITY(PIPERX0POLARITY),
.PIPERX0STATUS(PIPERX0STATUS),
.PIPERX0VALID(PIPERX0VALID),
.PIPERX1CHANISALIGNED(PIPERX1CHANISALIGNED),
.PIPERX1CHARISK(PIPERX1CHARISK),
.PIPERX1DATA(PIPERX1DATA),
.PIPERX1ELECIDLE(PIPERX1ELECIDLE),
.PIPERX1PHYSTATUS(PIPERX1PHYSTATUS),
.PIPERX1POLARITY(PIPERX1POLARITY),
.PIPERX1STATUS(PIPERX1STATUS),
.PIPERX1VALID(PIPERX1VALID),
.PIPERX2CHANISALIGNED(PIPERX2CHANISALIGNED),
.PIPERX2CHARISK(PIPERX2CHARISK),
.PIPERX2DATA(PIPERX2DATA),
.PIPERX2ELECIDLE(PIPERX2ELECIDLE),
.PIPERX2PHYSTATUS(PIPERX2PHYSTATUS),
.PIPERX2POLARITY(PIPERX2POLARITY),
.PIPERX2STATUS(PIPERX2STATUS),
.PIPERX2VALID(PIPERX2VALID),
.PIPERX3CHANISALIGNED(PIPERX3CHANISALIGNED),
.PIPERX3CHARISK(PIPERX3CHARISK),
.PIPERX3DATA(PIPERX3DATA),
.PIPERX3ELECIDLE(PIPERX3ELECIDLE),
.PIPERX3PHYSTATUS(PIPERX3PHYSTATUS),
.PIPERX3POLARITY(PIPERX3POLARITY),
.PIPERX3STATUS(PIPERX3STATUS),
.PIPERX3VALID(PIPERX3VALID),
.PIPERX4CHANISALIGNED(PIPERX4CHANISALIGNED),
.PIPERX4CHARISK(PIPERX4CHARISK),
.PIPERX4DATA(PIPERX4DATA),
.PIPERX4ELECIDLE(PIPERX4ELECIDLE),
.PIPERX4PHYSTATUS(PIPERX4PHYSTATUS),
.PIPERX4POLARITY(PIPERX4POLARITY),
.PIPERX4STATUS(PIPERX4STATUS),
.PIPERX4VALID(PIPERX4VALID),
.PIPERX5CHANISALIGNED(PIPERX5CHANISALIGNED),
.PIPERX5CHARISK(PIPERX5CHARISK),
.PIPERX5DATA(PIPERX5DATA),
.PIPERX5ELECIDLE(PIPERX5ELECIDLE),
.PIPERX5PHYSTATUS(PIPERX5PHYSTATUS),
.PIPERX5POLARITY(PIPERX5POLARITY),
.PIPERX5STATUS(PIPERX5STATUS),
.PIPERX5VALID(PIPERX5VALID),
.PIPERX6CHANISALIGNED(PIPERX6CHANISALIGNED),
.PIPERX6CHARISK(PIPERX6CHARISK),
.PIPERX6DATA(PIPERX6DATA),
.PIPERX6ELECIDLE(PIPERX6ELECIDLE),
.PIPERX6PHYSTATUS(PIPERX6PHYSTATUS),
.PIPERX6POLARITY(PIPERX6POLARITY),
.PIPERX6STATUS(PIPERX6STATUS),
.PIPERX6VALID(PIPERX6VALID),
.PIPERX7CHANISALIGNED(PIPERX7CHANISALIGNED),
.PIPERX7CHARISK(PIPERX7CHARISK),
.PIPERX7DATA(PIPERX7DATA),
.PIPERX7ELECIDLE(PIPERX7ELECIDLE),
.PIPERX7PHYSTATUS(PIPERX7PHYSTATUS),
.PIPERX7POLARITY(PIPERX7POLARITY),
.PIPERX7STATUS(PIPERX7STATUS),
.PIPERX7VALID(PIPERX7VALID),
.PIPETX0CHARISK(PIPETX0CHARISK),
.PIPETX0COMPLIANCE(PIPETX0COMPLIANCE),
.PIPETX0DATA(PIPETX0DATA),
.PIPETX0ELECIDLE(PIPETX0ELECIDLE),
.PIPETX0POWERDOWN(PIPETX0POWERDOWN),
.PIPETX1CHARISK(PIPETX1CHARISK),
.PIPETX1COMPLIANCE(PIPETX1COMPLIANCE),
.PIPETX1DATA(PIPETX1DATA),
.PIPETX1ELECIDLE(PIPETX1ELECIDLE),
.PIPETX1POWERDOWN(PIPETX1POWERDOWN),
.PIPETX2CHARISK(PIPETX2CHARISK),
.PIPETX2COMPLIANCE(PIPETX2COMPLIANCE),
.PIPETX2DATA(PIPETX2DATA),
.PIPETX2ELECIDLE(PIPETX2ELECIDLE),
.PIPETX2POWERDOWN(PIPETX2POWERDOWN),
.PIPETX3CHARISK(PIPETX3CHARISK),
.PIPETX3COMPLIANCE(PIPETX3COMPLIANCE),
.PIPETX3DATA(PIPETX3DATA),
.PIPETX3ELECIDLE(PIPETX3ELECIDLE),
.PIPETX3POWERDOWN(PIPETX3POWERDOWN),
.PIPETX4CHARISK(PIPETX4CHARISK),
.PIPETX4COMPLIANCE(PIPETX4COMPLIANCE),
.PIPETX4DATA(PIPETX4DATA),
.PIPETX4ELECIDLE(PIPETX4ELECIDLE),
.PIPETX4POWERDOWN(PIPETX4POWERDOWN),
.PIPETX5CHARISK(PIPETX5CHARISK),
.PIPETX5COMPLIANCE(PIPETX5COMPLIANCE),
.PIPETX5DATA(PIPETX5DATA),
.PIPETX5ELECIDLE(PIPETX5ELECIDLE),
.PIPETX5POWERDOWN(PIPETX5POWERDOWN),
.PIPETX6CHARISK(PIPETX6CHARISK),
.PIPETX6COMPLIANCE(PIPETX6COMPLIANCE),
.PIPETX6DATA(PIPETX6DATA),
.PIPETX6ELECIDLE(PIPETX6ELECIDLE),
.PIPETX6POWERDOWN(PIPETX6POWERDOWN),
.PIPETX7CHARISK(PIPETX7CHARISK),
.PIPETX7COMPLIANCE(PIPETX7COMPLIANCE),
.PIPETX7DATA(PIPETX7DATA),
.PIPETX7ELECIDLE(PIPETX7ELECIDLE),
.PIPETX7POWERDOWN(PIPETX7POWERDOWN),
.PIPETXDEEMPH(PIPETXDEEMPH),
.PIPETXMARGIN(PIPETXMARGIN),
.PIPETXRATE(PIPETXRATE),
.PIPETXRCVRDET(PIPETXRCVRDET),
.PIPETXRESET(PIPETXRESET),
.PL2DIRECTEDLSTATE(PL2DIRECTEDLSTATE),
.PL2L0REQ(PL2L0REQ),
.PL2LINKUP(PL2LINKUP),
.PL2RECEIVERERR(PL2RECEIVERERR),
.PL2RECOVERY(PL2RECOVERY),
.PL2RXELECIDLE(PL2RXELECIDLE),
.PL2RXPMSTATE(PL2RXPMSTATE),
.PL2SUSPENDOK(PL2SUSPENDOK),
.PLDBGMODE(PLDBGMODE),
.PLDBGVEC(PLDBGVEC),
.PLDIRECTEDCHANGEDONE(PLDIRECTEDCHANGEDONE),
.PLDIRECTEDLINKAUTON(PLDIRECTEDLINKAUTON),
.PLDIRECTEDLINKCHANGE(PLDIRECTEDLINKCHANGE),
.PLDIRECTEDLINKSPEED(PLDIRECTEDLINKSPEED),
.PLDIRECTEDLINKWIDTH(PLDIRECTEDLINKWIDTH),
.PLDIRECTEDLTSSMNEW(PLDIRECTEDLTSSMNEW),
.PLDIRECTEDLTSSMNEWVLD(PLDIRECTEDLTSSMNEWVLD),
.PLDIRECTEDLTSSMSTALL(PLDIRECTEDLTSSMSTALL),
.PLDOWNSTREAMDEEMPHSOURCE(PLDOWNSTREAMDEEMPHSOURCE),
.PLINITIALLINKWIDTH(PLINITIALLINKWIDTH),
.PLLANEREVERSALMODE(PLLANEREVERSALMODE),
.PLLINKGEN2CAP(PLLINKGEN2CAP),
.PLLINKPARTNERGEN2SUPPORTED(PLLINKPARTNERGEN2SUPPORTED),
.PLLINKUPCFGCAP(PLLINKUPCFGCAP),
.PLLTSSMSTATE(PLLTSSMSTATE),
.PLPHYLNKUPN(PLPHYLNKUPN),
.PLRECEIVEDHOTRST(PLRECEIVEDHOTRST),
.PLRSTN(PLRSTN),
.PLRXPMSTATE(PLRXPMSTATE),
.PLSELLNKRATE(PLSELLNKRATE),
.PLSELLNKWIDTH(PLSELLNKWIDTH),
.PLTRANSMITHOTRST(PLTRANSMITHOTRST),
.PLTXPMSTATE(PLTXPMSTATE),
.PLUPSTREAMPREFERDEEMPH(PLUPSTREAMPREFERDEEMPH),
.RECEIVEDFUNCLVLRSTN(RECEIVEDFUNCLVLRSTN),
.SYSRSTN(SYSRSTN),
.TL2ASPMSUSPENDCREDITCHECK(TL2ASPMSUSPENDCREDITCHECK),
.TL2ASPMSUSPENDCREDITCHECKOK(TL2ASPMSUSPENDCREDITCHECKOK),
.TL2ASPMSUSPENDREQ(TL2ASPMSUSPENDREQ),
.TL2ERRFCPE(TL2ERRFCPE),
.TL2ERRHDR(TL2ERRHDR),
.TL2ERRMALFORMED(TL2ERRMALFORMED),
.TL2ERRRXOVERFLOW(TL2ERRRXOVERFLOW),
.TL2PPMSUSPENDOK(TL2PPMSUSPENDOK),
.TL2PPMSUSPENDREQ(TL2PPMSUSPENDREQ),
.TLRSTN(TLRSTN),
.TRNFCCPLD(TRNFCCPLD),
.TRNFCCPLH(TRNFCCPLH),
.TRNFCNPD(TRNFCNPD),
.TRNFCNPH(TRNFCNPH),
.TRNFCPD(TRNFCPD),
.TRNFCPH(TRNFCPH),
.TRNFCSEL(TRNFCSEL),
.TRNLNKUP(TRNLNKUP),
.TRNRBARHIT(TRNRBARHIT),
.TRNRD(TRNRD),
.TRNRDLLPDATA(TRNRDLLPDATA),
.TRNRDLLPSRCRDY(TRNRDLLPSRCRDY),
.TRNRDSTRDY(TRNRDSTRDY),
.TRNRECRCERR(TRNRECRCERR),
.TRNREOF(TRNREOF),
.TRNRERRFWD(TRNRERRFWD),
.TRNRFCPRET(TRNRFCPRET),
.TRNRNPOK(TRNRNPOK),
.TRNRNPREQ(TRNRNPREQ),
.TRNRREM(TRNRREM),
.TRNRSOF(TRNRSOF),
.TRNRSRCDSC(TRNRSRCDSC),
.TRNRSRCRDY(TRNRSRCRDY),
.TRNTBUFAV(TRNTBUFAV),
.TRNTCFGGNT(TRNTCFGGNT),
.TRNTCFGREQ(TRNTCFGREQ),
.TRNTD(TRNTD),
.TRNTDLLPDATA(TRNTDLLPDATA),
.TRNTDLLPDSTRDY(TRNTDLLPDSTRDY),
.TRNTDLLPSRCRDY(TRNTDLLPSRCRDY),
.TRNTDSTRDY(TRNTDSTRDY),
.TRNTECRCGEN(TRNTECRCGEN),
.TRNTEOF(TRNTEOF),
.TRNTERRDROP(TRNTERRDROP),
.TRNTERRFWD(TRNTERRFWD),
.TRNTREM(TRNTREM),
.TRNTSOF(TRNTSOF),
.TRNTSRCDSC(TRNTSRCDSC),
.TRNTSRCRDY(TRNTSRCRDY),
.TRNTSTR(TRNTSTR),
.USERCLK(USERCLK),
.USERCLK2(USERCLK2),
.USERRSTN(USERRSTN)
);
endmodule |
module decoder ( cx, d );
input [18:0] cx;
output [5:0] d;
wire n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434,
n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445,
n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456,
n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467,
n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, n478,
n479, n480, n481, n482, n483, n484, n485, n486, n487, n488, n489,
n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, n500,
n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511,
n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522,
n523, n524, n525, n526, n527, n528, n529, n530;
MUX2X1 U122 ( .B(n413), .A(n414), .S(cx[5]), .Y(d[5]) );
NOR2X1 U123 ( .A(n415), .B(n416), .Y(n414) );
MUX2X1 U124 ( .B(n417), .A(n418), .S(cx[4]), .Y(d[4]) );
NOR2X1 U125 ( .A(n419), .B(n416), .Y(n418) );
NAND2X1 U126 ( .A(n420), .B(n421), .Y(n416) );
MUX2X1 U127 ( .B(n422), .A(n421), .S(n423), .Y(d[3]) );
AND2X1 U128 ( .A(n420), .B(n424), .Y(n422) );
INVX1 U129 ( .A(n425), .Y(n420) );
NAND3X1 U130 ( .A(n426), .B(n427), .C(n428), .Y(n425) );
MUX2X1 U131 ( .B(n429), .A(n430), .S(cx[2]), .Y(d[2]) );
NOR2X1 U132 ( .A(n431), .B(n432), .Y(n430) );
INVX1 U133 ( .A(n433), .Y(n429) );
MUX2X1 U134 ( .B(n434), .A(n435), .S(n436), .Y(d[1]) );
NOR2X1 U135 ( .A(n433), .B(n432), .Y(n434) );
NAND2X1 U136 ( .A(n437), .B(n427), .Y(n432) );
MUX2X1 U137 ( .B(n427), .A(n438), .S(cx[0]), .Y(d[0]) );
AND2X1 U138 ( .A(n426), .B(n437), .Y(n438) );
INVX1 U139 ( .A(n439), .Y(n437) );
NAND3X1 U140 ( .A(n428), .B(n421), .C(n424), .Y(n439) );
NOR2X1 U141 ( .A(n415), .B(n419), .Y(n424) );
INVX1 U142 ( .A(n413), .Y(n419) );
NAND3X1 U143 ( .A(n440), .B(n441), .C(n442), .Y(n413) );
NOR2X1 U144 ( .A(n443), .B(n444), .Y(n442) );
NAND2X1 U145 ( .A(n445), .B(n446), .Y(n444) );
INVX1 U146 ( .A(n417), .Y(n415) );
NAND3X1 U147 ( .A(n447), .B(n448), .C(n449), .Y(n417) );
NOR2X1 U148 ( .A(n450), .B(n451), .Y(n449) );
NAND2X1 U149 ( .A(n446), .B(n452), .Y(n451) );
NAND3X1 U150 ( .A(n453), .B(n454), .C(n455), .Y(n450) );
NOR2X1 U151 ( .A(n456), .B(n457), .Y(n448) );
NOR2X1 U152 ( .A(n458), .B(n459), .Y(n447) );
NAND3X1 U153 ( .A(n460), .B(n461), .C(n462), .Y(n421) );
NOR2X1 U154 ( .A(n440), .B(n463), .Y(n462) );
INVX1 U155 ( .A(n464), .Y(n428) );
NAND3X1 U156 ( .A(n465), .B(n466), .C(n467), .Y(n464) );
NOR2X1 U157 ( .A(n468), .B(n469), .Y(n467) );
OAI21X1 U158 ( .A(n470), .B(n453), .C(n471), .Y(n469) );
OAI21X1 U159 ( .A(n452), .B(n472), .C(n473), .Y(n471) );
MUX2X1 U160 ( .B(n474), .A(n475), .S(n463), .Y(n472) );
NAND2X1 U161 ( .A(n476), .B(n453), .Y(n474) );
OAI21X1 U162 ( .A(n477), .B(n440), .C(n478), .Y(n468) );
NAND2X1 U163 ( .A(n479), .B(n480), .Y(n478) );
OAI21X1 U164 ( .A(n457), .B(n454), .C(n476), .Y(n480) );
INVX1 U165 ( .A(n481), .Y(n477) );
OAI22X1 U166 ( .A(n453), .B(n473), .C(n443), .D(n482), .Y(n481) );
MUX2X1 U167 ( .B(n483), .A(n456), .S(n484), .Y(n466) );
AND2X1 U168 ( .A(n485), .B(n486), .Y(n465) );
MUX2X1 U169 ( .B(n487), .A(n470), .S(n457), .Y(n486) );
NOR2X1 U170 ( .A(n452), .B(n456), .Y(n487) );
MUX2X1 U171 ( .B(n488), .A(n489), .S(n490), .Y(n485) );
NAND2X1 U172 ( .A(n491), .B(n492), .Y(n489) );
AOI22X1 U173 ( .A(n445), .B(n493), .C(n455), .D(n453), .Y(n492) );
AOI22X1 U174 ( .A(n482), .B(n475), .C(n440), .D(n494), .Y(n491) );
OAI21X1 U175 ( .A(n473), .B(n479), .C(n495), .Y(n488) );
INVX1 U176 ( .A(n459), .Y(n495) );
NAND3X1 U177 ( .A(n494), .B(n470), .C(n475), .Y(n459) );
NOR2X1 U178 ( .A(n431), .B(n433), .Y(n426) );
NOR2X1 U179 ( .A(n496), .B(n497), .Y(n433) );
NAND3X1 U180 ( .A(n463), .B(n440), .C(n498), .Y(n497) );
NAND3X1 U181 ( .A(n490), .B(n461), .C(n499), .Y(n496) );
NOR2X1 U182 ( .A(n473), .B(n500), .Y(n499) );
INVX1 U183 ( .A(n501), .Y(n461) );
NAND3X1 U184 ( .A(n484), .B(n483), .C(n502), .Y(n501) );
NOR2X1 U185 ( .A(n456), .B(n503), .Y(n502) );
NAND2X1 U186 ( .A(n443), .B(n445), .Y(n503) );
INVX1 U187 ( .A(n435), .Y(n431) );
NAND3X1 U188 ( .A(n490), .B(n441), .C(n504), .Y(n435) );
NOR2X1 U189 ( .A(n445), .B(n505), .Y(n504) );
NAND2X1 U190 ( .A(n443), .B(n454), .Y(n505) );
NOR2X1 U191 ( .A(n506), .B(n507), .Y(n441) );
NAND3X1 U192 ( .A(n500), .B(n473), .C(n498), .Y(n507) );
NOR3X1 U193 ( .A(n457), .B(n508), .C(n453), .Y(n498) );
NAND3X1 U194 ( .A(n456), .B(n494), .C(n509), .Y(n506) );
NOR2X1 U195 ( .A(n483), .B(n484), .Y(n509) );
INVX1 U196 ( .A(n476), .Y(n484) );
INVX1 U197 ( .A(n493), .Y(n483) );
OR2X1 U198 ( .A(n510), .B(n511), .Y(n427) );
NAND3X1 U199 ( .A(n463), .B(n460), .C(n440), .Y(n511) );
INVX1 U200 ( .A(n454), .Y(n440) );
XOR2X1 U201 ( .A(n512), .B(n513), .Y(n454) );
XOR2X1 U202 ( .A(cx[8]), .B(cx[5]), .Y(n513) );
NOR2X1 U203 ( .A(n514), .B(n515), .Y(n460) );
NAND3X1 U204 ( .A(n500), .B(n473), .C(n508), .Y(n515) );
INVX1 U205 ( .A(n470), .Y(n508) );
XOR2X1 U206 ( .A(cx[4]), .B(n516), .Y(n470) );
XOR2X1 U207 ( .A(cx[7]), .B(cx[5]), .Y(n516) );
INVX1 U208 ( .A(n455), .Y(n473) );
XNOR2X1 U209 ( .A(n517), .B(cx[13]), .Y(n455) );
INVX1 U210 ( .A(n452), .Y(n500) );
XNOR2X1 U211 ( .A(n518), .B(n519), .Y(n452) );
XNOR2X1 U212 ( .A(cx[4]), .B(cx[9]), .Y(n518) );
NAND3X1 U213 ( .A(n453), .B(n457), .C(n490), .Y(n514) );
INVX1 U214 ( .A(n446), .Y(n490) );
XNOR2X1 U215 ( .A(n520), .B(n521), .Y(n446) );
XOR2X1 U216 ( .A(cx[17]), .B(n522), .Y(n521) );
XNOR2X1 U217 ( .A(cx[2]), .B(cx[5]), .Y(n520) );
XNOR2X1 U218 ( .A(n523), .B(n524), .Y(n457) );
XOR2X1 U219 ( .A(cx[5]), .B(cx[10]), .Y(n524) );
XNOR2X1 U220 ( .A(n525), .B(cx[15]), .Y(n453) );
INVX1 U221 ( .A(n494), .Y(n463) );
XOR2X1 U222 ( .A(n519), .B(cx[14]), .Y(n494) );
XNOR2X1 U223 ( .A(cx[0]), .B(n423), .Y(n519) );
NAND3X1 U224 ( .A(n475), .B(n456), .C(n526), .Y(n510) );
INVX1 U225 ( .A(n458), .Y(n526) );
NAND3X1 U226 ( .A(n476), .B(n493), .C(n479), .Y(n458) );
INVX1 U227 ( .A(n445), .Y(n479) );
XNOR2X1 U228 ( .A(n523), .B(cx[16]), .Y(n445) );
XNOR2X1 U229 ( .A(cx[3]), .B(n522), .Y(n523) );
XNOR2X1 U230 ( .A(n525), .B(cx[11]), .Y(n493) );
XNOR2X1 U231 ( .A(cx[2]), .B(cx[4]), .Y(n525) );
XNOR2X1 U232 ( .A(n527), .B(n512), .Y(n476) );
XNOR2X1 U233 ( .A(cx[2]), .B(n423), .Y(n512) );
INVX1 U234 ( .A(cx[3]), .Y(n423) );
XNOR2X1 U235 ( .A(cx[1]), .B(cx[18]), .Y(n527) );
INVX1 U236 ( .A(n482), .Y(n456) );
XOR2X1 U237 ( .A(n528), .B(n529), .Y(n482) );
XNOR2X1 U238 ( .A(cx[5]), .B(n436), .Y(n529) );
XNOR2X1 U239 ( .A(cx[0]), .B(cx[12]), .Y(n528) );
INVX1 U240 ( .A(n443), .Y(n475) );
XNOR2X1 U241 ( .A(n517), .B(cx[6]), .Y(n443) );
XOR2X1 U242 ( .A(n530), .B(n522), .Y(n517) );
XNOR2X1 U243 ( .A(n436), .B(cx[4]), .Y(n522) );
INVX1 U244 ( .A(cx[1]), .Y(n436) );
XNOR2X1 U245 ( .A(cx[0]), .B(cx[5]), .Y(n530) );
endmodule |
module CapSense_Sys #(
parameter DIRECT=1, // Direct status, else: toggle
parameter FREQUENCY=24, // Clock in MHz
parameter N=4 // How many buttons
) (
input clk_i, // System clock
input rst_i, // System reset
input [N-1:0] capsense_i, // Buttons inputs
output oe, // Buttons OE
output [N-1:0] buttons_o, // Last sample result
output [N-1:0] debug_o // Used to measure the button timing
);*/
//localparam N=4;
localparam integer MOD_SAMP=FREQUENCY/1.5;
localparam integer MOD_BITS=$clog2(MOD_SAMP);
// FSM states
localparam IDLE=0, SAMPLING=1, DO_SAMPLE=2;
// Some constants
localparam ALL_1={N{1'b1}};
reg [1:0] state=IDLE;
reg [N-1:0] btns_r;
// CapSense sampling rate
wire clkSamp;
reg [MOD_BITS-1:0] cntSamp=0;
// CapSese polling rate
wire clkPoll;
reg [16:0] cntPoll=0;
// Buttons
wire [N-1:0] cur_btns;
reg [N-1:0] prev_btn_r=0;
reg [N-1:0] cur_btn_r=0;
// 1.5 MHz capacitors sample
always @(posedge clk_i)
if (cntSamp==MOD_SAMP-1)
cntSamp=0;
else
cntSamp=cntSamp+1;
assign clkSamp=!cntSamp ? 1 : 0;
// aprox. 87 ms
always @(posedge clk_i)
if (clkSamp)
cntPoll=cntPoll+1;
assign clkPoll=!cntPoll ? 1 : 0;
// Keep the capacitors discharged while we are idle
assign oe=state==IDLE ? 1 : 0;
always @(posedge clk_i)
begin : do_fsm
if (1'b0) // rst_i
begin
state=IDLE;
btns_r=0;
end
else
begin
case (state)
IDLE:
if (clkPoll)
state=SAMPLING;
SAMPLING:
// Sample the capacitors at the clkSamp rate
// If any of the capacitors is charged stop waiting
if (clkSamp && capsense_i)
state=DO_SAMPLE;
default: // DO_SAMPLE
// We wait 1 more cycle to mask small differences between
// buttons. Pressed buttons have big differeneces.
if (clkSamp) // For debug: && capsense_i==ALL_1
begin
// The "pressed" buttons are the ones that stay charging
btns_r=~capsense_i;
state=IDLE;
end
endcase
end
end
assign cur_btns=btns_r;
integer i;
always @(posedge clk_i)
begin
for (i=0; i<4; i=i+1)
if (!prev_btn_r[i] && cur_btns[i]) // pressed?
cur_btn_r[i]=~cur_btn_r[i]; // toggle
prev_btn_r=cur_btns;
end
assign buttons_o=DIRECT ? cur_btns : cur_btn_r;
//endmodule |
module sky130_fd_sc_lp__bufbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufbuf base (
.X(X),
.A(A)
);
endmodule |
module cyclone2_pmem (
address,
byteena,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clken;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena),
.address_a (address),
.data_a (data),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule |
module tx_multiplexer_64
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA"
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY);
localparam C_DATA_DELAY = 6'd6; // Delays read/write params to accommodate tx_port_buffer delay and tx_engine_formatter delay.
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rMainState=`S_TXENGUPR64_MAIN_IDLE, _rMainState=`S_TXENGUPR64_MAIN_IDLE;
reg rCountIsWr=0, _rCountIsWr=0;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountValid=0,_rCountValid=0;
reg rCountStart=0, _rCountStart=0;
reg rCountOdd32=0, _rCountOdd32=0;
reg [9:0] rCountLen=0, _rCountLen=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr;
wire [9:0] wRdLen;
wire [1:0] wRdSgChnl;
wire [63:0] wWrAddr;
wire [9:0] wWrLen;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR64_CAP_RD_WR, _rCapState=`S_TXENGUPR64_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [((C_DATA_DELAY+1)*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST_IN ? `S_TXENGUPR64_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = (rCapAddr[61:30] != 0);
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR64_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = (wRdAck<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR64_CAP_CAP : `S_TXENGUPR64_CAP_WR_RD);
end
`S_TXENGUPR64_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR64_CAP_CAP : `S_TXENGUPR64_CAP_RD_WR);
end
`S_TXENGUPR64_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG;
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR64_CAP_REL;
end
`S_TXENGUPR64_CAP_REL : begin
// Push into the formatting pipeline when ready
if (TXR_META_READY & rMainState[0]) // S_TXENGUPR64_MAIN_IDLE
_rCapState = (`S_TXENGUPR64_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR64_CAP_RD_WR
end
default : begin
_rCapState = `S_TXENGUPR64_CAP_RD_WR;
end
endcase
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST_IN ? `S_TXENGUPR64_MAIN_IDLE : _rMainState);
rCountIsWr <= #1 _rCountIsWr;
rCountLen <= #1 _rCountLen;
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountStart <= #1 _rCountStart;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCountOdd32 <= #1 _rCountOdd32;
rWrDataRen <= #1 _rWrDataRen;
rCountValid <= #1 RST_IN ? 0 : _rCountValid;
end
always @ (*) begin
_rMainState = rMainState;
_rCountIsWr = rCountIsWr;
_rCount = rCount;
_rCountLen = rCountLen;
_rCountDone = rCountDone;
_rCountStart = rCountStart;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCountOdd32 = rCountOdd32;
_rWrDataRen = rWrDataRen;
_rCountStart = 0;
_rCountValid = rCountValid;
case (rMainState)
`S_TXENGUPR64_MAIN_IDLE : begin
_rCountIsWr = rCapIsWr;
_rCountLen = rCapLen;
_rCount = rCapLen;
_rCountDone = (rCapLen <= 2'd2);
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCountOdd32 = (rCapLen[0] & ((rCapAddr[61:30] == 0)));
_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR64_CAP_REL
_rCountStart = (TXR_META_READY & rCapState[3]);
_rCountValid = TXR_META_READY & rCapState[3];
if (TXR_META_READY & rCapState[3]) // S_TXENGUPR64_CAP_REL
_rMainState = (`S_TXENGUPR64_MAIN_RD<<(rCapIsWr)); // Change to S_TXENGUPR64_MAIN_WR;
end
`S_TXENGUPR64_MAIN_RD : begin
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
`S_TXENGUPR64_MAIN_WR : begin
_rCount = rCount - 2'd2;
_rCountDone = (rCount <= 3'd4);
if (rCountDone) begin
_rWrDataRen = 0;
_rCountValid = 0;
_rMainState = (rCountOdd32 ? `S_TXENGUPR64_MAIN_IDLE : `S_TXENGUPR64_MAIN_WAIT);
end
end
`S_TXENGUPR64_MAIN_WAIT : begin // Signals request FIFO ren
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
default : begin
_rMainState = `S_TXENGUPR64_MAIN_IDLE;
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rChnl[(C_DATA_DELAY-2)*4 +:4];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
rValid <= #1 _rValid;
rDone <= #1 _rDone;
rStart <= #1 _rStart;
end
always @ (*) begin
_rWnR = {rWnR[((C_DATA_DELAY-1)*1)-1:0], rCapIsWr};
_rAddr = {rAddr[((C_DATA_DELAY-1)*62)-1:0], rCapAddr};
_rLen = {rLen[((C_DATA_DELAY-1)*10)-1:0], rCountLen};
_rChnl = {rChnl[((C_DATA_DELAY-1)*4)-1:0], rCountChnl};
_rTag = {rTag[((C_DATA_DELAY-1)*8)-1:0], (8'd0 | rCountTag)};
_rValid = {rValid[((C_DATA_DELAY-1)*1)-1:0], rCountValid & rCountIsWr}; // S_TXENGUPR64_MAIN_RD | S_TXENGUPR64_MAIN_WR
_rDone = {rDone[((C_DATA_DELAY-1)*1)-1:0], rCountDone};
_rStart = {rStart[((C_DATA_DELAY-1)*1)-1:0], rCountStart};
end
assign TXR_DATA = rWrData;
assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_OFFSET = 0;
assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
assign TXR_META_VALID = rCountStart;
assign TXR_META_TYPE = rCapIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
assign TXR_META_ADDR = {rCapAddr,2'b00};
assign TXR_META_LENGTH = rCapLen;
assign TXR_META_LDWBE = 4'b1111;
assign TXR_META_FDWBE = 4'b1111;
assign TXR_META_TAG = rCountTag;
assign TXR_META_EP = 1'b0;
assign TXR_META_ATTR = 3'b110;
assign TXR_META_TC = 0;
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[15:0],B[31:0],P[47:0]" */;
input CLK;
input [15:0]A;
input [31:0]B;
output [47:0]P;
endmodule |
module sky130_fd_sc_lp__a2bb2o_4 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__a2bb2o_4 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule |
module sky130_fd_sc_hs__clkdlyinv5sd2 (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule |
module uart_transmitter
(
input wire clk,
input wire rst,
input wire [7:0] data,
output reg nextch,
output reg txd
);
parameter CLK = 50_000_000;
parameter BAUD = 9600;
localparam RATE = CLK/BAUD;
localparam INIT = 0;
localparam TXD = 1;
reg state, next;
reg [31:0] cnt;
reg [4:0] bitcnt;
reg [9:0] rshift;
reg shift, load, clear, getch, gotch;
always @ (posedge clk or negedge rst) begin
if (!rst) begin
state <= INIT;
cnt <= 0;
bitcnt <= 0;
gotch <= 0;
end
else begin
if (nextch) begin
nextch <= 0;
gotch <= 1;
end
else if (getch && !gotch)
nextch <= 1;
cnt <= cnt + 1;
if (cnt >= RATE) begin
state <= next;
cnt <= 0;
if (load)
rshift <= {1'b1, data[7:0], 1'b0};
if (clear) begin
bitcnt <= 0;
gotch <= 0;
end
if (shift) begin
rshift <= rshift >> 1;
bitcnt <= bitcnt + 1;
end
end
end
end
always @ (state or bitcnt or rshift) begin
load <= 0;
shift <= 0;
clear <= 0;
getch <= 0;
txd <= 1;
case (state)
INIT: begin
next <= TXD;
load <= 1;
shift <= 0;
clear <= 0;
end
TXD: begin
if (bitcnt >= 9) begin
next <= INIT;
clear <= 1;
getch <= 1;
end
else begin
next <= TXD;
shift <= 1;
txd <= rshift[0];
end
end
endcase
end
endmodule |
module ps2_rx
(
input wire clk, reset,
input wire ps2d, ps2c, rx_en,
output reg rx_done_tick,
output wire [7:0] dout
);
// symbolic state declaration
localparam [1:0]
idle = 2'b00,
dps = 2'b01,
load = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [7:0] filter_reg;
wire [7:0] filter_next;
reg f_ps2c_reg;
wire f_ps2c_next;
reg [3:0] n_reg, n_next;
reg [10:0] b_reg, b_next;
wire fall_edge;
// body
//=================================================
// filter and falling-edge tick generation for ps2c
//=================================================
always @(posedge clk, posedge reset)
if (reset)
begin
filter_reg <= 0;
f_ps2c_reg <= 0;
end
else
begin
filter_reg <= filter_next;
f_ps2c_reg <= f_ps2c_next;
end
assign filter_next = {ps2c, filter_reg[7:1]};
assign f_ps2c_next = (filter_reg==8'b11111111) ? 1'b1 :
(filter_reg==8'b00000000) ? 1'b0 :
f_ps2c_reg;
assign fall_edge = f_ps2c_reg & ~f_ps2c_next;
//=================================================
// FSMD
//=================================================
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <= state_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next-state logic
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (fall_edge & rx_en)
begin
// shift in start bit
b_next = {ps2d, b_reg[10:1]};
n_next = 4'b1001;
state_next = dps;
end
dps: // 8 data + 1 parity + 1 stop
if (fall_edge)
begin
b_next = {ps2d, b_reg[10:1]};
if (n_reg==0)
state_next = load;
else
n_next = n_reg - 1;
end
load: // 1 extra clock to complete the last shift
begin
state_next = idle;
rx_done_tick = 1'b1;
end
endcase
end
// output
assign dout = b_reg[8:1]; // data bits
endmodule |
module robohand(reset, advance, ball_y, paddle_y);
// paddle Y location (0-480)
parameter PADDLESIZE = 10'd0;
parameter SCREENHEIGHT = 10'd0;
input reset;
input advance;
input [9:0] ball_y;
output reg[9:0] paddle_y;
// paddle move direction 0 = +, 1 = -
reg paddleDir;
reg [9:0] ptop;
reg [9:0] pbot;
reg [2:0] increment;
always @(negedge advance or posedge reset) begin
if (reset) begin
paddle_y <= SCREENHEIGHT/2;
end
else begin
if (ball_y < ptop || ball_y > pbot)
paddle_y <= paddlelimiter(paddleDir == 1'b0 ? paddle_y + 1'b1 : paddle_y - 1'b1);
end
end
always @(posedge advance) begin
ptop <= paddle_y - PADDLESIZE/2;
pbot <= paddle_y + PADDLESIZE/2;
paddleDir <= ball_y < paddle_y;
end
function [9:0] paddlelimiter;
input [9:0] py;
begin
if (py < PADDLESIZE/2)
paddlelimiter = PADDLESIZE/2;
else
if (py > SCREENHEIGHT-PADDLESIZE/2)
paddlelimiter = SCREENHEIGHT-PADDLESIZE/2;
else
paddlelimiter = py;
end
endfunction
endmodule |
module LCD_TEST ( // Host Side
iCLK,iRST_N,
// LCD Side
LCD_DATA,LCD_RW,LCD_EN,LCD_RS );
// Host Side
input iCLK,iRST_N;
// LCD Side
output [7:0] LCD_DATA;
output LCD_RW,LCD_EN,LCD_RS;
// Internal Wires/Registers
reg [5:0] LUT_INDEX;
reg [8:0] LUT_DATA;
reg [5:0] mLCD_ST;
reg [17:0] mDLY;
reg mLCD_Start;
reg [7:0] mLCD_DATA;
reg mLCD_RS;
wire mLCD_Done;
parameter LCD_INTIAL = 0;
parameter LCD_LINE1 = 5;
parameter LCD_CH_LINE = LCD_LINE1+16;
parameter LCD_LINE2 = LCD_LINE1+16+1;
parameter LUT_SIZE = LCD_LINE1+32+1;
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mLCD_ST <= 0;
mDLY <= 0;
mLCD_Start <= 0;
mLCD_DATA <= 0;
mLCD_RS <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mLCD_ST)
0: begin
mLCD_DATA <= LUT_DATA[7:0];
mLCD_RS <= LUT_DATA[8];
mLCD_Start <= 1;
mLCD_ST <= 1;
end
1: begin
if(mLCD_Done)
begin
mLCD_Start <= 0;
mLCD_ST <= 2;
end
end
2: begin
if(mDLY<18'h3FFFE)
mDLY <= mDLY+1;
else
begin
mDLY <= 0;
mLCD_ST <= 3;
end
end
3: begin
LUT_INDEX <= LUT_INDEX+1;
mLCD_ST <= 0;
end
endcase
end
end
end
always
begin
case(LUT_INDEX)
// Initial
LCD_INTIAL+0: LUT_DATA <= 9'h038;
LCD_INTIAL+1: LUT_DATA <= 9'h00C;
LCD_INTIAL+2: LUT_DATA <= 9'h001;
LCD_INTIAL+3: LUT_DATA <= 9'h006;
LCD_INTIAL+4: LUT_DATA <= 9'h080;
// Line 1
LCD_LINE1+0: LUT_DATA <= 9'h120; // Welcome to the
LCD_LINE1+1: LUT_DATA <= 9'h157;
LCD_LINE1+2: LUT_DATA <= 9'h165;
LCD_LINE1+3: LUT_DATA <= 9'h16C;
LCD_LINE1+4: LUT_DATA <= 9'h163;
LCD_LINE1+5: LUT_DATA <= 9'h16F;
LCD_LINE1+6: LUT_DATA <= 9'h16D;
LCD_LINE1+7: LUT_DATA <= 9'h165;
LCD_LINE1+8: LUT_DATA <= 9'h120;
LCD_LINE1+9: LUT_DATA <= 9'h174;
LCD_LINE1+10: LUT_DATA <= 9'h16F;
LCD_LINE1+11: LUT_DATA <= 9'h120;
LCD_LINE1+12: LUT_DATA <= 9'h174;
LCD_LINE1+13: LUT_DATA <= 9'h168;
LCD_LINE1+14: LUT_DATA <= 9'h165;
LCD_LINE1+15: LUT_DATA <= 9'h120;
// Change Line
LCD_CH_LINE: LUT_DATA <= 9'h0C0;
// Line 2
LCD_LINE2+0: LUT_DATA <= 9'h120; // Altera DE2-70
LCD_LINE2+1: LUT_DATA <= 9'h141;
LCD_LINE2+2: LUT_DATA <= 9'h16C;
LCD_LINE2+3: LUT_DATA <= 9'h174;
LCD_LINE2+4: LUT_DATA <= 9'h165;
LCD_LINE2+5: LUT_DATA <= 9'h172;
LCD_LINE2+6: LUT_DATA <= 9'h161;
LCD_LINE2+7: LUT_DATA <= 9'h120;
LCD_LINE2+8: LUT_DATA <= 9'h144;
LCD_LINE2+9: LUT_DATA <= 9'h145;
LCD_LINE2+10: LUT_DATA <= 9'h132;
LCD_LINE2+11: LUT_DATA <= 9'h1B0;
LCD_LINE2+12: LUT_DATA <= 9'h137;
LCD_LINE2+13: LUT_DATA <= 9'h130;
LCD_LINE2+14: LUT_DATA <= 9'h120;
LCD_LINE2+15: LUT_DATA <= 9'h120;
default: LUT_DATA <= 9'h120;
endcase
end
LCD_Controller u0 ( // Host Side
.iDATA(mLCD_DATA),
.iRS(mLCD_RS),
.iStart(mLCD_Start),
.oDone(mLCD_Done),
.iCLK(iCLK),
.iRST_N(iRST_N),
// LCD Interface
.LCD_DATA(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_RS(LCD_RS) );
endmodule |
module sky130_fd_sc_ls__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module ad_iqcor (
// data interface
clk,
valid,
data_i,
data_q,
valid_out,
data_out,
// control interface
iqcor_enable,
iqcor_coeff_1,
iqcor_coeff_2);
// select i/q if disabled
parameter IQSEL = 0;
// data interface
input clk;
input valid;
input [15:0] data_i;
input [15:0] data_q;
output valid_out;
output [15:0] data_out;
// control interface
input iqcor_enable;
input [15:0] iqcor_coeff_1;
input [15:0] iqcor_coeff_2;
// internal registers
reg p1_valid = 'd0;
reg [15:0] p1_data_i = 'd0;
reg [15:0] p1_data_q = 'd0;
reg [33:0] p1_data_p = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// internal signals
wire [33:0] p1_data_p_i_s;
wire p1_valid_s;
wire [15:0] p1_data_i_s;
wire [33:0] p1_data_p_q_s;
wire [15:0] p1_data_q_s;
// scaling functions - i
ad_mul #(.DELAY_DATA_WIDTH(17)) i_mul_i (
.clk (clk),
.data_a ({data_i[15], data_i}),
.data_b ({iqcor_coeff_1[15], iqcor_coeff_1}),
.data_p (p1_data_p_i_s),
.ddata_in ({valid, data_i}),
.ddata_out ({p1_valid_s, p1_data_i_s}));
// scaling functions - q
ad_mul #(.DELAY_DATA_WIDTH(16)) i_mul_q (
.clk (clk),
.data_a ({data_q[15], data_q}),
.data_b ({iqcor_coeff_2[15], iqcor_coeff_2}),
.data_p (p1_data_p_q_s),
.ddata_in (data_q),
.ddata_out (p1_data_q_s));
// sum
always @(posedge clk) begin
p1_valid <= p1_valid_s;
p1_data_i <= p1_data_i_s;
p1_data_q <= p1_data_q_s;
p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
end
// output registers
always @(posedge clk) begin
valid_out <= p1_valid;
if (iqcor_enable == 1'b1) begin
data_out <= p1_data_p[29:14];
end else if (IQSEL == 1) begin
data_out <= p1_data_q;
end else begin
data_out <= p1_data_i;
end
end
endmodule |
module crc_ccitt
#(parameter INIT = 16'hffff)
(input clk, input rst, input [7:0] d, input dv, output [15:0] crc);
wire [15:0] next_crc;
wire [15:0] crc_d = (rst ? INIT : next_crc);
r #(16) crc_r(.c(clk), .rst(1'b0), .en(dv | rst), .d(crc_d), .q(crc));
assign next_crc[0] = crc[8] ^ crc[12] ^ d[0] ^ d[4];
assign next_crc[1] = crc[9] ^ crc[13] ^ d[1] ^ d[5];
assign next_crc[2] = crc[10] ^ crc[14] ^ d[2] ^ d[6];
assign next_crc[3] = crc[11] ^ crc[15] ^ d[3] ^ d[7];
assign next_crc[4] = crc[12] ^ d[4];
assign next_crc[5] = crc[8] ^ crc[12] ^ crc[13] ^ d[0] ^ d[4] ^ d[5];
assign next_crc[6] = crc[9] ^ crc[13] ^ crc[14] ^ d[1] ^ d[5] ^ d[6];
assign next_crc[7] = crc[10] ^ crc[14] ^ crc[15] ^ d[2] ^ d[6] ^ d[7];
assign next_crc[8] = crc[0] ^ crc[11] ^ crc[15] ^ d[3] ^ d[7];
assign next_crc[9] = crc[1] ^ crc[12] ^ d[4];
assign next_crc[10] = crc[2] ^ crc[13] ^ d[5];
assign next_crc[11] = crc[3] ^ crc[14] ^ d[6];
assign next_crc[12] = crc[4] ^ crc[8] ^ crc[12] ^ crc[15] ^ d[0] ^ d[4] ^ d[7];
assign next_crc[13] = crc[5] ^ crc[9] ^ crc[13] ^ d[1] ^ d[5];
assign next_crc[14] = crc[6] ^ crc[10] ^ crc[14] ^ d[2] ^ d[6];
assign next_crc[15] = crc[7] ^ crc[11] ^ crc[15] ^ d[3] ^ d[7];
endmodule |
module hpdmc_iddr16 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT_Q0 = 1'b0,
parameter INIT_Q1 = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [15:0] Q0,
output [15:0] Q1,
input C0,
input C1,
input CE,
input [15:0] D,
input R,
input S
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr0 (
.Q0(Q0[0]),
.Q1(Q1[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[0]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr1 (
.Q0(Q0[1]),
.Q1(Q1[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[1]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr2 (
.Q0(Q0[2]),
.Q1(Q1[2]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[2]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr3 (
.Q0(Q0[3]),
.Q1(Q1[3]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[3]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr4 (
.Q0(Q0[4]),
.Q1(Q1[4]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[4]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr5 (
.Q0(Q0[5]),
.Q1(Q1[5]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[5]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr6 (
.Q0(Q0[6]),
.Q1(Q1[6]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[6]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr7 (
.Q0(Q0[7]),
.Q1(Q1[7]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[7]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr8 (
.Q0(Q0[8]),
.Q1(Q1[8]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[8]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr9 (
.Q0(Q0[9]),
.Q1(Q1[9]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[9]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr10 (
.Q0(Q0[10]),
.Q1(Q1[10]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[10]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr11 (
.Q0(Q0[11]),
.Q1(Q1[11]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[11]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr12 (
.Q0(Q0[12]),
.Q1(Q1[12]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[12]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr13 (
.Q0(Q0[13]),
.Q1(Q1[13]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[13]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr14 (
.Q0(Q0[14]),
.Q1(Q1[14]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[14]),
.R(R),
.S(S)
);
IDDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT_Q0(INIT_Q0),
.INIT_Q1(INIT_Q1),
.SRTYPE(SRTYPE)
) iddr15 (
.Q0(Q0[15]),
.Q1(Q1[15]),
.C0(C0),
.C1(C1),
.CE(CE),
.D(D[15]),
.R(R),
.S(S)
);
endmodule |
module sky130_fd_sc_hs__a41o_1 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__a41o_1 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a41o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule |
module sky130_fd_sc_ls__clkdlyinv5sd1 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module sky130_fd_sc_hs__a221oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module top
(
// Clocking & Reset
input clk_i,
input rst_i,
// Fault Output
output fault_o,
// Break Output
output break_o,
// Interrupt Input
input intr_i
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_KHZ = 8192;
parameter BOOT_VECTOR = 32'h10000000;
parameter ISR_VECTOR = 32'h10000000;
//-----------------------------------------------------------------
// Registers / Wires
//-----------------------------------------------------------------
wire [31:0] soc_addr;
wire [31:0] soc_data_w;
wire [31:0] soc_data_r;
wire soc_we;
wire soc_stb;
wire soc_ack;
wire soc_irq;
wire[31:0] dmem_address;
wire[31:0] dmem_data_w;
wire[31:0] dmem_data_r;
wire[3:0] dmem_sel;
wire[2:0] dmem_cti;
wire dmem_we;
wire dmem_stb;
wire dmem_cyc;
wire dmem_stall;
wire dmem_ack;
wire[31:0] imem_addr;
wire[31:0] imem_data;
wire[3:0] imem_sel;
wire imem_stb;
wire imem_cyc;
wire[2:0] imem_cti;
wire imem_stall;
wire imem_ack;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
// BlockRAM
ram
#(
.block_count(128) // 1MB
)
u_ram
(
.clka_i(clk_i),
.rsta_i(rst_i),
.stba_i(imem_stb),
.wea_i(1'b0),
.sela_i(imem_sel),
.addra_i(imem_addr[31:2]),
.dataa_i(32'b0),
.dataa_o(imem_data),
.acka_o(imem_ack),
.clkb_i(clk_i),
.rstb_i(rst_i),
.stbb_i(dmem_stb),
.web_i(dmem_we),
.selb_i(dmem_sel),
.addrb_i(dmem_address[31:2]),
.datab_i(dmem_data_w),
.datab_o(dmem_data_r),
.ackb_o(dmem_ack)
);
// CPU
cpu_if
#(
.CLK_KHZ(CLK_KHZ),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h10000000),
.ENABLE_ICACHE("ENABLED"),
.ENABLE_DCACHE("ENABLED"),
.REGISTER_FILE_TYPE("SIMULATION")
)
u_cpu
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.fault_o(fault_o),
.break_o(break_o),
.nmi_i(1'b0),
.intr_i(soc_irq),
// Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
.imem0_addr_o(imem_addr),
.imem0_data_i(imem_data),
.imem0_sel_o(imem_sel),
.imem0_cti_o(imem_cti),
.imem0_cyc_o(imem_cyc),
.imem0_stb_o(imem_stb),
.imem0_stall_i(1'b0),
.imem0_ack_i(imem_ack),
// Data Memory 0 (0x10000000 - 0x10FFFFFF)
.dmem0_addr_o(dmem_address),
.dmem0_data_o(dmem_data_w),
.dmem0_data_i(dmem_data_r),
.dmem0_sel_o(dmem_sel),
.dmem0_cti_o(dmem_cti),
.dmem0_cyc_o(dmem_cyc),
.dmem0_we_o(dmem_we),
.dmem0_stb_o(dmem_stb),
.dmem0_stall_i(1'b0),
.dmem0_ack_i(dmem_ack),
// Data Memory 1 (0x11000000 - 0x11FFFFFF)
.dmem1_addr_o(/*open*/),
.dmem1_data_o(/*open*/),
.dmem1_data_i(32'b0),
.dmem1_sel_o(/*open*/),
.dmem1_we_o(/*open*/),
.dmem1_stb_o(/*open*/),
.dmem1_cyc_o(/*open*/),
.dmem1_cti_o(/*open*/),
.dmem1_stall_i(1'b0),
.dmem1_ack_i(1'b1),
// Data Memory 2 (0x12000000 - 0x12FFFFFF)
.dmem2_addr_o(soc_addr),
.dmem2_data_o(soc_data_w),
.dmem2_data_i(soc_data_r),
.dmem2_sel_o(/*open*/),
.dmem2_we_o(soc_we),
.dmem2_stb_o(soc_stb),
.dmem2_cyc_o(/*open*/),
.dmem2_cti_o(/*open*/),
.dmem2_stall_i(1'b0),
.dmem2_ack_i(soc_ack)
);
// CPU SOC
soc
#(
.CLK_KHZ(CLK_KHZ),
.ENABLE_SYSTICK_TIMER("ENABLED"),
.ENABLE_HIGHRES_TIMER("ENABLED"),
.EXTERNAL_INTERRUPTS(1)
)
u_soc
(
// General - clocking & reset
.clk_i(clk_i),
.rst_i(rst_i),
.ext_intr_i(1'b0),
.intr_o(soc_irq),
.uart_tx_o(),
.uart_rx_i(1'b0),
// Memory Port
.io_addr_i(soc_addr),
.io_data_i(soc_data_w),
.io_data_o(soc_data_r),
.io_we_i(soc_we),
.io_stb_i(soc_stb),
.io_ack_o(soc_ack)
);
endmodule |
module crtregist
(
input hclock,
input hnreset,
input hwr,
input hncs,
input [3:0] hnben,
input [31:0] hdat_in,
input [7:2] haddr, // bit[2] used only in readback path
input ad_strst, /* synchronized reset for
* "display address updated" bit */
input vblnkst, // synchronized vertical blank status
input [11:0] lcounter_stat, // from line counter in TIMER (synch)
input dlp_wradd, // DLP write enable to display register
input [20:0] dlp_add, // display address from DLP
output reg [31:0] hdat_out,
output reg [7:0] vicount,
output reg [11:0] hicount,
output reg [13:0] hactive_o,
output reg [13:0] hblank_o,
output reg [13:0] hfporch_o,
output reg [13:0] hswidth_o,
output reg [11:0] vactive,
output reg [11:0] vblank,
output reg [11:0] vfporch,
output reg [11:0] vswidth,
output reg [3:0] dzoom,
output reg [15:4] db_pitch,
output reg [24:4] displ_start,
output reg [24:4] sec_start,
output reg poshs,
output reg posvs,
output reg compsync,
output reg crtintl,
output reg videnable,
output reg refresh_enable,
output reg ovignr,
output reg ovignr16l,
output reg [1:0] syncsenable,
output reg fdp_on, //1 - enables flat display mode
output reg addr_stat, // used as enble to synchr. with frame
output reg[9:0] pinl,
output reg ss_mode
);
parameter FRAME_COUNTorLINE_COUNT = 5'b0010_0,
DISP_STARTorDISP_PITCH = 5'b0010_1,
HACTIVEorHBLANK = 5'b0011_0,
HFPORCHorHSYNC = 5'b0011_1,
VACTIVEorVBLANK = 5'b0100_0,
VFPORCHorVSYNC = 5'b0100_1,
LCOUNTSorZOOM = 5'b0101_0,
SYNC_SELorMEM_CONFIG = 5'b0101_1 ,
SEC_STARTorRESERVED = 5'b0110_0 ;
reg [13:0] hactive, hblank, hfporch, hswidth;
reg [13:0] hactive_s, hblank_s, hfporch_s, hswidth_s;
reg [3:0] hshifter;
always @* hactive_o = {hactive_s[12:0], 1'b0};
always @* hblank_o = {hblank_s[12:0], 1'b0};
always @* hfporch_o = {hfporch_s[12:0], 1'b0};
always @* hswidth_o = {hswidth_s[12:0], 1'b0};
always @*
pinl[9:0] = (hactive_s[0]) ? (hactive_s[10:1]+1'b1) : hactive_s[10:1];
// shift /divide horizontal sync parameters
always @*
case (hshifter) // synopsys parallel_case full_case
4'b0,
4'b10,
4'b100,
4'b101,
4'b110,
4'b1000,
4'b1001,
4'b1010,
4'b1011,
4'b1100,
4'b1101,
4'b1110: begin
hactive_s[13:0]=hactive[13:0];
hblank_s[13:0]=hblank[13:0];
hfporch_s[13:0]=hfporch[13:0];
hswidth_s[13:0]=hswidth[13:0];
end // case: 4'b0,...
4'b1: begin
hactive_s[13:0]={1'b0,hactive[13:1]};
hblank_s[13:0]= {1'b0,hblank[13:1]};
hfporch_s[13:0]={1'b0,hfporch[13:1]};
hswidth_s[13:0]={1'b0,hswidth[13:1]};
end // case: 4'b1
4'b11: begin
hactive_s[13:0]={2'b0,hactive[13:2]};
hblank_s[13:0] ={2'b0,hblank[13:2]};
hfporch_s[13:0]={2'b0,hfporch[13:2]};
hswidth_s[13:0]={2'b0,hswidth[13:2]};
end // case: 4'b11
4'b111: begin
hactive_s[13:0]={3'b0,hactive[13:3]};
hblank_s[13:0]= {3'b0,hblank[13:3]};
hfporch_s[13:0]={3'b0,hfporch[13:3]};
hswidth_s[13:0]={3'b0,hswidth[13:3]};
end // case: 4'b111
4'b1111: begin
hactive_s[13:0]={4'b0,hactive[13:4]};
hblank_s[13:0]= {4'b0,hblank[13:4]};
hfporch_s[13:0]={4'b0,hfporch[13:4]};
hswidth_s[13:0]={4'b0,hswidth[13:4]};
end // case: 4'b1111
endcase
always @ (posedge hclock or negedge hnreset)
if(!hnreset) begin
syncsenable <= 2'b0;
videnable <= 1'b0;
refresh_enable <= 1'b0;
ovignr <= 1'b0;
ovignr16l <= 1'b0;
fdp_on <= 1'b1; // Now enable Flat panel on reset
ss_mode <= 1'b0;
end else if (hwr && !hncs) begin
case (haddr[7:2]) //
{SYNC_SELorMEM_CONFIG, 1'b0}: begin
if (!hnben[0]) videnable <= hdat_in[6];
if (!hnben[0]) syncsenable <= hdat_in[5:4];
if (!hnben[0]) {crtintl, compsync, posvs, poshs} <= hdat_in[3:0];
if (!hnben[1]) fdp_on <= hdat_in[8];
if (!hnben[3]) ss_mode <= hdat_in[30];
end
{SYNC_SELorMEM_CONFIG, 1'b1}: begin
if (!hnben[1]) refresh_enable <= hdat_in[8];
if (!hnben[1]) ovignr16l <= hdat_in[9];
if (!hnben[1]) ovignr <= hdat_in[10];
end
{FRAME_COUNTorLINE_COUNT, 1'b0}: begin
if (!hnben[0]) vicount[7:0] <= hdat_in[7:0];
end
{FRAME_COUNTorLINE_COUNT, 1'b1}: begin
if (!hnben[0]) hicount[7:0] <= {hdat_in[7:1], 1'b0};
if (!hnben[1]) hicount[11:8] <= hdat_in[11:8];
end
{DISP_STARTorDISP_PITCH, 1'b1}: begin
if (!hnben[0]) db_pitch[7:4] <= hdat_in[7:4];
if (!hnben[1]) db_pitch[15:8] <= hdat_in[15:8];
end
{HACTIVEorHBLANK, 1'b0}: begin
if (!hnben[0]) hactive[7:0] <= hdat_in[7:0];
if (!hnben[1]) hactive[13:8] <= hdat_in[13:8];
end
{HACTIVEorHBLANK, 1'b1}: begin
if (!hnben[0]) hblank[7:0] <= hdat_in[7:0];
if (!hnben[1]) hblank[13:8] <= hdat_in[13:8];
end
{HFPORCHorHSYNC, 1'b0}: begin
if (!hnben[0]) hfporch[7:0] <= hdat_in[7:0];
if (!hnben[1]) hfporch[13:8] <= hdat_in[13:8];
end
{HFPORCHorHSYNC, 1'b1}: begin
if (!hnben[0]) hswidth[7:0] <= hdat_in[7:0];
if (!hnben[1]) hswidth[13:8] <= hdat_in[13:8];
end
{VACTIVEorVBLANK, 1'b0}: begin
if (!hnben[0]) vactive[7:0] <= hdat_in[7:0];
if (!hnben[1]) vactive[11:8] <= hdat_in[11:8];
end
{VACTIVEorVBLANK, 1'b1}: begin
if (!hnben[0]) vblank[7:0] <= hdat_in[7:0];
if (!hnben[1]) vblank[11:8] <= hdat_in[11:8];
end
{VFPORCHorVSYNC, 1'b0}: begin
if (!hnben[0]) vfporch[7:0] <= hdat_in[7:0];
if (!hnben[1]) vfporch[11:8] <= hdat_in[11:8];
end
{VFPORCHorVSYNC, 1'b1}: begin
if (!hnben[0]) vswidth[7:0] <= hdat_in[7:0];
if (!hnben[1]) vswidth[11:8] <= hdat_in[11:8];
end
{LCOUNTSorZOOM, 1'b1}: begin
if (!hnben[0]) dzoom[3:0] <= hdat_in[3:0];
if (!hnben[2]) hshifter[3:0] <= hdat_in[19:16];
end
{SEC_STARTorRESERVED, 1'b0}: begin
if (!hnben[0]) sec_start[7:4] <= hdat_in[7:4];
if (!hnben[1]) sec_start[15:8] <= hdat_in[15:8];
if (!hnben[2]) sec_start[23:16] <= hdat_in[23:16];
if (!hnben[3]) sec_start[24] <= hdat_in[24];
end
endcase // case (haddr)
end // if (hwr && !hncs)
// displ_start register can be modyfied by host and DLP, DLP no byte writes
always @ (posedge hclock) begin
// host writes
if( hwr && !hncs && (haddr[7:2] == {DISP_STARTorDISP_PITCH, 1'b0}) ) begin
if (!hnben[0]) displ_start[7:4] <= hdat_in[7:4];
if (!hnben[1]) displ_start[15:8] <= hdat_in[15:8];
if (!hnben[2]) displ_start[23:16] <= hdat_in[23:16];
if (!hnben[3]) displ_start[24] <= hdat_in[24];
end else if (dlp_wradd) //DLP writes
displ_start[24:4] <= dlp_add;
end
// ad_strst is a one hclk active high signal
// generated after the display start address gets synchronized
// (once per frame)
// This is now a synchronous signal for synchronous clearing.
always @(posedge hclock or negedge hnreset) begin
if (!hnreset) addr_stat <= 1'b0;
else if (ad_strst) addr_stat <= 1'b0;
else if ((hwr && !hncs && !hnben[3]
&& (haddr[7:2] == {DISP_STARTorDISP_PITCH, 1'b0})
) || dlp_wradd)
addr_stat <= 1'b1;
end
/*********** output mux **************************************************/
// haddr[2] in this case statement got added for layout improvements
// (64->32 bus)
// Only to avoid redefinitions in case values bit[2] is treated seperately
// even if it looks strange
always @*
case (haddr[7:2]) //synopsys parallel_case
{FRAME_COUNTorLINE_COUNT, 1'b0}: hdat_out[31:0] = {24'b0, vicount[7:0]};
{FRAME_COUNTorLINE_COUNT, 1'b1}: hdat_out[31:0] = {20'b0, hicount[11:0]};
{DISP_STARTorDISP_PITCH, 1'b0}: hdat_out[31:0] = {addr_stat, 1'b0,
vblnkst, 4'b0,
displ_start[24:4],
4'b0};
{DISP_STARTorDISP_PITCH, 1'b1}: hdat_out[31:0] = {16'b0, db_pitch[15:4],
4'b0};
{HACTIVEorHBLANK, 1'b0}: hdat_out[31:0] = {18'b0, hactive[13:0]};
{HACTIVEorHBLANK, 1'b1}: hdat_out[31:0] = {18'b0, hblank[13:0]};
{HFPORCHorHSYNC, 1'b0}: hdat_out[31:0] = {18'b0, hfporch[13:0]};
{HFPORCHorHSYNC, 1'b1}: hdat_out[31:0] = {18'b0, hswidth[13:0]};
{VACTIVEorVBLANK, 1'b0}: hdat_out[31:0] = {20'b0, vactive[11:0]};
{VACTIVEorVBLANK, 1'b1}: hdat_out[31:0] = {20'b0, vblank[11:0]};
{VFPORCHorVSYNC, 1'b0}: hdat_out[31:0] = {20'b0, vfporch[11:0]};
{VFPORCHorVSYNC, 1'b1}: hdat_out[31:0] = {20'b0, vswidth[11:0]};
{LCOUNTSorZOOM, 1'b0}: hdat_out[31:0] = {20'b0,
lcounter_stat[11:0]};
{LCOUNTSorZOOM, 1'b1}: hdat_out[31:0] = {12'b0, hshifter[3:0],
12'b0, dzoom[3:0]};
{SYNC_SELorMEM_CONFIG, 1'b0}: hdat_out[31:0] = {1'b0, ss_mode,
1'b0, 13'b0,
7'b0, fdp_on,
1'b0, videnable,
syncsenable[1:0],
crtintl, compsync,
posvs, poshs };
{SYNC_SELorMEM_CONFIG, 1'b1}: hdat_out[31:0] = {8'b0, 8'b0, 5'b0,
ovignr, ovignr16l,
refresh_enable, 8'b0};
{SEC_STARTorRESERVED, 1'b0}: hdat_out[31:0] = {7'b0, sec_start[24:4],
4'b0};
{SEC_STARTorRESERVED, 1'b1}: hdat_out[31:0] = 32'b0;
default: hdat_out[31:0]= 32'b0; // why not?
endcase
endmodule |
module Logic(output [31:0] LogicAnswer, input [31:0] A,input [31:0] B, input [2:0] OpCode);
wire [31:0] ANDAns;
wire [31:0] ORAns;
wire [31:0] XORAns;
wire [31:0] LeftLSHIFTERAns;
wire [31:0] RightLSHIFTERAns;
wire [31:0] LeftASHIFTERAns;
wire [31:0] RightASHIFTERAns;
genvar i;
AND_32bit l1(ANDAns, A, B);
OR_32bit l2(ORAns, A, B);
XOR_32bit l3(XORAns, A, B);
LSHIFTER_32bit l4(LeftLSHIFTERAns, A, 1);
LSHIFTER_32bit l5(RightLSHIFTERAns, A, 0);
ASHIFTER_32bit l6(LeftASHIFTERAns, A, 1);
ASHIFTER_32bit l7(RightASHIFTERAns, A, 0);
generate for(i=0; i<32; i=i+1) begin: multiple2to1muxs
mux8to1 Mux1(LogicAnswer[i], ANDAns[i], ORAns[i], XORAns[i], LeftLSHIFTERAns[i], RightLSHIFTERAns[i], LeftASHIFTERAns[i], RightASHIFTERAns[i], 32'b0, OpCode); //'
end endgenerate
endmodule |
module sky130_fd_sc_hdll__mux2i_1 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__mux2i_1 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule |
module sky130_fd_sc_lp__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_lp__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule |
module system_acl_iface_acl_kernel_interface_mm_interconnect_0 (
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cra_reset_reset_bridge_in_reset_reset, // kernel_cra_reset_reset_bridge_in_reset.reset
input wire [29:0] address_span_extender_0_expanded_master_address, // address_span_extender_0_expanded_master.address
output wire address_span_extender_0_expanded_master_waitrequest, // .waitrequest
input wire [0:0] address_span_extender_0_expanded_master_burstcount, // .burstcount
input wire [3:0] address_span_extender_0_expanded_master_byteenable, // .byteenable
input wire address_span_extender_0_expanded_master_read, // .read
output wire [31:0] address_span_extender_0_expanded_master_readdata, // .readdata
output wire address_span_extender_0_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_0_expanded_master_write, // .write
input wire [31:0] address_span_extender_0_expanded_master_writedata, // .writedata
output wire [29:0] kernel_cra_s0_address, // kernel_cra_s0.address
output wire kernel_cra_s0_write, // .write
output wire kernel_cra_s0_read, // .read
input wire [63:0] kernel_cra_s0_readdata, // .readdata
output wire [63:0] kernel_cra_s0_writedata, // .writedata
output wire [0:0] kernel_cra_s0_burstcount, // .burstcount
output wire [7:0] kernel_cra_s0_byteenable, // .byteenable
input wire kernel_cra_s0_readdatavalid, // .readdatavalid
input wire kernel_cra_s0_waitrequest, // .waitrequest
output wire kernel_cra_s0_debugaccess // .debugaccess
);
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_0_expanded_master_agent:av_waitrequest -> address_span_extender_0_expanded_master_translator:uav_waitrequest
wire [2:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_0_expanded_master_translator:uav_burstcount -> address_span_extender_0_expanded_master_agent:av_burstcount
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_0_expanded_master_translator:uav_writedata -> address_span_extender_0_expanded_master_agent:av_writedata
wire [29:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_0_expanded_master_translator:uav_address -> address_span_extender_0_expanded_master_agent:av_address
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_0_expanded_master_translator:uav_lock -> address_span_extender_0_expanded_master_agent:av_lock
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_0_expanded_master_translator:uav_write -> address_span_extender_0_expanded_master_agent:av_write
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_0_expanded_master_translator:uav_read -> address_span_extender_0_expanded_master_agent:av_read
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_0_expanded_master_agent:av_readdata -> address_span_extender_0_expanded_master_translator:uav_readdata
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_0_expanded_master_translator:uav_debugaccess -> address_span_extender_0_expanded_master_agent:av_debugaccess
wire [3:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_0_expanded_master_translator:uav_byteenable -> address_span_extender_0_expanded_master_agent:av_byteenable
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_0_expanded_master_agent:av_readdatavalid -> address_span_extender_0_expanded_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_0_expanded_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_0_expanded_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_0_expanded_master_agent:rp_startofpacket
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_0_expanded_master_agent:rp_data
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_0_expanded_master_agent:rp_channel
wire rsp_mux_src_ready; // address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire kernel_cra_s0_agent_m0_waitrequest; // kernel_cra_s0_translator:uav_waitrequest -> kernel_cra_s0_agent:m0_waitrequest
wire [3:0] kernel_cra_s0_agent_m0_burstcount; // kernel_cra_s0_agent:m0_burstcount -> kernel_cra_s0_translator:uav_burstcount
wire [63:0] kernel_cra_s0_agent_m0_writedata; // kernel_cra_s0_agent:m0_writedata -> kernel_cra_s0_translator:uav_writedata
wire [29:0] kernel_cra_s0_agent_m0_address; // kernel_cra_s0_agent:m0_address -> kernel_cra_s0_translator:uav_address
wire kernel_cra_s0_agent_m0_write; // kernel_cra_s0_agent:m0_write -> kernel_cra_s0_translator:uav_write
wire kernel_cra_s0_agent_m0_lock; // kernel_cra_s0_agent:m0_lock -> kernel_cra_s0_translator:uav_lock
wire kernel_cra_s0_agent_m0_read; // kernel_cra_s0_agent:m0_read -> kernel_cra_s0_translator:uav_read
wire [63:0] kernel_cra_s0_agent_m0_readdata; // kernel_cra_s0_translator:uav_readdata -> kernel_cra_s0_agent:m0_readdata
wire kernel_cra_s0_agent_m0_readdatavalid; // kernel_cra_s0_translator:uav_readdatavalid -> kernel_cra_s0_agent:m0_readdatavalid
wire kernel_cra_s0_agent_m0_debugaccess; // kernel_cra_s0_agent:m0_debugaccess -> kernel_cra_s0_translator:uav_debugaccess
wire [7:0] kernel_cra_s0_agent_m0_byteenable; // kernel_cra_s0_agent:m0_byteenable -> kernel_cra_s0_translator:uav_byteenable
wire kernel_cra_s0_agent_rf_source_endofpacket; // kernel_cra_s0_agent:rf_source_endofpacket -> kernel_cra_s0_agent_rsp_fifo:in_endofpacket
wire kernel_cra_s0_agent_rf_source_valid; // kernel_cra_s0_agent:rf_source_valid -> kernel_cra_s0_agent_rsp_fifo:in_valid
wire kernel_cra_s0_agent_rf_source_startofpacket; // kernel_cra_s0_agent:rf_source_startofpacket -> kernel_cra_s0_agent_rsp_fifo:in_startofpacket
wire [137:0] kernel_cra_s0_agent_rf_source_data; // kernel_cra_s0_agent:rf_source_data -> kernel_cra_s0_agent_rsp_fifo:in_data
wire kernel_cra_s0_agent_rf_source_ready; // kernel_cra_s0_agent_rsp_fifo:in_ready -> kernel_cra_s0_agent:rf_source_ready
wire kernel_cra_s0_agent_rsp_fifo_out_endofpacket; // kernel_cra_s0_agent_rsp_fifo:out_endofpacket -> kernel_cra_s0_agent:rf_sink_endofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_valid; // kernel_cra_s0_agent_rsp_fifo:out_valid -> kernel_cra_s0_agent:rf_sink_valid
wire kernel_cra_s0_agent_rsp_fifo_out_startofpacket; // kernel_cra_s0_agent_rsp_fifo:out_startofpacket -> kernel_cra_s0_agent:rf_sink_startofpacket
wire [137:0] kernel_cra_s0_agent_rsp_fifo_out_data; // kernel_cra_s0_agent_rsp_fifo:out_data -> kernel_cra_s0_agent:rf_sink_data
wire kernel_cra_s0_agent_rsp_fifo_out_ready; // kernel_cra_s0_agent:rf_sink_ready -> kernel_cra_s0_agent_rsp_fifo:out_ready
wire kernel_cra_s0_agent_rdata_fifo_src_valid; // kernel_cra_s0_agent:rdata_fifo_src_valid -> kernel_cra_s0_agent:rdata_fifo_sink_valid
wire [65:0] kernel_cra_s0_agent_rdata_fifo_src_data; // kernel_cra_s0_agent:rdata_fifo_src_data -> kernel_cra_s0_agent:rdata_fifo_sink_data
wire kernel_cra_s0_agent_rdata_fifo_src_ready; // kernel_cra_s0_agent:rdata_fifo_sink_ready -> kernel_cra_s0_agent:rdata_fifo_src_ready
wire address_span_extender_0_expanded_master_agent_cp_endofpacket; // address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_0_expanded_master_agent_cp_valid; // address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
wire address_span_extender_0_expanded_master_agent_cp_startofpacket; // address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [100:0] address_span_extender_0_expanded_master_agent_cp_data; // address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_0_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_0_expanded_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire kernel_cra_s0_agent_rp_endofpacket; // kernel_cra_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
wire kernel_cra_s0_agent_rp_valid; // kernel_cra_s0_agent:rp_valid -> router_001:sink_valid
wire kernel_cra_s0_agent_rp_startofpacket; // kernel_cra_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [136:0] kernel_cra_s0_agent_rp_data; // kernel_cra_s0_agent:rp_data -> router_001:sink_data
wire kernel_cra_s0_agent_rp_ready; // router_001:sink_ready -> kernel_cra_s0_agent:rp_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> kernel_cra_s0_cmd_width_adapter:in_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> kernel_cra_s0_cmd_width_adapter:in_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> kernel_cra_s0_cmd_width_adapter:in_startofpacket
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> kernel_cra_s0_cmd_width_adapter:in_data
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> kernel_cra_s0_cmd_width_adapter:in_channel
wire cmd_mux_src_ready; // kernel_cra_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire kernel_cra_s0_cmd_width_adapter_src_endofpacket; // kernel_cra_s0_cmd_width_adapter:out_endofpacket -> kernel_cra_s0_agent:cp_endofpacket
wire kernel_cra_s0_cmd_width_adapter_src_valid; // kernel_cra_s0_cmd_width_adapter:out_valid -> kernel_cra_s0_agent:cp_valid
wire kernel_cra_s0_cmd_width_adapter_src_startofpacket; // kernel_cra_s0_cmd_width_adapter:out_startofpacket -> kernel_cra_s0_agent:cp_startofpacket
wire [136:0] kernel_cra_s0_cmd_width_adapter_src_data; // kernel_cra_s0_cmd_width_adapter:out_data -> kernel_cra_s0_agent:cp_data
wire kernel_cra_s0_cmd_width_adapter_src_ready; // kernel_cra_s0_agent:cp_ready -> kernel_cra_s0_cmd_width_adapter:out_ready
wire [0:0] kernel_cra_s0_cmd_width_adapter_src_channel; // kernel_cra_s0_cmd_width_adapter:out_channel -> kernel_cra_s0_agent:cp_channel
wire router_001_src_endofpacket; // router_001:src_endofpacket -> kernel_cra_s0_rsp_width_adapter:in_endofpacket
wire router_001_src_valid; // router_001:src_valid -> kernel_cra_s0_rsp_width_adapter:in_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> kernel_cra_s0_rsp_width_adapter:in_startofpacket
wire [136:0] router_001_src_data; // router_001:src_data -> kernel_cra_s0_rsp_width_adapter:in_data
wire [0:0] router_001_src_channel; // router_001:src_channel -> kernel_cra_s0_rsp_width_adapter:in_channel
wire router_001_src_ready; // kernel_cra_s0_rsp_width_adapter:in_ready -> router_001:src_ready
wire kernel_cra_s0_rsp_width_adapter_src_endofpacket; // kernel_cra_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire kernel_cra_s0_rsp_width_adapter_src_valid; // kernel_cra_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire kernel_cra_s0_rsp_width_adapter_src_startofpacket; // kernel_cra_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire [100:0] kernel_cra_s0_rsp_width_adapter_src_data; // kernel_cra_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire kernel_cra_s0_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> kernel_cra_s0_rsp_width_adapter:out_ready
wire [0:0] kernel_cra_s0_rsp_width_adapter_src_channel; // kernel_cra_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_0_expanded_master_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_0_expanded_master_read), // .read
.av_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_0_expanded_master_write), // .write
.av_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) kernel_cra_s0_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cra_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.uav_read (kernel_cra_s0_agent_m0_read), // .read
.uav_write (kernel_cra_s0_agent_m0_write), // .write
.uav_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.uav_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.uav_lock (kernel_cra_s0_agent_m0_lock), // .lock
.uav_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.av_address (kernel_cra_s0_address), // avalon_anti_slave_0.address
.av_write (kernel_cra_s0_write), // .write
.av_read (kernel_cra_s0_read), // .read
.av_readdata (kernel_cra_s0_readdata), // .readdata
.av_writedata (kernel_cra_s0_writedata), // .writedata
.av_burstcount (kernel_cra_s0_burstcount), // .burstcount
.av_byteenable (kernel_cra_s0_byteenable), // .byteenable
.av_readdatavalid (kernel_cra_s0_readdatavalid), // .readdatavalid
.av_waitrequest (kernel_cra_s0_waitrequest), // .waitrequest
.av_debugaccess (kernel_cra_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (76),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_ORI_BURST_SIZE_H (100),
.ST_DATA_W (101),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_expanded_master_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_0_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_0_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (120),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (101),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (102),
.PKT_TRANS_POSTED (103),
.PKT_TRANS_WRITE (104),
.PKT_TRANS_READ (105),
.PKT_TRANS_LOCK (106),
.PKT_SRC_ID_H (122),
.PKT_SRC_ID_L (122),
.PKT_DEST_ID_H (123),
.PKT_DEST_ID_L (123),
.PKT_BURSTWRAP_H (112),
.PKT_BURSTWRAP_L (112),
.PKT_BYTE_CNT_H (111),
.PKT_BYTE_CNT_L (108),
.PKT_PROTECTION_H (127),
.PKT_PROTECTION_L (125),
.PKT_RESPONSE_STATUS_H (133),
.PKT_RESPONSE_STATUS_L (132),
.PKT_BURST_SIZE_H (115),
.PKT_BURST_SIZE_L (113),
.PKT_ORI_BURST_SIZE_L (134),
.PKT_ORI_BURST_SIZE_H (136),
.ST_CHANNEL_W (1),
.ST_DATA_W (137),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cra_s0_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (kernel_cra_s0_agent_m0_address), // m0.address
.m0_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (kernel_cra_s0_agent_m0_lock), // .lock
.m0_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (kernel_cra_s0_agent_m0_read), // .read
.m0_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.m0_write (kernel_cra_s0_agent_m0_write), // .write
.rp_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (kernel_cra_s0_agent_rp_ready), // .ready
.rp_valid (kernel_cra_s0_agent_rp_valid), // .valid
.rp_data (kernel_cra_s0_agent_rp_data), // .data
.rp_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.cp_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.cp_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (kernel_cra_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (kernel_cra_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (kernel_cra_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (138),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) kernel_cra_s0_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (kernel_cra_s0_agent_rf_source_data), // in.data
.in_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.in_ready (kernel_cra_s0_agent_rf_source_ready), // .ready
.in_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (kernel_cra_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router router (
.sink_ready (address_span_extender_0_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_0_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 router_001 (
.sink_ready (kernel_cra_s0_agent_rp_ready), // sink.ready
.sink_valid (kernel_cra_s0_agent_rp_valid), // .valid
.sink_data (kernel_cra_s0_agent_rp_data), // .data
.sink_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.sink_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (65),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (72),
.IN_PKT_TRANS_COMPRESSED_READ (66),
.IN_PKT_BURSTWRAP_H (76),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (79),
.IN_PKT_BURST_SIZE_L (77),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (71),
.IN_PKT_BURST_TYPE_H (81),
.IN_PKT_BURST_TYPE_L (80),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (101),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (111),
.OUT_PKT_BYTE_CNT_L (108),
.OUT_PKT_TRANS_COMPRESSED_READ (102),
.OUT_PKT_BURST_SIZE_H (115),
.OUT_PKT_BURST_SIZE_L (113),
.OUT_PKT_RESPONSE_STATUS_H (133),
.OUT_PKT_RESPONSE_STATUS_L (132),
.OUT_PKT_TRANS_EXCLUSIVE (107),
.OUT_PKT_BURST_TYPE_H (117),
.OUT_PKT_BURST_TYPE_L (116),
.OUT_PKT_ORI_BURST_SIZE_L (134),
.OUT_PKT_ORI_BURST_SIZE_H (136),
.OUT_ST_DATA_W (137),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (101),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (111),
.IN_PKT_BYTE_CNT_L (108),
.IN_PKT_TRANS_COMPRESSED_READ (102),
.IN_PKT_BURSTWRAP_H (112),
.IN_PKT_BURSTWRAP_L (112),
.IN_PKT_BURST_SIZE_H (115),
.IN_PKT_BURST_SIZE_L (113),
.IN_PKT_RESPONSE_STATUS_H (133),
.IN_PKT_RESPONSE_STATUS_L (132),
.IN_PKT_TRANS_EXCLUSIVE (107),
.IN_PKT_BURST_TYPE_H (117),
.IN_PKT_BURST_TYPE_L (116),
.IN_PKT_ORI_BURST_SIZE_L (134),
.IN_PKT_ORI_BURST_SIZE_H (136),
.IN_ST_DATA_W (137),
.OUT_PKT_ADDR_H (65),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (72),
.OUT_PKT_TRANS_COMPRESSED_READ (66),
.OUT_PKT_BURST_SIZE_H (79),
.OUT_PKT_BURST_SIZE_L (77),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (71),
.OUT_PKT_BURST_TYPE_H (81),
.OUT_PKT_BURST_TYPE_L (80),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule |
module pcie_hip_s4gx_gen2_x4_128_example_chaining_pipen1b (
// inputs:
free_100MHz,
local_rstn,
pcie_rstn,
pclk_in,
phystatus_ext,
pipe_mode,
pld_clk,
refclk,
rx_in0,
rx_in1,
rx_in2,
rx_in3,
rxdata0_ext,
rxdata1_ext,
rxdata2_ext,
rxdata3_ext,
rxdatak0_ext,
rxdatak1_ext,
rxdatak2_ext,
rxdatak3_ext,
rxelecidle0_ext,
rxelecidle1_ext,
rxelecidle2_ext,
rxelecidle3_ext,
rxstatus0_ext,
rxstatus1_ext,
rxstatus2_ext,
rxstatus3_ext,
rxvalid0_ext,
rxvalid1_ext,
rxvalid2_ext,
rxvalid3_ext,
test_in,
// outputs:
clk250_out,
clk500_out,
core_clk_out,
gen2_speed,
lane_width_code,
pcie_reconfig_busy,
phy_sel_code,
powerdown_ext,
rate_ext,
rc_pll_locked,
ref_clk_sel_code,
rxpolarity0_ext,
rxpolarity1_ext,
rxpolarity2_ext,
rxpolarity3_ext,
test_out_icm,
tx_out0,
tx_out1,
tx_out2,
tx_out3,
txcompl0_ext,
txcompl1_ext,
txcompl2_ext,
txcompl3_ext,
txdata0_ext,
txdata1_ext,
txdata2_ext,
txdata3_ext,
txdatak0_ext,
txdatak1_ext,
txdatak2_ext,
txdatak3_ext,
txdetectrx_ext,
txelecidle0_ext,
txelecidle1_ext,
txelecidle2_ext,
txelecidle3_ext
)
;
output clk250_out;
output clk500_out;
output core_clk_out;
output gen2_speed;
output [ 3: 0] lane_width_code;
output pcie_reconfig_busy;
output [ 3: 0] phy_sel_code;
output [ 1: 0] powerdown_ext;
output rate_ext;
output rc_pll_locked;
output [ 3: 0] ref_clk_sel_code;
output rxpolarity0_ext;
output rxpolarity1_ext;
output rxpolarity2_ext;
output rxpolarity3_ext;
output [ 8: 0] test_out_icm;
output tx_out0;
output tx_out1;
output tx_out2;
output tx_out3;
output txcompl0_ext;
output txcompl1_ext;
output txcompl2_ext;
output txcompl3_ext;
output [ 7: 0] txdata0_ext;
output [ 7: 0] txdata1_ext;
output [ 7: 0] txdata2_ext;
output [ 7: 0] txdata3_ext;
output txdatak0_ext;
output txdatak1_ext;
output txdatak2_ext;
output txdatak3_ext;
output txdetectrx_ext;
output txelecidle0_ext;
output txelecidle1_ext;
output txelecidle2_ext;
output txelecidle3_ext;
input free_100MHz;
input local_rstn;
input pcie_rstn;
input pclk_in;
input phystatus_ext;
input pipe_mode;
input pld_clk;
input refclk;
input rx_in0;
input rx_in1;
input rx_in2;
input rx_in3;
input [ 7: 0] rxdata0_ext;
input [ 7: 0] rxdata1_ext;
input [ 7: 0] rxdata2_ext;
input [ 7: 0] rxdata3_ext;
input rxdatak0_ext;
input rxdatak1_ext;
input rxdatak2_ext;
input rxdatak3_ext;
input rxelecidle0_ext;
input rxelecidle1_ext;
input rxelecidle2_ext;
input rxelecidle3_ext;
input [ 2: 0] rxstatus0_ext;
input [ 2: 0] rxstatus1_ext;
input [ 2: 0] rxstatus2_ext;
input [ 2: 0] rxstatus3_ext;
input rxvalid0_ext;
input rxvalid1_ext;
input rxvalid2_ext;
input rxvalid3_ext;
input [ 39: 0] test_in;
wire app_int_ack_icm;
wire app_int_sts_icm;
wire app_msi_ack;
wire [ 4: 0] app_msi_num;
wire app_msi_req;
wire [ 2: 0] app_msi_tc;
wire [ 12: 0] cfg_busdev_icm;
wire [ 31: 0] cfg_devcsr_icm;
wire [ 19: 0] cfg_io_bas;
wire [ 31: 0] cfg_linkcsr_icm;
wire [ 15: 0] cfg_msicsr;
wire [ 11: 0] cfg_np_bas;
wire [ 43: 0] cfg_pr_bas;
wire [ 31: 0] cfg_prmcsr_icm;
wire clk250_out;
wire clk500_out;
wire core_clk_out;
wire [ 6: 0] cpl_err_icm;
wire [ 6: 0] cpl_err_in;
wire cpl_pending_icm;
wire [ 4: 0] dl_ltssm;
wire [127: 0] err_desc;
wire fixedclk_serdes;
wire gen2_speed;
wire [ 23: 0] gnd_cfg_tcvcmap_icm;
wire gnd_msi_stream_ready0;
wire [ 9: 0] gnd_pm_data;
wire gnd_tx_stream_mask0;
wire [ 19: 0] ko_cpl_spc_vc0;
wire [ 3: 0] lane_act;
wire [ 3: 0] lane_width_code;
wire lmi_ack;
wire [ 11: 0] lmi_addr;
wire [ 31: 0] lmi_din;
wire [ 31: 0] lmi_dout;
wire lmi_rden;
wire lmi_wren;
wire [ 4: 0] open_aer_msi_num;
wire [ 23: 0] open_cfg_tcvcmap;
wire open_cplerr_lmi_busy;
wire [ 7: 0] open_msi_stream_data0;
wire open_msi_stream_valid0;
wire [ 9: 0] open_pm_data;
wire open_rx_st_err0;
wire otb0;
wire otb1;
wire pcie_reconfig_busy;
wire [ 4: 0] pex_msi_num_icm;
wire [ 3: 0] phy_sel_code;
wire pme_to_sr;
wire [ 1: 0] powerdown_ext;
wire rate_ext;
wire rc_pll_locked;
wire reconfig_clk;
wire reconfig_clk_locked;
wire [ 3: 0] ref_clk_sel_code;
wire rx_mask0;
wire [ 7: 0] rx_st_bardec0;
wire [ 15: 0] rx_st_be0;
wire [127: 0] rx_st_data0;
wire rx_st_empty0;
wire rx_st_eop0;
wire rx_st_sop0;
wire [ 81: 0] rx_stream_data0;
wire [ 81: 0] rx_stream_data0_1;
wire rx_stream_ready0;
wire rx_stream_valid0;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire srstn;
wire [ 8: 0] test_out_icm;
wire [ 8: 0] test_out_int;
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
wire [ 52: 0] tl_cfg_sts;
wire tl_cfg_sts_wr;
wire tx_fifo_empty0;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire [127: 0] tx_st_data0;
wire tx_st_empty0;
wire tx_st_eop0;
wire tx_st_err0;
wire tx_st_sop0;
wire [ 35: 0] tx_stream_cred0;
wire [ 74: 0] tx_stream_data0;
wire [ 74: 0] tx_stream_data0_1;
wire tx_stream_ready0;
wire tx_stream_valid0;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdetectrx_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
assign ref_clk_sel_code = 0;
assign lane_width_code = 2;
assign phy_sel_code = 6;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
assign gnd_pm_data = 0;
assign ko_cpl_spc_vc0[7 : 0] = 8'd112;
assign ko_cpl_spc_vc0[19 : 8] = 12'd448;
assign gnd_cfg_tcvcmap_icm = 0;
assign tx_st_sop0 = tx_stream_data0[73];
assign tx_st_err0 = tx_stream_data0[74];
assign rx_stream_data0 = {rx_st_be0[7 : 0], rx_st_sop0, rx_st_empty0, rx_st_bardec0, rx_st_data0[63 : 0]};
assign rx_stream_data0_1 = {rx_st_be0[15 : 8], rx_st_sop0, rx_st_eop0, rx_st_bardec0, rx_st_data0[127 : 64]};
assign tx_st_data0 = {tx_stream_data0_1[63 : 0],tx_stream_data0[63 : 0]};
assign tx_st_eop0 = tx_stream_data0_1[72];
assign tx_st_empty0 = tx_stream_data0[72];
assign test_out_icm = test_out_int;
assign pcie_reconfig_busy = 1'b1;
assign gen2_speed = cfg_linkcsr_icm[17];
assign gnd_tx_stream_mask0 = 1'b0;
assign gnd_msi_stream_ready0 = 1'b0;
pcie_hip_s4gx_gen2_x4_128_plus ep_plus
(
.app_int_ack (app_int_ack_icm),
.app_int_sts (app_int_sts_icm),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.clk250_out (clk250_out),
.clk500_out (clk500_out),
.core_clk_out (core_clk_out),
.cpl_err (cpl_err_icm),
.cpl_pending (cpl_pending_icm),
.fixedclk_serdes (fixedclk_serdes),
.lane_act (lane_act),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_dout (lmi_dout),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.local_rstn (local_rstn),
.ltssm (dl_ltssm),
.pcie_rstn (pcie_rstn),
.pclk_in (pclk_in),
.pex_msi_num (pex_msi_num_icm),
.phystatus_ext (phystatus_ext),
.pipe_mode (pipe_mode),
.pld_clk (pld_clk),
.pm_auxpwr (1'b0),
.pm_data (gnd_pm_data),
.pm_event (1'b0),
.pme_to_cr (pme_to_sr),
.pme_to_sr (pme_to_sr),
.powerdown_ext (powerdown_ext),
.rate_ext (rate_ext),
.rc_pll_locked (rc_pll_locked),
.reconfig_clk (reconfig_clk),
.reconfig_clk_locked (reconfig_clk_locked),
.refclk (refclk),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rx_st_bardec0 (rx_st_bardec0),
.rx_st_be0 (rx_st_be0),
.rx_st_data0 (rx_st_data0),
.rx_st_empty0 (rx_st_empty0),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (open_rx_st_err0),
.rx_st_mask0 (rx_mask0),
.rx_st_ready0 (rx_stream_ready0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_valid0 (rx_stream_valid0),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.srstn (srstn),
.test_in (test_in),
.test_out (test_out_int),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr),
.tx_cred0 (tx_stream_cred0),
.tx_fifo_empty0 (tx_fifo_empty0),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.tx_st_data0 (tx_st_data0),
.tx_st_empty0 (tx_st_empty0),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (tx_st_err0),
.tx_st_ready0 (tx_stream_ready0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_valid0 (tx_stream_valid0),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdetectrx_ext (txdetectrx_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext)
);
altpcierd_reconfig_clk_pll reconfig_pll
(
.c0 (reconfig_clk),
.c1 (fixedclk_serdes),
.inclk0 (free_100MHz),
.locked (reconfig_clk_locked)
);
altpcierd_tl_cfg_sample cfgbus
(
.cfg_busdev (cfg_busdev_icm),
.cfg_devcsr (cfg_devcsr_icm),
.cfg_io_bas (cfg_io_bas),
.cfg_linkcsr (cfg_linkcsr_icm),
.cfg_msicsr (cfg_msicsr),
.cfg_np_bas (cfg_np_bas),
.cfg_pr_bas (cfg_pr_bas),
.cfg_prmcsr (cfg_prmcsr_icm),
.cfg_tcvcmap (open_cfg_tcvcmap),
.pld_clk (pld_clk),
.rstn (srstn),
.tl_cfg_add (tl_cfg_add),
.tl_cfg_ctl (tl_cfg_ctl),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts),
.tl_cfg_sts_wr (tl_cfg_sts_wr)
);
defparam cfgbus.HIP_SV = 0;
altpcierd_cplerr_lmi lmi_blk
(
.clk_in (pld_clk),
.cpl_err_in (cpl_err_in),
.cpl_err_out (cpl_err_icm),
.cplerr_lmi_busy (open_cplerr_lmi_busy),
.err_desc (err_desc),
.lmi_ack (lmi_ack),
.lmi_addr (lmi_addr),
.lmi_din (lmi_din),
.lmi_rden (lmi_rden),
.lmi_wren (lmi_wren),
.rstn (srstn)
);
altpcierd_example_app_chaining app
(
.aer_msi_num (open_aer_msi_num),
.app_int_ack (app_int_ack_icm),
.app_int_sts (app_int_sts_icm),
.app_msi_ack (app_msi_ack),
.app_msi_num (app_msi_num),
.app_msi_req (app_msi_req),
.app_msi_tc (app_msi_tc),
.cfg_busdev (cfg_busdev_icm),
.cfg_devcsr (cfg_devcsr_icm),
.cfg_linkcsr (cfg_linkcsr_icm),
.cfg_msicsr (cfg_msicsr),
.cfg_prmcsr (cfg_prmcsr_icm),
.cfg_tcvcmap (gnd_cfg_tcvcmap_icm),
.clk_in (pld_clk),
.cpl_err (cpl_err_in),
.cpl_pending (cpl_pending_icm),
.err_desc (err_desc),
.ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
.msi_stream_data0 (open_msi_stream_data0),
.msi_stream_ready0 (gnd_msi_stream_ready0),
.msi_stream_valid0 (open_msi_stream_valid0),
.pex_msi_num (pex_msi_num_icm),
.pm_data (open_pm_data),
.rstn (srstn),
.rx_stream_data0_0 (rx_stream_data0),
.rx_stream_data0_1 (rx_stream_data0_1),
.rx_stream_mask0 (rx_mask0),
.rx_stream_ready0 (rx_stream_ready0),
.rx_stream_valid0 (rx_stream_valid0),
.test_sim (test_in[0]),
.tx_stream_cred0 (tx_stream_cred0),
.tx_stream_data0_0 (tx_stream_data0),
.tx_stream_data0_1 (tx_stream_data0_1),
.tx_stream_fifo_empty0 (tx_fifo_empty0),
.tx_stream_mask0 (gnd_tx_stream_mask0),
.tx_stream_ready0 (tx_stream_ready0),
.tx_stream_valid0 (tx_stream_valid0)
);
defparam app.AVALON_WADDR = 12,
app.CHECK_BUS_MASTER_ENA = 1,
app.CHECK_RX_BUFFER_CPL = 1,
app.CLK_250_APP = 0,
app.ECRC_FORWARD_CHECK = 0,
app.ECRC_FORWARD_GENER = 0,
app.MAX_NUMTAG = 32,
app.MAX_PAYLOAD_SIZE_BYTE = 256,
app.TL_SELECTION = 7,
app.TXCRED_WIDTH = 36;
endmodule |
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_hd__o221ai dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_awready,
m_axi_arready,
s_axi_rready,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
s_axi_awvalid,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_awready;
input m_axi_arready;
input s_axi_rready;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input s_axi_awvalid;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [22:0]Q;
wire \RD.ar_channel_0_n_0 ;
wire \RD.ar_channel_0_n_10 ;
wire \RD.ar_channel_0_n_11 ;
wire \RD.ar_channel_0_n_16 ;
wire \RD.ar_channel_0_n_3 ;
wire \RD.ar_channel_0_n_4 ;
wire \RD.ar_channel_0_n_46 ;
wire \RD.ar_channel_0_n_47 ;
wire \RD.ar_channel_0_n_48 ;
wire \RD.ar_channel_0_n_49 ;
wire \RD.ar_channel_0_n_5 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_1 ;
wire SI_REG_n_132;
wire SI_REG_n_133;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_149;
wire SI_REG_n_153;
wire SI_REG_n_154;
wire SI_REG_n_155;
wire SI_REG_n_156;
wire SI_REG_n_157;
wire SI_REG_n_161;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_168;
wire SI_REG_n_169;
wire SI_REG_n_170;
wire SI_REG_n_171;
wire SI_REG_n_172;
wire SI_REG_n_173;
wire SI_REG_n_174;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_181;
wire SI_REG_n_182;
wire SI_REG_n_26;
wire SI_REG_n_64;
wire SI_REG_n_8;
wire SI_REG_n_82;
wire \WR.aw_channel_0_n_0 ;
wire \WR.aw_channel_0_n_10 ;
wire \WR.aw_channel_0_n_15 ;
wire \WR.aw_channel_0_n_3 ;
wire \WR.aw_channel_0_n_4 ;
wire \WR.aw_channel_0_n_47 ;
wire \WR.aw_channel_0_n_48 ;
wire \WR.aw_channel_0_n_49 ;
wire \WR.aw_channel_0_n_50 ;
wire \WR.aw_channel_0_n_9 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire \ar.ar_pipe/m_valid_i0 ;
wire \ar.ar_pipe/p_1_in ;
wire \ar.ar_pipe/s_ready_i0 ;
wire [1:0]\ar_cmd_fsm_0/state ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire \aw.aw_pipe/p_1_in ;
wire [1:0]\aw_cmd_fsm_0/state ;
wire [11:0]axaddr_incr;
wire [11:0]b_awid;
wire [3:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:2]wrap_cnt;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel \RD.ar_channel_0
(.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.E(\ar.ar_pipe/p_1_in ),
.O({SI_REG_n_140,SI_REG_n_141,SI_REG_n_142,SI_REG_n_143}),
.Q({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_82,si_rs_arsize,si_rs_araddr}),
.S({\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset [1:0]}),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [2]),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [1:0]}),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_161),
.\axaddr_offset_r_reg[3]_1 (SI_REG_n_165),
.\cnt_read_reg[2]_rep__0 (\RD.r_channel_0_n_1 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_4 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_5 ),
.\m_payload_i_reg[3] ({SI_REG_n_132,SI_REG_n_133,SI_REG_n_134,SI_REG_n_135}),
.\m_payload_i_reg[47] (SI_REG_n_64),
.\m_payload_i_reg[47]_0 (SI_REG_n_167),
.\m_payload_i_reg[5] (SI_REG_n_166),
.\m_payload_i_reg[6] ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
.\m_payload_i_reg[7] ({SI_REG_n_136,SI_REG_n_137,SI_REG_n_138,SI_REG_n_139}),
.m_valid_i0(\ar.ar_pipe/m_valid_i0 ),
.\r_arid_r_reg[11] (s_arid_r),
.r_push_r_reg(\RD.ar_channel_0_n_3 ),
.r_rlast(r_rlast),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i0(\ar.ar_pipe/s_ready_i0 ),
.s_ready_i_reg(s_axi_arready),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\ar_cmd_fsm_0/state ),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_0 ),
.\wrap_cnt_r_reg[3] (\RD.ar_channel_0_n_10 ),
.\wrap_cnt_r_reg[3]_0 (\RD.ar_channel_0_n_11 ),
.\wrap_cnt_r_reg[3]_1 (\RD.ar_channel_0_n_16 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3]_0 ({SI_REG_n_156,SI_REG_n_157}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_0 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_168),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_1 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_3 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice SI_REG
(.D(wrap_cnt),
.E(\aw.aw_pipe/p_1_in ),
.O({SI_REG_n_140,SI_REG_n_141,SI_REG_n_142,SI_REG_n_143}),
.Q({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_26,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[3] ({SI_REG_n_132,SI_REG_n_133,SI_REG_n_134,SI_REG_n_135}),
.\axaddr_incr_reg[7] ({SI_REG_n_136,SI_REG_n_137,SI_REG_n_138,SI_REG_n_139}),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [1:0]}),
.axaddr_offset_0({\cmd_translator_0/wrap_cmd_0/axaddr_offset [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset [1:0]}),
.\axaddr_offset_r_reg[2] (SI_REG_n_154),
.\axaddr_offset_r_reg[2]_0 (SI_REG_n_166),
.\axaddr_offset_r_reg[2]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2]),
.\axaddr_offset_r_reg[2]_2 (\WR.aw_channel_0_n_15 ),
.\axaddr_offset_r_reg[2]_3 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [2]),
.\axaddr_offset_r_reg[2]_4 (\RD.ar_channel_0_n_16 ),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\WR.aw_channel_0_n_10 ),
.\axaddr_offset_r_reg[3]_1 ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [1:0]}),
.\axaddr_offset_r_reg[3]_2 (\RD.ar_channel_0_n_11 ),
.\axlen_cnt_reg[3] (SI_REG_n_8),
.\axlen_cnt_reg[3]_0 (SI_REG_n_64),
.b_push(b_push),
.\cnt_read_reg[2]_rep__0 (SI_REG_n_168),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\cnt_read_reg[4]_rep__0 (\RD.r_channel_0_n_0 ),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 }),
.m_valid_i0(\ar.ar_pipe/m_valid_i0 ),
.m_valid_i_reg(\ar.ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_155),
.next_pending_r_reg_0(SI_REG_n_167),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_82,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.s_ready_i0(\ar.ar_pipe/s_ready_i0 ),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\WR.aw_channel_0_n_4 ),
.\state_reg[0]_rep_0 (\RD.ar_channel_0_n_5 ),
.\state_reg[1] (\aw_cmd_fsm_0/state ),
.\state_reg[1]_0 (\ar_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_0 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_3 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_0 ),
.\state_reg[1]_rep_2 (\RD.ar_channel_0_n_4 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174,SI_REG_n_175}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
.\wrap_cnt_r_reg[2] (SI_REG_n_149),
.\wrap_cnt_r_reg[2]_0 (SI_REG_n_161),
.\wrap_cnt_r_reg[3] (SI_REG_n_153),
.\wrap_cnt_r_reg[3]_0 ({SI_REG_n_156,SI_REG_n_157}),
.\wrap_cnt_r_reg[3]_1 (SI_REG_n_165),
.\wrap_second_len_r_reg[1] (\WR.aw_channel_0_n_9 ),
.\wrap_second_len_r_reg[1]_0 (\RD.ar_channel_0_n_10 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ),
.\wrap_second_len_r_reg[3]_2 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel \WR.aw_channel_0
(.D(wrap_cnt),
.E(\aw.aw_pipe/p_1_in ),
.Q({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_26,si_rs_awsize,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_incr(axaddr_incr),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [1:0]}),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2]),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [1:0]}),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_149),
.\axaddr_offset_r_reg[3]_1 (SI_REG_n_153),
.\axlen_cnt_reg[7] (\WR.aw_channel_0_n_3 ),
.\axlen_cnt_reg[7]_0 (\WR.aw_channel_0_n_4 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[47] (SI_REG_n_8),
.\m_payload_i_reg[47]_0 (SI_REG_n_155),
.\m_payload_i_reg[5] (SI_REG_n_154),
.\m_payload_i_reg[6] ({SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174,SI_REG_n_175}),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0]_rep (\aw_cmd_fsm_0/state ),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_0 ),
.\wrap_cnt_r_reg[3] (\WR.aw_channel_0_n_9 ),
.\wrap_cnt_r_reg[3]_0 (\WR.aw_channel_0_n_10 ),
.\wrap_cnt_r_reg[3]_1 (\WR.aw_channel_0_n_15 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel
(\wrap_boundary_axaddr_r_reg[11] ,
\state_reg[0]_rep ,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_1 ,
m_axi_arvalid,
m_valid_i0,
s_ready_i0,
E,
r_rlast,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
Q,
m_axi_arready,
si_rs_arvalid,
\cnt_read_reg[2]_rep__0 ,
\m_payload_i_reg[47] ,
\axaddr_offset_r_reg[3]_0 ,
axaddr_offset,
\axaddr_offset_r_reg[3]_1 ,
D,
\m_payload_i_reg[47]_0 ,
areset_d1,
\m_payload_i_reg[5] ,
s_axi_arvalid,
s_ready_i_reg,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[6] );
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\state_reg[0]_rep ;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output [2:0]\axaddr_offset_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_1 ;
output m_axi_arvalid;
output m_valid_i0;
output s_ready_i0;
output [0:0]E;
output r_rlast;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input [31:0]Q;
input m_axi_arready;
input si_rs_arvalid;
input \cnt_read_reg[2]_rep__0 ;
input \m_payload_i_reg[47] ;
input \axaddr_offset_r_reg[3]_0 ;
input [2:0]axaddr_offset;
input \axaddr_offset_r_reg[3]_1 ;
input [2:0]D;
input \m_payload_i_reg[47]_0 ;
input areset_d1;
input \m_payload_i_reg[5] ;
input s_axi_arvalid;
input s_ready_i_reg;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input [1:0]\wrap_second_len_r_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6] ;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [31:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_10;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_6;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_3;
wire \cnt_read_reg[2]_rep__0 ;
wire \incr_cmd_0/sel_first ;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[5] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire m_valid_i0;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push_r_reg;
wire r_rlast;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg;
wire sel_first_i;
wire si_rs_arvalid;
wire [1:0]\state_reg[0]_rep ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [2:2]\wrap_cmd_0/axaddr_offset_r ;
wire [0:0]\wrap_cmd_0/wrap_second_len ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [1:0]\wrap_second_len_r_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D(ar_cmd_fsm_0_n_6),
.E(ar_cmd_fsm_0_n_8),
.Q(\state_reg[0]_rep ),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[0] (ar_cmd_fsm_0_n_16),
.axaddr_offset(axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r }),
.\axlen_cnt_reg[7] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[7]_0 (cmd_translator_0_n_3),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[46] (Q[18]),
.\m_payload_i_reg[5] (\m_payload_i_reg[5] ),
.m_valid_i0(m_valid_i0),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq1_reg(cmd_translator_0_n_10),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i0(s_ready_i0),
.s_ready_i_reg(s_ready_i_reg),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_9),
.sel_first_reg_0(ar_cmd_fsm_0_n_10),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(cmd_translator_0_n_0),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\wrap_boundary_axaddr_r_reg[11] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.\wrap_second_len_r_reg[0] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[0]_0 (\wrap_second_len_r_reg[3] [0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 cmd_translator_0
(.D({axaddr_offset[2],\axaddr_offset_r_reg[2] ,axaddr_offset[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q(Q[19:0]),
.S(S),
.aclk(aclk),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r ,\axaddr_offset_r_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[0] (cmd_translator_0_n_3),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(ar_cmd_fsm_0_n_8),
.r_rlast(r_rlast),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_0),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(ar_cmd_fsm_0_n_10),
.sel_first_reg_3(ar_cmd_fsm_0_n_9),
.sel_first_reg_4(ar_cmd_fsm_0_n_16),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (cmd_translator_0_n_10),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0]_0 ),
.\state_reg[1] (\state_reg[0]_rep ),
.\state_reg[1]_0 (ar_cmd_fsm_0_n_0),
.\state_reg[1]_rep (r_push_r_reg),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 ({D,\wrap_cmd_0/wrap_second_len }),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 ,ar_cmd_fsm_0_n_6}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(Q[30]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(Q[31]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[25]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[26]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[27]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(Q[28]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(Q[29]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel
(\wrap_boundary_axaddr_r_reg[11] ,
\state_reg[0]_rep ,
\axlen_cnt_reg[7] ,
\axlen_cnt_reg[7]_0 ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_1 ,
E,
b_push,
m_axi_awvalid,
m_axi_awaddr,
in,
S,
aclk,
Q,
si_rs_awvalid,
\cnt_read_reg[1]_rep__0 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
D,
\axaddr_offset_r_reg[3]_0 ,
axaddr_offset,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[47] ,
\m_payload_i_reg[47]_0 ,
areset_d1,
\m_payload_i_reg[5] ,
axaddr_incr,
\m_payload_i_reg[6] );
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\state_reg[0]_rep ;
output \axlen_cnt_reg[7] ;
output \axlen_cnt_reg[7]_0 ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output [2:0]\axaddr_offset_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_1 ;
output [0:0]E;
output b_push;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [15:0]in;
output [3:0]S;
input aclk;
input [31:0]Q;
input si_rs_awvalid;
input \cnt_read_reg[1]_rep__0 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [1:0]D;
input \axaddr_offset_r_reg[3]_0 ;
input [2:0]axaddr_offset;
input \axaddr_offset_r_reg[3]_1 ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input \m_payload_i_reg[47] ;
input \m_payload_i_reg[47]_0 ;
input areset_d1;
input \m_payload_i_reg[5] ;
input [11:0]axaddr_incr;
input [6:0]\m_payload_i_reg[6] ;
wire [1:0]D;
wire [0:0]E;
wire [31:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_12;
wire aw_cmd_fsm_0_n_14;
wire aw_cmd_fsm_0_n_15;
wire aw_cmd_fsm_0_n_16;
wire aw_cmd_fsm_0_n_2;
wire aw_cmd_fsm_0_n_8;
wire aw_cmd_fsm_0_n_9;
wire [11:0]axaddr_incr;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire \incr_cmd_0/sel_first ;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[5] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire sel_first;
wire sel_first_i;
wire si_rs_awvalid;
wire [1:0]\state_reg[0]_rep ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [2:2]\wrap_cmd_0/axaddr_offset_r ;
wire [0:0]\wrap_cmd_0/wrap_second_len ;
wire [0:0]wrap_cnt;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D(wrap_cnt),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(\state_reg[0]_rep ),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset(axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r }),
.\axaddr_wrap_reg[11] (aw_cmd_fsm_0_n_14),
.\axlen_cnt_reg[0] (aw_cmd_fsm_0_n_8),
.\axlen_cnt_reg[0]_0 (cmd_translator_0_n_5),
.\axlen_cnt_reg[7] (\axlen_cnt_reg[7] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7]_0 ),
.\axlen_cnt_reg[7]_1 (aw_cmd_fsm_0_n_2),
.\axlen_cnt_reg[7]_2 (cmd_translator_0_n_6),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[46] ({Q[18],Q[16:15]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[5] (\m_payload_i_reg[5] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_9),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_12),
.s_axburst_eq1_reg_0(cmd_translator_0_n_12),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_15),
.sel_first_reg_0(aw_cmd_fsm_0_n_16),
.sel_first_reg_1(cmd_translator_0_n_2),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[0] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[0]_0 (\wrap_second_len_r_reg[3] [0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator cmd_translator_0
(.D({axaddr_offset[2],\axaddr_offset_r_reg[2] ,axaddr_offset[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(cmd_translator_0_n_5),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r ,\axaddr_offset_r_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[2] (cmd_translator_0_n_6),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_9),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_12),
.\m_payload_i_reg[47] (Q[19:0]),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_1 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_16),
.sel_first_reg_2(aw_cmd_fsm_0_n_15),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (aw_cmd_fsm_0_n_14),
.\state_reg[0]_rep (aw_cmd_fsm_0_n_2),
.\state_reg[1] (\state_reg[0]_rep ),
.\state_reg[1]_0 (aw_cmd_fsm_0_n_8),
.\state_reg[1]_rep (cmd_translator_0_n_12),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 ({D,wrap_cnt}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 ,\wrap_cmd_0/wrap_second_len }));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(Q[30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(Q[31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(in[7]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(Q[28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(Q[29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[19]),
.Q(in[3]),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__0 ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__0 ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [15:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_5;
wire \bresp_cnt[7]_i_6_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_3),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bresp_push(bresp_push),
.bvalid_i_reg(bid_fifo_0_n_5),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_6_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_6_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_6
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_6_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_3),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_5),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACEAAAA))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(m_axi_bresp[0]),
.I2(m_axi_bresp[1]),
.I3(\s_bresp_acc_reg_n_0_[1] ),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EC))
\s_bresp_acc[1]_i_1
(.I0(m_axi_bresp[1]),
.I1(\s_bresp_acc_reg_n_0_[1] ),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator
(next_pending_r_reg,
wrap_next_pending,
sel_first_reg_0,
sel_first_0,
sel_first,
Q,
\axlen_cnt_reg[2] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\state_reg[1]_rep ,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
S,
incr_next_pending,
aclk,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
sel_first_reg_2,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_awvalid,
\axaddr_offset_r_reg[3]_0 ,
D,
\m_payload_i_reg[47]_0 ,
\m_payload_i_reg[47]_1 ,
next,
axaddr_incr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[0] ,
\state_reg[1]_0 ,
\state_reg[0]_rep ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output next_pending_r_reg;
output wrap_next_pending;
output sel_first_reg_0;
output sel_first_0;
output sel_first;
output [0:0]Q;
output \axlen_cnt_reg[2] ;
output \wrap_cnt_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \state_reg[1]_rep ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input sel_first_reg_2;
input [0:0]E;
input [19:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_awvalid;
input \axaddr_offset_r_reg[3]_0 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input \m_payload_i_reg[47]_1 ;
input next;
input [11:0]axaddr_incr;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [0:0]\state_reg[1]_0 ;
input \state_reg[0]_rep ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[2] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [19:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[47]_1 ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire [0:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \wrap_cnt_r_reg[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd incr_cmd_0
(.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[0]_0 (sel_first_0),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.\axlen_cnt_reg[2]_0 (\axlen_cnt_reg[2] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[11] (incr_cmd_0_n_15),
.\m_axi_awaddr[5] (incr_cmd_0_n_16),
.\m_payload_i_reg[46] ({\m_payload_i_reg[47] [18:17],\m_payload_i_reg[47] [14:12],\m_payload_i_reg[47] [5],\m_payload_i_reg[47] [3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1]_0 ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[47] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[1]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd wrap_cmd_0
(.D(D),
.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[47] ({\m_payload_i_reg[47] [19:15],\m_payload_i_reg[47] [13:0]}),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_1 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.sel_first_reg_0(sel_first),
.sel_first_reg_1(sel_first_reg_2),
.sel_first_reg_2(incr_cmd_0_n_15),
.sel_first_reg_3(incr_cmd_0_n_16),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_1 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_0 ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1
(sel_first_reg_0,
sel_first,
sel_first_reg_1,
\axlen_cnt_reg[0] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\axaddr_offset_r_reg[3] ,
S,
aclk,
sel_first_i,
sel_first_reg_2,
sel_first_reg_3,
E,
Q,
\state_reg[1] ,
si_rs_arvalid,
\m_payload_i_reg[47] ,
\axaddr_offset_r_reg[3]_0 ,
D,
\m_payload_i_reg[47]_0 ,
\state_reg[1]_rep ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
\state_reg[0]_rep_0 ,
\axaddr_offset_r_reg[3]_1 ,
m_valid_i_reg,
\state_reg[1]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
sel_first_reg_4,
m_axi_arready);
output sel_first_reg_0;
output sel_first;
output sel_first_reg_1;
output \axlen_cnt_reg[0] ;
output \wrap_cnt_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input aclk;
input sel_first_i;
input sel_first_reg_2;
input sel_first_reg_3;
input [0:0]E;
input [19:0]Q;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input \m_payload_i_reg[47] ;
input \axaddr_offset_r_reg[3]_0 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input \state_reg[1]_rep ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input \state_reg[0]_rep_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input \state_reg[1]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [0:0]sel_first_reg_4;
input m_axi_arready;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [19:0]Q;
wire [3:0]S;
wire aclk;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[0] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_3;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire [0:0]sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire wrap_cmd_0_n_6;
wire wrap_cmd_0_n_7;
wire \wrap_cnt_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 incr_cmd_0
(.E(E),
.O(O),
.Q({Q[18:16],Q[14:12],Q[5],Q[3:0]}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[0]_0 (sel_first),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10}),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[11] (incr_cmd_0_n_11),
.\m_axi_araddr[1] (incr_cmd_0_n_15),
.\m_axi_araddr[2] (incr_cmd_0_n_14),
.\m_axi_araddr[3] (incr_cmd_0_n_13),
.\m_axi_araddr[5] (incr_cmd_0_n_12),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_4),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_0 (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(Q[15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_6),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_7),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(Q[15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 wrap_cmd_0
(.D(D),
.E(E),
.Q({Q[19:15],Q[13:0]}),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.s_axburst_eq0_reg(wrap_cmd_0_n_6),
.s_axburst_eq1_reg(wrap_cmd_0_n_7),
.sel_first_i(sel_first_i),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_11),
.sel_first_reg_3(incr_cmd_0_n_12),
.sel_first_reg_4(incr_cmd_0_n_13),
.sel_first_reg_5(incr_cmd_0_n_14),
.sel_first_reg_6(incr_cmd_0_n_15),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[0]_0 ,
Q,
\axlen_cnt_reg[2]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_awaddr[11] ,
\m_axi_awaddr[5] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
E,
\m_payload_i_reg[46] ,
\m_payload_i_reg[47] ,
next,
axaddr_incr,
\state_reg[0] ,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output \axaddr_incr_reg[0]_0 ;
output [0:0]Q;
output \axlen_cnt_reg[2]_0 ;
output [10:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_awaddr[11] ;
output \m_axi_awaddr[5] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [0:0]E;
input [9:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[47] ;
input next;
input [11:0]axaddr_incr;
input [0:0]\state_reg[0] ;
input [0:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]E;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire \axaddr_incr[0]_i_1_n_0 ;
wire \axaddr_incr[10]_i_1_n_0 ;
wire \axaddr_incr[11]_i_1_n_0 ;
wire \axaddr_incr[11]_i_2_n_0 ;
wire \axaddr_incr[1]_i_1_n_0 ;
wire \axaddr_incr[2]_i_1_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1_n_0 ;
wire \axaddr_incr[4]_i_1_n_0 ;
wire \axaddr_incr[5]_i_1_n_0 ;
wire \axaddr_incr[6]_i_1_n_0 ;
wire \axaddr_incr[7]_i_1_n_0 ;
wire \axaddr_incr[8]_i_1_n_0 ;
wire \axaddr_incr[9]_i_1_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [10:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4_n_1 ;
wire \axaddr_incr_reg[11]_i_4_n_2 ;
wire \axaddr_incr_reg[11]_i_4_n_3 ;
wire \axaddr_incr_reg[11]_i_4_n_4 ;
wire \axaddr_incr_reg[11]_i_4_n_5 ;
wire \axaddr_incr_reg[11]_i_4_n_6 ;
wire \axaddr_incr_reg[11]_i_4_n_7 ;
wire \axaddr_incr_reg[3]_i_3_n_0 ;
wire \axaddr_incr_reg[3]_i_3_n_1 ;
wire \axaddr_incr_reg[3]_i_3_n_2 ;
wire \axaddr_incr_reg[3]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_3_n_4 ;
wire \axaddr_incr_reg[3]_i_3_n_5 ;
wire \axaddr_incr_reg[3]_i_3_n_6 ;
wire \axaddr_incr_reg[3]_i_3_n_7 ;
wire \axaddr_incr_reg[7]_i_3_n_0 ;
wire \axaddr_incr_reg[7]_i_3_n_1 ;
wire \axaddr_incr_reg[7]_i_3_n_2 ;
wire \axaddr_incr_reg[7]_i_3_n_3 ;
wire \axaddr_incr_reg[7]_i_3_n_4 ;
wire \axaddr_incr_reg[7]_i_3_n_5 ;
wire \axaddr_incr_reg[7]_i_3_n_6 ;
wire \axaddr_incr_reg[7]_i_3_n_7 ;
wire \axaddr_incr_reg_n_0_[5] ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1_n_0 ;
wire \axlen_cnt[3]_i_2_n_0 ;
wire \axlen_cnt[4]_i_1_n_0 ;
wire \axlen_cnt[5]_i_1_n_0 ;
wire \axlen_cnt[6]_i_1_n_0 ;
wire \axlen_cnt[7]_i_2_n_0 ;
wire \axlen_cnt[7]_i_3_n_0 ;
wire \axlen_cnt_reg[2]_0 ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[11] ;
wire \m_axi_awaddr[5] ;
wire [9:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire next;
wire next_pending_r_i_5_n_0;
wire next_pending_r_reg_0;
wire sel_first_reg_0;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire [0:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1
(.I0(axaddr_incr[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_7 ),
.O(\axaddr_incr[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1
(.I0(axaddr_incr[10]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_5 ),
.O(\axaddr_incr[10]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\axaddr_incr[11]_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(next),
.O(\axaddr_incr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2
(.I0(axaddr_incr[11]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_4 ),
.O(\axaddr_incr[11]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1
(.I0(axaddr_incr[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_6 ),
.O(\axaddr_incr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1
(.I0(axaddr_incr[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_5 ),
.O(\axaddr_incr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1
(.I0(axaddr_incr[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_4 ),
.O(\axaddr_incr[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0102))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg[11]_0 [3]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg[11]_0 [2]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg[11]_0 [1]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_14_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[3]));
LUT4 #(
.INIT(16'h262A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[2]));
LUT4 #(
.INIT(16'h060A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.I3(next),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1
(.I0(axaddr_incr[4]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_7 ),
.O(\axaddr_incr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1
(.I0(axaddr_incr[5]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_6 ),
.O(\axaddr_incr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1
(.I0(axaddr_incr[6]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_5 ),
.O(\axaddr_incr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1
(.I0(axaddr_incr[7]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_4 ),
.O(\axaddr_incr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1
(.I0(axaddr_incr[8]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_7 ),
.O(\axaddr_incr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1
(.I0(axaddr_incr[9]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_6 ),
.O(\axaddr_incr[9]_i_1_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[0]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[10]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [9]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[11]_i_2_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [10]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4
(.CI(\axaddr_incr_reg[7]_i_3_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4_n_1 ,\axaddr_incr_reg[11]_i_4_n_2 ,\axaddr_incr_reg[11]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4_n_4 ,\axaddr_incr_reg[11]_i_4_n_5 ,\axaddr_incr_reg[11]_i_4_n_6 ,\axaddr_incr_reg[11]_i_4_n_7 }),
.S(\axaddr_incr_reg[11]_0 [10:7]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[1]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[2]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[3]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3_n_0 ,\axaddr_incr_reg[3]_i_3_n_1 ,\axaddr_incr_reg[3]_i_3_n_2 ,\axaddr_incr_reg[3]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(\axaddr_incr_reg[11]_0 [3:0]),
.O({\axaddr_incr_reg[3]_i_3_n_4 ,\axaddr_incr_reg[3]_i_3_n_5 ,\axaddr_incr_reg[3]_i_3_n_6 ,\axaddr_incr_reg[3]_i_3_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[4]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[5]_i_1_n_0 ),
.Q(\axaddr_incr_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[6]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[7]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3
(.CI(\axaddr_incr_reg[3]_i_3_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3_n_0 ,\axaddr_incr_reg[7]_i_3_n_1 ,\axaddr_incr_reg[7]_i_3_n_2 ,\axaddr_incr_reg[7]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3_n_4 ,\axaddr_incr_reg[7]_i_3_n_5 ,\axaddr_incr_reg[7]_i_3_n_6 ,\axaddr_incr_reg[7]_i_3_n_7 }),
.S({\axaddr_incr_reg[11]_0 [6:5],\axaddr_incr_reg_n_0_[5] ,\axaddr_incr_reg[11]_0 [4]}));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[8]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[9]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [8]),
.R(1'b0));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[46] [8]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg[2]_0 ),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[2]_i_1
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(Q),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg[2]_0 ),
.I4(E),
.I5(\m_payload_i_reg[46] [9]),
.O(\axlen_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEBAAAAAAAA))
\axlen_cnt[3]_i_2
(.I0(\m_payload_i_reg[47] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(Q),
.I5(\axlen_cnt_reg[2]_0 ),
.O(\axlen_cnt[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(Q),
.O(\axlen_cnt[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[7]_i_3_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\state_reg[1] ),
.Q(Q),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[5]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[6]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[7]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[0]_rep ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT2 #(
.INIT(4'hB))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[46] [7]),
.O(\m_axi_awaddr[11] ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[5] ),
.I2(\m_payload_i_reg[46] [7]),
.I3(\m_payload_i_reg[46] [4]),
.O(\m_axi_awaddr[5] ));
LUT5 #(
.INIT(32'h55545555))
next_pending_r_i_3__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.I4(next_pending_r_i_5_n_0),
.O(\axlen_cnt_reg[2]_0 ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_5
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_i_5_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2
(incr_next_pending,
\axaddr_incr_reg[0]_0 ,
\axlen_cnt_reg[0]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_araddr[11] ,
\m_axi_araddr[5] ,
\m_axi_araddr[3] ,
\m_axi_araddr[2] ,
\m_axi_araddr[1] ,
S,
aclk,
sel_first_reg_0,
E,
Q,
\m_payload_i_reg[47] ,
\state_reg[1]_rep ,
\m_payload_i_reg[47]_0 ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
si_rs_arvalid,
\state_reg[0]_rep ,
m_valid_i_reg,
\state_reg[1] ,
sel_first_reg_1,
\state_reg[1]_0 ,
m_axi_arready);
output incr_next_pending;
output \axaddr_incr_reg[0]_0 ;
output \axlen_cnt_reg[0]_0 ;
output [7:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_araddr[11] ;
output \m_axi_araddr[5] ;
output \m_axi_araddr[3] ;
output \m_axi_araddr[2] ;
output \m_axi_araddr[1] ;
output [3:0]S;
input aclk;
input sel_first_reg_0;
input [0:0]E;
input [10:0]Q;
input \m_payload_i_reg[47] ;
input \state_reg[1]_rep ;
input \m_payload_i_reg[47]_0 ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input si_rs_arvalid;
input \state_reg[0]_rep ;
input [0:0]m_valid_i_reg;
input \state_reg[1] ;
input [0:0]sel_first_reg_1;
input [1:0]\state_reg[1]_0 ;
input m_axi_arready;
wire [0:0]E;
wire [3:0]O;
wire [10:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[0]_i_1__0_n_0 ;
wire \axaddr_incr[10]_i_1__0_n_0 ;
wire \axaddr_incr[11]_i_2__0_n_0 ;
wire \axaddr_incr[1]_i_1__0_n_0 ;
wire \axaddr_incr[2]_i_1__0_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1__0_n_0 ;
wire \axaddr_incr[4]_i_1__0_n_0 ;
wire \axaddr_incr[5]_i_1__0_n_0 ;
wire \axaddr_incr[6]_i_1__0_n_0 ;
wire \axaddr_incr[7]_i_1__0_n_0 ;
wire \axaddr_incr[8]_i_1__0_n_0 ;
wire \axaddr_incr[9]_i_1__0_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [7:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4__0_n_1 ;
wire \axaddr_incr_reg[11]_i_4__0_n_2 ;
wire \axaddr_incr_reg[11]_i_4__0_n_3 ;
wire \axaddr_incr_reg[11]_i_4__0_n_4 ;
wire \axaddr_incr_reg[11]_i_4__0_n_5 ;
wire \axaddr_incr_reg[11]_i_4__0_n_6 ;
wire \axaddr_incr_reg[11]_i_4__0_n_7 ;
wire \axaddr_incr_reg[3]_i_3__0_n_0 ;
wire \axaddr_incr_reg[3]_i_3__0_n_1 ;
wire \axaddr_incr_reg[3]_i_3__0_n_2 ;
wire \axaddr_incr_reg[3]_i_3__0_n_3 ;
wire \axaddr_incr_reg[3]_i_3__0_n_4 ;
wire \axaddr_incr_reg[3]_i_3__0_n_5 ;
wire \axaddr_incr_reg[3]_i_3__0_n_6 ;
wire \axaddr_incr_reg[3]_i_3__0_n_7 ;
wire \axaddr_incr_reg[7]_i_3__0_n_0 ;
wire \axaddr_incr_reg[7]_i_3__0_n_1 ;
wire \axaddr_incr_reg[7]_i_3__0_n_2 ;
wire \axaddr_incr_reg[7]_i_3__0_n_3 ;
wire \axaddr_incr_reg[7]_i_3__0_n_4 ;
wire \axaddr_incr_reg[7]_i_3__0_n_5 ;
wire \axaddr_incr_reg[7]_i_3__0_n_6 ;
wire \axaddr_incr_reg[7]_i_3__0_n_7 ;
wire \axaddr_incr_reg_n_0_[1] ;
wire \axaddr_incr_reg_n_0_[2] ;
wire \axaddr_incr_reg_n_0_[3] ;
wire \axaddr_incr_reg_n_0_[5] ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__1_n_0 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2__0_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[11] ;
wire \m_axi_araddr[1] ;
wire \m_axi_araddr[2] ;
wire \m_axi_araddr[3] ;
wire \m_axi_araddr[5] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__0_n_0;
wire next_pending_r_i_4__0_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire [0:0]sel_first_reg_1;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_7 ),
.O(\axaddr_incr[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1__0
(.I0(O[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_5 ),
.O(\axaddr_incr[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2__0
(.I0(O[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_4 ),
.O(\axaddr_incr[11]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_6 ),
.O(\axaddr_incr[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_5 ),
.O(\axaddr_incr[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[3]_i_10
(.I0(Q[0]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg_n_0_[3] ),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg_n_0_[2] ),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg_n_0_[1] ),
.I1(Q[6]),
.I2(Q[5]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_4 ),
.O(\axaddr_incr[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[3]_i_7
(.I0(Q[3]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[3]_i_8
(.I0(Q[2]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[3]_i_9
(.I0(Q[1]),
.I1(Q[5]),
.I2(Q[6]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1__0
(.I0(\m_payload_i_reg[7] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_7 ),
.O(\axaddr_incr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1__0
(.I0(\m_payload_i_reg[7] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_6 ),
.O(\axaddr_incr[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1__0
(.I0(\m_payload_i_reg[7] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_5 ),
.O(\axaddr_incr[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1__0
(.I0(\m_payload_i_reg[7] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_4 ),
.O(\axaddr_incr[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1__0
(.I0(O[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_7 ),
.O(\axaddr_incr[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1__0
(.I0(O[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_6 ),
.O(\axaddr_incr[9]_i_1__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[0]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[10]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[11]_i_2__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4__0
(.CI(\axaddr_incr_reg[7]_i_3__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4__0_n_1 ,\axaddr_incr_reg[11]_i_4__0_n_2 ,\axaddr_incr_reg[11]_i_4__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4__0_n_4 ,\axaddr_incr_reg[11]_i_4__0_n_5 ,\axaddr_incr_reg[11]_i_4__0_n_6 ,\axaddr_incr_reg[11]_i_4__0_n_7 }),
.S(\axaddr_incr_reg[11]_0 [7:4]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[1]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[2]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[3]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3__0_n_0 ,\axaddr_incr_reg[3]_i_3__0_n_1 ,\axaddr_incr_reg[3]_i_3__0_n_2 ,\axaddr_incr_reg[3]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr_reg_n_0_[3] ,\axaddr_incr_reg_n_0_[2] ,\axaddr_incr_reg_n_0_[1] ,\axaddr_incr_reg[11]_0 [0]}),
.O({\axaddr_incr_reg[3]_i_3__0_n_4 ,\axaddr_incr_reg[3]_i_3__0_n_5 ,\axaddr_incr_reg[3]_i_3__0_n_6 ,\axaddr_incr_reg[3]_i_3__0_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[4]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[5]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[6]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[7]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3__0
(.CI(\axaddr_incr_reg[3]_i_3__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3__0_n_0 ,\axaddr_incr_reg[7]_i_3__0_n_1 ,\axaddr_incr_reg[7]_i_3__0_n_2 ,\axaddr_incr_reg[7]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3__0_n_4 ,\axaddr_incr_reg[7]_i_3__0_n_5 ,\axaddr_incr_reg[7]_i_3__0_n_6 ,\axaddr_incr_reg[7]_i_3__0_n_7 }),
.S({\axaddr_incr_reg[11]_0 [3:2],\axaddr_incr_reg_n_0_[5] ,\axaddr_incr_reg[11]_0 [1]}));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[8]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[9]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
LUT5 #(
.INIT(32'h20FF2020))
\axlen_cnt[0]_i_1__2
(.I0(si_rs_arvalid),
.I1(\state_reg[0]_rep ),
.I2(Q[8]),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(Q[9]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[2]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg[0]_0 ),
.I4(E),
.I5(Q[10]),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEBAAAAAAAA))
\axlen_cnt[3]_i_2__0
(.I0(\m_payload_i_reg[47] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[3]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h55545555))
\axlen_cnt[3]_i_4
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.I4(next_pending_r_i_4__0_n_0),
.O(\axlen_cnt_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hB))
\m_axi_araddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(Q[7]),
.O(\m_axi_araddr[11] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[1]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[1] ),
.I2(Q[7]),
.I3(Q[1]),
.O(\m_axi_araddr[1] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[2] ),
.I2(Q[7]),
.I3(Q[2]),
.O(\m_axi_araddr[2] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[3]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[3] ),
.I2(Q[7]),
.I3(Q[3]),
.O(\m_axi_araddr[3] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[5] ),
.I2(Q[7]),
.I3(Q[4]),
.O(\m_axi_araddr[5] ));
LUT5 #(
.INIT(32'hFFFF505C))
next_pending_r_i_1__2
(.I0(next_pending_r_i_2__0_n_0),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(E),
.I4(\m_payload_i_reg[47]_0 ),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0002))
next_pending_r_i_2__0
(.I0(next_pending_r_i_4__0_n_0),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_2__0_n_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_4__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(next_pending_r_i_4__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel
(m_valid_i_reg,
\state_reg[1]_rep ,
m_axi_rready,
out,
\skid_buffer_reg[46] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output m_axi_rready;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_1;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_4;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [12:0]trans_in;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[4]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_1),
.\cnt_read_reg[4]_rep__2_2 (rd_data_fifo_0_n_2),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_4));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__3 (rd_data_fifo_0_n_2),
.\cnt_read_reg[0]_rep__3_0 (rd_data_fifo_0_n_4),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (rd_data_fifo_0_n_1),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm
(\axlen_cnt_reg[7] ,
Q,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
D,
\wrap_second_len_r_reg[0] ,
E,
sel_first_reg,
sel_first_reg_0,
sel_first_i,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[11] ,
\axaddr_incr_reg[0] ,
m_axi_arvalid,
m_valid_i0,
s_ready_i0,
\m_payload_i_reg[0]_1 ,
m_axi_arready,
si_rs_arvalid,
\axlen_cnt_reg[7]_0 ,
s_axburst_eq1_reg,
\cnt_read_reg[2]_rep__0 ,
\wrap_second_len_r_reg[0]_0 ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
sel_first_reg_1,
areset_d1,
sel_first,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[46] ,
\m_payload_i_reg[5] ,
s_axi_arvalid,
s_ready_i_reg,
aclk);
output \axlen_cnt_reg[7] ;
output [1:0]Q;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[0] ;
output [0:0]E;
output sel_first_reg;
output sel_first_reg_0;
output sel_first_i;
output \wrap_cnt_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_0 ;
output [0:0]\wrap_boundary_axaddr_r_reg[11] ;
output [0:0]\axaddr_incr_reg[0] ;
output m_axi_arvalid;
output m_valid_i0;
output s_ready_i0;
output [0:0]\m_payload_i_reg[0]_1 ;
input m_axi_arready;
input si_rs_arvalid;
input \axlen_cnt_reg[7]_0 ;
input s_axburst_eq1_reg;
input \cnt_read_reg[2]_rep__0 ;
input [0:0]\wrap_second_len_r_reg[0]_0 ;
input \axaddr_offset_r_reg[3] ;
input [0:0]axaddr_offset;
input sel_first_reg_1;
input areset_d1;
input sel_first;
input sel_first_reg_2;
input [1:0]\axaddr_offset_r_reg[3]_0 ;
input [0:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[5] ;
input s_axi_arvalid;
input s_ready_i_reg;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]\axaddr_incr_reg[0] ;
wire [0:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [1:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire \cnt_read_reg[2]_rep__0 ;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire [0:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[5] ;
wire m_valid_i0;
wire [1:0]next_state__0;
wire r_push_r_reg;
wire s_axburst_eq1_reg;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg;
wire sel_first;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire [0:0]\wrap_boundary_axaddr_r_reg[11] ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire [0:0]\wrap_second_len_r_reg[0] ;
wire [0:0]\wrap_second_len_r_reg[0]_0 ;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[11]_i_1__0
(.I0(sel_first),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[0] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[5] ),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[3]_i_1__2
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(Q[0]),
.I3(Q[1]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00005140))
\axlen_cnt[7]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(m_axi_arready),
.I3(si_rs_arvalid),
.I4(\axlen_cnt_reg[7]_0 ),
.O(\axlen_cnt_reg[7] ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__1
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(m_valid_i0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(m_axi_arready),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h8FFF8F8F))
s_ready_i_i_1__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(s_ready_i0));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__2
(.I0(m_axi_arready),
.I1(sel_first_reg_1),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first),
.I2(\m_payload_i_reg[0] ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0]_0 ),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__4
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\m_payload_i_reg[0]_0 ),
.I4(m_axi_arready),
.I5(sel_first_reg_2),
.O(sel_first_i));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg),
.I5(\cnt_read_reg[2]_rep__0 ),
.O(next_state__0[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1
(.I0(\cnt_read_reg[2]_rep__0 ),
.I1(s_axburst_eq1_reg),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(\m_payload_i_reg[0] ),
.O(next_state__0[1]));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state__0[0]),
.Q(Q[0]),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state__0[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state__0[1]),
.Q(Q[1]),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state__0[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(\wrap_boundary_axaddr_r_reg[11] ));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_4__0
(.I0(\axaddr_offset_r_reg[3]_0 [1]),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(\m_payload_i_reg[0] ),
.O(\wrap_cnt_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_6__0
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(\m_payload_i_reg[0] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(\wrap_second_len_r_reg[0] ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__0_0 ,
SR,
D,
bresp_push,
bvalid_i_reg,
out,
b_push,
shandshake_r,
areset_d1,
Q,
\bresp_cnt_reg[7] ,
mhandshake_r,
si_rs_bready,
bvalid_i_reg_0,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__0_0 ;
output [0:0]SR;
output [0:0]D;
output bresp_push;
output bvalid_i_reg;
output [11:0]out;
input b_push;
input shandshake_r;
input areset_d1;
input [1:0]Q;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input si_rs_bready;
input bvalid_i_reg_0;
input [15:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire \bresp_cnt[7]_i_3_n_0 ;
wire \bresp_cnt[7]_i_4_n_0 ;
wire \bresp_cnt[7]_i_5_n_0 ;
wire [7:0]\bresp_cnt_reg[7] ;
wire bresp_push;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [15:0]in;
wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire shandshake_r;
wire si_rs_bready;
LUT4 #(
.INIT(16'hABAA))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(\bresp_cnt[7]_i_4_n_0 ),
.I3(\bresp_cnt[7]_i_5_n_0 ),
.O(SR));
LUT6 #(
.INIT(64'hEEFEFFFFFFFFEEFE))
\bresp_cnt[7]_i_3
(.I0(\bresp_cnt_reg[7] [7]),
.I1(\bresp_cnt_reg[7] [6]),
.I2(\bresp_cnt_reg[7] [0]),
.I3(\memory_reg[3][0]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFFF6FFFF))
\bresp_cnt[7]_i_4
(.I0(\bresp_cnt_reg[7] [1]),
.I1(\memory_reg[3][1]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [4]),
.I3(\bresp_cnt_reg[7] [5]),
.I4(mhandshake_r),
.O(\bresp_cnt[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000D00DD00DD00D))
\bresp_cnt[7]_i_5
(.I0(\memory_reg[3][0]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [0]),
.I2(\bresp_cnt_reg[7] [2]),
.I3(\memory_reg[3][2]_srl4_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_0 ),
.I5(\cnt_read_reg[0]_rep__0_0 ),
.O(\bresp_cnt[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'h0444))
bvalid_i_i_1
(.I0(areset_d1),
.I1(bvalid_i_i_2_n_0),
.I2(si_rs_bready),
.I3(bvalid_i_reg_0),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1
(.I0(bresp_push),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
LUT6 #(
.INIT(64'h0000000041004141))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [2]),
.I3(\bresp_cnt_reg[7] [0]),
.I4(\memory_reg[3][0]_srl4_n_0 ),
.I5(\memory_reg[3][0]_srl4_i_3_n_0 ),
.O(bresp_push));
LUT2 #(
.INIT(4'h8))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFBFFFFFFFFFFFB))
\memory_reg[3][0]_srl4_i_3
(.I0(\bresp_cnt[7]_i_3_n_0 ),
.I1(mhandshake_r),
.I2(\bresp_cnt_reg[7] [5]),
.I3(\bresp_cnt_reg[7] [4]),
.I4(\memory_reg[3][1]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [1]),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(out[1]));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0
(Q,
mhandshake,
m_axi_bready,
\skid_buffer_reg[1] ,
shandshake_r,
sel,
m_axi_bvalid,
mhandshake_r,
in,
aclk,
areset_d1,
D);
output [1:0]Q;
output mhandshake;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input shandshake_r;
input sel;
input m_axi_bvalid;
input mhandshake_r;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(shandshake_r),
.I3(sel),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1
(\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
\cnt_read_reg[4]_rep__2_2 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
\cnt_read_reg[4]_rep__0_0 ,
si_rs_rready,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output \cnt_read_reg[4]_rep__2_2 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input \cnt_read_reg[4]_rep__0_0 ;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read[4]_i_5_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep__3_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep__2_2 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT3 #(
.INIT(8'h69))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h9AA6))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(s_ready_i_reg),
.I3(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hA9AAAA6A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[0]_rep__2_n_0 ),
.I3(\cnt_read[4]_i_5_n_0 ),
.I4(s_ready_i_reg),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAA6AA9AAAAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read[4]_i_5_n_0 ),
.I4(s_ready_i_reg),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h99AA99AA99AA55A6))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_1 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_2 ),
.I3(\cnt_read[4]_i_3__0_n_0 ),
.I4(s_ready_i_reg),
.I5(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'h7F))
\cnt_read[4]_i_2__0
(.I0(\cnt_read_reg[0]_rep__3_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_2 ));
LUT6 #(
.INIT(64'h0000000000100000))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read[4]_i_5_n_0 ),
.I3(\cnt_read_reg[4]_rep__0_0 ),
.I4(si_rs_rready),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h6000E000FFFFFFFF))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[0]_rep__3_n_0 ),
.I5(m_axi_rvalid),
.O(\cnt_read[4]_i_5_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__3
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__3_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_1 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h9FFF1FFF))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[0]_rep__3_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'h8AAA0AAA0AAAAAAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[0]_rep__3_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_0 ),
.I3(\cnt_read_reg[4]_rep__2_1 ),
.I4(\cnt_read_reg[1]_rep__2_n_0 ),
.I5(\cnt_read_reg[2]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h40C0C000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__3_n_0 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\state_reg[1]_rep ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2
(m_valid_i_reg,
\state_reg[1]_rep ,
\skid_buffer_reg[46] ,
s_ready_i_reg,
r_push_r,
si_rs_rready,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[4]_rep__2 ,
\cnt_read_reg[0]_rep__3 ,
\cnt_read_reg[0]_rep__3_0 ,
in,
aclk,
areset_d1);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output [12:0]\skid_buffer_reg[46] ;
input s_ready_i_reg;
input r_push_r;
input si_rs_rready;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[4]_rep__2 ;
input \cnt_read_reg[0]_rep__3 ;
input \cnt_read_reg[0]_rep__3_0 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__3 ;
wire \cnt_read_reg[0]_rep__3_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_i_3_n_0;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(r_push_r),
.I2(s_ready_i_reg),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hDB24))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFF7F0080FEFF0100))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h9A999AAA))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read_reg[2]_rep__0_n_0 ),
.I3(\cnt_read_reg[3]_rep__0_n_0 ),
.I4(\cnt_read[4]_i_3_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h2AAAAAAA2AAA2AAA))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__1_n_0 ),
.I3(r_push_r),
.I4(m_valid_i_reg),
.I5(si_rs_rready),
.O(\cnt_read[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000004))
\cnt_read[4]_i_3
(.I0(r_push_r),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(\cnt_read_reg[0]_rep__1_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[4]_i_3_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'h80808080FF808080))
m_valid_i_i_2
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read_reg[3]_rep__0_n_0 ),
.I2(m_valid_i_i_3_n_0),
.I3(\cnt_read_reg[3]_rep__2 ),
.I4(\cnt_read_reg[4]_rep__2 ),
.I5(\cnt_read_reg[0]_rep__3 ),
.O(m_valid_i_reg));
LUT3 #(
.INIT(8'h80))
m_valid_i_i_3
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__1_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.O(m_valid_i_i_3_n_0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBFEEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__3_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__1_n_0 ),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[4]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm
(\axlen_cnt_reg[7] ,
\axlen_cnt_reg[7]_0 ,
\axlen_cnt_reg[7]_1 ,
next,
Q,
D,
\wrap_second_len_r_reg[0] ,
\axlen_cnt_reg[0] ,
s_axburst_eq0_reg,
incr_next_pending,
sel_first_i,
s_axburst_eq1_reg,
E,
\axaddr_wrap_reg[11] ,
sel_first_reg,
sel_first_reg_0,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_0 ,
\m_payload_i_reg[0] ,
b_push,
m_axi_awvalid,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__0 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
si_rs_awvalid,
\axlen_cnt_reg[7]_2 ,
\wrap_second_len_r_reg[0]_0 ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
\m_payload_i_reg[46] ,
\axlen_cnt_reg[0]_0 ,
wrap_next_pending,
next_pending_r_reg,
\m_payload_i_reg[47] ,
sel_first,
areset_d1,
sel_first_0,
sel_first_reg_1,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[5] ,
aclk);
output \axlen_cnt_reg[7] ;
output \axlen_cnt_reg[7]_0 ;
output \axlen_cnt_reg[7]_1 ;
output next;
output [1:0]Q;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[0] ;
output [0:0]\axlen_cnt_reg[0] ;
output s_axburst_eq0_reg;
output incr_next_pending;
output sel_first_i;
output s_axburst_eq1_reg;
output [0:0]E;
output [0:0]\axaddr_wrap_reg[11] ;
output sel_first_reg;
output sel_first_reg_0;
output \wrap_cnt_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_0 ;
output [0:0]\m_payload_i_reg[0] ;
output b_push;
output m_axi_awvalid;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__0 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input si_rs_awvalid;
input \axlen_cnt_reg[7]_2 ;
input [0:0]\wrap_second_len_r_reg[0]_0 ;
input \axaddr_offset_r_reg[3] ;
input [0:0]axaddr_offset;
input [2:0]\m_payload_i_reg[46] ;
input [0:0]\axlen_cnt_reg[0]_0 ;
input wrap_next_pending;
input next_pending_r_reg;
input \m_payload_i_reg[47] ;
input sel_first;
input areset_d1;
input sel_first_0;
input sel_first_reg_1;
input [1:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[5] ;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [1:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire [0:0]\axlen_cnt_reg[0] ;
wire [0:0]\axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg[7]_1 ;
wire \axlen_cnt_reg[7]_2 ;
wire b_push;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]\m_payload_i_reg[0] ;
wire [2:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[5] ;
wire next;
wire next_pending_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire si_rs_awvalid;
wire \state[0]_i_1_n_0 ;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1__0_n_0 ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire wrap_next_pending;
wire [0:0]\wrap_second_len_r_reg[0] ;
wire [0:0]\wrap_second_len_r_reg[0]_0 ;
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[46] [2]),
.I2(\axlen_cnt_reg[7]_0 ),
.I3(si_rs_awvalid),
.I4(\axlen_cnt_reg[7] ),
.I5(\m_payload_i_reg[5] ),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__0
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[46] [1]),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\axlen_cnt_reg[7]_2 ),
.O(\axlen_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hFF04))
\axlen_cnt[3]_i_1__0
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(next),
.O(\axaddr_wrap_reg[11] ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT5 #(
.INIT(32'h0000FF04))
\axlen_cnt[7]_i_1__0
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7] ),
.I3(next),
.I4(\axlen_cnt_reg[7]_2 ),
.O(\axlen_cnt_reg[7]_1 ));
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(\axlen_cnt_reg[7] ),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(b_push),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0] ));
LUT6 #(
.INIT(64'h88008888A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(\axlen_cnt_reg[7] ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__0 ),
.I5(s_axburst_eq1_reg_0),
.O(b_push));
LUT5 #(
.INIT(32'hFFFFF404))
next_pending_r_i_1
(.I0(E),
.I1(next_pending_r_reg),
.I2(next),
.I3(\axlen_cnt_reg[7]_2 ),
.I4(\m_payload_i_reg[47] ),
.O(incr_next_pending));
LUT6 #(
.INIT(64'hF3F3FFFF51000000))
next_pending_r_i_2
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\axlen_cnt_reg[7]_0 ),
.I5(\axlen_cnt_reg[7] ),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hBA8A))
s_axburst_eq0_i_1
(.I0(incr_next_pending),
.I1(sel_first_i),
.I2(\m_payload_i_reg[46] [0]),
.I3(wrap_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hFE02))
s_axburst_eq1_i_1
(.I0(incr_next_pending),
.I1(\m_payload_i_reg[46] [0]),
.I2(sel_first_i),
.I3(wrap_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1
(.I0(next),
.I1(sel_first),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1__0
(.I0(next),
.I1(sel_first_0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFF04FFFFFF04FF04))
sel_first_i_1__1
(.I0(\axlen_cnt_reg[7] ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7]_0 ),
.I3(areset_d1),
.I4(next),
.I5(sel_first_reg_1),
.O(sel_first_i));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hBBBA))
\state[0]_i_1
(.I0(\state[0]_i_2_n_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00F000F055750000))
\state[0]_i_2
(.I0(m_axi_awready),
.I1(s_axburst_eq1_reg_0),
.I2(\cnt_read_reg[1]_rep__0 ),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\axlen_cnt_reg[7]_0 ),
.I5(\axlen_cnt_reg[7] ),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0CAE0000000000))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\axlen_cnt_reg[7] ),
.I5(\axlen_cnt_reg[7]_0 ),
.O(\state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg[7]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg[7] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\axlen_cnt_reg[7] ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7]_0 ),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_4
(.I0(\axaddr_offset_r_reg[3]_0 [1]),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(si_rs_awvalid),
.I3(\axlen_cnt_reg[7] ),
.O(\wrap_cnt_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_6
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(si_rs_awvalid),
.I3(\axlen_cnt_reg[7] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(\wrap_second_len_r_reg[0] ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd
(wrap_next_pending,
sel_first_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_awvalid,
\axaddr_offset_r_reg[3]_1 ,
D,
\m_payload_i_reg[47]_0 ,
next,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
sel_first_reg_3,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[0] ,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output wrap_next_pending;
output sel_first_reg_0;
output \wrap_cnt_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_awvalid;
input \axaddr_offset_r_reg[3]_1 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input next;
input sel_first_reg_2;
input [10:0]\axaddr_incr_reg[11] ;
input sel_first_reg_3;
input \axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire aclk;
wire [10:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1_n_0 ;
wire \axlen_cnt[1]_i_1_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire [18:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_i_2__1_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire [11:0]wrap_boundary_axaddr_r;
wire [1:1]wrap_cnt;
wire [3:0]wrap_cnt_r;
wire \wrap_cnt_r_reg[3]_0 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(wrap_cnt_r[1]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(wrap_cnt_r[2]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S(axaddr_wrap[11:8]));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S(axaddr_wrap[7:4]));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAC3AAC3AAC3AAC0))
\axlen_cnt[1]_i_1
(.I0(\m_payload_i_reg[47] [16]),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(E),
.I4(\axlen_cnt_reg_n_0_[3] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAACCCCCCC0))
\axlen_cnt[3]_i_1
(.I0(\m_payload_i_reg[47] [18]),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(E),
.O(\axlen_cnt[3]_i_1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [10]),
.O(m_axi_awaddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[1]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [2]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [3]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_awaddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[5]_INST_0
(.I0(\m_payload_i_reg[47] [5]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[5]),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_3),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_awaddr[9]));
LUT5 #(
.INIT(32'hFEAAFEAE))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[47]_0 ),
.I1(next_pending_r_reg_n_0),
.I2(next),
.I3(next_pending_r_i_2__1_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__1
(.I0(\state_reg[1] [0]),
.I1(si_rs_awvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_2__1_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h3D310E02))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_2 ),
.I3(D[1]),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(wrap_cnt));
LUT6 #(
.INIT(64'h000CAAA8000C0000))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_second_len_r_reg[3]_0 [1]),
.I1(\axaddr_offset_r_reg[3]_1 ),
.I2(D[1]),
.I3(D[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [0]),
.O(\wrap_cnt_r_reg[3]_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(wrap_cnt),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3
(sel_first_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
s_axburst_eq0_reg,
s_axburst_eq1_reg,
m_axi_araddr,
\axaddr_offset_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
Q,
\state_reg[1] ,
si_rs_arvalid,
\axaddr_offset_r_reg[3]_1 ,
D,
sel_first_i,
incr_next_pending,
\m_payload_i_reg[47] ,
\state_reg[1]_rep ,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
sel_first_reg_3,
sel_first_reg_4,
sel_first_reg_5,
sel_first_reg_6,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output sel_first_reg_0;
output \wrap_cnt_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output s_axburst_eq0_reg;
output s_axburst_eq1_reg;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]Q;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input \axaddr_offset_r_reg[3]_1 ;
input [3:0]D;
input sel_first_i;
input incr_next_pending;
input \m_payload_i_reg[47] ;
input \state_reg[1]_rep ;
input sel_first_reg_2;
input [7:0]\axaddr_incr_reg[11] ;
input sel_first_reg_3;
input sel_first_reg_4;
input sel_first_reg_5;
input sel_first_reg_6;
input \axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [18:0]Q;
wire aclk;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__1_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__2_n_0;
wire next_pending_r_reg_n_0;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire sel_first_reg_5;
wire sel_first_reg_6;
wire si_rs_arvalid;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r[1]_i_1__0_n_0 ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\wrap_cnt_r_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\wrap_cnt_r_reg_n_0_[1] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[11] ,\axaddr_wrap_reg_n_0_[10] ,\axaddr_wrap_reg_n_0_[9] ,\axaddr_wrap_reg_n_0_[8] }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[7] ,\axaddr_wrap_reg_n_0_[6] ,\axaddr_wrap_reg_n_0_[5] ,\axaddr_wrap_reg_n_0_[4] }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__1
(.I0(Q[15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAC3AAC3AAC3AAC0))
\axlen_cnt[1]_i_1__2
(.I0(Q[16]),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(E),
.I4(\axlen_cnt_reg_n_0_[3] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(Q[17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAACCCCCCC0))
\axlen_cnt[3]_i_1__1
(.I0(Q[18]),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(E),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(Q[14]),
.I3(Q[0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(Q[14]),
.I3(Q[10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(Q[14]),
.I3(Q[11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_araddr[11]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[1]_INST_0
(.I0(Q[1]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[1] ),
.I3(Q[14]),
.I4(sel_first_reg_6),
.O(m_axi_araddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[2]_INST_0
(.I0(Q[2]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[2] ),
.I3(Q[14]),
.I4(sel_first_reg_5),
.O(m_axi_araddr[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[3]_INST_0
(.I0(Q[3]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[3] ),
.I3(Q[14]),
.I4(sel_first_reg_4),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(Q[14]),
.I3(Q[4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_araddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[5]_INST_0
(.I0(Q[5]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[5] ),
.I3(Q[14]),
.I4(sel_first_reg_3),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(Q[14]),
.I3(Q[6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(Q[14]),
.I3(Q[7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(Q[14]),
.I3(Q[8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(Q[14]),
.I3(Q[9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFEAAFEAE))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[47] ),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(next_pending_r_i_2__2_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__2
(.I0(\state_reg[1] [0]),
.I1(si_rs_arvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_2__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(Q[14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(Q[14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(Q[10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(Q[11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(Q[7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(Q[8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(Q[9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h3D310E02))
\wrap_cnt_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_2 ),
.I3(D[1]),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_cnt_r[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h000CAAA8000C0000))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_second_len_r_reg[3]_0 [1]),
.I1(\axaddr_offset_r_reg[3]_1 ),
.I2(D[1]),
.I3(D[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [0]),
.O(\wrap_cnt_r_reg[3]_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_cnt_r[1]_i_1__0_n_0 ),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
\axlen_cnt_reg[3] ,
Q,
\axlen_cnt_reg[3]_0 ,
\s_arid_r_reg[11] ,
axaddr_incr,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[7] ,
O,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
axaddr_offset,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_cnt_r_reg[2]_0 ,
axaddr_offset_0,
\wrap_cnt_r_reg[3]_1 ,
\axaddr_offset_r_reg[2]_0 ,
next_pending_r_reg_0,
\cnt_read_reg[2]_rep__0 ,
\wrap_boundary_axaddr_r_reg[6] ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
s_ready_i0,
m_valid_i0,
aresetn,
\state_reg[1] ,
\state_reg[1]_0 ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
S,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_1 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[2]_2 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_awvalid,
b_push,
\wrap_second_len_r_reg[3]_2 ,
\state_reg[1]_rep_1 ,
\wrap_second_len_r_reg[1]_0 ,
\axaddr_offset_r_reg[2]_3 ,
\axaddr_offset_r_reg[3]_1 ,
\axaddr_offset_r_reg[3]_2 ,
\axaddr_offset_r_reg[2]_4 ,
\state_reg[0]_rep_0 ,
\state_reg[1]_rep_2 ,
si_rs_bvalid,
s_axi_bready,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output \axlen_cnt_reg[3]_0 ;
output [54:0]\s_arid_r_reg[11] ;
output [11:0]axaddr_incr;
output [3:0]\axaddr_incr_reg[3] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output [2:0]axaddr_offset;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [1:0]\wrap_cnt_r_reg[3]_0 ;
output [2:0]\wrap_second_len_r_reg[3]_0 ;
output \wrap_cnt_r_reg[2]_0 ;
output [2:0]axaddr_offset_0;
output \wrap_cnt_r_reg[3]_1 ;
output \axaddr_offset_r_reg[2]_0 ;
output next_pending_r_reg_0;
output \cnt_read_reg[2]_rep__0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input s_ready_i0;
input m_valid_i0;
input aresetn;
input [1:0]\state_reg[1] ;
input [1:0]\state_reg[1]_0 ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_1 ;
input [2:0]\axaddr_offset_r_reg[3] ;
input \axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[2]_2 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input s_axi_awvalid;
input b_push;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input \state_reg[1]_rep_1 ;
input \wrap_second_len_r_reg[1]_0 ;
input [0:0]\axaddr_offset_r_reg[2]_3 ;
input [2:0]\axaddr_offset_r_reg[3]_1 ;
input \axaddr_offset_r_reg[3]_2 ;
input \axaddr_offset_r_reg[2]_4 ;
input \state_reg[0]_rep_0 ;
input \state_reg[1]_rep_2 ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire \ar.ar_pipe_n_2 ;
wire aresetn;
wire \aw.aw_pipe_n_1 ;
wire \aw.aw_pipe_n_90 ;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [2:0]axaddr_offset;
wire [2:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[2]_0 ;
wire [0:0]\axaddr_offset_r_reg[2]_1 ;
wire \axaddr_offset_r_reg[2]_2 ;
wire [0:0]\axaddr_offset_r_reg[2]_3 ;
wire \axaddr_offset_r_reg[2]_4 ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [2:0]\axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[2]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire m_valid_i0;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [54:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire \state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_cnt_r_reg[2] ;
wire \wrap_cnt_r_reg[2]_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [1:0]\wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire \wrap_second_len_r_reg[1] ;
wire \wrap_second_len_r_reg[1]_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice \ar.ar_pipe
(.O(O),
.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[0]_0 (\aw.aw_pipe_n_90 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.axaddr_offset_0(axaddr_offset_0[2:1]),
.\axaddr_offset_r_reg[0] (axaddr_offset_0[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2]_0 ),
.\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_3 ),
.\axaddr_offset_r_reg[2]_1 (\axaddr_offset_r_reg[2]_4 ),
.\axaddr_offset_r_reg[3] (si_rs_arvalid),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_2 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i0(m_valid_i0),
.m_valid_i_reg_0(\ar.ar_pipe_n_2 ),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_ready_i0(s_ready_i0),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_cnt_r_reg[2] (\wrap_cnt_r_reg[2]_0 ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.\wrap_second_len_r_reg[1] (\wrap_second_len_r_reg[1]_0 ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_2 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 \aw.aw_pipe
(.D(D),
.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (\aw.aw_pipe_n_90 ),
.\aresetn_d_reg[1]_inv_0 (\ar.ar_pipe_n_2 ),
.axaddr_incr(axaddr_incr),
.axaddr_offset(axaddr_offset[2:1]),
.\axaddr_offset_r_reg[0] (axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_1 ),
.\axaddr_offset_r_reg[2]_1 (\axaddr_offset_r_reg[2]_2 ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(\aw.aw_pipe_n_1 ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_cnt_r_reg[2] (\wrap_cnt_r_reg[2] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[1] (\wrap_second_len_r_reg[1] ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1 \b.b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\ar.ar_pipe_n_2 ),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2 \r.r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\ar.ar_pipe_n_2 ),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_rep__0 (\cnt_read_reg[4]_rep__0 ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice
(s_axi_arready,
\axaddr_offset_r_reg[3] ,
m_valid_i_reg_0,
\axlen_cnt_reg[3] ,
Q,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[7] ,
O,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
\axaddr_offset_r_reg[0] ,
axaddr_offset_0,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\aresetn_d_reg[0] ,
s_ready_i0,
aclk,
m_valid_i0,
\aresetn_d_reg[0]_0 ,
\state_reg[1] ,
\m_payload_i_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_0 ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\axaddr_offset_r_reg[2]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_valid_i_reg_1);
output s_axi_arready;
output \axaddr_offset_r_reg[3] ;
output m_valid_i_reg_0;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output [3:0]\axaddr_incr_reg[3] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]\wrap_cnt_r_reg[3] ;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output \axaddr_offset_r_reg[0] ;
output [1:0]axaddr_offset_0;
output \wrap_cnt_r_reg[3]_0 ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
input \aresetn_d_reg[0] ;
input s_ready_i0;
input aclk;
input m_valid_i0;
input \aresetn_d_reg[0]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input \axaddr_offset_r_reg[2]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [0:0]m_valid_i_reg_1;
wire [3:0]O;
wire [54:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[3]_i_4__0_n_0 ;
wire \axaddr_incr[3]_i_5__0_n_0 ;
wire \axaddr_incr[3]_i_6__0_n_0 ;
wire \axaddr_incr_reg[11]_i_3__0_n_1 ;
wire \axaddr_incr_reg[11]_i_3__0_n_2 ;
wire \axaddr_incr_reg[11]_i_3__0_n_3 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire \axaddr_incr_reg[3]_i_2__0_n_0 ;
wire \axaddr_incr_reg[3]_i_2__0_n_1 ;
wire \axaddr_incr_reg[3]_i_2__0_n_2 ;
wire \axaddr_incr_reg[3]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire \axaddr_incr_reg[7]_i_2__0_n_0 ;
wire \axaddr_incr_reg[7]_i_2__0_n_1 ;
wire \axaddr_incr_reg[7]_i_2__0_n_2 ;
wire \axaddr_incr_reg[7]_i_2__0_n_3 ;
wire [1:0]axaddr_offset_0;
wire \axaddr_offset_r[0]_i_2__0_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[3]_i_2__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[2] ;
wire [0:0]\axaddr_offset_r_reg[2]_0 ;
wire \axaddr_offset_r_reg[2]_1 ;
wire \axaddr_offset_r_reg[3] ;
wire [2:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[52]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_ready_i0;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_5__0_n_0 ;
wire \wrap_cnt_r_reg[2] ;
wire [1:0]\wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_second_len_r[3]_i_2__0_n_0 ;
wire \wrap_second_len_r[3]_i_3__0_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_6__0_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3__0
(.CI(\axaddr_incr_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3__0_n_1 ,\axaddr_incr_reg[11]_i_3__0_n_2 ,\axaddr_incr_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2__0_n_0 ,\axaddr_incr_reg[3]_i_2__0_n_1 ,\axaddr_incr_reg[3]_i_2__0_n_2 ,\axaddr_incr_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4__0_n_0 ,\axaddr_incr[3]_i_5__0_n_0 ,\axaddr_incr[3]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[7]_i_2__0
(.CI(\axaddr_incr_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2__0_n_0 ,\axaddr_incr_reg[7]_i_2__0_n_1 ,\axaddr_incr_reg[7]_i_2__0_n_2 ,\axaddr_incr_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[36]),
.I3(Q[1]),
.I4(Q[35]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I1(Q[40]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(axaddr_offset_0[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[4]),
.I2(Q[36]),
.I3(Q[3]),
.I4(Q[35]),
.I5(Q[2]),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I1(Q[42]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(axaddr_offset_0[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[5]),
.I2(Q[36]),
.I3(Q[4]),
.I4(Q[35]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h0020))
\axlen_cnt[3]_i_3__0
(.I0(Q[42]),
.I1(\state_reg[1] [0]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\state_reg[1] [1]),
.O(\axlen_cnt_reg[3] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(\m_payload_i[52]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[52]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(\axaddr_offset_r_reg[3] ),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_3
(.I0(\state_reg[1]_rep ),
.I1(Q[42]),
.I2(Q[40]),
.I3(Q[39]),
.I4(Q[41]),
.O(next_pending_r_reg));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[39]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hFF0F553300000000))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[36]),
.I5(Q[2]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h503F5F3F00000000))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[36]),
.I3(Q[35]),
.I4(Q[42]),
.I5(Q[4]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[42]),
.I2(Q[35]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1]_rep ),
.I3(\wrap_cnt_r_reg[2] ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(\wrap_cnt_r_reg[3] [0]));
LUT3 #(
.INIT(8'h6A))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFFFEAEAFFEA))
\wrap_cnt_r[3]_i_3__0
(.I0(\axaddr_offset_r_reg[3]_1 ),
.I1(\axlen_cnt_reg[3] ),
.I2(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\wrap_cnt_r[3]_i_5__0_n_0 ),
.I5(\axaddr_offset_r_reg[2]_1 ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT4 #(
.INIT(16'hFFDF))
\wrap_cnt_r[3]_i_5__0
(.I0(Q[41]),
.I1(\state_reg[0]_rep ),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\state_reg[1]_rep_0 ),
.O(\wrap_cnt_r[3]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h0001000000010001))
\wrap_second_len_r[0]_i_2__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset_0[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(\wrap_cnt_r_reg[2] ));
LUT6 #(
.INIT(64'hF00EFFFFF00E0000))
\wrap_second_len_r[1]_i_1__0
(.I0(axaddr_offset_0[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(axaddr_offset_0[0]),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hCCC2FFFFCCC20000))
\wrap_second_len_r[2]_i_1__0
(.I0(axaddr_offset_0[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(axaddr_offset_0[0]),
.I3(\axaddr_offset_r_reg[0] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFE00FFFFFE00FE00))
\wrap_second_len_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset_0[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [3]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\wrap_second_len_r[3]_i_2__0
(.I0(\axlen_cnt_reg[3] ),
.I1(\wrap_second_len_r[3]_i_3__0_n_0 ),
.I2(Q[36]),
.I3(Q[5]),
.I4(Q[35]),
.I5(Q[6]),
.O(\wrap_second_len_r[3]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[3]_i_3__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[3]),
.O(\wrap_second_len_r[3]_i_3__0_n_0 ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
\axlen_cnt_reg[3] ,
Q,
axaddr_incr,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
\axaddr_offset_r_reg[0] ,
axaddr_offset,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
\state_reg[1] ,
S,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[2]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_awvalid,
b_push,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output [11:0]axaddr_incr;
output [1:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output \axaddr_offset_r_reg[0] ;
output [1:0]axaddr_offset;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input [1:0]\state_reg[1] ;
input [3:0]S;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3] ;
input \axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[2]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input s_axi_awvalid;
input b_push;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [0:0]E;
wire [1:0]D;
wire [0:0]E;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire [11:0]axaddr_incr;
wire \axaddr_incr[3]_i_4_n_0 ;
wire \axaddr_incr[3]_i_5_n_0 ;
wire \axaddr_incr[3]_i_6_n_0 ;
wire \axaddr_incr_reg[11]_i_3_n_1 ;
wire \axaddr_incr_reg[11]_i_3_n_2 ;
wire \axaddr_incr_reg[11]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_2_n_0 ;
wire \axaddr_incr_reg[3]_i_2_n_1 ;
wire \axaddr_incr_reg[3]_i_2_n_2 ;
wire \axaddr_incr_reg[3]_i_2_n_3 ;
wire \axaddr_incr_reg[7]_i_2_n_0 ;
wire \axaddr_incr_reg[7]_i_2_n_1 ;
wire \axaddr_incr_reg[7]_i_2_n_2 ;
wire \axaddr_incr_reg[7]_i_2_n_3 ;
wire [1:0]axaddr_offset;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[1]_i_2_n_0 ;
wire \axaddr_offset_r[3]_i_2_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[2] ;
wire [0:0]\axaddr_offset_r_reg[2]_0 ;
wire \axaddr_offset_r_reg[2]_1 ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [61:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_5_n_0 ;
wire \wrap_cnt_r_reg[2] ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire \wrap_second_len_r[3]_i_3_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_6_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3
(.CI(\axaddr_incr_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3_n_1 ,\axaddr_incr_reg[11]_i_3_n_2 ,\axaddr_incr_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[11:8]),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2_n_0 ,\axaddr_incr_reg[3]_i_2_n_1 ,\axaddr_incr_reg[3]_i_2_n_2 ,\axaddr_incr_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4_n_0 ,\axaddr_incr[3]_i_5_n_0 ,\axaddr_incr[3]_i_6_n_0 }),
.O(axaddr_incr[3:0]),
.S(S));
CARRY4 \axaddr_incr_reg[7]_i_2
(.CI(\axaddr_incr_reg[3]_i_2_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2_n_0 ,\axaddr_incr_reg[7]_i_2_n_1 ,\axaddr_incr_reg[7]_i_2_n_2 ,\axaddr_incr_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[7:4]),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[36]),
.I3(Q[1]),
.I4(Q[35]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r[1]_i_2_n_0 ),
.I1(Q[40]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [1]),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[2]_i_2
(.I0(Q[5]),
.I1(Q[4]),
.I2(Q[36]),
.I3(Q[3]),
.I4(Q[35]),
.I5(Q[2]),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r[3]_i_2_n_0 ),
.I1(Q[42]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [2]),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[5]),
.I2(Q[36]),
.I3(Q[4]),
.I4(Q[35]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0020))
\axlen_cnt[3]_i_3
(.I0(Q[42]),
.I1(\state_reg[1] [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\axlen_cnt_reg[3] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(skid_buffer[52]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(E),
.D(skid_buffer[52]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_4
(.I0(\state_reg[1]_rep ),
.I1(Q[42]),
.I2(Q[40]),
.I3(Q[39]),
.I4(Q[41]),
.O(next_pending_r_reg));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_awready),
.I2(b_push),
.I3(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[39]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hFF0F553300000000))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[36]),
.I5(Q[2]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h503F5F3F00000000))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[36]),
.I3(Q[35]),
.I4(Q[42]),
.I5(Q[4]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[42]),
.I2(Q[35]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1]_rep ),
.I3(\wrap_cnt_r_reg[2] ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(D[0]));
LUT3 #(
.INIT(8'h6A))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_second_len_r_reg[3] [1]),
.O(D[1]));
LUT6 #(
.INIT(64'hFFFFFFFFEAEAFFEA))
\wrap_cnt_r[3]_i_3
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\axlen_cnt_reg[3] ),
.I2(\axaddr_offset_r[3]_i_2_n_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\wrap_cnt_r[3]_i_5_n_0 ),
.I5(\axaddr_offset_r_reg[2]_1 ),
.O(\wrap_cnt_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\wrap_cnt_r[3]_i_5
(.I0(Q[41]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\wrap_cnt_r[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0001000000010001))
\wrap_second_len_r[0]_i_2
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3] [2]),
.O(\wrap_cnt_r_reg[2] ));
LUT6 #(
.INIT(64'hF00EFFFFF00E0000))
\wrap_second_len_r[1]_i_1
(.I0(axaddr_offset[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(axaddr_offset[0]),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hCCC2FFFFCCC20000))
\wrap_second_len_r[2]_i_1
(.I0(axaddr_offset[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(axaddr_offset[0]),
.I3(\axaddr_offset_r_reg[0] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFE00FFFFFE00FE00))
\wrap_second_len_r[3]_i_1
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [3]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\wrap_second_len_r[3]_i_2
(.I0(\axlen_cnt_reg[3] ),
.I1(\wrap_second_len_r[3]_i_3_n_0 ),
.I2(Q[36]),
.I3(Q[5]),
.I4(Q[35]),
.I5(Q[6]),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[3]_i_3
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[3]),
.O(\wrap_second_len_r[3]_i_3_n_0 ));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__0
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[2]_rep__0 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[2]_rep__0 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[2]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[4]_i_4
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__0 ),
.O(\cnt_read_reg[2]_rep__0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\cnt_read_reg[4]_rep__0 ),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\cnt_read_reg[4]_rep__0 ),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [11:0]s_axi_wid;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(s_axi_wid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module stage1 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/bachelors.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule |
module test_isim_top;
// Inputs
reg CLOCK_IN;
reg RESET;
reg [2:0] SWITCH;
// Outputs
wire [3:0] LED;
// Instantiate the Unit Under Test (UUT)
Top uut (
.CLOCK_IN(CLOCK_IN),
.RESET(RESET),
.SW(SWITCH),
.LED(LED)
);
always #10 CLOCK_IN = ~CLOCK_IN;
initial begin
// Initialize Inputs
CLOCK_IN = 0;
RESET = 1;
SWITCH = 2'b001;
// Wait 100 ns for global reset to finish
#120;
// Add stimulus here
RESET = 0;
end
endmodule |
module sky130_fd_sc_lp__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule |
module sky130_fd_sc_lp__nor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_hd__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
FIFO fifo_cb (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/FIFO.sdf",fifo_cb,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
rst=1'd1; // Reset
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd45;
// Push...
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd231;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd37;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd174;
// Pop
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd45;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd145;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd24; // Empty
// Pop more
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd245;
// Push
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd235;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd39;
// Push and Pop
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd1;
d_in=8'd201;
// Continue pushing
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd72;
// DO NOT PUSH NOR POP
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd82;
// Continue pushing
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd58;
#10 // FULL
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd238;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd125;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule |
module mem (
input clk,
input reset,
input [31:0] addr,
input [3:0] mask,
input enable,
input cmd,
input [31:0] write_data,
output reg [31:0] load_data,
output reg valid
);
localparam MEMORY_SIZE = (1 << 14);
reg [31:0] memory [MEMORY_SIZE - 1:0];
wire [29:0] word_addr = addr[31:2];
initial begin
/* Loads by word addresses. Address 0x302c corresponds to 0x0c0b. */
$readmemh("mem.hex", memory);
end
always @ (*) begin
if (enable && cmd == `MEM_CMD_READ) begin
load_data = memory[word_addr];
valid = 1;
end else begin
load_data = 32'b0;
valid = 0;
end
end
wire [31:0] expanded_mask = {mask[3] ? 8'hFF : 8'h00,
mask[2] ? 8'hFF : 8'h00,
mask[1] ? 8'hFF : 8'h00,
mask[0] ? 8'hFF : 8'h00};
wire [31:0] to_be_written = (memory[word_addr] & ~expanded_mask) | (write_data & expanded_mask);
always @ (*) begin
if (enable && cmd == `MEM_CMD_WRITE) begin
memory[word_addr] = to_be_written;
end
end
endmodule |
module hdmi_video (
input CLOCK_50_i,
input reset_i,
output hdmi_clk_o,
output hdmi_de_o,
output hdmi_vs_o,
output hdmi_hs_o,
output [23:0] hdmi_d_o,
output [15:0] a_o,
output vram_clk_o,
input [23:0] color_dat_i,
output [2:0] video_pixel_o,
output border_o,
input [15:0] video_offset_i
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire inDisplayArea;
reg [10:0] CounterX = 0;
reg [9:0] CounterY = 0;
// These are actual pixel cursors res 800x600
wire [9:0] cursorx;
wire [9:0] cursory;
wire [9:0] bitmapx;
wire [9:0] bitmapy;
wire inbitmap_area;
//=======================================================
// Combinational logic
//=======================================================
// if in bitmap area, show blue, if border area show green, else nothing
assign hdmi_d_o = { (inDisplayArea) ? color_dat_i : 24'd0 };
assign hdmi_de_o = inDisplayArea;
assign hdmi_hs_o = (CounterX >= 128) || (CounterY < 4) ; // change this value to move the display horizontally
assign hdmi_vs_o = (CounterY >= 4); // change this value to move the display vertically
assign inDisplayArea = (CounterX >= 216) && (CounterX < 1016) && (CounterY >= 27) && (CounterY < 627);
// These are actual pixel cursors res 800x600
assign cursorx = (inDisplayArea) ? CounterX - 10'd216 : 1'b0;
assign cursory = (inDisplayArea) ? CounterY - 10'd27 : 1'b0;
// Now work out if we're in the bitmapped area or border area
assign inbitmap_area = (cursorx >= 80) && (cursorx < 719) && (cursory >= 100) && (cursory < 500);
// What's our position in the bitmap area
assign bitmapx = (inbitmap_area) ? cursorx - 10'd80 : 10'd0;
assign bitmapy = (inbitmap_area) ? cursory - 10'd100 : 10'd0;
// Calculate our ram address
// Offset + (raster row offset 0-7 X h800) + line 0-200 * 80 + X (excluding bit positions)
wire [13:0] rastercalc = video_offset_i[10:0] + (bitmapy[3:1] << 11) + (bitmapy[9:4] * 7'd80) + bitmapx[9:3];
assign a_o = {video_offset_i[15:14], rastercalc};
// Send pixel number within video data byte
assign video_pixel_o = bitmapx[2:0];
// Send border signal
assign border_o = (inDisplayArea) && !(inbitmap_area);
//=======================================================
// Simulation control
//=======================================================
`ifndef SIMULATION
wire video_clock;
wire vram_clock;
// PLL - gives us various clocks from 50MHz
hdmi_clock video_clk(
.inclk0( CLOCK_50_i ),
.areset( reset_i ), // reset.reset
.c0(video_clock), // outclk0.clk
.c1(vram_clock) // outclk1.clk 4x video clock, so after 2 clocks data is available for strobe in
);
`else
// 40MHz clock
reg video_clock = 0;
reg vram_clock = 0;
always begin
#12 video_clock <= 1;
#24 video_clock <= 0;
end
// 120MHz clock
always begin
#4 vram_clock <= 1;
#4 vram_clock <= 0;
#4 vram_clock <= 1;
#5 vram_clock <= 0;
#4 vram_clock <= 1;
#4 vram_clock <= 0;
end
`endif
assign hdmi_clk_o = video_clock;
assign vram_clk_o = vram_clock;
//=======================================================
// Structural coding
//=======================================================
wire CounterXmaxed = (CounterX==11'd1055);
always @(posedge video_clock)
CounterX <= (CounterXmaxed) ? 11'd0 : CounterX + 1'b1;
always @(posedge video_clock)
if(CounterXmaxed) CounterY <= (CounterY == 627) ? 10'd0 : CounterY + 1'b1;
endmodule |
module usb_system_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule |
module value_membank(
clk,
nrst,
wren,
rdaddr,
wraddr,
start_init,
done_init,
c0_in,
c1_in,
c2_in,
c3_in,
c0_out,
c1_out,
c2_out,
c3_out
);
input clk;
input nrst;
input wren;
input start_init; // Pulse
input [9:0] rdaddr;
input [9:0] wraddr;
input [63:0] c0_in;
input [63:0] c1_in;
input [63:0] c2_in;
input [63:0] c3_in;
output [63:0] c0_out;
output [63:0] c1_out;
output [63:0] c2_out;
output [63:0] c3_out;
output done_init; // Pulse
//---------------------------------------------------------------------//
// Wires and Regs
//---------------------------------------------------------------------//
reg [63:0] buffer0;
reg [63:0] buffer1;
reg [63:0] buffer2;
reg [63:0] buffer3;
reg [10:0] timer1;
reg [1:0] state;
wire t1_expire = timer1[10];
wire init = !t1_expire;
wire [9:0] mem_wraddr = init ? timer1[9:0] : wraddr;
wire mem_wren = init || wren;
wire done_init = state[1];
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
mem_1k c0_mem_1k(
.data(init ? 64'd0 : c0_in),
.rdaddress(rdaddr),
.rdclock(clk),
.wraddress(mem_wraddr),
.wren(mem_wren),
.wrclock(clk),
.q(c0_out)
);
mem_1k c1_mem_1k(
.data(init ? 64'd0 : c1_in),
.rdaddress(rdaddr),
.rdclock(clk),
.wraddress(mem_wraddr),
.wren(mem_wren),
.wrclock(clk),
.q(c1_out)
);
mem_1k c2_mem_1k(
.rdclock(clk),
.data(init ? 64'd0 : c2_in),
.rdaddress(rdaddr),
.wraddress(mem_wraddr),
.wren(mem_wren),
.wrclock(clk),
.q(c2_out)
);
mem_1k c3_mem_1k(
.data(init ? 64'd0 : c3_in),
.rdaddress(rdaddr),
.rdclock(clk),
.wraddress(mem_wraddr),
.wren(mem_wren),
.wrclock(clk),
.q(c3_out)
);
//---------------------------------------------------------------------//
// Control Logic
//---------------------------------------------------------------------//
// Timer T1
// - Count down from 1027 or other set value to -1.
// - Timer value is used as initialization address.
// - Loads on 'start_init' pulse.
// - Stops when reaches -1.
always@(posedge clk)
if(!nrst) timer1 <= -1;
else if(start_init) timer1 <= 11'b01111111111;
else if(!t1_expire) timer1 <= timer1 - 1;
// State machine to pulse 'done_init' when finished.
always@(posedge clk)
if(!nrst) state <= 2'b00;
else if(start_init) state <= 2'b01;
else if((state == 2'b01) && t1_expire) state <= 2'b10;
else if(state == 2'b10) state <= 2'b00;
endmodule |
module servo(clk, rst, rs232_in, rs232_in_stb, rs232_in_ack, rs232_out, servos, rs232_out_stb, servos_stb, rs232_out_ack, servos_ack);
input clk;
input rst;
input [15:0] rs232_in;
input rs232_in_stb;
output rs232_in_ack;
output [15:0] rs232_out;
output rs232_out_stb;
input rs232_out_ack;
output [15:0] servos;
output servos_stb;
input servos_ack;
wire [15:0] wire_140036826114168;
wire wire_140036826114168_stb;
wire wire_140036826114168_ack;
servo_ui servo_ui_32237832(
.clk(clk),
.rst(rst),
.input_rs232(rs232_in),
.input_rs232_stb(rs232_in_stb),
.input_rs232_ack(rs232_in_ack),
.output_control(wire_140036826114168),
.output_control_stb(wire_140036826114168_stb),
.output_control_ack(wire_140036826114168_ack),
.output_rs232(rs232_out),
.output_rs232_stb(rs232_out_stb),
.output_rs232_ack(rs232_out_ack));
servo_controller servo_controller_32246024(
.clk(clk),
.rst(rst),
.input_control(wire_140036826114168),
.input_control_stb(wire_140036826114168_stb),
.input_control_ack(wire_140036826114168_ack),
.output_servos(servos),
.output_servos_stb(servos_stb),
.output_servos_ack(servos_ack));
endmodule |
module definition
// -----------------------------
always @ (*)
begin
cfg_enable_partial_be_notification = cfg_enable_ecc | cfg_enable_auto_corr | cfg_enable_no_dm;
end
always @ (*)
begin
cfg_max_cmd_burstcount = cfg_burst_length / CFG_DWIDTH_RATIO;
cfg_max_cmd_burstcount_2x = 2 * cfg_max_cmd_burstcount;
end
assign burstcount_list_write = update_cmd_if_accepted;
assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1'b0}}, update_cmd_if_burstcount};
assign burstcount_list_read = notify_data_if_valid;
// Burst count list to keep track of burst count value,
// to be used for comparison with burst count value from burst tracking logic
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_INT_SIZE_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
burstcount_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (burstcount_list_read_data_valid),
.list_get_entry_ready (burstcount_list_read),
.list_get_entry_id (burstcount_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (burstcount_list_write),
.list_put_entry_ready (),
.list_put_entry_id (burstcount_list_write_data)
);
always @ (*)
begin
if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b0;
end
if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))
begin
update_data_if_burstcount_same_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_same_burstcount_list = 1'b0;
end
end
// dataid_array management
genvar i;
generate
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array_management
assign update_data_if_burstcount_greatereq [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_greatereq_burstcount_list;
assign update_data_if_burstcount_same [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_same_burstcount_list;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_address [i] <= 0;
dataid_array_burstcount [i] <= 0;
dataid_array_tbp_id [i] <= 0;
dataid_array_data_ready [i] <= 1'b0;
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b0;
err_dataid_array_overwritten <= 0;
err_dataid_array_invalidread <= 0;
end
else
begin
// update cmd, update data & read data will not happen on same cycle
// update cmd interface
if (update_cmd_if_accepted && (update_cmd_if_data_id == i))
begin
dataid_array_address [i] <= update_cmd_if_address;
dataid_array_burstcount [i] <= update_cmd_if_burstcount;
dataid_array_tbp_id [i] <= update_cmd_if_tbp_id;
dataid_array_valid [i] <= 1'b1;
mux_dataid_array_done [i] <= 1'b0;
if (dataid_array_valid[i])
begin
err_dataid_array_overwritten <= 1;
end
end
// update data interface
if (update_data_if_burstcount_greatereq[i])
begin
dataid_array_data_ready [i] <= 1'b1;
end
// read data interface
if (read_data_if_valid_first && (read_data_if_data_id_vector_first[i]))
begin
dataid_array_address [i] <= dataid_array_address [i] + 1;
dataid_array_burstcount [i] <= dataid_array_burstcount [i] - 1;
dataid_array_data_ready [i] <= 0;
if (dataid_array_burstcount [i] == 1'b1)
begin
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b1;
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
if (~dataid_array_valid[i])
begin
err_dataid_array_invalidread <= 1;
end
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
end
end
always @ (*)
begin
if (update_data_if_burstcount_greatereq[i])
begin
mux_notify_data_if_valid [i] = 1'b1;
end
else
begin
mux_notify_data_if_valid [i] = 1'b0;
end
end
end
endgenerate
// mux to generate signals from output of dataid_array
// 1. notify TBP that data is ready to be read
// 2. notify other blocks burstcount consumed by dataid_array entry
// 3. generate read data address
assign notify_data_if_valid = update_data_if_burstcount_greatereq_burstcount_list;
assign notify_data_if_burstcount= burstcount_list_read_data;
assign read_data_if_burstcount = mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
assign read_data_if_done = |mux_dataid_array_done;
assign update_cmd_if_address_blocked= mux_update_cmd_if_address_blocked_q1 | mux_update_cmd_if_address_blocked_q2 | mux_update_cmd_if_address_blocked_q3 | mux_update_cmd_if_address_blocked_q4;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
mux_update_cmd_if_address_blocked_q1 <= 0;
mux_update_cmd_if_address_blocked_q2 <= 0;
mux_update_cmd_if_address_blocked_q3 <= 0;
mux_update_cmd_if_address_blocked_q4 <= 0;
end
else
begin
mux_update_cmd_if_address_blocked_q1 <= |mux_update_cmd_if_address_blocked[(CFG_DATAID_ARRAY_DEPTH-1):(CFG_DATAID_ARRAY_DEPTH/4*3)];
mux_update_cmd_if_address_blocked_q2 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/4*3)-1):(CFG_DATAID_ARRAY_DEPTH/2)];
mux_update_cmd_if_address_blocked_q3 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/2)-1):(CFG_DATAID_ARRAY_DEPTH/4)];
mux_update_cmd_if_address_blocked_q4 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/4)-1):0];
end
end
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one afi_wlat group
begin
always @ (*)
begin
read_data_if_address = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
end
end
else
begin
wire rdata_address_list_read;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_read_data;
wire rdata_address_list_read_data_valid;
wire rdata_address_list_write;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_write_data;
assign rdata_address_list_read = read_data_if_valid_last;
assign rdata_address_list_write = read_data_if_valid_first;
assign rdata_address_list_write_data = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
// Read data address list, to keep track of read address to different write data buffer group
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CTL_LIST_DEPTH (CFG_DRAM_WLAT_GROUP),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
rdata_address_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (rdata_address_list_read_data_valid),
.list_get_entry_ready (rdata_address_list_read),
.list_get_entry_id (rdata_address_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (rdata_address_list_write),
.list_put_entry_ready (),
.list_put_entry_id (rdata_address_list_write_data)
);
for (i = 0;i < CFG_LOCAL_WLAT_GROUP;i = i + 1)
begin : rdata_if_address_per_dqs_group
always @ (*)
begin
if (read_data_if_valid_first_vector [i])
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_write_data;
end
else
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_read_data;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address_blocked <= 0;
end
else
begin
write_data_if_address_blocked <= |mux_write_data_if_address_blocked;
end
end
always @ (*)
begin
mux_tbp_data_ready [0] = (mux_notify_data_if_valid [0]) ? dataid_array_tbp_id [0] : {CFG_TBP_NUM{1'b0}};
mux_notify_data_if_burstcount [0] = (mux_notify_data_if_valid [0]) ? dataid_array_burstcount [0] : 0;
mux_read_data_if_address [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_address [0] : 0;
mux_read_data_if_burstcount [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_burstcount [0] : 0;
mux_write_data_if_address_blocked [0] = (dataid_array_data_ready[0] & ( (dataid_array_address[0] == write_data_if_nextaddress) | (dataid_array_address[0] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ~( (dataid_array_address[0] < update_cmd_if_address) & (dataid_array_address[0] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ( (dataid_array_address[0] >= update_cmd_if_address) & (dataid_array_address[0] <= update_cmd_if_nextmaxaddress) ));
end
end
genvar j;
generate
for (j = 1; j < CFG_DATAID_ARRAY_DEPTH; j = j + 1)
begin : gen_mux_dataid_array_output
always @ (*)
begin
mux_tbp_data_ready [j] = mux_tbp_data_ready [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_tbp_id [j] : {CFG_TBP_NUM{1'b0}} );
mux_notify_data_if_burstcount [j] = mux_notify_data_if_burstcount [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_burstcount [j] : 0 );
mux_read_data_if_address [j] = mux_read_data_if_address [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_address [j] : 0 );
mux_read_data_if_burstcount [j] = mux_read_data_if_burstcount [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_burstcount [j] : 0 );
mux_write_data_if_address_blocked [j] = (dataid_array_data_ready[j] & ( (dataid_array_address[j] == write_data_if_nextaddress) | (dataid_array_address[j] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ~( (dataid_array_address[j] < update_cmd_if_address) & (dataid_array_address[j] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ( (dataid_array_address[j] >= update_cmd_if_address) & (dataid_array_address[j] <= update_cmd_if_nextmaxaddress) ));
end
end
end
endgenerate
assign notify_tbp_data_ready = mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1];
// address generation for data location in buffer
assign update_cmd_if_accepted = update_cmd_if_ready & update_cmd_if_valid;
assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_accepted_r <= 0;
update_cmd_if_address_r <= 0;
update_cmd_if_nextaddress_r <= 0;
end
else
begin
update_cmd_if_accepted_r <= update_cmd_if_accepted;
update_cmd_if_address_r <= update_cmd_if_address;
update_cmd_if_nextaddress_r <= update_cmd_if_nextaddress;
end
end
always @ (*)
begin
if (update_cmd_if_accepted_r)
begin
update_cmd_if_address = update_cmd_if_nextaddress_r;
end
else
begin
update_cmd_if_address = update_cmd_if_address_r;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address <= 0;
write_data_if_nextaddress <= 0;
end
else
begin
if (write_data_if_accepted)
begin
write_data_if_address <= write_data_if_address + 1;
write_data_if_nextaddress <= write_data_if_address + 2;
end
else
begin
write_data_if_nextaddress <= write_data_if_address + 1;
end
end
end
always @ (*)
begin
update_cmd_if_nextmaxaddress = update_cmd_if_address + cfg_max_cmd_burstcount_2x;
end
always @ (*)
begin
if (update_cmd_if_address > update_cmd_if_nextmaxaddress)
begin
update_cmd_if_nextmaxaddress_wrapped = 1'b1;
end
else
begin
update_cmd_if_nextmaxaddress_wrapped = 1'b0;
end
end
// un-notified burstcount counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_next_unnotified_burstcount <= 0;
end
else
begin
update_cmd_if_next_unnotified_burstcount <= update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_burstcount_r <= 0;
end
else
begin
update_cmd_if_burstcount_r <= update_cmd_if_burstcount;
end
end
always @ (*)
begin
if (update_cmd_if_accepted_r)
begin
update_cmd_if_unnotified_burstcount = update_cmd_if_next_unnotified_burstcount + update_cmd_if_burstcount_r;
end
else
begin
update_cmd_if_unnotified_burstcount = update_cmd_if_next_unnotified_burstcount;
end
end
// currently buffer_cmd_unallocated_counter only used for debug purposes
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_cmd_unallocated_counter <= {CFG_BUFFER_ADDR_WIDTH{1'b1}};
err_buffer_cmd_unallocated_counter_overflow <= 0;
end
else
begin
if (update_cmd_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;
end
else if (update_cmd_if_accepted)
begin
// write only
{err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;
end
else if (read_data_if_valid_last)
begin
// read only
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter + 1;
end
else
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter;
end
end
end
assign update_cmd_if_ready = ~update_cmd_if_address_blocked;
assign write_data_if_accepted = write_data_if_ready & write_data_if_valid;
always @ (*)
begin
if (write_data_if_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
write_data_if_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
// if cfg_enable_partial_be_notification, de-assert write read if partial be detected, and we have no commands being tracked currently
write_data_if_ready = ~buffer_valid_counter_full & ~partial_be_when_no_cmd_tracked;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
read_data_if_datavalid <= 0;
end
else
begin
read_data_if_datavalid <= read_data_if_valid;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
buffer_valid_counter_full <= 1'b0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (write_data_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
else if (write_data_if_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
if (buffer_valid_counter == {{(CFG_BUFFER_ADDR_WIDTH - 1){1'b1}}, 1'b0}) // when valid counter is counting up to all_ones
begin
buffer_valid_counter_full <= 1'b1;
end
else
begin
buffer_valid_counter_full <= 1'b0;
end
end
else if (read_data_if_valid_last)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
buffer_valid_counter_full <= 1'b0;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
end
end
// partial be generation logic
always @ (*)
begin
if (partial_be_when_no_cmd_tracked)
begin
notify_tbp_data_partial_be = update_data_if_valid & (|update_data_if_burstcount_same);
end
else
begin
notify_tbp_data_partial_be = partial_be_detected;
end
end
assign update_data_bc_gt_update_cmd_unnotified_bc = ~update_data_if_valid | (update_data_if_burstcount >= update_cmd_if_unnotified_burstcount);
generate
if (CFG_ECC_BE_ALLLOW_RMW) begin
reg detect_all_zeros_be;
reg detect_all_ones_be;
reg detect_partial_write_be;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
detect_all_zeros_be <= 1'b0;
detect_partial_write_be <= 1'b0;
detect_all_ones_be <= 1'b0;
end
else begin
if (write_data_if_accepted & write_data_if_allzeros_be)
begin
detect_all_zeros_be <= 1'b1;
end
else if (write_data_if_accepted & ~write_data_if_partial_be & ~write_data_if_allzeros_be)
begin
detect_all_ones_be <= 1'b1;
end
else if (write_data_if_accepted & write_data_if_partial_be)
begin
detect_partial_write_be <= 1'b1;
end
else if (|update_data_if_burstcount_same)
begin
detect_all_zeros_be <= 1'b0;
detect_partial_write_be <= 1'b0;
detect_all_ones_be <= 1'b0;
end
end
end
always @ (*)
begin
if (|update_data_if_burstcount_same)
begin
if (detect_partial_write_be)
begin
partial_be_detected = 1'b1;
end
else if (detect_all_zeros_be & ~detect_all_ones_be)
begin
partial_be_detected = 1'b1;
end
else
begin
partial_be_detected = 1'b0;
end
end
else
begin
partial_be_detected = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
// there's finally a cmd being tracked, but there's insufficient data in buffer
// this cmd has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
// there's finally a cmd being tracked, and there's sufficient data in buffer
if (|update_data_if_burstcount_same)
begin
// this command has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else
begin
// this command doesnt have partial be
// let partial_be_when_no_cmd_tracked continue asserted
end
end
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_be & update_data_bc_gt_update_cmd_unnotified_bc;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
end
end
end
end
else begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
// there's finally a cmd being tracked, but there's insufficient data in buffer
// this cmd has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
// there's finally a cmd being tracked, and there's sufficient data in buffer
if (|update_data_if_burstcount_same)
begin
// this command has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_be;
end
else
begin
// this command doesnt have partial be
// let partial_be_when_no_cmd_tracked continue asserted
end
end
end
else if (partial_be_detected & ~notify_data_if_valid)
begin
partial_be_detected <= partial_be_detected;
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_be & update_data_bc_gt_update_cmd_unnotified_bc;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_be;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
end
end
end
endgenerate
endmodule |
module ram_2k (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [10:0] addr;
output [7:0] rdata;
input [7:0] wdata;
// Net declarations
wire dp;
// Module instantiations
RAMB16_S9 ram (.DO(rdata),
.DOP (dp),
.ADDR (addr),
.CLK (clk),
.DI (wdata),
.DIP (dp),
.EN (cs),
.SSR (rst),
.WE (we));
defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
/*
defparam ram.INIT_00 = 256'h31303938373635343332313039383736_35343332313039383736353433323130;
defparam ram.INIT_01 = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
defparam ram.INIT_02 = 256'h3139383736353433323130393837363534;
defparam ram.INIT_03 = 256'h43000000;
defparam ram.INIT_05 = 256'h32;
defparam ram.INIT_07 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_0A = 256'h34;
defparam ram.INIT_0C = 256'h3500000000000000000000000000000000;
defparam ram.INIT_0F = 256'h36;
defparam ram.INIT_11 = 256'h3700000000000000000000000000000000;
defparam ram.INIT_14 = 256'h38;
defparam ram.INIT_16 = 256'h3900000000000000000000000000000000;
defparam ram.INIT_19 = 256'h30;
defparam ram.INIT_1B = 256'h3100000000000000000000000000000000;
defparam ram.INIT_1E = 256'h32;
defparam ram.INIT_20 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_23 = 256'h34;
defparam ram.INIT_25 = 256'h3500000000000000000000000000000000;
defparam ram.INIT_28 = 256'h36;
defparam ram.INIT_2A = 256'h3700000000000000000000000000000000;
defparam ram.INIT_2D = 256'h38;
defparam ram.INIT_2F = 256'h3900000000000000000000000000000000;
defparam ram.INIT_32 = 256'h30;
defparam ram.INIT_34 = 256'h3100000000000000000000000000000000;
defparam ram.INIT_37 = 256'h32;
defparam ram.INIT_39 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_3C = 256'h31303938373635343332313039383736_35343332313039383736353433323134;
defparam ram.INIT_3D = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
defparam ram.INIT_3E = 256'h35343332313039383736353433323130_39383736353433323130393837363534;
defparam ram.INIT_3F = 256'h37363534333231303938373635343332_31303938373635343332313039383736;
*/
endmodule |
module sky130_fd_sc_hvl__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule |
module sky130_fd_sc_ms__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule |
module SingleCycleProc(CLK, Reset_L, startPC, dmemOut);
input Reset_L, CLK;
input [31:0] startPC;
output [31:0] dmemOut;
wire [31:0] PC;
wire [31:0] Instr;
//
// INSERT YOUR CPU MODULES HERE
ProgramCounter PC1(PC, PC, Reset_L, startPC,CLK);
InstrMem IM1(PC, Instr);
wire RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend;
wire [3:0]ALUOp;
Control_Unit C1(RegDst, ALUSrc, MemToReg, RegWrite, MemRead, MemWrite, Branch, Jump, SignExtend, ALUOp, Instr[31:26]);
wire [3:0] ALUctrl;
ALUControl AC1(ALUctrl, ALUOp,Instr[5:0]);
wire [4:0] Waddr;
MUX5_2to1 mux1(Instr[20:16], Instr[15:11], RegDst, Waddr );
wire [31:0]Read1, Read2, Writedata;
RegisterFile RF1(Read1, Read2, Writedata, Instr[25:21],Instr[20:16], Waddr, RegWrite, CLK, Reset_L);
wire [31:0]Immediate; //Sign extended value
SIGN_EXTEND SE1(Instr[15:0], Immediate);
wire [31:0] ALUin, Result; //
wire Zero;
MUX32_2to1 mux2(Read2, Immediate, ALUSrc, ALUin);
ALU_behav ALU1( Read1, ALUin, ALUctrl, Writedata, Overflow, 1'b0, Carry_out, Zero );
//
// Debugging
//
/*
always @(RegDst or Waddr)
begin
$display("RegDst %b Waddr %d" , RegDst, Waddr );
end
*/
//Monitor changes in the program counter
/* always @(PC)
begin
#10 $display($time," PC=%d Instr: op=%d rs=%d rt=%d rd=%d imm16=%d funct=%d",
PC,Instr[31:26],Instr[25:21],Instr[20:16],Instr[15:11],Instr[15:0],Instr[5:0]);
end
*/
/* Monitors memory writes
always @(MemWrite)
begin
#1 $display($time," MemWrite=%b clock=%d addr=%d data=%d",
MemWrite, clock, dmemaddr, rportb);
end
*/
/*always @(Instr)
begin
#10 $display($time,"OPCODE=%b, ALUctrl=%b , ALUOp=%b", Instr[31:26],ALUctrl, ALUOp);
end
*/
endmodule |
module m555 (CLK);
parameter StartTime = 0, Ton = 50, Toff = 50, Tcc = Ton+Toff; //
output CLK;
reg CLK;
initial begin
#StartTime CLK = 0;
end
// The following is correct if clock starts at LOW level at StartTime //
always begin
#Toff CLK = ~CLK;
#Ton CLK = ~CLK;
end
endmodule |
module testCPU(Reset_L, startPC, testData);
input [31:0] testData;
output Reset_L;
output [31:0] startPC;
reg Reset_L;
reg [31:0] startPC;
initial begin
// Your program 1
Reset_L = 0; startPC = 0 * 4;
#101 // insures reset is asserted across negative clock edge
Reset_L = 1;
#1000; // allow enough time for program 1 to run to completion
Reset_L = 0;
// #1 $display ("Program 1: Result: %d", testData);
// Your program 2
//startPC = 14 * 4;
//#101 Reset_L = 1;
//#10000;
//Reset_L = 0;
//#1 $display ("Program 2: Result: %d", testData);
// etc.
// Run other programs here
$finish;
end
endmodule |
module TopProcessor;
wire reset, CLK, Reset_L;
wire [31:0] startPC;
wire [31:0] testData;
m555 system_clock(CLK);
SingleCycleProc SSProc(CLK, Reset_L, startPC, testData);
testCPU tcpu(Reset_L, startPC, testData);
endmodule |
module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, output MEMADD, MFA,READ_WRITE,WORD_BYTE);
ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);
initial fork
Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
#1 Reset = 0;
join
always@(posedge MFA)begin
$display("MEMADD = %d", MEMADD);
if(READ_WRITE == 1) begin
case(MEMADD)
8'h00:begin
#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h04:begin
#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h08:begin
#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h0C:begin
#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h10:begin
#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h14:begin
#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h18:begin
#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h1C:begin
#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h20:begin
#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h24:begin
#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h28:begin
#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
8'h2C:begin
#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
default:begin
#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1;
#5 MEMLOAD=0;
end
endcase
#5 MFC = 1 ;#7 MFC = 0 ;
end
end
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench5.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench5);
//$display(" Test Results" );
//$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end
endmodule |
module fifo_async_103x32 (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full
);
input wire rst;
input wire wr_clk;
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [102 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [102 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire prog_full;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(103),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(103),
.C_ENABLE_RLOCS(0),
.C_FAMILY("zynq"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(16),
.C_PROG_FULL_THRESH_NEGATE_VAL(15),
.C_PROG_FULL_TYPE(1),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(32),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(5),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(5),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(5'B0),
.prog_empty_thresh_assert(5'B0),
.prog_empty_thresh_negate(5'B0),
.prog_full_thresh(5'B0),
.prog_full_thresh_assert(5'B0),
.prog_full_thresh_negate(5'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(prog_full),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule |
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module multplr(input [5:0]X,Y, output reg [11:0] prdct );
wire [5:0] p1,p2,p3,p4,p5,p6;
partialprdct ppdct(X,Y,p1,p2,p3,p4,p5,p6);
/////////////////L0ha1s(lavel zero half adder 1 sum)
reg L0ha1s,L0ha1c,L0fa1s,L0fa1c,L0fa2s,L0fa2c,L0fa3s,L0fa3c,L0fa4s,L0fa4c,L0ha2s,L0ha2c;
/////////////////L1ha1s(lavel 1 half adder 1 sum)
reg L1ha1s,L1ha1c,L1fa1s,L1fa1c,L1fa2s,L1fa2c,L1fa3s,L1fa3c,L1fa4s,L1fa4c,L1ha2s,L1ha2c;
/////////////////L2ha1s(lavel 2 half adder 1 sum)
reg L2ha1s,L2ha1c,L2fa1s,L2fa1c,L2fa2s,L2fa2c,L2fa3s,L2fa3c,L2fa4s,L2fa4c,L2fa5s,L2fa5c;
/////////////////L3ha1s(lavel 3 half adder 1 sum)
reg L3ha1s,L3ha1c,L3ha2s,L3ha2c,L3fa1s,L3fa1c,L3fa2s,L3fa2c,L3fa3s,L3fa3c,L3ha3s,L3ha3c,L3ha4s,L3ha4c,L3ha5s,L3ha5c;
////////////////////ripple carry signals//////////
reg c1,c2,c3,c4,c5,c6,c7,c8;
///////////////////////Half Adders and Full Adders Layers//////////////////////////
////////////////////LAYER 0 adders///////////////////
always @* begin
hfaddr(p1[1],p2[0],L0ha1s,L0ha1c);
fuladdr( p1[2],p2[1],p3[0],L0fa1s,L0fa1c);
fuladdr( p1[3],p2[2],p3[1],L0fa2s,L0fa2c);
fuladdr( p1[4],p2[3],p3[2],L0fa3s,L0fa3c);
fuladdr(p1[5],p2[4],p3[3],L0fa4s,L0fa4c);
hfaddr(p2[5],p3[4],L0ha2s,L0ha2c);
////////////////////LAYER 1 adders///////////////////
hfaddr(p4[1],p5[0], L1ha1s,L1ha1c);
fuladdr( p4[2],p5[1],p6[0],L1fa1s,L1fa1c);
fuladdr( p4[3],p5[2],p6[1],L1fa2s,L1fa2c);
fuladdr( p4[4],p5[3],p6[2],L1fa3s,L1fa3c);
fuladdr( p4[5],p5[4],p6[3],L1fa4s,L1fa4c);
hfaddr(p5[5],p6[4],L1ha2s,L1ha2c);
////////////////////LAYER 2 adders///////////////////
hfaddr(L0ha1c,L0fa1s, L2ha1s,L2ha1c);
fuladdr( L0fa1c,L0fa2s,p4[0],L2fa1s,L2fa1c);
fuladdr( L0fa2c,L1ha1s,L0fa3s,L2fa2s,L2fa2c);
fuladdr( L0fa3c,L1fa1s,L0fa4s,L2fa3s,L2fa3c);
fuladdr( L0fa4c,L1fa2s,L0ha2s,L2fa4s,L2fa4c);
fuladdr( L0ha2c,L1fa3s,p3[5],L2fa5s,L2fa5c);
////////////////////LAYER 3 adders///////////////////
hfaddr(L2ha1c,L2fa1s, L3ha1s,L3ha1c);
hfaddr(L2fa1c,L2fa2s, L3ha2s,L3ha2c);
fuladdr( L2fa2c,L1ha1c,L2fa3s,L3fa1s,L3fa1c);
fuladdr( L2fa3c,L1fa1c,L2fa4s,L3fa2s,L3fa2c);
fuladdr( L2fa4c,L1fa2c,L2fa5s,L3fa3s,L3fa3c);
hfaddr(L2fa5c,L1fa4s, L3ha3s,L3ha3c);
hfaddr(L1fa4c,L1ha2s, L3ha4s,L3ha4c);
hfaddr(L1ha2c,p6[5], L3ha5s,L3ha5c);
//////Finally Carry propagate Adder//////////////////
prdct[0] = p1[0];
prdct[1] = L0ha1s;
prdct[2] = L2ha1s;
prdct[3] = L3ha1s;
hfaddr(L3ha1c,L3ha2s,prdct[4],c1);
fuladdr( c1,L3ha2c,L3fa1s,prdct[5],c2);
fuladdr( c2,L3fa1c,L3fa2s,prdct[6],c3);
fuladdr( c3,L3fa2c,L3fa3s,prdct[7],c4);
fuladdr( c4,L3fa3c,L3ha3s,prdct[8],c5);
fuladdr( c5,L3ha3c,L3ha4s,prdct[9],c6);
fuladdr( c6,L3ha4c,L3ha5s,prdct[10],c7);
hfaddr( c7,L3ha5c,prdct[11],c8);
end
/////////////////////half adder task////////////////////////
task hfaddr(input a,b,output x,y);
begin
x=a^b;
y=a&b;
end
endtask
/////////////////////Full Adder adder task////////////////////////
task fuladdr(input a,b,c,output x,y);
reg w1;
begin
w1 =(a^b);
x = w1^c;
y =(w1&c)|(a&b);
end
endtask
endmodule |
module sky130_fd_sc_ms__inv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module mux4(/*AUTOARG*/
// Outputs
out,
// Inputs
in0, in1, in2, in3, sel0, sel1, sel2, sel3
);
parameter DW=99;
//data inputs
input [DW-1:0] in0;
input [DW-1:0] in1;
input [DW-1:0] in2;
input [DW-1:0] in3;
//select inputs
input sel0;
input sel1;
input sel2;
input sel3;
output [DW-1:0] out;
assign out[DW-1:0] = ({(DW){sel0}} & in0[DW-1:0] |
{(DW){sel1}} & in1[DW-1:0] |
{(DW){sel2}} & in2[DW-1:0] |
{(DW){sel3}} & in3[DW-1:0]);
endmodule |
module sdio_data_phy (
input clk,
input rst,
input i_posedge_stb,
input i_interrupt,
//Configuration
input i_ddr_en,
input i_spi_phy,
input i_sd1_phy,
input i_sd4_phy,
//Data Interface
input i_activate,
output reg o_finished,
input i_write_flag,
input [12:0] i_data_count,
output reg o_data_wr_stb,
output [7:0] o_data_wr_data,
input i_data_rd_stb,
input [7:0] i_data_rd_data,
output reg o_data_hst_rdy, //Host May not be ready
input i_data_com_rdy,
output reg o_data_crc_good,
//FPGA Platform Interface
output reg o_sdio_data_dir,
input [7:0] i_sdio_data_in,
output reg [7:0] o_sdio_data_out
);
//local parameters
localparam IDLE = 4'h0;
localparam START = 4'h1;
localparam WRITE = 4'h2;
localparam READ = 4'h3;
localparam CRC = 4'h4;
localparam WRITE_CRC = 4'h5;
localparam FINISHED = 4'h6;
localparam PROCESS_CRC = 4'h1;
//registes/wires
reg [3:0] state;
reg [3:0] crc_state;
reg [12:0] data_count;
wire data_crc_good;
reg [3:0] crc_bit;
wire [15:0] crc_out [0:3];
reg crc_rst;
wire crc_main_rst;
wire crc_main_en;
reg [15:0] host_crc [0:3];
wire [15:0] host_crc0;
wire [15:0] host_crc1;
wire [15:0] host_crc2;
wire [15:0] host_crc3;
wire [15:0] crc_out0;
wire [15:0] crc_out1;
wire [15:0] crc_out2;
wire [15:0] crc_out3;
reg [7:0] read_data;
reg [7:0] crc_data;
wire sdio_data1;
wire sdio_data2;
wire sdio_data3;
reg capture_crc;
reg enable_crc;
reg prev_clk_edge;
wire posege_clk;
reg buffered_read_stb;
reg [7:0] buffered_read_data;
integer i;
//submodules
genvar g;
generate
for (g = 0; g < 4; g = g + 1) begin : data_crc
/*
crc16 crc (
.clk (clk_x2 ),
.rst (crc_main_rst ),
.en (crc_main_en ),
.bit (crc_data[g] ),
.crc (crc_out[g] )
);
*/
crc16_2bit crc(
.clk (clk ),
.rst (crc_main_rst ),
.en (crc_main_en ),
.bit1 (crc_data[g] ),
.bit0 (crc_data[g + 4] ),
.crc (crc_out[g] )
);
end
endgenerate
//asynchronous logic
assign crc_main_rst = i_data_rd_stb ? 1'b0 : crc_rst;
assign crc_main_en = i_data_rd_stb ? 1'b1 : enable_crc;
assign crc_out0 = crc_out[0];
assign crc_out1 = crc_out[1];
assign crc_out2 = crc_out[2];
assign crc_out3 = crc_out[3];
assign host_crc0 = host_crc[0];
assign host_crc1 = host_crc[1];
assign host_crc2 = host_crc[2];
assign host_crc3 = host_crc[3];
assign o_data_wr_data= o_sdio_data_dir ? 8'h00 : i_sdio_data_in;
assign data_crc_good = ( (host_crc[0] == crc_out[0]) &&
(host_crc[1] == crc_out[1]) &&
(host_crc[2] == crc_out[2]) &&
(host_crc[3] == crc_out[3]));
reg top_flag;
//CRC State Machine
always @ (posedge clk) begin
if (rst) begin
crc_rst <= 1;
crc_state <= IDLE;
enable_crc <= 0;
crc_data <= 0;
top_flag <= 0;
end
else begin
case (crc_state)
IDLE: begin
crc_rst <= 1;
crc_data <= 0;
if (capture_crc) begin
top_flag <= 1;
crc_rst <= 0;
crc_state <= PROCESS_CRC;
enable_crc <= 1;
end
end
PROCESS_CRC: begin
if (i_write_flag) begin
crc_data[0] <= i_sdio_data_in[4'h3];
crc_data[1] <= i_sdio_data_in[4'h2];
crc_data[2] <= i_sdio_data_in[4'h1];
crc_data[3] <= i_sdio_data_in[4'h0];
crc_data[4] <= i_sdio_data_in[4'h7];
crc_data[5] <= i_sdio_data_in[4'h6];
crc_data[6] <= i_sdio_data_in[4'h5];
crc_data[7] <= i_sdio_data_in[4'h4];
end
else begin
//Read Flag
crc_data[0] <= i_data_rd_data[4'h3];
crc_data[1] <= i_data_rd_data[4'h3];
crc_data[2] <= i_data_rd_data[4'h1];
crc_data[3] <= i_data_rd_data[4'h0];
crc_data[4] <= i_data_rd_data[4'h7];
crc_data[5] <= i_data_rd_data[4'h6];
crc_data[6] <= i_data_rd_data[4'h5];
crc_data[7] <= i_data_rd_data[4'h4];
end
if (!capture_crc) begin
crc_state <= FINISHED;
enable_crc <= 0;
end
end
FINISHED: begin
if (state == IDLE) begin
crc_state <= IDLE;
end
end
endcase
top_flag <= ~top_flag;
end
end
always @ (posedge clk)begin
if (rst) begin
buffered_read_stb <= 1'b0;
buffered_read_data <= 8'h00;
end
else begin
buffered_read_stb <= i_data_rd_stb;
buffered_read_data <= i_data_rd_data;
end
end
always @ (posedge clk) begin
if (rst) begin
o_sdio_data_out <= 8'hFF;
end
else begin
o_sdio_data_out <= read_data;
end
end
always @ (posedge clk) begin
o_data_wr_stb <= 0;
if (rst) begin
o_data_crc_good <= 0;
state <= IDLE;
o_data_hst_rdy <= 0;
data_count <= 0;
o_sdio_data_dir <= 0;
capture_crc <= 0;
read_data <= 0;
o_finished <= 0;
for (i = 0; i < 4; i = i + 1) begin
host_crc[i] <= 0;
end
end
else begin
read_data <= i_data_rd_data;
case (state)
IDLE: begin
o_finished <= 0;
data_count <= 0;
if (i_interrupt) begin
o_sdio_data_dir <= 1;
read_data <= 8'hFD;
end
else begin
o_sdio_data_dir <= 0;
read_data <= 8'hFF;
end
o_data_hst_rdy <= 0;
if (i_activate) begin
o_sdio_data_dir <= 0;
o_data_crc_good <= 0;
for (i = 0; i < 4; i = i + 1) begin
host_crc[i] <= 0;
end
state <= START;
end
end
START: begin
read_data <= 8'hFF;
//$display ("sdio_data_phy: SD4 Transaction Started!");
if (i_write_flag) begin
o_data_hst_rdy <= 1;
if (i_sdio_data_in[0] == 0) begin
capture_crc <= 1;
state <= WRITE;
end
else begin
end
end
else begin
if (i_sdio_data_in[2]) begin
o_data_hst_rdy <= 1;
if (i_data_com_rdy) begin
//Both the data bus is ready and the host has not issued the wait signal
o_sdio_data_dir <= 1;
state <= READ;
end
end
end
if (!i_activate) begin
state <= IDLE;
end
end
WRITE: begin
o_data_wr_stb <= 1;
if (data_count == i_data_count - 1) begin
//capture_crc <= 0;
end
if (data_count < i_data_count) begin
data_count <= data_count + 1;
end
else begin
o_data_wr_stb <= 0;
capture_crc <= 0;
state <= CRC;
data_count <= 0;
//data_count <= data_count + 1;
host_crc[0] <= {host_crc[0][13:0], i_sdio_data_in[7], i_sdio_data_in[3]};
host_crc[1] <= {host_crc[1][13:0], i_sdio_data_in[6], i_sdio_data_in[2]};
host_crc[2] <= {host_crc[2][13:0], i_sdio_data_in[5], i_sdio_data_in[1]};
host_crc[3] <= {host_crc[3][13:0], i_sdio_data_in[4], i_sdio_data_in[0]};
end
//Cancel a Transaction
if (!i_activate) begin
state <= IDLE;
end
end
READ: begin
//Cancel a Transaction
if (i_data_rd_stb) begin
host_crc[0] <= crc_out[0];
host_crc[1] <= crc_out[1];
host_crc[2] <= crc_out[2];
host_crc[3] <= crc_out[3];
end
if (!i_activate) begin
state <= IDLE;
end
if (data_count < i_data_count) begin
if (!buffered_read_stb) begin
read_data <= 8'hFF;
end
if (i_data_rd_stb && !buffered_read_stb) begin
read_data <= 8'h00;
end
//Is there a read strobe?
if (buffered_read_stb) begin
//It's okay if we start capturing the CRC when data is 0, it will not modify the outcome
//Is this the first byte?
read_data <= buffered_read_data;
data_count <= data_count + 1;
end
end
if (data_count >= i_data_count) begin
capture_crc <= 0;
state <= WRITE_CRC;
data_count <= 0;
//if (data_count >= (i_data_count - 1)) begin
read_data <= {host_crc0[15], host_crc1[15], host_crc2[15], host_crc3[15],
host_crc0[14], host_crc1[14], host_crc2[14], host_crc3[14]};
host_crc[0] <= {host_crc[0][13:0], 2'b00};
host_crc[1] <= {host_crc[1][13:0], 2'b00};
host_crc[2] <= {host_crc[2][13:0], 2'b00};
host_crc[3] <= {host_crc[3][13:0], 2'b00};
end
end
CRC: begin
if (data_count < (`CRC_COUNT - 1)) begin
data_count <= data_count + 1;
host_crc[0] <= {host_crc[0][13:0], i_sdio_data_in[7], i_sdio_data_in[3]};
host_crc[1] <= {host_crc[1][13:0], i_sdio_data_in[6], i_sdio_data_in[2]};
host_crc[2] <= {host_crc[2][13:0], i_sdio_data_in[5], i_sdio_data_in[1]};
host_crc[3] <= {host_crc[3][13:0], i_sdio_data_in[4], i_sdio_data_in[0]};
end
else begin
state <= FINISHED;
end
end
WRITE_CRC: begin
if (data_count < `CRC_COUNT) begin
data_count <= data_count + 1;
read_data <= {host_crc[0][15], host_crc[1][15], host_crc[2][15], host_crc[3][15],
host_crc[0][14], host_crc[1][14], host_crc[2][14], host_crc[3][14]};
host_crc[0] <= {host_crc[0][13:0], 2'b00};
host_crc[1] <= {host_crc[1][13:0], 2'b00};
host_crc[2] <= {host_crc[2][13:0], 2'b00};
host_crc[3] <= {host_crc[3][13:0], 2'b00};
end
else begin
read_data <= 8'hFF;
state <= FINISHED;
end
end
FINISHED: begin
o_finished <= 1;
o_data_hst_rdy <= 0;
read_data <= 8'hFF;
o_sdio_data_dir <= 0;
o_data_crc_good <= data_crc_good;
if (!i_activate) begin
state <= IDLE;
end
end
default: begin
if (!i_activate) begin
state <= IDLE;
end
end
endcase
end
end
endmodule |
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
// flags FIFO
reg [2:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
fifo[0] <= #1 0;
fifo[1] <= #1 0;
fifo[2] <= #1 0;
fifo[3] <= #1 0;
fifo[4] <= #1 0;
fifo[5] <= #1 0;
fifo[6] <= #1 0;
fifo[7] <= #1 0;
fifo[8] <= #1 0;
fifo[9] <= #1 0;
fifo[10] <= #1 0;
fifo[11] <= #1 0;
fifo[12] <= #1 0;
fifo[13] <= #1 0;
fifo[14] <= #1 0;
fifo[15] <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
fifo[top] <= #1 data_in[2:0];
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= #1 0;
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
fifo[top] <= #1 data_in[2:0];
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = {data8_out,fifo[bottom]};
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule |
module ram_128_134 (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [133:0] data;
input [6:0] rdaddress;
input rden;
input [6:0] wraddress;
input wren;
output [133:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [133:0] q = sub_wire0[133:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({134{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 128,
altsyncram_component.numwords_b = 128,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 7,
altsyncram_component.widthad_b = 7,
altsyncram_component.width_a = 134,
altsyncram_component.width_b = 134,
altsyncram_component.width_byteena_a = 1;
endmodule |
module GrayCounter(
input clk,
input incdec,
input stop,
input rst,
output [7:0] gray,
output [7:0] normal
);
parameter CLK_DIV = 17_000_000;
reg [31:0] clkDiv = 32'd0;
reg [7:0] curGray = 8'b0;
reg [7:0] curNum = 8'b0;
assign gray = curGray;
assign normal = curNum;
always @(posedge clk)
begin
// increment the clock divider
clkDiv = clkDiv + 1;
// reset and run control
if (rst == 1) begin
clkDiv = 0;
curNum = 8'b0;
end else if (stop == 1)
clkDiv = clkDiv - 1;
else if (clkDiv == CLK_DIV)
begin
// first, reset the clock divider
clkDiv = 0;
// use the inc/dec input
if (incdec == 1)
curNum = curNum + 1;
else
curNum = curNum - 1;
end
curGray = curNum ^ (curNum >> 1);
end
endmodule |
module sky130_fd_sc_hs__and4bb (
//# {{data|Data Signals}}
input A_N ,
input B_N ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule |
module Mealy (
output out,
input in,
input clk,
input reset_n
);
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
reg state, nextState;
reg out;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
state <= 0;
end else begin
state <= nextState;
end
end
always @(*) begin
case(state)
S0: begin
if (in == 0) begin
nextState <= S0;
out <= 0;
end else if (in == 1) begin
nextState <= S1;
out <= 1;
end else begin
nextState <= S0;
out <= 0;
end
end
S1: begin
if (in == 0) begin
nextState <= S1;
out <= 0;
end else if (in == 1) begin
nextState <= S2;
out <= 1;
end else begin
nextState <= S0;
out <= 0;
end
end
S2: begin
if (in == 0) begin
nextState <= S2;
out <= 0;
end else if (in == 1) begin
nextState <= S3;
out <= 1;
end else begin
nextState <= S0;
out <= 0;
end
end
S3: begin
if (in == 0) begin
nextState <= S3;
out <= 0;
end else if (in == 1) begin
nextState <= S0;
out <= 1;
end else begin
nextState <= S0;
out <= 0;
end
end
endcase
end
endmodule |
module sky130_fd_sc_ls__nand4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__nand4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule |
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