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module TimeHoldOver_Qsys_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [23:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [23:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire i_readdatavalid, // .readdatavalid
input wire eic_port_valid, // interrupt_controller_in.valid
input wire [44:0] eic_port_data, // .data
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
TimeHoldOver_Qsys_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.eic_port_valid (eic_port_valid), // interrupt_controller_in.valid
.eic_port_data (eic_port_data), // .data
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule |
module buffer_BB_to_stage
#(
parameter N = 8,
parameter LOG_N = 3,
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
// Start signals
input wire start,
// From buffer_BB
input wire read_full,
input wire [WIDTH+MWIDTH-1: 0] read_data,
output reg read_delete,
// To Stage
output wire [LOG_N-1:0] out_addr0,
output wire [LOG_N-1:0] out_addr1,
output reg out_nd,
output reg [WIDTH-1:0] out_data0,
output reg [WIDTH-1:0] out_data1,
// To mStore
output reg out_mnd,
output reg [MWIDTH-1:0] out_m,
// Whether it is active
output wire active,
output reg error
);
reg [LOG_N-1:0] addr;
assign out_addr0 = addr;
assign out_addr1 = addr + 1;
reg read_counter;
wire [WIDTH-1:0] read_data_s;
wire [MWIDTH-1:0] read_data_m;
assign {read_data_s, read_data_m} = read_data;
reg first_read;
reg active_o;
assign active = active_o | start;
always @ (posedge clk)
begin
// Set the default values;
out_nd <= 1'b0;
read_delete <= 1'b0;
out_mnd <= 1'b0;
if (~rst_n)
begin
active_o <= 1'b0;
addr <= {LOG_N{1'b0}};
read_counter <= 1'b0;
error <= 1'b0;
end
else if (start)
begin
if (active_o)
error <= 1'b1;
else
begin
active_o <= 1'b1;
addr <= {LOG_N{1'b0}};
read_counter <= 1'b0;
first_read <= 1'b1;
end
end
else if (active_o & read_full)
begin
out_mnd <= 1'b1;
out_m <= read_data_m;
// We can only read one item from the buffer each block
// cycle. But we write to the stage two at a time
// so we have to save values and only write every second
// clock cycle.
read_counter <= ~read_counter;
read_delete <= 1'b1;
if (~read_counter)
begin
out_data0 <= read_data_s;
if (~first_read)
addr <= addr + 2;
first_read <= 1'b0;
end
else
begin
out_data1 <= read_data_s;
out_nd <= 1'b1;
if (addr == N-2)
begin
active_o <= 1'b0;
end
end
end
end
endmodule |
module sky130_fd_sc_hs__dlygate4sd3 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule |
module ram_cell(
clk,
reset_n,
data_in,
dir_max,
data_valid_in,
data_out,
data_valid_out,
cellwidth,
cellinrow,
cellheight,
storecycles,
onoff,
mode,
n_bin_exp,
newcell_signal,
newline_signal,
loadcompleted,
storecompleted,
count_store_int,
address_a_int
);
parameter HISTOGRAM_WIDTH = 16;
parameter HISTMEM_WORD = 1024;
localparam HISTMEM_ADDR_WIDTH = $clog2(HISTMEM_WORD);
input clk, reset_n;
input [15:0] data_in;
input [7:0] dir_max;
input data_valid_in;
//% \brief cell width (in pixel) minus 1
input [9:0] cellwidth;
//% \brief number of cells in a complete frame row minus 1
input [9:0] cellinrow;
//% \brief cell height (in pixel) minus 1
input [9:0] cellheight;
//% \brief number of data_valid_out pulse during store phase
//% storecycles could be computed as:
//% \f[ store\_cycles = \frac{RAM\_WIDTH}{2^{n\_bin\_exp}} \f]
//% where:
//% - n_bin_exp input parameter
//% - RAM_WIDTH number of memory location (now is fixed to 1024)
//%
input [15:0] storecycles;
//% \brief Activation signal
//% onoff = 1 means active
//% onoff = 0 means not active
input onoff;
//% \brief Operation mode configuration
//% - mode = 0 means \a Luminance histogram
//% - mode = 1 means \a Gradient histogram
input mode;
//% \brief Number of Bins
//% Accepted values are:
//% - n_bin_exp = 2
//% - n_bin_exp = 3
//% - n_bin_exp = 4 which means \f$ 2^4 \f$ bins
input [3:0] n_bin_exp;
//% \todo 32bit extension for luminance histogram
output [(HISTOGRAM_WIDTH-1):0] data_out;
//% asserted when valid data are sent to output
output data_valid_out;
output newcell_signal;
output newline_signal;
output loadcompleted;
output storecompleted;
output [15:0] count_store_int;
output [(HISTMEM_ADDR_WIDTH-1):0] address_a_int;
/*! @brief Memory address LSBs
* @detail These signals point the current memory location
* according to the mode configuration
* @{
*/
reg [7:0] address_lowbits, address_lowbits_new;
/*! @} */
reg [(HISTMEM_ADDR_WIDTH-1):0] address_a;
reg [(HISTOGRAM_WIDTH-1):0] data_a;
reg [(HISTOGRAM_WIDTH-1):0] data_a_d1;
reg data_valid_in_msk;
/*! @brief Internal registers
* @{
*/
reg [9:0] count_cellwidth;
reg [9:0] count_cellinrow;
reg [9:0] count_cellheight;
wire [15:0] count_store;
//! @}
//~ reg loadcompleted_d1;
/*! @brief Data valid signal to subcells
* @{
*/
reg data_valid_subcell_0, data_valid_subcell_1;
//! @}
reg [3:0] store_fsm, store_fsm_new;
/*! @brief count_store register extended by 1bit
* @details It is used during the store phase to perform a 2cycles
* store and clean operation
* @{
*/
reg [15+1:0] count_store_extended;
//! @}
//% \brief It acts as a subcell trigger
reg active_cell;
/*! @brief It represents the count_store_extended LSB.
* @{
*/
wire store_clean_state;
//! @}
//% Asserted during switch to another cell
wire newcell_signal;
//% Asserted when an image line has been scanned (and resets count_cellwidth)
wire newline_signal;
//% Asserted when the load phase is completed
wire loadcompleted;
//% Asserted when the store phase is completed
wire storecompleted;
wire [(HISTOGRAM_WIDTH-1):0] q_b_subcell_0, q_b_subcell_1;
wire clear_signal;
localparam START_STATE = 4'b0001;
localparam WAIT_MEM = 4'b0010;
localparam WORK_STATE = 4'b0100;
localparam END_STATE = 4'b1000;
// keep in mind!
// mode = 0 luminance
// mode = 1 hog
//%
//% address_lowbits_new
//%
always@(*)
case (mode)
1'b0: address_lowbits_new[7:0] = data_in[7:0];
1'b1: address_lowbits_new[7:0] = dir_max[7:0];
default:
address_lowbits_new[7:0] = data_in[7:0];
endcase
//%
//% address_lowbits
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
address_lowbits <= 8'b0;
else
address_lowbits <= address_lowbits_new;
//%
//% address_a
//%
always@(*)
case (n_bin_exp)
// 4 bins
4'd2: address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-2:0], address_lowbits[1:0]};
// 8 bins
4'd3: address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-3:0], address_lowbits[2:0]};
// 16 bins
4'd4: address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-4:0], address_lowbits[3:0]};
// 256 bins
4'd8: address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-8:0], address_lowbits[7:0]};
default:
//% 16 bins default
address_a = {count_cellinrow[(HISTMEM_ADDR_WIDTH-1)-4:0], address_lowbits[3:0]};
endcase
//%
//% data_valid_in_msk
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_valid_in_msk <= 1'b0;
else
data_valid_in_msk <= data_valid_in & onoff;
//%
//% data_a
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_a <= {HISTOGRAM_WIDTH{1'b0}};
else
data_a <= (mode == 1) ? data_in : 1;
//%
//% data_a_d1
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_a_d1 <= {HISTOGRAM_WIDTH{1'b0}};
else
data_a_d1 <= data_a;
//%
//% active_cell
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 1'b0)
active_cell = 1'b0;
else
if (data_valid_in_msk)
active_cell <= ~active_cell;
else
active_cell <= active_cell;
//%
//% data_valid_subcell_0
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_valid_subcell_0 <= 1'b0;
else
data_valid_subcell_0 <= data_valid_in_msk & ~active_cell;//~count_cellwidth[0];
//%
//% data_valid_subcell_1
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
data_valid_subcell_1 <= 1'b0;
else
data_valid_subcell_1 <= data_valid_in_msk & active_cell;//count_cellwidth[0];
//%
//% newcell_signal
//%
assign newcell_signal = (count_cellwidth == cellwidth)
&& data_valid_in_msk;
//%
//% count_cellwidth
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_cellwidth <= 10'b0;
else
if (onoff == 0)
count_cellwidth <= 10'b0;
else
if (newcell_signal)
count_cellwidth <= 10'b0;
else
if (data_valid_in_msk)
count_cellwidth <= count_cellwidth + 1;
else
count_cellwidth <= count_cellwidth;
//%
//% newline_signal
//%
assign newline_signal = (count_cellinrow == cellinrow)
&& (count_cellwidth == cellwidth)
&& data_valid_in_msk;
//%
//% count_cellinrow
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_cellinrow <= 10'b0;
else
if (onoff == 0)
count_cellinrow <= 10'b0;
else
if (newline_signal)
count_cellinrow <= 10'b0;
else
if (newcell_signal)
count_cellinrow <= count_cellinrow + 1;
else
count_cellinrow <= count_cellinrow;
//%
//% loadcompleted
//%
assign loadcompleted = (count_cellheight == cellheight)
&& (count_cellinrow == cellinrow)
&& (count_cellwidth == cellwidth)
&& data_valid_in_msk;
//%
//% count_cellheight
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_cellheight <= 10'd0;
else
if (onoff == 0)
count_cellheight <= 10'd0;
else
if (loadcompleted)
count_cellheight <= 10'd0;
else
if (newline_signal)
count_cellheight <= count_cellheight + 1;
else
count_cellheight <= count_cellheight;
//%
//% loadcompleted_d1
//% acts as a store phase delay (useful on a one cell histogram test)
//%
//~ always@(posedge clk or negedge reset_n)
//~ if (reset_n == 0)
//~ loadcompleted_d1 <= 0;
//~ else
//~ loadcompleted_d1 <= loadcompleted;
//%
//% store_fsm
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
store_fsm <= START_STATE;
else
store_fsm <= store_fsm_new;
//%
//% store_fsm_new
//%
always@(*)
case (store_fsm)
START_STATE:
if (onoff == 1'b0)
store_fsm_new = START_STATE;
else
if (loadcompleted)
store_fsm_new = WAIT_MEM;
else
store_fsm_new = START_STATE;
WAIT_MEM:
if (onoff == 1'b0)
store_fsm_new = START_STATE;
else
store_fsm_new = WORK_STATE;
WORK_STATE:
if (onoff == 1'b0)
store_fsm_new = START_STATE;
else
if (storecompleted)
store_fsm_new = END_STATE;
else
store_fsm_new = WORK_STATE;
END_STATE:
store_fsm_new = START_STATE;
endcase
//%
//% store_clean_state
//%
assign store_clean_state = count_store_extended[0];
/*
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
store_clean_state <= 1'b0;
else
if (onoff == 0)
store_clean_state <= 1'b0;
else
if ((store_fsm == WORK_STATE) || (store_fsm == WAIT_MEM))
store_clean_state <= ~store_clean_state;
else
store_clean_state <= store_clean_state;
*/
//%
//% storecompleted
//% asserted when the store_fsm has completed
assign storecompleted = (count_store == storecycles);
//%
//% count_store
//%
assign count_store = count_store_extended[16:1];
/*
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_store <= 16'd0;
else
if (onoff == 0)
count_store <= 16'b0;
else
if (storecompleted)
count_store <= 16'b0;
else
count_store <= count_store + store_clean_state;
*/
//%
//% count_store_extended
//%
always@(posedge clk or negedge reset_n)
if (reset_n == 0)
count_store_extended <= 17'd0;
else
if (onoff == 0)
count_store_extended <= 17'd0;
else
if (storecompleted)
count_store_extended <= 17'd0;
else
if ((store_fsm == WORK_STATE) || (store_fsm == WAIT_MEM))
count_store_extended <= count_store_extended + 1'b1;
else
count_store_extended <= count_store_extended;
//%
//% data_valid_out
//%
assign data_valid_out = ~store_clean_state && (store_fsm == WORK_STATE);
//%
//% data_out
//%
assign data_out = q_b_subcell_0 + q_b_subcell_1;
//%
//% clear_signal
//%
assign clear_signal = (store_clean_state == 1'b1);
assign count_store_int = count_store;
assign address_a_int = address_a;
ram_subcell
#( .HISTMEM_WORD(HISTMEM_WORD),
.HISTOGRAM_WIDTH(HISTOGRAM_WIDTH) )
ram_subcell_0 (
.clk(clk),
.reset_n(reset_n),
.data_a(data_a_d1),
.data_b({HISTOGRAM_WIDTH{1'b0}}),
.data_valid_in(data_valid_subcell_0),
.address_a_valid(~active_cell),
.memory_clear(clear_signal),
.enable_wire(onoff),
.q_b(q_b_subcell_0),
.q_a(),
.address_a(address_a),
.address_b(count_store[(HISTMEM_ADDR_WIDTH-1):0])
);
ram_subcell
#( .HISTMEM_WORD(HISTMEM_WORD),
.HISTOGRAM_WIDTH(HISTOGRAM_WIDTH) )
ram_subcell_1 (
.clk(clk),
.reset_n(reset_n),
.data_a(data_a_d1),
.data_b({HISTOGRAM_WIDTH{1'b0}}),
.data_valid_in(data_valid_subcell_1),
.address_a_valid(active_cell),
.memory_clear(clear_signal),
.enable_wire(onoff),
.q_b(q_b_subcell_1),
.q_a(),
.address_a(address_a),
.address_b(count_store[(HISTMEM_ADDR_WIDTH-1):0])
);
endmodule |
module oh_reg1 #(parameter DW = 1 // data width
)
( input nreset, //async active low reset
input clk, // clk
input en, // write enable
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
reg [DW-1:0] out_reg;
always @ (posedge clk or negedge nreset)
if(!nreset)
out_reg[DW-1:0] <= 'b0;
else if(en)
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
endmodule |
module ex_mem_buffer(
input wire clock,
input wire reset,
input wire[`SIGNAL_BUS] stall,
input wire ex_write_enable,
input wire[`REGS_ADDR_BUS] ex_write_addr,
input wire[`REGS_DATA_BUS] ex_write_data,
input wire ex_write_hilo_enable,
input wire[`REGS_DATA_BUS] ex_write_hi_data,
input wire[`REGS_DATA_BUS] ex_write_lo_data,
input wire[`DOUBLE_REGS_DATA_BUS] ex_current_result,
input wire[`CYCLE_BUS] ex_current_cycle,
input wire[`ALU_OPERATOR_BUS] ex_alu_operator,
input wire[`REGS_DATA_BUS] ex_alu_operand2,
input wire[`REGS_DATA_BUS] ex_ram_addr,
output reg mem_write_enable,
output reg[`REGS_ADDR_BUS] mem_write_addr,
output reg[`REGS_DATA_BUS] mem_write_data,
output reg mem_write_hilo_enable,
output reg[`REGS_DATA_BUS] mem_write_hi_data,
output reg[`REGS_DATA_BUS] mem_write_lo_data,
output reg[`DOUBLE_REGS_DATA_BUS] mem_last_result,
output reg[`CYCLE_BUS] mem_last_cycle,
output reg[`ALU_OPERATOR_BUS] mem_alu_operator,
output reg[`REGS_DATA_BUS] mem_alu_operand2,
output reg[`REGS_DATA_BUS] mem_ram_addr
);
always @ (posedge clock) begin
if (reset == `ENABLE) begin
mem_write_enable <= `DISABLE;
mem_write_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but 0 is used
mem_write_hilo_enable <= `DISABLE;
mem_write_hi_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_write_lo_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_last_result <= 0; // FIXME: {`ZERO_WORD, `ZEROWORD} should be used here, but 0 is used
mem_last_cycle <= 0; // FIXME: 2'b00 should be used here, but 0 is used
mem_alu_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but 0 is used
mem_alu_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_ram_addr <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end if (stall[3] == `ENABLE && stall[4] == `DISABLE) begin
mem_write_enable <= `DISABLE;
mem_write_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_write_addr <= 0; // FIXME: NOPRegAddr should be used here, but 0 is used
mem_write_hilo_enable <= `DISABLE;
mem_write_hi_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_write_lo_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_last_result <= ex_current_result;
mem_last_cycle <= ex_current_cycle;
mem_alu_operator <= 0; // FIXME: EXE_NOP_OP should be used here, but 0 is used
mem_alu_operand2 <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
mem_ram_addr <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end else if (stall[3] == `DISABLE) begin
mem_write_enable <= ex_write_enable;
mem_write_addr <= ex_write_addr;
mem_write_data <= ex_write_data;
mem_write_hilo_enable <= ex_write_hilo_enable;
mem_write_hi_data <= ex_write_hi_data;
mem_write_lo_data <= ex_write_lo_data;
mem_last_result <= 0; // FIXME: {`ZERO_WORD, `ZEROWORD} should be used here, but 0 is used
mem_last_cycle <= 0; // FIXME: 2'b00 should be used here, but 0 is used
mem_alu_operator <= ex_alu_operator;
mem_alu_operand2 <= ex_alu_operand2;
mem_ram_addr <= ex_ram_addr;
end else begin
mem_last_result <= ex_current_result;
mem_last_cycle <= ex_current_cycle;
end
end
endmodule |
module axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata ),
.s_axis_tx_tready (s_axis_tx_tready ),
.s_axis_tx_tvalid (s_axis_tx_tvalid ),
.s_axis_tx_tkeep (s_axis_tx_tkeep ),
.s_axis_tx_tlast (s_axis_tx_tlast ),
.s_axis_tx_tuser (s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td (trn_td ),
.trn_tsof (trn_tsof ),
.trn_teof (trn_teof ),
.trn_tsrc_rdy (trn_tsrc_rdy ),
.trn_tdst_rdy (trn_tdst_rdy ),
.trn_tsrc_dsc (trn_tsrc_dsc ),
.trn_trem (trn_trem ),
.trn_terrfwd (trn_terrfwd ),
.trn_tstr (trn_tstr ),
.trn_tecrc_gen (trn_tecrc_gen ),
.trn_lnk_up (trn_lnk_up ),
// System
//-----------
.tready_thrtl (tready_thrtl ),
.user_clk (user_clk ),
.user_rst (user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata ),
.s_axis_tx_tvalid (s_axis_tx_tvalid ),
.s_axis_tx_tuser (s_axis_tx_tuser ),
.s_axis_tx_tlast (s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok (user_turnoff_ok ),
.user_tcfg_gnt (user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av (trn_tbuf_av ),
.trn_tdst_rdy (trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req (trn_tcfg_req ),
.trn_tcfg_gnt (trn_tcfg_gnt ),
.trn_lnk_up (trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state (cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to (cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate (cfg_pmcsr_powerstate ),
.trn_rdllp_data (trn_rdllp_data ),
.trn_rdllp_src_rdy (trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff (cfg_to_turnoff ),
.cfg_turnoff_ok (cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl (tready_thrtl ),
.user_clk (user_clk ),
.user_rst (user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule |
module decoder
(
input [31:0] instruction,
output [5:0] op,
output [4:0] rs,
output [4:0] rt,
output [4:0] rd,
output [4:0] sham,
output [5:0] funct,
output [15:0] imm16,
output [25:0] imm26
);
`include "defines.vh"
assign op = instruction[`OP];
assign rs = instruction[`RS];
assign rt = instruction[`RT];
assign rd = instruction[`RD];
assign sham = instruction[`SHAM];
assign funct = instruction[`FUNCT];
assign imm16 = instruction[`IMM16];
assign imm26 = instruction[`IMM26];
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\DataTx_R_reg[0] ,
\DataTx_R_reg[0]_0 ,
\DataTx_R_reg[0]_1 ,
\DataTx_R_reg[0]_2 ,
\DataTx_R_reg[0]_3 ,
\DataTx_R_reg[0]_4 ,
data_rdy_bit_reg,
D,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
\s_axi_rdata_i_reg[31] ,
s_axi_rvalid_i_reg,
s_axi_bvalid_i_reg,
S_AXI_ACLK,
Q,
S_AXI_ARVALID,
s_axi_bvalid_i_reg_0,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
S_AXI_WVALID_0,
\state_reg[1] ,
S_AXI_ARESETN,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
\DataTx_R_reg[31] ,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ,
S_AXI_RREADY,
s_axi_rvalid_i_reg_0,
S_AXI_BREADY,
s_axi_bvalid_i_reg_1);
output \DataTx_R_reg[0] ;
output \DataTx_R_reg[0]_0 ;
output \DataTx_R_reg[0]_1 ;
output \DataTx_R_reg[0]_2 ;
output \DataTx_R_reg[0]_3 ;
output \DataTx_R_reg[0]_4 ;
output data_rdy_bit_reg;
output [1:0]D;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]\s_axi_rdata_i_reg[31] ;
output s_axi_rvalid_i_reg;
output s_axi_bvalid_i_reg;
input S_AXI_ACLK;
input [1:0]Q;
input S_AXI_ARVALID;
input s_axi_bvalid_i_reg_0;
input [0:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input S_AXI_WVALID_0;
input \state_reg[1] ;
input S_AXI_ARESETN;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]\DataTx_R_reg[31] ;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
input S_AXI_RREADY;
input s_axi_rvalid_i_reg_0;
input S_AXI_BREADY;
input s_axi_bvalid_i_reg_1;
wire Bus_RNW_reg_i_1_n_0;
wire [1:0]D;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire \DataTx_R_reg[0] ;
wire \DataTx_R_reg[0]_0 ;
wire \DataTx_R_reg[0]_1 ;
wire \DataTx_R_reg[0]_2 ;
wire \DataTx_R_reg[0]_3 ;
wire \DataTx_R_reg[0]_4 ;
wire [31:0]\DataTx_R_reg[31] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
wire [0:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire [1:0]Q;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARREADY_INST_0_i_1_n_0;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_RREADY;
wire S_AXI_WVALID;
wire S_AXI_WVALID_0;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire ce_expnd_i_4;
wire cs_ce_clr;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
wire s_axi_bvalid_i0;
wire s_axi_bvalid_i_reg;
wire s_axi_bvalid_i_reg_0;
wire s_axi_bvalid_i_reg_1;
wire \s_axi_rdata_i[0]_i_2_n_0 ;
wire \s_axi_rdata_i[0]_i_3_n_0 ;
wire \s_axi_rdata_i[0]_i_4_n_0 ;
wire \s_axi_rdata_i[10]_i_2_n_0 ;
wire \s_axi_rdata_i[11]_i_2_n_0 ;
wire \s_axi_rdata_i[12]_i_2_n_0 ;
wire \s_axi_rdata_i[13]_i_2_n_0 ;
wire \s_axi_rdata_i[14]_i_2_n_0 ;
wire \s_axi_rdata_i[15]_i_2_n_0 ;
wire \s_axi_rdata_i[16]_i_2_n_0 ;
wire \s_axi_rdata_i[17]_i_2_n_0 ;
wire \s_axi_rdata_i[18]_i_2_n_0 ;
wire \s_axi_rdata_i[19]_i_2_n_0 ;
wire \s_axi_rdata_i[1]_i_2_n_0 ;
wire \s_axi_rdata_i[20]_i_2_n_0 ;
wire \s_axi_rdata_i[21]_i_2_n_0 ;
wire \s_axi_rdata_i[22]_i_2_n_0 ;
wire \s_axi_rdata_i[23]_i_2_n_0 ;
wire \s_axi_rdata_i[23]_i_3_n_0 ;
wire \s_axi_rdata_i[23]_i_4_n_0 ;
wire \s_axi_rdata_i[2]_i_2_n_0 ;
wire \s_axi_rdata_i[3]_i_2_n_0 ;
wire \s_axi_rdata_i[4]_i_2_n_0 ;
wire \s_axi_rdata_i[5]_i_2_n_0 ;
wire \s_axi_rdata_i[6]_i_2_n_0 ;
wire \s_axi_rdata_i[7]_i_2_n_0 ;
wire \s_axi_rdata_i[8]_i_2_n_0 ;
wire \s_axi_rdata_i[9]_i_2_n_0 ;
wire [31:0]\s_axi_rdata_i_reg[31] ;
wire s_axi_rvalid_i0;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire start;
wire \state_reg[1] ;
LUT6 #(
.INIT(64'hFEFFFFFF02020202))
Bus_RNW_reg_i_1
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_AWVALID),
.I4(S_AXI_WVALID),
.I5(\DataTx_R_reg[0]_4 ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\DataTx_R_reg[0]_4 ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000004))
\DataTx_L[31]_i_1
(.I0(\DataTx_R_reg[0]_0 ),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[0]_4 ),
.I3(\DataTx_R_reg[0]_2 ),
.I4(\DataTx_R_reg[0]_3 ),
.I5(\DataTx_R_reg[0] ),
.O(\DataTx_L_reg[0] ));
LUT6 #(
.INIT(64'h0000000000000004))
\DataTx_R[31]_i_1
(.I0(\DataTx_R_reg[0]_1 ),
.I1(\DataTx_R_reg[0]_0 ),
.I2(\DataTx_R_reg[0]_4 ),
.I3(\DataTx_R_reg[0]_2 ),
.I4(\DataTx_R_reg[0]_3 ),
.I5(\DataTx_R_reg[0] ),
.O(E));
LUT6 #(
.INIT(64'h020202020202FF02))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_4));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_4),
.Q(\DataTx_R_reg[0]_3 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h08080808FF080808))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_3),
.Q(\DataTx_R_reg[0]_2 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h08080808FF080808))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[1]),
.I2(S_AXI_ARADDR[0]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[1]),
.I5(S_AXI_AWADDR[0]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_2),
.Q(\DataTx_R_reg[0]_1 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFF80808080808080))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_1));
LUT4 #(
.INIT(16'h0002))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_ARADDR[2]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3
(.I0(S_AXI_ARVALID),
.I1(S_AXI_WVALID),
.I2(S_AXI_AWVALID),
.I3(Q[1]),
.I4(Q[0]),
.I5(S_AXI_AWADDR[2]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_1),
.Q(\DataTx_R_reg[0]_0 ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hFD))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(S_AXI_ARESETN),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I2(S_AXI_ARREADY_INST_0_i_1_n_0),
.O(cs_ce_clr));
LUT5 #(
.INIT(32'h03020202))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_AWVALID),
.I4(S_AXI_WVALID),
.O(start));
LUT5 #(
.INIT(32'hAAAAAEAA))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ),
.I2(S_AXI_AWADDR[1]),
.I3(S_AXI_AWADDR[2]),
.I4(S_AXI_AWADDR[0]),
.O(ce_expnd_i_0));
LUT6 #(
.INIT(64'h0000000000000400))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4
(.I0(S_AXI_ARADDR[0]),
.I1(S_AXI_ARADDR[2]),
.I2(S_AXI_ARADDR[1]),
.I3(S_AXI_ARVALID),
.I4(Q[0]),
.I5(Q[1]),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ));
LUT5 #(
.INIT(32'h00001000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5
(.I0(Q[0]),
.I1(Q[1]),
.I2(S_AXI_AWVALID),
.I3(S_AXI_WVALID),
.I4(S_AXI_ARVALID),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_0),
.Q(\DataTx_R_reg[0] ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF8))
S_AXI_ARREADY_INST_0
(.I0(\DataTx_R_reg[0]_4 ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.O(S_AXI_ARREADY));
LUT5 #(
.INIT(32'hFFFFFFFE))
S_AXI_ARREADY_INST_0_i_1
(.I0(\DataTx_R_reg[0] ),
.I1(\DataTx_R_reg[0]_3 ),
.I2(\DataTx_R_reg[0]_2 ),
.I3(\DataTx_R_reg[0]_0 ),
.I4(\DataTx_R_reg[0]_1 ),
.O(S_AXI_ARREADY_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF4))
S_AXI_AWREADY_INST_0
(.I0(\DataTx_R_reg[0]_4 ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.O(S_AXI_AWREADY));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFFFE))
data_rdy_bit_i_2
(.I0(\DataTx_R_reg[0] ),
.I1(\DataTx_R_reg[0]_3 ),
.I2(\DataTx_R_reg[0]_2 ),
.I3(\DataTx_R_reg[0]_4 ),
.O(data_rdy_bit_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFFFF))
data_rdy_bit_i_3
(.I0(\DataTx_R_reg[0]_3 ),
.I1(\DataTx_R_reg[0]_2 ),
.I2(\DataTx_R_reg[0]_1 ),
.I3(\DataTx_R_reg[0]_0 ),
.I4(\DataTx_R_reg[0] ),
.I5(\DataTx_R_reg[0]_4 ),
.O(data_rdy_bit_reg));
LUT3 #(
.INIT(8'hBA))
s_axi_bvalid_i_i_1
(.I0(s_axi_bvalid_i0),
.I1(S_AXI_BREADY),
.I2(s_axi_bvalid_i_reg_1),
.O(s_axi_bvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000AE00))
s_axi_bvalid_i_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\DataTx_R_reg[0]_4 ),
.I3(Q[1]),
.I4(Q[0]),
.O(s_axi_bvalid_i0));
LUT6 #(
.INIT(64'hFFAAEAAAEAAAEAAA))
\s_axi_rdata_i[0]_i_1
(.I0(\s_axi_rdata_i[0]_i_2_n_0 ),
.I1(data_rdy_bit),
.I2(\DataTx_R_reg[0] ),
.I3(\s_axi_rdata_i[0]_i_3_n_0 ),
.I4(\DataTx_R_reg[0]_0 ),
.I5(\DataTx_R_reg[31] [0]),
.O(\s_axi_rdata_i_reg[31] [0]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_rdata_i[0]_i_2
(.I0(\s_axi_rdata_i[0]_i_4_n_0 ),
.I1(\DataTx_L_reg[31] [0]),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [0]),
.I4(\DataRx_L_reg[23] [0]),
.I5(\s_axi_rdata_i[23]_i_2_n_0 ),
.O(\s_axi_rdata_i[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\s_axi_rdata_i[0]_i_3
(.I0(\DataTx_R_reg[0]_4 ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.O(\s_axi_rdata_i[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[0]_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_1 ),
.O(\s_axi_rdata_i[0]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[10]_i_1
(.I0(\DataRx_L_reg[23] [10]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [10]),
.I4(\s_axi_rdata_i[10]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [10]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[10]_i_2
(.I0(\DataTx_L_reg[31] [10]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [10]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[11]_i_1
(.I0(\DataRx_L_reg[23] [11]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [11]),
.I4(\s_axi_rdata_i[11]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [11]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[11]_i_2
(.I0(\DataTx_L_reg[31] [11]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [11]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[11]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[12]_i_1
(.I0(\DataRx_L_reg[23] [12]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [12]),
.I4(\s_axi_rdata_i[12]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [12]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[12]_i_2
(.I0(\DataTx_L_reg[31] [12]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [12]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[13]_i_1
(.I0(\DataRx_L_reg[23] [13]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [13]),
.I4(\s_axi_rdata_i[13]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [13]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[13]_i_2
(.I0(\DataTx_L_reg[31] [13]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [13]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[14]_i_1
(.I0(\DataRx_L_reg[23] [14]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [14]),
.I4(\s_axi_rdata_i[14]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [14]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[14]_i_2
(.I0(\DataTx_L_reg[31] [14]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [14]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[15]_i_1
(.I0(\DataRx_L_reg[23] [15]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [15]),
.I4(\s_axi_rdata_i[15]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [15]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[15]_i_2
(.I0(\DataTx_L_reg[31] [15]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [15]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[16]_i_1
(.I0(\DataRx_L_reg[23] [16]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [16]),
.I4(\s_axi_rdata_i[16]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [16]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[16]_i_2
(.I0(\DataTx_L_reg[31] [16]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [16]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[16]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[17]_i_1
(.I0(\DataRx_L_reg[23] [17]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [17]),
.I4(\s_axi_rdata_i[17]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [17]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[17]_i_2
(.I0(\DataTx_L_reg[31] [17]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [17]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[17]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[18]_i_1
(.I0(\DataRx_L_reg[23] [18]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [18]),
.I4(\s_axi_rdata_i[18]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [18]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[18]_i_2
(.I0(\DataTx_L_reg[31] [18]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [18]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[18]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[19]_i_1
(.I0(\DataRx_L_reg[23] [19]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [19]),
.I4(\s_axi_rdata_i[19]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [19]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[19]_i_2
(.I0(\DataTx_L_reg[31] [19]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [19]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[19]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[1]_i_1
(.I0(\DataRx_L_reg[23] [1]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [1]),
.I4(\s_axi_rdata_i[1]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [1]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[1]_i_2
(.I0(\DataTx_L_reg[31] [1]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [1]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[20]_i_1
(.I0(\DataRx_L_reg[23] [20]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [20]),
.I4(\s_axi_rdata_i[20]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [20]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[20]_i_2
(.I0(\DataTx_L_reg[31] [20]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [20]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[20]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[21]_i_1
(.I0(\DataRx_L_reg[23] [21]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [21]),
.I4(\s_axi_rdata_i[21]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [21]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[21]_i_2
(.I0(\DataTx_L_reg[31] [21]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [21]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[21]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[22]_i_1
(.I0(\DataRx_L_reg[23] [22]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [22]),
.I4(\s_axi_rdata_i[22]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [22]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[22]_i_2
(.I0(\DataTx_L_reg[31] [22]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [22]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[22]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[23]_i_1
(.I0(\DataRx_L_reg[23] [23]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [23]),
.I4(\s_axi_rdata_i[23]_i_4_n_0 ),
.O(\s_axi_rdata_i_reg[31] [23]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[23]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_3 ),
.O(\s_axi_rdata_i[23]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[23]_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_2 ),
.O(\s_axi_rdata_i[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[23]_i_4
(.I0(\DataTx_L_reg[31] [23]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [23]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[24]_i_1
(.I0(\DataTx_L_reg[31] [24]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [24]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [24]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[25]_i_1
(.I0(\DataTx_L_reg[31] [25]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [25]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [25]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[26]_i_1
(.I0(\DataTx_L_reg[31] [26]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [26]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [26]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[27]_i_1
(.I0(\DataTx_L_reg[31] [27]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [27]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [27]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[28]_i_1
(.I0(\DataTx_L_reg[31] [28]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [28]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [28]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[29]_i_1
(.I0(\DataTx_L_reg[31] [29]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [29]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [29]));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[2]_i_1
(.I0(\DataRx_L_reg[23] [2]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [2]),
.I4(\s_axi_rdata_i[2]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [2]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[2]_i_2
(.I0(\DataTx_L_reg[31] [2]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [2]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[30]_i_1
(.I0(\DataTx_L_reg[31] [30]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [30]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [30]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[31]_i_2
(.I0(\DataTx_L_reg[31] [31]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [31]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [31]));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[3]_i_1
(.I0(\DataRx_L_reg[23] [3]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [3]),
.I4(\s_axi_rdata_i[3]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [3]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[3]_i_2
(.I0(\DataTx_L_reg[31] [3]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [3]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[4]_i_1
(.I0(\DataRx_L_reg[23] [4]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [4]),
.I4(\s_axi_rdata_i[4]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [4]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[4]_i_2
(.I0(\DataTx_L_reg[31] [4]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [4]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[5]_i_1
(.I0(\DataRx_L_reg[23] [5]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [5]),
.I4(\s_axi_rdata_i[5]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [5]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[5]_i_2
(.I0(\DataTx_L_reg[31] [5]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [5]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[6]_i_1
(.I0(\DataRx_L_reg[23] [6]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [6]),
.I4(\s_axi_rdata_i[6]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [6]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[6]_i_2
(.I0(\DataTx_L_reg[31] [6]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [6]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[7]_i_1
(.I0(\DataRx_L_reg[23] [7]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [7]),
.I4(\s_axi_rdata_i[7]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [7]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[7]_i_2
(.I0(\DataTx_L_reg[31] [7]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [7]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[8]_i_1
(.I0(\DataRx_L_reg[23] [8]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [8]),
.I4(\s_axi_rdata_i[8]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [8]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[8]_i_2
(.I0(\DataTx_L_reg[31] [8]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [8]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[9]_i_1
(.I0(\DataRx_L_reg[23] [9]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [9]),
.I4(\s_axi_rdata_i[9]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [9]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[9]_i_2
(.I0(\DataTx_L_reg[31] [9]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [9]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[9]_i_2_n_0 ));
LUT3 #(
.INIT(8'hBA))
s_axi_rvalid_i_i_1
(.I0(s_axi_rvalid_i0),
.I1(S_AXI_RREADY),
.I2(s_axi_rvalid_i_reg_0),
.O(s_axi_rvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000EA00))
s_axi_rvalid_i_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\DataTx_R_reg[0]_4 ),
.I3(Q[0]),
.I4(Q[1]),
.O(s_axi_rvalid_i0));
LUT4 #(
.INIT(16'hFFF4))
\state[0]_i_1
(.I0(Q[1]),
.I1(S_AXI_ARVALID),
.I2(s_axi_bvalid_i0),
.I3(s_axi_bvalid_i_reg_0),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF4454))
\state[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(S_AXI_WVALID_0),
.I3(S_AXI_ARVALID),
.I4(\state_reg[1] ),
.I5(s_axi_rvalid_i0),
.O(D[1]));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg,
S_AXI_RVALID,
S_AXI_BVALID,
data_rdy_bit_reg,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
S_AXI_RDATA,
S_AXI_ACLK,
SR,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
Q,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] );
output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
output Bus_RNW_reg;
output S_AXI_RVALID;
output S_AXI_BVALID;
output data_rdy_bit_reg;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]S_AXI_RDATA;
input S_AXI_ACLK;
input [0:0]SR;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]Q;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire Bus_RNW_reg;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [31:0]Q;
wire [0:0]SR;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire S_AXI_WVALID;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.\DataRx_L_reg[23] (\DataRx_L_reg[23] ),
.\DataRx_R_reg[23] (\DataRx_R_reg[23] ),
.\DataTx_L_reg[0] (\DataTx_L_reg[0] ),
.\DataTx_L_reg[31] (\DataTx_L_reg[31] ),
.\DataTx_R_reg[0] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\DataTx_R_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\DataTx_R_reg[0]_1 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\DataTx_R_reg[0]_2 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\DataTx_R_reg[0]_3 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\DataTx_R_reg[0]_4 (Bus_RNW_reg),
.E(E),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.Q(Q),
.SR(SR),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WVALID(S_AXI_WVALID),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(data_rdy_bit_reg),
.data_rdy_bit_reg_0(data_rdy_bit_reg_0));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl
(out,
S_AXI_RDATA,
S_AXI_AWREADY,
S_AXI_ARREADY,
S_AXI_BVALID,
S_AXI_RVALID,
SDATA_O,
S_AXI_ACLK,
SDATA_I,
S_AXI_WDATA,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID);
output [1:0]out;
output [31:0]S_AXI_RDATA;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output S_AXI_BVALID;
output S_AXI_RVALID;
output SDATA_O;
input S_AXI_ACLK;
input SDATA_I;
input [31:0]S_AXI_WDATA;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_8;
wire [23:0]DataRx_L;
wire [23:0]DataRx_R;
wire [31:0]DataTx_L;
wire [31:0]DataTx_R;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire SDATA_I;
wire SDATA_O;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire [31:0]S_AXI_WDATA;
wire S_AXI_WVALID;
wire USER_LOGIC_I_n_0;
wire USER_LOGIC_I_n_69;
wire data_rdy_bit;
wire [1:0]out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\DataRx_L_reg[23] (DataRx_L),
.\DataRx_R_reg[23] (DataRx_R),
.\DataTx_L_reg[0] (AXI_LITE_IPIF_I_n_12),
.\DataTx_L_reg[31] (DataTx_L),
.E(AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (USER_LOGIC_I_n_0),
.Q(DataTx_R),
.SR(USER_LOGIC_I_n_69),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WVALID(S_AXI_WVALID),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(AXI_LITE_IPIF_I_n_8),
.data_rdy_bit_reg_0(AXI_LITE_IPIF_I_n_13));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic USER_LOGIC_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.E(AXI_LITE_IPIF_I_n_12),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (AXI_LITE_IPIF_I_n_8),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (AXI_LITE_IPIF_I_n_13),
.Q(out),
.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.SR(USER_LOGIC_I_n_69),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_WDATA(S_AXI_WDATA),
.data_rdy_bit(data_rdy_bit),
.\s_axi_rdata_i_reg[23] (DataRx_L),
.\s_axi_rdata_i_reg[23]_0 (DataRx_R),
.\s_axi_rdata_i_reg[24] (USER_LOGIC_I_n_0),
.\s_axi_rdata_i_reg[31] (DataTx_L),
.\s_axi_rdata_i_reg[31]_0 (DataTx_R));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser
(lrclk_d1,
sclk_d1,
E,
\rdata_reg_reg[23]_0 ,
\bit_cntr_reg[4]_0 ,
sdata_reg_reg,
\FSM_onehot_iis_state_reg[0] ,
data_rdy_bit_reg,
\FSM_onehot_iis_state_reg[0]_0 ,
\DataRx_L_reg[23] ,
\DataRx_R_reg[23] ,
Q,
S_AXI_ACLK,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
out,
data_rdy_bit,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
S_AXI_ARESETN,
SDATA_I);
output lrclk_d1;
output sclk_d1;
output [0:0]E;
output [0:0]\rdata_reg_reg[23]_0 ;
output [0:0]\bit_cntr_reg[4]_0 ;
output sdata_reg_reg;
output \FSM_onehot_iis_state_reg[0] ;
output data_rdy_bit_reg;
output \FSM_onehot_iis_state_reg[0]_0 ;
output [23:0]\DataRx_L_reg[23] ;
output [23:0]\DataRx_R_reg[23] ;
input [1:0]Q;
input S_AXI_ACLK;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input [2:0]out;
input data_rdy_bit;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input S_AXI_ARESETN;
input SDATA_I;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]E;
wire \FSM_onehot_iis_state_reg[0] ;
wire \FSM_onehot_iis_state_reg[0]_0 ;
wire \FSM_sequential_iis_state[0]_i_1_n_0 ;
wire \FSM_sequential_iis_state[1]_i_1_n_0 ;
wire \FSM_sequential_iis_state[2]_i_1_n_0 ;
wire \FSM_sequential_iis_state[2]_i_2_n_0 ;
wire \FSM_sequential_iis_state[2]_i_3_n_0 ;
wire \FSM_sequential_iis_state[2]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [1:0]Q;
wire SDATA_I;
wire S_AXI_ACLK;
wire S_AXI_ARESETN;
wire \bit_cntr[4]_i_1_n_0 ;
wire [0:0]\bit_cntr_reg[4]_0 ;
wire [4:0]bit_cntr_reg__0;
wire bit_rdy;
wire data_rdy_bit;
wire data_rdy_bit_i_4_n_0;
wire data_rdy_bit_reg;
wire eqOp;
(* RTL_KEEP = "yes" *) wire [2:0]iis_state;
wire ldata_reg;
wire ldata_reg0;
wire lrclk_d1;
wire [2:0]out;
wire [4:0]plusOp__1;
wire rdata_reg0;
wire [0:0]\rdata_reg_reg[23]_0 ;
wire sclk_d1;
wire sdata_reg_reg;
LUT4 #(
.INIT(16'h0080))
\DataRx_L[23]_i_1
(.I0(eqOp),
.I1(iis_state[2]),
.I2(iis_state[1]),
.I3(iis_state[0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000020))
\DataRx_L[23]_i_2
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[4]),
.I3(bit_cntr_reg__0[1]),
.I4(bit_cntr_reg__0[2]),
.O(eqOp));
LUT3 #(
.INIT(8'h40))
\FSM_onehot_iis_state[4]_i_3
(.I0(lrclk_d1),
.I1(Q[1]),
.I2(out[1]),
.O(\FSM_onehot_iis_state_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hDF))
\FSM_onehot_iis_state[4]_i_5
(.I0(lrclk_d1),
.I1(Q[1]),
.I2(out[0]),
.O(\FSM_onehot_iis_state_reg[0] ));
LUT6 #(
.INIT(64'h75777F7745444044))
\FSM_sequential_iis_state[0]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[0]),
.O(\FSM_sequential_iis_state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3A7B3F7B0A480048))
\FSM_sequential_iis_state[1]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[1]),
.O(\FSM_sequential_iis_state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3FB33FB30F800080))
\FSM_sequential_iis_state[2]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[2]),
.O(\FSM_sequential_iis_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFA33FF000A330F))
\FSM_sequential_iis_state[2]_i_2
(.I0(bit_rdy),
.I1(\FSM_sequential_iis_state[2]_i_4_n_0 ),
.I2(iis_state[2]),
.I3(iis_state[0]),
.I4(iis_state[1]),
.I5(eqOp),
.O(\FSM_sequential_iis_state[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h22A222A2EEAE22A2))
\FSM_sequential_iis_state[2]_i_3
(.I0(bit_rdy),
.I1(iis_state[2]),
.I2(iis_state[0]),
.I3(iis_state[1]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\FSM_sequential_iis_state[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hB))
\FSM_sequential_iis_state[2]_i_4
(.I0(Q[1]),
.I1(lrclk_d1),
.O(\FSM_sequential_iis_state[2]_i_4_n_0 ));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[0]_i_1_n_0 ),
.Q(iis_state[0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[1]_i_1_n_0 ),
.Q(iis_state[1]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[2]_i_1_n_0 ),
.Q(iis_state[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\bit_cntr[0]_i_1
(.I0(bit_cntr_reg__0[0]),
.O(plusOp__1[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\bit_cntr[1]_i_1
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\bit_cntr[2]_i_1
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h6CCC))
\bit_cntr[3]_i_1
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[3]),
.I2(bit_cntr_reg__0[0]),
.I3(bit_cntr_reg__0[2]),
.O(plusOp__1[3]));
LUT3 #(
.INIT(8'hD7))
\bit_cntr[4]_i_1
(.I0(iis_state[1]),
.I1(iis_state[0]),
.I2(iis_state[2]),
.O(\bit_cntr[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\bit_cntr[4]_i_2
(.I0(Q[0]),
.I1(sclk_d1),
.O(bit_rdy));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h2))
\bit_cntr[4]_i_2__0
(.I0(sclk_d1),
.I1(Q[0]),
.O(\bit_cntr_reg[4]_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h78F0F0F0))
\bit_cntr[4]_i_3
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[2]),
.I2(bit_cntr_reg__0[4]),
.I3(bit_cntr_reg__0[1]),
.I4(bit_cntr_reg__0[0]),
.O(plusOp__1[4]));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[0]),
.Q(bit_cntr_reg__0[0]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[1]),
.Q(bit_cntr_reg__0[1]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[2]),
.Q(bit_cntr_reg__0[2]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[3]),
.Q(bit_cntr_reg__0[3]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[4]),
.Q(bit_cntr_reg__0[4]),
.R(\bit_cntr[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCC00EA0000000000))
data_rdy_bit_i_1
(.I0(data_rdy_bit),
.I1(E),
.I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I4(data_rdy_bit_i_4_n_0),
.I5(S_AXI_ARESETN),
.O(data_rdy_bit_reg));
LUT6 #(
.INIT(64'h0000000090000000))
data_rdy_bit_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I2(eqOp),
.I3(iis_state[2]),
.I4(iis_state[1]),
.I5(iis_state[0]),
.O(data_rdy_bit_i_4_n_0));
LUT3 #(
.INIT(8'h01))
\ldata_reg[23]_i_1
(.I0(iis_state[1]),
.I1(iis_state[0]),
.I2(iis_state[2]),
.O(ldata_reg));
LUT5 #(
.INIT(32'h00004000))
\ldata_reg[23]_i_2
(.I0(iis_state[2]),
.I1(iis_state[0]),
.I2(iis_state[1]),
.I3(Q[0]),
.I4(sclk_d1),
.O(ldata_reg0));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(SDATA_I),
.Q(\DataRx_L_reg[23] [0]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [9]),
.Q(\DataRx_L_reg[23] [10]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [10]),
.Q(\DataRx_L_reg[23] [11]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [11]),
.Q(\DataRx_L_reg[23] [12]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [12]),
.Q(\DataRx_L_reg[23] [13]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [13]),
.Q(\DataRx_L_reg[23] [14]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [14]),
.Q(\DataRx_L_reg[23] [15]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [15]),
.Q(\DataRx_L_reg[23] [16]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [16]),
.Q(\DataRx_L_reg[23] [17]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [17]),
.Q(\DataRx_L_reg[23] [18]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [18]),
.Q(\DataRx_L_reg[23] [19]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [0]),
.Q(\DataRx_L_reg[23] [1]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [19]),
.Q(\DataRx_L_reg[23] [20]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [20]),
.Q(\DataRx_L_reg[23] [21]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [21]),
.Q(\DataRx_L_reg[23] [22]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [22]),
.Q(\DataRx_L_reg[23] [23]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [1]),
.Q(\DataRx_L_reg[23] [2]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [2]),
.Q(\DataRx_L_reg[23] [3]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [3]),
.Q(\DataRx_L_reg[23] [4]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [4]),
.Q(\DataRx_L_reg[23] [5]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [5]),
.Q(\DataRx_L_reg[23] [6]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [6]),
.Q(\DataRx_L_reg[23] [7]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [7]),
.Q(\DataRx_L_reg[23] [8]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [8]),
.Q(\DataRx_L_reg[23] [9]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
lrclk_d1_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Q[1]),
.Q(lrclk_d1),
.R(1'b0));
LUT5 #(
.INIT(32'h00004000))
\rdata_reg[23]_i_1
(.I0(iis_state[0]),
.I1(iis_state[1]),
.I2(iis_state[2]),
.I3(Q[0]),
.I4(sclk_d1),
.O(rdata_reg0));
LUT6 #(
.INIT(64'h4040FF4040404040))
\rdata_reg[23]_i_1__0
(.I0(Q[0]),
.I1(sclk_d1),
.I2(out[2]),
.I3(out[0]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\rdata_reg_reg[23]_0 ));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(SDATA_I),
.Q(\DataRx_R_reg[23] [0]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [9]),
.Q(\DataRx_R_reg[23] [10]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [10]),
.Q(\DataRx_R_reg[23] [11]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [11]),
.Q(\DataRx_R_reg[23] [12]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [12]),
.Q(\DataRx_R_reg[23] [13]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [13]),
.Q(\DataRx_R_reg[23] [14]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [14]),
.Q(\DataRx_R_reg[23] [15]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [15]),
.Q(\DataRx_R_reg[23] [16]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [16]),
.Q(\DataRx_R_reg[23] [17]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [17]),
.Q(\DataRx_R_reg[23] [18]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [18]),
.Q(\DataRx_R_reg[23] [19]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [0]),
.Q(\DataRx_R_reg[23] [1]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [19]),
.Q(\DataRx_R_reg[23] [20]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [20]),
.Q(\DataRx_R_reg[23] [21]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [21]),
.Q(\DataRx_R_reg[23] [22]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [22]),
.Q(\DataRx_R_reg[23] [23]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [1]),
.Q(\DataRx_R_reg[23] [2]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [2]),
.Q(\DataRx_R_reg[23] [3]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [3]),
.Q(\DataRx_R_reg[23] [4]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [4]),
.Q(\DataRx_R_reg[23] [5]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [5]),
.Q(\DataRx_R_reg[23] [6]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [6]),
.Q(\DataRx_R_reg[23] [7]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [7]),
.Q(\DataRx_R_reg[23] [8]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [8]),
.Q(\DataRx_R_reg[23] [9]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
sclk_d1_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Q[0]),
.Q(sclk_d1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hB))
sdata_reg_i_2
(.I0(Q[0]),
.I1(sclk_d1),
.O(sdata_reg_reg));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser
(SDATA_O,
out,
S_AXI_ACLK,
Q,
sclk_d1,
lrclk_d1,
\DataTx_L_reg[23] ,
\DataTx_R_reg[23] ,
\clk_cntr_reg[4] ,
lrclk_d1_reg,
lrclk_d1_reg_0,
E,
sclk_d1_reg);
output SDATA_O;
output [2:0]out;
input S_AXI_ACLK;
input [1:0]Q;
input sclk_d1;
input lrclk_d1;
input [23:0]\DataTx_L_reg[23] ;
input [23:0]\DataTx_R_reg[23] ;
input \clk_cntr_reg[4] ;
input lrclk_d1_reg;
input lrclk_d1_reg_0;
input [0:0]E;
input [0:0]sclk_d1_reg;
wire [23:0]\DataTx_L_reg[23] ;
wire [23:0]\DataTx_R_reg[23] ;
wire [0:0]E;
wire \FSM_onehot_iis_state[1]_i_1_n_0 ;
wire \FSM_onehot_iis_state[2]_i_1_n_0 ;
wire \FSM_onehot_iis_state[3]_i_1_n_0 ;
wire \FSM_onehot_iis_state[4]_i_1_n_0 ;
wire \FSM_onehot_iis_state[4]_i_2_n_0 ;
wire [1:0]Q;
wire SDATA_O;
wire S_AXI_ACLK;
wire \bit_cntr[4]_i_1__0_n_0 ;
wire [4:0]bit_cntr_reg__0;
wire \clk_cntr_reg[4] ;
wire eqOp;
(* RTL_KEEP = "yes" *) wire ldata_reg;
wire \ldata_reg[0]_i_1_n_0 ;
wire \ldata_reg[10]_i_1_n_0 ;
wire \ldata_reg[11]_i_1_n_0 ;
wire \ldata_reg[12]_i_1_n_0 ;
wire \ldata_reg[13]_i_1_n_0 ;
wire \ldata_reg[14]_i_1_n_0 ;
wire \ldata_reg[15]_i_1_n_0 ;
wire \ldata_reg[16]_i_1_n_0 ;
wire \ldata_reg[17]_i_1_n_0 ;
wire \ldata_reg[18]_i_1_n_0 ;
wire \ldata_reg[19]_i_1_n_0 ;
wire \ldata_reg[1]_i_1_n_0 ;
wire \ldata_reg[20]_i_1_n_0 ;
wire \ldata_reg[21]_i_1_n_0 ;
wire \ldata_reg[22]_i_1_n_0 ;
wire \ldata_reg[23]_i_1__0_n_0 ;
wire \ldata_reg[23]_i_2__0_n_0 ;
wire \ldata_reg[2]_i_1_n_0 ;
wire \ldata_reg[3]_i_1_n_0 ;
wire \ldata_reg[4]_i_1_n_0 ;
wire \ldata_reg[5]_i_1_n_0 ;
wire \ldata_reg[6]_i_1_n_0 ;
wire \ldata_reg[7]_i_1_n_0 ;
wire \ldata_reg[8]_i_1_n_0 ;
wire \ldata_reg[9]_i_1_n_0 ;
wire \ldata_reg_reg_n_0_[0] ;
wire \ldata_reg_reg_n_0_[10] ;
wire \ldata_reg_reg_n_0_[11] ;
wire \ldata_reg_reg_n_0_[12] ;
wire \ldata_reg_reg_n_0_[13] ;
wire \ldata_reg_reg_n_0_[14] ;
wire \ldata_reg_reg_n_0_[15] ;
wire \ldata_reg_reg_n_0_[16] ;
wire \ldata_reg_reg_n_0_[17] ;
wire \ldata_reg_reg_n_0_[18] ;
wire \ldata_reg_reg_n_0_[19] ;
wire \ldata_reg_reg_n_0_[1] ;
wire \ldata_reg_reg_n_0_[20] ;
wire \ldata_reg_reg_n_0_[21] ;
wire \ldata_reg_reg_n_0_[22] ;
wire \ldata_reg_reg_n_0_[2] ;
wire \ldata_reg_reg_n_0_[3] ;
wire \ldata_reg_reg_n_0_[4] ;
wire \ldata_reg_reg_n_0_[5] ;
wire \ldata_reg_reg_n_0_[6] ;
wire \ldata_reg_reg_n_0_[7] ;
wire \ldata_reg_reg_n_0_[8] ;
wire \ldata_reg_reg_n_0_[9] ;
wire lrclk_d1;
wire lrclk_d1_reg;
wire lrclk_d1_reg_0;
(* RTL_KEEP = "yes" *) wire [2:0]out;
(* RTL_KEEP = "yes" *) wire p_0_in2_in;
wire [23:0]p_1_in;
wire p_2_in;
wire [4:0]plusOp__2;
wire \rdata_reg_reg_n_0_[0] ;
wire \rdata_reg_reg_n_0_[10] ;
wire \rdata_reg_reg_n_0_[11] ;
wire \rdata_reg_reg_n_0_[12] ;
wire \rdata_reg_reg_n_0_[13] ;
wire \rdata_reg_reg_n_0_[14] ;
wire \rdata_reg_reg_n_0_[15] ;
wire \rdata_reg_reg_n_0_[16] ;
wire \rdata_reg_reg_n_0_[17] ;
wire \rdata_reg_reg_n_0_[18] ;
wire \rdata_reg_reg_n_0_[19] ;
wire \rdata_reg_reg_n_0_[1] ;
wire \rdata_reg_reg_n_0_[20] ;
wire \rdata_reg_reg_n_0_[21] ;
wire \rdata_reg_reg_n_0_[22] ;
wire \rdata_reg_reg_n_0_[23] ;
wire \rdata_reg_reg_n_0_[2] ;
wire \rdata_reg_reg_n_0_[3] ;
wire \rdata_reg_reg_n_0_[4] ;
wire \rdata_reg_reg_n_0_[5] ;
wire \rdata_reg_reg_n_0_[6] ;
wire \rdata_reg_reg_n_0_[7] ;
wire \rdata_reg_reg_n_0_[8] ;
wire \rdata_reg_reg_n_0_[9] ;
wire sclk_d1;
wire [0:0]sclk_d1_reg;
wire sdata_reg_i_1_n_0;
LUT5 #(
.INIT(32'hAAAAAABA))
\FSM_onehot_iis_state[1]_i_1
(.I0(ldata_reg),
.I1(p_0_in2_in),
.I2(out[2]),
.I3(out[1]),
.I4(out[0]),
.O(\FSM_onehot_iis_state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0ACA))
\FSM_onehot_iis_state[2]_i_1
(.I0(p_0_in2_in),
.I1(out[0]),
.I2(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.I3(ldata_reg),
.O(\FSM_onehot_iis_state[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\FSM_onehot_iis_state[3]_i_1
(.I0(p_0_in2_in),
.I1(ldata_reg),
.I2(out[0]),
.O(\FSM_onehot_iis_state[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEEFFFFFEEEFFFF))
\FSM_onehot_iis_state[4]_i_1
(.I0(ldata_reg),
.I1(lrclk_d1_reg),
.I2(out[2]),
.I3(eqOp),
.I4(lrclk_d1_reg_0),
.I5(p_0_in2_in),
.O(\FSM_onehot_iis_state[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0010))
\FSM_onehot_iis_state[4]_i_2
(.I0(ldata_reg),
.I1(p_0_in2_in),
.I2(out[1]),
.I3(out[0]),
.O(\FSM_onehot_iis_state[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h02000000))
\FSM_onehot_iis_state[4]_i_4
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.I2(bit_cntr_reg__0[2]),
.I3(bit_cntr_reg__0[4]),
.I4(bit_cntr_reg__0[3]),
.O(eqOp));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b1))
\FSM_onehot_iis_state_reg[0]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(1'b0),
.Q(ldata_reg),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[1]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[1]_i_1_n_0 ),
.Q(out[0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_onehot_iis_state[2]_i_1_n_0 ),
.Q(p_0_in2_in),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[3]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[3]_i_1_n_0 ),
.Q(out[1]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[4]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[4]_i_2_n_0 ),
.Q(out[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT1 #(
.INIT(2'h1))
\bit_cntr[0]_i_1__0
(.I0(bit_cntr_reg__0[0]),
.O(plusOp__2[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\bit_cntr[1]_i_1__0
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.O(plusOp__2[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h78))
\bit_cntr[2]_i_1__0
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[2]),
.O(plusOp__2[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\bit_cntr[3]_i_1__0
(.I0(bit_cntr_reg__0[2]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[1]),
.I3(bit_cntr_reg__0[3]),
.O(plusOp__2[3]));
LUT2 #(
.INIT(4'h1))
\bit_cntr[4]_i_1__0
(.I0(out[2]),
.I1(p_0_in2_in),
.O(\bit_cntr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h7FFF8000))
\bit_cntr[4]_i_3__0
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[1]),
.I2(bit_cntr_reg__0[0]),
.I3(bit_cntr_reg__0[2]),
.I4(bit_cntr_reg__0[4]),
.O(plusOp__2[4]));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[0]),
.Q(bit_cntr_reg__0[0]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[1]),
.Q(bit_cntr_reg__0[1]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[2]),
.Q(bit_cntr_reg__0[2]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[3]),
.Q(bit_cntr_reg__0[3]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[4]),
.Q(bit_cntr_reg__0[4]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h0800))
\ldata_reg[0]_i_1
(.I0(\DataTx_L_reg[23] [0]),
.I1(out[0]),
.I2(Q[1]),
.I3(lrclk_d1),
.O(\ldata_reg[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[10]_i_1
(.I0(\ldata_reg_reg_n_0_[9] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [10]),
.O(\ldata_reg[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[11]_i_1
(.I0(\ldata_reg_reg_n_0_[10] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [11]),
.O(\ldata_reg[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[12]_i_1
(.I0(\ldata_reg_reg_n_0_[11] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [12]),
.O(\ldata_reg[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[13]_i_1
(.I0(\ldata_reg_reg_n_0_[12] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [13]),
.O(\ldata_reg[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[14]_i_1
(.I0(\ldata_reg_reg_n_0_[13] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [14]),
.O(\ldata_reg[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[15]_i_1
(.I0(\ldata_reg_reg_n_0_[14] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [15]),
.O(\ldata_reg[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[16]_i_1
(.I0(\ldata_reg_reg_n_0_[15] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [16]),
.O(\ldata_reg[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[17]_i_1
(.I0(\ldata_reg_reg_n_0_[16] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [17]),
.O(\ldata_reg[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[18]_i_1
(.I0(\ldata_reg_reg_n_0_[17] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [18]),
.O(\ldata_reg[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[19]_i_1
(.I0(\ldata_reg_reg_n_0_[18] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [19]),
.O(\ldata_reg[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[1]_i_1
(.I0(\ldata_reg_reg_n_0_[0] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [1]),
.O(\ldata_reg[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[20]_i_1
(.I0(\ldata_reg_reg_n_0_[19] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [20]),
.O(\ldata_reg[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[21]_i_1
(.I0(\ldata_reg_reg_n_0_[20] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [21]),
.O(\ldata_reg[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[22]_i_1
(.I0(\ldata_reg_reg_n_0_[21] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [22]),
.O(\ldata_reg[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h2020FF2020202020))
\ldata_reg[23]_i_1__0
(.I0(p_0_in2_in),
.I1(Q[0]),
.I2(sclk_d1),
.I3(out[0]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\ldata_reg[23]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[23]_i_2__0
(.I0(\ldata_reg_reg_n_0_[22] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [23]),
.O(\ldata_reg[23]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[2]_i_1
(.I0(\ldata_reg_reg_n_0_[1] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [2]),
.O(\ldata_reg[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[3]_i_1
(.I0(\ldata_reg_reg_n_0_[2] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [3]),
.O(\ldata_reg[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[4]_i_1
(.I0(\ldata_reg_reg_n_0_[3] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [4]),
.O(\ldata_reg[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[5]_i_1
(.I0(\ldata_reg_reg_n_0_[4] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [5]),
.O(\ldata_reg[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[6]_i_1
(.I0(\ldata_reg_reg_n_0_[5] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [6]),
.O(\ldata_reg[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[7]_i_1
(.I0(\ldata_reg_reg_n_0_[6] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [7]),
.O(\ldata_reg[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[8]_i_1
(.I0(\ldata_reg_reg_n_0_[7] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [8]),
.O(\ldata_reg[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[9]_i_1
(.I0(\ldata_reg_reg_n_0_[8] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [9]),
.O(\ldata_reg[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[0]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[0] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[10]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[10] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[11]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[11] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[12]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[12] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[13]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[13] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[14]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[14] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[15]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[15] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[16]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[16] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[17]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[17] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[18]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[18] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[19]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[19] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[1]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[1] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[20]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[20] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[21]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[21] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[22]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[22] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[23]_i_2__0_n_0 ),
.Q(p_2_in),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[2]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[2] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[3]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[3] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[4]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[4] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[5]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[5] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[6]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[6] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[7]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[7] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[8]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[8] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[9]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[9] ),
.R(ldata_reg));
LUT4 #(
.INIT(16'h0800))
\rdata_reg[0]_i_1
(.I0(\DataTx_R_reg[23] [0]),
.I1(out[0]),
.I2(Q[1]),
.I3(lrclk_d1),
.O(p_1_in[0]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[10]_i_1
(.I0(\rdata_reg_reg_n_0_[9] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [10]),
.O(p_1_in[10]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[11]_i_1
(.I0(\rdata_reg_reg_n_0_[10] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [11]),
.O(p_1_in[11]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[12]_i_1
(.I0(\rdata_reg_reg_n_0_[11] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [12]),
.O(p_1_in[12]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[13]_i_1
(.I0(\rdata_reg_reg_n_0_[12] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [13]),
.O(p_1_in[13]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[14]_i_1
(.I0(\rdata_reg_reg_n_0_[13] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [14]),
.O(p_1_in[14]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[15]_i_1
(.I0(\rdata_reg_reg_n_0_[14] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [15]),
.O(p_1_in[15]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[16]_i_1
(.I0(\rdata_reg_reg_n_0_[15] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [16]),
.O(p_1_in[16]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[17]_i_1
(.I0(\rdata_reg_reg_n_0_[16] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [17]),
.O(p_1_in[17]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[18]_i_1
(.I0(\rdata_reg_reg_n_0_[17] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [18]),
.O(p_1_in[18]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[19]_i_1
(.I0(\rdata_reg_reg_n_0_[18] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [19]),
.O(p_1_in[19]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[1]_i_1
(.I0(\rdata_reg_reg_n_0_[0] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [1]),
.O(p_1_in[1]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[20]_i_1
(.I0(\rdata_reg_reg_n_0_[19] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [20]),
.O(p_1_in[20]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[21]_i_1
(.I0(\rdata_reg_reg_n_0_[20] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [21]),
.O(p_1_in[21]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[22]_i_1
(.I0(\rdata_reg_reg_n_0_[21] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [22]),
.O(p_1_in[22]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[23]_i_2
(.I0(\rdata_reg_reg_n_0_[22] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [23]),
.O(p_1_in[23]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[2]_i_1
(.I0(\rdata_reg_reg_n_0_[1] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [2]),
.O(p_1_in[2]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[3]_i_1
(.I0(\rdata_reg_reg_n_0_[2] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [3]),
.O(p_1_in[3]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[4]_i_1
(.I0(\rdata_reg_reg_n_0_[3] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [4]),
.O(p_1_in[4]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[5]_i_1
(.I0(\rdata_reg_reg_n_0_[4] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [5]),
.O(p_1_in[5]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[6]_i_1
(.I0(\rdata_reg_reg_n_0_[5] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [6]),
.O(p_1_in[6]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[7]_i_1
(.I0(\rdata_reg_reg_n_0_[6] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [7]),
.O(p_1_in[7]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[8]_i_1
(.I0(\rdata_reg_reg_n_0_[7] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [8]),
.O(p_1_in[8]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[9]_i_1
(.I0(\rdata_reg_reg_n_0_[8] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [9]),
.O(p_1_in[9]));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[0]),
.Q(\rdata_reg_reg_n_0_[0] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[10]),
.Q(\rdata_reg_reg_n_0_[10] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[11]),
.Q(\rdata_reg_reg_n_0_[11] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[12]),
.Q(\rdata_reg_reg_n_0_[12] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[13]),
.Q(\rdata_reg_reg_n_0_[13] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[14]),
.Q(\rdata_reg_reg_n_0_[14] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[15]),
.Q(\rdata_reg_reg_n_0_[15] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[16]),
.Q(\rdata_reg_reg_n_0_[16] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[17]),
.Q(\rdata_reg_reg_n_0_[17] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[18]),
.Q(\rdata_reg_reg_n_0_[18] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[19]),
.Q(\rdata_reg_reg_n_0_[19] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[1]),
.Q(\rdata_reg_reg_n_0_[1] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[20]),
.Q(\rdata_reg_reg_n_0_[20] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[21]),
.Q(\rdata_reg_reg_n_0_[21] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[22]),
.Q(\rdata_reg_reg_n_0_[22] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[23]),
.Q(\rdata_reg_reg_n_0_[23] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[2]),
.Q(\rdata_reg_reg_n_0_[2] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[3]),
.Q(\rdata_reg_reg_n_0_[3] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[4]),
.Q(\rdata_reg_reg_n_0_[4] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[5]),
.Q(\rdata_reg_reg_n_0_[5] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[6]),
.Q(\rdata_reg_reg_n_0_[6] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[7]),
.Q(\rdata_reg_reg_n_0_[7] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[8]),
.Q(\rdata_reg_reg_n_0_[8] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[9]),
.Q(\rdata_reg_reg_n_0_[9] ),
.R(ldata_reg));
LUT6 #(
.INIT(64'hFFFFCCAF0000CCA0))
sdata_reg_i_1
(.I0(\rdata_reg_reg_n_0_[23] ),
.I1(p_2_in),
.I2(out[2]),
.I3(p_0_in2_in),
.I4(\clk_cntr_reg[4] ),
.I5(SDATA_O),
.O(sdata_reg_i_1_n_0));
FDRE #(
.INIT(1'b0))
sdata_reg_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(sdata_reg_i_1_n_0),
.Q(SDATA_O),
.R(ldata_reg));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(BCLK,
LRCLK,
SDATA_I,
SDATA_O,
S_AXI_ACLK,
S_AXI_ARESETN,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_BREADY,
S_AXI_ARADDR,
S_AXI_ARVALID,
S_AXI_RREADY,
S_AXI_ARREADY,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RVALID,
S_AXI_WREADY,
S_AXI_BRESP,
S_AXI_BVALID,
S_AXI_AWREADY);
output BCLK;
output LRCLK;
input SDATA_I;
output SDATA_O;
(* max_fanout = "10000" *) (* sigis = "Clk" *) (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK" *)
(* x_interface_parameter = "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input S_AXI_ACLK;
(* max_fanout = "10000" *) (* sigis = "Rst" *) (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST" *)
(* x_interface_parameter = "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW" *) input S_AXI_ARESETN;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]S_AXI_AWADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input S_AXI_AWVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]S_AXI_WDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]S_AXI_WSTRB;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input S_AXI_WVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input S_AXI_BREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]S_AXI_ARADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input S_AXI_ARVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input S_AXI_RREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output S_AXI_ARREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]S_AXI_RDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]S_AXI_RRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output S_AXI_RVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output S_AXI_WREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]S_AXI_BRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output S_AXI_BVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output S_AXI_AWREADY;
wire \<const0> ;
wire BCLK;
wire LRCLK;
wire SDATA_I;
wire SDATA_O;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire S_AXI_ACLK;
wire [31:0]S_AXI_ARADDR;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [31:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire [31:0]S_AXI_WDATA;
wire S_AXI_WVALID;
assign S_AXI_BRESP[1] = \<const0> ;
assign S_AXI_BRESP[0] = \<const0> ;
assign S_AXI_RRESP[1] = \<const0> ;
assign S_AXI_RRESP[0] = \<const0> ;
assign S_AXI_WREADY = S_AXI_AWREADY;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl U0
(.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR[4:2]),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR[4:2]),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WVALID(S_AXI_WVALID),
.out({LRCLK,BCLK}));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(\DataTx_R_reg[0] ,
\DataTx_R_reg[0]_0 ,
\DataTx_R_reg[0]_1 ,
\DataTx_R_reg[0]_2 ,
\DataTx_R_reg[0]_3 ,
\DataTx_R_reg[0]_4 ,
S_AXI_RVALID,
S_AXI_BVALID,
data_rdy_bit_reg,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
S_AXI_RDATA,
S_AXI_ACLK,
SR,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
Q,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] );
output \DataTx_R_reg[0] ;
output \DataTx_R_reg[0]_0 ;
output \DataTx_R_reg[0]_1 ;
output \DataTx_R_reg[0]_2 ;
output \DataTx_R_reg[0]_3 ;
output \DataTx_R_reg[0]_4 ;
output S_AXI_RVALID;
output S_AXI_BVALID;
output data_rdy_bit_reg;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]S_AXI_RDATA;
input S_AXI_ACLK;
input [0:0]SR;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]Q;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire \DataTx_R_reg[0] ;
wire \DataTx_R_reg[0]_0 ;
wire \DataTx_R_reg[0]_1 ;
wire \DataTx_R_reg[0]_2 ;
wire \DataTx_R_reg[0]_3 ;
wire \DataTx_R_reg[0]_4 ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ;
wire [31:0]IP2Bus_Data;
wire I_DECODER_n_46;
wire I_DECODER_n_47;
wire I_DECODER_n_7;
wire I_DECODER_n_8;
wire [31:0]Q;
wire [0:0]SR;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire S_AXI_WVALID;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
wire p_2_out;
wire [3:0]plusOp;
wire rst;
wire s_axi_rdata_i;
wire [1:0]state;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
wire timeout;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(p_2_out));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.I3(timeout),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[3]),
.Q(timeout),
.R(p_2_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D({I_DECODER_n_7,I_DECODER_n_8}),
.\DataRx_L_reg[23] (\DataRx_L_reg[23] ),
.\DataRx_R_reg[23] (\DataRx_R_reg[23] ),
.\DataTx_L_reg[0] (\DataTx_L_reg[0] ),
.\DataTx_L_reg[31] (\DataTx_L_reg[31] ),
.\DataTx_R_reg[0] (\DataTx_R_reg[0] ),
.\DataTx_R_reg[0]_0 (\DataTx_R_reg[0]_0 ),
.\DataTx_R_reg[0]_1 (\DataTx_R_reg[0]_1 ),
.\DataTx_R_reg[0]_2 (\DataTx_R_reg[0]_2 ),
.\DataTx_R_reg[0]_3 (\DataTx_R_reg[0]_3 ),
.\DataTx_R_reg[0]_4 (\DataTx_R_reg[0]_4 ),
.\DataTx_R_reg[31] (Q),
.E(E),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (timeout),
.Q(state),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WVALID_0(\state[1]_i_2_n_0 ),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(data_rdy_bit_reg),
.data_rdy_bit_reg_0(data_rdy_bit_reg_0),
.s_axi_bvalid_i_reg(I_DECODER_n_47),
.s_axi_bvalid_i_reg_0(\state[0]_i_2_n_0 ),
.s_axi_bvalid_i_reg_1(S_AXI_BVALID),
.\s_axi_rdata_i_reg[31] (IP2Bus_Data),
.s_axi_rvalid_i_reg(I_DECODER_n_46),
.s_axi_rvalid_i_reg_0(S_AXI_RVALID),
.\state_reg[1] (\state[1]_i_3_n_0 ));
FDRE rst_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(SR),
.Q(rst),
.R(1'b0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_47),
.Q(S_AXI_BVALID),
.R(rst));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[0]),
.Q(S_AXI_RDATA[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[10]),
.Q(S_AXI_RDATA[10]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[11]),
.Q(S_AXI_RDATA[11]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[12]),
.Q(S_AXI_RDATA[12]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[13]),
.Q(S_AXI_RDATA[13]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[14]),
.Q(S_AXI_RDATA[14]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[15]),
.Q(S_AXI_RDATA[15]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[16]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[16]),
.Q(S_AXI_RDATA[16]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[17]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[17]),
.Q(S_AXI_RDATA[17]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[18]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[18]),
.Q(S_AXI_RDATA[18]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[19]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[19]),
.Q(S_AXI_RDATA[19]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[1]),
.Q(S_AXI_RDATA[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[20]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[20]),
.Q(S_AXI_RDATA[20]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[21]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[21]),
.Q(S_AXI_RDATA[21]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[22]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[22]),
.Q(S_AXI_RDATA[22]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[23]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[23]),
.Q(S_AXI_RDATA[23]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[24]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[24]),
.Q(S_AXI_RDATA[24]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[25]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[25]),
.Q(S_AXI_RDATA[25]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[26]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[26]),
.Q(S_AXI_RDATA[26]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[27]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[27]),
.Q(S_AXI_RDATA[27]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[28]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[28]),
.Q(S_AXI_RDATA[28]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[29]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[29]),
.Q(S_AXI_RDATA[29]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[2]),
.Q(S_AXI_RDATA[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[30]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[30]),
.Q(S_AXI_RDATA[30]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[31]),
.Q(S_AXI_RDATA[31]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[3]),
.Q(S_AXI_RDATA[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[4]),
.Q(S_AXI_RDATA[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[5]),
.Q(S_AXI_RDATA[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[6]),
.Q(S_AXI_RDATA[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[7]),
.Q(S_AXI_RDATA[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[8]),
.Q(S_AXI_RDATA[8]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[9]),
.Q(S_AXI_RDATA[9]),
.R(rst));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_46),
.Q(S_AXI_RVALID),
.R(rst));
LUT6 #(
.INIT(64'h07770000FFFF0000))
\state[0]_i_2
(.I0(S_AXI_BVALID),
.I1(S_AXI_BREADY),
.I2(S_AXI_RREADY),
.I3(S_AXI_RVALID),
.I4(state[0]),
.I5(state[1]),
.O(\state[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_2
(.I0(S_AXI_AWVALID),
.I1(S_AXI_WVALID),
.O(\state[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h002A2A2A))
\state[1]_i_3
(.I0(state[1]),
.I1(S_AXI_RVALID),
.I2(S_AXI_RREADY),
.I3(S_AXI_BREADY),
.I4(S_AXI_BVALID),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_8),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_7),
.Q(state[1]),
.R(rst));
endmodule |
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic
(\s_axi_rdata_i_reg[24] ,
Q,
data_rdy_bit,
SDATA_O,
\s_axi_rdata_i_reg[31] ,
\s_axi_rdata_i_reg[31]_0 ,
SR,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[23]_0 ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
S_AXI_ACLK,
S_AXI_ARESETN,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
SDATA_I,
E,
S_AXI_WDATA,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] );
output \s_axi_rdata_i_reg[24] ;
output [1:0]Q;
output data_rdy_bit;
output SDATA_O;
output [31:0]\s_axi_rdata_i_reg[31] ;
output [31:0]\s_axi_rdata_i_reg[31]_0 ;
output [0:0]SR;
output [23:0]\s_axi_rdata_i_reg[23] ;
output [23:0]\s_axi_rdata_i_reg[23]_0 ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input S_AXI_ACLK;
input S_AXI_ARESETN;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input SDATA_I;
input [0:0]E;
input [31:0]S_AXI_WDATA;
input [0:0]\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire Bus_RNW_reg;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire [0:0]\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire Inst_iis_deser_n_3;
wire Inst_iis_deser_n_33;
wire Inst_iis_deser_n_34;
wire Inst_iis_deser_n_35;
wire Inst_iis_deser_n_36;
wire Inst_iis_deser_n_37;
wire Inst_iis_deser_n_38;
wire Inst_iis_deser_n_39;
wire Inst_iis_deser_n_40;
wire Inst_iis_deser_n_41;
wire Inst_iis_deser_n_42;
wire Inst_iis_deser_n_43;
wire Inst_iis_deser_n_44;
wire Inst_iis_deser_n_45;
wire Inst_iis_deser_n_46;
wire Inst_iis_deser_n_47;
wire Inst_iis_deser_n_48;
wire Inst_iis_deser_n_49;
wire Inst_iis_deser_n_5;
wire Inst_iis_deser_n_50;
wire Inst_iis_deser_n_51;
wire Inst_iis_deser_n_52;
wire Inst_iis_deser_n_53;
wire Inst_iis_deser_n_54;
wire Inst_iis_deser_n_55;
wire Inst_iis_deser_n_56;
wire Inst_iis_deser_n_6;
wire Inst_iis_deser_n_7;
wire Inst_iis_deser_n_8;
wire Inst_iis_ser_n_1;
wire Inst_iis_ser_n_2;
wire [1:0]Q;
wire SDATA_I;
wire SDATA_O;
wire [0:0]SR;
wire S_AXI_ACLK;
wire S_AXI_ARESETN;
wire [31:0]S_AXI_WDATA;
wire \clk_cntr[10]_i_2_n_0 ;
wire \clk_cntr_reg_n_0_[0] ;
wire \clk_cntr_reg_n_0_[1] ;
wire \clk_cntr_reg_n_0_[2] ;
wire \clk_cntr_reg_n_0_[3] ;
wire \clk_cntr_reg_n_0_[5] ;
wire \clk_cntr_reg_n_0_[6] ;
wire \clk_cntr_reg_n_0_[7] ;
wire \clk_cntr_reg_n_0_[8] ;
wire \clk_cntr_reg_n_0_[9] ;
wire data_rdy;
wire data_rdy_bit;
wire [23:0]ldata_reg;
wire lrclk_d1;
wire p_0_in4_in;
wire [10:0]plusOp__0;
wire [23:0]\s_axi_rdata_i_reg[23] ;
wire [23:0]\s_axi_rdata_i_reg[23]_0 ;
wire \s_axi_rdata_i_reg[24] ;
wire [31:0]\s_axi_rdata_i_reg[31] ;
wire [31:0]\s_axi_rdata_i_reg[31]_0 ;
wire sclk_d1;
wire write_bit;
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[0]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[0]),
.Q(\s_axi_rdata_i_reg[23] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[10]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[10]),
.Q(\s_axi_rdata_i_reg[23] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[11]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[11]),
.Q(\s_axi_rdata_i_reg[23] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[12]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[12]),
.Q(\s_axi_rdata_i_reg[23] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[13]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[13]),
.Q(\s_axi_rdata_i_reg[23] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[14]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[14]),
.Q(\s_axi_rdata_i_reg[23] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[15]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[15]),
.Q(\s_axi_rdata_i_reg[23] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[16]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[16]),
.Q(\s_axi_rdata_i_reg[23] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[17]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[17]),
.Q(\s_axi_rdata_i_reg[23] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[18]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[18]),
.Q(\s_axi_rdata_i_reg[23] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[19]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[19]),
.Q(\s_axi_rdata_i_reg[23] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[1]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[1]),
.Q(\s_axi_rdata_i_reg[23] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[20]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[20]),
.Q(\s_axi_rdata_i_reg[23] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[21]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[21]),
.Q(\s_axi_rdata_i_reg[23] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[22]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[22]),
.Q(\s_axi_rdata_i_reg[23] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[23]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[23]),
.Q(\s_axi_rdata_i_reg[23] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[2]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[2]),
.Q(\s_axi_rdata_i_reg[23] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[3]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[3]),
.Q(\s_axi_rdata_i_reg[23] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[4]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[4]),
.Q(\s_axi_rdata_i_reg[23] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[5]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[5]),
.Q(\s_axi_rdata_i_reg[23] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[6]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[6]),
.Q(\s_axi_rdata_i_reg[23] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[7]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[7]),
.Q(\s_axi_rdata_i_reg[23] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[8]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[8]),
.Q(\s_axi_rdata_i_reg[23] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[9]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[9]),
.Q(\s_axi_rdata_i_reg[23] [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[0]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_56),
.Q(\s_axi_rdata_i_reg[23]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[10]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_46),
.Q(\s_axi_rdata_i_reg[23]_0 [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[11]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_45),
.Q(\s_axi_rdata_i_reg[23]_0 [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[12]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_44),
.Q(\s_axi_rdata_i_reg[23]_0 [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[13]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_43),
.Q(\s_axi_rdata_i_reg[23]_0 [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[14]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_42),
.Q(\s_axi_rdata_i_reg[23]_0 [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[15]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_41),
.Q(\s_axi_rdata_i_reg[23]_0 [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[16]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_40),
.Q(\s_axi_rdata_i_reg[23]_0 [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[17]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_39),
.Q(\s_axi_rdata_i_reg[23]_0 [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[18]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_38),
.Q(\s_axi_rdata_i_reg[23]_0 [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[19]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_37),
.Q(\s_axi_rdata_i_reg[23]_0 [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[1]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_55),
.Q(\s_axi_rdata_i_reg[23]_0 [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[20]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_36),
.Q(\s_axi_rdata_i_reg[23]_0 [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[21]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_35),
.Q(\s_axi_rdata_i_reg[23]_0 [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[22]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_34),
.Q(\s_axi_rdata_i_reg[23]_0 [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[23]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_33),
.Q(\s_axi_rdata_i_reg[23]_0 [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[2]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_54),
.Q(\s_axi_rdata_i_reg[23]_0 [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[3]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_53),
.Q(\s_axi_rdata_i_reg[23]_0 [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[4]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_52),
.Q(\s_axi_rdata_i_reg[23]_0 [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[5]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_51),
.Q(\s_axi_rdata_i_reg[23]_0 [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[6]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_50),
.Q(\s_axi_rdata_i_reg[23]_0 [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[7]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_49),
.Q(\s_axi_rdata_i_reg[23]_0 [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[8]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_48),
.Q(\s_axi_rdata_i_reg[23]_0 [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[9]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_47),
.Q(\s_axi_rdata_i_reg[23]_0 [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[0]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[0]),
.Q(\s_axi_rdata_i_reg[31] [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[10]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[10]),
.Q(\s_axi_rdata_i_reg[31] [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[11]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[11]),
.Q(\s_axi_rdata_i_reg[31] [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[12]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[12]),
.Q(\s_axi_rdata_i_reg[31] [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[13]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[13]),
.Q(\s_axi_rdata_i_reg[31] [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[14]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[14]),
.Q(\s_axi_rdata_i_reg[31] [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[15]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[15]),
.Q(\s_axi_rdata_i_reg[31] [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[16]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[16]),
.Q(\s_axi_rdata_i_reg[31] [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[17]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[17]),
.Q(\s_axi_rdata_i_reg[31] [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[18]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[18]),
.Q(\s_axi_rdata_i_reg[31] [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[19]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[19]),
.Q(\s_axi_rdata_i_reg[31] [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[1]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[1]),
.Q(\s_axi_rdata_i_reg[31] [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[20]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[20]),
.Q(\s_axi_rdata_i_reg[31] [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[21]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[21]),
.Q(\s_axi_rdata_i_reg[31] [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[22]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[22]),
.Q(\s_axi_rdata_i_reg[31] [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[23]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[23]),
.Q(\s_axi_rdata_i_reg[31] [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[24]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[24]),
.Q(\s_axi_rdata_i_reg[31] [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[25]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[25]),
.Q(\s_axi_rdata_i_reg[31] [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[26]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[26]),
.Q(\s_axi_rdata_i_reg[31] [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[27]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[27]),
.Q(\s_axi_rdata_i_reg[31] [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[28]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[28]),
.Q(\s_axi_rdata_i_reg[31] [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[29]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[29]),
.Q(\s_axi_rdata_i_reg[31] [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[2]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[2]),
.Q(\s_axi_rdata_i_reg[31] [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[30]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[30]),
.Q(\s_axi_rdata_i_reg[31] [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[31]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[31]),
.Q(\s_axi_rdata_i_reg[31] [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[3]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[3]),
.Q(\s_axi_rdata_i_reg[31] [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[4]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[4]),
.Q(\s_axi_rdata_i_reg[31] [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[5]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[5]),
.Q(\s_axi_rdata_i_reg[31] [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[6]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[6]),
.Q(\s_axi_rdata_i_reg[31] [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[7]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[7]),
.Q(\s_axi_rdata_i_reg[31] [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[8]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[8]),
.Q(\s_axi_rdata_i_reg[31] [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[9]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[9]),
.Q(\s_axi_rdata_i_reg[31] [9]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[0]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[0]),
.Q(\s_axi_rdata_i_reg[31]_0 [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[10]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[10]),
.Q(\s_axi_rdata_i_reg[31]_0 [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[11]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[11]),
.Q(\s_axi_rdata_i_reg[31]_0 [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[12]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[12]),
.Q(\s_axi_rdata_i_reg[31]_0 [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[13]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[13]),
.Q(\s_axi_rdata_i_reg[31]_0 [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[14]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[14]),
.Q(\s_axi_rdata_i_reg[31]_0 [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[15]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[15]),
.Q(\s_axi_rdata_i_reg[31]_0 [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[16]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[16]),
.Q(\s_axi_rdata_i_reg[31]_0 [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[17]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[17]),
.Q(\s_axi_rdata_i_reg[31]_0 [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[18]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[18]),
.Q(\s_axi_rdata_i_reg[31]_0 [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[19]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[19]),
.Q(\s_axi_rdata_i_reg[31]_0 [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[1]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[1]),
.Q(\s_axi_rdata_i_reg[31]_0 [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[20]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[20]),
.Q(\s_axi_rdata_i_reg[31]_0 [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[21]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[21]),
.Q(\s_axi_rdata_i_reg[31]_0 [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[22]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[22]),
.Q(\s_axi_rdata_i_reg[31]_0 [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[23]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[23]),
.Q(\s_axi_rdata_i_reg[31]_0 [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[24]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[24]),
.Q(\s_axi_rdata_i_reg[31]_0 [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[25]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[25]),
.Q(\s_axi_rdata_i_reg[31]_0 [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[26]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[26]),
.Q(\s_axi_rdata_i_reg[31]_0 [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[27]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[27]),
.Q(\s_axi_rdata_i_reg[31]_0 [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[28]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[28]),
.Q(\s_axi_rdata_i_reg[31]_0 [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[29]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[29]),
.Q(\s_axi_rdata_i_reg[31]_0 [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[2]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[2]),
.Q(\s_axi_rdata_i_reg[31]_0 [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[30]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[30]),
.Q(\s_axi_rdata_i_reg[31]_0 [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[31]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[31]),
.Q(\s_axi_rdata_i_reg[31]_0 [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[3]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[3]),
.Q(\s_axi_rdata_i_reg[31]_0 [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[4]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[4]),
.Q(\s_axi_rdata_i_reg[31]_0 [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[5]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[5]),
.Q(\s_axi_rdata_i_reg[31]_0 [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[6]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[6]),
.Q(\s_axi_rdata_i_reg[31]_0 [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[7]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[7]),
.Q(\s_axi_rdata_i_reg[31]_0 [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[8]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[8]),
.Q(\s_axi_rdata_i_reg[31]_0 [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[9]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[9]),
.Q(\s_axi_rdata_i_reg[31]_0 [9]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser Inst_iis_deser
(.\DataRx_L_reg[23] (ldata_reg),
.\DataRx_R_reg[23] ({Inst_iis_deser_n_33,Inst_iis_deser_n_34,Inst_iis_deser_n_35,Inst_iis_deser_n_36,Inst_iis_deser_n_37,Inst_iis_deser_n_38,Inst_iis_deser_n_39,Inst_iis_deser_n_40,Inst_iis_deser_n_41,Inst_iis_deser_n_42,Inst_iis_deser_n_43,Inst_iis_deser_n_44,Inst_iis_deser_n_45,Inst_iis_deser_n_46,Inst_iis_deser_n_47,Inst_iis_deser_n_48,Inst_iis_deser_n_49,Inst_iis_deser_n_50,Inst_iis_deser_n_51,Inst_iis_deser_n_52,Inst_iis_deser_n_53,Inst_iis_deser_n_54,Inst_iis_deser_n_55,Inst_iis_deser_n_56}),
.E(data_rdy),
.\FSM_onehot_iis_state_reg[0] (Inst_iis_deser_n_6),
.\FSM_onehot_iis_state_reg[0]_0 (Inst_iis_deser_n_8),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.Q(Q),
.SDATA_I(SDATA_I),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.\bit_cntr_reg[4]_0 (write_bit),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(Inst_iis_deser_n_7),
.lrclk_d1(lrclk_d1),
.out({Inst_iis_ser_n_1,Inst_iis_ser_n_2,p_0_in4_in}),
.\rdata_reg_reg[23]_0 (Inst_iis_deser_n_3),
.sclk_d1(sclk_d1),
.sdata_reg_reg(Inst_iis_deser_n_5));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser Inst_iis_ser
(.\DataTx_L_reg[23] (\s_axi_rdata_i_reg[31] [23:0]),
.\DataTx_R_reg[23] (\s_axi_rdata_i_reg[31]_0 [23:0]),
.E(Inst_iis_deser_n_3),
.Q(Q),
.SDATA_O(SDATA_O),
.S_AXI_ACLK(S_AXI_ACLK),
.\clk_cntr_reg[4] (Inst_iis_deser_n_5),
.lrclk_d1(lrclk_d1),
.lrclk_d1_reg(Inst_iis_deser_n_8),
.lrclk_d1_reg_0(Inst_iis_deser_n_6),
.out({Inst_iis_ser_n_1,Inst_iis_ser_n_2,p_0_in4_in}),
.sclk_d1(sclk_d1),
.sclk_d1_reg(write_bit));
LUT1 #(
.INIT(2'h1))
\clk_cntr[0]_i_1
(.I0(\clk_cntr_reg_n_0_[0] ),
.O(plusOp__0[0]));
LUT6 #(
.INIT(64'hF7FFFFFF08000000))
\clk_cntr[10]_i_1
(.I0(\clk_cntr_reg_n_0_[9] ),
.I1(\clk_cntr_reg_n_0_[7] ),
.I2(\clk_cntr[10]_i_2_n_0 ),
.I3(\clk_cntr_reg_n_0_[6] ),
.I4(\clk_cntr_reg_n_0_[8] ),
.I5(Q[1]),
.O(plusOp__0[10]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\clk_cntr[10]_i_2
(.I0(Q[0]),
.I1(\clk_cntr_reg_n_0_[2] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[1] ),
.I4(\clk_cntr_reg_n_0_[3] ),
.I5(\clk_cntr_reg_n_0_[5] ),
.O(\clk_cntr[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\clk_cntr[1]_i_1
(.I0(\clk_cntr_reg_n_0_[0] ),
.I1(\clk_cntr_reg_n_0_[1] ),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h78))
\clk_cntr[2]_i_1
(.I0(\clk_cntr_reg_n_0_[1] ),
.I1(\clk_cntr_reg_n_0_[0] ),
.I2(\clk_cntr_reg_n_0_[2] ),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h7F80))
\clk_cntr[3]_i_1
(.I0(\clk_cntr_reg_n_0_[2] ),
.I1(\clk_cntr_reg_n_0_[0] ),
.I2(\clk_cntr_reg_n_0_[1] ),
.I3(\clk_cntr_reg_n_0_[3] ),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h7FFF8000))
\clk_cntr[4]_i_1
(.I0(\clk_cntr_reg_n_0_[3] ),
.I1(\clk_cntr_reg_n_0_[1] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[2] ),
.I4(Q[0]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\clk_cntr[5]_i_1
(.I0(Q[0]),
.I1(\clk_cntr_reg_n_0_[2] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[1] ),
.I4(\clk_cntr_reg_n_0_[3] ),
.I5(\clk_cntr_reg_n_0_[5] ),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\clk_cntr[6]_i_1
(.I0(\clk_cntr[10]_i_2_n_0 ),
.I1(\clk_cntr_reg_n_0_[6] ),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hD2))
\clk_cntr[7]_i_1
(.I0(\clk_cntr_reg_n_0_[6] ),
.I1(\clk_cntr[10]_i_2_n_0 ),
.I2(\clk_cntr_reg_n_0_[7] ),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hDF20))
\clk_cntr[8]_i_1
(.I0(\clk_cntr_reg_n_0_[7] ),
.I1(\clk_cntr[10]_i_2_n_0 ),
.I2(\clk_cntr_reg_n_0_[6] ),
.I3(\clk_cntr_reg_n_0_[8] ),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hF7FF0800))
\clk_cntr[9]_i_1
(.I0(\clk_cntr_reg_n_0_[8] ),
.I1(\clk_cntr_reg_n_0_[6] ),
.I2(\clk_cntr[10]_i_2_n_0 ),
.I3(\clk_cntr_reg_n_0_[7] ),
.I4(\clk_cntr_reg_n_0_[9] ),
.O(plusOp__0[9]));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[0]),
.Q(\clk_cntr_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[10]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[10]),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[1]),
.Q(\clk_cntr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[2]),
.Q(\clk_cntr_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[3]),
.Q(\clk_cntr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[4]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[5]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[5]),
.Q(\clk_cntr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[6]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[6]),
.Q(\clk_cntr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[7]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[7]),
.Q(\clk_cntr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[8]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[8]),
.Q(\clk_cntr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[9]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[9]),
.Q(\clk_cntr_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
data_rdy_bit_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Inst_iis_deser_n_7),
.Q(data_rdy_bit),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(S_AXI_ARESETN),
.O(SR));
LUT6 #(
.INIT(64'h0000000400040448))
slv_ip2bus_data
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I5(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(\s_axi_rdata_i_reg[24] ));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module tag_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter `BSG_INV_PARAM(tag_width_lp)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter block_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)+`BSG_SAFE_CLOG2(block_size_in_words_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
)
(
input clk_i
, input reset_i
, input en_i
, input v_i
, input ready_o
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input v_o
, input yumi_i
, input [data_width_p-1:0] data_o
, input [id_width_p-1:0] id_o
);
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
`declare_bsg_cache_non_blocking_tag_info_s(tag_width_lp);
bsg_cache_non_blocking_tag_info_s [ways_p-1:0][sets_p-1:0] shadow_tag;
logic [data_width_p-1:0] result [*]; // indexed by id.
wire [lg_ways_lp-1:0] addr_way = cache_pkt.addr[block_offset_width_lp+lg_sets_lp+:lg_ways_lp];
wire [lg_sets_lp-1:0] addr_index = cache_pkt.addr[block_offset_width_lp+:lg_sets_lp];
always_ff @ (posedge clk_i) begin
if (reset_i) begin
for (integer i = 0; i < ways_p; i++)
for (integer j = 0; j < ways_p; j++)
shadow_tag[i][j] <= '0;
end
else begin
if (v_i & ready_o & en_i) begin
case (cache_pkt.opcode)
TAGST: begin
result[cache_pkt.id] = '0;
shadow_tag[addr_way][addr_index].tag <= cache_pkt.data[0+:tag_width_lp];
shadow_tag[addr_way][addr_index].valid <= cache_pkt.data[data_width_p-1];
shadow_tag[addr_way][addr_index].lock <= cache_pkt.data[data_width_p-2];
end
TAGLV: begin
result[cache_pkt.id] = '0;
result[cache_pkt.id][1] = shadow_tag[addr_way][addr_index].lock;
result[cache_pkt.id][0] = shadow_tag[addr_way][addr_index].valid;
end
TAGLA: begin
result[cache_pkt.id] = {
shadow_tag[addr_way][addr_index].tag,
addr_index,
{block_offset_width_lp{1'b0}}
};
end
endcase
end
end
if (~reset_i & v_o & yumi_i & en_i) begin
$display("id=%d, data=%x", id_o, data_o);
assert(result[id_o] == data_o)
else $fatal("[BSG_FATAL] Output does not match expected result. Id= %d, Expected: %x. Actual: %x",
id_o, result[id_o], data_o);
end
end
endmodule |
module usbHostControl(
busClk, rstSyncToBusClk,
usbClk, rstSyncToUsbClk,
//sendPacket
TxFifoRE, TxFifoData, TxFifoEmpty,
//getPacket
RxFifoWE, RxFifoData, RxFifoFull,
RxByteStatus, RxData, RxDataValid,
SIERxTimeOut, SIERxTimeOutEn,
//speedCtrlMux
fullSpeedRate, fullSpeedPol,
//HCTxPortArbiter
HCTxPortEn, HCTxPortRdy,
HCTxPortData, HCTxPortCtrl,
//rxStatusMonitor
connectStateIn,
resumeDetectedIn,
//USBHostControlBI
busAddress,
busDataIn,
busDataOut,
busWriteEn,
busStrobe_i,
SOFSentIntOut,
connEventIntOut,
resumeIntOut,
transDoneIntOut,
hostControlSelect
);
input busClk;
input rstSyncToBusClk;
input usbClk;
input rstSyncToUsbClk;
//sendPacket
output TxFifoRE;
input [7:0] TxFifoData;
input TxFifoEmpty;
//getPacket
output RxFifoWE;
output [7:0] RxFifoData;
input RxFifoFull;
input [7:0] RxByteStatus;
input [7:0] RxData;
input RxDataValid;
input SIERxTimeOut;
output SIERxTimeOutEn;
//speedCtrlMux
output fullSpeedRate;
output fullSpeedPol;
//HCTxPortArbiter
output HCTxPortEn;
input HCTxPortRdy;
output [7:0] HCTxPortData;
output [7:0] HCTxPortCtrl;
//rxStatusMonitor
input [1:0] connectStateIn;
input resumeDetectedIn;
//USBHostControlBI
input [3:0] busAddress;
input [7:0] busDataIn;
output [7:0] busDataOut;
input busWriteEn;
input busStrobe_i;
output SOFSentIntOut;
output connEventIntOut;
output resumeIntOut;
output transDoneIntOut;
input hostControlSelect;
wire busClk;
wire rstSyncToBusClk;
wire usbClk;
wire rstSyncToUsbClk;
wire [10:0] frameNum;
wire SOFSent;
wire TxFifoRE;
wire [7:0] TxFifoData;
wire TxFifoEmpty;
wire RxFifoWE;
wire [7:0] RxFifoData;
wire RxFifoFull;
wire [7:0] RxByteStatus;
wire [7:0] RxData;
wire RxDataValid;
wire SIERxTimeOut;
wire SIERxTimeOutEn;
wire fullSpeedRate;
wire fullSpeedPol;
wire HCTxPortEn;
wire HCTxPortRdy;
wire [7:0] HCTxPortData;
wire [7:0] HCTxPortCtrl;
wire [1:0] connectStateIn;
wire resumeDetectedIn;
wire [3:0] busAddress;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire busWriteEn;
wire busStrobe_i;
wire SOFSentIntOut;
wire connEventIntOut;
wire resumeIntOut;
wire transDoneIntOut;
wire hostControlSelect;
//internal wiring
wire SOFTimerClr;
wire getPacketREn;
wire getPacketRdy;
wire HCTxGnt;
wire HCTxReq;
wire [3:0] HC_PID;
wire HC_SP_WEn;
wire SOFTxGnt;
wire SOFTxReq;
wire SOF_SP_WEn;
wire SOFEnable;
wire SOFSyncEn;
wire sendPacketCPReadyIn;
wire sendPacketCPReadyOut;
wire [3:0] sendPacketCPPIDIn;
wire [3:0] sendPacketCPPIDOut;
wire sendPacketCPWEnIn;
wire sendPacketCPWEnOut;
wire [7:0] SOFCntlCntl;
wire [7:0] SOFCntlData;
wire SOFCntlGnt;
wire SOFCntlReq;
wire SOFCntlWEn;
wire [7:0] directCntlCntl;
wire [7:0] directCntlData;
wire directCntlGnt;
wire directCntlReq;
wire directCntlWEn;
wire [7:0] sendPacketCntl;
wire [7:0] sendPacketData;
wire sendPacketGnt;
wire sendPacketReq;
wire sendPacketWEn;
wire [15:0] SOFTimer;
wire clrTxReq;
wire transDone;
wire transReq;
wire isoEn;
wire [1:0] transType;
wire preAmbleEnable;
wire [1:0] directLineState;
wire directLineCtrlEn;
wire [6:0] TxAddr;
wire [3:0] TxEndP;
wire [7:0] RxPktStatus;
wire [3:0] RxPID;
wire [1:0] connectStateOut;
wire resumeIntFromRxStatusMon;
wire connectionEventFromRxStatusMon;
USBHostControlBI u_USBHostControlBI
(.address(busAddress),
.dataIn(busDataIn),
.dataOut(busDataOut),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.SOFSentIntOut(SOFSentIntOut),
.connEventIntOut(connEventIntOut),
.resumeIntOut(resumeIntOut),
.transDoneIntOut(transDoneIntOut),
.TxTransTypeReg(transType),
.TxSOFEnableReg(SOFEnable),
.TxAddrReg(TxAddr),
.TxEndPReg(TxEndP),
.frameNumIn(frameNum),
.RxPktStatusIn(RxPktStatus),
.RxPIDIn(RxPID),
.connectStateIn(connectStateOut),
.SOFSentIn(SOFSent),
.connEventIn(connectionEventFromRxStatusMon),
.resumeIntIn(resumeIntFromRxStatusMon),
.transDoneIn(transDone),
.hostControlSelect(hostControlSelect),
.clrTransReq(clrTxReq),
.preambleEn(preAmbleEnable),
.SOFSync(SOFSyncEn),
.TxLineState(directLineState),
.LineDirectControlEn(directLineCtrlEn),
.fullSpeedPol(fullSpeedPol),
.fullSpeedRate(fullSpeedRate),
.transReq(transReq),
.isoEn(isoEn),
.SOFTimer(SOFTimer)
);
hostcontroller u_hostController
(.RXStatus(RxPktStatus),
.clearTXReq(clrTxReq),
.clk(usbClk),
.getPacketREn(getPacketREn),
.getPacketRdy(getPacketRdy),
.rst(rstSyncToUsbClk),
.sendPacketArbiterGnt(HCTxGnt),
.sendPacketArbiterReq(HCTxReq),
.sendPacketPID(HC_PID),
.sendPacketRdy(sendPacketCPReadyOut),
.sendPacketWEn(HC_SP_WEn),
.transDone(transDone),
.transReq(transReq),
.transType(transType),
.isoEn(isoEn) );
SOFController u_SOFController
(.HCTxPortCntl(SOFCntlCntl),
.HCTxPortData(SOFCntlData),
.HCTxPortGnt(SOFCntlGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(SOFCntlReq),
.HCTxPortWEn(SOFCntlWEn),
.SOFEnable(SOFEnable),
.SOFTimerClr(SOFTimerClr),
.SOFTimer(SOFTimer),
.clk(usbClk),
.rst(rstSyncToUsbClk) );
SOFTransmit u_SOFTransmit
(.SOFEnable(SOFEnable),
.SOFSent(SOFSent),
.SOFSyncEn(SOFSyncEn),
.SOFTimerClr(SOFTimerClr),
.SOFTimer(SOFTimer),
.clk(usbClk),
.rst(rstSyncToUsbClk),
.sendPacketArbiterGnt(SOFTxGnt),
.sendPacketArbiterReq(SOFTxReq),
.sendPacketRdy(sendPacketCPReadyOut),
.sendPacketWEn(SOF_SP_WEn),
.fullSpeedRate(fullSpeedRate) );
sendPacketArbiter u_sendPacketArbiter
(.HCTxGnt(HCTxGnt),
.HCTxReq(HCTxReq),
.HC_PID(HC_PID),
.HC_SP_WEn(HC_SP_WEn),
.SOFTxGnt(SOFTxGnt),
.SOFTxReq(SOFTxReq),
.SOF_SP_WEn(SOF_SP_WEn),
.clk(usbClk),
.rst(rstSyncToUsbClk),
.sendPacketPID(sendPacketCPPIDIn),
.sendPacketWEnable(sendPacketCPWEnIn) );
sendPacketCheckPreamble u_sendPacketCheckPreamble
(.sendPacketCPPID(sendPacketCPPIDIn),
.clk(usbClk),
.preAmbleEnable(preAmbleEnable),
.rst(rstSyncToUsbClk),
.sendPacketCPReady(sendPacketCPReadyOut),
.sendPacketCPWEn(sendPacketCPWEnIn),
.sendPacketPID(sendPacketCPPIDOut),
.sendPacketRdy(sendPacketCPReadyIn),
.sendPacketWEn(sendPacketCPWEnOut) );
sendPacket u_sendPacket
(.HCTxPortCntl(sendPacketCntl),
.HCTxPortData(sendPacketData),
.HCTxPortGnt(sendPacketGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(sendPacketReq),
.HCTxPortWEn(sendPacketWEn),
.PID(sendPacketCPPIDOut),
.TxAddr(TxAddr),
.TxEndP(TxEndP),
.clk(usbClk),
.fifoData(TxFifoData),
.fifoEmpty(TxFifoEmpty),
.fifoReadEn(TxFifoRE),
.frameNum(frameNum),
.rst(rstSyncToUsbClk),
.sendPacketRdy(sendPacketCPReadyIn),
.sendPacketWEn(sendPacketCPWEnOut),
.fullSpeedPolarity(fullSpeedPol) );
directControl u_directControl
(.HCTxPortCntl(directCntlCntl),
.HCTxPortData(directCntlData),
.HCTxPortGnt(directCntlGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(directCntlReq),
.HCTxPortWEn(directCntlWEn),
.clk(usbClk),
.directControlEn(directLineCtrlEn),
.directControlLineState(directLineState),
.rst(rstSyncToUsbClk) );
HCTxPortArbiter u_HCTxPortArbiter
(.HCTxPortCntl(HCTxPortCtrl),
.HCTxPortData(HCTxPortData),
.HCTxPortWEnable(HCTxPortEn),
.SOFCntlCntl(SOFCntlCntl),
.SOFCntlData(SOFCntlData),
.SOFCntlGnt(SOFCntlGnt),
.SOFCntlReq(SOFCntlReq),
.SOFCntlWEn(SOFCntlWEn),
.clk(usbClk),
.directCntlCntl(directCntlCntl),
.directCntlData(directCntlData),
.directCntlGnt(directCntlGnt),
.directCntlReq(directCntlReq),
.directCntlWEn(directCntlWEn),
.rst(rstSyncToUsbClk),
.sendPacketCntl(sendPacketCntl),
.sendPacketData(sendPacketData),
.sendPacketGnt(sendPacketGnt),
.sendPacketReq(sendPacketReq),
.sendPacketWEn(sendPacketWEn) );
getPacket u_getPacket
(.RXDataIn(RxData),
.RXDataValid(RxDataValid),
.RXFifoData(RxFifoData),
.RXFifoFull(RxFifoFull),
.RXFifoWEn(RxFifoWE),
.RXPacketRdy(getPacketRdy),
.RXPktStatus(RxPktStatus),
.RXStreamStatusIn(RxByteStatus),
.RxPID(RxPID),
.SIERxTimeOut(SIERxTimeOut),
.SIERxTimeOutEn(SIERxTimeOutEn),
.clk(usbClk),
.getPacketEn(getPacketREn),
.rst(rstSyncToUsbClk) );
rxStatusMonitor u_rxStatusMonitor
(.connectStateIn(connectStateIn),
.connectStateOut(connectStateOut),
.resumeDetectedIn(resumeDetectedIn),
.connectionEventOut(connectionEventFromRxStatusMon),
.resumeIntOut(resumeIntFromRxStatusMon),
.clk(usbClk),
.rst(rstSyncToUsbClk) );
endmodule |
module sky130_fd_sc_ms__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule |
module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule |
module sync_signal(
input clk, /* clock */
input in, /* input signal */
output out, /* synchronized output signal */
output falling, /* synchronized falling edge output */
output rising, /* synchronized rising edge output */
);
reg [2:0] shiftreg;
initial begin
shiftreg <= 0;
end
always @(posedge clk) begin
shiftreg[2:1] <= shiftreg[1:0];
shiftreg[0] <= in;
end
assign out = shiftreg[1];
assign falling = shiftreg[2] & ~shiftreg[1];
assign rising = ~shiftreg[2] & shiftreg[1];
endmodule |
module bd_350b_slot_0_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule |
module system_acl_iface_acl_kernel_clk (
output wire kernel_clk2x_clk, // kernel_clk2x.clk
input wire pll_refclk_clk, // pll_refclk.clk
output wire ctrl_waitrequest, // ctrl.waitrequest
output wire [31:0] ctrl_readdata, // .readdata
output wire ctrl_readdatavalid, // .readdatavalid
input wire [0:0] ctrl_burstcount, // .burstcount
input wire [31:0] ctrl_writedata, // .writedata
input wire [10:0] ctrl_address, // .address
input wire ctrl_write, // .write
input wire ctrl_read, // .read
input wire [3:0] ctrl_byteenable, // .byteenable
input wire ctrl_debugaccess, // .debugaccess
output wire kernel_clk_clk, // kernel_clk.clk
output wire kernel_pll_locked_export, // kernel_pll_locked.export
input wire clk_clk, // clk.clk
input wire reset_reset_n // reset.reset_n
);
wire [63:0] pll_reconfig_0_reconfig_to_pll_reconfig_to_pll; // pll_reconfig_0:reconfig_to_pll -> kernel_pll:reconfig_to_pll
wire [63:0] kernel_pll_reconfig_from_pll_reconfig_from_pll; // kernel_pll:reconfig_from_pll -> pll_reconfig_0:reconfig_from_pll
wire kernel_pll_outclk0_clk; // kernel_pll:outclk_0 -> global_routing_kernel_clk:s
wire kernel_pll_outclk1_clk; // kernel_pll:outclk_1 -> [counter:clk2x, global_routing_kernel_clk2x:s]
wire kernel_pll_locked_export_signal; // kernel_pll:locked -> pll_lock_avs_0:lock
wire ctrl_m0_waitrequest; // mm_interconnect_0:ctrl_m0_waitrequest -> ctrl:m0_waitrequest
wire [31:0] ctrl_m0_readdata; // mm_interconnect_0:ctrl_m0_readdata -> ctrl:m0_readdata
wire ctrl_m0_debugaccess; // ctrl:m0_debugaccess -> mm_interconnect_0:ctrl_m0_debugaccess
wire [10:0] ctrl_m0_address; // ctrl:m0_address -> mm_interconnect_0:ctrl_m0_address
wire ctrl_m0_read; // ctrl:m0_read -> mm_interconnect_0:ctrl_m0_read
wire [3:0] ctrl_m0_byteenable; // ctrl:m0_byteenable -> mm_interconnect_0:ctrl_m0_byteenable
wire ctrl_m0_readdatavalid; // mm_interconnect_0:ctrl_m0_readdatavalid -> ctrl:m0_readdatavalid
wire [31:0] ctrl_m0_writedata; // ctrl:m0_writedata -> mm_interconnect_0:ctrl_m0_writedata
wire ctrl_m0_write; // ctrl:m0_write -> mm_interconnect_0:ctrl_m0_write
wire [0:0] ctrl_m0_burstcount; // ctrl:m0_burstcount -> mm_interconnect_0:ctrl_m0_burstcount
wire [31:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata; // pll_reconfig_0:mgmt_readdata -> mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_readdata
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest; // pll_reconfig_0:mgmt_waitrequest -> mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_waitrequest
wire [5:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_address -> pll_reconfig_0:mgmt_address
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_read -> pll_reconfig_0:mgmt_read
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_write -> pll_reconfig_0:mgmt_write
wire [31:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_writedata -> pll_reconfig_0:mgmt_writedata
wire mm_interconnect_0_pll_rom_s1_chipselect; // mm_interconnect_0:pll_rom_s1_chipselect -> pll_rom:chipselect
wire [31:0] mm_interconnect_0_pll_rom_s1_readdata; // pll_rom:readdata -> mm_interconnect_0:pll_rom_s1_readdata
wire mm_interconnect_0_pll_rom_s1_debugaccess; // mm_interconnect_0:pll_rom_s1_debugaccess -> pll_rom:debugaccess
wire [7:0] mm_interconnect_0_pll_rom_s1_address; // mm_interconnect_0:pll_rom_s1_address -> pll_rom:address
wire [3:0] mm_interconnect_0_pll_rom_s1_byteenable; // mm_interconnect_0:pll_rom_s1_byteenable -> pll_rom:byteenable
wire mm_interconnect_0_pll_rom_s1_write; // mm_interconnect_0:pll_rom_s1_write -> pll_rom:write
wire [31:0] mm_interconnect_0_pll_rom_s1_writedata; // mm_interconnect_0:pll_rom_s1_writedata -> pll_rom:writedata
wire mm_interconnect_0_pll_rom_s1_clken; // mm_interconnect_0:pll_rom_s1_clken -> pll_rom:clken
wire [31:0] mm_interconnect_0_counter_s_readdata; // counter:slave_readdata -> mm_interconnect_0:counter_s_readdata
wire mm_interconnect_0_counter_s_waitrequest; // counter:slave_waitrequest -> mm_interconnect_0:counter_s_waitrequest
wire [1:0] mm_interconnect_0_counter_s_address; // mm_interconnect_0:counter_s_address -> counter:slave_address
wire mm_interconnect_0_counter_s_read; // mm_interconnect_0:counter_s_read -> counter:slave_read
wire [3:0] mm_interconnect_0_counter_s_byteenable; // mm_interconnect_0:counter_s_byteenable -> counter:slave_byteenable
wire mm_interconnect_0_counter_s_readdatavalid; // counter:slave_readdatavalid -> mm_interconnect_0:counter_s_readdatavalid
wire mm_interconnect_0_counter_s_write; // mm_interconnect_0:counter_s_write -> counter:slave_write
wire [31:0] mm_interconnect_0_counter_s_writedata; // mm_interconnect_0:counter_s_writedata -> counter:slave_writedata
wire [31:0] mm_interconnect_0_pll_sw_reset_s_readdata; // pll_sw_reset:slave_readdata -> mm_interconnect_0:pll_sw_reset_s_readdata
wire mm_interconnect_0_pll_sw_reset_s_waitrequest; // pll_sw_reset:slave_waitrequest -> mm_interconnect_0:pll_sw_reset_s_waitrequest
wire mm_interconnect_0_pll_sw_reset_s_read; // mm_interconnect_0:pll_sw_reset_s_read -> pll_sw_reset:slave_read
wire [3:0] mm_interconnect_0_pll_sw_reset_s_byteenable; // mm_interconnect_0:pll_sw_reset_s_byteenable -> pll_sw_reset:slave_byteenable
wire mm_interconnect_0_pll_sw_reset_s_write; // mm_interconnect_0:pll_sw_reset_s_write -> pll_sw_reset:slave_write
wire [31:0] mm_interconnect_0_pll_sw_reset_s_writedata; // mm_interconnect_0:pll_sw_reset_s_writedata -> pll_sw_reset:slave_writedata
wire [31:0] mm_interconnect_0_pll_lock_avs_0_s_readdata; // pll_lock_avs_0:slave_readdata -> mm_interconnect_0:pll_lock_avs_0_s_readdata
wire mm_interconnect_0_pll_lock_avs_0_s_read; // mm_interconnect_0:pll_lock_avs_0_s_read -> pll_lock_avs_0:slave_read
wire [31:0] mm_interconnect_0_version_id_0_s_readdata; // version_id_0:slave_readdata -> mm_interconnect_0:version_id_0_s_readdata
wire mm_interconnect_0_version_id_0_s_read; // mm_interconnect_0:version_id_0_s_read -> version_id_0:slave_read
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> kernel_pll:rst
wire pll_sw_reset_sw_reset_reset; // pll_sw_reset:sw_reset_n_out -> rst_controller:reset_in0
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [ctrl:reset, mm_interconnect_0:ctrl_reset_reset_bridge_in_reset_reset, pll_lock_avs_0:resetn, pll_reconfig_0:mgmt_reset, pll_rom:reset, pll_sw_reset:resetn, rst_translator:in_reset, version_id_0:resetn]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [pll_rom:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [counter:resetn, mm_interconnect_0:counter_clk_reset_reset_bridge_in_reset_reset]
system_acl_iface_acl_kernel_clk_kernel_pll kernel_pll (
.refclk (pll_refclk_clk), // refclk.clk
.rst (rst_controller_reset_out_reset), // reset.reset
.outclk_0 (kernel_pll_outclk0_clk), // outclk0.clk
.outclk_1 (kernel_pll_outclk1_clk), // outclk1.clk
.locked (kernel_pll_locked_export_signal), // locked.export
.reconfig_to_pll (pll_reconfig_0_reconfig_to_pll_reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (kernel_pll_reconfig_from_pll_reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.reconf_width (64),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("")
) pll_reconfig_0 (
.mgmt_clk (clk_clk), // mgmt_clk.clk
.mgmt_reset (rst_controller_001_reset_out_reset), // mgmt_reset.reset
.mgmt_readdata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata), // mgmt_avalon_slave.readdata
.mgmt_waitrequest (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.mgmt_read (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read), // .read
.mgmt_write (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write), // .write
.mgmt_address (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address), // .address
.mgmt_writedata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.reconfig_to_pll (pll_reconfig_0_reconfig_to_pll_reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (kernel_pll_reconfig_from_pll_reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll
);
system_acl_iface_acl_kernel_clk_pll_rom pll_rom (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_pll_rom_s1_address), // s1.address
.debugaccess (mm_interconnect_0_pll_rom_s1_debugaccess), // .debugaccess
.clken (mm_interconnect_0_pll_rom_s1_clken), // .clken
.chipselect (mm_interconnect_0_pll_rom_s1_chipselect), // .chipselect
.write (mm_interconnect_0_pll_rom_s1_write), // .write
.readdata (mm_interconnect_0_pll_rom_s1_readdata), // .readdata
.writedata (mm_interconnect_0_pll_rom_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_pll_rom_s1_byteenable), // .byteenable
.reset (rst_controller_001_reset_out_reset), // reset1.reset
.reset_req (rst_controller_001_reset_out_reset_req) // .reset_req
);
timer #(
.WIDTH (32),
.S_WIDTH_A (2)
) counter (
.clk (kernel_clk_clk), // clk.clk
.clk2x (kernel_pll_outclk1_clk), // clk2x.clk
.resetn (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
.slave_address (mm_interconnect_0_counter_s_address), // s.address
.slave_writedata (mm_interconnect_0_counter_s_writedata), // .writedata
.slave_read (mm_interconnect_0_counter_s_read), // .read
.slave_write (mm_interconnect_0_counter_s_write), // .write
.slave_byteenable (mm_interconnect_0_counter_s_byteenable), // .byteenable
.slave_waitrequest (mm_interconnect_0_counter_s_waitrequest), // .waitrequest
.slave_readdata (mm_interconnect_0_counter_s_readdata), // .readdata
.slave_readdatavalid (mm_interconnect_0_counter_s_readdatavalid) // .readdatavalid
);
global_routing global_routing_kernel_clk (
.s (kernel_pll_outclk0_clk), // clk.clk
.g (kernel_clk_clk) // global_clk.clk
);
global_routing global_routing_kernel_clk2x (
.s (kernel_pll_outclk1_clk), // clk.clk
.g (kernel_clk2x_clk) // global_clk.clk
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (11),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (0),
.PIPELINE_RESPONSE (0)
) ctrl (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.s0_waitrequest (ctrl_waitrequest), // s0.waitrequest
.s0_readdata (ctrl_readdata), // .readdata
.s0_readdatavalid (ctrl_readdatavalid), // .readdatavalid
.s0_burstcount (ctrl_burstcount), // .burstcount
.s0_writedata (ctrl_writedata), // .writedata
.s0_address (ctrl_address), // .address
.s0_write (ctrl_write), // .write
.s0_read (ctrl_read), // .read
.s0_byteenable (ctrl_byteenable), // .byteenable
.s0_debugaccess (ctrl_debugaccess), // .debugaccess
.m0_waitrequest (ctrl_m0_waitrequest), // m0.waitrequest
.m0_readdata (ctrl_m0_readdata), // .readdata
.m0_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.m0_burstcount (ctrl_m0_burstcount), // .burstcount
.m0_writedata (ctrl_m0_writedata), // .writedata
.m0_address (ctrl_m0_address), // .address
.m0_write (ctrl_m0_write), // .write
.m0_read (ctrl_m0_read), // .read
.m0_byteenable (ctrl_m0_byteenable), // .byteenable
.m0_debugaccess (ctrl_m0_debugaccess), // .debugaccess
.s0_response (), // (terminated)
.m0_response (2'b00) // (terminated)
);
sw_reset #(
.WIDTH (32),
.LOG2_RESET_CYCLES (10)
) pll_sw_reset (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_0_pll_sw_reset_s_write), // s.write
.slave_writedata (mm_interconnect_0_pll_sw_reset_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_0_pll_sw_reset_s_byteenable), // .byteenable
.slave_read (mm_interconnect_0_pll_sw_reset_s_read), // .read
.slave_readdata (mm_interconnect_0_pll_sw_reset_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_0_pll_sw_reset_s_waitrequest), // .waitrequest
.sw_reset_n_out (pll_sw_reset_sw_reset_reset) // sw_reset.reset_n
);
pll_lock_avs #(
.WIDTH (32)
) pll_lock_avs_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.lock (kernel_pll_locked_export_signal), // lock.export
.lock_export (kernel_pll_locked_export), // lock_export.export
.slave_read (mm_interconnect_0_pll_lock_avs_0_s_read), // s.read
.slave_readdata (mm_interconnect_0_pll_lock_avs_0_s_readdata) // .readdata
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1598029823)
) version_id_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_0_version_id_0_s_read), // s.read
.slave_readdata (mm_interconnect_0_version_id_0_s_readdata) // .readdata
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.global_routing_kernel_clk_global_clk_clk (kernel_clk_clk), // global_routing_kernel_clk_global_clk.clk
.counter_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // counter_clk_reset_reset_bridge_in_reset.reset
.ctrl_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ctrl_reset_reset_bridge_in_reset.reset
.ctrl_m0_address (ctrl_m0_address), // ctrl_m0.address
.ctrl_m0_waitrequest (ctrl_m0_waitrequest), // .waitrequest
.ctrl_m0_burstcount (ctrl_m0_burstcount), // .burstcount
.ctrl_m0_byteenable (ctrl_m0_byteenable), // .byteenable
.ctrl_m0_read (ctrl_m0_read), // .read
.ctrl_m0_readdata (ctrl_m0_readdata), // .readdata
.ctrl_m0_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.ctrl_m0_write (ctrl_m0_write), // .write
.ctrl_m0_writedata (ctrl_m0_writedata), // .writedata
.ctrl_m0_debugaccess (ctrl_m0_debugaccess), // .debugaccess
.counter_s_address (mm_interconnect_0_counter_s_address), // counter_s.address
.counter_s_write (mm_interconnect_0_counter_s_write), // .write
.counter_s_read (mm_interconnect_0_counter_s_read), // .read
.counter_s_readdata (mm_interconnect_0_counter_s_readdata), // .readdata
.counter_s_writedata (mm_interconnect_0_counter_s_writedata), // .writedata
.counter_s_byteenable (mm_interconnect_0_counter_s_byteenable), // .byteenable
.counter_s_readdatavalid (mm_interconnect_0_counter_s_readdatavalid), // .readdatavalid
.counter_s_waitrequest (mm_interconnect_0_counter_s_waitrequest), // .waitrequest
.pll_lock_avs_0_s_read (mm_interconnect_0_pll_lock_avs_0_s_read), // pll_lock_avs_0_s.read
.pll_lock_avs_0_s_readdata (mm_interconnect_0_pll_lock_avs_0_s_readdata), // .readdata
.pll_reconfig_0_mgmt_avalon_slave_address (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address), // pll_reconfig_0_mgmt_avalon_slave.address
.pll_reconfig_0_mgmt_avalon_slave_write (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write), // .write
.pll_reconfig_0_mgmt_avalon_slave_read (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read), // .read
.pll_reconfig_0_mgmt_avalon_slave_readdata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata), // .readdata
.pll_reconfig_0_mgmt_avalon_slave_writedata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.pll_reconfig_0_mgmt_avalon_slave_waitrequest (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.pll_rom_s1_address (mm_interconnect_0_pll_rom_s1_address), // pll_rom_s1.address
.pll_rom_s1_write (mm_interconnect_0_pll_rom_s1_write), // .write
.pll_rom_s1_readdata (mm_interconnect_0_pll_rom_s1_readdata), // .readdata
.pll_rom_s1_writedata (mm_interconnect_0_pll_rom_s1_writedata), // .writedata
.pll_rom_s1_byteenable (mm_interconnect_0_pll_rom_s1_byteenable), // .byteenable
.pll_rom_s1_chipselect (mm_interconnect_0_pll_rom_s1_chipselect), // .chipselect
.pll_rom_s1_clken (mm_interconnect_0_pll_rom_s1_clken), // .clken
.pll_rom_s1_debugaccess (mm_interconnect_0_pll_rom_s1_debugaccess), // .debugaccess
.pll_sw_reset_s_write (mm_interconnect_0_pll_sw_reset_s_write), // pll_sw_reset_s.write
.pll_sw_reset_s_read (mm_interconnect_0_pll_sw_reset_s_read), // .read
.pll_sw_reset_s_readdata (mm_interconnect_0_pll_sw_reset_s_readdata), // .readdata
.pll_sw_reset_s_writedata (mm_interconnect_0_pll_sw_reset_s_writedata), // .writedata
.pll_sw_reset_s_byteenable (mm_interconnect_0_pll_sw_reset_s_byteenable), // .byteenable
.pll_sw_reset_s_waitrequest (mm_interconnect_0_pll_sw_reset_s_waitrequest), // .waitrequest
.version_id_0_s_read (mm_interconnect_0_version_id_0_s_read), // version_id_0_s.read
.version_id_0_s_readdata (mm_interconnect_0_version_id_0_s_readdata) // .readdata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("none"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~pll_sw_reset_sw_reset_reset), // reset_in0.reset
.reset_in1 (~reset_reset_n), // reset_in1.reset
.clk (), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule |
module xfft(aclk, s_axis_config_tdata, s_axis_config_tvalid, s_axis_config_tready, s_axis_data_tdata, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tlast, m_axis_data_tdata, m_axis_data_tuser, m_axis_data_tvalid, m_axis_data_tready, m_axis_data_tlast, event_frame_started, event_tlast_unexpected, event_tlast_missing, event_status_channel_halt, event_data_in_channel_halt, event_data_out_channel_halt)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tdata[7:0],s_axis_config_tvalid,s_axis_config_tready,s_axis_data_tdata[31:0],s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tlast,m_axis_data_tdata[63:0],m_axis_data_tuser[15:0],m_axis_data_tvalid,m_axis_data_tready,m_axis_data_tlast,event_frame_started,event_tlast_unexpected,event_tlast_missing,event_status_channel_halt,event_data_in_channel_halt,event_data_out_channel_halt" */;
input aclk;
input [7:0]s_axis_config_tdata;
input s_axis_config_tvalid;
output s_axis_config_tready;
input [31:0]s_axis_data_tdata;
input s_axis_data_tvalid;
output s_axis_data_tready;
input s_axis_data_tlast;
output [63:0]m_axis_data_tdata;
output [15:0]m_axis_data_tuser;
output m_axis_data_tvalid;
input m_axis_data_tready;
output m_axis_data_tlast;
output event_frame_started;
output event_tlast_unexpected;
output event_tlast_missing;
output event_status_channel_halt;
output event_data_in_channel_halt;
output event_data_out_channel_halt;
endmodule |
module test_axis_demux_64_4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] input_axis_tdata = 0;
reg [7:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_0_axis_tready = 0;
reg output_1_axis_tready = 0;
reg output_2_axis_tready = 0;
reg output_3_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire input_axis_tready;
wire [63:0] output_0_axis_tdata;
wire [7:0] output_0_axis_tkeep;
wire output_0_axis_tvalid;
wire output_0_axis_tlast;
wire output_0_axis_tuser;
wire [63:0] output_1_axis_tdata;
wire [7:0] output_1_axis_tkeep;
wire output_1_axis_tvalid;
wire output_1_axis_tlast;
wire output_1_axis_tuser;
wire [63:0] output_2_axis_tdata;
wire [7:0] output_2_axis_tkeep;
wire output_2_axis_tvalid;
wire output_2_axis_tlast;
wire output_2_axis_tuser;
wire [63:0] output_3_axis_tdata;
wire [7:0] output_3_axis_tkeep;
wire output_3_axis_tvalid;
wire output_3_axis_tlast;
wire output_3_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tkeep,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_0_axis_tready,
output_1_axis_tready,
output_2_axis_tready,
output_3_axis_tready,
enable,
select);
$to_myhdl(input_axis_tready,
output_0_axis_tdata,
output_0_axis_tkeep,
output_0_axis_tvalid,
output_0_axis_tlast,
output_0_axis_tuser,
output_1_axis_tdata,
output_1_axis_tkeep,
output_1_axis_tvalid,
output_1_axis_tlast,
output_1_axis_tuser,
output_2_axis_tdata,
output_2_axis_tkeep,
output_2_axis_tvalid,
output_2_axis_tlast,
output_2_axis_tuser,
output_3_axis_tdata,
output_3_axis_tkeep,
output_3_axis_tvalid,
output_3_axis_tlast,
output_3_axis_tuser);
// dump file
$dumpfile("test_axis_demux_64_4.lxt");
$dumpvars(0, test_axis_demux_64_4);
end
axis_demux_64_4 #(
.DATA_WIDTH(64)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI outputs
.output_0_axis_tdata(output_0_axis_tdata),
.output_0_axis_tkeep(output_0_axis_tkeep),
.output_0_axis_tvalid(output_0_axis_tvalid),
.output_0_axis_tready(output_0_axis_tready),
.output_0_axis_tlast(output_0_axis_tlast),
.output_0_axis_tuser(output_0_axis_tuser),
.output_1_axis_tdata(output_1_axis_tdata),
.output_1_axis_tkeep(output_1_axis_tkeep),
.output_1_axis_tvalid(output_1_axis_tvalid),
.output_1_axis_tready(output_1_axis_tready),
.output_1_axis_tlast(output_1_axis_tlast),
.output_1_axis_tuser(output_1_axis_tuser),
.output_2_axis_tdata(output_2_axis_tdata),
.output_2_axis_tkeep(output_2_axis_tkeep),
.output_2_axis_tvalid(output_2_axis_tvalid),
.output_2_axis_tready(output_2_axis_tready),
.output_2_axis_tlast(output_2_axis_tlast),
.output_2_axis_tuser(output_2_axis_tuser),
.output_3_axis_tdata(output_3_axis_tdata),
.output_3_axis_tkeep(output_3_axis_tkeep),
.output_3_axis_tvalid(output_3_axis_tvalid),
.output_3_axis_tready(output_3_axis_tready),
.output_3_axis_tlast(output_3_axis_tlast),
.output_3_axis_tuser(output_3_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule |
module multiplexer(q, data, select);
output q;
input [31:0] data;
input [5:0] select;
wire q;
wire [31:0] data;
wire [5:0] select;
assign q =
(select == 5'h00) ? data[0] :
(select == 5'h01) ? data[1] :
(select == 5'h02) ? data[2] :
(select == 5'h03) ? data[3] :
(select == 5'h04) ? data[4] :
(select == 5'h05) ? data[5] :
(select == 5'h06) ? data[6] :
(select == 5'h07) ? data[7] :
(select == 5'h08) ? data[8] :
(select == 5'h09) ? data[9] :
(select == 5'h0A) ? data[10] :
(select == 5'h0B) ? data[11] :
(select == 5'h0C) ? data[12] :
(select == 5'h0D) ? data[13] :
(select == 5'h0E) ? data[14] :
(select == 5'h0F) ? data[15] :
(select == 5'h10) ? data[16] :
(select == 5'h11) ? data[17] :
(select == 5'h12) ? data[18] :
(select == 5'h13) ? data[19] :
(select == 5'h14) ? data[20] :
(select == 5'h15) ? data[21] :
(select == 5'h16) ? data[22] :
(select == 5'h17) ? data[23] :
(select == 5'h18) ? data[24] :
(select == 5'h19) ? data[25] :
(select == 5'h1A) ? data[26] :
(select == 5'h1B) ? data[27] :
(select == 5'h1C) ? data[28] :
(select == 5'h1D) ? data[29] :
(select == 5'h1E) ? data[30] :
(select == 5'h1F) ? data[31] : 1'bx;
endmodule |
module outputs)
wire [1:0] out10; // From test of Test.v
wire [1:0] out32; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out32 (out32[1:0]),
.out10 (out10[1:0]),
// Inputs
.in (in[1:0]));
// Test loop
always @ (posedge clk) begin
in <= in + 1;
`ifdef TEST_VERBOSE
$write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10);
`endif
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule |
module Test (/*AUTOARG*/
// Outputs
out32, out10,
// Inputs
in
);
input [1:0] in;
output [1:0] out32;
output [1:0] out10;
assign out32 = in[3:2];
assign out10 = in[1:0];
endmodule |
module CRC_chk(
Reset ,
Clk ,
CRC_data ,
CRC_init ,
CRC_en ,
//From CPU
CRC_chk_en ,
CRC_err
);
input Reset ;
input Clk ;
input[7:0] CRC_data ;
input CRC_init ;
input CRC_en ;
//From CPU
input CRC_chk_en ;
output CRC_err ;
//******************************************************************************
//internal signals
//******************************************************************************
reg [31:0] CRC_reg;
wire[31:0] Next_CRC;
//******************************************************************************
//input data width is 8bit, and the first bit is bit[0]
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0]=C[24]^C[30]^D[1]^D[7];
NewCRC[1]=C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2]=C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3]=C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4]=C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5]=C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6]=C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7]=C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8]=C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9]=C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10]=C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11]=C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12]=C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13]=C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14]=C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15]=C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16]=C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17]=C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18]=C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19]=C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20]=C[12]^C[28]^D[3];
NewCRC[21]=C[13]^C[29]^D[2];
NewCRC[22]=C[14]^C[24]^D[7];
NewCRC[23]=C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24]=C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25]=C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26]=C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27]=C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28]=C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29]=C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30]=C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31]=C[23]^C[29]^D[2];
NextCRC=NewCRC;
end
endfunction
always @ (posedge Clk or posedge Reset)
if (Reset)
CRC_reg <=32'hffffffff;
else if (CRC_init)
CRC_reg <=32'hffffffff;
else if (CRC_en)
CRC_reg <=NextCRC(CRC_data,CRC_reg);
assign CRC_err = CRC_chk_en&(CRC_reg[31:0] != 32'hc704dd7b);
endmodule |
module altera_mult_add_q1u2
(
aclr0,
clock0,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_pipeline_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_register3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.selected_device_family = "Cyclone IV E",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_pipeline_aclr_a = "ACLR0",
altera_mult_add_rtl1.signed_pipeline_aclr_b = "ACLR0",
altera_mult_add_rtl1.signed_pipeline_register_a = "CLOCK0",
altera_mult_add_rtl1.signed_pipeline_register_b = "CLOCK0",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 32,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule |
module sky130_fd_sc_lp__sleep_sergate_plv (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
// Module ports
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
// Local signals
wire vgnd ;
wire pwrgood_pp0_out_VIRTPWR;
// Name Output Other arguments
pulldown pulldown0 (vgnd );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_VIRTPWR, VPWR, VPWR, vgnd );
bufif0 bufif00 (VIRTPWR , pwrgood_pp0_out_VIRTPWR, SLEEP);
endmodule |
module sync #(
// implementation options
parameter IMP_TEST = 1,
parameter IMP_FILTER = 1,
parameter IMP_DDR = 1,
// data width
parameter DW = 32
)(
// configuration and control signals
input wire intTestMode,
input wire numberScheme,
input wire filter_mode,
input wire demux_mode,
input wire falling_edge,
// input stream
input wire sti_clk,
input wire sti_rst,
input wire [DW-1:0] sti_data_p,
input wire [DW-1:0] sti_data_n,
// output stream
output wire [DW-1:0] sto_data,
output wire sto_valid
);
//
// Sample config flags (for better synthesis)...
//
dly_signal sampled_intTestMode_reg (sti_clk, intTestMode , sampled_intTestMode );
dly_signal sampled_numberScheme_reg (sti_clk, numberScheme, sampled_numberScheme);
//
// Internal test mode. Put a 8-bit test pattern munged in
// different ways onto the 32-bit input...
//
reg [7:0] tc;
initial tc=0;
always @ (posedge sti_clk, posedge sti_rst)
if (sti_rst) tc <= 8'h00;
else tc <= tc + 'b1;
wire [7:0] tc1 = {tc[0],tc[1],tc[2],tc[3],tc[4],tc[5],tc[6],tc[7]};
wire [7:0] tc2 = {tc[3],tc[2],tc[1],tc[0],tc[4],tc[5],tc[6],tc[7]};
wire [7:0] tc3 = {tc[3],tc[2],tc[1],tc[0],tc[7],tc[6],tc[5],tc[4]};
wire [31:0] itm_count;
dly_signal #(DW) sampled_tc_reg (sti_clk, {tc3,tc2,tc1,tc}, itm_count);
wire [DW-1:0] itm_sti_data_p = (sampled_intTestMode) ? itm_count : sti_data_p;
wire [DW-1:0] itm_sti_data_n = (sampled_intTestMode) ? ~itm_count : sti_data_n;
//
// posedge resynchronization and delay of input data
reg [DW-1:0] dly_sti_data_p;
reg [DW-1:0] dly_sti_data_n;
always @(posedge sti_clk)
begin
dly_sti_data_p <= sti_data_p;
dly_sti_data_n <= sti_data_n;
end
//
// Instantiate demux. Special case for number scheme mode, since demux upper bits we have
// the final full 32-bit shouldn't be swapped. So it's preswapped here, to "undo" the final
// numberscheme on output...
//
// Demultiplexes 16 input channels into 32 output channels,
// thus doubling the sampling rate for those channels.
//
wire [DW-1:0] demux_sti_data = (sampled_numberScheme) ? {sti_data_p[DW/2+:DW/2], dly_sti_data_n[DW/2+:DW/2]}
: {sti_data_p[ 0 +:DW/2], dly_sti_data_n[ 0 +:DW/2]};
//
// Fast 32 channel digital noise filter using a single LUT function for each
// individual channel. It will filter out all pulses that only appear for half
// a clock cycle. This way a pulse has to be at least 5-10ns long to be accepted
// as valid. This is sufficient for sample rates up to 100MHz.
//
reg [DW-1:0] filtered_sti_data;
always @(posedge sti_clk)
filtered_sti_data <= (filtered_sti_data | dly_sti_data_p | sti_data_p) & dly_sti_data_n;
//
// Another pipeline step for sti_data selector to not decrease maximum clock rate...
//
reg [1:0] select;
reg [DW-1:0] selectdata;
always @(posedge sti_clk)
begin
// IED - better starting point for synth tools...
if (demux_mode) select <= 2'b10;
else if (filter_mode) select <= 2'b11;
else select <= {1'b0,falling_edge};
// 4:1 mux...
case (select)
2'b00 : selectdata <= itm_sti_data_p;
2'b01 : selectdata <= itm_sti_data_n;
2'b10 : selectdata <= demux_sti_data;
2'b11 : selectdata <= filtered_sti_data;
endcase
end
//
// Apply number scheme. ie: swap upper/lower 16 bits as desired...
//
assign sto_data = (sampled_numberScheme) ? {selectdata[15:0],selectdata[31:16]} : selectdata;
assign sto_valid = 1'b1;
endmodule |
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule |
module Freq_Count_Top(
input sys_clk_50m,ch_c,
output reg [63:0] freq_reg,
input sys_rst_n
);
reg Gate_1S; //1ÃëÖÓ¼ÆÊý´°¿Ú
wire Load;
reg EN_FT;
reg CLR;
//-----------------------------------------------------------------------
parameter HIGH_TIME_Gate_1S = 50_000_000;
parameter LOW_TIME_Gate_1S = 100_000_000;
//-----------------------------------------------------------------------
reg [31:0] count;
always@(posedge sys_clk_50m or negedge sys_rst_n)begin
if(!sys_rst_n)begin
count <= 32'b0;
Gate_1S <= 1'b0;
end
else begin
count <= count + 1'b1;
if(count == HIGH_TIME_Gate_1S)
Gate_1S <= 1'b0;
else if(count == LOW_TIME_Gate_1S)begin
count <= 32'b1;
Gate_1S <= 1'b1;
end
end
end
//-----------------------------------------------------------------------
always@(posedge ch_c)
CLR <= Gate_1S | EN_FT;
always@(posedge ch_c or negedge sys_rst_n)begin
if(!sys_rst_n)begin
EN_FT = 0;
end
else begin
EN_FT = Gate_1S;
end
end
assign Load = !EN_FT;
reg [63:0] FT_out;
always @(posedge ch_c or negedge CLR)begin
if(!CLR)begin
FT_out <= 64'b0;
end
else if(EN_FT)begin
FT_out <= FT_out + 1'b1;
end
end
// COUNTER_LOAD_MACRO #(
// .COUNT_BY(48'h000000000001),
// .DEVICE("7SERIES"),
// .WIDTH_DATA(48)
// ) freq_counter (
// .Q(FT_out),
// .CLK(ch_c),
// .CE(EN_FT),
// .DIRECTION(1'b1),
// .LOAD(CLR),
// .LOAD_DATA(32'b0),
// .RST(!sys_rst_n)
// );
always@(posedge Load)begin
//freq_reg <= {16'b0, FT_out};
freq_reg <= FT_out;
end
endmodule |
module var23_multi(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, valid);
wire _0000_;
wire _0001_;
wire _0002_;
wire _0003_;
wire _0004_;
wire _0005_;
wire _0006_;
wire _0007_;
wire _0008_;
wire _0009_;
wire _0010_;
wire _0011_;
wire _0012_;
wire _0013_;
wire _0014_;
wire _0015_;
wire _0016_;
wire _0017_;
wire _0018_;
wire _0019_;
wire _0020_;
wire _0021_;
wire _0022_;
wire _0023_;
wire _0024_;
wire _0025_;
wire _0026_;
wire _0027_;
wire _0028_;
wire _0029_;
wire _0030_;
wire _0031_;
wire _0032_;
wire _0033_;
wire _0034_;
wire _0035_;
wire _0036_;
wire _0037_;
wire _0038_;
wire _0039_;
wire _0040_;
wire _0041_;
wire _0042_;
wire _0043_;
wire _0044_;
wire _0045_;
wire _0046_;
wire _0047_;
wire _0048_;
wire _0049_;
wire _0050_;
wire _0051_;
wire _0052_;
wire _0053_;
wire _0054_;
wire _0055_;
wire _0056_;
wire _0057_;
wire _0058_;
wire _0059_;
wire _0060_;
wire _0061_;
wire _0062_;
wire _0063_;
wire _0064_;
wire _0065_;
wire _0066_;
wire _0067_;
wire _0068_;
wire _0069_;
wire _0070_;
wire _0071_;
wire _0072_;
wire _0073_;
wire _0074_;
wire _0075_;
wire _0076_;
wire _0077_;
wire _0078_;
wire _0079_;
wire _0080_;
wire _0081_;
wire _0082_;
wire _0083_;
wire _0084_;
wire _0085_;
wire _0086_;
wire _0087_;
wire _0088_;
wire _0089_;
wire _0090_;
wire _0091_;
wire _0092_;
wire _0093_;
wire _0094_;
wire _0095_;
wire _0096_;
wire _0097_;
wire _0098_;
wire _0099_;
wire _0100_;
wire _0101_;
wire _0102_;
wire _0103_;
wire _0104_;
wire _0105_;
wire _0106_;
wire _0107_;
wire _0108_;
wire _0109_;
wire _0110_;
wire _0111_;
wire _0112_;
wire _0113_;
wire _0114_;
wire _0115_;
wire _0116_;
wire _0117_;
wire _0118_;
wire _0119_;
wire _0120_;
wire _0121_;
wire _0122_;
wire _0123_;
wire _0124_;
wire _0125_;
wire _0126_;
wire _0127_;
wire _0128_;
wire _0129_;
wire _0130_;
wire _0131_;
wire _0132_;
wire _0133_;
wire _0134_;
wire _0135_;
wire _0136_;
wire _0137_;
wire _0138_;
wire _0139_;
wire _0140_;
wire _0141_;
wire _0142_;
wire _0143_;
wire _0144_;
wire _0145_;
wire _0146_;
wire _0147_;
wire _0148_;
wire _0149_;
wire _0150_;
wire _0151_;
wire _0152_;
wire _0153_;
wire _0154_;
wire _0155_;
wire _0156_;
wire _0157_;
wire _0158_;
wire _0159_;
wire _0160_;
wire _0161_;
wire _0162_;
wire _0163_;
wire _0164_;
wire _0165_;
wire _0166_;
wire _0167_;
wire _0168_;
wire _0169_;
wire _0170_;
wire _0171_;
wire _0172_;
wire _0173_;
wire _0174_;
wire _0175_;
wire _0176_;
wire _0177_;
wire _0178_;
wire _0179_;
wire _0180_;
wire _0181_;
wire _0182_;
wire _0183_;
wire _0184_;
wire _0185_;
wire _0186_;
wire _0187_;
wire _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire _0193_;
wire _0194_;
wire _0195_;
wire _0196_;
wire _0197_;
wire _0198_;
wire _0199_;
wire _0200_;
wire _0201_;
wire _0202_;
wire _0203_;
wire _0204_;
wire _0205_;
wire _0206_;
wire _0207_;
wire _0208_;
wire _0209_;
wire _0210_;
wire _0211_;
wire _0212_;
wire _0213_;
wire _0214_;
wire _0215_;
wire _0216_;
wire _0217_;
wire _0218_;
wire _0219_;
wire _0220_;
wire _0221_;
wire _0222_;
wire _0223_;
wire _0224_;
wire _0225_;
wire _0226_;
wire _0227_;
wire _0228_;
wire _0229_;
wire _0230_;
wire _0231_;
wire _0232_;
wire _0233_;
wire _0234_;
wire _0235_;
wire _0236_;
wire _0237_;
wire _0238_;
wire _0239_;
wire _0240_;
wire _0241_;
wire _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire _0259_;
wire _0260_;
wire _0261_;
wire _0262_;
wire _0263_;
wire _0264_;
wire _0265_;
wire _0266_;
wire _0267_;
wire _0268_;
wire _0269_;
wire _0270_;
wire _0271_;
wire _0272_;
wire _0273_;
wire _0274_;
wire _0275_;
wire _0276_;
wire _0277_;
wire _0278_;
wire _0279_;
wire _0280_;
wire _0281_;
wire _0282_;
wire _0283_;
wire _0284_;
wire _0285_;
wire _0286_;
wire _0287_;
wire _0288_;
wire _0289_;
wire _0290_;
wire _0291_;
wire _0292_;
wire _0293_;
wire _0294_;
wire _0295_;
wire _0296_;
wire _0297_;
wire _0298_;
wire _0299_;
wire _0300_;
wire _0301_;
wire _0302_;
wire _0303_;
wire _0304_;
wire _0305_;
wire _0306_;
wire _0307_;
wire _0308_;
wire _0309_;
wire _0310_;
wire _0311_;
wire _0312_;
wire _0313_;
wire _0314_;
wire _0315_;
wire _0316_;
wire _0317_;
wire _0318_;
wire _0319_;
wire _0320_;
wire _0321_;
wire _0322_;
wire _0323_;
wire _0324_;
wire _0325_;
wire _0326_;
wire _0327_;
wire _0328_;
wire _0329_;
wire _0330_;
wire _0331_;
wire _0332_;
wire _0333_;
wire _0334_;
wire _0335_;
wire _0336_;
wire _0337_;
wire _0338_;
wire _0339_;
wire _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
wire _0377_;
wire _0378_;
wire _0379_;
wire _0380_;
wire _0381_;
wire _0382_;
wire _0383_;
wire _0384_;
wire _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire _0392_;
wire _0393_;
wire _0394_;
wire _0395_;
wire _0396_;
wire _0397_;
wire _0398_;
wire _0399_;
wire _0400_;
wire _0401_;
wire _0402_;
wire _0403_;
wire _0404_;
wire _0405_;
wire _0406_;
wire _0407_;
wire _0408_;
wire _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
wire _0417_;
wire _0418_;
wire _0419_;
wire _0420_;
wire _0421_;
wire _0422_;
wire _0423_;
wire _0424_;
wire _0425_;
wire _0426_;
wire _0427_;
wire _0428_;
wire _0429_;
wire _0430_;
wire _0431_;
wire _0432_;
wire _0433_;
wire _0434_;
wire _0435_;
wire _0436_;
wire _0437_;
wire _0438_;
wire _0439_;
wire _0440_;
wire _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
wire _0445_;
wire _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
wire _0450_;
wire _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
wire _0455_;
wire _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
wire _0460_;
wire _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
wire _0465_;
wire _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
wire _0470_;
wire _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
wire _0475_;
wire _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
wire _0480_;
wire _0481_;
wire _0482_;
wire _0483_;
wire _0484_;
wire _0485_;
wire _0486_;
wire _0487_;
wire _0488_;
wire _0489_;
wire _0490_;
wire _0491_;
wire _0492_;
wire _0493_;
wire _0494_;
wire _0495_;
wire _0496_;
wire _0497_;
wire _0498_;
wire _0499_;
wire _0500_;
wire _0501_;
wire _0502_;
wire _0503_;
wire _0504_;
wire _0505_;
wire _0506_;
wire _0507_;
wire _0508_;
wire _0509_;
wire _0510_;
wire _0511_;
wire _0512_;
wire _0513_;
wire _0514_;
wire _0515_;
wire _0516_;
wire _0517_;
wire _0518_;
wire _0519_;
wire _0520_;
wire _0521_;
wire _0522_;
wire _0523_;
wire _0524_;
wire _0525_;
wire _0526_;
wire _0527_;
wire _0528_;
wire _0529_;
wire _0530_;
wire _0531_;
wire _0532_;
wire _0533_;
wire _0534_;
wire _0535_;
wire _0536_;
wire _0537_;
wire _0538_;
wire _0539_;
wire _0540_;
wire _0541_;
wire _0542_;
wire _0543_;
wire _0544_;
wire _0545_;
wire _0546_;
wire _0547_;
wire _0548_;
wire _0549_;
wire _0550_;
wire _0551_;
wire _0552_;
wire _0553_;
wire _0554_;
wire _0555_;
wire _0556_;
wire _0557_;
wire _0558_;
wire _0559_;
wire _0560_;
wire _0561_;
wire _0562_;
wire _0563_;
wire _0564_;
wire _0565_;
wire _0566_;
wire _0567_;
wire _0568_;
wire _0569_;
wire _0570_;
wire _0571_;
wire _0572_;
wire _0573_;
wire _0574_;
wire _0575_;
wire _0576_;
wire _0577_;
wire _0578_;
wire _0579_;
wire _0580_;
wire _0581_;
wire _0582_;
wire _0583_;
wire _0584_;
wire _0585_;
wire _0586_;
wire _0587_;
wire _0588_;
wire _0589_;
wire _0590_;
wire _0591_;
wire _0592_;
wire _0593_;
wire _0594_;
wire _0595_;
wire _0596_;
wire _0597_;
wire _0598_;
wire _0599_;
wire _0600_;
wire _0601_;
wire _0602_;
wire _0603_;
wire _0604_;
wire _0605_;
wire _0606_;
wire _0607_;
wire _0608_;
wire _0609_;
wire _0610_;
wire _0611_;
wire _0612_;
wire _0613_;
wire _0614_;
wire _0615_;
wire _0616_;
wire _0617_;
wire _0618_;
wire _0619_;
wire _0620_;
wire _0621_;
wire _0622_;
wire _0623_;
wire _0624_;
wire _0625_;
wire _0626_;
wire _0627_;
wire _0628_;
wire _0629_;
wire _0630_;
wire _0631_;
wire _0632_;
wire _0633_;
wire _0634_;
wire _0635_;
wire _0636_;
wire _0637_;
wire _0638_;
wire _0639_;
wire _0640_;
wire _0641_;
wire _0642_;
wire _0643_;
wire _0644_;
wire _0645_;
wire _0646_;
wire _0647_;
wire _0648_;
wire _0649_;
wire _0650_;
wire _0651_;
wire _0652_;
wire _0653_;
wire _0654_;
wire _0655_;
wire _0656_;
wire _0657_;
wire _0658_;
wire _0659_;
wire _0660_;
wire _0661_;
wire _0662_;
wire _0663_;
wire _0664_;
wire _0665_;
wire _0666_;
wire _0667_;
wire _0668_;
wire _0669_;
wire _0670_;
wire _0671_;
wire _0672_;
wire _0673_;
wire _0674_;
wire _0675_;
wire _0676_;
wire _0677_;
wire _0678_;
wire _0679_;
wire _0680_;
wire _0681_;
wire _0682_;
wire _0683_;
wire _0684_;
wire _0685_;
wire _0686_;
wire _0687_;
wire _0688_;
wire _0689_;
wire _0690_;
wire _0691_;
wire _0692_;
wire _0693_;
wire _0694_;
wire _0695_;
wire _0696_;
wire _0697_;
wire _0698_;
wire _0699_;
wire _0700_;
wire _0701_;
wire _0702_;
wire _0703_;
wire _0704_;
wire _0705_;
wire _0706_;
wire _0707_;
wire _0708_;
wire _0709_;
wire _0710_;
wire _0711_;
wire _0712_;
wire _0713_;
wire _0714_;
wire _0715_;
wire _0716_;
wire _0717_;
wire _0718_;
wire _0719_;
wire _0720_;
wire _0721_;
wire _0722_;
wire _0723_;
wire _0724_;
wire _0725_;
wire _0726_;
wire _0727_;
wire _0728_;
wire _0729_;
wire _0730_;
wire _0731_;
wire _0732_;
wire _0733_;
wire _0734_;
wire _0735_;
wire _0736_;
wire _0737_;
wire _0738_;
wire _0739_;
wire _0740_;
wire _0741_;
wire _0742_;
wire _0743_;
wire _0744_;
wire _0745_;
wire _0746_;
wire _0747_;
wire _0748_;
wire _0749_;
wire _0750_;
wire _0751_;
wire _0752_;
wire _0753_;
wire _0754_;
wire _0755_;
wire _0756_;
wire _0757_;
wire _0758_;
wire _0759_;
wire _0760_;
wire _0761_;
wire _0762_;
wire _0763_;
wire _0764_;
wire _0765_;
wire _0766_;
wire _0767_;
wire _0768_;
wire _0769_;
wire _0770_;
wire _0771_;
(* src = "var23_multi.v:3" *)
input A;
(* src = "var23_multi.v:3" *)
input B;
(* src = "var23_multi.v:3" *)
input C;
(* src = "var23_multi.v:3" *)
input D;
(* src = "var23_multi.v:3" *)
input E;
(* src = "var23_multi.v:3" *)
input F;
(* src = "var23_multi.v:3" *)
input G;
(* src = "var23_multi.v:3" *)
input H;
(* src = "var23_multi.v:3" *)
input I;
(* src = "var23_multi.v:3" *)
input J;
(* src = "var23_multi.v:3" *)
input K;
(* src = "var23_multi.v:3" *)
input L;
(* src = "var23_multi.v:3" *)
input M;
(* src = "var23_multi.v:3" *)
input N;
(* src = "var23_multi.v:3" *)
input O;
(* src = "var23_multi.v:3" *)
input P;
(* src = "var23_multi.v:3" *)
input Q;
(* src = "var23_multi.v:3" *)
input R;
(* src = "var23_multi.v:3" *)
input S;
(* src = "var23_multi.v:3" *)
input T;
(* src = "var23_multi.v:3" *)
input U;
(* src = "var23_multi.v:3" *)
input V;
(* src = "var23_multi.v:3" *)
input W;
(* src = "var23_multi.v:4" *)
output valid;
assign _0150_ = ~W;
assign _0161_ = ~T;
assign _0172_ = ~P;
assign _0183_ = ~J;
assign _0194_ = ~(B ^ A);
assign _0205_ = _0194_ ^ _0183_;
assign _0216_ = _0205_ ^ K;
assign _0227_ = _0216_ & M;
assign _0238_ = ~(_0205_ & K);
assign _0259_ = B & A;
assign _0260_ = ~(B | A);
assign _0271_ = J ? _0259_ : _0260_;
assign _0282_ = _0271_ ^ _0238_;
assign _0293_ = _0282_ ^ L;
assign _0304_ = _0293_ ^ _0227_;
assign _0315_ = ~O;
assign _0336_ = _0216_ ^ M;
assign _0337_ = _0336_ | _0315_;
assign _0348_ = _0337_ ^ _0304_;
assign _0359_ = ~(_0348_ | _0172_);
assign _0370_ = ~((_0336_ | _0304_) & O);
assign _0381_ = ~N;
assign _0392_ = _0293_ & _0227_;
assign _0403_ = ~D;
assign _0414_ = ~C;
assign _0425_ = _0259_ ^ _0414_;
assign _0436_ = _0425_ ^ _0403_;
assign _0447_ = _0436_ ^ G;
assign _0458_ = _0447_ ^ H;
assign _0469_ = _0458_ ^ I;
assign _0480_ = _0260_ & J;
assign _0491_ = _0480_ ^ _0469_;
assign _0502_ = _0491_ ^ K;
assign _0513_ = ~(_0271_ | _0238_);
assign _0524_ = _0282_ & L;
assign _0535_ = _0524_ | _0513_;
assign _0546_ = _0535_ ^ _0502_;
assign _0557_ = _0546_ ^ _0392_;
assign _0568_ = _0557_ ^ _0381_;
assign _0579_ = _0568_ ^ _0370_;
assign _0590_ = _0579_ & _0359_;
assign _0611_ = ~(_0579_ | _0359_);
assign _0612_ = _0611_ | _0590_;
assign _0623_ = ~Q;
assign _0634_ = _0348_ ^ _0172_;
assign _0645_ = ~(_0634_ | _0623_);
assign _0656_ = _0645_ ^ _0612_;
assign _0667_ = _0656_ ^ R;
assign _0678_ = _0667_ ^ S;
assign _0689_ = _0678_ ^ _0161_;
assign _0700_ = _0336_ ^ _0315_;
assign _0711_ = _0700_ | _0161_;
assign _0722_ = _0634_ ^ _0623_;
assign _0733_ = _0722_ ^ _0711_;
assign _0744_ = _0733_ & U;
assign _0752_ = _0744_ & _0689_;
assign _0753_ = _0667_ & S;
assign _0754_ = _0568_ | _0370_;
assign _0755_ = _0557_ | _0381_;
assign _0756_ = _0546_ & _0392_;
assign _0757_ = _0502_ & _0524_;
assign _0758_ = ~_0513_;
assign _0759_ = ~(_0491_ & K);
assign _0760_ = ~(_0759_ & _0758_);
assign _0761_ = ~I;
assign _0762_ = _0458_ ^ _0761_;
assign _0763_ = ~((_0762_ & _0260_) | _0183_);
assign _0764_ = _0458_ | _0761_;
assign _0765_ = ~(_0425_ | _0403_);
assign _0766_ = ~((_0259_ & _0414_) | _0260_);
assign _0767_ = _0766_ ^ _0765_;
assign _0768_ = _0767_ ^ F;
assign _0769_ = _0436_ & G;
assign _0770_ = ~((_0447_ & H) | _0769_);
assign _0771_ = ~(_0770_ ^ _0768_);
assign _0000_ = _0771_ ^ J;
assign _0001_ = _0000_ ^ _0764_;
assign _0002_ = _0001_ ^ _0763_;
assign _0003_ = ~(_0002_ ^ _0760_);
assign _0004_ = _0003_ ^ _0757_;
assign _0005_ = _0004_ ^ M;
assign _0006_ = _0005_ ^ _0756_;
assign _0007_ = _0006_ ^ _0755_;
assign _0008_ = _0007_ ^ _0754_;
assign _0009_ = ~(_0008_ & _0590_);
assign _0010_ = _0008_ | _0590_;
assign _0011_ = ~(_0010_ & _0009_);
assign _0012_ = _0645_ & _0612_;
assign _0013_ = ~((_0656_ & R) | _0012_);
assign _0014_ = ~(_0013_ ^ _0011_);
assign _0015_ = _0014_ ^ _0161_;
assign _0016_ = _0015_ ^ _0753_;
assign _0017_ = ~(_0678_ | _0161_);
assign _0018_ = ~(_0722_ | _0711_);
assign _0019_ = _0018_ & _0689_;
assign _0020_ = ~(_0019_ | _0017_);
assign _0021_ = ~(_0020_ ^ _0016_);
assign _0022_ = ~(_0021_ ^ _0752_);
assign _0023_ = _0733_ ^ U;
assign _0024_ = _0023_ & W;
assign _0025_ = ~(_0744_ | _0018_);
assign _0026_ = _0025_ ^ _0689_;
assign _0027_ = ~_0026_;
assign _0028_ = _0023_ ^ W;
assign _0029_ = _0700_ ^ _0161_;
assign _0030_ = ~((_0029_ | _0028_) & (_0027_ | _0024_));
assign _0031_ = ~((_0022_ & _0150_) | _0030_);
assign _0032_ = ~V;
assign _0033_ = _0021_ & _0752_;
assign _0034_ = ~((_0014_ & _0678_) | _0161_);
assign _0035_ = ~((_0019_ & _0016_) | _0034_);
assign _0036_ = ~R;
assign _0037_ = ~((_0011_ & _0656_) | _0036_);
assign _0038_ = ~_0634_;
assign _0039_ = ~(_0038_ & _0611_);
assign _0040_ = ~((_0039_ | _0010_) & _0009_);
assign _0041_ = ~(_0040_ & Q);
assign _0042_ = ~(_0007_ | _0754_);
assign _0043_ = _0006_ | _0755_;
assign _0044_ = ~(_0004_ & M);
assign _0045_ = ~(_0005_ & _0756_);
assign _0046_ = ~(_0045_ & _0044_);
assign _0047_ = _0003_ & _0757_;
assign _0048_ = ~((_0759_ & _0758_) | _0002_);
assign _0049_ = ~(_0260_ | _0183_);
assign _0050_ = ~(_0762_ & _0049_);
assign _0051_ = ~((_0771_ | _0469_) & J);
assign _0052_ = ~((_0050_ | _0001_) & _0051_);
assign _0053_ = ~(_0768_ & _0769_);
assign _0054_ = ~F;
assign _0055_ = _0767_ | _0054_;
assign _0056_ = D & C;
assign _0057_ = ~(_0056_ | _0260_);
assign _0058_ = _0057_ | _0259_;
assign _0059_ = _0058_ ^ _0055_;
assign _0060_ = _0059_ ^ _0053_;
assign _0061_ = ~H;
assign _0062_ = _0447_ & H;
assign _0063_ = _0768_ & _0062_;
assign _0064_ = ~(_0063_ | _0061_);
assign _0065_ = _0064_ ^ _0060_;
assign _0066_ = _0771_ | _0458_;
assign _0067_ = _0066_ & I;
assign _0068_ = _0067_ ^ _0065_;
assign _0069_ = _0068_ ^ _0052_;
assign _0070_ = _0069_ ^ _0048_;
assign _0071_ = ~(_0070_ ^ _0047_);
assign _0072_ = _0071_ ^ _0046_;
assign _0073_ = _0072_ ^ _0043_;
assign _0074_ = _0073_ ^ O;
assign _0075_ = _0074_ ^ _0042_;
assign _0076_ = _0075_ ^ P;
assign _0077_ = _0076_ ^ _0009_;
assign _0078_ = _0077_ ^ _0041_;
assign _0079_ = ~(_0078_ ^ _0037_);
assign _0080_ = _0014_ & _0753_;
assign _0081_ = _0080_ ^ _0079_;
assign _0082_ = _0081_ ^ _0035_;
assign _0083_ = _0082_ ^ U;
assign _0084_ = ~(_0083_ ^ _0033_);
assign _0085_ = ~(_0084_ | _0032_);
assign _0086_ = ~_0085_;
assign _0087_ = _0082_ & U;
assign _0088_ = ~((_0083_ & _0033_) | _0087_);
assign _0089_ = ~(_0081_ | _0035_);
assign _0090_ = _0078_ & _0037_;
assign _0091_ = ~(_0075_ & P);
assign _0092_ = ~(_0075_ | P);
assign _0093_ = ~((_0092_ | _0009_) & _0091_);
assign _0094_ = _0073_ & O;
assign _0095_ = _0074_ & _0042_;
assign _0096_ = _0095_ | _0094_;
assign _0097_ = ~((_0045_ & _0044_) | _0071_);
assign _0098_ = _0070_ & _0047_;
assign _0099_ = _0067_ & _0065_;
assign _0100_ = _0060_ & H;
assign _0101_ = _0100_ | _0063_;
assign _0102_ = ~(_0059_ | _0053_);
assign _0103_ = ~((_0058_ | _0767_) & F);
assign _0104_ = ~_0260_;
assign _0105_ = ~((_0056_ & _0104_) | _0259_);
assign _0106_ = _0105_ ^ _0103_;
assign _0107_ = _0106_ ^ _0102_;
assign _0108_ = _0107_ ^ _0101_;
assign _0109_ = _0108_ ^ _0099_;
assign _0110_ = _0068_ & _0052_;
assign _0111_ = _0069_ & _0048_;
assign _0112_ = ~(_0111_ | _0110_);
assign _0113_ = ~(_0112_ ^ _0109_);
assign _0114_ = _0113_ ^ _0098_;
assign _0115_ = _0114_ ^ _0097_;
assign _0116_ = ~(_0006_ | _0557_);
assign _0117_ = ~((_0072_ & _0116_) | _0381_);
assign _0118_ = _0117_ ^ _0115_;
assign _0119_ = _0118_ ^ _0096_;
assign _0120_ = _0119_ ^ _0093_;
assign _0121_ = ~((_0077_ & _0040_) | _0623_);
assign _0122_ = _0121_ ^ _0120_;
assign _0123_ = _0122_ ^ _0090_;
assign _0124_ = ~S;
assign _0125_ = _0014_ & _0667_;
assign _0126_ = ~((_0125_ & _0079_) | _0124_);
assign _0127_ = _0126_ ^ _0123_;
assign _0128_ = ~(_0127_ ^ _0089_);
assign _0129_ = _0128_ & _0088_;
assign _0130_ = ~_0023_;
assign _0131_ = ~((_0026_ | _0130_) & _0022_);
assign _0132_ = ~((_0131_ | _0031_) & W);
assign _0133_ = ~((_0129_ & _0086_) | _0132_);
assign _0134_ = ~((_0084_ & _0032_) | _0129_);
assign _0135_ = ~((_0134_ | _0133_) & (_0031_ | W));
assign _0136_ = G & E;
assign _0137_ = ~_0136_;
assign _0138_ = G | E;
assign _0139_ = _0138_ & _0137_;
assign _0140_ = _0139_ ^ _0061_;
assign _0141_ = _0140_ ^ I;
assign _0142_ = _0141_ ^ J;
assign _0143_ = _0142_ & K;
assign _0144_ = _0141_ & J;
assign _0145_ = ~(_0139_ | _0061_);
assign _0146_ = D ^ A;
assign _0147_ = _0146_ ^ F;
assign _0148_ = _0147_ ^ _0136_;
assign _0149_ = _0148_ ^ _0145_;
assign _0151_ = ~(_0140_ & I);
assign _0152_ = _0149_ ^ _0151_;
assign _0153_ = _0144_ ? _0149_ : _0152_;
assign _0154_ = _0153_ ^ _0143_;
assign _0155_ = _0142_ ^ K;
assign _0156_ = ~(_0155_ | _0381_);
assign _0157_ = _0155_ ^ _0381_;
assign _0158_ = ~((_0157_ & O) | _0156_);
assign _0159_ = _0158_ ^ _0154_;
assign _0160_ = _0157_ ^ O;
assign _0162_ = _0160_ ^ P;
assign _0163_ = _0162_ | J;
assign _0164_ = ~((_0163_ | _0159_) & Q);
assign _0165_ = ~(_0157_ & O);
assign _0166_ = ~(_0165_ | _0154_);
assign _0167_ = ~_0154_;
assign _0168_ = _0156_ & _0167_;
assign _0169_ = ~(_0148_ ^ _0145_);
assign _0170_ = ~(_0169_ & _0140_);
assign _0171_ = ~(_0170_ & I);
assign _0173_ = _0147_ ? _0137_ : _0138_;
assign _0174_ = ~(_0173_ & H);
assign _0175_ = _0147_ & _0136_;
assign _0176_ = _0146_ | _0054_;
assign _0177_ = ~E;
assign _0178_ = ~(D & A);
assign _0179_ = ~(_0178_ ^ B);
assign _0180_ = _0179_ ^ _0177_;
assign _0181_ = _0180_ ^ _0176_;
assign _0182_ = _0181_ ^ _0175_;
assign _0184_ = _0182_ ^ H;
assign _0185_ = _0184_ ^ _0174_;
assign _0186_ = ~(_0185_ ^ _0171_);
assign _0187_ = _0169_ & _0141_;
assign _0188_ = _0153_ & _0143_;
assign _0189_ = ~((_0187_ & J) | _0188_);
assign _0190_ = _0189_ ^ _0186_;
assign _0191_ = _0190_ ^ L;
assign _0192_ = _0191_ ^ _0168_;
assign _0193_ = ~(_0192_ ^ _0166_);
assign _0195_ = ~_0159_;
assign _0196_ = ~(_0160_ | _0172_);
assign _0197_ = _0196_ & _0195_;
assign _0198_ = _0197_ ^ _0193_;
assign _0199_ = _0198_ ^ _0164_;
assign _0200_ = _0623_ | J;
assign _0201_ = ~(_0162_ | _0200_);
assign _0202_ = _0201_ | _0196_;
assign _0203_ = _0202_ ^ _0195_;
assign _0204_ = ~(Q ^ J);
assign _0206_ = ~_0204_;
assign _0207_ = ~(_0206_ | _0162_);
assign _0208_ = ~((_0207_ & _0203_) | _0036_);
assign _0209_ = _0208_ & _0199_;
assign _0210_ = ~(_0198_ | _0164_);
assign _0211_ = _0192_ & _0166_;
assign _0212_ = _0191_ & _0168_;
assign _0213_ = _0190_ & L;
assign _0214_ = ~(_0186_ & _0188_);
assign _0215_ = ~(_0185_ | _0171_);
assign _0217_ = _0182_ | _0173_;
assign _0218_ = _0217_ & H;
assign _0219_ = _0181_ & _0175_;
assign _0220_ = ~(_0179_ & E);
assign _0221_ = ~_0194_;
assign _0222_ = E & D;
assign _0223_ = _0222_ & _0221_;
assign _0224_ = _0259_ | _0403_;
assign _0225_ = ~((_0224_ & _0220_) | _0223_);
assign _0226_ = ~_0146_;
assign _0228_ = ~((_0180_ & _0226_) | _0054_);
assign _0229_ = _0228_ ^ _0225_;
assign _0230_ = _0229_ ^ G;
assign _0231_ = _0230_ ^ _0219_;
assign _0232_ = _0231_ ^ _0218_;
assign _0233_ = _0232_ ^ _0215_;
assign _0234_ = ~((_0186_ & _0187_) | _0183_);
assign _0235_ = ~(_0234_ ^ _0233_);
assign _0236_ = _0235_ ^ _0214_;
assign _0237_ = _0236_ ^ _0213_;
assign _0239_ = _0237_ ^ M;
assign _0240_ = _0239_ ^ N;
assign _0241_ = _0240_ ^ _0212_;
assign _0242_ = _0241_ ^ O;
assign _0243_ = _0242_ ^ _0211_;
assign _0244_ = ~(_0160_ | _0159_);
assign _0245_ = ~((_0244_ & _0193_) | _0172_);
assign _0246_ = _0245_ ^ _0243_;
assign _0247_ = _0246_ ^ _0210_;
assign _0248_ = _0247_ ^ _0209_;
assign _0249_ = _0248_ & S;
assign _0250_ = _0208_ ^ _0199_;
assign _0251_ = _0250_ ^ S;
assign _0252_ = _0204_ & R;
assign _0253_ = ~_0252_;
assign _0254_ = ~(_0253_ | _0162_);
assign _0255_ = ~(_0254_ ^ _0203_);
assign _0256_ = _0204_ ^ R;
assign _0257_ = ~(_0256_ | _0124_);
assign _0258_ = ~_0257_;
assign _0261_ = _0253_ & _0200_;
assign _0262_ = _0261_ ^ _0162_;
assign _0263_ = _0262_ | _0258_;
assign _0264_ = ~(_0263_ | _0255_);
assign _0265_ = _0264_ & _0251_;
assign _0266_ = ~(_0250_ & S);
assign _0267_ = _0255_ & S;
assign _0268_ = ~_0267_;
assign _0269_ = ~(_0268_ & _0266_);
assign _0270_ = _0269_ | _0265_;
assign _0272_ = _0248_ ^ S;
assign _0273_ = _0272_ & _0270_;
assign _0274_ = _0273_ | _0249_;
assign _0275_ = _0245_ & _0243_;
assign _0276_ = _0241_ & O;
assign _0277_ = _0242_ & _0211_;
assign _0278_ = _0277_ | _0276_;
assign _0279_ = _0239_ & N;
assign _0280_ = _0240_ & _0212_;
assign _0281_ = _0280_ | _0279_;
assign _0283_ = _0237_ & M;
assign _0284_ = _0234_ & _0233_;
assign _0285_ = ~(_0232_ & _0215_);
assign _0286_ = _0231_ & _0218_;
assign _0287_ = _0229_ & G;
assign _0288_ = ~((_0230_ & _0219_) | _0287_);
assign _0289_ = _0259_ & D;
assign _0290_ = _0223_ | _0289_;
assign _0291_ = ~((_0228_ & _0225_) | _0290_);
assign _0292_ = _0291_ ^ _0288_;
assign _0294_ = _0292_ ^ _0286_;
assign _0295_ = _0294_ ^ _0285_;
assign _0296_ = ~(_0295_ ^ _0284_);
assign _0297_ = ~K;
assign _0298_ = _0152_ & _0142_;
assign _0299_ = _0298_ & _0186_;
assign _0300_ = ~((_0299_ & _0235_) | _0297_);
assign _0301_ = _0300_ ^ _0296_;
assign _0302_ = ~_0301_;
assign _0303_ = _0236_ & _0213_;
assign _0305_ = _0301_ ^ _0303_;
assign _0306_ = _0283_ ? _0302_ : _0305_;
assign _0307_ = _0306_ ^ _0281_;
assign _0308_ = _0307_ ^ _0278_;
assign _0309_ = _0308_ ^ _0275_;
assign _0310_ = _0246_ & _0210_;
assign _0311_ = _0247_ & _0209_;
assign _0312_ = _0311_ | _0310_;
assign _0313_ = _0312_ ^ _0309_;
assign _0314_ = _0313_ & _0274_;
assign _0316_ = _0309_ & _0311_;
assign _0317_ = _0308_ & _0310_;
assign _0318_ = _0308_ & _0275_;
assign _0319_ = _0301_ & _0283_;
assign _0320_ = ~_0319_;
assign _0321_ = _0301_ & _0303_;
assign _0322_ = ~_0285_;
assign _0323_ = _0292_ & _0322_;
assign _0324_ = ~(_0292_ & _0286_);
assign _0325_ = ~((_0291_ | _0288_) & _0324_);
assign _0326_ = _0325_ | _0323_;
assign _0327_ = ~_0295_;
assign _0328_ = _0300_ & _0296_;
assign _0329_ = ~((_0327_ & _0284_) | _0328_);
assign _0330_ = _0329_ ^ _0326_;
assign _0331_ = ~(_0330_ ^ _0321_);
assign _0332_ = ~(_0331_ ^ _0320_);
assign _0333_ = _0307_ & _0278_;
assign _0334_ = ~((_0306_ & _0281_) | _0333_);
assign _0335_ = _0334_ ^ _0332_;
assign _0338_ = ~(_0335_ ^ _0318_);
assign _0339_ = _0338_ ^ _0317_;
assign _0340_ = _0339_ ^ _0316_;
assign _0341_ = ~(_0338_ & _0317_);
assign _0342_ = ~_0318_;
assign _0343_ = ~(_0335_ | _0342_);
assign _0344_ = ~_0332_;
assign _0345_ = ~_0321_;
assign _0346_ = ~(_0331_ & _0319_);
assign _0347_ = ~((_0330_ | _0345_) & _0346_);
assign _0349_ = ~((_0326_ & _0328_) | _0347_);
assign _0350_ = ~((_0334_ | _0344_) & _0349_);
assign _0351_ = ~(_0350_ | _0343_);
assign _0352_ = ~(_0351_ & _0341_);
assign _0353_ = ~((_0340_ & _0314_) | _0352_);
assign _0354_ = _0263_ & S;
assign _0355_ = _0354_ ^ _0255_;
assign _0356_ = ~(_0262_ ^ _0257_);
assign _0357_ = _0256_ ^ _0124_;
assign _0358_ = _0357_ | _0356_;
assign _0360_ = _0358_ | _0355_;
assign _0361_ = _0360_ & T;
assign _0362_ = _0268_ & _0263_;
assign _0363_ = ~(_0362_ ^ _0251_);
assign _0364_ = ~(_0363_ & _0361_);
assign _0365_ = ~(_0272_ ^ _0270_);
assign _0366_ = ~((_0365_ | _0161_) & _0364_);
assign _0367_ = _0313_ ^ _0274_;
assign _0368_ = _0367_ & _0366_;
assign _0369_ = _0340_ ^ _0314_;
assign _0371_ = ~((_0369_ & _0368_) | (_0339_ & _0316_));
assign _0372_ = _0371_ & _0353_;
assign _0373_ = ~(_0367_ ^ _0366_);
assign _0374_ = _0363_ ^ _0361_;
assign _0375_ = ~_0374_;
assign _0376_ = _0364_ & T;
assign _0377_ = _0376_ ^ _0365_;
assign _0378_ = ~(_0377_ & _0375_);
assign _0379_ = ~(_0378_ & U);
assign _0380_ = ~(_0379_ | _0373_);
assign _0382_ = _0369_ ^ _0368_;
assign _0383_ = ~(_0357_ | _0161_);
assign _0384_ = ~_0383_;
assign _0385_ = _0357_ & _0161_;
assign _0386_ = ~((_0384_ & _0032_) | _0385_);
assign _0387_ = _0386_ ^ _0356_;
assign _0388_ = _0387_ & W;
assign _0389_ = ~(_0384_ | _0356_);
assign _0390_ = _0389_ ^ _0355_;
assign _0391_ = ~_0356_;
assign _0393_ = ~(_0385_ | _0383_);
assign _0394_ = ~((_0393_ & _0391_) | _0032_);
assign _0395_ = _0394_ ^ _0390_;
assign _0396_ = ~(_0394_ & _0390_);
assign _0397_ = ~U;
assign _0398_ = _0374_ ^ _0397_;
assign _0399_ = _0398_ ^ _0396_;
assign _0400_ = ~((_0395_ & _0388_) | _0399_);
assign _0401_ = ~(_0400_ | _0150_);
assign _0402_ = ~_0401_;
assign _0404_ = _0379_ & _0373_;
assign _0405_ = _0398_ | _0396_;
assign _0406_ = ~(_0374_ | _0397_);
assign _0407_ = _0406_ ^ _0377_;
assign _0408_ = _0407_ & _0405_;
assign _0409_ = ~((_0408_ | _0404_) & _0402_);
assign _0410_ = ~((_0409_ & _0382_) | _0380_);
assign _0411_ = _0399_ | W;
assign _0412_ = ~((_0411_ | _0380_) & _0382_);
assign _0413_ = ~((_0412_ | _0404_) & (_0407_ | _0405_));
assign _0415_ = ~((_0401_ | _0382_) & _0413_);
assign _0416_ = ~((_0415_ | _0410_) & _0372_);
assign _0417_ = ~(_0128_ | _0088_);
assign _0418_ = ~(_0126_ & _0123_);
assign _0419_ = _0117_ & _0115_;
assign _0420_ = _0114_ & _0097_;
assign _0421_ = _0105_ | _0103_;
assign _0422_ = ~(_0106_ & _0102_);
assign _0423_ = ~(_0422_ & _0421_);
assign _0424_ = ~((_0107_ & _0101_) | _0423_);
assign _0426_ = ~(_0108_ & _0099_);
assign _0427_ = ~(_0109_ & _0110_);
assign _0428_ = _0427_ & _0426_;
assign _0429_ = ~(_0428_ ^ _0424_);
assign _0430_ = ~((_0113_ & _0098_) | (_0109_ & _0111_));
assign _0431_ = _0430_ ^ _0429_;
assign _0432_ = _0431_ ^ _0420_;
assign _0433_ = ~(_0432_ ^ _0419_);
assign _0434_ = _0118_ & _0096_;
assign _0435_ = _0119_ & _0093_;
assign _0437_ = _0435_ | _0434_;
assign _0438_ = _0437_ ^ _0433_;
assign _0439_ = ~(_0121_ & _0120_);
assign _0440_ = ~(_0122_ & _0090_);
assign _0441_ = _0440_ & _0439_;
assign _0442_ = ~(_0441_ ^ _0438_);
assign _0443_ = ~(_0442_ | _0418_);
assign _0444_ = E ^ C;
assign _0445_ = _0444_ ^ H;
assign _0446_ = _0445_ ^ K;
assign _0448_ = _0446_ ^ L;
assign _0449_ = _0448_ ^ _0623_;
assign _0450_ = ~(_0449_ | _0124_);
assign _0451_ = ~(_0448_ | _0623_);
assign _0452_ = _0446_ & L;
assign _0453_ = E ^ D;
assign _0454_ = C ? _0403_ : _0453_;
assign _0455_ = _0454_ ^ G;
assign _0456_ = _0444_ & H;
assign _0457_ = _0445_ & K;
assign _0459_ = ~(_0457_ | _0456_);
assign _0460_ = ~(_0459_ ^ _0455_);
assign _0461_ = _0460_ ^ _0452_;
assign _0462_ = _0461_ ^ _0381_;
assign _0463_ = _0462_ ^ O;
assign _0464_ = _0463_ ^ _0451_;
assign _0465_ = _0464_ ^ _0036_;
assign _0466_ = _0465_ & _0450_;
assign _0467_ = _0464_ | _0036_;
assign _0468_ = _0463_ & _0451_;
assign _0470_ = _0455_ & _0456_;
assign _0471_ = ~G;
assign _0472_ = ~(_0454_ | _0471_);
assign _0473_ = _0056_ ^ A;
assign _0474_ = ~((_0403_ & _0414_) | _0177_);
assign _0475_ = _0474_ ^ _0473_;
assign _0476_ = _0475_ ^ F;
assign _0477_ = _0476_ ^ _0472_;
assign _0478_ = _0477_ ^ _0470_;
assign _0479_ = _0478_ ^ _0761_;
assign _0481_ = ~(_0455_ & _0457_);
assign _0482_ = _0481_ & K;
assign _0483_ = _0482_ ^ _0479_;
assign _0484_ = ~(_0460_ & _0452_);
assign _0485_ = _0484_ & L;
assign _0486_ = _0485_ ^ _0483_;
assign _0487_ = ~(_0461_ | _0381_);
assign _0488_ = ~((_0462_ & O) | _0487_);
assign _0489_ = ~(_0488_ ^ _0486_);
assign _0490_ = _0489_ ^ P;
assign _0492_ = _0490_ ^ _0468_;
assign _0493_ = _0492_ ^ _0467_;
assign _0494_ = ~(_0493_ & _0466_);
assign _0495_ = ~_0463_;
assign _0496_ = ~(_0495_ | _0448_);
assign _0497_ = ~((_0490_ & _0496_) | _0623_);
assign _0498_ = ~(_0489_ & P);
assign _0499_ = ~((_0486_ & _0462_) | _0315_);
assign _0500_ = ~(_0485_ & _0483_);
assign _0501_ = _0479_ | _0297_;
assign _0503_ = _0501_ & _0481_;
assign _0504_ = ~((_0476_ | _0454_) & G);
assign _0505_ = _0475_ | _0054_;
assign _0506_ = _0474_ & _0473_;
assign _0507_ = _0178_ & C;
assign _0508_ = _0507_ ^ _0194_;
assign _0509_ = _0508_ ^ _0177_;
assign _0510_ = _0509_ ^ _0506_;
assign _0511_ = _0510_ ^ _0505_;
assign _0512_ = _0511_ ^ _0504_;
assign _0514_ = _0477_ & _0470_;
assign _0515_ = ~((_0478_ & I) | _0514_);
assign _0516_ = _0515_ ^ _0512_;
assign _0517_ = ~(_0516_ ^ _0503_);
assign _0518_ = _0517_ ^ _0500_;
assign _0519_ = _0518_ ^ M;
assign _0520_ = _0486_ & _0487_;
assign _0521_ = _0520_ ^ _0519_;
assign _0522_ = ~(_0521_ ^ _0499_);
assign _0523_ = _0522_ ^ _0498_;
assign _0525_ = _0523_ ^ _0497_;
assign _0526_ = _0525_ ^ _0036_;
assign _0527_ = ~(_0526_ | _0494_);
assign _0528_ = _0492_ | _0467_;
assign _0529_ = ~(_0525_ & R);
assign _0530_ = ~(_0529_ & _0528_);
assign _0531_ = _0518_ & M;
assign _0532_ = ~L;
assign _0533_ = _0517_ & _0483_;
assign _0534_ = ~((_0533_ | _0532_) & _0484_);
assign _0536_ = _0516_ | _0503_;
assign _0537_ = _0512_ & _0514_;
assign _0538_ = ~(_0511_ | _0504_);
assign _0539_ = ~(_0510_ | _0505_);
assign _0540_ = ~(_0509_ & _0506_);
assign _0541_ = ~((_0508_ | _0177_) & _0540_);
assign _0542_ = ~A;
assign _0543_ = B & _0542_;
assign _0544_ = B | _0542_;
assign _0545_ = ~((_0544_ & _0414_) | _0543_);
assign _0547_ = ~(_0545_ & D);
assign _0548_ = _0545_ | D;
assign _0549_ = ~((_0548_ & _0547_) | (_0056_ & _0259_));
assign _0550_ = _0549_ ^ _0177_;
assign _0551_ = _0550_ ^ _0541_;
assign _0552_ = _0551_ ^ _0539_;
assign _0553_ = _0552_ ^ _0538_;
assign _0554_ = ~(_0553_ ^ _0537_);
assign _0555_ = ~(_0512_ & _0478_);
assign _0556_ = _0555_ & I;
assign _0558_ = _0556_ ^ _0554_;
assign _0559_ = _0558_ ^ _0536_;
assign _0560_ = _0559_ ^ _0534_;
assign _0561_ = _0560_ ^ _0531_;
assign _0562_ = ~_0486_;
assign _0563_ = _0562_ | _0461_;
assign _0564_ = _0563_ | _0519_;
assign _0565_ = _0564_ & N;
assign _0566_ = ~(_0565_ ^ _0561_);
assign _0567_ = ~(_0521_ & _0499_);
assign _0569_ = ~(_0567_ & O);
assign _0570_ = _0569_ ^ _0566_;
assign _0571_ = ~((_0522_ & _0489_) | _0172_);
assign _0572_ = ~(_0571_ ^ _0570_);
assign _0573_ = ~(_0523_ & _0497_);
assign _0574_ = ~(_0573_ & Q);
assign _0575_ = _0574_ ^ _0572_;
assign _0576_ = _0575_ ^ R;
assign _0577_ = _0576_ ^ _0530_;
assign _0578_ = ~(_0577_ ^ _0527_);
assign _0580_ = _0465_ ^ _0450_;
assign _0581_ = _0493_ ^ _0466_;
assign _0582_ = _0581_ | _0580_;
assign _0583_ = _0582_ & T;
assign _0584_ = _0494_ & _0528_;
assign _0585_ = _0584_ ^ _0526_;
assign _0586_ = ~(_0585_ & _0583_);
assign _0587_ = ~((_0578_ | _0161_) & _0586_);
assign _0588_ = _0577_ & _0527_;
assign _0589_ = _0575_ & R;
assign _0591_ = ~((_0576_ & _0530_) | _0589_);
assign _0592_ = ~((_0572_ | _0623_) & _0573_);
assign _0593_ = _0571_ & _0570_;
assign _0594_ = ~((_0566_ | _0315_) & _0567_);
assign _0595_ = _0565_ & _0561_;
assign _0596_ = _0560_ & _0531_;
assign _0597_ = _0559_ & _0534_;
assign _0598_ = ~(_0558_ | _0536_);
assign _0599_ = ~((_0555_ & _0554_) | _0761_);
assign _0600_ = _0474_ | _0473_;
assign _0601_ = _0509_ | _0600_;
assign _0602_ = _0540_ & F;
assign _0603_ = ~((_0551_ & F) | (_0602_ & _0601_));
assign _0604_ = ~_0506_;
assign _0605_ = _0550_ & _0541_;
assign _0606_ = _0056_ & A;
assign _0607_ = ~((_0104_ & C) | _0259_);
assign _0608_ = _0607_ & _0547_;
assign _0609_ = ~((_0608_ | _0606_) & (_0549_ | _0177_));
assign _0610_ = ~((_0609_ | _0605_) & _0604_);
assign _0613_ = _0610_ ^ _0603_;
assign _0614_ = _0552_ & _0538_;
assign _0615_ = ~((_0553_ & _0537_) | _0614_);
assign _0616_ = ~(_0615_ ^ _0613_);
assign _0617_ = _0616_ ^ _0599_;
assign _0618_ = _0617_ ^ _0598_;
assign _0619_ = _0618_ ^ _0597_;
assign _0620_ = _0619_ ^ _0596_;
assign _0621_ = _0620_ ^ _0595_;
assign _0622_ = _0621_ ^ _0594_;
assign _0624_ = _0622_ ^ _0593_;
assign _0625_ = ~(_0624_ ^ _0592_);
assign _0626_ = _0625_ ^ _0591_;
assign _0627_ = _0626_ ^ _0588_;
assign _0628_ = _0627_ & _0587_;
assign _0629_ = _0626_ & _0588_;
assign _0630_ = ~(_0625_ | _0591_);
assign _0631_ = _0624_ & _0592_;
assign _0632_ = _0616_ & _0599_;
assign _0633_ = ~(_0613_ & _0614_);
assign _0635_ = ~(_0610_ | _0603_);
assign _0636_ = ~(_0506_ | _0606_);
assign _0637_ = ~(_0636_ ^ _0635_);
assign _0638_ = ~((_0553_ & _0537_) | _0637_);
assign _0639_ = ~(_0638_ & _0633_);
assign _0640_ = ~(_0639_ ^ _0632_);
assign _0641_ = _0617_ & _0598_;
assign _0642_ = ~((_0618_ & _0597_) | _0641_);
assign _0643_ = ~(_0642_ ^ _0640_);
assign _0644_ = _0619_ & _0596_;
assign _0646_ = ~((_0620_ & _0595_) | _0644_);
assign _0647_ = ~(_0646_ ^ _0643_);
assign _0648_ = _0621_ & _0594_;
assign _0649_ = ~((_0622_ & _0593_) | _0648_);
assign _0650_ = _0649_ ^ _0647_;
assign _0651_ = _0650_ ^ _0631_;
assign _0652_ = _0651_ ^ _0630_;
assign _0653_ = _0652_ ^ _0629_;
assign _0654_ = ~(_0653_ | _0628_);
assign _0655_ = ~_0433_;
assign _0657_ = ~((_0435_ | _0434_) & _0655_);
assign _0658_ = _0650_ & _0631_;
assign _0659_ = _0432_ & _0419_;
assign _0660_ = _0431_ & _0420_;
assign _0661_ = ~(_0430_ | _0429_);
assign _0662_ = _0424_ | _0427_;
assign _0663_ = ~((_0639_ & _0632_) | (_0635_ & _0606_));
assign _0664_ = _0663_ & _0662_;
assign _0665_ = ~((_0642_ | _0640_) & _0664_);
assign _0666_ = _0665_ | _0661_;
assign _0668_ = ~(_0666_ | _0660_);
assign _0669_ = ~((_0646_ | _0643_) & _0668_);
assign _0670_ = ~(_0669_ | _0659_);
assign _0671_ = ~((_0649_ | _0647_) & _0670_);
assign _0672_ = _0671_ | _0658_;
assign _0673_ = ~((_0651_ & _0630_) | _0672_);
assign _0674_ = ~(_0673_ & _0657_);
assign _0675_ = ~((_0652_ & _0629_) | _0674_);
assign _0676_ = _0675_ & _0654_;
assign _0677_ = ~((_0441_ | _0438_) & _0676_);
assign _0679_ = ~(_0677_ | _0443_);
assign _0680_ = ~(_0586_ & T);
assign _0681_ = _0680_ ^ _0578_;
assign _0682_ = _0681_ & U;
assign _0683_ = _0585_ ^ _0583_;
assign _0684_ = _0580_ ^ _0161_;
assign _0685_ = ~(_0684_ | _0397_);
assign _0686_ = ~(_0580_ | _0161_);
assign _0687_ = _0686_ ^ _0581_;
assign _0688_ = _0687_ & _0685_;
assign _0690_ = _0683_ ? U : _0688_;
assign _0691_ = _0681_ ^ U;
assign _0692_ = _0691_ & _0690_;
assign _0693_ = _0692_ | _0682_;
assign _0694_ = _0627_ ^ _0587_;
assign _0695_ = _0683_ ^ U;
assign _0696_ = _0687_ ^ _0685_;
assign _0697_ = ~(_0696_ & V);
assign _0698_ = ~(_0697_ | _0695_);
assign _0699_ = _0688_ ? _0683_ : _0695_;
assign _0701_ = _0684_ ^ _0397_;
assign _0702_ = _0449_ ^ _0124_;
assign _0703_ = ~(_0702_ | _0701_);
assign _0704_ = ~(_0703_ | _0696_);
assign _0705_ = _0704_ | _0699_;
assign _0706_ = ~((_0705_ & V) | _0698_);
assign _0707_ = ~(_0691_ ^ _0690_);
assign _0708_ = _0707_ | _0706_;
assign _0709_ = ~((_0691_ & _0690_) | _0682_);
assign _0710_ = _0694_ ^ _0709_;
assign _0712_ = ~(_0710_ | _0708_);
assign _0713_ = ~((_0694_ & _0693_) | _0712_);
assign _0714_ = _0713_ & _0679_;
assign _0715_ = _0127_ & _0089_;
assign _0716_ = _0442_ ^ _0418_;
assign _0717_ = ~(_0716_ & _0715_);
assign _0718_ = _0707_ & _0706_;
assign _0719_ = _0702_ ^ V;
assign _0720_ = ~((_0719_ | _0701_) & (_0699_ | V));
assign _0721_ = _0720_ | _0698_;
assign _0723_ = _0703_ & V;
assign _0724_ = ~_0723_;
assign _0725_ = _0724_ | _0699_;
assign _0726_ = _0696_ ? _0723_ : _0725_;
assign _0727_ = _0726_ | _0721_;
assign _0728_ = ~((_0727_ | _0718_) & _0708_);
assign _0729_ = ~(_0109_ & _0111_);
assign _0730_ = ~(_0113_ & _0098_);
assign _0731_ = ~((_0730_ & _0729_) | _0429_);
assign _0732_ = _0731_ | _0660_;
assign _0734_ = ~(_0732_ | _0659_);
assign _0735_ = _0734_ & _0657_;
assign _0736_ = _0735_ & _0662_;
assign _0737_ = ~((_0438_ | _0439_) & _0736_);
assign _0738_ = ~(_0707_ | _0706_);
assign _0739_ = _0653_ ^ _0628_;
assign _0740_ = ~((_0739_ & _0738_) | _0710_);
assign _0741_ = ~((_0740_ & _0728_) | (_0737_ & _0443_));
assign _0742_ = _0741_ & _0717_;
assign _0743_ = ~(_0742_ & _0714_);
assign _0745_ = _0716_ ^ _0715_;
assign _0746_ = ~((_0745_ & _0417_) | _0743_);
assign _0747_ = ~(_0417_ | _0129_);
assign _0748_ = _0745_ ^ _0417_;
assign _0749_ = ~((_0747_ & _0085_) | _0748_);
assign _0750_ = _0749_ & _0746_;
assign _0751_ = _0750_ & _0416_;
assign valid = _0751_ & _0135_;
endmodule |
module sky130_fd_sc_hs__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule |
module sim;
// VCD Dump
//initial begin
// $dumpfile("run.vcd");
// $dumpvars;
//end
// Generate Clock
reg clk = 1'b0;
always #5 clk = ~clk;
// MulDiv Unit
reg [1:0] verbose;
reg [2:0] src_msg_fn;
reg [31:0] nmults;
reg [31:0] src_msg_a;
reg [31:0] src_msg_b;
reg src_val = 1'b0;
wire src_rdy;
//wire [63:0] sink_msg;
wire [31:0] sink_msg;
wire sink_val;
wire sink_rdy = 1'b1; // Always ready to accept result
wire muldivreq_go = src_val && src_rdy;
wire muldivresp_go = sink_val && sink_rdy;
reg reset = 1'b1;
imuldiv_IntMulVariable imul
(
.clk (clk),
.reset (reset),
.mulreq_msg_a (src_msg_a),
.mulreq_msg_b (src_msg_b),
.mulreq_val (src_val),
.mulreq_rdy (src_rdy),
.mulresp_msg_result (sink_msg),
.mulresp_val (sink_val),
.mulresp_rdy (sink_rdy)
);
//---------------------------------------------------------------------------
// Test Vectors
//---------------------------------------------------------------------------
integer idx;
reg [31:0] in0[999:0];
reg [31:0] in1[999:0];
reg [31:0] out[999:0];
initial begin
idx = 0;
in0[ 0]=32'h67f34f6d; in1[ 0]=32'h24c617a0; out[ 0]=32'h96826f20;
in0[ 1]=32'hb5d9ed18; in1[ 1]=32'h7eb389c5; out[ 1]=32'h285d4b78;
in0[ 2]=32'h5786f1db; in1[ 2]=32'h435acae1; out[ 2]=32'hc06f5f7b;
in0[ 3]=32'h70047e7d; in1[ 3]=32'hff3e1308; out[ 3]=32'hfacd3ae8;
in0[ 4]=32'h5530cbf5; in1[ 4]=32'hc4984d96; out[ 4]=32'h4568328e;
in0[ 5]=32'h34147951; in1[ 5]=32'hf65b9385; out[ 5]=32'hc6178a15;
in0[ 6]=32'h75174485; in1[ 6]=32'h2920e6bc; out[ 6]=32'hc245cfac;
in0[ 7]=32'h26171439; in1[ 7]=32'h8c871861; out[ 7]=32'h6eb30199;
in0[ 8]=32'h117cb918; in1[ 8]=32'h2c809d62; out[ 8]=32'hdb429330;
in0[ 9]=32'h4164f86c; in1[ 9]=32'h7995f109; out[ 9]=32'hfd4667cc;
in0[ 10]=32'hf2c40f62; in1[ 10]=32'h897e310f; out[ 10]=32'hc4aaa8be;
in0[ 11]=32'h610082d8; in1[ 11]=32'hb6fdc399; out[ 11]=32'h3c70bb18;
in0[ 12]=32'hfdb3bc12; in1[ 12]=32'hbb9dd55e; out[ 12]=32'h3084089c;
in0[ 13]=32'h1da3dd7e; in1[ 13]=32'h89ec653a; out[ 13]=32'hfbaae48c;
in0[ 14]=32'hcc0d8e74; in1[ 14]=32'h9b30bcb3; out[ 14]=32'h93d7cb1c;
in0[ 15]=32'ha37d20a5; in1[ 15]=32'hf5de555a; out[ 15]=32'h3dea4302;
in0[ 16]=32'h892ea376; in1[ 16]=32'had1c78fd; out[ 16]=32'h0e9edb9e;
in0[ 17]=32'he1d01c91; in1[ 17]=32'h3793ff36; out[ 17]=32'h7c9d7596;
in0[ 18]=32'he5867c11; in1[ 18]=32'ha0e0ee12; out[ 18]=32'h59ac8732;
in0[ 19]=32'hd119415a; in1[ 19]=32'h906fa0b0; out[ 19]=32'h803b2de0;
in0[ 20]=32'ha52d20c0; in1[ 20]=32'hb70ab4a1; out[ 20]=32'h23e898c0;
in0[ 21]=32'h988bebd1; in1[ 21]=32'h7365b610; out[ 21]=32'heeda5310;
in0[ 22]=32'hf5412b23; in1[ 22]=32'hdbf52a72; out[ 22]=32'h2197f396;
in0[ 23]=32'he16f4ef6; in1[ 23]=32'h761bd7f5; out[ 23]=32'hf2c92b6e;
in0[ 24]=32'h7b85eeb6; in1[ 24]=32'hac28c326; out[ 24]=32'hef261104;
in0[ 25]=32'h3be0f2e1; in1[ 25]=32'hfcf48677; out[ 25]=32'h8f26ac97;
in0[ 26]=32'h85ec31ac; in1[ 26]=32'h5a4dd21e; out[ 26]=32'hdb28ea28;
in0[ 27]=32'h47d041ec; in1[ 27]=32'h74df3ccc; out[ 27]=32'h65fbd810;
in0[ 28]=32'h4048c934; in1[ 28]=32'h49827b21; out[ 28]=32'h4275ebb4;
in0[ 29]=32'h49469987; in1[ 29]=32'hd87f15d7; out[ 29]=32'h66dc0361;
in0[ 30]=32'hc981f522; in1[ 30]=32'h8ac94675; out[ 30]=32'h6d1e548a;
in0[ 31]=32'h093a1e26; in1[ 31]=32'hd677487d; out[ 31]=32'ha185688e;
in0[ 32]=32'haf27aab1; in1[ 32]=32'h931b1789; out[ 32]=32'hf03b3fb9;
in0[ 33]=32'he4981875; in1[ 33]=32'h004ae4cf; out[ 33]=32'h5e95fa9b;
in0[ 34]=32'hbbea7acf; in1[ 34]=32'hb32d6451; out[ 34]=32'h608cb77f;
in0[ 35]=32'hc3a0da02; in1[ 35]=32'hf99ff344; out[ 35]=32'hfee7ce88;
in0[ 36]=32'h4c9d8ecb; in1[ 36]=32'hfa56f325; out[ 36]=32'hd7825457;
in0[ 37]=32'hec8d9cc4; in1[ 37]=32'hb1c15a91; out[ 37]=32'h7916b304;
in0[ 38]=32'he9400bcb; in1[ 38]=32'hcefa10a8; out[ 38]=32'hf1026d38;
in0[ 39]=32'h8482ecc4; in1[ 39]=32'h0d4ebc72; out[ 39]=32'h3fe55f48;
in0[ 40]=32'h0a15e96b; in1[ 40]=32'h203af540; out[ 40]=32'hc01bc1c0;
in0[ 41]=32'ha4653582; in1[ 41]=32'hdae36b48; out[ 41]=32'hb01a6290;
in0[ 42]=32'h08b9ea64; in1[ 42]=32'h5b8f48cc; out[ 42]=32'hb7eee7b0;
in0[ 43]=32'h419c1ce8; in1[ 43]=32'ha69a4650; out[ 43]=32'h04407880;
in0[ 44]=32'h575e10f4; in1[ 44]=32'habc8117a; out[ 44]=32'h1c944848;
in0[ 45]=32'h75c41c0d; in1[ 45]=32'h596944c7; out[ 45]=32'ha93a421b;
in0[ 46]=32'hec0ffb99; in1[ 46]=32'h1db25718; out[ 46]=32'hd5629558;
in0[ 47]=32'h6064f66a; in1[ 47]=32'hca550c64; out[ 47]=32'hd82f3968;
in0[ 48]=32'h10754117; in1[ 48]=32'hcaec691b; out[ 48]=32'hfb444c6d;
in0[ 49]=32'h74cadc3d; in1[ 49]=32'h8db4a155; out[ 49]=32'hcfc17d41;
in0[ 50]=32'h371d921d; in1[ 50]=32'h3d616d79; out[ 50]=32'hea2d68b5;
in0[ 51]=32'h6e841170; in1[ 51]=32'he57ead4b; out[ 51]=32'h6599cbd0;
in0[ 52]=32'h6464ffd4; in1[ 52]=32'h692633d0; out[ 52]=32'h9e7f1840;
in0[ 53]=32'h0f2356e6; in1[ 53]=32'h592afec1; out[ 53]=32'hb198b766;
in0[ 54]=32'h9c7f213a; in1[ 54]=32'hd10fabf3; out[ 54]=32'hc444480e;
in0[ 55]=32'hb45d0921; in1[ 55]=32'h67f680ec; out[ 55]=32'hd70aea6c;
in0[ 56]=32'h6331711a; in1[ 56]=32'hd89f5d10; out[ 56]=32'h585383a0;
in0[ 57]=32'h2dae0b84; in1[ 57]=32'h436b815b; out[ 57]=32'h4cd79bec;
in0[ 58]=32'hcefbd30f; in1[ 58]=32'hf8c9e39f; out[ 58]=32'h19556351;
in0[ 59]=32'h432d54cc; in1[ 59]=32'hfb5e1791; out[ 59]=32'h46335b8c;
in0[ 60]=32'h7249d9b7; in1[ 60]=32'he6ae8883; out[ 60]=32'h1bd5a0a5;
in0[ 61]=32'hd1a06415; in1[ 61]=32'hc530a942; out[ 61]=32'hda5baa6a;
in0[ 62]=32'h1f6e422d; in1[ 62]=32'h08fc6c4e; out[ 62]=32'ha3cf25b6;
in0[ 63]=32'h91896038; in1[ 63]=32'hb107b9a4; out[ 63]=32'hdc121be0;
in0[ 64]=32'h3f79e4fd; in1[ 64]=32'h1534b813; out[ 64]=32'h9705d6c7;
in0[ 65]=32'hee3ac762; in1[ 65]=32'h0385a7d9; out[ 65]=32'h03cdf012;
in0[ 66]=32'h0baffde4; in1[ 66]=32'h55d6f147; out[ 66]=32'hdc6b0e3c;
in0[ 67]=32'h6ad2a566; in1[ 67]=32'hc9b12c54; out[ 67]=32'hb311cd78;
in0[ 68]=32'ha518fa06; in1[ 68]=32'hea8216c2; out[ 68]=32'hb575fc8c;
in0[ 69]=32'h5e87c367; in1[ 69]=32'h79fdd610; out[ 69]=32'h319f5070;
in0[ 70]=32'h7e3a298b; in1[ 70]=32'h66d0b415; out[ 70]=32'h62eb2467;
in0[ 71]=32'h50d7d8ed; in1[ 71]=32'h84485084; out[ 71]=32'h59bdea34;
in0[ 72]=32'h453530fc; in1[ 72]=32'h24c557ea; out[ 72]=32'h78306a58;
in0[ 73]=32'h829e2190; in1[ 73]=32'hff9f7faf; out[ 73]=32'h052f6170;
in0[ 74]=32'h38a8b121; in1[ 74]=32'hc5506a3a; out[ 74]=32'h6edfcb7a;
in0[ 75]=32'hed137b52; in1[ 75]=32'h2f30695a; out[ 75]=32'h83cdfcd4;
in0[ 76]=32'ha524c9bd; in1[ 76]=32'h4fd2fae2; out[ 76]=32'h8786aada;
in0[ 77]=32'he3ef9ace; in1[ 77]=32'h6e2ee860; out[ 77]=32'hf328bd40;
in0[ 78]=32'hbe1a989b; in1[ 78]=32'h908efb5e; out[ 78]=32'hb75e01ea;
in0[ 79]=32'h83f1d8dd; in1[ 79]=32'h01cfe0f4; out[ 79]=32'h97f712a4;
in0[ 80]=32'hbb9a2450; in1[ 80]=32'h482efb5b; out[ 80]=32'hd7c55870;
in0[ 81]=32'he6c0a9d6; in1[ 81]=32'h8b0481f7; out[ 81]=32'h92d0b37a;
in0[ 82]=32'h3562690a; in1[ 82]=32'h032471f1; out[ 82]=32'h956a4c6a;
in0[ 83]=32'hd0ff2e60; in1[ 83]=32'heff8f177; out[ 83]=32'hee46eea0;
in0[ 84]=32'hb4b16f6e; in1[ 84]=32'h12442bcf; out[ 84]=32'h3e6893f2;
in0[ 85]=32'h1c6ffba1; in1[ 85]=32'h713c6b02; out[ 85]=32'h11c84242;
in0[ 86]=32'h657c6487; in1[ 86]=32'h7fc1e97e; out[ 86]=32'hed7f5972;
in0[ 87]=32'h611488f2; in1[ 87]=32'he8948161; out[ 87]=32'h9db1d5b2;
in0[ 88]=32'h0b2dc798; in1[ 88]=32'h2efbd35e; out[ 88]=32'hd85991d0;
in0[ 89]=32'h976b00b2; in1[ 89]=32'hffa8326b; out[ 89]=32'hf2ac0e66;
in0[ 90]=32'h88a725b6; in1[ 90]=32'h1912dbf3; out[ 90]=32'h20b77dc2;
in0[ 91]=32'hcf4bb68f; in1[ 91]=32'h085b63b0; out[ 91]=32'h287bcf50;
in0[ 92]=32'h1965d1cb; in1[ 92]=32'h819cb1cb; out[ 92]=32'hac7eb6f9;
in0[ 93]=32'hc0ff188b; in1[ 93]=32'h0e04a247; out[ 93]=32'hf073c48d;
in0[ 94]=32'h7ea2e156; in1[ 94]=32'hb133fdca; out[ 94]=32'h3f59cbdc;
in0[ 95]=32'h7c5433dd; in1[ 95]=32'h9880bdc7; out[ 95]=32'hf63e79cb;
in0[ 96]=32'h4c04c579; in1[ 96]=32'h8c835b5e; out[ 96]=32'hd4dd856e;
in0[ 97]=32'hbc7af287; in1[ 97]=32'hf25842a4; out[ 97]=32'h6db22c7c;
in0[ 98]=32'he5bb2796; in1[ 98]=32'hd67b3899; out[ 98]=32'ha69578a6;
in0[ 99]=32'h3b3f1b45; in1[ 99]=32'hf0591df6; out[ 99]=32'h3fb8054e;
in0[100]=32'hef6965de; in1[100]=32'hcc392eac; out[100]=32'h618c5528;
in0[101]=32'h75db7464; in1[101]=32'hde732e12; out[101]=32'hb9442708;
in0[102]=32'h3ceb3472; in1[102]=32'h7da99e66; out[102]=32'hb957416c;
in0[103]=32'h8b95d7fb; in1[103]=32'h4d749456; out[103]=32'he1efaa52;
in0[104]=32'hb884bbf4; in1[104]=32'h43967e77; out[104]=32'h172d766c;
in0[105]=32'hee9c1a25; in1[105]=32'h434b6b99; out[105]=32'h3210171d;
in0[106]=32'h4dac2709; in1[106]=32'h17ce8672; out[106]=32'heb561802;
in0[107]=32'h3605bc3e; in1[107]=32'h701fb675; out[107]=32'haff51c56;
in0[108]=32'h93f73d6f; in1[108]=32'h2119bc20; out[108]=32'h5edc31e0;
in0[109]=32'he418c577; in1[109]=32'h81e9baec; out[109]=32'hf69d7fb4;
in0[110]=32'h490bf0e3; in1[110]=32'h768b1f88; out[110]=32'hadc47598;
in0[111]=32'h0b0f0343; in1[111]=32'h10a2d939; out[111]=32'h708184eb;
in0[112]=32'hd5bafb2f; in1[112]=32'h777d0f74; out[112]=32'h4c64924c;
in0[113]=32'h64825c2a; in1[113]=32'hec544896; out[113]=32'h8415d09c;
in0[114]=32'h6e3b29ea; in1[114]=32'h4fb87322; out[114]=32'h8ddfaf14;
in0[115]=32'h450c98d8; in1[115]=32'h07b2b48b; out[115]=32'h877edd48;
in0[116]=32'hbe4d28de; in1[116]=32'hfbe99445; out[116]=32'hc27a5bd6;
in0[117]=32'ha38665e6; in1[117]=32'hd2b26222; out[117]=32'hb0c7948c;
in0[118]=32'hfff19cc1; in1[118]=32'h1f642cfa; out[118]=32'h1348407a;
in0[119]=32'h1ea06a92; in1[119]=32'h8cf6caa4; out[119]=32'h73277988;
in0[120]=32'hab045171; in1[120]=32'hcd50ae58; out[120]=32'ha926ccd8;
in0[121]=32'hb24505ff; in1[121]=32'hc5a5bec7; out[121]=32'he675eb39;
in0[122]=32'h48b02005; in1[122]=32'hd4f6ac00; out[122]=32'h3e515c00;
in0[123]=32'hf8480a15; in1[123]=32'h7c525722; out[123]=32'hdbb879ca;
in0[124]=32'h510984e2; in1[124]=32'hba1d8d46; out[124]=32'ha864cfcc;
in0[125]=32'h824683ac; in1[125]=32'hde34f160; out[125]=32'h23564c80;
in0[126]=32'h6d95ea79; in1[126]=32'h459b1b4d; out[126]=32'h5a154965;
in0[127]=32'h4d6c5b12; in1[127]=32'h9f2d863a; out[127]=32'h72620e14;
in0[128]=32'h2ef0f552; in1[128]=32'h9113c4a5; out[128]=32'h6436e5da;
in0[129]=32'hc86138ac; in1[129]=32'he1fd5a8b; out[129]=32'h28b23d64;
in0[130]=32'h705b3dfc; in1[130]=32'hd96c9081; out[130]=32'hb327fbfc;
in0[131]=32'he3a1b6bb; in1[131]=32'h2e3872a1; out[131]=32'hbefb319b;
in0[132]=32'h11e5bd1b; in1[132]=32'hea07e059; out[132]=32'h18135e63;
in0[133]=32'h2104ead6; in1[133]=32'h74824168; out[133]=32'he24bbcf0;
in0[134]=32'h2a405c7f; in1[134]=32'h5fdbde20; out[134]=32'h59e6b1e0;
in0[135]=32'hf70431db; in1[135]=32'h1a70d446; out[135]=32'h123efde2;
in0[136]=32'h620bae7f; in1[136]=32'h845a8375; out[136]=32'h9e47bd0b;
in0[137]=32'hb3068fc5; in1[137]=32'h6e31c02c; out[137]=32'hdba975dc;
in0[138]=32'h7a50dbb8; in1[138]=32'he0670e3a; out[138]=32'h895dd7b0;
in0[139]=32'h8b58ae0c; in1[139]=32'h15e1c4e2; out[139]=32'hde16d698;
in0[140]=32'hc9105594; in1[140]=32'hf3ab2e40; out[140]=32'hd951fd00;
in0[141]=32'hb87b5f8e; in1[141]=32'hb0b053ce; out[141]=32'hc4e1ee44;
in0[142]=32'h36353408; in1[142]=32'hb9d1350a; out[142]=32'h6461b050;
in0[143]=32'h19f612af; in1[143]=32'hc8d4c354; out[143]=32'h25e56e6c;
in0[144]=32'h6da5ea7e; in1[144]=32'h2b6316d8; out[144]=32'h9edeae50;
in0[145]=32'h24273c49; in1[145]=32'hb9a5cb6c; out[145]=32'hf96851cc;
in0[146]=32'h284209d1; in1[146]=32'h15aa7a66; out[146]=32'h2cc78346;
in0[147]=32'h2cfced3c; in1[147]=32'h6957d6a3; out[147]=32'h4ebf3534;
in0[148]=32'ha92c257a; in1[148]=32'hf1f072ac; out[148]=32'h4eb981f8;
in0[149]=32'h59fd3ff7; in1[149]=32'h72a961c1; out[149]=32'h0538d037;
in0[150]=32'h885be472; in1[150]=32'hb547ebbb; out[150]=32'heb728546;
in0[151]=32'h0c766ef7; in1[151]=32'h4073156d; out[151]=32'h9e7c822b;
in0[152]=32'h0a79a0b1; in1[152]=32'hac32059e; out[152]=32'h25c6a23e;
in0[153]=32'h58cec29e; in1[153]=32'h5a436932; out[153]=32'ha18ed0dc;
in0[154]=32'h29ea5695; in1[154]=32'he56aace8; out[154]=32'h913c9308;
in0[155]=32'he66e0225; in1[155]=32'h532fed3c; out[155]=32'h3d8fc1ac;
in0[156]=32'h8f8d88cc; in1[156]=32'h919679d7; out[156]=32'h290e4f54;
in0[157]=32'h38df8e47; in1[157]=32'h1f0c945f; out[157]=32'h9d8ad859;
in0[158]=32'hbc4b3ab7; in1[158]=32'h5a52e8dd; out[158]=32'hdec587fb;
in0[159]=32'h085b46c2; in1[159]=32'hdd8f4894; out[159]=32'h81097828;
in0[160]=32'hefd70ecc; in1[160]=32'h869adb8e; out[160]=32'hb1aab928;
in0[161]=32'h75c13e5c; in1[161]=32'h17546ddf; out[161]=32'h95127e24;
in0[162]=32'hbcef8505; in1[162]=32'h0971bccd; out[162]=32'h15b23101;
in0[163]=32'h91c64a6e; in1[163]=32'h77e35119; out[163]=32'h1b7412be;
in0[164]=32'h802486ca; in1[164]=32'hc2080107; out[164]=32'hefd67986;
in0[165]=32'ha84c5fda; in1[165]=32'hbd7afe58; out[165]=32'h413f3ef0;
in0[166]=32'hdb171d57; in1[166]=32'hc68f1932; out[166]=32'hb9fa39fe;
in0[167]=32'h75c16123; in1[167]=32'h40ea150b; out[167]=32'h76450b81;
in0[168]=32'hc1e1b5cc; in1[168]=32'h592df361; out[168]=32'h96f2864c;
in0[169]=32'hfb00829b; in1[169]=32'h8572e7b4; out[169]=32'ha23bb1fc;
in0[170]=32'hef3ae1c5; in1[170]=32'h9c06943c; out[170]=32'h72f0ce2c;
in0[171]=32'h52feee10; in1[171]=32'h09683863; out[171]=32'h23299030;
in0[172]=32'h5d3d1fd9; in1[172]=32'hff2b58b6; out[172]=32'hccda3c46;
in0[173]=32'h9223c2ac; in1[173]=32'hd92da212; out[173]=32'hebf08818;
in0[174]=32'h5a95f71f; in1[174]=32'hdf61f1d2; out[174]=32'h2067e66e;
in0[175]=32'hd7a387b5; in1[175]=32'he268fd80; out[175]=32'h5a69bb80;
in0[176]=32'h5e3e30a0; in1[176]=32'hf32a25c1; out[176]=32'he429c8a0;
in0[177]=32'h193d9671; in1[177]=32'ha8502aad; out[177]=32'h549d345d;
in0[178]=32'h5d7ec9f5; in1[178]=32'hd3cffcc3; out[178]=32'h427c019f;
in0[179]=32'h335ad266; in1[179]=32'h37f1b415; out[179]=32'h0e68fa5e;
in0[180]=32'h6ef9f02e; in1[180]=32'h4bfee527; out[180]=32'h4390bd02;
in0[181]=32'h7dd02a51; in1[181]=32'hdfc72649; out[181]=32'h3a9b1719;
in0[182]=32'hc5e0d16b; in1[182]=32'hd50e4f5e; out[182]=32'h8406ea4a;
in0[183]=32'h6c7722dc; in1[183]=32'hcfb3c156; out[183]=32'h852191e8;
in0[184]=32'h5a9e2e9e; in1[184]=32'hd5fb12f4; out[184]=32'ha8f58a98;
in0[185]=32'h47bb68fb; in1[185]=32'h3ee2cc52; out[185]=32'hc945a466;
in0[186]=32'h712ba121; in1[186]=32'h3661d998; out[186]=32'h30fda498;
in0[187]=32'he74a85f7; in1[187]=32'h42064cdb; out[187]=32'hce4fee4d;
in0[188]=32'h0d358178; in1[188]=32'he398216f; out[188]=32'he7239b08;
in0[189]=32'h4f019ae7; in1[189]=32'h1301b1cf; out[189]=32'hbe4cf7c9;
in0[190]=32'h9475aae5; in1[190]=32'h2137e41e; out[190]=32'h6e30fad6;
in0[191]=32'h3a97727d; in1[191]=32'h9432ab85; out[191]=32'h3a91f9f1;
in0[192]=32'h5b2245b2; in1[192]=32'h619774ac; out[192]=32'h50997b98;
in0[193]=32'hed2c2809; in1[193]=32'hd488d86a; out[193]=32'h2ed82bba;
in0[194]=32'hfbc2ee41; in1[194]=32'hd764c9c5; out[194]=32'h72766105;
in0[195]=32'h7e1418fb; in1[195]=32'h84d5236d; out[195]=32'ha2cff3df;
in0[196]=32'ha0cff57e; in1[196]=32'h7c1b5264; out[196]=32'h5a284138;
in0[197]=32'h8b40e8d4; in1[197]=32'h2c89813d; out[197]=32'hed3e4e84;
in0[198]=32'ha45f7fbe; in1[198]=32'h1d6583b0; out[198]=32'hcbfc0ca0;
in0[199]=32'hdafd79b9; in1[199]=32'h9d0f20d7; out[199]=32'h30ef5a5f;
in0[200]=32'hc5c0be81; in1[200]=32'hcf1215ea; out[200]=32'h45e0b6ea;
in0[201]=32'h9346d97a; in1[201]=32'hcb8cf452; out[201]=32'h60b1f114;
in0[202]=32'h166e124d; in1[202]=32'h49fb3fb4; out[202]=32'hc264d124;
in0[203]=32'h3553c7d9; in1[203]=32'h9ce0c010; out[203]=32'h44ff3d90;
in0[204]=32'h9bb30307; in1[204]=32'h08aa175e; out[204]=32'h7ba6bd92;
in0[205]=32'h5deb4426; in1[205]=32'h39b68ba7; out[205]=32'heb7e16ca;
in0[206]=32'h4744250b; in1[206]=32'h9e9219ab; out[206]=32'h2c68d159;
in0[207]=32'ha9d355c2; in1[207]=32'h0ddcb0ed; out[207]=32'h1053c49a;
in0[208]=32'h001a1c66; in1[208]=32'h9de73758; out[208]=32'hd31dad10;
in0[209]=32'hc8a2d971; in1[209]=32'h46444aef; out[209]=32'h0ae7aa7f;
in0[210]=32'h13d7bea0; in1[210]=32'h4d28230a; out[210]=32'h2e7d5240;
in0[211]=32'hd5415afc; in1[211]=32'h82dcf376; out[211]=32'h7e0d2428;
in0[212]=32'hd8bc8ce0; in1[212]=32'h0b3f3b10; out[212]=32'h4b606e00;
in0[213]=32'h05f84252; in1[213]=32'h40bc9890; out[213]=32'hf73dfe20;
in0[214]=32'hfc644a3a; in1[214]=32'hd195f70e; out[214]=32'h1edc052c;
in0[215]=32'he894a00d; in1[215]=32'h799595bd; out[215]=32'h8372ba99;
in0[216]=32'h71b0cf67; in1[216]=32'h6f9f6364; out[216]=32'h433ed93c;
in0[217]=32'h37e55cb4; in1[217]=32'hab0612f8; out[217]=32'haeee7660;
in0[218]=32'hd3fce285; in1[218]=32'he652436a; out[218]=32'h02989a12;
in0[219]=32'hb0a1907a; in1[219]=32'h9b7c35b3; out[219]=32'hccf9474e;
in0[220]=32'hb501460b; in1[220]=32'h276b709e; out[220]=32'h39070aca;
in0[221]=32'hf258edba; in1[221]=32'he7e5eb82; out[221]=32'h30c47674;
in0[222]=32'h04836a14; in1[222]=32'h470cc4d9; out[222]=32'hf58c3af4;
in0[223]=32'h5a3380b3; in1[223]=32'hbcb021b3; out[223]=32'ha4aa1029;
in0[224]=32'ha99556be; in1[224]=32'he1f6840c; out[224]=32'h4c4e08e8;
in0[225]=32'he2ab629d; in1[225]=32'ha56dddd6; out[225]=32'h9d3ef83e;
in0[226]=32'h742114f4; in1[226]=32'h87e84d8c; out[226]=32'h1e84d970;
in0[227]=32'h062133cb; in1[227]=32'h605c3d31; out[227]=32'hd2a648db;
in0[228]=32'h253163d7; in1[228]=32'h265cf808; out[228]=32'hcd8766b8;
in0[229]=32'hc714ae5c; in1[229]=32'h1de35fd3; out[229]=32'hca53d9d4;
in0[230]=32'h6d6deaba; in1[230]=32'h4574eae8; out[230]=32'h2272bc90;
in0[231]=32'ha4e12a2f; in1[231]=32'h969453c8; out[231]=32'hbdc231b8;
in0[232]=32'h9ecef5ed; in1[232]=32'h9e40bd89; out[232]=32'h899194d5;
in0[233]=32'h0c88088c; in1[233]=32'h26cb1b1a; out[233]=32'h2dbba238;
in0[234]=32'h0301a7f4; in1[234]=32'he4831e32; out[234]=32'h09dd65a8;
in0[235]=32'hb4d1df26; in1[235]=32'h5e78ab10; out[235]=32'h0afc5460;
in0[236]=32'h07aa454b; in1[236]=32'hc0045727; out[236]=32'h5da90b6d;
in0[237]=32'h87cf6cdc; in1[237]=32'ha1fcbf84; out[237]=32'h4dbc4570;
in0[238]=32'hb88e2c54; in1[238]=32'h01906ab6; out[238]=32'h56ae4bb8;
in0[239]=32'hc9c74a91; in1[239]=32'hed0abd5a; out[239]=32'h38c743fa;
in0[240]=32'h205b6f69; in1[240]=32'h6db1c399; out[240]=32'hb91b90c1;
in0[241]=32'h9fdb295c; in1[241]=32'h8a17a800; out[241]=32'h22686000;
in0[242]=32'h49f8456b; in1[242]=32'hf747f782; out[242]=32'h98ba7d56;
in0[243]=32'ha77cbdb4; in1[243]=32'hefbc6e2c; out[243]=32'hbf23f2f0;
in0[244]=32'h3f6b9639; in1[244]=32'hac7d6c79; out[244]=32'h030f0cf1;
in0[245]=32'h0e36d935; in1[245]=32'hc3a7585f; out[245]=32'h3197d2ab;
in0[246]=32'h4dcfbc10; in1[246]=32'h6c46ce0e; out[246]=32'h971128e0;
in0[247]=32'hf964d8ec; in1[247]=32'hb28129af; out[247]=32'h099a1554;
in0[248]=32'hab1cce1c; in1[248]=32'h88a2ee89; out[248]=32'ha7c054fc;
in0[249]=32'h266b218d; in1[249]=32'h5a394ff2; out[249]=32'h6b053a4a;
in0[250]=32'h32270ce5; in1[250]=32'h0a0cef9f; out[250]=32'h2806cd3b;
in0[251]=32'h26664bc3; in1[251]=32'h5001d320; out[251]=32'h58fe3160;
in0[252]=32'h23a3f25d; in1[252]=32'hbd775ef6; out[252]=32'hc4c40b5e;
in0[253]=32'hfe0d1219; in1[253]=32'hef7313c3; out[253]=32'hf487a40b;
in0[254]=32'hc6bae0ce; in1[254]=32'h4a37eff6; out[254]=32'h47b657f4;
in0[255]=32'hf14eb26f; in1[255]=32'h54fa7895; out[255]=32'h02d7e29b;
in0[256]=32'ha7779e11; in1[256]=32'hd7d1c505; out[256]=32'ha4da2b55;
in0[257]=32'h487286a7; in1[257]=32'h783de1f0; out[257]=32'hf1820390;
in0[258]=32'h6d0a23ba; in1[258]=32'h7faa616a; out[258]=32'hfd404504;
in0[259]=32'h8508150c; in1[259]=32'h24a4c40a; out[259]=32'h8e1e0278;
in0[260]=32'h434541b1; in1[260]=32'h6a265a0a; out[260]=32'h0412caea;
in0[261]=32'hc7bb828e; in1[261]=32'hdccae8cf; out[261]=32'h7afb40d2;
in0[262]=32'h383379f5; in1[262]=32'h04975ccc; out[262]=32'h0c5c3b3c;
in0[263]=32'h4f7a11db; in1[263]=32'hcab990ff; out[263]=32'h89e5f925;
in0[264]=32'h683ffeb4; in1[264]=32'hb1e2531b; out[264]=32'h0d3c38fc;
in0[265]=32'h830492cb; in1[265]=32'h2409d01c; out[265]=32'hc0e7fe34;
in0[266]=32'h2ed4e2c0; in1[266]=32'h0910246b; out[266]=32'h6eddc640;
in0[267]=32'h05cce361; in1[267]=32'hf7c2072b; out[267]=32'h7a23d84b;
in0[268]=32'h6b0d8e18; in1[268]=32'h76ebeec4; out[268]=32'h10831a60;
in0[269]=32'h309edc08; in1[269]=32'hc4e2319e; out[269]=32'hc93954f0;
in0[270]=32'h62885fbc; in1[270]=32'he67c3b35; out[270]=32'h1b5c25ec;
in0[271]=32'h9c0d22e9; in1[271]=32'h9f23050e; out[271]=32'h474175be;
in0[272]=32'h1091462e; in1[272]=32'hb676cb3d; out[272]=32'h327832f6;
in0[273]=32'hc28b4b48; in1[273]=32'h764876ee; out[273]=32'h6e732cf0;
in0[274]=32'h91c732e4; in1[274]=32'hf26df08b; out[274]=32'h19f261cc;
in0[275]=32'h686f510b; in1[275]=32'h202c24b9; out[275]=32'h6dbb1cf3;
in0[276]=32'h307c7801; in1[276]=32'h534cc6a4; out[276]=32'h47d9a6a4;
in0[277]=32'hf050d7d6; in1[277]=32'h1e936a7b; out[277]=32'hf4184fd2;
in0[278]=32'h860d3200; in1[278]=32'h51debf7b; out[278]=32'h9ca50600;
in0[279]=32'h7683c0f8; in1[279]=32'h2c10b734; out[279]=32'hf1347a60;
in0[280]=32'h8791b65a; in1[280]=32'h656cfa9a; out[280]=32'h49b39624;
in0[281]=32'h59dd85c8; in1[281]=32'h51b9a59a; out[281]=32'hcc046250;
in0[282]=32'h8c20197f; in1[282]=32'h51dceda3; out[282]=32'h082ecedd;
in0[283]=32'hbaf7c487; in1[283]=32'h2dde9bc0; out[283]=32'h65e32240;
in0[284]=32'h32887e2d; in1[284]=32'hb1c0d168; out[284]=32'hb535ff48;
in0[285]=32'h68fe2a8f; in1[285]=32'h689f0f2b; out[285]=32'h0e008705;
in0[286]=32'h868ccca9; in1[286]=32'h2944e26a; out[286]=32'h70ddeffa;
in0[287]=32'hc745aba5; in1[287]=32'h12e5d12b; out[287]=32'h7e6e89b7;
in0[288]=32'h4669f0bd; in1[288]=32'hf07de8bf; out[288]=32'h477ee503;
in0[289]=32'h44ef4adf; in1[289]=32'h4735c1c8; out[289]=32'h9b8f9d38;
in0[290]=32'h7d4faa6e; in1[290]=32'he51ccc78; out[290]=32'h432f8b90;
in0[291]=32'h65186931; in1[291]=32'h9901ee55; out[291]=32'hf5177b45;
in0[292]=32'hb52815f6; in1[292]=32'h3a4c714e; out[292]=32'h24f046f4;
in0[293]=32'hed8f3e7d; in1[293]=32'he69dc5e3; out[293]=32'h81c399d7;
in0[294]=32'h2e78dfb1; in1[294]=32'h82c02c5e; out[294]=32'h7d948efe;
in0[295]=32'h03396cd0; in1[295]=32'haf9c1966; out[295]=32'h6341aae0;
in0[296]=32'h1d7ec22f; in1[296]=32'h18e5279f; out[296]=32'hbd5ac431;
in0[297]=32'h9e3299bd; in1[297]=32'h9922b25f; out[297]=32'h43c67723;
in0[298]=32'hec01bdfa; in1[298]=32'he76557d9; out[298]=32'h2eabfeea;
in0[299]=32'h313c30b1; in1[299]=32'h52cd2e9a; out[299]=32'h1eb2187a;
in0[300]=32'h4929e525; in1[300]=32'h87b996a9; out[300]=32'hf3a8f36d;
in0[301]=32'h21ba358e; in1[301]=32'h5dc1ca81; out[301]=32'he325088e;
in0[302]=32'hcd39e881; in1[302]=32'h0bc71b25; out[302]=32'h0c2b35a5;
in0[303]=32'h7bdb4c17; in1[303]=32'hc179439e; out[303]=32'h2421fb32;
in0[304]=32'hbe1f82ea; in1[304]=32'h20c67732; out[304]=32'h48fe57b4;
in0[305]=32'hd23a4e6f; in1[305]=32'h2b647012; out[305]=32'h92c613ce;
in0[306]=32'hbdd7052b; in1[306]=32'h55483457; out[306]=32'hec377d9d;
in0[307]=32'hceef2e5a; in1[307]=32'h36571fd8; out[307]=32'h4d0201f0;
in0[308]=32'ha542c9a4; in1[308]=32'h0fe359e3; out[308]=32'h2abed06c;
in0[309]=32'h22ea522a; in1[309]=32'h7ca89e7e; out[309]=32'h119a5cac;
in0[310]=32'h09969daf; in1[310]=32'hd4954bf3; out[310]=32'hed04f21d;
in0[311]=32'h3e2e3058; in1[311]=32'h10644993; out[311]=32'h42aeda88;
in0[312]=32'h04c28347; in1[312]=32'h47b7fa8c; out[312]=32'h175420d4;
in0[313]=32'h844a8205; in1[313]=32'hafde939e; out[313]=32'h99fb1e16;
in0[314]=32'h3e9d095d; in1[314]=32'h51befdc6; out[314]=32'hffbc26ee;
in0[315]=32'h9edbab39; in1[315]=32'hd8719469; out[315]=32'hd33f2e61;
in0[316]=32'he307c937; in1[316]=32'hdb5ee340; out[316]=32'h989012c0;
in0[317]=32'hfe15712a; in1[317]=32'h3de33ef7; out[317]=32'hb2565b86;
in0[318]=32'h1a1cb012; in1[318]=32'h90eca548; out[318]=32'h46251f10;
in0[319]=32'h1f17cff4; in1[319]=32'h6dbd01e4; out[319]=32'h34292950;
in0[320]=32'h105bc55a; in1[320]=32'hffd76e1e; out[320]=32'hbe23cc8c;
in0[321]=32'hfb093a3e; in1[321]=32'he2662482; out[321]=32'hb7944b7c;
in0[322]=32'h059e15a3; in1[322]=32'h29931c55; out[322]=32'haf74031f;
in0[323]=32'h3ae8e1c4; in1[323]=32'h85202c97; out[323]=32'hd2aada9c;
in0[324]=32'hbc19e2a4; in1[324]=32'h57c1cfe5; out[324]=32'hcb0e58b4;
in0[325]=32'ha981aa5a; in1[325]=32'h10aa07d5; out[325]=32'h544f32e2;
in0[326]=32'hdb7f68b3; in1[326]=32'hc20a33aa; out[326]=32'he1752fde;
in0[327]=32'h23a84380; in1[327]=32'h3a25422c; out[327]=32'h43d29a00;
in0[328]=32'h5e94cd95; in1[328]=32'h3c88d1b7; out[328]=32'h3b5d9a83;
in0[329]=32'h40593305; in1[329]=32'hed9922f7; out[329]=32'h0dd3e3d3;
in0[330]=32'heacfa854; in1[330]=32'h74c78ae0; out[330]=32'h4fbc9180;
in0[331]=32'he09aafbc; in1[331]=32'hbd1335d5; out[331]=32'hbe0a236c;
in0[332]=32'hb583bc7f; in1[332]=32'h4b1b9eef; out[332]=32'hdab85c91;
in0[333]=32'h72f2be80; in1[333]=32'h9bc8c686; out[333]=32'h3e66b700;
in0[334]=32'h02a33ce1; in1[334]=32'hea5f2fde; out[334]=32'h833b1a1e;
in0[335]=32'h73586a52; in1[335]=32'h9aa9a950; out[335]=32'hedf35ba0;
in0[336]=32'ha71510b7; in1[336]=32'h3d67fcbf; out[336]=32'hb9cc9c89;
in0[337]=32'h78846532; in1[337]=32'h3d37b4a6; out[337]=32'he4bec66c;
in0[338]=32'h87317543; in1[338]=32'he87b2fdb; out[338]=32'hcb079d51;
in0[339]=32'h7faf79cf; in1[339]=32'h52e1678c; out[339]=32'hcae7e634;
in0[340]=32'h918d4bad; in1[340]=32'hcf193505; out[340]=32'h5f524b61;
in0[341]=32'hbec49725; in1[341]=32'h38014301; out[341]=32'he1784625;
in0[342]=32'hcba2d5c6; in1[342]=32'h677b98a2; out[342]=32'hec1ad74c;
in0[343]=32'he0d8f342; in1[343]=32'he3ec2b50; out[343]=32'h7b801aa0;
in0[344]=32'h09a26145; in1[344]=32'h1a40571f; out[344]=32'hacf83a5b;
in0[345]=32'h398ad762; in1[345]=32'h4d3e963c; out[345]=32'h7a79e6f8;
in0[346]=32'h5a7b1fb8; in1[346]=32'h54da3cf4; out[346]=32'h7b795b60;
in0[347]=32'hf59f933f; in1[347]=32'hef3df99e; out[347]=32'hb5b827e2;
in0[348]=32'h47f452fa; in1[348]=32'h72270452; out[348]=32'hd5a47c14;
in0[349]=32'h382e7b64; in1[349]=32'h8ca6f02f; out[349]=32'h970e675c;
in0[350]=32'h5977e140; in1[350]=32'h45216187; out[350]=32'he3d108c0;
in0[351]=32'hce4b4aab; in1[351]=32'hf0100490; out[351]=32'h3234ac30;
in0[352]=32'h4ab70502; in1[352]=32'h1edbb5db; out[352]=32'hd5d1b2b6;
in0[353]=32'hc1b9756e; in1[353]=32'h04d51d64; out[353]=32'h1b4554f8;
in0[354]=32'h0f5bd55b; in1[354]=32'hd1a139eb; out[354]=32'h05091d89;
in0[355]=32'h5292538b; in1[355]=32'h787f45e7; out[355]=32'h8c82d96d;
in0[356]=32'h073509d8; in1[356]=32'hcc982bbf; out[356]=32'h4179a028;
in0[357]=32'ha38a7dd3; in1[357]=32'h7c9977d0; out[357]=32'ha81e5070;
in0[358]=32'he3ce3ed3; in1[358]=32'h90970998; out[358]=32'h411fb848;
in0[359]=32'hf3eac30a; in1[359]=32'hacc60367; out[359]=32'h75799706;
in0[360]=32'hdb03760a; in1[360]=32'h02e54338; out[360]=32'h7b987030;
in0[361]=32'h97278147; in1[361]=32'he8c4f906; out[361]=32'h4a0716aa;
in0[362]=32'h10655e95; in1[362]=32'h1fe5e0d2; out[362]=32'hcc32f63a;
in0[363]=32'hf8e70168; in1[363]=32'h5f6eae1f; out[363]=32'h599ddb98;
in0[364]=32'hf3441422; in1[364]=32'h6f510056; out[364]=32'hd5a0c36c;
in0[365]=32'h844c484f; in1[365]=32'hf563c8c0; out[365]=32'h6340f340;
in0[366]=32'he067ec5b; in1[366]=32'h3cdff143; out[366]=32'hc7f986d1;
in0[367]=32'h69e7963d; in1[367]=32'h7fb283a7; out[367]=32'h515e38cb;
in0[368]=32'h8503508c; in1[368]=32'h07bccccc; out[368]=32'h9da3bf90;
in0[369]=32'hbfef7179; in1[369]=32'h13fd890d; out[369]=32'h02778425;
in0[370]=32'hc26b607f; in1[370]=32'h5cf54b56; out[370]=32'hc2e29faa;
in0[371]=32'hfd20103d; in1[371]=32'h02e206a5; out[371]=32'hb5e5e551;
in0[372]=32'h8c17bc54; in1[372]=32'hfb1a5315; out[372]=32'hac89aee4;
in0[373]=32'hd87e0a47; in1[373]=32'hd061f51c; out[373]=32'he28612c4;
in0[374]=32'h0de756f3; in1[374]=32'hc8405ee0; out[374]=32'hb1194ea0;
in0[375]=32'h9d308733; in1[375]=32'h42171331; out[375]=32'hfbe7a9c3;
in0[376]=32'h2236b91b; in1[376]=32'hcb664cee; out[376]=32'h37961b1a;
in0[377]=32'hc4643707; in1[377]=32'he183b560; out[377]=32'hd01195a0;
in0[378]=32'h50eb5fee; in1[378]=32'hb51c65dd; out[378]=32'h7c12b676;
in0[379]=32'h4424567b; in1[379]=32'h81fc7dd5; out[379]=32'h8c8a0357;
in0[380]=32'h4772bdcb; in1[380]=32'h9e13308b; out[380]=32'haef41d39;
in0[381]=32'hc651ba43; in1[381]=32'h5224d51d; out[381]=32'h1ea7d897;
in0[382]=32'h784e9df5; in1[382]=32'hbca44184; out[382]=32'h1b98a754;
in0[383]=32'haa3f78c6; in1[383]=32'h170c1fdf; out[383]=32'h70322e7a;
in0[384]=32'hdfdb7a1a; in1[384]=32'hdf6fe8a9; out[384]=32'h45d12b2a;
in0[385]=32'h689e6563; in1[385]=32'hf1615f30; out[385]=32'h02d5bf90;
in0[386]=32'hd98a8701; in1[386]=32'hc150d721; out[386]=32'h538d3e21;
in0[387]=32'he8ac8645; in1[387]=32'he459d68b; out[387]=32'hafe79577;
in0[388]=32'he5275a4c; in1[388]=32'h274b64f8; out[388]=32'h65a929a0;
in0[389]=32'hc887f403; in1[389]=32'hbcb6ed2b; out[389]=32'h39dec381;
in0[390]=32'h262c77d7; in1[390]=32'h9b83b13d; out[390]=32'h5779353b;
in0[391]=32'hbe39e2a6; in1[391]=32'h6d4d84fe; out[391]=32'h703a78b4;
in0[392]=32'hfd4b62bf; in1[392]=32'h63da7958; out[392]=32'ha73c38a8;
in0[393]=32'h31eb0ed8; in1[393]=32'hdd14ee95; out[393]=32'h367c73b8;
in0[394]=32'h314032d7; in1[394]=32'h89d32311; out[394]=32'h026bc547;
in0[395]=32'h293052f3; in1[395]=32'haddf4d11; out[395]=32'hbdd59923;
in0[396]=32'h4c833be5; in1[396]=32'h09ddd75c; out[396]=32'h7827d94c;
in0[397]=32'h235a5d6c; in1[397]=32'h39aca3af; out[397]=32'h84d1a0d4;
in0[398]=32'h911e32a6; in1[398]=32'h8ea73717; out[398]=32'ha4e236ea;
in0[399]=32'he05082e8; in1[399]=32'he5253ed5; out[399]=32'h96391b08;
in0[400]=32'h804eff2c; in1[400]=32'h41e9ccfe; out[400]=32'hacc43da8;
in0[401]=32'h9ea72601; in1[401]=32'h09dba185; out[401]=32'h17985f85;
in0[402]=32'ha23e06cb; in1[402]=32'hc1ca0660; out[402]=32'hb2994e20;
in0[403]=32'had826f8d; in1[403]=32'he4f1f77b; out[403]=32'hcf09a3bf;
in0[404]=32'h64d61f05; in1[404]=32'h863a0036; out[404]=32'hea4c8b0e;
in0[405]=32'h4c4fbfdc; in1[405]=32'h871225c2; out[405]=32'hdca230b8;
in0[406]=32'h66cd4776; in1[406]=32'hd1e1a1b7; out[406]=32'hbb654b5a;
in0[407]=32'h2375dcf3; in1[407]=32'hb3ae9815; out[407]=32'hfa0567ef;
in0[408]=32'h2fff94b5; in1[408]=32'h4ff79261; out[408]=32'h48499295;
in0[409]=32'h82da5afe; in1[409]=32'h61151514; out[409]=32'hd75bf1d8;
in0[410]=32'h177a273d; in1[410]=32'h10d532c3; out[410]=32'h3376cd77;
in0[411]=32'h09995287; in1[411]=32'h44e45613; out[411]=32'h94567a05;
in0[412]=32'hcb34d9a0; in1[412]=32'h3c3d6423; out[412]=32'hc85c40e0;
in0[413]=32'h1268632d; in1[413]=32'hf12c0a70; out[413]=32'h8a4725b0;
in0[414]=32'h76401fd9; in1[414]=32'hd1f42c0b; out[414]=32'h9e0eaa53;
in0[415]=32'hc05114ce; in1[415]=32'ha170c28f; out[415]=32'h872ebb12;
in0[416]=32'h0494598b; in1[416]=32'hf554b1bc; out[416]=32'h5776dd14;
in0[417]=32'hb6d04f2d; in1[417]=32'h1c3e6562; out[417]=32'h43e1103a;
in0[418]=32'h4bb2c190; in1[418]=32'h7766ca7b; out[418]=32'h7afea030;
in0[419]=32'hbb7eb320; in1[419]=32'hda5b814f; out[419]=32'ha0bc66e0;
in0[420]=32'h8f023613; in1[420]=32'h5a55bad7; out[420]=32'h587437f5;
in0[421]=32'h284c2a9e; in1[421]=32'h6fbb8289; out[421]=32'he1d10a8e;
in0[422]=32'h860ba2cf; in1[422]=32'ha6ca3ff2; out[422]=32'h4566d8ae;
in0[423]=32'hcdc95e87; in1[423]=32'h61c93b9f; out[423]=32'h97d9d2d9;
in0[424]=32'h540a20e4; in1[424]=32'hd91cd541; out[424]=32'ha0e00de4;
in0[425]=32'ha65feeac; in1[425]=32'h46780927; out[425]=32'ha0a16834;
in0[426]=32'h7155396b; in1[426]=32'hbdb9af06; out[426]=32'h67927d82;
in0[427]=32'h86e5b808; in1[427]=32'h16ff4c33; out[427]=32'h125e0998;
in0[428]=32'hb08aa190; in1[428]=32'h567f53b1; out[428]=32'h88ab6490;
in0[429]=32'h56cfa254; in1[429]=32'h3822c24d; out[429]=32'h649f7b44;
in0[430]=32'hda1b2555; in1[430]=32'ha6e633e3; out[430]=32'h76e0095f;
in0[431]=32'h68ab91e8; in1[431]=32'h29232139; out[431]=32'h86ba64a8;
in0[432]=32'hf68f4ddb; in1[432]=32'hcb28e872; out[432]=32'h7d972386;
in0[433]=32'h80cf194b; in1[433]=32'h7179939e; out[433]=32'h7acaad4a;
in0[434]=32'h5422ba61; in1[434]=32'hc93d6242; out[434]=32'h8e6a2f02;
in0[435]=32'hf21be95d; in1[435]=32'h72317b0e; out[435]=32'hbb737216;
in0[436]=32'h4842eef8; in1[436]=32'h4c05c0c6; out[436]=32'h61d6d3d0;
in0[437]=32'hc97c8d0f; in1[437]=32'h4e4a2df7; out[437]=32'ha44dbc79;
in0[438]=32'h302dcc6e; in1[438]=32'hed4e7e2d; out[438]=32'h222f1356;
in0[439]=32'h206fb5fa; in1[439]=32'h4dcae4df; out[439]=32'h88a62cc6;
in0[440]=32'h87e9cd9c; in1[440]=32'h4f148f6c; out[440]=32'h24ace1d0;
in0[441]=32'h4adfca26; in1[441]=32'h15d6152d; out[441]=32'h9eafa6ae;
in0[442]=32'hdf201a3d; in1[442]=32'hbc1d2eb3; out[442]=32'h8d124ea7;
in0[443]=32'h4ee10118; in1[443]=32'h32f33004; out[443]=32'h25808460;
in0[444]=32'hb6b40dd1; in1[444]=32'h0bff6268; out[444]=32'he49e9ee8;
in0[445]=32'h14f9899a; in1[445]=32'h7b8edb59; out[445]=32'h14e3948a;
in0[446]=32'heb3347b1; in1[446]=32'h6a582040; out[446]=32'h24a00c40;
in0[447]=32'habab26f8; in1[447]=32'h07b60af7; out[447]=32'hcdf84948;
in0[448]=32'h352ba96f; in1[448]=32'h446c5805; out[448]=32'h02ec772b;
in0[449]=32'h704cea88; in1[449]=32'h2cf7157c; out[449]=32'h5db6c1e0;
in0[450]=32'h499b6d22; in1[450]=32'h0dcc5865; out[450]=32'h28edbe6a;
in0[451]=32'h36a88abf; in1[451]=32'h4eea4439; out[451]=32'hf4f7a087;
in0[452]=32'h1395da31; in1[452]=32'hc248d001; out[452]=32'h54a5aa31;
in0[453]=32'h0ecaa2e7; in1[453]=32'hf8c80ad1; out[453]=32'h0a440497;
in0[454]=32'h71d790f0; in1[454]=32'h8aafdf0c; out[454]=32'h916bdb40;
in0[455]=32'hea22c667; in1[455]=32'h65efd9c6; out[455]=32'h6e3bc2aa;
in0[456]=32'h85c46717; in1[456]=32'h1c950314; out[456]=32'h44f052cc;
in0[457]=32'h26b1ecc5; in1[457]=32'h6cb2f76d; out[457]=32'he22de2e1;
in0[458]=32'hba2b3b2c; in1[458]=32'hdcd50e4f; out[458]=32'hdc2faa94;
in0[459]=32'hc5fddfc2; in1[459]=32'h44fec335; out[459]=32'he97c192a;
in0[460]=32'h5ab76cfb; in1[460]=32'ha0db97e9; out[460]=32'hdcf33d73;
in0[461]=32'hb6752a70; in1[461]=32'ha1739668; out[461]=32'h46c6dd80;
in0[462]=32'h349d7305; in1[462]=32'h37bfaf4a; out[462]=32'hbadeaa72;
in0[463]=32'hc333e1bd; in1[463]=32'h45eb971c; out[463]=32'h1d522bac;
in0[464]=32'h3ac73949; in1[464]=32'ha3343292; out[464]=32'h8ca2eda2;
in0[465]=32'h777ee05c; in1[465]=32'h9098a488; out[465]=32'hb9c220e0;
in0[466]=32'h63bdcff6; in1[466]=32'hf2c4623f; out[466]=32'hf9aa598a;
in0[467]=32'h8796d48d; in1[467]=32'hf97c012a; out[467]=32'heedf6c22;
in0[468]=32'h7bb98415; in1[468]=32'h724aba9e; out[468]=32'hae88c6f6;
in0[469]=32'h891dc838; in1[469]=32'h4621c8b5; out[469]=32'h55b24f98;
in0[470]=32'h5b7f7e4e; in1[470]=32'h3cf85d6f; out[470]=32'ha0ba19d2;
in0[471]=32'h98db9ea5; in1[471]=32'h53f0dca5; out[471]=32'h7b930c59;
in0[472]=32'h2dafcd38; in1[472]=32'h621dee9f; out[472]=32'h805285c8;
in0[473]=32'h02fda827; in1[473]=32'hf93d4fdc; out[473]=32'hd92b8a84;
in0[474]=32'hccd04b7a; in1[474]=32'h8bbe0522; out[474]=32'h87af6834;
in0[475]=32'h61c20952; in1[475]=32'h6d9bb2bb; out[475]=32'he1ddd2e6;
in0[476]=32'h371926a4; in1[476]=32'h18f0a985; out[476]=32'hd4535734;
in0[477]=32'hda36a2f8; in1[477]=32'h7a927ea6; out[477]=32'h8513bcd0;
in0[478]=32'h5c1013f0; in1[478]=32'h853f4ed8; out[478]=32'h2bb3f280;
in0[479]=32'had1b0674; in1[479]=32'h1e3f3f39; out[479]=32'h6026fbd4;
in0[480]=32'hb58a7c06; in1[480]=32'h799b3188; out[480]=32'he0f10930;
in0[481]=32'h56c235d2; in1[481]=32'h0cea1d88; out[481]=32'h21396190;
in0[482]=32'h25bbb347; in1[482]=32'hb2155ac4; out[482]=32'hf38f385c;
in0[483]=32'h83d0ae04; in1[483]=32'h1f51d507; out[483]=32'hc6c2161c;
in0[484]=32'ha90fa26e; in1[484]=32'hf27b24fd; out[484]=32'h4e24feb6;
in0[485]=32'h85a919b2; in1[485]=32'h7f5db65d; out[485]=32'h6a5ce1aa;
in0[486]=32'h6b920915; in1[486]=32'h3601d3cb; out[486]=32'h215e82a7;
in0[487]=32'hc05ec16d; in1[487]=32'h4d0c8d02; out[487]=32'h8b628bda;
in0[488]=32'h00242b86; in1[488]=32'h28d8cd5d; out[488]=32'had0e1dae;
in0[489]=32'heb173b4f; in1[489]=32'h06dbdd7f; out[489]=32'h454e9f31;
in0[490]=32'h9655f377; in1[490]=32'h7a8376e6; out[490]=32'hfb5696ea;
in0[491]=32'h5b4cae40; in1[491]=32'h19682e80; out[491]=32'h77a6a000;
in0[492]=32'hd1108034; in1[492]=32'h6a811e3e; out[492]=32'hb3392498;
in0[493]=32'h17be06f3; in1[493]=32'h059f4211; out[493]=32'ha1561c23;
in0[494]=32'hd161b06a; in1[494]=32'h0e55840d; out[494]=32'h601e9d62;
in0[495]=32'hebb047e5; in1[495]=32'hc351738e; out[495]=32'h1a88c006;
in0[496]=32'h919c1779; in1[496]=32'h468a4bcd; out[496]=32'h12193ee5;
in0[497]=32'hb33b88a3; in1[497]=32'h1ce82a35; out[497]=32'h877607bf;
in0[498]=32'h94c75b34; in1[498]=32'hacaaa1af; out[498]=32'h952b0c8c;
in0[499]=32'hbff5cfed; in1[499]=32'hb7706b7e; out[499]=32'h9b9465a6;
in0[500]=32'h89ff8ef9; in1[500]=32'h05d853ec; out[500]=32'h920a888c;
in0[501]=32'h1fc79367; in1[501]=32'h87a66236; out[501]=32'h005085ba;
in0[502]=32'h9927705e; in1[502]=32'h38d4162a; out[502]=32'h21f8836c;
in0[503]=32'h07e72040; in1[503]=32'h9a5f9952; out[503]=32'h220e9480;
in0[504]=32'h7cb50803; in1[504]=32'h50ffc714; out[504]=32'h625bf53c;
in0[505]=32'h8c8b46f1; in1[505]=32'hbc9b8979; out[505]=32'he6b680e9;
in0[506]=32'h6ecd8416; in1[506]=32'ha750bce8; out[506]=32'hf81fdbf0;
in0[507]=32'h26c011c5; in1[507]=32'hfe40b9d4; out[507]=32'hcb261424;
in0[508]=32'h61f851bd; in1[508]=32'hcc74ce70; out[508]=32'h540dd8b0;
in0[509]=32'h5969dc0c; in1[509]=32'h7d1feeb3; out[509]=32'h710c0464;
in0[510]=32'h9afe52a4; in1[510]=32'h801528f2; out[510]=32'h08c7bf08;
in0[511]=32'h596e2d01; in1[511]=32'heb0559b5; out[511]=32'h54902ab5;
in0[512]=32'hfa03b872; in1[512]=32'h5ee2c65c; out[512]=32'h6aa274f8;
in0[513]=32'h65eae2fc; in1[513]=32'hf5a727a0; out[513]=32'hb9c64180;
in0[514]=32'haa962b3c; in1[514]=32'h81435276; out[514]=32'h47c525a8;
in0[515]=32'hb6286f44; in1[515]=32'hd4739e93; out[515]=32'hd96fdc0c;
in0[516]=32'h58f8eae9; in1[516]=32'h925f6c51; out[516]=32'h38539fb9;
in0[517]=32'h30cc3af1; in1[517]=32'h74ded52a; out[517]=32'h3f8a308a;
in0[518]=32'hf6dfd1b0; in1[518]=32'hdfffd3bf; out[518]=32'hd9218250;
in0[519]=32'hb2731da8; in1[519]=32'h1f3750a0; out[519]=32'h384f0900;
in0[520]=32'h2a15c3a5; in1[520]=32'h5b6e2c4b; out[520]=32'hc9e6ad57;
in0[521]=32'h25eba5cb; in1[521]=32'hfed480f9; out[521]=32'h6b35c273;
in0[522]=32'hfcf372a9; in1[522]=32'hc3d99169; out[522]=32'h900cc051;
in0[523]=32'h3355b468; in1[523]=32'h14ffc7fb; out[523]=32'hc7dcb9f8;
in0[524]=32'hd657194e; in1[524]=32'hfcd3eb6e; out[524]=32'hb0f17984;
in0[525]=32'h7b33e115; in1[525]=32'h16ba7f29; out[525]=32'hcf3a775d;
in0[526]=32'hfed76553; in1[526]=32'h4aad8b6f; out[526]=32'hea7ffffd;
in0[527]=32'h8ea179fd; in1[527]=32'h02f53ab6; out[527]=32'hb5910bde;
in0[528]=32'hb562e909; in1[528]=32'h3ed2309a; out[528]=32'h0093df6a;
in0[529]=32'hea1fc4a5; in1[529]=32'h455fb3c6; out[529]=32'hbd4c769e;
in0[530]=32'h6bd38a89; in1[530]=32'h5f9dd850; out[530]=32'hfc03e2d0;
in0[531]=32'h3eb364ab; in1[531]=32'hed83bd79; out[531]=32'he69dd3d3;
in0[532]=32'h423ed877; in1[532]=32'h57b6f1f0; out[532]=32'h9a4cf690;
in0[533]=32'h713913b1; in1[533]=32'h4be69ec1; out[533]=32'h22351671;
in0[534]=32'hd461bb54; in1[534]=32'ha829ae18; out[534]=32'h76f0a7e0;
in0[535]=32'h7b219ec1; in1[535]=32'ha8472222; out[535]=32'h8113b7a2;
in0[536]=32'h8b0fd506; in1[536]=32'hdedfdbaf; out[536]=32'h5f48c11a;
in0[537]=32'hbc65b0c9; in1[537]=32'h35197ac0; out[537]=32'ha32560c0;
in0[538]=32'he00858c4; in1[538]=32'hdcc57312; out[538]=32'h3f4a49c8;
in0[539]=32'h1ffc98a0; in1[539]=32'hd366c955; out[539]=32'ha2744d20;
in0[540]=32'ha900400b; in1[540]=32'hbd96d03d; out[540]=32'h1e8a329f;
in0[541]=32'h20150d4a; in1[541]=32'h1193e1e1; out[541]=32'h3eacb80a;
in0[542]=32'h9aee50d7; in1[542]=32'h4822b24c; out[542]=32'he7837dd4;
in0[543]=32'hab02ba00; in1[543]=32'hee969349; out[543]=32'h50950a00;
in0[544]=32'h02ecab3e; in1[544]=32'h2635c3b6; out[544]=32'h0287f814;
in0[545]=32'hb46883dc; in1[545]=32'h534f4f75; out[545]=32'hb959278c;
in0[546]=32'h497cceb1; in1[546]=32'h26369698; out[546]=32'ha28c6f18;
in0[547]=32'h7419250a; in1[547]=32'h8d9e1d0c; out[547]=32'ha88bde78;
in0[548]=32'h53e951ad; in1[548]=32'hbfe3e969; out[548]=32'h456ff4f5;
in0[549]=32'hd3e7e1d5; in1[549]=32'h69b2f158; out[549]=32'h86692638;
in0[550]=32'ha9adb447; in1[550]=32'h54003bc8; out[550]=32'he4413478;
in0[551]=32'h3f520473; in1[551]=32'h3d254083; out[551]=32'hf3b406d9;
in0[552]=32'h2303edc4; in1[552]=32'haf905811; out[552]=32'h673e2a04;
in0[553]=32'h2acb1125; in1[553]=32'he0a557e4; out[553]=32'h8c87d7f4;
in0[554]=32'hd51195e6; in1[554]=32'h3da9aa0b; out[554]=32'h98222ce2;
in0[555]=32'hfabcb732; in1[555]=32'h74028e64; out[555]=32'hb5b94b88;
in0[556]=32'hf332a118; in1[556]=32'h4d47bac1; out[556]=32'h07dee318;
in0[557]=32'h7f4fa284; in1[557]=32'h1d098de9; out[557]=32'h66a19e24;
in0[558]=32'h1d03d1b0; in1[558]=32'hbb5d4118; out[558]=32'h6d895880;
in0[559]=32'hcdb562c0; in1[559]=32'hbaca3103; out[559]=32'h8c86e840;
in0[560]=32'h25ec4393; in1[560]=32'hae307454; out[560]=32'h15b4c83c;
in0[561]=32'hfd2bb67d; in1[561]=32'h3cea30cc; out[561]=32'h0b4edb9c;
in0[562]=32'h874150af; in1[562]=32'h6ae97300; out[562]=32'h3c859d00;
in0[563]=32'h7d7a33d5; in1[563]=32'h492a8a69; out[563]=32'h9502145d;
in0[564]=32'hd02c2ba7; in1[564]=32'h2fa112d4; out[564]=32'h9cace44c;
in0[565]=32'ha403a2d5; in1[565]=32'h34733e55; out[565]=32'hc053a6b9;
in0[566]=32'h8d39b22e; in1[566]=32'h6b7d02c2; out[566]=32'hb39362dc;
in0[567]=32'hd17ed76f; in1[567]=32'h40efbdd9; out[567]=32'h1a329017;
in0[568]=32'h592b57c9; in1[568]=32'h10d1d169; out[568]=32'h308b1a71;
in0[569]=32'hef4a481a; in1[569]=32'h080cdf17; out[569]=32'h65b32056;
in0[570]=32'h01bb0ea7; in1[570]=32'hdcc150c9; out[570]=32'h6059b11f;
in0[571]=32'h2a2d02f8; in1[571]=32'hf6737d51; out[571]=32'hf8190878;
in0[572]=32'h7456a02b; in1[572]=32'hdc65f8fb; out[572]=32'h210fb229;
in0[573]=32'h029b7ea6; in1[573]=32'h0f857fb2; out[573]=32'h7a30696c;
in0[574]=32'hb4bf93c8; in1[574]=32'h7118978f; out[574]=32'h19ee84b8;
in0[575]=32'h3097015d; in1[575]=32'h6e17d021; out[575]=32'h09edbcfd;
in0[576]=32'had591abc; in1[576]=32'hc9a69bde; out[576]=32'h385d0308;
in0[577]=32'h2d0d6180; in1[577]=32'h71e29d49; out[577]=32'ha09c4d80;
in0[578]=32'hc2f96071; in1[578]=32'h7baec102; out[578]=32'h5f75f1e2;
in0[579]=32'h799e088a; in1[579]=32'h3bb3f07a; out[579]=32'he3cf71c4;
in0[580]=32'hf732dfbf; in1[580]=32'h376699fb; out[580]=32'hf5b48745;
in0[581]=32'h3dd97323; in1[581]=32'he67130a7; out[581]=32'h62e3abd5;
in0[582]=32'h89225c2f; in1[582]=32'hf30295eb; out[582]=32'h378ffa25;
in0[583]=32'h17028136; in1[583]=32'hb3ccd87b; out[583]=32'he441a4f2;
in0[584]=32'hb82753b2; in1[584]=32'hdeb3c49f; out[584]=32'h5df7438e;
in0[585]=32'h4d9096b8; in1[585]=32'h47de1f97; out[585]=32'hfe192e88;
in0[586]=32'hc724b7d6; in1[586]=32'h7ff733f3; out[586]=32'he1f42222;
in0[587]=32'h0231ac72; in1[587]=32'h719d6f45; out[587]=32'h3512e8ba;
in0[588]=32'ha7492361; in1[588]=32'hff0eccee; out[588]=32'h5c7e302e;
in0[589]=32'h5bdbead0; in1[589]=32'h2bc6e750; out[589]=32'hb27b1100;
in0[590]=32'h97493a77; in1[590]=32'h5612b597; out[590]=32'h18e59f31;
in0[591]=32'hd8c36f47; in1[591]=32'ha3ec09ce; out[591]=32'h16a10a22;
in0[592]=32'h224acbbb; in1[592]=32'h13c381bb; out[592]=32'hcdbd0c99;
in0[593]=32'h912feb62; in1[593]=32'h76af5ba0; out[593]=32'hda9cf340;
in0[594]=32'h85e9bd5d; in1[594]=32'h7210866a; out[594]=32'h0bb71682;
in0[595]=32'hfabdcbbf; in1[595]=32'h2a5ffa74; out[595]=32'he8d9d88c;
in0[596]=32'h82c768ab; in1[596]=32'h8ab12274; out[596]=32'h4a7d237c;
in0[597]=32'h3dcf547d; in1[597]=32'h3dafe7e0; out[597]=32'hb519b860;
in0[598]=32'ha0250a6f; in1[598]=32'hed3bbedf; out[598]=32'h289778b1;
in0[599]=32'hea55bca3; in1[599]=32'h568f7f3e; out[599]=32'h6a658c7a;
in0[600]=32'h87fb9dc1; in1[600]=32'h30123066; out[600]=32'ha3670ae6;
in0[601]=32'hefe1d3b0; in1[601]=32'h53b6d309; out[601]=32'h1f8a8130;
in0[602]=32'h56587563; in1[602]=32'h0ac2ca74; out[602]=32'hbfbb4edc;
in0[603]=32'h8b235b6f; in1[603]=32'hac12258c; out[603]=32'h355b0bb4;
in0[604]=32'h05886c3e; in1[604]=32'hfb375146; out[604]=32'hb8df36f4;
in0[605]=32'h876f7539; in1[605]=32'h3b5798c0; out[605]=32'hba90c2c0;
in0[606]=32'h3ae3c831; in1[606]=32'h11d05d42; out[606]=32'hd74369a2;
in0[607]=32'hca9571c8; in1[607]=32'h9810d340; out[607]=32'haea44a00;
in0[608]=32'h4974dfa0; in1[608]=32'h242f8fe2; out[608]=32'hb077cb40;
in0[609]=32'hd1f68af5; in1[609]=32'h4c3dd4d5; out[609]=32'hb59581d9;
in0[610]=32'h1234876e; in1[610]=32'h6fd23c2c; out[610]=32'h3b010ee8;
in0[611]=32'hcbebc633; in1[611]=32'h46815271; out[611]=32'h5a41d283;
in0[612]=32'h81fd0bb0; in1[612]=32'hbc61436a; out[612]=32'hba85e6e0;
in0[613]=32'h8ee65edd; in1[613]=32'hf0473ebd; out[613]=32'hca588f29;
in0[614]=32'h5d6057d0; in1[614]=32'hcc357ca4; out[614]=32'h6a510140;
in0[615]=32'h1f3d4dab; in1[615]=32'h8b9bd016; out[615]=32'h5de89cb2;
in0[616]=32'h22941b26; in1[616]=32'hc62018c2; out[616]=32'hdf8822cc;
in0[617]=32'haac3dfab; in1[617]=32'h9376ac38; out[617]=32'h3ef1d168;
in0[618]=32'hfd607cd8; in1[618]=32'h4117ff5b; out[618]=32'h3d0f88c8;
in0[619]=32'h5b4c6de2; in1[619]=32'h56c53038; out[619]=32'hc83c6970;
in0[620]=32'hd9a5ae02; in1[620]=32'hc1d8b01a; out[620]=32'h56250c34;
in0[621]=32'h55a72bae; in1[621]=32'ha61fc92b; out[621]=32'hc271f43a;
in0[622]=32'hc7c38beb; in1[622]=32'hf406edf0; out[622]=32'h935dbb50;
in0[623]=32'ha8750abb; in1[623]=32'hf7c0694e; out[623]=32'hce4ff7fa;
in0[624]=32'h9d40d9c4; in1[624]=32'h90d13696; out[624]=32'hdaf2f0d8;
in0[625]=32'hd448b4e8; in1[625]=32'haef03704; out[625]=32'h3980aba0;
in0[626]=32'h157d6dc3; in1[626]=32'h0461d998; out[626]=32'hb76676c8;
in0[627]=32'h27c72fd0; in1[627]=32'hfaea5bbb; out[627]=32'hb09edcf0;
in0[628]=32'haf1da01c; in1[628]=32'hbc4f693f; out[628]=32'h3799e2e4;
in0[629]=32'h40ecf94e; in1[629]=32'hfb7579db; out[629]=32'hf73523ba;
in0[630]=32'hcea7c3c8; in1[630]=32'hff742f61; out[630]=32'h0922e6c8;
in0[631]=32'h95432aee; in1[631]=32'hc25239a6; out[631]=32'hda58d454;
in0[632]=32'hf82443be; in1[632]=32'h4442a039; out[632]=32'hd965d54e;
in0[633]=32'h75d3408a; in1[633]=32'h7120507b; out[633]=32'h9beb224e;
in0[634]=32'h62083c5c; in1[634]=32'h8ccf7ac0; out[634]=32'h91551d00;
in0[635]=32'h07c9240a; in1[635]=32'he61749ec; out[635]=32'hc19a1338;
in0[636]=32'h3fe90226; in1[636]=32'hc6073f6e; out[636]=32'h40b04654;
in0[637]=32'h825c6e19; in1[637]=32'h8beb9bb3; out[637]=32'hc13d1e7b;
in0[638]=32'hc201a99d; in1[638]=32'h56942350; out[638]=32'ha7797810;
in0[639]=32'h8fd51d04; in1[639]=32'h4bf23fb7; out[639]=32'hdd43b9dc;
in0[640]=32'h96e4844a; in1[640]=32'h01b150c5; out[640]=32'h485aecf2;
in0[641]=32'h2d57626e; in1[641]=32'h6a6eb968; out[641]=32'h68e57ab0;
in0[642]=32'h096a8dc8; in1[642]=32'h169c0b08; out[642]=32'h754c0640;
in0[643]=32'h7e7aeffd; in1[643]=32'h88224367; out[643]=32'h57dfc5cb;
in0[644]=32'h80cd4236; in1[644]=32'hb37920f4; out[644]=32'h796fdb78;
in0[645]=32'hdd4d04e4; in1[645]=32'h6d085209; out[645]=32'hae663404;
in0[646]=32'h72ec3ec0; in1[646]=32'h15eb8379; out[646]=32'h9005e8c0;
in0[647]=32'h8ea6c2fc; in1[647]=32'h14341276; out[647]=32'hc5c39828;
in0[648]=32'he2025ba8; in1[648]=32'h1b5995a9; out[648]=32'h284f49e8;
in0[649]=32'he97bc552; in1[649]=32'hdee3413d; out[649]=32'h234dd68a;
in0[650]=32'h6906e47a; in1[650]=32'h53018a4e; out[650]=32'h29bd612c;
in0[651]=32'h973e9bf7; in1[651]=32'hb306187b; out[651]=32'he67e17ad;
in0[652]=32'h7bc417c5; in1[652]=32'h8e641f54; out[652]=32'hea2ca7a4;
in0[653]=32'h369aedd7; in1[653]=32'h54b20920; out[653]=32'h313849e0;
in0[654]=32'h8eeba447; in1[654]=32'h587e2c11; out[654]=32'h40d41cb7;
in0[655]=32'h4c56b073; in1[655]=32'h83755923; out[655]=32'h10c11ab9;
in0[656]=32'h00136160; in1[656]=32'h11ae7a11; out[656]=32'hccf13760;
in0[657]=32'h0402862c; in1[657]=32'headccba9; out[657]=32'h2bdf770c;
in0[658]=32'h8be5b7d3; in1[658]=32'hafafef8f; out[658]=32'h822cabdd;
in0[659]=32'h7e6db5b4; in1[659]=32'h29d9c9f5; out[659]=32'hfc3d3944;
in0[660]=32'h72e81c44; in1[660]=32'h3106e68c; out[660]=32'h0dec8d30;
in0[661]=32'h65e95c4b; in1[661]=32'hf10d887d; out[661]=32'h06c8e89f;
in0[662]=32'h427c12db; in1[662]=32'ha728f4f1; out[662]=32'ha7fe7c2b;
in0[663]=32'h7b24fac1; in1[663]=32'h155c1eb8; out[663]=32'hca52d8b8;
in0[664]=32'he62ff57c; in1[664]=32'h68b743da; out[664]=32'h6dba7f98;
in0[665]=32'h1d8e8137; in1[665]=32'h97a9775d; out[665]=32'hb92481fb;
in0[666]=32'hd6e7073a; in1[666]=32'h46b25771; out[666]=32'h41c2e69a;
in0[667]=32'hb7f302aa; in1[667]=32'h682eedd5; out[667]=32'h91349972;
in0[668]=32'hf4d85e7d; in1[668]=32'h3774d316; out[668]=32'h0c1d25be;
in0[669]=32'h4ac2ccb4; in1[669]=32'h73c38095; out[669]=32'hb2d724c4;
in0[670]=32'h18412b6f; in1[670]=32'h4c1d46d6; out[670]=32'hf7eda8ca;
in0[671]=32'hebda608e; in1[671]=32'he31266f4; out[671]=32'h82989b58;
in0[672]=32'hc00901b3; in1[672]=32'h7081a590; out[672]=32'hfe5c53b0;
in0[673]=32'h666afa58; in1[673]=32'hbf353f2b; out[673]=32'h03cbb4c8;
in0[674]=32'h15cb6357; in1[674]=32'h0b98c51c; out[674]=32'h9e58d084;
in0[675]=32'hf5fd2041; in1[675]=32'hc1b1c680; out[675]=32'h13736680;
in0[676]=32'hc6c5c409; in1[676]=32'h85461587; out[676]=32'h52d51dbf;
in0[677]=32'h5040e891; in1[677]=32'h8f07df1b; out[677]=32'h5c65d64b;
in0[678]=32'hb4a99fca; in1[678]=32'hb390472a; out[678]=32'hcec53d24;
in0[679]=32'hd34375eb; in1[679]=32'h2bd60958; out[679]=32'h09c7cbc8;
in0[680]=32'ha24a4f77; in1[680]=32'h752f7ea0; out[680]=32'hfb673c60;
in0[681]=32'h52ea42cd; in1[681]=32'h0c2e0c6e; out[681]=32'h38a05016;
in0[682]=32'h87722f16; in1[682]=32'he14b9ba6; out[682]=32'h17feda44;
in0[683]=32'h14f8199c; in1[683]=32'h5a666afe; out[683]=32'h94ec00c8;
in0[684]=32'h7d3021cc; in1[684]=32'hcd21a278; out[684]=32'hdb3eefa0;
in0[685]=32'h71f6fb9d; in1[685]=32'h8c619d0d; out[685]=32'h74570ff9;
in0[686]=32'h8eebf651; in1[686]=32'h32d358b2; out[686]=32'h53801c52;
in0[687]=32'h5b00fe01; in1[687]=32'h568dc61f; out[687]=32'h0620881f;
in0[688]=32'h2e270509; in1[688]=32'hcd077e90; out[688]=32'h82ac4310;
in0[689]=32'h4774fb11; in1[689]=32'hf8b59e18; out[689]=32'he0f10798;
in0[690]=32'h0fb27a6c; in1[690]=32'h0ca73923; out[690]=32'hcf1cc8c4;
in0[691]=32'h3682c016; in1[691]=32'h0d60f88c; out[691]=32'h9fd65c08;
in0[692]=32'h6f2a83e8; in1[692]=32'h9409c561; out[692]=32'h99c582e8;
in0[693]=32'h7df19d31; in1[693]=32'h37011b1e; out[693]=32'h621596be;
in0[694]=32'h5ea794ab; in1[694]=32'h8f4a8691; out[694]=32'hd32ab6db;
in0[695]=32'h43100787; in1[695]=32'hf96809ae; out[695]=32'h8300dcc2;
in0[696]=32'h77c01544; in1[696]=32'h4ac54aba; out[696]=32'h8d091b68;
in0[697]=32'h49e8b394; in1[697]=32'hc0be3494; out[697]=32'h46d9e190;
in0[698]=32'h844caad1; in1[698]=32'h8945c43f; out[698]=32'h24fb0d6f;
in0[699]=32'he72c42fe; in1[699]=32'h11b4cdf5; out[699]=32'ha7998316;
in0[700]=32'h917a0541; in1[700]=32'h6e2012a4; out[700]=32'h5ca9efa4;
in0[701]=32'hf97bbefd; in1[701]=32'h105a8443; out[701]=32'h0ecf7037;
in0[702]=32'h019c0f4c; in1[702]=32'h4def12a0; out[702]=32'h1e90e780;
in0[703]=32'h8ef2a455; in1[703]=32'hd86aa729; out[703]=32'hf141c49d;
in0[704]=32'h57a6a204; in1[704]=32'h2548d392; out[704]=32'h79b1b248;
in0[705]=32'hff59eb92; in1[705]=32'haa09a630; out[705]=32'h6bbed760;
in0[706]=32'hbbb1abdb; in1[706]=32'h35bf1565; out[706]=32'h2f96c467;
in0[707]=32'h27f61653; in1[707]=32'h6abc4caf; out[707]=32'h22cde6bd;
in0[708]=32'h8eeacd2f; in1[708]=32'h3e6d227e; out[708]=32'h45d43b22;
in0[709]=32'h0653ce53; in1[709]=32'h8c906eb8; out[709]=32'h0193f5a8;
in0[710]=32'h4f9f9aba; in1[710]=32'he837410f; out[710]=32'hfe994ae6;
in0[711]=32'h7c966fa1; in1[711]=32'hec3b7766; out[711]=32'hb7ef5126;
in0[712]=32'h862ac559; in1[712]=32'h00c4dd91; out[712]=32'h02bb9c69;
in0[713]=32'hc26a33f9; in1[713]=32'h12e86478; out[713]=32'h39bda0b8;
in0[714]=32'h661865df; in1[714]=32'hd9dd4d21; out[714]=32'h784c34bf;
in0[715]=32'h3a70efaa; in1[715]=32'hca1f1c5e; out[715]=32'hf944986c;
in0[716]=32'h2a8bc4ba; in1[716]=32'hb7bcf1cd; out[716]=32'h14b7a2f2;
in0[717]=32'h10a60431; in1[717]=32'h56527b18; out[717]=32'h2145ef98;
in0[718]=32'h6547c7e7; in1[718]=32'h34b4772e; out[718]=32'h0b3e4c82;
in0[719]=32'h5fa4ece7; in1[719]=32'h740f6a04; out[719]=32'h5634599c;
in0[720]=32'h90bc5c64; in1[720]=32'h31ab5289; out[720]=32'ha5317984;
in0[721]=32'hd2b11a5f; in1[721]=32'h948a6dee; out[721]=32'h6c16f752;
in0[722]=32'hf66a76d6; in1[722]=32'h29e420f5; out[722]=32'h3f567ace;
in0[723]=32'h6e9f031f; in1[723]=32'ha75dd3c8; out[723]=32'hd70ffd38;
in0[724]=32'h379cf2ce; in1[724]=32'h209eb256; out[724]=32'h6ab0cd34;
in0[725]=32'h3ae6592f; in1[725]=32'hd0c40792; out[725]=32'h5bcb25ce;
in0[726]=32'h3671fe35; in1[726]=32'h7d4d2807; out[726]=32'ha3c73b73;
in0[727]=32'h6e8f629d; in1[727]=32'h47721cad; out[727]=32'hda98d019;
in0[728]=32'h425527f6; in1[728]=32'h251e188c; out[728]=32'h7f24ea88;
in0[729]=32'haefe5814; in1[729]=32'ha3ff5562; out[729]=32'he8885ba8;
in0[730]=32'h5b6c52a8; in1[730]=32'he64d321c; out[730]=32'hf485da60;
in0[731]=32'h0255bf54; in1[731]=32'h9cc835af; out[731]=32'h02da2e6c;
in0[732]=32'h77708c8b; in1[732]=32'hea9e5ef5; out[732]=32'h6e1b8b07;
in0[733]=32'hfae1fe5e; in1[733]=32'h22f8e542; out[733]=32'hbdddaa3c;
in0[734]=32'hb5c7f26b; in1[734]=32'h626325c5; out[734]=32'h7e480357;
in0[735]=32'hfb39148c; in1[735]=32'hf4cb47e8; out[735]=32'h3b7172e0;
in0[736]=32'h7b94f843; in1[736]=32'h5553c887; out[736]=32'h4a3c4355;
in0[737]=32'h7fd29a19; in1[737]=32'hdf534038; out[737]=32'h59b2f578;
in0[738]=32'h8620dda4; in1[738]=32'h0169e6e5; out[738]=32'h0ecb9bb4;
in0[739]=32'h285806fc; in1[739]=32'h610c8a7c; out[739]=32'hce373a10;
in0[740]=32'hbe333c61; in1[740]=32'h42ed5a6c; out[740]=32'h28a492ec;
in0[741]=32'hded9ac0e; in1[741]=32'hd8d5ef7d; out[741]=32'hff9014d6;
in0[742]=32'h73c7d1ca; in1[742]=32'hc7b921b4; out[742]=32'hcb848c08;
in0[743]=32'he1d7ad49; in1[743]=32'hbddb8f99; out[743]=32'h962557a1;
in0[744]=32'h74a9793a; in1[744]=32'hb9752fb1; out[744]=32'h17f0771a;
in0[745]=32'h220ff634; in1[745]=32'h37b8d725; out[745]=32'h75744184;
in0[746]=32'hea79cbec; in1[746]=32'h9df0c356; out[746]=32'h747f4548;
in0[747]=32'h896762fc; in1[747]=32'hdafa21ff; out[747]=32'h73d61504;
in0[748]=32'he869d9a0; in1[748]=32'h416a4f22; out[748]=32'h44774740;
in0[749]=32'hc6f401cf; in1[749]=32'h3c353c5d; out[749]=32'h5aec2c33;
in0[750]=32'h3be1843a; in1[750]=32'hd0408184; out[750]=32'hb26967e8;
in0[751]=32'h6d4e0539; in1[751]=32'h50a8b9a0; out[751]=32'heff174a0;
in0[752]=32'h84b97e74; in1[752]=32'h9abeb48e; out[752]=32'hade5b458;
in0[753]=32'h6f18a5ec; in1[753]=32'he3291fd3; out[753]=32'h64345584;
in0[754]=32'h70a80ccf; in1[754]=32'h300874d4; out[754]=32'ha770676c;
in0[755]=32'h70e7b0ca; in1[755]=32'h691c8a80; out[755]=32'h893d4900;
in0[756]=32'h03754d8e; in1[756]=32'h99172ce4; out[756]=32'h138f7a78;
in0[757]=32'hb00070aa; in1[757]=32'hec60dfa8; out[757]=32'hda2e0590;
in0[758]=32'hb0882116; in1[758]=32'he26d92d5; out[758]=32'h0680134e;
in0[759]=32'h50b2120e; in1[759]=32'habc4e180; out[759]=32'h079f5500;
in0[760]=32'h797ed0d9; in1[760]=32'he6666469; out[760]=32'h8b0e6d01;
in0[761]=32'h01c7c842; in1[761]=32'h926f1856; out[761]=32'hcc81762c;
in0[762]=32'h8edef358; in1[762]=32'h4b249b5c; out[762]=32'h55d5bba0;
in0[763]=32'h7673a8a9; in1[763]=32'hc771a080; out[763]=32'h54d6f480;
in0[764]=32'h4852a3fb; in1[764]=32'h7371ddc2; out[764]=32'h48faf336;
in0[765]=32'h5846b456; in1[765]=32'h3a31aa36; out[765]=32'h93212624;
in0[766]=32'hafaa67d4; in1[766]=32'h4b5f9bc8; out[766]=32'h0daa79a0;
in0[767]=32'h0dbfef5c; in1[767]=32'hb3716244; out[767]=32'h1c38cc70;
in0[768]=32'h6cda3af6; in1[768]=32'h08a0ce5c; out[768]=32'h439f2468;
in0[769]=32'h0442d79f; in1[769]=32'h1366fa20; out[769]=32'h854639e0;
in0[770]=32'hd34713a5; in1[770]=32'h16047b31; out[770]=32'h139f0995;
in0[771]=32'hceb1e054; in1[771]=32'h70b6c0e3; out[771]=32'hebb0ea7c;
in0[772]=32'hf4a4cd59; in1[772]=32'hc0e499f2; out[772]=32'h65c84f22;
in0[773]=32'h9f05d316; in1[773]=32'ha88caebc; out[773]=32'h9dc7f828;
in0[774]=32'h28e105fe; in1[774]=32'h2c7d6c34; out[774]=32'hd1425f98;
in0[775]=32'hd784f726; in1[775]=32'h93817d07; out[775]=32'h2d76500a;
in0[776]=32'h4c214b9e; in1[776]=32'hfa577085; out[776]=32'h1d136916;
in0[777]=32'hbaef164a; in1[777]=32'h37bebb5d; out[777]=32'hff0f26e2;
in0[778]=32'ha19a251b; in1[778]=32'hd4fc42a5; out[778]=32'hc87ee067;
in0[779]=32'hb7f3695f; in1[779]=32'h1d28c52f; out[779]=32'h4f9e7371;
in0[780]=32'he62456e2; in1[780]=32'hc372bdee; out[780]=32'ha091a01c;
in0[781]=32'h037c942e; in1[781]=32'h1a85f375; out[781]=32'h807d6306;
in0[782]=32'hb8527030; in1[782]=32'h9018c157; out[782]=32'h4f185050;
in0[783]=32'hd2cfd45d; in1[783]=32'hcc3ae070; out[783]=32'h4dd048b0;
in0[784]=32'ha6901834; in1[784]=32'h13c7e1c8; out[784]=32'h72449ca0;
in0[785]=32'hfdb87188; in1[785]=32'h48d5a74c; out[785]=32'h5af96c60;
in0[786]=32'he7e70713; in1[786]=32'h494afa79; out[786]=32'haf98e5fb;
in0[787]=32'ha05cc6de; in1[787]=32'h4fe9e5e2; out[787]=32'h11da25fc;
in0[788]=32'hc5a510d0; in1[788]=32'h0e60adee; out[788]=32'hf9d23160;
in0[789]=32'hd32f17b7; in1[789]=32'h7b52eb64; out[789]=32'h3ec8407c;
in0[790]=32'h9bbb131c; in1[790]=32'hf73f47b2; out[790]=32'he2440d78;
in0[791]=32'hfc428160; in1[791]=32'h98cd9b51; out[791]=32'haf400f60;
in0[792]=32'h3d363a31; in1[792]=32'h7a504f4a; out[792]=32'hf6f1f12a;
in0[793]=32'he74cb373; in1[793]=32'h09e893f0; out[793]=32'h8e2b44d0;
in0[794]=32'he411903b; in1[794]=32'hf10f0ba0; out[794]=32'h4aa1ade0;
in0[795]=32'h19cc3dbd; in1[795]=32'ha2e74acf; out[795]=32'h35898dd3;
in0[796]=32'hb379882b; in1[796]=32'hacebbba7; out[796]=32'hbe383d0d;
in0[797]=32'h42035c62; in1[797]=32'h72b030af; out[797]=32'he8fe86fe;
in0[798]=32'hf0869abf; in1[798]=32'h6a8b433e; out[798]=32'h96ce7742;
in0[799]=32'h2f808a99; in1[799]=32'h4cc5586a; out[799]=32'hee9afb5a;
in0[800]=32'h22e37496; in1[800]=32'h9b910e76; out[800]=32'h602df124;
in0[801]=32'hf14018ee; in1[801]=32'h2398e799; out[801]=32'h5d1da83e;
in0[802]=32'h87c6b61a; in1[802]=32'h7a4194d3; out[802]=32'h6aa91f6e;
in0[803]=32'h5e922448; in1[803]=32'hb3216d0f; out[803]=32'hc94ac838;
in0[804]=32'hcef689b5; in1[804]=32'h0f9adbd6; out[804]=32'h5bc6f44e;
in0[805]=32'h2b6f3a06; in1[805]=32'h9808c945; out[805]=32'h69b9599e;
in0[806]=32'haad8fd6f; in1[806]=32'h9b44f677; out[806]=32'h74e27899;
in0[807]=32'h07cbd38d; in1[807]=32'hb9e8e3bb; out[807]=32'h0b418eff;
in0[808]=32'hee8d1192; in1[808]=32'h06c8b07e; out[808]=32'h8b9305dc;
in0[809]=32'h9331da71; in1[809]=32'h0e33cc67; out[809]=32'ha5a3ef77;
in0[810]=32'h48fc6a82; in1[810]=32'hd7c0a2b4; out[810]=32'h1c612768;
in0[811]=32'hb040f69f; in1[811]=32'h45a9eb6f; out[811]=32'hb885e3f1;
in0[812]=32'hdfae8626; in1[812]=32'h40eb4e2c; out[812]=32'h43c0a288;
in0[813]=32'h590b54c7; in1[813]=32'h2ca8f127; out[813]=32'h12214151;
in0[814]=32'hbbd5e2c3; in1[814]=32'hf95b758a; out[814]=32'h48405c1e;
in0[815]=32'hb59400e7; in1[815]=32'h5dd78643; out[815]=32'hab362675;
in0[816]=32'he61f8fb6; in1[816]=32'ha58877da; out[816]=32'h495dfafc;
in0[817]=32'hd148953a; in1[817]=32'he73c2677; out[817]=32'h5e7bf9f6;
in0[818]=32'h22713626; in1[818]=32'hd5516982; out[818]=32'hacb9154c;
in0[819]=32'h0db9b7b2; in1[819]=32'ha079bc61; out[819]=32'ha9675272;
in0[820]=32'had6c96cb; in1[820]=32'hace39dd6; out[820]=32'hab418cb2;
in0[821]=32'h01347f50; in1[821]=32'h48612c2f; out[821]=32'hfbd51fb0;
in0[822]=32'h6f03624d; in1[822]=32'h12fcd0ff; out[822]=32'h82097ab3;
in0[823]=32'h42b2dd3b; in1[823]=32'h52b02b2d; out[823]=32'hc329cc5f;
in0[824]=32'h4e994709; in1[824]=32'hb5f33af9; out[824]=32'hf7b921c1;
in0[825]=32'h96d0a1fd; in1[825]=32'h46ff7537; out[825]=32'h49de6e5b;
in0[826]=32'h56ea80f4; in1[826]=32'h465718a2; out[826]=32'h87687a68;
in0[827]=32'h600688d9; in1[827]=32'h76315ed2; out[827]=32'h6324f002;
in0[828]=32'hdb339f89; in1[828]=32'h02f0f4e9; out[828]=32'h587ac7b1;
in0[829]=32'h031fd187; in1[829]=32'he343d99c; out[829]=32'h6b541d44;
in0[830]=32'h34793c57; in1[830]=32'h79465db3; out[830]=32'h5a7acbd5;
in0[831]=32'h63bf7a71; in1[831]=32'h16b9e6f6; out[831]=32'h13aa2e96;
in0[832]=32'h469dfdfd; in1[832]=32'hacdb76b0; out[832]=32'ha3203bf0;
in0[833]=32'hf59925a7; in1[833]=32'he81e5206; out[833]=32'h91385fea;
in0[834]=32'had739049; in1[834]=32'hf2cea905; out[834]=32'hca40026d;
in0[835]=32'h36efae1b; in1[835]=32'h64495a45; out[835]=32'h43826b47;
in0[836]=32'h238258df; in1[836]=32'h249f7b37; out[836]=32'hd0353ce9;
in0[837]=32'h1cc4ba42; in1[837]=32'hfe959706; out[837]=32'h9ae34b8c;
in0[838]=32'h0fe91ce1; in1[838]=32'h52151a39; out[838]=32'ha84b4819;
in0[839]=32'h30e9bd88; in1[839]=32'h66a69821; out[839]=32'h2cda2e88;
in0[840]=32'ha7a45ee9; in1[840]=32'h422d160a; out[840]=32'h6d88bb1a;
in0[841]=32'h1ea2eeee; in1[841]=32'ha9582e4f; out[841]=32'hfb067f72;
in0[842]=32'h9357886d; in1[842]=32'hdcae50e6; out[842]=32'h215ca1ee;
in0[843]=32'h993c3957; in1[843]=32'hf5bccb34; out[843]=32'h4097a2ac;
in0[844]=32'hb5c4c627; in1[844]=32'h5e72e629; out[844]=32'h75e8c63f;
in0[845]=32'hdd4e0948; in1[845]=32'ha45f4f98; out[845]=32'h0ceabac0;
in0[846]=32'hd57ff30e; in1[846]=32'h35ce6e8b; out[846]=32'h622cfc9a;
in0[847]=32'hba754df0; in1[847]=32'h5e18b749; out[847]=32'h74a9c970;
in0[848]=32'h002c110f; in1[848]=32'h3575c2cb; out[848]=32'h6eb9e4e5;
in0[849]=32'h42f1ec67; in1[849]=32'h301725e2; out[849]=32'h9dfe95ee;
in0[850]=32'h8570223f; in1[850]=32'he2ab824d; out[850]=32'h92334af3;
in0[851]=32'hb08dab1a; in1[851]=32'h6982262b; out[851]=32'h3c65995e;
in0[852]=32'h1ce61f60; in1[852]=32'hb635f9e9; out[852]=32'he0d6ee60;
in0[853]=32'h6166676b; in1[853]=32'h80c4ee72; out[853]=32'h41ab87a6;
in0[854]=32'h60a9faf9; in1[854]=32'hf7b24cd7; out[854]=32'h6565b31f;
in0[855]=32'hf7fc5bd8; in1[855]=32'hddf61c0c; out[855]=32'hf36fee20;
in0[856]=32'h8280d70b; in1[856]=32'h62676aa4; out[856]=32'haf01510c;
in0[857]=32'hbc571b36; in1[857]=32'hee5ce41a; out[857]=32'hb07cdb7c;
in0[858]=32'h4debbae5; in1[858]=32'ha3344c1d; out[858]=32'h94b427f1;
in0[859]=32'h6673942b; in1[859]=32'h0cd9b768; out[859]=32'hda51ee78;
in0[860]=32'h929de9ff; in1[860]=32'h7ba8e6b8; out[860]=32'h56134948;
in0[861]=32'h48e72bc9; in1[861]=32'h02c25c75; out[861]=32'h25b53edd;
in0[862]=32'h5c969b37; in1[862]=32'h9a758feb; out[862]=32'h2517347d;
in0[863]=32'h2b4973bf; in1[863]=32'hecfc9fec; out[863]=32'h8a9e5514;
in0[864]=32'haa214d5f; in1[864]=32'h22c10bd5; out[864]=32'heea7750b;
in0[865]=32'hfac69c8b; in1[865]=32'h8a85d7f4; out[865]=32'h14fcf17c;
in0[866]=32'hbb6d593f; in1[866]=32'hb4333fd7; out[866]=32'h655974e9;
in0[867]=32'h201bdf98; in1[867]=32'hdc6dcd01; out[867]=32'h45e09798;
in0[868]=32'hd9dbb1ae; in1[868]=32'he7fa7b47; out[868]=32'h8038e142;
in0[869]=32'he83f9c2c; in1[869]=32'h861bcd00; out[869]=32'h70b33c00;
in0[870]=32'hdfe7ab14; in1[870]=32'h72a00316; out[870]=32'hc969efb8;
in0[871]=32'h18b9f119; in1[871]=32'h2d2995e1; out[871]=32'hf6c173f9;
in0[872]=32'h290de2a2; in1[872]=32'h1168f552; out[872]=32'h4427a1e4;
in0[873]=32'h6540deed; in1[873]=32'ha0a6bace; out[873]=32'h49d994b6;
in0[874]=32'hd9c933dc; in1[874]=32'h9d47677e; out[874]=32'h72e90a48;
in0[875]=32'hafd53f92; in1[875]=32'h9cb6a46a; out[875]=32'h94d1da74;
in0[876]=32'h9b95ff41; in1[876]=32'h9624304a; out[876]=32'h145bf8ca;
in0[877]=32'h0f9690d2; in1[877]=32'h978b2515; out[877]=32'h8a4e3b3a;
in0[878]=32'h024e4482; in1[878]=32'ha711e8a6; out[878]=32'hc7783c4c;
in0[879]=32'h5ab0c19e; in1[879]=32'h4194d5c3; out[879]=32'h3313f15a;
in0[880]=32'hf10559e8; in1[880]=32'h7982f9e4; out[880]=32'h2d06baa0;
in0[881]=32'hb4bace11; in1[881]=32'h120867fe; out[881]=32'h1cc94bde;
in0[882]=32'ha1192886; in1[882]=32'hef88349c; out[882]=32'he8bfe9a8;
in0[883]=32'hd3da0c6b; in1[883]=32'hdb6fa8a9; out[883]=32'hde7d6aa3;
in0[884]=32'ha542a42c; in1[884]=32'hc744f219; out[884]=32'hf263a04c;
in0[885]=32'h27b54b1d; in1[885]=32'h8d45f01c; out[885]=32'h8610672c;
in0[886]=32'h8c6ca4b1; in1[886]=32'h6fb43912; out[886]=32'h9bc2fd72;
in0[887]=32'h3838a3ae; in1[887]=32'h2ad7068b; out[887]=32'hddb8f37a;
in0[888]=32'h6361d786; in1[888]=32'hd057b4a4; out[888]=32'h94c249d8;
in0[889]=32'h52f576e6; in1[889]=32'h70df5d01; out[889]=32'hb18104e6;
in0[890]=32'h425e7c2a; in1[890]=32'hbfbe4942; out[890]=32'h8aeffcd4;
in0[891]=32'h32ae06a3; in1[891]=32'h6ffb74d0; out[891]=32'h37384070;
in0[892]=32'h1f9299de; in1[892]=32'h9d3beba6; out[892]=32'ha8788ff4;
in0[893]=32'he00034af; in1[893]=32'h60e869f0; out[893]=32'h74652b10;
in0[894]=32'he46090cc; in1[894]=32'h5eca7b95; out[894]=32'h7abe4abc;
in0[895]=32'h6df504dc; in1[895]=32'h10549105; out[895]=32'h45b9b44c;
in0[896]=32'hea69b44c; in1[896]=32'h44cfc6da; out[896]=32'h58ea50b8;
in0[897]=32'hd998f2cf; in1[897]=32'ha331e107; out[897]=32'ha73592a9;
in0[898]=32'h8dee83c7; in1[898]=32'h9db08e22; out[898]=32'hca95e26e;
in0[899]=32'he90b1d77; in1[899]=32'h4f042daf; out[899]=32'h71a30f59;
in0[900]=32'h2d3808e7; in1[900]=32'h875ee752; out[900]=32'h21cd4afe;
in0[901]=32'h512b991e; in1[901]=32'hd1601039; out[901]=32'hb586f7ae;
in0[902]=32'h52555c7b; in1[902]=32'hb7645560; out[902]=32'h44c38520;
in0[903]=32'h9b87db2b; in1[903]=32'hff276316; out[903]=32'h1ffb76b2;
in0[904]=32'h4b6a1102; in1[904]=32'h82d5f871; out[904]=32'h34f571e2;
in0[905]=32'hee9fc019; in1[905]=32'h0f7587f5; out[905]=32'hdf9d06ed;
in0[906]=32'h03d5e1ce; in1[906]=32'hf4584465; out[906]=32'h4a2cce46;
in0[907]=32'h4e13a879; in1[907]=32'h1dc77e41; out[907]=32'h2af854b9;
in0[908]=32'hd6c35404; in1[908]=32'h5b962024; out[908]=32'h44505090;
in0[909]=32'h449712a2; in1[909]=32'h2185b14f; out[909]=32'h2eaac1fe;
in0[910]=32'h620027dc; in1[910]=32'hd82f8e03; out[910]=32'h2d807f94;
in0[911]=32'h5b87389b; in1[911]=32'he02dfe04; out[911]=32'h2b85ac6c;
in0[912]=32'hff7b67e8; in1[912]=32'h03c02cd4; out[912]=32'h6e0dec20;
in0[913]=32'h7922eb46; in1[913]=32'h0afab1f0; out[913]=32'h33c3f7a0;
in0[914]=32'h830ef7de; in1[914]=32'hf587d3eb; out[914]=32'hd11b82ca;
in0[915]=32'h3d7cad14; in1[915]=32'h0224d4d1; out[915]=32'hf0eddd54;
in0[916]=32'h400214f0; in1[916]=32'h7ffc383a; out[916]=32'ha14d3e60;
in0[917]=32'h9cea8cc1; in1[917]=32'h5be30a05; out[917]=32'ha43749c5;
in0[918]=32'h65c3d702; in1[918]=32'h5b8cf6e4; out[918]=32'h1e1f69c8;
in0[919]=32'h586e040f; in1[919]=32'he0cc912a; out[919]=32'h2e4d2976;
in0[920]=32'h0adceb49; in1[920]=32'hae1858fd; out[920]=32'h5a0d9f25;
in0[921]=32'h44fbed33; in1[921]=32'h41b15987; out[921]=32'he993d0e5;
in0[922]=32'ha1361dfb; in1[922]=32'h9fc369fb; out[922]=32'hfd8c5819;
in0[923]=32'hedddf017; in1[923]=32'hf52bc1b9; out[923]=32'h8e40d79f;
in0[924]=32'h6b2ac1d8; in1[924]=32'hbedaa861; out[924]=32'h0c5932d8;
in0[925]=32'ha2538568; in1[925]=32'h89011976; out[925]=32'h27eea5f0;
in0[926]=32'hb38b2c97; in1[926]=32'h22d1d502; out[926]=32'ha876fc2e;
in0[927]=32'h1e8dcda7; in1[927]=32'hbc0865f9; out[927]=32'hbb47ea6f;
in0[928]=32'h62a04d42; in1[928]=32'he3e3e90c; out[928]=32'h8d5ab118;
in0[929]=32'h0a5b33a2; in1[929]=32'h09137d43; out[929]=32'hc51a9d66;
in0[930]=32'hf761404b; in1[930]=32'h1f37f967; out[930]=32'h04c6d12d;
in0[931]=32'h33125917; in1[931]=32'hae27a759; out[931]=32'hedfff9ff;
in0[932]=32'h94591673; in1[932]=32'hbef9009f; out[932]=32'h532ff16d;
in0[933]=32'ha8bcc9ca; in1[933]=32'h95f13469; out[933]=32'h1795cbda;
in0[934]=32'h6d5f8168; in1[934]=32'hf7c01f9e; out[934]=32'h779d7630;
in0[935]=32'h84e791f1; in1[935]=32'hbc85e823; out[935]=32'hd6205bf3;
in0[936]=32'h81136a65; in1[936]=32'hb39ec118; out[936]=32'h065e1e78;
in0[937]=32'h6b98237a; in1[937]=32'he9bbf4c2; out[937]=32'h7f392a74;
in0[938]=32'hfbc88922; in1[938]=32'h585bcdbc; out[938]=32'hec2aeef8;
in0[939]=32'h51aaea89; in1[939]=32'h29ab689f; out[939]=32'hc2f25317;
in0[940]=32'h1e52d098; in1[940]=32'h2897a1a5; out[940]=32'h6a3809f8;
in0[941]=32'h4951ce7a; in1[941]=32'h8892eead; out[941]=32'h2bd1f472;
in0[942]=32'h3a773ceb; in1[942]=32'h686a0506; out[942]=32'h644a0482;
in0[943]=32'h28b26b37; in1[943]=32'ha915122b; out[943]=32'h7c04e03d;
in0[944]=32'hbb62d718; in1[944]=32'hbd9c98ad; out[944]=32'h1c219b38;
in0[945]=32'h0e1b6b25; in1[945]=32'hd6634915; out[945]=32'h571c5709;
in0[946]=32'h8a12f39b; in1[946]=32'h8fe8a50d; out[946]=32'h937145df;
in0[947]=32'hace3497f; in1[947]=32'hc792cbae; out[947]=32'h6131a952;
in0[948]=32'hf1e33f32; in1[948]=32'h5041bdea; out[948]=32'h8b11adb4;
in0[949]=32'hfb13090f; in1[949]=32'hec3582d7; out[949]=32'h3bb13999;
in0[950]=32'h0f0e6582; in1[950]=32'hc8c343c6; out[950]=32'h4bb9888c;
in0[951]=32'hb934822e; in1[951]=32'ha01052e9; out[951]=32'h455d37de;
in0[952]=32'hc9ea3217; in1[952]=32'h9bc9c080; out[952]=32'hdbb94b80;
in0[953]=32'h46dcad91; in1[953]=32'h1ed38538; out[953]=32'h32f54cb8;
in0[954]=32'h822ceb31; in1[954]=32'hfb95f346; out[954]=32'h2a0cd266;
in0[955]=32'ha5c9f9a2; in1[955]=32'hce261c59; out[955]=32'h24918152;
in0[956]=32'he049c89c; in1[956]=32'hfabaec4b; out[956]=32'hd3e595b4;
in0[957]=32'hc18fc20c; in1[957]=32'h0f637478; out[957]=32'h9df465a0;
in0[958]=32'h8d9b3ff9; in1[958]=32'h111a5551; out[958]=32'h62a6eac9;
in0[959]=32'h09c9adb0; in1[959]=32'hf87aba4c; out[959]=32'hb5f17040;
in0[960]=32'h26c959fa; in1[960]=32'hee68e73b; out[960]=32'h9a28529e;
in0[961]=32'h468e3a8f; in1[961]=32'h6ae13517; out[961]=32'h7695ddd9;
in0[962]=32'hfdaa8e92; in1[962]=32'h8b61e5f6; out[962]=32'h9ebf9a4c;
in0[963]=32'hb5a8d252; in1[963]=32'h291d87e1; out[963]=32'ha5941812;
in0[964]=32'h5a75b528; in1[964]=32'h1e436362; out[964]=32'h3f95d150;
in0[965]=32'haf4aca69; in1[965]=32'h9570d177; out[965]=32'h35f3cfcf;
in0[966]=32'h5477dba9; in1[966]=32'h068a4325; out[966]=32'hf2e9fa6d;
in0[967]=32'h49380ddb; in1[967]=32'h291a7e5f; out[967]=32'h3ddcee45;
in0[968]=32'h6311b748; in1[968]=32'hf394b902; out[968]=32'he1367690;
in0[969]=32'h9dca68b1; in1[969]=32'hc286eee4; out[969]=32'ha43fcba4;
in0[970]=32'h4cc0cbc9; in1[970]=32'h4178dbb4; out[970]=32'h751c3c54;
in0[971]=32'h2c44a9e5; in1[971]=32'h81a61118; out[971]=32'h45362278;
in0[972]=32'hf6eb60ca; in1[972]=32'hb323a9dc; out[972]=32'h0eca8798;
in0[973]=32'h64fe0070; in1[973]=32'hec0eb6e7; out[973]=32'hfba20510;
in0[974]=32'h570918e2; in1[974]=32'he740a2f6; out[974]=32'h8afced2c;
in0[975]=32'hf5c0beaa; in1[975]=32'ha3bd4293; out[975]=32'hd0574f9e;
in0[976]=32'hca884cb9; in1[976]=32'hb712fab6; out[976]=32'hbbd53586;
in0[977]=32'h7183f4f5; in1[977]=32'hcb6bd8a3; out[977]=32'h471aafff;
in0[978]=32'h32c090c8; in1[978]=32'he3805d9b; out[978]=32'h6b305118;
in0[979]=32'h27a01739; in1[979]=32'ha85b5cc6; out[979]=32'hd76d7216;
in0[980]=32'hca1ecd06; in1[980]=32'h1f6324cf; out[980]=32'hc70e9fda;
in0[981]=32'h93e0efb0; in1[981]=32'h43c8dc61; out[981]=32'ha7b611b0;
in0[982]=32'h54508e7c; in1[982]=32'h0ce4ea44; out[982]=32'hbe1330f0;
in0[983]=32'h98b644c4; in1[983]=32'h48e914cd; out[983]=32'h3db860f4;
in0[984]=32'h48afee7f; in1[984]=32'h0431950c; out[984]=32'h705e18f4;
in0[985]=32'hcd7fb32e; in1[985]=32'hb53707cc; out[985]=32'h448b0aa8;
in0[986]=32'hed11e356; in1[986]=32'h7399c6de; out[986]=32'hebbda894;
in0[987]=32'hdbf49b9c; in1[987]=32'h38c12e37; out[987]=32'ha61f7684;
in0[988]=32'h7962888e; in1[988]=32'hb46b88fe; out[988]=32'hb3a8ece4;
in0[989]=32'h260a77ed; in1[989]=32'ha4ddc857; out[989]=32'h76d8e98b;
in0[990]=32'hf4b1b206; in1[990]=32'he64ab8d3; out[990]=32'h40260af2;
in0[991]=32'h45b35df2; in1[991]=32'h801d317f; out[991]=32'h8d60ed0e;
in0[992]=32'h67ab1a9e; in1[992]=32'hb324b580; out[992]=32'h07970500;
in0[993]=32'h49845ba5; in1[993]=32'h73ee210b; out[993]=32'h8ae63517;
in0[994]=32'he547b72d; in1[994]=32'hd8ed9d9e; out[994]=32'h0a42a6c6;
in0[995]=32'h2c79afab; in1[995]=32'h30e71b97; out[995]=32'ha49aa6dd;
in0[996]=32'h598abf4b; in1[996]=32'h87a7ad1c; out[996]=32'he55f9b34;
in0[997]=32'hda26caf5; in1[997]=32'hb2840d76; out[997]=32'h8683fdee;
in0[998]=32'h8f6579b8; in1[998]=32'h0c42201d; out[998]=32'hef25c9d8;
in0[999]=32'hfe455497; in1[999]=32'h344d1e55; out[999]=32'haa59c823;
end
//---------------------------------------------------------------------------
// Initial Block
//---------------------------------------------------------------------------
initial begin
// Reset signal
#10 reset = 1'b0;
// Parse Arguments
if ( !$value$plusargs( "nmults=%d", nmults ) ) begin
$display( "No nmults specified! Example: ./simv +nmults=10" ); $finish;
end
if ( !$value$plusargs( "verbose=%d", verbose ) ) begin
verbose = 0;
end
// Set request valid high
src_val = 1'b1;
// Always end simulation after a set time to prevent renegade simulations
// from filling up our drives with a huge VCD file...
#100000000000
$display( "### ERROR: Simulation timed out!!! ###" );
$finish;
end
//---------------------------------------------------------------------------
// Begin Sim Loop
//---------------------------------------------------------------------------
reg busy = 1'b0;
reg [31:0] cycle_count = 32'd0;
always @ ( * ) begin
src_msg_a <= in0[ idx % 1000 ];
src_msg_b <= in1[ idx % 1000 ];
end
//
always @ ( posedge clk ) begin
// Line Trace
//$display( "%d ( %h %h | %h )",
// cycle_count,
// imul.dpath.a_reg, imul.dpath.b_reg,
// imul.dpath.result_reg[31:0] );
// Computation has started
if ( muldivreq_go ) begin
busy <= 1'b1;
end
// Result is ready, display output, increment index.
else if ( muldivresp_go ) begin
// Weird first one fails, second passes... hmm.
//$display( "%h, %d", sink_msg, sink_msg );
//$display( "%h, %d", out[idx], out[idx] );
//$display( "%h, %d", src_msg_a * src_msg_b, src_msg_a * src_msg_b );
//`VC_TEST_EQ( "MulVar", sink_msg, out[ idx ])
//`VC_TEST_EQ( "MulVar", sink_msg, src_msg_a*src_msg_b)
//$display( "%h * %h = %h", src_msg_a, src_msg_b, sink_msg );
`VC_TEST_EQ( "MulVar", sink_msg, out[ idx % 1000 ])
idx = idx + 1;
end
// We've done all the multiplies! Print cycle count and terminate.
if ( idx == nmults ) begin
$display( "Cycle Count = %d", cycle_count );
$finish;
end
// Reset val signal after operands have been accepted
//if ( src_val ) begin
// src_val <= 1'b0;
//end
// If computation has started, start counting cycles. We need to
// count starting the clock edge when new operands are flopped in to
// accurately measure the total clock cycles since the simulation
// terminates before the final clock cycle can be flopped into the register.
if ( muldivreq_go || busy ) begin
cycle_count <= cycle_count + 1;
end
end
endmodule |
module ovl_next_wrapped(
clk,
rst,
enable,
num_cks,
start_event,
test_expr,
prevConfigInvalid,
out
);
parameter num_cks_max = 7;
parameter num_cks_width = 3;
input clk;
input rst;
input enable;
input [num_cks_width-1:0] num_cks;
input start_event;
input test_expr;
input prevConfigInvalid;
output out;
wire [2:0] result_3bit;
wire [2:0] result_3bit_comb;
`ifdef SMV
ovl_next ovl_next (.num_cks_max(7),
.num_cks_width(3),
.clock(clk),
.reset(rst),
.enable(enable),
.num_cks(num_cks),
.start_event(start_event),
.test_expr(test_expr),
.fire(result_3bit),
.fire_comb(result_3bit_comb)
);
`else // !`ifdef SMV
ovl_next #(
.num_cks_max(7),
.num_cks_width(3)
) ovl_next(
.clock(clk),
.reset(rst),
.enable(enable),
.num_cks(num_cks),
.start_event(start_event),
.test_expr(test_expr),
.fire(result_3bit),
.fire_comb(result_3bit_comb)
);
`endif // !`ifdef SMV
assign out = result_3bit_comb[0] & ~prevConfigInvalid;
endmodule |
module tst_bench_top();
//
// wires && regs
//
reg clk;
reg rstn;
wire [31:0] adr;
wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i;
wire we;
wire stb;
wire cyc;
wire ack;
wire inta;
reg [7:0] q, qq;
wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
parameter PRER_LO = 3'b000;
parameter PRER_HI = 3'b001;
parameter CTR = 3'b010;
parameter RXR = 3'b011;
parameter TXR = 3'b011;
parameter CR = 3'b100;
parameter SR = 3'b100;
parameter TXR_R = 3'b101; // undocumented / reserved output
parameter CR_R = 3'b110; // undocumented / reserved output
parameter RD = 1'b1;
parameter WR = 1'b0;
parameter SADR = 7'b0010_000;
//
// Module body
//
// generate clock
always #5 clk = ~clk;
// hookup wishbone master model
wb_master_model #(8, 32) u0 (
.clk(clk),
.rst(rstn),
.adr(adr),
.din(dat_i),
.dout(dat_o),
.cyc(cyc),
.stb(stb),
.we(we),
.sel(),
.ack(ack),
.err(1'b0),
.rty(1'b0)
);
wire stb0 = stb & ~adr[3];
wire stb1 = stb & adr[3];
assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i);
// hookup wishbone_i2c_master core
i2c_master_top i2c_top (
// wishbone interface
.wb_clk_i(clk),
.wb_rst_i(1'b0),
.arst_i(rstn),
.wb_adr_i(adr[2:0]),
.wb_dat_i(dat_o),
.wb_dat_o(dat0_i),
.wb_we_i(we),
.wb_stb_i(stb0),
.wb_cyc_i(cyc),
.wb_ack_o(ack),
.wb_inta_o(inta),
// i2c signals
.scl_pad_i(scl),
.scl_pad_o(scl0_o),
.scl_padoen_o(scl0_oen),
.sda_pad_i(sda),
.sda_pad_o(sda0_o),
.sda_padoen_o(sda0_oen)
),
i2c_top2 (
// wishbone interface
.wb_clk_i(clk),
.wb_rst_i(1'b0),
.arst_i(rstn),
.wb_adr_i(adr[2:0]),
.wb_dat_i(dat_o),
.wb_dat_o(dat1_i),
.wb_we_i(we),
.wb_stb_i(stb1),
.wb_cyc_i(cyc),
.wb_ack_o(ack),
.wb_inta_o(inta),
// i2c signals
.scl_pad_i(scl),
.scl_pad_o(scl1_o),
.scl_padoen_o(scl1_oen),
.sda_pad_i(sda),
.sda_pad_o(sda1_o),
.sda_padoen_o(sda1_oen)
);
// hookup i2c slave model
i2c_slave_model #(SADR) i2c_slave (
.scl(scl),
.sda(sda)
);
// create i2c lines
delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl),
m1_scl (scl1_oen ? 1'bz : scl1_o, scl),
m0_sda (sda0_oen ? 1'bz : sda0_o, sda),
m1_sda (sda1_oen ? 1'bz : sda1_o, sda);
pullup p1(scl); // pullup scl line
pullup p2(sda); // pullup sda line
initial
begin
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",tst_bench_top,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
// force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
$display("\nstatus: %t Testbench started\n\n", $time);
// $dumpfile("bench.vcd");
// $dumpvars(1, tst_bench_top);
// $dumpvars(1, tst_bench_top.i2c_slave);
// initially values
clk = 0;
// reset system
rstn = 1'b1; // negate reset
#2;
rstn = 1'b0; // assert reset
repeat(1) @(posedge clk);
rstn = 1'b1; // negate reset
$display("status: %t done reset", $time);
@(posedge clk);
//
// program core
//
// program internal registers
u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
$display("status: %t programmed registers", $time);
u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
$display("status: %t verified registers", $time);
u0.wb_write(1, CTR, 8'h80); // enable core
$display("status: %t core enabled", $time);
//
// access slave (write)
//
// drive slave address
u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(0, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// send memory address
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave memory address 01", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(0, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// send memory contents
u0.wb_write(1, TXR, 8'ha5); // present data
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write data a5", $time);
while (scl) #1;
force scl= 1'b0;
#100000;
release scl;
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// send memory contents for next memory address (auto_inc)
u0.wb_write(1, TXR, 8'h5a); // present data
u0.wb_write(0, CR, 8'h50); // set command (stop, write)
$display("status: %t write next data 5a, generate 'stop'", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
//
// delay
//
// #100000; // wait for 100us.
// $display("status: %t wait 100us", $time);
//
// access slave (read)
//
// drive slave address
u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
$display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// send memory address
u0.wb_write(1, TXR, 8'h01); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave address 01", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// drive slave address
u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
$display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// check data just received
u0.wb_read(1, RXR, qq);
if(qq !== 8'ha5)
$display("\nERROR: Expected a5, received %x at time %t", qq, $time);
else
$display("status: %t received %x", $time, qq);
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// check data just received
u0.wb_read(1, RXR, qq);
if(qq !== 8'h5a)
$display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
else
$display("status: %t received %x", $time, qq);
// read data from slave
u0.wb_write(1, CR, 8'h20); // set command (read, ack_read)
$display("status: %t read + ack", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// check data just received
u0.wb_read(1, RXR, qq);
$display("status: %t received %x from 3rd read address", $time, qq);
// read data from slave
u0.wb_write(1, CR, 8'h28); // set command (read, nack_read)
$display("status: %t read + nack", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// check data just received
u0.wb_read(1, RXR, qq);
$display("status: %t received %x from 4th read address", $time, qq);
//
// check invalid slave memory address
//
// drive slave address
u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
u0.wb_write(0, CR, 8'h90 ); // set command (start, write)
$display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// send memory address
u0.wb_write(1, TXR, 8'h10); // present slave's memory address
u0.wb_write(0, CR, 8'h10); // set command (write)
$display("status: %t write slave memory address 10", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
// slave should have send NACK
$display("status: %t Check for nack", $time);
if(!q[7])
$display("\nERROR: Expected NACK, received ACK\n");
// read data from slave
u0.wb_write(1, CR, 8'h40); // set command (stop)
$display("status: %t generate 'stop'", $time);
// check tip bit
u0.wb_read(1, SR, q);
while(q[1])
u0.wb_read(1, SR, q); // poll it until it is zero
$display("status: %t tip==0", $time);
#250000; // wait 250us
$display("\n\nstatus: %t Testbench done", $time);
$finish;
end
endmodule |
module delay (in, out);
input in;
output out;
assign out = in;
specify
(in => out) = (600,600);
endspecify
endmodule |
module for actual values.
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0
)
(
input clk,
input rst,
input phy_init_done,
input rd_data_valid,
input [APPDATA_WIDTH-1:0] app_cmp_data,
input [APPDATA_WIDTH-1:0] rd_data_fifo_in,
output reg error,
output reg error_cmp
);
wire [(APPDATA_WIDTH/16)-1:0] byte_err_fall;
reg [(APPDATA_WIDTH/16)-1:0] byte_err_fall_r;
wire [(APPDATA_WIDTH/16)-1:0] byte_err_rise;
reg [(APPDATA_WIDTH/16)-1:0] byte_err_rise_r;
wire [(APPDATA_WIDTH/2)-1:0] cmp_data_fall;
wire [(APPDATA_WIDTH/2)-1:0] cmp_data_rise;
wire [APPDATA_WIDTH-1:0] cmp_data_r;
reg [APPDATA_WIDTH-1:0] cmp_data_r1;
reg cmp_start;
wire [(APPDATA_WIDTH/2)-1:0] data_fall_r;
wire [(APPDATA_WIDTH/2)-1:0] data_rise_r;
reg err_fall;
reg err_rise;
reg error_tmp_r;
wire error_tmp_r1;
wire error_tmp_r2;
wire [APPDATA_WIDTH-1:0] rd_data_r;
wire [APPDATA_WIDTH-1:0] rd_data_r1;
reg [APPDATA_WIDTH-1:0] rd_data_r2;
wire rd_data_valid_r;
reg rd_data_valid_r1;
reg rd_data_valid_r2;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//***************************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
// instantiate discrete flops for better timing
genvar rd_data_i;
generate
for (rd_data_i = 0; rd_data_i < APPDATA_WIDTH;
rd_data_i = rd_data_i + 1) begin: gen_rd_data
FDRSE ff_rd_data
(
.Q (rd_data_r[rd_data_i]),
.C (clk),
.CE (1'b1),
.D (rd_data_fifo_in[rd_data_i]),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_rd_data_r1
(
.Q (rd_data_r1[rd_data_i]),
.C (clk),
.CE (1'b1),
.D (rd_data_r[rd_data_i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
genvar cmp_data_i;
generate
for (cmp_data_i = 0; cmp_data_i < APPDATA_WIDTH;
cmp_data_i = cmp_data_i + 1) begin: gen_cmp_data
FDRSE ff_cmp_data
(
.Q (cmp_data_r[cmp_data_i]),
.C (clk),
.CE (1'b1),
.D (app_cmp_data[cmp_data_i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
assign data_fall_r = rd_data_r2[APPDATA_WIDTH-1:(APPDATA_WIDTH/2)];
assign data_rise_r = rd_data_r2[(APPDATA_WIDTH/2)-1:0];
assign cmp_data_fall = cmp_data_r[APPDATA_WIDTH-1:(APPDATA_WIDTH/2)];
assign cmp_data_rise = cmp_data_r[(APPDATA_WIDTH/2)-1:0];
// Instantiate ff for timing.
FDRSE ff_rd_data_valid_r
(
.Q (rd_data_valid_r),
.C (clk),
.CE (1'b1),
.D (rd_data_valid),
.R (1'b0),
.S (1'b0)
);
always @(posedge clk) begin
if (rst_r1) begin
rd_data_valid_r1 <= 1'd0;
end else begin
rd_data_valid_r1 <= rd_data_valid_r & phy_init_done;
end
end
always @(posedge clk)begin
rd_data_r2 <= rd_data_r1;
cmp_data_r1 <= cmp_data_r;
rd_data_valid_r2 <= rd_data_valid_r1;
end
genvar cmp_i;
generate
for (cmp_i = 0; cmp_i < APPDATA_WIDTH/16; cmp_i = cmp_i + 1) begin: gen_cmp
assign byte_err_fall[cmp_i]
= (rd_data_valid_r2 &&
(data_fall_r[8*(cmp_i+1)-1:8*cmp_i] !=
cmp_data_fall[8*(cmp_i+1)-1:8*cmp_i]));
assign byte_err_rise[cmp_i]
= (rd_data_valid_r2 &&
(data_rise_r[8*(cmp_i+1)-1:8*cmp_i] !=
cmp_data_rise[8*(cmp_i+1)-1:8*cmp_i]));
end
endgenerate
always @(posedge clk) begin
byte_err_rise_r <= byte_err_rise;
byte_err_fall_r <= byte_err_fall;
end
always @(posedge clk)
if (rst_r1) begin
err_rise <= 1'bx;
err_fall <= 1'bx;
cmp_start <= 1'b0;
error_tmp_r <= 1'b0;
end else begin
err_rise <= | byte_err_rise_r;
err_fall <= | byte_err_fall_r;
// start comparing when initialization/calibration complete, and we
// get first valid readback
if (rd_data_valid_r2)
cmp_start <= 1'b1;
if (cmp_start && !error_tmp_r)
error_tmp_r <= err_rise | err_fall;
//synthesis translate_off
if ((err_rise || err_fall) && cmp_start)
$display ("ERROR at time %t" , $time);
//synthesis translate_on
end
// FF inst to force synthesis to infer ff's.
// Done for timing.
FDRSE ff_error_1
(
.Q (error_tmp_r1),
.C (clk),
.CE (1'b1),
.D (error_tmp_r),
.R (1'b0),
.S (1'b0)
);
FDRSE ff_error_2
(
.Q (error_tmp_r2),
.C (clk),
.CE (1'b1),
.D (error_tmp_r1),
.R (1'b0),
.S (1'b0)
);
always @(posedge clk) begin
error <= error_tmp_r2;
error_cmp <= err_rise | err_fall;
end
endmodule |
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 SET = 1'b0;
#80 D = 1'b1;
#100 RESET = 1'b1;
#120 SET = 1'b1;
#140 D = 1'b0;
#160 RESET = 1'b0;
#180 SET = 1'b0;
#200 SET = 1'b1;
#220 RESET = 1'b1;
#240 D = 1'b1;
#260 SET = 1'bx;
#280 RESET = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_hd__udp_dff$NSR dut (.SET(SET), .RESET(RESET), .D(D), .Q(Q), .CLK_N(CLK_N));
endmodule |
module antares_control_unit #(parameter ENABLE_HW_MULT = 1, // Enable multiply instructions
parameter ENABLE_HW_DIV = 1, // Enable div instructions
parameter ENABLE_HW_CLOZ = 1 // Enable CL=/CLZ instructions
)(
input [5:0] opcode, // The instruction opcode
input [5:0] op_function, // For RR-type instruction
input [4:0] op_rs, // For mtc0 and mfc0 instructions
input [4:0] op_rt, // For branch instructions
output [7:0] dp_hazard,
output id_imm_sign_ext, // sign extend the imm16
output id_movn, // MOVN instruction
output id_movz, // MOVZ instruction
output id_llsc, // LL/SC instructions
output id_syscall, // Syscall exception
output id_breakpoint, // Breakpoint exception
output id_reserved, // Reserved instruction exception
output id_mfc0, // Coprocessor 0 instruction
output id_mtc0, // Coprocessor 0 instruction
output id_eret, // Coprocessor 0 instruction
output id_cp1_instruction, // Coprocessor 1 instruction
output id_cp2_instruction, // Coprocessor 2 instruction
output id_cp3_instruction, // Coprocessor 3 instruction
output id_id_exception_source, // Instruction is a potential source of exception
output id_ex_exception_source, // Instruction is a potential source of exception
output id_mem_exception_source, // Instruction is a potential source of exception
output id_trap, // Trap instruction
output id_trap_condition, // Trap condition
output id_gpr_we, // write data from WB stage, to GPR
output id_mem_to_gpr_select, // Select GPR write data: MEM or ALU
output [4:0] id_alu_operation, // ALU function
output [1:0] id_alu_port_a_select, // Shift, jump and link
output [1:0] id_alu_port_b_select, // R-instruction, I-instruction or jump
output [1:0] id_gpr_wa_select, // Select GPR write address
output id_jump, // Jump instruction
output id_branch, // Branch instruction
output id_mem_write, // Write to Memory: 0 = read, 1 = write.
output id_mem_byte, // Read/Write one byte
output id_mem_halfword, // Read/Write halfword (16 bits )
output id_mem_data_sign_ext // Sign extend for byte/halfword memory operations
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] datapath; // all control signals
//--------------------------------------------------------------------------
// Signal Declaration: wires
//--------------------------------------------------------------------------
wire no_mult;
wire no_div;
wire no_clo_clz;
//--------------------------------------------------------------------------
// assigments
//--------------------------------------------------------------------------
assign id_imm_sign_ext = (opcode != `OP_ANDI) & (opcode != `OP_ORI) & (opcode != `OP_XORI);
assign id_movn = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_MOVN);
assign id_movz = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_MOVZ);
assign id_llsc = (opcode == `OP_LL) | (opcode == `OP_SC);
assign id_syscall = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_SYSCALL);
assign id_breakpoint = (opcode == `OP_TYPE_R) & (op_function == `FUNCTION_OP_BREAK);
assign id_mfc0 = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_MFC);
assign id_mtc0 = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_MTC);
assign id_eret = (opcode == `OP_TYPE_CP0) & (op_rs == `RS_OP_ERET) & (op_function == `FUNCTION_OP_ERET);
assign id_cp1_instruction = (opcode == `OP_TYPE_CP1);
assign id_cp2_instruction = (opcode == `OP_TYPE_CP2);
assign id_cp3_instruction = (opcode == `OP_TYPE_CP3);
assign id_reserved = no_mult | no_div | no_clo_clz;
//--------------------------------------------------------------------------
// Check for mult instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_MULT) begin
assign no_mult = 1'b0;
end
else begin
assign no_mult = ((datapath[20:16] == `ALU_OP_MADD) | (datapath[20:16] == `ALU_OP_MADDU) |
(datapath[20:16] == `ALU_OP_MSUB) | (datapath[20:16] == `ALU_OP_MSUBU) |
(datapath[20:16] == `ALU_OP_MULS) | (datapath[20:16] == `ALU_OP_MULU));
end
endgenerate
//--------------------------------------------------------------------------
// Check for div instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_DIV) begin
assign no_div = 1'b0;
end
else begin
assign no_div = ((datapath[20:16] == `ALU_OP_DIV) | (datapath[20:16] == `ALU_OP_DIVU));
end
endgenerate
//--------------------------------------------------------------------------
// Check for CL0/CLZ instructions
//--------------------------------------------------------------------------
generate
if(ENABLE_HW_CLOZ) begin
assign no_clo_clz = 1'b0;
end
else begin
assign no_clo_clz = ((datapath[20:16] == `ALU_OP_CLO) | (datapath[20:16] == `ALU_OP_CLZ));
end
endgenerate
/*
Datapath controls.
All signals are active High.
----------------------------------------------------------------------------
Bit Name Description
----------------------------------------------------------------------------
31 : Wants Rs by ID
30 : Needs Rs by ID
29 : Wants Rt by ID
28 : Needs Rt by ID
27 : Wants Rs by EX
26 : Needs Rs by EX
25 : Wants Rt by EX
24 : Needs Rt by EX
-------------------------------
23 : id_id_exception_source Instruction can cause exception @ ID
22 : id_ex_exception_source Instruction can cause exception @ EX
21 : id_mem_exception_source Instruction can cause exception @ MEM
-------------------------------
20 : id_alu_operation Operation to execute.
19 : .
18 : .
17 : .
16 : .
-------------------------------
15: id_trap Trap instruction
14: id_trap_condition Condition: ALU result = 0 (0), ALU result != 0 (1)
-------------------------------
13 : id_gpr_we Write enable (GPR)
12 : id_mem_to_gpr_select Select data: ALU(0), MEM(1)
-------------------------------
11 : id_alu_port_a_select Select: Rs(0), shamt(1), 0x04(2), 0x10(3)
10 : .
9 : id_alu_port_b_select Select: Rt(0), SImm16(1), PCAdd4(2), ZImm16(3)
8 : .
7 : id_gpr_wa_select Select register: Rd(0), Rt(1), 31(2)
6 : .
-------------------------------
5 : id_jump Jump instruction
4 : id_branch Branch instruction
-------------------------------
3 : id_mem_write Write to data memory
2 : id_mem_byte Enable read/write one byte
1 : id_mem_halfword Enable read/write 2 bytes (16 bits data)
0 : id_mem_data_sign_ext Zero extend data (0) or Sign extend data (1)
----------------------------------------------------------------------------
*/
assign dp_hazard = datapath[31:24];
assign id_id_exception_source = datapath[23];
assign id_ex_exception_source = datapath[22];
assign id_mem_exception_source = datapath[21];
assign id_alu_operation = datapath[20:16];
assign id_trap = datapath[15];
assign id_trap_condition = datapath[14];
assign id_gpr_we = datapath[13];
assign id_mem_to_gpr_select = datapath[12];
assign id_alu_port_a_select = datapath[11:10];
assign id_alu_port_b_select = datapath[9:8];
assign id_gpr_wa_select = datapath[7:6];
assign id_jump = datapath[5];
assign id_branch = datapath[4];
assign id_mem_write = datapath[3];
assign id_mem_byte = datapath[2];
assign id_mem_halfword = datapath[1];
assign id_mem_data_sign_ext = datapath[0];
//--------------------------------------------------------------------------
// set the control signals
//--------------------------------------------------------------------------
always @(*) begin
case(opcode)
`OP_TYPE_R : begin
case (op_function)
`FUNCTION_OP_ADD : begin datapath = `DP_ADD; end
`FUNCTION_OP_ADDU : begin datapath = `DP_ADDU; end
`FUNCTION_OP_AND : begin datapath = `DP_AND; end
`FUNCTION_OP_BREAK : begin datapath = `DP_BREAK; end
`FUNCTION_OP_DIV : begin datapath = `DP_DIV; end
`FUNCTION_OP_DIVU : begin datapath = `DP_DIVU; end
`FUNCTION_OP_JALR : begin datapath = `DP_JALR; end
`FUNCTION_OP_JR : begin datapath = `DP_JR; end
`FUNCTION_OP_MFHI : begin datapath = `DP_MFHI; end
`FUNCTION_OP_MFLO : begin datapath = `DP_MFLO; end
`FUNCTION_OP_MOVN : begin datapath = `DP_MOVN; end
`FUNCTION_OP_MOVZ : begin datapath = `DP_MOVZ; end
`FUNCTION_OP_MTHI : begin datapath = `DP_MTHI; end
`FUNCTION_OP_MTLO : begin datapath = `DP_MTLO; end
`FUNCTION_OP_MULT : begin datapath = `DP_MULT; end
`FUNCTION_OP_MULTU : begin datapath = `DP_MULTU; end
`FUNCTION_OP_NOR : begin datapath = `DP_NOR; end
`FUNCTION_OP_OR : begin datapath = `DP_OR; end
`FUNCTION_OP_SLL : begin datapath = `DP_SLL; end
`FUNCTION_OP_SLLV : begin datapath = `DP_SLLV; end
`FUNCTION_OP_SLT : begin datapath = `DP_SLT; end
`FUNCTION_OP_SLTU : begin datapath = `DP_SLTU; end
`FUNCTION_OP_SRA : begin datapath = `DP_SRA; end
`FUNCTION_OP_SRAV : begin datapath = `DP_SRAV; end
`FUNCTION_OP_SRL : begin datapath = `DP_SRL; end
`FUNCTION_OP_SRLV : begin datapath = `DP_SRLV; end
`FUNCTION_OP_SUB : begin datapath = `DP_SUB; end
`FUNCTION_OP_SUBU : begin datapath = `DP_SUBU; end
`FUNCTION_OP_SYSCALL : begin datapath = `DP_SYSCALL; end
`FUNCTION_OP_TEQ : begin datapath = `DP_TEQ; end
`FUNCTION_OP_TGE : begin datapath = `DP_TGE; end
`FUNCTION_OP_TGEU : begin datapath = `DP_TGEU; end
`FUNCTION_OP_TLT : begin datapath = `DP_TLT; end
`FUNCTION_OP_TLTU : begin datapath = `DP_TLTU; end
`FUNCTION_OP_TNE : begin datapath = `DP_TNE; end
`FUNCTION_OP_XOR : begin datapath = `DP_XOR; end
default : begin datapath = `DP_NONE; end
endcase // case (op_function)
end // case: `OP_TYPE_R
`OP_TYPE_R2 : begin
case (op_function)
`FUNCTION_OP_CLO : begin datapath = `DP_CLO; end
`FUNCTION_OP_CLZ : begin datapath = `DP_CLZ; end
`FUNCTION_OP_MADD : begin datapath = `DP_MADD; end
`FUNCTION_OP_MADDU : begin datapath = `DP_MADDU; end
`FUNCTION_OP_MSUB : begin datapath = `DP_MSUB; end
`FUNCTION_OP_MSUBU : begin datapath = `DP_MSUBU; end
default : begin datapath = `DP_NONE; end
endcase // case (op_function)
end // case: `OP_TYPE_R2
`OP_TYPE_REGIMM : begin
case (op_rt)
`RT_OP_BGEZ : begin datapath = `DP_BGEZ; end
`RT_OP_BGEZAL : begin datapath = `DP_BGEZAL; end
`RT_OP_BLTZ : begin datapath = `DP_BLTZ; end
`RT_OP_BLTZAL : begin datapath = `DP_BLTZAL; end
`RT_OP_TEQI : begin datapath = `DP_TEQI; end
`RT_OP_TGEI : begin datapath = `DP_TGEI; end
`RT_OP_TGEIU : begin datapath = `DP_TGEIU; end
`RT_OP_TLTI : begin datapath = `DP_TLTI; end
`RT_OP_TLTIU : begin datapath = `DP_TLTIU; end
`RT_OP_TNEI : begin datapath = `DP_TNEI; end
default : begin datapath = `DP_NONE; end
endcase // case (op_rt)
end // case: `OP_TYPE_REGIMM
`OP_TYPE_CP0 : begin
case (op_rs)
`RS_OP_MFC : begin datapath = `DP_MFC0; end
`RS_OP_MTC : begin datapath = `DP_MTC0; end
`RS_OP_ERET : begin datapath = `DP_ERET; end
default : begin datapath = `DP_NONE; end
endcase // case (op_rs)
end
`OP_ADDI : begin datapath = `DP_ADDI; end
`OP_ADDIU : begin datapath = `DP_ADDIU; end
`OP_ANDI : begin datapath = `DP_ANDI; end
`OP_BEQ : begin datapath = `DP_BEQ; end
`OP_BGTZ : begin datapath = `DP_BGTZ; end
`OP_BLEZ : begin datapath = `DP_BLEZ; end
`OP_BNE : begin datapath = `DP_BNE; end
`OP_J : begin datapath = `DP_J; end
`OP_JAL : begin datapath = `DP_JAL; end
`OP_LB : begin datapath = `DP_LB; end
`OP_LBU : begin datapath = `DP_LBU; end
`OP_LH : begin datapath = `DP_LH; end
`OP_LHU : begin datapath = `DP_LHU; end
`OP_LL : begin datapath = `DP_LL; end
`OP_LUI : begin datapath = `DP_LUI; end
`OP_LW : begin datapath = `DP_LW; end
`OP_ORI : begin datapath = `DP_ORI; end
`OP_SB : begin datapath = `DP_SB; end
`OP_SC : begin datapath = `DP_SC; end
`OP_SH : begin datapath = `DP_SH; end
`OP_SLTI : begin datapath = `DP_SLTI; end
`OP_SLTIU : begin datapath = `DP_SLTIU; end
`OP_SW : begin datapath = `DP_SW; end
`OP_XORI : begin datapath = `DP_XORI; end
default : begin datapath = `DP_NONE; end
endcase // case (opcode)
end // always @ (*)
endmodule |
module ALU_behav( ADin, BDin, ALU_ctr, Result, Overflow, Carry_in, Carry_out, Zero );
parameter n = 32, Ctr_size = 4;
input Carry_in;
input [Ctr_size-1:0] ALU_ctr;
input [n-1:0] ADin, BDin;
output [n-1:0] Result;
reg [n-1:0] Result, tmp;
output Carry_out, Overflow, Zero;
reg Carry_out, Overflow, Zero;
always @(ALU_ctr or ADin or BDin or Carry_in)
begin
case(ALU_ctr)
`ADD: begin
{Carry_out, Result} = ADin + BDin + Carry_in;
Overflow = ADin[n-1] & BDin[n-1] & ~Result[n-1]
| ~ADin[n-1] & ~BDin[n-1] & Result[n-1];
end
`ADDU: {Overflow, Result} = ADin + BDin + Carry_in;
`SUB: begin
{Carry_out, Result} = ADin - BDin;
Overflow = ADin[n-1] & ~BDin[n-1] & Result[n-1]
| ~ADin[n-1] & BDin[n-1] & ~Result[n-1];
end
`SUBU: {Overflow, Result} = ADin - BDin;
`SLT: begin
{Carry_out, tmp} = ADin - BDin;
Overflow = ADin[n-1] & ~BDin[n-1] & ~tmp[n-1]
| ~ADin[n-1] & BDin[n-1] & tmp[n-1];
$display("\nSLT:- [%d] tmp = %d [%b]; Cout=%b, Ovf=%b; A=%d, B=%d",
$time, tmp, tmp, Carry_out, Overflow, ADin, BDin );
Result = tmp[n-1] ^ Overflow;
$display("\nSLT:+R=%d [%b]", Result, Result );
end
`SLTU: begin
{Carry_out, tmp} = ADin - BDin;
$display("SLTU:- [%d] tmp = %d [%b]; Cout=%b, Ovf=%b; A=%d, B=%d",
$time, tmp, tmp, Carry_out, Overflow, ADin, BDin );
Result = Carry_out;
$display("SLTU:+R=%d [%b]", Result, Result );
end
`OR : Result = ADin | BDin;
`AND: Result = ADin & BDin;
`XOR: Result = ADin ^ BDin;
`NOP: Result = ADin;
`SLL: Result = ADin << BDin;
`SRL: Result = ADin >> BDin;
`SRA: Result = $signed(ADin) >>> BDin;
`BNE: if ((ADin-BDin)!=0)Result =0 ;// Branch if not equal
`NOP: Result= 1'bZ;
endcase
Zero = ~| Result; // Result = 32'b0
end
/* always @ (Result)
begin
$display("%0d\t ADin = %0d BDin = %0d; Result = %0d; Cout = %b Ovfl = %b Zero = %b OP = %b", $time, ADin, BDin, Result, Carry_out, Overflow, Zero, ALU_ctr );
end
*/
endmodule |
module TestALU;
// parameter n = 32, Ctr_size = 4;
// reg [n-1:0] A, B, T;
// wire [n-1:0] R, tt;
// reg Carry_in;
// wire Carry_out, Overflow, Zero;
// reg [Ctr_size-1:0] ALU_ctr;
// integer num;
// ALU_behav ALU( A, B, ALU_ctr, R, Overflow, Carry_in, Carry_out, Zero );
// always @( R or Carry_out or Overflow or Zero )
// begin
// $display("%0d\tA = %0d B = %0d; R = %0d; Cout = %b Ovfl = %b Zero = %b OP = %b n = %d", $time, A, B, R, Carry_out, Overflow, Zero, ALU_ctr, num );
// num = num + 1;
// end
// initial begin
// #0 num = 0; Carry_in = 0;
// #1 A = 101; B = 0; ALU_ctr = `NOP;
// #10 A = 10; B = 10; ALU_ctr = `ADD;
// #10 A = 10; B = 20; ALU_ctr = `ADDU;
// #10 A = 10; B = 20; ALU_ctr = `SLT;
// #10 A = 10; B = 20; ALU_ctr = `SLTU;
// #10 A = 32'hffffffff; B = 1; ALU_ctr = `ADDU;
// #10 A = 10; B = 10; ALU_ctr = `ADDU;
// #10 A = 10; B = 10; ALU_ctr = `SUB;
// #10 A = 1; B = 1; ALU_ctr = `SUBU;
// #10 A = 10; B = 10; ALU_ctr = `SUB;
// #10 A = 10; B = 10; ALU_ctr = `SUBU;
// #10 A = -13; B = -12; ALU_ctr = `SLT;
// #100 $finish;
// end
// endmodule |
module Computer(
inout [WORD_WIDTH-1:0] ADDR_bus_inout,
inout [WORD_WIDTH-1:0] DATA_bus_inout,
input CLK_in,
input RST_in
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SA_WIDTH = DR_WIDTH;
parameter SB_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter FS_WIDTH = 4;
parameter CNTRL_FLAGS_WIDTH = 7;
parameter ULA_FLAG_WIDTH = 4;
parameter CNTRL_WIDTH = DR_WIDTH+SA_WIDTH+SB_WIDTH+FS_WIDTH+CNTRL_FLAGS_WIDTH;
wire [WORD_WIDTH-1:0] INSTR_bus, CONST_bus, DMEM_bus, COUNTER_bus;
wire [CNTRL_WIDTH-1:0] CNTRL_bus;
wire [ULA_FLAG_WIDTH-1:0] ULA_FLAG_bus;
Computer_InstructionMemory IM0(
.INSTR_out(INSTR_bus),
.COUNTER_in(COUNTER_bus)
);
Computer_ControlUnit CU0(
.CONST_bus_out(CONST_bus),
.CNTRL_bus_out(CNTRL_bus),
.COUNTER_bus_out(COUNTER_bus),
.ADDR_bus_in(ADDR_bus_inout),
.INSTR_bus_in(INSTR_bus),
.ULA_FLAG_bus_in(ULA_FLAG_bus),
.CLK(CLK_in),
.RST(RST_in)
);
Computer_Datapath DP0(
.ADDR_bus_out(ADDR_bus_inout),
.DATA_bus_out(DATA_bus_inout),
.FLAG_bus_out(ULA_FLAG_bus),
.CNTRL_bus_in(CNTRL_bus),
.CONST_bus_in(CONST_bus),
.DMEM_bus_in(DMEM_bus),
.CLK(CLK_in),
.RST(RST_in)
);
endmodule |
module sky130_fd_sc_ls__sedfxtp_4 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ls__sedfxtp_4 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule |
module tb_lab4dpath;
// Inputs
reg [9:0] x1;
reg [9:0] x2;
reg [9:0] x3;
// Outputs
wire [9:0] y;
reg clock;
reg[8*100:1] aline;
`define FSIZE 1024
`define LATENCY 2
integer infifo[(`FSIZE-1):0];
integer head,tail;
integer fd;
integer count,status;
integer i_a, i_b, i_c, i_result;
integer o_a, o_b, o_c, o_result;
integer errors;
integer clock_count;
// Instantiate the Unit Under Test (UUT)
lab4dpath uut (
.x1(x1),
.x2(x2),
.x3(x3),
.clk(clock),
.y(y)
);
initial begin
clock = 0;
#100 //reset delay
forever #25 clock = ~clock;
end
initial begin
// Initialize Inputs
x1 = 0;
x2 = 0;
x3 = 0;
head = 0;
tail = 0;
clock_count = 0;
fd = $fopen("multadd_vectors.txt","r");
count = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Add stimulus here
errors = 0;
while ($fgets(aline,fd)) begin
status = $sscanf(aline,"%x %x %x %x",i_a, i_b, i_c, i_result);
@(negedge clock);
x1 = i_a;
x2 = i_b;
x3 = i_c;
infifo[head]=i_a;inc_head;
infifo[head]=i_b;inc_head;
infifo[head]=i_c;inc_head;
infifo[head]=i_result;inc_head;
end //end while
end
task inc_head;
begin
head = head + 1;
if (head == `FSIZE) head = 0;
end
endtask
task inc_tail;
begin
tail = tail + 1;
if (tail == `FSIZE) tail = 0;
end
endtask
always @(negedge clock) begin
clock_count = clock_count + 1;
if (clock_count > `LATENCY+1) begin
o_a = infifo[tail];inc_tail;
o_b = infifo[tail];inc_tail;
o_c = infifo[tail];inc_tail;
o_result = infifo[tail];inc_tail;
if (o_result == y) begin
$display("%d PASS, x1: %x, x2: %x, x3: %x, y: %x\n",count,o_a,o_b,o_c,y);
end else begin
$display("%d FAIL, x1: %x, x2: %x, x3: %x, y (actual): %x, y (expected): %x\n",count,o_a,o_b,o_c,y,o_result);
errors = errors + 1;
end
end //end if
end
endmodule |
module de4_pcie_top(
input OSC_50_BANK2,
input PCIE_PREST_n,
input PCIE_REFCLK_p,
input [3:0] PCIE_RX_p,
output [3:0] PCIE_TX_p,
output [7:0] LED,
output [35:0] GPIO1_D
);
wire [16:0] pcie_reconfig_fromgxb_0_data;
wire [ 3:0] pcie_reconfig_togxb_data;
altgx_reconfig gxreconf0 (
.reconfig_clk(OSC_50_BANK2),
.reconfig_fromgxb(pcie_reconfig_fromgxb_0_data),
.reconfig_togxb(pcie_reconfig_togxb_data)
);
de4_pcie u0 (
.clk_clk (OSC_50_BANK2),
.pcie_pcie_rstn_export (PCIE_PREST_n),
.pcie_refclk_export (PCIE_REFCLK_p),
.pcie_rx_in_rx_datain_0 (PCIE_RX_p[0]),
.pcie_rx_in_rx_datain_1 (PCIE_RX_p[1]),
.pcie_rx_in_rx_datain_2 (PCIE_RX_p[2]),
.pcie_rx_in_rx_datain_3 (PCIE_RX_p[3]),
.pcie_tx_out_tx_dataout_0 (PCIE_TX_p[0]),
.pcie_tx_out_tx_dataout_1 (PCIE_TX_p[1]),
.pcie_tx_out_tx_dataout_2 (PCIE_TX_p[2]),
.pcie_tx_out_tx_dataout_3 (PCIE_TX_p[3]),
.reset_reset_n (1'b1),
.irqflagtap_irqflagtap (GPIO1_D[14]),
.pcie_reconfig_gxbclk_clk (OSC_50_BANK2),
.pcie_reconfig_fromgxb_0_data (pcie_reconfig_fromgxb_0_data),
.pcie_reconfig_togxb_data (pcie_reconfig_togxb_data),
);
endmodule |
module sky130_fd_sc_ms__a2111o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module sky130_fd_sc_lp__inputiso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule |
module sky130_fd_sc_ms__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule |
module mem2serial #(parameter AW = 8)
(
output reg read_clock_enable,
input [47:0] read_data,
input read_empty, // high is input is empty
input reset, // active low
input clock,
input uart_ready,
output reg [7:0] uart_data,
output reg uart_clock_enable);
parameter idle = 0, write_data = 1, wait_write_done = 2,
write_trailer = 3, wait_write_trailer_done = 4;
reg [2:0] state;
reg [7:0] write_pos;
reg [47:0] data;
always @(negedge reset or negedge clock) begin
if (~reset) begin
state <= idle;
uart_clock_enable <= 0;
read_clock_enable <= 0;
write_pos <= 00;
end
else
case (state)
idle: begin
if (~read_empty)
if (read_clock_enable) begin
data <= read_data;
state <= write_data;
read_clock_enable <= 0;
write_pos <= 40;
end else
read_clock_enable <= 1;
else
read_clock_enable <= 0;
end
write_data: begin
if (uart_ready) begin
uart_data[7] <= data[write_pos + 7];
uart_data[6] <= data[write_pos + 6];
uart_data[5] <= data[write_pos + 5];
uart_data[4] <= data[write_pos + 4];
uart_data[3] <= data[write_pos + 3];
uart_data[2] <= data[write_pos + 2];
uart_data[1] <= data[write_pos + 1];
uart_data[0] <= data[write_pos + 0];
uart_clock_enable <= 1;
write_pos <= write_pos - 8;
state <= wait_write_done;
end
end
wait_write_done: begin
if (~uart_ready) begin
uart_clock_enable <= 0;
if (write_pos > 40) begin /* overflow. finished writing */
write_pos <= 0;
state <= write_trailer;
end else
state <= write_data;
end
end
write_trailer: begin
if (uart_ready) begin
if (write_pos == 0) begin
uart_clock_enable <= 1;
uart_data <= 'h0a;
state <= wait_write_trailer_done;
end
else if (write_pos == 1) begin
uart_clock_enable <= 1;
uart_data <= 'h0d;
state <= wait_write_trailer_done;
end
else if (write_pos >= 2) begin
state <= idle;
end
write_pos <= write_pos + 1;
end
end
wait_write_trailer_done: begin
if (~uart_ready) begin
uart_clock_enable <= 0;
state <= write_trailer;
end
end
endcase
end
endmodule |
module sky130_fd_sc_lp__iso1n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
endmodule |
module mult_21_coeff_83443 (
clken,
clock,
dataa,
result);
input clken;
input clock;
input [20:0] dataa;
output [41:0] result;
wire [41:0] sub_wire0;
wire [20:0] sub_wire1 = 21'd83443;
wire [41:0] result = sub_wire0[41:0];
lpm_mult lpm_mult_component (
.clock (clock),
.datab (sub_wire1),
.clken (clken),
.dataa (dataa),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=NO,INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=1",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 21,
lpm_mult_component.lpm_widthb = 21,
lpm_mult_component.lpm_widthp = 42;
endmodule |
module m_port_ultra_tb;
// Inputs
reg CLK100MHZ;
reg CPU_RESETN;
reg BTNC;
reg [32767:0] convexCloud;
// Outputs
wire [4095:0] convexHull1;
wire [4095:0] convexHull2;
wire [4095:0] convexHull3;
wire [4095:0] convexHull4;
wire [4095:0] convexHull5;
wire [4095:0] convexHull6;
wire [4095:0] convexHull7;
wire [4095:0] convexHull8;
wire [8:0] convexHullSize1;
wire [8:0] convexHullSize2;
wire [8:0] convexHullSize3;
wire [8:0] convexHullSize4;
wire [8:0] convexHullSize5;
wire [8:0] convexHullSize6;
wire [8:0] convexHullSize7;
wire [8:0] convexHullSize8;
wire processorDone1;
wire processorDone2;
wire processorDone3;
wire processorDone4;
wire processorDone5;
wire processorDone6;
wire processorDone7;
wire processorDone8;
wire QINIT, QPULSE, QDIVIDE, QCONVEX_HULL, QDISPLAY;
// Parameters
parameter CLK_PERIOD = 20;
// Instantiate the Unit Under Test (UUT)
m_port_ultra UUT(
.clk (CLK100MHZ),
.reset_n (CPU_RESETN),
.ack (BTNC),
.convexCloud (convexCloud),
.convexHull1 (convexHull1),
.convexHull2 (convexHull2),
.convexHull3 (convexHull3),
.convexHull4 (convexHull4),
.convexHull5 (convexHull5),
.convexHull6 (convexHull6),
.convexHull7 (convexHull7),
.convexHull8 (convexHull8),
.convexHullSize1 (convexHullSize1),
.convexHullSize2 (convexHullSize2),
.convexHullSize3 (convexHullSize3),
.convexHullSize4 (convexHullSize4),
.convexHullSize5 (convexHullSize5),
.convexHullSize6 (convexHullSize6),
.convexHullSize7 (convexHullSize7),
.convexHullSize8 (convexHullSize8),
.processorDone1 (processorDone1),
.processorDone2 (processorDone2),
.processorDone3 (processorDone3),
.processorDone4 (processorDone4),
.processorDone5 (processorDone5),
.processorDone6 (processorDone6),
.processorDone7 (processorDone7),
.processorDone8 (processorDone8),
.QINIT (QINIT),
.QPULSE (QPULSE),
.QDIVIDE (QDIVIDE),
.QCONVEX_HULL (QCONVEX_HULL),
.QDISPLAY (QDISPLAY)
);
initial begin : CLOCK_GENERATOR
CLK100MHZ = 0;
forever begin
# (CLK_PERIOD / 2) CLK100MHZ = ~CLK100MHZ;
end
end
integer counter;
initial begin : STIMULUS
// 256 per processor, 64
convexCloud = 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// Wait for global reset to finish
#100;
// Generate a reset
CPU_RESETN = 0; #20;
CPU_RESETN = 1; #20;
BTNC = 0; #20;
BTNC = 1; #20;
BTNC = 0; #20;
// Give a long time for machine to finish
//#8000;
//32000;
#500000;
// Wait for global reset to finish
#100;
end
endmodule |
module pcx_buf_pm_odd(/*AUTOARG*/
// Outputs
arbpc1_pcxdp_grant_pa, arbpc1_pcxdp_q0_hold_pa_l,
arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_qsel1_pa_l,
arbpc1_pcxdp_shift_px, arbpc3_pcxdp_grant_pa,
arbpc3_pcxdp_q0_hold_pa_l, arbpc3_pcxdp_qsel0_pa,
arbpc3_pcxdp_qsel1_pa_l, arbpc3_pcxdp_shift_px,
arbpc4_pcxdp_grant_pa, arbpc4_pcxdp_q0_hold_pa_l,
arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_qsel1_pa_l,
arbpc4_pcxdp_shift_px,
// Inputs
arbpc1_pcxdp_grant_arbbf_pa, arbpc1_pcxdp_q0_hold_arbbf_pa_l,
arbpc1_pcxdp_qsel0_arbbf_pa, arbpc1_pcxdp_qsel1_arbbf_pa_l,
arbpc1_pcxdp_shift_arbbf_px, arbpc3_pcxdp_grant_arbbf_pa,
arbpc3_pcxdp_q0_hold_arbbf_pa_l, arbpc3_pcxdp_qsel0_arbbf_pa,
arbpc3_pcxdp_qsel1_arbbf_pa_l, arbpc3_pcxdp_shift_arbbf_px,
arbpc4_pcxdp_grant_arbbf_pa, arbpc4_pcxdp_q0_hold_arbbf_pa_l,
arbpc4_pcxdp_qsel0_arbbf_pa, arbpc4_pcxdp_qsel1_arbbf_pa_l,
arbpc4_pcxdp_shift_arbbf_px
);
output arbpc1_pcxdp_grant_pa ;
output arbpc1_pcxdp_q0_hold_pa_l ;
output arbpc1_pcxdp_qsel0_pa ;
output arbpc1_pcxdp_qsel1_pa_l ;
output arbpc1_pcxdp_shift_px ;
output arbpc3_pcxdp_grant_pa ;
output arbpc3_pcxdp_q0_hold_pa_l ;
output arbpc3_pcxdp_qsel0_pa ;
output arbpc3_pcxdp_qsel1_pa_l ;
output arbpc3_pcxdp_shift_px ;
output arbpc4_pcxdp_grant_pa ;
output arbpc4_pcxdp_q0_hold_pa_l ;
output arbpc4_pcxdp_qsel0_pa ;
output arbpc4_pcxdp_qsel1_pa_l ;
output arbpc4_pcxdp_shift_px ;
input arbpc1_pcxdp_grant_arbbf_pa;
input arbpc1_pcxdp_q0_hold_arbbf_pa_l;
input arbpc1_pcxdp_qsel0_arbbf_pa;
input arbpc1_pcxdp_qsel1_arbbf_pa_l;
input arbpc1_pcxdp_shift_arbbf_px;
input arbpc3_pcxdp_grant_arbbf_pa;
input arbpc3_pcxdp_q0_hold_arbbf_pa_l;
input arbpc3_pcxdp_qsel0_arbbf_pa;
input arbpc3_pcxdp_qsel1_arbbf_pa_l;
input arbpc3_pcxdp_shift_arbbf_px;
input arbpc4_pcxdp_grant_arbbf_pa;
input arbpc4_pcxdp_q0_hold_arbbf_pa_l;
input arbpc4_pcxdp_qsel0_arbbf_pa;
input arbpc4_pcxdp_qsel1_arbbf_pa_l;
input arbpc4_pcxdp_shift_arbbf_px;
assign arbpc1_pcxdp_grant_pa = arbpc1_pcxdp_grant_arbbf_pa;
assign arbpc1_pcxdp_q0_hold_pa_l = arbpc1_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc1_pcxdp_qsel0_pa = arbpc1_pcxdp_qsel0_arbbf_pa;
assign arbpc1_pcxdp_qsel1_pa_l = arbpc1_pcxdp_qsel1_arbbf_pa_l;
assign arbpc1_pcxdp_shift_px = arbpc1_pcxdp_shift_arbbf_px;
assign arbpc3_pcxdp_grant_pa = arbpc3_pcxdp_grant_arbbf_pa;
assign arbpc3_pcxdp_q0_hold_pa_l = arbpc3_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc3_pcxdp_qsel0_pa = arbpc3_pcxdp_qsel0_arbbf_pa;
assign arbpc3_pcxdp_qsel1_pa_l = arbpc3_pcxdp_qsel1_arbbf_pa_l;
assign arbpc3_pcxdp_shift_px = arbpc3_pcxdp_shift_arbbf_px;
assign arbpc4_pcxdp_grant_pa = arbpc4_pcxdp_grant_arbbf_pa;
assign arbpc4_pcxdp_q0_hold_pa_l = arbpc4_pcxdp_q0_hold_arbbf_pa_l;
assign arbpc4_pcxdp_qsel0_pa = arbpc4_pcxdp_qsel0_arbbf_pa;
assign arbpc4_pcxdp_qsel1_pa_l = arbpc4_pcxdp_qsel1_arbbf_pa_l;
assign arbpc4_pcxdp_shift_px = arbpc4_pcxdp_shift_arbbf_px;
endmodule |
module npu8_top
(
input CLK,
input RESET_X,
input [7:0] ADR,
input WR,
input RD,
output [31:0] RDATA,
input [31:0] WDATA,
output INT
);
wire SOFT_RESET;
wire START;
wire FINISH;
wire [1:0] OP; // 0:ADD 1:MUL 2:RQT
wire [1:0] MSEL_INPUTA_SEL;
wire [1:0] MSEL_INPUTB_SEL;
wire [1:0] MSEL_OUTPUTC_SEL;
wire INV_ASEL;
wire INV_BSEL;
wire [31:0] M0VAL;
wire [9:0] M1POS;
wire [9:0] M1SIZE;
wire [9:0] M2POS;
wire [9:0] M2SIZE;
wire [9:0] M3POS;
wire [9:0] M3SIZE;
wire [31:0] AD_GAIN;
wire [31:0] AD_QPARAM;
wire [31:0] MLC_GAGB;
wire [31:0] MLC_GAOB;
wire [31:0] MLC_GBOA;
wire [31:0] ML1_GAIN;
wire [31:0] ML1_QPARAM;
wire [31:0] ML2_GAIN;
wire [31:0] ML2_QPARAM;
wire [7:0] REQ_MID;
wire [31:0] REQ_GAIN;
wire [7:0] RMAX;
wire [7:0] RMIN;
wire [7:0] M0_RDATA;
wire M1_WR;
wire [9:0] M1_WADR;
wire [9:0] M1_RADR;
wire [7:0] M1_WDATA;
wire [7:0] M1_RDATA;
wire M2_WR;
wire [9:0] M2_WADR;
wire [9:0] M2_RADR;
wire [7:0] M2_WDATA;
wire [7:0] M2_RDATA;
wire M3_WR;
wire [9:0] M3_WADR;
wire [9:0] M3_RADR;
wire [7:0] M3_WDATA;
wire [7:0] M3_RDATA;
wire NPU_EN;
wire [7:0] A_RDATA;
wire [7:0] B_RDATA;
wire LM_EN;
wire [7:0] C_WDATA;
//cpu if
cpu_if cpu_if
(
.CLK(CLK),
.RESET_X(RESET_X),
// CPU
.ADR(ADR),
.RDATA(RDATA),
.RD(RD),
.WR(WR),
.WDATA(WDATA),
.INT(INT),
//REGISTERS
.SOFT_RESET(SOFT_RESET),
.START(START),
.FINISH(FINISH),
.OP(OP), // 0:ADD 1:MUL 2:RQT
.MSEL_INPUTA_SEL(MSEL_INPUTA_SEL),
.MSEL_INPUTB_SEL(MSEL_INPUTB_SEL),
.MSEL_OUTPUTC_SEL(MSEL_OUTPUTC_SEL),
.INV_ASEL(INV_ASEL),
.INV_BSEL(INV_BSEL),
.M0VAL(M0VAL),
.M1POS(M1POS),
.M1SIZE(M1SIZE),
.M2POS(M2POS),
.M2SIZE(M2SIZE),
.M3POS(M3POS),
.M3SIZE(M3SIZE),
.AD_GAIN(AD_GAIN),
.AD_QPARAM(AD_QPARAM),
.MLC_GAGB(MLC_GAGB),
.MLC_GAOB(MLC_GAOB),
.MLC_GBOA(MLC_GBOA),
.ML1_GAIN(ML1_GAIN),
.ML1_QPARAM(ML1_QPARAM),
.ML2_GAIN(ML2_GAIN),
.ML2_QPARAM(ML2_QPARAM),
.REQ_MID(REQ_MID),
.REQ_GAIN(REQ_GAIN),
.RMAX(RMAX),
.RMIN(RMIN)
);
//local memory
M0 m0(.M0VAL(M0VAL), .RDATA(M0_RDATA));
local_mem m1( .CLK(CLK), .WR(M1_WR), .WADR(M1_WADR), .RADR(M1_RADR), .WDATA(M1_WDATA), .RDATA(M1_RDATA));
local_mem m2( .CLK(CLK), .WR(M2_WR), .WADR(M2_WADR), .RADR(M2_RADR), .WDATA(M2_WDATA), .RDATA(M2_RDATA));
local_mem m3( .CLK(CLK), .WR(M3_WR), .WADR(M3_WADR), .RADR(M3_RADR), .WDATA(M3_WDATA), .RDATA(M3_RDATA));
//local memory controller
lmcnt lmcnt
(
.CLK(CLK),
.RESET_X(RESET_X),
.SOFT_RESET(SOFT_RESET),
.START(START),
.FINISH(FINISH),
.MSEL_INPUTA_SEL(MSEL_INPUTA_SEL),
.MSEL_INPUTB_SEL(MSEL_INPUTB_SEL),
.MSEL_OUTPUTC_SEL(MSEL_OUTPUTC_SEL),
.M1POS(M1POS),
.M1SIZE(M1SIZE),
.M2POS(M2POS),
.M3POS(M3POS),
.M0_RDATA(M0_RDATA),
.M1_WR(M1_WR),
.M1_WADR(M1_WADR),
.M1_WDATA(M1_WDATA),
.M1_RADR(M1_RADR),
.M1_RDATA(M1_RDATA),
.M2_WR(M2_WR),
.M2_WADR(M2_WADR),
.M2_WDATA(M2_WDATA),
.M2_RADR(M2_RADR),
.M2_RDATA(M2_RDATA),
.M3_WR(M3_WR),
.M3_WADR(M3_WADR),
.M3_WDATA(M3_WDATA),
.M3_RADR(M3_RADR),
.M3_RDATA(M3_RDATA),
.NPU_EN(NPU_EN),
.A_RDATA(A_RDATA),
.B_RDATA(B_RDATA),
.LM_EN(LM_EN),
.C_WDATA(C_WDATA)
);
//NPU8
npu_core npu_core
(
.CLK(CLK),
.RESET_X(RESET_X),
.SOFT_RESET(SOFT_RESET),
.OP(OP),
.INV_ASEL(INV_ASEL),
.INV_BSEL(INV_BSEL),
.INPUT_EN(NPU_EN),
.A_IN(A_RDATA),
.B_IN(B_RDATA),
.OUTPUT_EN(LM_EN),
.C_OUT(C_WDATA),
.AD_GAIN(AD_GAIN),
.AD_QPARAM(AD_QPARAM),
.MLC_GAGB(MLC_GAGB),
.MLC_GAOB(MLC_GAOB),
.MLC_GBOA(MLC_GBOA),
.ML1_GAIN(ML1_GAIN),
.ML1_QPARAM(ML1_QPARAM),
.ML2_GAIN(ML2_GAIN),
.ML2_QPARAM(ML2_QPARAM),
.REQ_MID(REQ_MID),
.REQ_GAIN(REQ_GAIN),
.RMAX(RMAX),
.RMIN(RMIN)
);
endmodule |
module MAX6682Mean (
(* intersynth_port = "Reset_n_i", src = "../../verilog/max6682mean.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/max6682mean.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/max6682mean.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/max6682mean.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/max6682mean.v:11" *)
output MAX6682CS_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataOut", src = "../../verilog/max6682mean.v:13" *)
input[7:0] SPI_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Write", src = "../../verilog/max6682mean.v:15" *)
output SPI_Write_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_ReadNext", src = "../../verilog/max6682mean.v:17" *)
output SPI_ReadNext_o,
(* intersynth_conntype = "Byte", intersynth_port = "SPI_DataIn", src = "../../verilog/max6682mean.v:19" *)
output[7:0] SPI_Data_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOFull", src = "../../verilog/max6682mean.v:21" *)
input SPI_FIFOFull_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_FIFOEmpty", src = "../../verilog/max6682mean.v:23" *)
input SPI_FIFOEmpty_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_Transmission", src = "../../verilog/max6682mean.v:25" *)
input SPI_Transmission_i,
(* intersynth_conntype = "Word", intersynth_param = "PauseCounterPreset_i", src = "../../verilog/max6682mean.v:27" *)
input[15:0] PauseCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetH_i", src = "../../verilog/max6682mean.v:29" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetL_i", src = "../../verilog/max6682mean.v:31" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/max6682mean.v:33" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/max6682mean.v:35" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPOL", src = "../../verilog/max6682mean.v:37" *)
output SPI_CPOL_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_CPHA", src = "../../verilog/max6682mean.v:39" *)
output SPI_CPHA_o,
(* intersynth_conntype = "Bit", intersynth_port = "SPI_LSBFE", src = "../../verilog/max6682mean.v:41" *)
output SPI_LSBFE_o
);
(* src = "../../verilog/max6682mean.v:303" *)
wire [15:0] \$add$../../verilog/max6682mean.v:303$35_Y ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_add.v:7" *)
wire \$extract$\AddSubCmp_Add_Direct$2146.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_add.v:10" *)
wire \$extract$\AddSubCmp_Add_Direct$2146.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_add.v:9" *)
wire \$extract$\AddSubCmp_Add_Direct$2146.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_add.v:8" *)
wire \$extract$\AddSubCmp_Add_Direct$2146.Zero_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$extract$\AddSubCmp_Greater_Direct$2147.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$extract$\AddSubCmp_Greater_Direct$2147.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$extract$\AddSubCmp_Greater_Direct$2147.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$extract$\AddSubCmp_Greater_Direct$2147.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$extract$\AddSubCmp_Greater_Direct$2147.Zero_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$extract$\Counter32_RV1_Timer$2140.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$extract$\Counter32_RV1_Timer$2140.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$extract$\Counter32_RV1_Timer$2140.Overflow_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$extract$\Counter_RV1_Timer$2139.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$extract$\Counter_RV1_Timer$2139.Overflow_s ;
(* src = "../../../../wordregister/verilog/wordregister_mux.v:30" *)
wire [15:0] \$extract$\WordRegister_Mux_Direct$2143.D_s ;
(* src = "../../../../wordregister/verilog/wordregister_mux.v:29" *)
wire \$extract$\WordRegister_Mux_Direct$2143.Enable_s ;
(* src = "../../verilog/max6682mean.v:283" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/max6682mean.v:281" *)
wire [15:0] Accumulator;
(* src = "../../verilog/max6682mean.v:54" *)
wire [7:0] Byte0;
(* src = "../../verilog/max6682mean.v:55" *)
wire [7:0] Byte1;
(* src = "../../verilog/max6682mean.v:89" *)
wire PauseTimerEnable;
(* src = "../../verilog/max6682mean.v:90" *)
wire PauseTimerOvfl;
(* src = "../../verilog/max6682mean.v:88" *)
wire PauseTimerPreset;
(* src = "../../verilog/spifsm.v:9" *)
wire \SPI_FSM_1.SPI_FSM_Done ;
(* src = "../../verilog/spifsm.v:4" *)
wire \SPI_FSM_1.SPI_FSM_Start ;
(* src = "../../verilog/spifsm.v:24" *)
wire \SPI_FSM_1.SPI_FSM_Wr0 ;
(* src = "../../verilog/spifsm.v:23" *)
wire \SPI_FSM_1.SPI_FSM_Wr1 ;
(* src = "../../verilog/max6682mean.v:95" *)
wire SensorFSM_StoreValue;
(* src = "../../verilog/max6682mean.v:93" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/max6682mean.v:91" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/max6682mean.v:92" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/max6682mean.v:280" *)
wire [15:0] SensorValue;
wire SPIFSM_1_Out6_s;
wire SPIFSM_1_Out7_s;
wire SPIFSM_1_Out8_s;
wire SPIFSM_1_Out9_s;
wire SPIFSM_1_Out10_s;
wire SPIFSM_1_Out11_s;
wire SPIFSM_1_Out12_s;
wire SPIFSM_1_Out13_s;
wire SPIFSM_1_Out14_s;
wire SPIFSM_1_CfgMode_s;
wire SPIFSM_1_CfgClk_s;
wire SPIFSM_1_CfgShift_s;
wire SPIFSM_1_CfgDataIn_s;
wire SPIFSM_1_CfgDataOut_s;
wire SensorFSM_1_Out8_s;
wire SensorFSM_1_Out9_s;
wire SensorFSM_1_CfgMode_s;
wire SensorFSM_1_CfgClk_s;
wire SensorFSM_1_CfgShift_s;
wire SensorFSM_1_CfgDataIn_s;
wire SensorFSM_1_CfgDataOut_s;
AbsDiff \$extract$\AbsDiff$2141 (
.A_i(SensorValue_o),
.B_i(Accumulator),
.D_o(AbsDiffResult)
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_add.v:12" *)
AddSubCmp \$extract$\AddSubCmp_Add_Direct$2146.ThisAddSubCmp (
.A_i(Accumulator),
.AddOrSub_i(1'b0),
.B_i(SensorValue),
.Carry_i(1'b0),
.Carry_o(\$extract$\AddSubCmp_Add_Direct$2146.Carry_s ),
.D_o(\$add$../../verilog/max6682mean.v:303$35_Y ),
.Overflow_o(\$extract$\AddSubCmp_Add_Direct$2146.Overflow_s ),
.Sign_o(\$extract$\AddSubCmp_Add_Direct$2146.Sign_s ),
.Zero_o(\$extract$\AddSubCmp_Add_Direct$2146.Zero_s )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$extract$\AddSubCmp_Greater_Direct$2147.ThisAddSubCmp (
.A_i(AbsDiffResult),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$extract$\AddSubCmp_Greater_Direct$2147.Carry_s ),
.D_o(\$extract$\AddSubCmp_Greater_Direct$2147.D_s ),
.Overflow_o(\$extract$\AddSubCmp_Greater_Direct$2147.Overflow_s ),
.Sign_o(\$extract$\AddSubCmp_Greater_Direct$2147.Sign_s ),
.Zero_o(\$extract$\AddSubCmp_Greater_Direct$2147.Zero_s )
);
(* src = "../../../../byte2wordsel/verilog/byte2wordsel_11msb.v:10" *)
Byte2WordSel \$extract$\Byte2WordSel_11MSB_Direct$2155.DUT (
.H_i(Byte1),
.L_i(Byte0),
.Mask_i(4'b1011),
.Shift_i(4'b0101),
.Y_o(SensorValue)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$extract$\Counter32_RV1_Timer$2140.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$extract$\Counter32_RV1_Timer$2140.DH_s ),
.DL_o(\$extract$\Counter32_RV1_Timer$2140.DL_s ),
.Direction_i(1'b1),
.Enable_i(SensorFSM_TimerEnable),
.Overflow_o(\$extract$\Counter32_RV1_Timer$2140.Overflow_s ),
.PresetValH_i(PeriodCounterPresetH_i),
.PresetValL_i(PeriodCounterPresetL_i),
.Preset_i(SensorFSM_TimerPreset),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(SensorFSM_TimerOvfl)
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$extract$\Counter_RV1_Timer$2139.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$extract$\Counter_RV1_Timer$2139.D_s ),
.Direction_i(1'b1),
.Enable_i(PauseTimerEnable),
.Overflow_o(\$extract$\Counter_RV1_Timer$2139.Overflow_s ),
.PresetVal_i(PauseCounterPreset_i),
.Preset_i(PauseTimerPreset),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(PauseTimerOvfl)
);
WordMuxDual \$extract$\WordMuxDual$2156 (
.A_i(\$add$../../verilog/max6682mean.v:303$35_Y ),
.B_i(SensorValue),
.S_i(SensorFSM_StoreValue),
.Y_o(\$extract$\WordRegister_Mux_Direct$2143.D_s )
);
WordRegister \$extract$\WordRegister$2142 (
.Clk_i(Clk_i),
.D_i(Accumulator),
.Enable_i(CpuIntr_o),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../wordregister/verilog/wordregister_mux.v:35" *)
WordRegister \$extract$\WordRegister_Mux_Direct$2143.ThisWordRegister (
.Clk_i(Clk_i),
.D_i(\$extract$\WordRegister_Mux_Direct$2143.D_s ),
.Enable_i(\$extract$\WordRegister_Mux_Direct$2143.Enable_s ),
.Q_o(Accumulator),
.Reset_n_i(Reset_n_i)
);
SensorFSM SensorFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(PauseTimerOvfl),
.In2_i(\SPI_FSM_1.SPI_FSM_Done ),
.In3_i(SensorFSM_TimerOvfl),
.In4_i(\$extract$\AddSubCmp_Greater_Direct$2147.Carry_s ),
.In5_i(\$extract$\AddSubCmp_Greater_Direct$2147.Zero_s ),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(CpuIntr_o),
.Out1_o(SensorFSM_StoreValue),
.Out2_o(\SPI_FSM_1.SPI_FSM_Start ),
.Out3_o(SensorFSM_TimerEnable),
.Out4_o(SensorFSM_TimerPreset),
.Out5_o(\$extract$\WordRegister_Mux_Direct$2143.Enable_s ),
.Out6_o(PauseTimerEnable),
.Out7_o(PauseTimerPreset),
.Out8_o(SensorFSM_1_Out8_s),
.Out9_o(SensorFSM_1_Out9_s),
.CfgMode_i(SensorFSM_1_CfgMode_s),
.CfgClk_i(SensorFSM_1_CfgClk_s),
.CfgShift_i(SensorFSM_1_CfgShift_s),
.CfgDataIn_i(SensorFSM_1_CfgDataIn_s),
.CfgDataOut_o(SensorFSM_1_CfgDataOut_s)
);
ByteRegister \$techmap\SPI_FSM_1.$extract$\ByteRegister$2144 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\SPI_FSM_1.SPI_FSM_Wr0 ),
.Q_o(Byte0),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\SPI_FSM_1.$extract$\ByteRegister$2145 (
.Clk_i(Clk_i),
.D_i(SPI_Data_i),
.Enable_i(\SPI_FSM_1.SPI_FSM_Wr1 ),
.Q_o(Byte1),
.Reset_n_i(Reset_n_i)
);
SPIFSM SPIFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(\SPI_FSM_1.SPI_FSM_Start ),
.In1_i(SPI_Transmission_i),
.In2_i(1'b0),
.In3_i(1'b0),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\SPI_FSM_1.SPI_FSM_Done ),
.Out1_o(\SPI_FSM_1.SPI_FSM_Wr0 ),
.Out2_o(\SPI_FSM_1.SPI_FSM_Wr1 ),
.Out3_o(SPI_ReadNext_o),
.Out4_o(SPI_Write_o),
.Out5_o(MAX6682CS_n_o),
.Out6_o(SPIFSM_1_Out6_s),
.Out7_o(SPIFSM_1_Out7_s),
.Out8_o(SPIFSM_1_Out8_s),
.Out9_o(SPIFSM_1_Out9_s),
.Out10_o(SPIFSM_1_Out10_s),
.Out11_o(SPIFSM_1_Out11_s),
.Out12_o(SPIFSM_1_Out12_s),
.Out13_o(SPIFSM_1_Out13_s),
.Out14_o(SPIFSM_1_Out14_s),
.CfgMode_i(SPIFSM_1_CfgMode_s),
.CfgClk_i(SPIFSM_1_CfgClk_s),
.CfgShift_i(SPIFSM_1_CfgShift_s),
.CfgDataIn_i(SPIFSM_1_CfgDataIn_s),
.CfgDataOut_o(SPIFSM_1_CfgDataOut_s)
);
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SPIFSM_1_CfgMode_s = 1'b0;
assign SPIFSM_1_CfgClk_s = 1'b0;
assign SPIFSM_1_CfgShift_s = 1'b0;
assign SPIFSM_1_CfgDataIn_s = 1'b0;
assign SensorFSM_1_CfgMode_s = 1'b0;
assign SensorFSM_1_CfgClk_s = 1'b0;
assign SensorFSM_1_CfgShift_s = 1'b0;
assign SensorFSM_1_CfgDataIn_s = 1'b0;
endmodule |
module small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1
)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk)
begin
if (wr_en)
queue[wr_ptr] <= din;
if (rd_en)
dout <=
// synthesis translate_off
#1
// synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth + 'h1;
else if (~wr_en & rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule |
module outputs
reg [2 : 0] first;
wire [3 : 0] count;
wire RDY_clear,
RDY_count,
RDY_deq,
RDY_enq,
RDY_first,
RDY_notEmpty,
RDY_notFull,
notEmpty,
notFull;
// register outPortFIFO_ifc_fifo_almost_full
reg outPortFIFO_ifc_fifo_almost_full;
wire outPortFIFO_ifc_fifo_almost_full$D_IN,
outPortFIFO_ifc_fifo_almost_full$EN;
// register outPortFIFO_ifc_fifo_deq_cnt
reg [63 : 0] outPortFIFO_ifc_fifo_deq_cnt;
wire [63 : 0] outPortFIFO_ifc_fifo_deq_cnt$D_IN;
wire outPortFIFO_ifc_fifo_deq_cnt$EN;
// register outPortFIFO_ifc_fifo_empty
reg outPortFIFO_ifc_fifo_empty;
wire outPortFIFO_ifc_fifo_empty$D_IN, outPortFIFO_ifc_fifo_empty$EN;
// register outPortFIFO_ifc_fifo_enq_cnt
reg [63 : 0] outPortFIFO_ifc_fifo_enq_cnt;
wire [63 : 0] outPortFIFO_ifc_fifo_enq_cnt$D_IN;
wire outPortFIFO_ifc_fifo_enq_cnt$EN;
// register outPortFIFO_ifc_fifo_full
reg outPortFIFO_ifc_fifo_full;
wire outPortFIFO_ifc_fifo_full$D_IN, outPortFIFO_ifc_fifo_full$EN;
// register outPortFIFO_ifc_fifo_head
reg [2 : 0] outPortFIFO_ifc_fifo_head;
wire [2 : 0] outPortFIFO_ifc_fifo_head$D_IN;
wire outPortFIFO_ifc_fifo_head$EN;
// register outPortFIFO_ifc_fifo_mem
reg [2 : 0] outPortFIFO_ifc_fifo_mem;
wire [2 : 0] outPortFIFO_ifc_fifo_mem$D_IN;
wire outPortFIFO_ifc_fifo_mem$EN;
// register outPortFIFO_ifc_fifo_mem_1
reg [2 : 0] outPortFIFO_ifc_fifo_mem_1;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_1$D_IN;
wire outPortFIFO_ifc_fifo_mem_1$EN;
// register outPortFIFO_ifc_fifo_mem_2
reg [2 : 0] outPortFIFO_ifc_fifo_mem_2;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_2$D_IN;
wire outPortFIFO_ifc_fifo_mem_2$EN;
// register outPortFIFO_ifc_fifo_mem_3
reg [2 : 0] outPortFIFO_ifc_fifo_mem_3;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_3$D_IN;
wire outPortFIFO_ifc_fifo_mem_3$EN;
// register outPortFIFO_ifc_fifo_mem_4
reg [2 : 0] outPortFIFO_ifc_fifo_mem_4;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_4$D_IN;
wire outPortFIFO_ifc_fifo_mem_4$EN;
// register outPortFIFO_ifc_fifo_mem_5
reg [2 : 0] outPortFIFO_ifc_fifo_mem_5;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_5$D_IN;
wire outPortFIFO_ifc_fifo_mem_5$EN;
// register outPortFIFO_ifc_fifo_mem_6
reg [2 : 0] outPortFIFO_ifc_fifo_mem_6;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_6$D_IN;
wire outPortFIFO_ifc_fifo_mem_6$EN;
// register outPortFIFO_ifc_fifo_mem_7
reg [2 : 0] outPortFIFO_ifc_fifo_mem_7;
wire [2 : 0] outPortFIFO_ifc_fifo_mem_7$D_IN;
wire outPortFIFO_ifc_fifo_mem_7$EN;
// register outPortFIFO_ifc_fifo_size_cnt
reg [3 : 0] outPortFIFO_ifc_fifo_size_cnt;
wire [3 : 0] outPortFIFO_ifc_fifo_size_cnt$D_IN;
wire outPortFIFO_ifc_fifo_size_cnt$EN;
// register outPortFIFO_ifc_fifo_tail
reg [2 : 0] outPortFIFO_ifc_fifo_tail;
wire [2 : 0] outPortFIFO_ifc_fifo_tail$D_IN;
wire outPortFIFO_ifc_fifo_tail$EN;
// rule scheduling signals
wire WILL_FIRE_RL_outPortFIFO_ifc_fifo_continuousAssert;
// remaining internal signals
wire [63 : 0] x__h1275, x__h2099;
wire [3 : 0] IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d48,
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d47;
wire [2 : 0] outPortFIFO_ifc_fifo_head_PLUS_1___d110,
outPortFIFO_ifc_fifo_tail_PLUS_1___d111;
wire IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d115,
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d33,
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d41,
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d32,
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d40,
IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d23,
IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d31,
outPortFIFO_ifc_fifo_empty_6_EQ_outPortFIFO_if_ETC___d82;
// action method enq
assign RDY_enq = 1'd1 ;
// action method deq
assign RDY_deq = 1'd1 ;
// value method first
always@(outPortFIFO_ifc_fifo_head or
outPortFIFO_ifc_fifo_mem_7 or
outPortFIFO_ifc_fifo_mem or
outPortFIFO_ifc_fifo_mem_1 or
outPortFIFO_ifc_fifo_mem_2 or
outPortFIFO_ifc_fifo_mem_3 or
outPortFIFO_ifc_fifo_mem_4 or
outPortFIFO_ifc_fifo_mem_5 or outPortFIFO_ifc_fifo_mem_6)
begin
case (outPortFIFO_ifc_fifo_head)
3'd0: first = outPortFIFO_ifc_fifo_mem;
3'd1: first = outPortFIFO_ifc_fifo_mem_1;
3'd2: first = outPortFIFO_ifc_fifo_mem_2;
3'd3: first = outPortFIFO_ifc_fifo_mem_3;
3'd4: first = outPortFIFO_ifc_fifo_mem_4;
3'd5: first = outPortFIFO_ifc_fifo_mem_5;
3'd6: first = outPortFIFO_ifc_fifo_mem_6;
3'd7: first = outPortFIFO_ifc_fifo_mem_7;
endcase
end
assign RDY_first = 1'd1 ;
// value method notFull
assign notFull = !outPortFIFO_ifc_fifo_full ;
assign RDY_notFull = 1'd1 ;
// value method notEmpty
assign notEmpty = !outPortFIFO_ifc_fifo_empty ;
assign RDY_notEmpty = 1'd1 ;
// value method count
assign count = outPortFIFO_ifc_fifo_size_cnt ;
assign RDY_count = 1'd1 ;
// action method clear
assign RDY_clear = 1'd1 ;
// rule RL_outPortFIFO_ifc_fifo_continuousAssert
assign WILL_FIRE_RL_outPortFIFO_ifc_fifo_continuousAssert =
outPortFIFO_ifc_fifo_empty &&
outPortFIFO_ifc_fifo_enq_cnt != outPortFIFO_ifc_fifo_deq_cnt ;
// register outPortFIFO_ifc_fifo_almost_full
assign outPortFIFO_ifc_fifo_almost_full$D_IN =
!EN_clear &&
(IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d33 ||
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d115) ;
assign outPortFIFO_ifc_fifo_almost_full$EN = 1'd1 ;
// register outPortFIFO_ifc_fifo_deq_cnt
assign outPortFIFO_ifc_fifo_deq_cnt$D_IN = EN_clear ? 64'd0 : x__h1275 ;
assign outPortFIFO_ifc_fifo_deq_cnt$EN = EN_clear || EN_deq ;
// register outPortFIFO_ifc_fifo_empty
assign outPortFIFO_ifc_fifo_empty$D_IN =
EN_clear ||
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d41 ;
assign outPortFIFO_ifc_fifo_empty$EN = 1'd1 ;
// register outPortFIFO_ifc_fifo_enq_cnt
assign outPortFIFO_ifc_fifo_enq_cnt$D_IN = EN_clear ? 64'd0 : x__h2099 ;
assign outPortFIFO_ifc_fifo_enq_cnt$EN = EN_clear || EN_enq ;
// register outPortFIFO_ifc_fifo_full
assign outPortFIFO_ifc_fifo_full$D_IN =
!EN_clear &&
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d115 ;
assign outPortFIFO_ifc_fifo_full$EN = 1'd1 ;
// register outPortFIFO_ifc_fifo_head
assign outPortFIFO_ifc_fifo_head$D_IN =
EN_clear ? 3'd0 : outPortFIFO_ifc_fifo_head_PLUS_1___d110 ;
assign outPortFIFO_ifc_fifo_head$EN = EN_clear || EN_deq ;
// register outPortFIFO_ifc_fifo_mem
assign outPortFIFO_ifc_fifo_mem$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd0 ;
// register outPortFIFO_ifc_fifo_mem_1
assign outPortFIFO_ifc_fifo_mem_1$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_1$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd1 ;
// register outPortFIFO_ifc_fifo_mem_2
assign outPortFIFO_ifc_fifo_mem_2$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_2$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd2 ;
// register outPortFIFO_ifc_fifo_mem_3
assign outPortFIFO_ifc_fifo_mem_3$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_3$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd3 ;
// register outPortFIFO_ifc_fifo_mem_4
assign outPortFIFO_ifc_fifo_mem_4$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_4$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd4 ;
// register outPortFIFO_ifc_fifo_mem_5
assign outPortFIFO_ifc_fifo_mem_5$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_5$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd5 ;
// register outPortFIFO_ifc_fifo_mem_6
assign outPortFIFO_ifc_fifo_mem_6$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_6$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd6 ;
// register outPortFIFO_ifc_fifo_mem_7
assign outPortFIFO_ifc_fifo_mem_7$D_IN = enq_sendData ;
assign outPortFIFO_ifc_fifo_mem_7$EN =
!EN_clear && EN_enq && outPortFIFO_ifc_fifo_tail == 3'd7 ;
// register outPortFIFO_ifc_fifo_size_cnt
assign outPortFIFO_ifc_fifo_size_cnt$D_IN =
EN_clear ?
4'd0 :
IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d48 ;
assign outPortFIFO_ifc_fifo_size_cnt$EN = 1'd1 ;
// register outPortFIFO_ifc_fifo_tail
assign outPortFIFO_ifc_fifo_tail$D_IN =
EN_clear ? 3'd0 : outPortFIFO_ifc_fifo_tail_PLUS_1___d111 ;
assign outPortFIFO_ifc_fifo_tail$EN = EN_clear || EN_enq ;
// remaining internal signals
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d115 =
(EN_deq && EN_enq) ?
outPortFIFO_ifc_fifo_full :
!EN_deq &&
IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d23 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d33 =
(EN_deq && EN_enq) ?
outPortFIFO_ifc_fifo_almost_full :
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d32 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d41 =
(EN_deq && EN_enq) ?
outPortFIFO_ifc_fifo_empty :
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d40 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_AND_outPort_ETC___d48 =
(EN_deq && EN_enq) ?
outPortFIFO_ifc_fifo_size_cnt :
IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d47 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d32 =
EN_deq ?
outPortFIFO_ifc_fifo_tail == outPortFIFO_ifc_fifo_head :
IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d31 ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d40 =
EN_deq ?
outPortFIFO_ifc_fifo_head_PLUS_1___d110 ==
outPortFIFO_ifc_fifo_tail :
!EN_enq && outPortFIFO_ifc_fifo_empty ;
assign IF_outPortFIFO_ifc_fifo_w_deq_whas_THEN_outPor_ETC___d47 =
EN_deq ?
outPortFIFO_ifc_fifo_size_cnt - 4'd1 :
(EN_enq ?
outPortFIFO_ifc_fifo_size_cnt + 4'd1 :
outPortFIFO_ifc_fifo_size_cnt) ;
assign IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d23 =
EN_enq ?
outPortFIFO_ifc_fifo_tail_PLUS_1___d111 ==
outPortFIFO_ifc_fifo_head :
outPortFIFO_ifc_fifo_full ;
assign IF_outPortFIFO_ifc_fifo_w_enq_whas_THEN_outPor_ETC___d31 =
EN_enq ?
outPortFIFO_ifc_fifo_tail + 3'd2 == outPortFIFO_ifc_fifo_head :
outPortFIFO_ifc_fifo_almost_full ;
assign outPortFIFO_ifc_fifo_empty_6_EQ_outPortFIFO_if_ETC___d82 =
outPortFIFO_ifc_fifo_empty ==
(outPortFIFO_ifc_fifo_head == outPortFIFO_ifc_fifo_tail &&
!outPortFIFO_ifc_fifo_full) ;
assign outPortFIFO_ifc_fifo_head_PLUS_1___d110 =
outPortFIFO_ifc_fifo_head + 3'd1 ;
assign outPortFIFO_ifc_fifo_tail_PLUS_1___d111 =
outPortFIFO_ifc_fifo_tail + 3'd1 ;
assign x__h1275 = outPortFIFO_ifc_fifo_deq_cnt + 64'd1 ;
assign x__h2099 = outPortFIFO_ifc_fifo_enq_cnt + 64'd1 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
outPortFIFO_ifc_fifo_almost_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
outPortFIFO_ifc_fifo_deq_cnt <= `BSV_ASSIGNMENT_DELAY 64'd0;
outPortFIFO_ifc_fifo_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
outPortFIFO_ifc_fifo_enq_cnt <= `BSV_ASSIGNMENT_DELAY 64'd0;
outPortFIFO_ifc_fifo_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
outPortFIFO_ifc_fifo_head <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_1 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_2 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_3 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_4 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_5 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_6 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_mem_7 <= `BSV_ASSIGNMENT_DELAY 3'd0;
outPortFIFO_ifc_fifo_size_cnt <= `BSV_ASSIGNMENT_DELAY 4'd0;
outPortFIFO_ifc_fifo_tail <= `BSV_ASSIGNMENT_DELAY 3'd0;
end
else
begin
if (outPortFIFO_ifc_fifo_almost_full$EN)
outPortFIFO_ifc_fifo_almost_full <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_almost_full$D_IN;
if (outPortFIFO_ifc_fifo_deq_cnt$EN)
outPortFIFO_ifc_fifo_deq_cnt <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_deq_cnt$D_IN;
if (outPortFIFO_ifc_fifo_empty$EN)
outPortFIFO_ifc_fifo_empty <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_empty$D_IN;
if (outPortFIFO_ifc_fifo_enq_cnt$EN)
outPortFIFO_ifc_fifo_enq_cnt <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_enq_cnt$D_IN;
if (outPortFIFO_ifc_fifo_full$EN)
outPortFIFO_ifc_fifo_full <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_full$D_IN;
if (outPortFIFO_ifc_fifo_head$EN)
outPortFIFO_ifc_fifo_head <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_head$D_IN;
if (outPortFIFO_ifc_fifo_mem$EN)
outPortFIFO_ifc_fifo_mem <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem$D_IN;
if (outPortFIFO_ifc_fifo_mem_1$EN)
outPortFIFO_ifc_fifo_mem_1 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_1$D_IN;
if (outPortFIFO_ifc_fifo_mem_2$EN)
outPortFIFO_ifc_fifo_mem_2 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_2$D_IN;
if (outPortFIFO_ifc_fifo_mem_3$EN)
outPortFIFO_ifc_fifo_mem_3 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_3$D_IN;
if (outPortFIFO_ifc_fifo_mem_4$EN)
outPortFIFO_ifc_fifo_mem_4 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_4$D_IN;
if (outPortFIFO_ifc_fifo_mem_5$EN)
outPortFIFO_ifc_fifo_mem_5 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_5$D_IN;
if (outPortFIFO_ifc_fifo_mem_6$EN)
outPortFIFO_ifc_fifo_mem_6 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_6$D_IN;
if (outPortFIFO_ifc_fifo_mem_7$EN)
outPortFIFO_ifc_fifo_mem_7 <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_mem_7$D_IN;
if (outPortFIFO_ifc_fifo_size_cnt$EN)
outPortFIFO_ifc_fifo_size_cnt <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_size_cnt$D_IN;
if (outPortFIFO_ifc_fifo_tail$EN)
outPortFIFO_ifc_fifo_tail <= `BSV_ASSIGNMENT_DELAY
outPortFIFO_ifc_fifo_tail$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
outPortFIFO_ifc_fifo_almost_full = 1'h0;
outPortFIFO_ifc_fifo_deq_cnt = 64'hAAAAAAAAAAAAAAAA;
outPortFIFO_ifc_fifo_empty = 1'h0;
outPortFIFO_ifc_fifo_enq_cnt = 64'hAAAAAAAAAAAAAAAA;
outPortFIFO_ifc_fifo_full = 1'h0;
outPortFIFO_ifc_fifo_head = 3'h2;
outPortFIFO_ifc_fifo_mem = 3'h2;
outPortFIFO_ifc_fifo_mem_1 = 3'h2;
outPortFIFO_ifc_fifo_mem_2 = 3'h2;
outPortFIFO_ifc_fifo_mem_3 = 3'h2;
outPortFIFO_ifc_fifo_mem_4 = 3'h2;
outPortFIFO_ifc_fifo_mem_5 = 3'h2;
outPortFIFO_ifc_fifo_mem_6 = 3'h2;
outPortFIFO_ifc_fifo_mem_7 = 3'h2;
outPortFIFO_ifc_fifo_size_cnt = 4'hA;
outPortFIFO_ifc_fifo_tail = 3'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N)
if (EN_enq && outPortFIFO_ifc_fifo_full)
$display("location of dfifo: ",
"\"RegFIFO.bsv\", line 25, column 33\n");
if (RST_N)
if (EN_enq && outPortFIFO_ifc_fifo_full)
$display("Dynamic assertion failed: \"RegFIFO.bsv\", line 191, column 27\nouch, enqueuing to full FIFO");
if (RST_N) if (EN_enq && outPortFIFO_ifc_fifo_full) $finish(32'd0);
if (RST_N)
if (EN_deq && outPortFIFO_ifc_fifo_empty)
$display("location of dfifo: ",
"\"RegFIFO.bsv\", line 25, column 33\n");
if (RST_N)
if (EN_deq && outPortFIFO_ifc_fifo_empty)
$display("Dynamic assertion failed: \"RegFIFO.bsv\", line 198, column 28\nouch, dequeueing from empty FIFO");
if (RST_N) if (EN_deq && outPortFIFO_ifc_fifo_empty) $finish(32'd0);
if (RST_N)
if (WILL_FIRE_RL_outPortFIFO_ifc_fifo_continuousAssert)
$display("Continuous assertion failed: \"RegFIFO.bsv\", line 167, column 59\nmismatched in enq/deq count");
if (RST_N)
if (WILL_FIRE_RL_outPortFIFO_ifc_fifo_continuousAssert) $finish(32'd0);
if (RST_N)
if (!outPortFIFO_ifc_fifo_empty_6_EQ_outPortFIFO_if_ETC___d82)
$display("Continuous assertion failed: \"RegFIFO.bsv\", line 170, column 45\nerror in empty signals");
if (RST_N)
if (!outPortFIFO_ifc_fifo_empty_6_EQ_outPortFIFO_if_ETC___d82)
$finish(32'd0);
end
// synopsys translate_on
endmodule |
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
LinkFail, r_MAC, WCtrlDataStart, RStatStart,
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
StartTxDone, TxClk, RxClk, SetPauseTimer
);
parameter Tp = 1;
input [31:0] DataIn;
input [7:0] Address;
input Rw;
input [3:0] Cs;
input Clk;
input Reset;
input WCtrlDataStart;
input RStatStart;
input UpdateMIIRX_DATAReg;
input [15:0] Prsd;
output [31:0] DataOut;
reg [31:0] DataOut;
output r_RecSmall;
output r_Pad;
output r_HugEn;
output r_CrcEn;
output r_DlyCrcEn;
output r_FullD;
output r_ExDfrEn;
output r_NoBckof;
output r_LoopBck;
output r_IFG;
output r_Pro;
output r_Iam;
output r_Bro;
output r_NoPre;
output r_TxEn;
output r_RxEn;
output [31:0] r_HASH0;
output [31:0] r_HASH1;
input TxB_IRQ;
input TxE_IRQ;
input RxB_IRQ;
input RxE_IRQ;
input Busy_IRQ;
output [6:0] r_IPGT;
output [6:0] r_IPGR1;
output [6:0] r_IPGR2;
output [15:0] r_MinFL;
output [15:0] r_MaxFL;
output [3:0] r_MaxRet;
output [5:0] r_CollValid;
output r_TxFlow;
output r_RxFlow;
output r_PassAll;
output r_MiiNoPre;
output [7:0] r_ClkDiv;
output r_WCtrlData;
output r_RStat;
output r_ScanStat;
output [4:0] r_RGAD;
output [4:0] r_FIAD;
output [15:0]r_CtrlData;
input NValid_stat;
input Busy_stat;
input LinkFail;
output [47:0]r_MAC;
output [7:0] r_TxBDNum;
output int_o;
output [15:0]r_TxPauseTV;
output r_TxPauseRq;
input RstTxPauseRq;
input TxCtrlEndFrm;
input StartTxDone;
input TxClk;
input RxClk;
input SetPauseTimer;
reg irq_txb;
reg irq_txe;
reg irq_rxb;
reg irq_rxe;
reg irq_busy;
reg irq_txc;
reg irq_rxc;
reg SetTxCIrq_txclk;
reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
reg SetTxCIrq;
reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
reg SetRxCIrq_rxclk;
reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
reg SetRxCIrq;
reg ResetRxCIrq_sync1;
reg ResetRxCIrq_sync2;
reg ResetRxCIrq_sync3;
wire [3:0] Write = Cs & {4{Rw}};
wire Read = (|Cs) & ~Rw;
wire MODER_Sel = (Address == `ETH_MODER_ADR );
wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR );
wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR );
wire IPGT_Sel = (Address == `ETH_IPGT_ADR );
wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR );
wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR );
wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR );
wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR );
wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR );
wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR );
wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR );
wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR );
wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR );
wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR );
wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
wire [2:0] MODER_Wr;
wire [0:0] INT_SOURCE_Wr;
wire [0:0] INT_MASK_Wr;
wire [0:0] IPGT_Wr;
wire [0:0] IPGR1_Wr;
wire [0:0] IPGR2_Wr;
wire [3:0] PACKETLEN_Wr;
wire [2:0] COLLCONF_Wr;
wire [0:0] CTRLMODER_Wr;
wire [1:0] MIIMODER_Wr;
wire [0:0] MIICOMMAND_Wr;
wire [1:0] MIIADDRESS_Wr;
wire [1:0] MIITX_DATA_Wr;
wire MIIRX_DATA_Wr;
wire [3:0] MAC_ADDR0_Wr;
wire [1:0] MAC_ADDR1_Wr;
wire [3:0] HASH0_Wr;
wire [3:0] HASH1_Wr;
wire [2:0] TXCTRL_Wr;
wire [0:0] TX_BD_NUM_Wr;
assign MODER_Wr[0] = Write[0] & MODER_Sel;
assign MODER_Wr[1] = Write[1] & MODER_Sel;
assign MODER_Wr[2] = Write[2] & MODER_Sel;
assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel;
assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel;
assign IPGT_Wr[0] = Write[0] & IPGT_Sel;
assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel;
assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel;
assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel;
assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel;
assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel;
assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel;
assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel;
assign COLLCONF_Wr[1] = 1'b0; // Not used
assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel;
assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel;
assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel;
assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel;
assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel;
assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel;
assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel;
assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel;
assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel;
assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel;
assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel;
assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel;
assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel;
assign HASH0_Wr[0] = Write[0] & HASH0_Sel;
assign HASH0_Wr[1] = Write[1] & HASH0_Sel;
assign HASH0_Wr[2] = Write[2] & HASH0_Sel;
assign HASH0_Wr[3] = Write[3] & HASH0_Sel;
assign HASH1_Wr[0] = Write[0] & HASH1_Sel;
assign HASH1_Wr[1] = Write[1] & HASH1_Sel;
assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
wire [31:0] MODEROut;
wire [31:0] INT_SOURCEOut;
wire [31:0] INT_MASKOut;
wire [31:0] IPGTOut;
wire [31:0] IPGR1Out;
wire [31:0] IPGR2Out;
wire [31:0] PACKETLENOut;
wire [31:0] COLLCONFOut;
wire [31:0] CTRLMODEROut;
wire [31:0] MIIMODEROut;
wire [31:0] MIICOMMANDOut;
wire [31:0] MIIADDRESSOut;
wire [31:0] MIITX_DATAOut;
wire [31:0] MIIRX_DATAOut;
wire [31:0] MIISTATUSOut;
wire [31:0] MAC_ADDR0Out;
wire [31:0] MAC_ADDR1Out;
wire [31:0] TX_BD_NUMOut;
wire [31:0] HASH0Out;
wire [31:0] HASH1Out;
wire [31:0] TXCTRLOut;
// MODER Register
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
(
.DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
.Write (MODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
(
.DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
.Write (MODER_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
(
.DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
.DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
.Write (MODER_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
// INT_MASK Register
eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
(
.DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
.Write (INT_MASK_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
// IPGT Register
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
(
.DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
.DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
.Write (IPGT_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
// IPGR1 Register
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
(
.DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
.Write (IPGR1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
// IPGR2 Register
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
(
.DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
.Write (IPGR2_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
// PACKETLEN Register
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
.Write (PACKETLEN_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
.Write (PACKETLEN_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
.Write (PACKETLEN_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
(
.DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
.Write (PACKETLEN_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// COLLCONF Register
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
(
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
.Write (COLLCONF_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
(
.DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
.Write (COLLCONF_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
// TX_BD_NUM Register
eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
(
.DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
.Write (TX_BD_NUM_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
// CTRLMODER Register
eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
(
.DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
.Write (CTRLMODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
// MIIMODER Register
eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
.Write (MIIMODER_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
(
.DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
.Write (MIIMODER_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
// MIICOMMAND Register
eth_register #(1, 0) MIICOMMAND0
(
.DataIn (DataIn[0]),
.DataOut (MIICOMMANDOut[0]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(1, 0) MIICOMMAND1
(
.DataIn (DataIn[1]),
.DataOut (MIICOMMANDOut[1]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RStatStart)
);
eth_register #(1, 0) MIICOMMAND2
(
.DataIn (DataIn[2]),
.DataOut (MIICOMMANDOut[2]),
.Write (MIICOMMAND_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (WCtrlDataStart)
);
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
// MIIADDRESSRegister
eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
(
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
.Write (MIIADDRESS_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
(
.DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
.Write (MIIADDRESS_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
// MIITX_DATA Register
eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
.Write (MIITX_DATA_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
(
.DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
.Write (MIITX_DATA_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
// MIIRX_DATA Register
eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
(
.DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
.Write (MIIRX_DATA_Wr), // not written from WB
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
// MAC_ADDR0 Register
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
.Write (MAC_ADDR0_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
.Write (MAC_ADDR0_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
.Write (MAC_ADDR0_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
(
.DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
.Write (MAC_ADDR0_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// MAC_ADDR1 Register
eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
.Write (MAC_ADDR1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
(
.DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
.Write (MAC_ADDR1_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
// RXHASH0 Register
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
.Write (HASH0_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
.Write (HASH0_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
.Write (HASH0_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
(
.DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
.Write (HASH0_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// RXHASH1 Register
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
.Write (HASH1_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
.Write (HASH1_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
.Write (HASH1_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
(
.DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
.Write (HASH1_Wr[3]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
// TXCTRL Register
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
.Write (TXCTRL_Wr[0]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
.Write (TXCTRL_Wr[1]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (1'b0)
);
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
(
.DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
.Write (TXCTRL_Wr[2]),
.Clk (Clk),
.Reset (Reset),
.SyncReset (RstTxPauseRq)
);
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
// Reading data from registers
always @ (Address or Read or MODEROut or INT_SOURCEOut or
INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
HASH0Out or HASH1Out or TXCTRLOut
)
begin
if(Read) // read
begin
case(Address)
`ETH_MODER_ADR : DataOut<=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
`ETH_IPGT_ADR : DataOut<=IPGTOut;
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut<=HASH0Out;
`ETH_HASH1_ADR : DataOut<=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
default: DataOut<=32'h0;
endcase
end
else
DataOut<=32'h0;
end
assign r_RecSmall = MODEROut[16];
assign r_Pad = MODEROut[15];
assign r_HugEn = MODEROut[14];
assign r_CrcEn = MODEROut[13];
assign r_DlyCrcEn = MODEROut[12];
// assign r_Rst = MODEROut[11]; This signal is not used any more
assign r_FullD = MODEROut[10];
assign r_ExDfrEn = MODEROut[9];
assign r_NoBckof = MODEROut[8];
assign r_LoopBck = MODEROut[7];
assign r_IFG = MODEROut[6];
assign r_Pro = MODEROut[5];
assign r_Iam = MODEROut[4];
assign r_Bro = MODEROut[3];
assign r_NoPre = MODEROut[2];
assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
assign r_IPGT[6:0] = IPGTOut[6:0];
assign r_IPGR1[6:0] = IPGR1Out[6:0];
assign r_IPGR2[6:0] = IPGR2Out[6:0];
assign r_MinFL[15:0] = PACKETLENOut[31:16];
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
assign r_CollValid[5:0] = COLLCONFOut[5:0];
assign r_TxFlow = CTRLMODEROut[2];
assign r_RxFlow = CTRLMODEROut[1];
assign r_PassAll = CTRLMODEROut[0];
assign r_MiiNoPre = MIIMODEROut[8];
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
assign r_WCtrlData = MIICOMMANDOut[2];
assign r_RStat = MIICOMMANDOut[1];
assign r_ScanStat = MIICOMMANDOut[0];
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
assign MIISTATUSOut[2] = NValid_stat ;
assign MIISTATUSOut[1] = Busy_stat ;
assign MIISTATUSOut[0] = LinkFail ;
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
assign r_HASH1[31:0] = HASH1Out;
assign r_HASH0[31:0] = HASH0Out;
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
assign r_TxPauseRq = TXCTRLOut[16];
// Synchronizing TxC Interrupt
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
SetTxCIrq_txclk <=#Tp 1'b0;
else
if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
SetTxCIrq_txclk <=#Tp 1'b1;
else
if(ResetTxCIrq_sync2)
SetTxCIrq_txclk <=#Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync1 <=#Tp 1'b0;
else
SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync2 <=#Tp 1'b0;
else
SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq_sync3 <=#Tp 1'b0;
else
SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetTxCIrq <=#Tp 1'b0;
else
SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
end
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
ResetTxCIrq_sync1 <=#Tp 1'b0;
else
ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
end
always @ (posedge TxClk or posedge Reset)
begin
if(Reset)
ResetTxCIrq_sync2 <=#Tp 1'b0;
else
ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
end
// Synchronizing RxC Interrupt
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
SetRxCIrq_rxclk <=#Tp 1'b0;
else
if(SetPauseTimer & r_RxFlow)
SetRxCIrq_rxclk <=#Tp 1'b1;
else
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
SetRxCIrq_rxclk <=#Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync1 <=#Tp 1'b0;
else
SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync2 <=#Tp 1'b0;
else
SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq_sync3 <=#Tp 1'b0;
else
SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
SetRxCIrq <=#Tp 1'b0;
else
SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync1 <=#Tp 1'b0;
else
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync2 <=#Tp 1'b0;
else
ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
end
always @ (posedge RxClk or posedge Reset)
begin
if(Reset)
ResetRxCIrq_sync3 <=#Tp 1'b0;
else
ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
end
// Interrupt generation
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txb <= 1'b0;
else
if(TxB_IRQ)
irq_txb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[0])
irq_txb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txe <= 1'b0;
else
if(TxE_IRQ)
irq_txe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[1])
irq_txe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxb <= 1'b0;
else
if(RxB_IRQ)
irq_rxb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[2])
irq_rxb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxe <= 1'b0;
else
if(RxE_IRQ)
irq_rxe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[3])
irq_rxe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_busy <= 1'b0;
else
if(Busy_IRQ)
irq_busy <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[4])
irq_busy <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txc <= 1'b0;
else
if(SetTxCIrq)
irq_txc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[5])
irq_txc <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxc <= 1'b0;
else
if(SetRxCIrq)
irq_rxc <= #Tp 1'b1;
else
if(INT_SOURCE_Wr[0] & DataIn[6])
irq_rxc <= #Tp 1'b0;
end
// Generating interrupt signal
assign int_o = irq_txb & INT_MASKOut[0] |
irq_txe & INT_MASKOut[1] |
irq_rxb & INT_MASKOut[2] |
irq_rxe & INT_MASKOut[3] |
irq_busy & INT_MASKOut[4] |
irq_txc & INT_MASKOut[5] |
irq_rxc & INT_MASKOut[6] ;
// For reading interrupt status
assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
endmodule |
module OBUFDS_GTE4 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter [4:0] REFCLK_ICNTL_TX = 5'b00000
)(
output O,
output OB,
input CEB,
input I
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTE4";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTE4_dr.v"
`else
reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
reg [4:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
reg glblGTS = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
tri0 glblGTS = glbl.GTS;
`endif
// wire CEB_in;
// wire I_in;
// assign CEB_in = (CEB !== 1'bz) && CEB; // rv 0
// assign I_in = I;
// =====================
// Generate O
// =====================
assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I;
assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I;
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule |
module sky130_fd_sc_lp__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule |
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__probec_p dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule |
module top
(
input CLK_P,
input CLK_N,
input RST_X_IN,
output TXD,
input RXD,
output reg [7:0] LED
);
//Active Low SW
wire clk;
wire reset_x;
wire [`ADDR_LEN-1:0] pc;
wire [4*`INSN_LEN-1:0] idata;
wire [8:0] imem_addr;
wire [`DATA_LEN-1:0] dmem_data;
wire [`DATA_LEN-1:0] dmem_wdata;
wire [`ADDR_LEN-1:0] dmem_addr;
wire dmem_we;
wire [`DATA_LEN-1:0] dmem_wdata_core;
wire [`ADDR_LEN-1:0] dmem_addr_core;
wire dmem_we_core;
wire utx_we;
wire finish_we;
reg finished;
wire ready_tx;
wire loaded;
reg prog_loading;
wire [4*`INSN_LEN-1:0] prog_loaddata;
wire [`ADDR_LEN-1:0] prog_loadaddr;
wire prog_dmem_we;
wire prog_imem_we;
assign utx_we = (~finished && dmem_we_core && (dmem_addr_core == 32'h0)) ? 1'b1 : 1'b0;
assign finish_we = (dmem_we_core && (dmem_addr_core == 32'h8)) ? 1'b1 : 1'b0;
always @ (posedge clk) begin
if (!reset_x) begin
LED <= 0;
end else if (utx_we) begin
LED <= {LED[7], dmem_wdata[6:0]};
end else if (finish_we) begin
LED <= {1'b1, LED[6:0]};
end
end
always @ (posedge clk) begin
if (!reset_x) begin
prog_loading <= 1'b1;
end else begin
prog_loading <= ~loaded;
end
end
always @ (posedge clk) begin
if (!reset_x) begin
finished <= 0;
end else if (finish_we) begin
finished <= 1;
end
end
GEN_MMCM_DS genmmcmds
(
.CLK_P(CLK_P),
.CLK_N(CLK_N),
.RST_X_I(~RST_X_IN),
.CLK_O(clk),
.RST_X_O(reset_x)
);
pipeline pipe
(
.clk(clk),
.reset(~reset_x | prog_loading),
.pc(pc),
.idata(idata),
.dmem_wdata(dmem_wdata_core),
.dmem_addr(dmem_addr_core),
.dmem_we(dmem_we_core),
.dmem_data(dmem_data)
);
assign dmem_addr = prog_loading ? prog_loadaddr : dmem_addr_core;
assign dmem_we = prog_loading ? prog_dmem_we : dmem_we_core;
assign dmem_wdata = prog_loading ? prog_loaddata[127:96] : dmem_wdata_core;
dmem datamemory(
.clk(clk),
.addr({2'b0, dmem_addr[`ADDR_LEN-1:2]}),
.wdata(dmem_wdata),
.we(dmem_we),
.rdata(dmem_data)
);
assign imem_addr = prog_loading ? prog_loadaddr[12:4] : pc[12:4];
imem_ld instmemory(
.clk(~clk),
.addr(imem_addr),
.rdata(idata),
.wdata(prog_loaddata),
.we(prog_imem_we)
);
SingleUartTx sutx
(
.CLK(clk),
.RST_X(reset_x),
.TXD(TXD),
.ERR(),
.DT01(dmem_wdata[7:0]),
.WE01(utx_we)
);
PLOADER loader
(
.CLK(clk),
.RST_X(reset_x),
.RXD(RXD),
.ADDR(prog_loadaddr),
.DATA(prog_loaddata),
.WE_32(prog_dmem_we),
.WE_128(prog_imem_we),
.DONE(loaded)
);
endmodule |
module galois_lfsr
(
input clk,
input calib_done,
input [`NUM_USER_INPUTS-1:0] buf_inputs,
output reg [`WORD_BITS-1:0] rnd
);
initial begin
// Input to LFSR can't be 0
rnd = 1;
end
reg [`WORD_BITS-1:0] counter = 0;
reg [`NUM_USER_INPUTS-1:0] prev_inputs = 0;
reg prev_calib_done = 0;
always @ (posedge clk) begin
counter <= counter + 1;
prev_calib_done <= calib_done;
prev_inputs <= buf_inputs;
if ((calib_done && !prev_calib_done)
|| buf_inputs != prev_inputs) begin
// Seed output by XORing with counter
rnd <= rnd ^ counter;
counter <= 0;
end else begin
// Increment LFSR
rnd[`WORD_BITS-1] <= rnd[0];
rnd[`WORD_BITS-2] <= rnd[`WORD_BITS-1];
rnd[`WORD_BITS-3] <= rnd[`WORD_BITS-2] ^ rnd[0];
rnd[`WORD_BITS-4] <= rnd[`WORD_BITS-3] ^ rnd[0];
rnd[`WORD_BITS-5] <= rnd[`WORD_BITS-4];
rnd[`WORD_BITS-6] <= rnd[`WORD_BITS-5] ^ rnd[0];
rnd[`WORD_BITS-7:0] <= rnd[`WORD_BITS-6:1];
end
end
endmodule |
module dcache_pmem_mux
(
// Inputs
input clk_i
,input rst_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
,input select_i
,input [ 3:0] inport0_wr_i
,input inport0_rd_i
,input [ 7:0] inport0_len_i
,input [ 31:0] inport0_addr_i
,input [ 31:0] inport0_write_data_i
,input [ 3:0] inport1_wr_i
,input inport1_rd_i
,input [ 7:0] inport1_len_i
,input [ 31:0] inport1_addr_i
,input [ 31:0] inport1_write_data_i
// Outputs
,output [ 3:0] outport_wr_o
,output outport_rd_o
,output [ 7:0] outport_len_o
,output [ 31:0] outport_addr_o
,output [ 31:0] outport_write_data_o
,output inport0_accept_o
,output inport0_ack_o
,output inport0_error_o
,output [ 31:0] inport0_read_data_o
,output inport1_accept_o
,output inport1_ack_o
,output inport1_error_o
,output [ 31:0] inport1_read_data_o
);
//-----------------------------------------------------------------
// Output Mux
//-----------------------------------------------------------------
reg [ 3:0] outport_wr_r;
reg outport_rd_r;
reg [ 7:0] outport_len_r;
reg [ 31:0] outport_addr_r;
reg [ 31:0] outport_write_data_r;
reg select_q;
always @ *
begin
case (select_i)
1'd1:
begin
outport_wr_r = inport1_wr_i;
outport_rd_r = inport1_rd_i;
outport_len_r = inport1_len_i;
outport_addr_r = inport1_addr_i;
outport_write_data_r = inport1_write_data_i;
end
default:
begin
outport_wr_r = inport0_wr_i;
outport_rd_r = inport0_rd_i;
outport_len_r = inport0_len_i;
outport_addr_r = inport0_addr_i;
outport_write_data_r = inport0_write_data_i;
end
endcase
end
assign outport_wr_o = outport_wr_r;
assign outport_rd_o = outport_rd_r;
assign outport_len_o = outport_len_r;
assign outport_addr_o = outport_addr_r;
assign outport_write_data_o = outport_write_data_r;
// Delayed version of selector to match phase of response signals
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
select_q <= 1'b0;
else
select_q <= select_i;
assign inport0_ack_o = (select_q == 1'd0) && outport_ack_i;
assign inport0_error_o = (select_q == 1'd0) && outport_error_i;
assign inport0_read_data_o = outport_read_data_i;
assign inport0_accept_o = (select_i == 1'd0) && outport_accept_i;
assign inport1_ack_o = (select_q == 1'd1) && outport_ack_i;
assign inport1_error_o = (select_q == 1'd1) && outport_error_i;
assign inport1_read_data_o = outport_read_data_i;
assign inport1_accept_o = (select_i == 1'd1) && outport_accept_i;
endmodule |
module axi_tb;
reg clk, rst;
wire [31:0] ARADDR;
wire ARVALID;
wire ARREADY;
wire [7:0] ARLEN;
wire [2:0] ARSIZE;
wire RVALID;
wire [31:0] RDATA;
wire RREADY;
wire RLAST;
wire [31:0] AWADDR;
wire AWVALID;
wire AWREADY;
wire [7:0] AWLEN;
wire [2:0] AWSIZE;
wire WVALID;
wire WREADY;
wire [31:0] WDATA;
wire WLAST;
wire BVALID;
wire BREADY;
wire [1:0] BRESP;
initial begin
clk <= 0;
rst <= 1;
#15
rst <= ~rst;
#10000
$finish;
end
always begin
#10 clk = ~clk;
end
main main_inst(.clk(clk), .rst(rst),
.a_ARADDR(ARADDR), .b_ARADDR(ARADDR),
.a_ARVALID(ARVALID),. b_ARVALID(ARVALID),
.a_ARREADY(ARREADY), .b_ARREADY(ARREADY),
.a_ARLEN(ARLEN), .b_ARLEN(ARLEN),
.a_ARSIZE(ARSIZE), .b_ARSIZE(ARSIZE),
.a_RVALID(RVALID), .b_RVALID(RVALID),
.a_RDATA(RDATA), .b_RDATA(RDATA),
.a_RREADY(RREADY), .b_RREADY(RREADY),
.a_RLAST(RLAST), .b_RLAST(RLAST),
.a_AWADDR(AWADDR), .b_AWADDR(AWADDR),
.a_AWVALID(AWVALID), .b_AWVALID(AWVALID),
.a_AWREADY(AWREADY), .b_AWREADY(AWREADY),
.a_AWLEN(AWLEN), .b_AWLEN(AWLEN),
.a_AWSIZE(AWSIZE), .b_AWSIZE(AWSIZE),
.a_WVALID(WVALID), .b_WVALID(WVALID),
.a_WREADY(WREADY), .b_WREADY(WREADY),
.a_WDATA(WDATA), .b_WDATA(WDATA),
.a_WLAST(WLAST), .b_WLAST(WLAST),
.a_BVALID(BVALID), .b_BVALID(BVALID),
.a_BREADY(BREADY), .b_BREADY(BREADY),
.a_BRESP(BRESP), .b_BRESP(BRESP)
);
initial begin
$dumpfile("/tmp/axi.vcd");
$dumpvars(0, main_inst);
end
endmodule |
module Q_FRAG_MODES (QCK, QST, QRT, QEN, QDI, QDS, CZI, QZ, FAKE_CONST);
input wire QCK;
input wire QST;
input wire QRT;
input wire QEN;
input wire QDI;
input wire QDS;
input wire CZI;
output wire QZ;
input wire FAKE_CONST;
parameter MODE = "INT";
// Q_FRAG with the FF connected to CZI
generate if (MODE == "INT") begin
(* pack="C_FRAG_to_FF;B_FRAG_to_FF" *)
wire qd;
assign qd = CZI;
Q_FRAG q_frag (
.QCK (QCK),
.QST (QST),
.QRT (QRT),
.QEN (QEN),
.QZ (QZ),
.QD (qd),
.CONST0 (QDS),
.CONST1 (FAKE_CONST)
);
// Q_FRAG with the FF connected to QDI (external)
end else if (MODE == "EXT") begin
Q_FRAG q_frag (
.QCK (QCK),
.QST (QST),
.QRT (QRT),
.QEN (QEN),
.QZ (QZ),
.QD (QDI),
.CONST0 (FAKE_CONST),
.CONST1 (QDS)
);
end endgenerate
endmodule |
module Block_Mat_exit570_pr (
ap_clk,
ap_rst,
ap_start,
start_full_n,
ap_done,
ap_continue,
ap_idle,
ap_ready,
start_out,
start_write,
height,
width,
gamma,
img3_rows_V_out_din,
img3_rows_V_out_full_n,
img3_rows_V_out_write,
img3_cols_V_out_din,
img3_cols_V_out_full_n,
img3_cols_V_out_write,
p_cols_assign_cast_out_out_din,
p_cols_assign_cast_out_out_full_n,
p_cols_assign_cast_out_out_write,
p_rows_assign_cast_out_out_din,
p_rows_assign_cast_out_out_full_n,
p_rows_assign_cast_out_out_write,
gamma_out_din,
gamma_out_full_n,
gamma_out_write,
ap_return_0,
ap_return_1
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
input start_full_n;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output start_out;
output start_write;
input [15:0] height;
input [15:0] width;
input [7:0] gamma;
output [15:0] img3_rows_V_out_din;
input img3_rows_V_out_full_n;
output img3_rows_V_out_write;
output [15:0] img3_cols_V_out_din;
input img3_cols_V_out_full_n;
output img3_cols_V_out_write;
output [11:0] p_cols_assign_cast_out_out_din;
input p_cols_assign_cast_out_out_full_n;
output p_cols_assign_cast_out_out_write;
output [11:0] p_rows_assign_cast_out_out_din;
input p_rows_assign_cast_out_out_full_n;
output p_rows_assign_cast_out_out_write;
output [7:0] gamma_out_din;
input gamma_out_full_n;
output gamma_out_write;
output [15:0] ap_return_0;
output [15:0] ap_return_1;
reg ap_done;
reg ap_idle;
reg start_write;
reg img3_rows_V_out_write;
reg img3_cols_V_out_write;
reg p_cols_assign_cast_out_out_write;
reg p_rows_assign_cast_out_out_write;
reg gamma_out_write;
reg[15:0] ap_return_0;
reg[15:0] ap_return_1;
reg real_start;
reg start_once_reg;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg internal_ap_ready;
reg img3_rows_V_out_blk_n;
reg img3_cols_V_out_blk_n;
reg p_cols_assign_cast_out_out_blk_n;
reg p_rows_assign_cast_out_out_blk_n;
reg gamma_out_blk_n;
reg ap_block_state1;
reg [15:0] ap_return_0_preg;
reg [15:0] ap_return_1_preg;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 start_once_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_0_preg = 16'd0;
#0 ap_return_1_preg = 16'd0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_0_preg <= 16'd0;
end else begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_0_preg <= height;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_1_preg <= 16'd0;
end else begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_1_preg <= width;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
start_once_reg <= 1'b0;
end else begin
if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
start_once_reg <= 1'b1;
end else if ((internal_ap_ready == 1'b1)) begin
start_once_reg <= 1'b0;
end
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_0 = height;
end else begin
ap_return_0 = ap_return_0_preg;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_1 = width;
end else begin
ap_return_1 = ap_return_1_preg;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
gamma_out_blk_n = gamma_out_full_n;
end else begin
gamma_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
gamma_out_write = 1'b1;
end else begin
gamma_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_cols_V_out_blk_n = img3_cols_V_out_full_n;
end else begin
img3_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_cols_V_out_write = 1'b1;
end else begin
img3_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img3_rows_V_out_blk_n = img3_rows_V_out_full_n;
end else begin
img3_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img3_rows_V_out_write = 1'b1;
end else begin
img3_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
internal_ap_ready = 1'b1;
end else begin
internal_ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_cols_assign_cast_out_out_blk_n = p_cols_assign_cast_out_out_full_n;
end else begin
p_cols_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_out_out_write = 1'b1;
end else begin
p_cols_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
p_rows_assign_cast_out_out_blk_n = p_rows_assign_cast_out_out_full_n;
end else begin
p_rows_assign_cast_out_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_out_out_write = 1'b1;
end else begin
p_rows_assign_cast_out_out_write = 1'b0;
end
end
always @ (*) begin
if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
real_start = 1'b0;
end else begin
real_start = ap_start;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
start_write = 1'b1;
end else begin
start_write = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @ (*) begin
ap_block_state1 = ((real_start == 1'b0) | (gamma_out_full_n == 1'b0) | (p_rows_assign_cast_out_out_full_n == 1'b0) | (p_cols_assign_cast_out_out_full_n == 1'b0) | (img3_cols_V_out_full_n == 1'b0) | (img3_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_ready = internal_ap_ready;
assign gamma_out_din = gamma;
assign img3_cols_V_out_din = width;
assign img3_rows_V_out_din = height;
assign p_cols_assign_cast_out_out_din = width[11:0];
assign p_rows_assign_cast_out_out_din = height[11:0];
assign start_out = real_start;
endmodule |
module note_pitch2dds_3st_gen(clk, note, pitch, adder);
input wire clk;
input wire [6:0] note;
input wire [13:0] pitch;
output reg [31:0] adder;
reg [32:0] adder_sum;
reg [7:0] adder_mul;
reg [3:0] state;
reg [6:0] note_local;
reg [13:0] pitch_local;
initial begin
note_local <= 7'd0;
pitch_local <= 14'd08192; // 0 - pitch wheel
adder <= 32'd0;
state <= 4'd0;
Snote <= 9'D0;
end
//считаем pitch Wheel
// in_val сначала << 7
// а потом
//; ALGORITHM:
//; Clear accumulator
//; Add input / 1024 to accumulator >> 10
//; Add input / 2048 to accumulator >> 11
//; Move accumulator to result
//; Approximated constant: 0.00146484, Error: 0 %
//вычитаем 8192
wire signed [14:0] in_val_centered = (pitch - 14'd08192);
//15+11 = 26 бит
wire signed [26:0] in_val_fix = in_val_centered <<< 11;
//mul 0.00146484
wire signed [26:0] in_val_mul = (in_val_fix >>> 10) + (in_val_fix >>> 11);
//старшая часть, которую прибавим к номеру ноты
wire signed [26:0] t_in_val_hi = in_val_mul >>> 11;
wire signed [7:0] in_val_hi = t_in_val_hi[7:0];
//младшая 8 битная часть, которую будем применять в линейной интерполяции
wire [7:0] in_val_lo = in_val_mul[10:3];
reg signed [8:0] Snote ; //= note;
wire [7:0] note_n = ((Snote + in_val_hi)< 0) ? 7'd0 :
((Snote + in_val_hi)> 127) ? 7'd0127 : Snote + in_val_hi;
wire [31:0] adder_by_table;
note2dds note2dds_table(clk, note_n[6:0], adder_by_table);
always @ (posedge clk) begin
if (state==4'd00) begin
Snote <= note;
if ((note!=note_local)||(pitch!=pitch_local)) begin
note_local<=note;
pitch_local<=pitch;
adder_sum<=33'd0;
adder_mul<=8'd0;
end
end else if ((state==4'd01)||(state==4'd02)||(state==4'd03)) begin
Snote <= Snote + 1'b1; //if не обязателен
if (state==4'd01) adder_mul <= 8'd0255 - in_val_lo;
if (state==4'd02) adder_mul <= in_val_lo;
adder_sum <= adder_sum + (adder_mul * adder_by_table);
end else if (state==4'd04) begin
adder <= adder_sum >> 8;
end
end
always @ (posedge clk) begin
//смена стейтов
if (state==4'd00) begin
if ((note!=note_local)||(pitch!=pitch_local)) begin
state<=4'd01;
end else begin
state<=4'd00;
end
end else if (state==4'd01) begin
state<=4'd02;
end else if (state==4'd02) begin
state<=4'd03;
end else if (state==4'd03) begin
state<=4'd04;
end else if (state==4'd04) begin
state<=4'd00;
end
end
endmodule |
module output_shaper (
input wire d,
input wire [3:0] hightime,
input wire [3:0] deadtime,
input wire CLK,
output wire pulse,
input wire reset);
wire gate_closed;
output_shaper_core shape (
.d(d && ~gate_closed),
.hightime(hightime),
.deadtime(deadtime),
.CLK(CLK),
.pulse(pulse),
.reset(reset),
.gate_closed(gate_closed));
endmodule |
module output_shaper_core (
input wire d,
input wire [3:0] hightime,
input wire [3:0] deadtime,
input wire CLK,
output wire pulse,
output wire gate_closed,
input wire reset);
reg closed;
reg signal_entered;
reg output_pulse;
wire delay_hightime;
wire delay_deadtime;
reg hightime_reset;
reg deadtime_reset;
always@(posedge CLK)
begin
hightime_reset <= reset || delay_hightime;
deadtime_reset <= reset || delay_deadtime;
//the idea: the result of (signal_entered || closed) should be the test-condition, if new signals are allowed to enter
// however we want to be flexible and another - external - test-condition should be usable
// therfore we export (signal_entered || closed) as gate_closed and it must be manually combined with the input signal
if (d) signal_entered <= 1'b1; else signal_entered <= 1'b0;
//hightime check
if (hightime_reset == 1'b1) output_pulse <= 1'b0; else if (signal_entered == 1'b1) output_pulse <= 1'b1;
//deadtime check
if (deadtime_reset == 1'b1) closed <= 1'b0; else if (signal_entered == 1'b1) closed <= 1'b1;
end
assign pulse = output_pulse;
assign gate_closed = signal_entered || closed;
SRL16 #(.INIT(16'h0000)) HIGHTIME_DELAY (
.D(signal_entered),
.A0(hightime[0]), .A1(hightime[1]), .A2(hightime[2]), .A3(hightime[3]),
.CLK(CLK),
.Q(delay_hightime));
SRL16 #(.INIT(16'h0000)) DEADTIME_DELAY (
.D(delay_hightime),
.A0(deadtime[0]), .A1(deadtime[1]), .A2(deadtime[2]), .A3(deadtime[3]),
.CLK(CLK),
.Q(delay_deadtime));
endmodule |
module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256; //Stratix IV M9Ks
localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH;
localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE);
input clk;
input reset;
input kernel_clk;
input kernel_reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data;
output snoop_valid;
input snoop_ready;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
reg snoop_overflow;
// Register snoop data first
reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r; //word-address
reg snoop_valid_r;
wire snoop_fifo_empty;
wire overflow;
wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw;
always@(posedge clk)
begin
snoop_data_r<={address,export_burstcount};
snoop_valid_r<=export_write && !export_waitrequest;
end
// 1) Fifo to store snooped accesses from host
dcfifo dcfifo_component (
.wrclk (clk),
.data (snoop_data_r),
.wrreq (snoop_valid_r),
.rdclk (kernel_clk),
.rdreq (snoop_valid & snoop_ready),
.q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]),
.rdempty (snoop_fifo_empty),
.rdfull (overflow),
.aclr (1'b0),
.rdusedw (rdusedw),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix IV",
dcfifo_component.lpm_numwords = FIFO_SIZE,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH,
dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
assign snoop_valid=~snoop_fifo_empty;
always@(posedge kernel_clk)
snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) );
// Overflow piggy backed onto MSB of stream. Since overflow guarantees
// there is something to be read out, we can be sure that this will reach
// the cache.
assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign waitrequest = export_waitrequest;
endmodule |
module ArrayUltrasound(
//trans
input sysclk,
//hv7350
output [15:0] E_P,
output [15:0] E_N,
//hv2901
output HV_SW_CLR,
output HV_SW_LE,
output HV_SW_CLK,
output HV_SW_DOUT,
output HV_EN,
//mt8816
output [3:0] AX,
output [2:0] AY,
output MT_CS,
output MT_Strobe,
output MT_Data,
//ad9273 output
output ADCLK,
// input DCO,
input FCO,
input OUTA,
input OUTB,
input OUTC,
input OUTD,
input OUTE,
input OUTF,
input OUTG,
input OUTH,
//ad9273 spi_in
output SPI_CLK,
inout SPI_Data,
output SPI_CS,
output STBY,
output PWDN,
//ad5601 tgc
output sclk,
output reg sync,
output reg sdin,
// output reg HSync, //output Enable // not used
// output reg FSync, //frame // not used
// output reg TestCLK, // not used
// output reg LCLK_o, // LCD CLK not used
// output HS, // not used
// output VS, // not used
// output reg [7:0] R_Data, // not used
// output reg [7:0] G_Data, // not used
// output reg [7:0] B_Data, // not used
// output DE,
// output LCD_RST,
// output LCD_PWM,
// output SPENA,
// output SPDA,
// output SPCK,
// cc3200
input CC3200_SPI_CLK,
input CC3200_SPI_CS,
output CC3200_SPI_DIN,
input CC3200_SPI_DOUT,
input Envelop
);
reg RST_n;
reg [31:0] RST_Counter;
always @(posedge sysclk) begin //50MHz
if(RST_Counter <= 32'd48) begin
RST_Counter <= RST_Counter + 1'b1;
RST_n <= 1'b1;
end
else if(RST_Counter <= 32'd96000) begin
RST_Counter <= RST_Counter + 1'b1;
RST_n <= 1'b0;
end
else begin
RST_n <= 1'b1;
end
end
reg Enable;
wire [1:0] Zoom ;
wire [5:0] Gain;
reg [7:0] Line_Num;
wire [7:0] Line_Num_tmp;
wire [8:0] Trans_Addr;
wire [8:0] Trans_Data;
// assign Line_Num= {Line_Num_tmp[6:1],1'b1};
ComWithCC3200 ComWithCC3200 (
.CC3200_SPI_CLK (CC3200_SPI_CLK),
.CC3200_SPI_CS (CC3200_SPI_CS),
.CC3200_SPI_DIN (CC3200_SPI_DIN),
.CC3200_SPI_DOUT (CC3200_SPI_DOUT),
.Envelop (Envelop),
.Line_Num (Line_Num_tmp),
.Enable (),
.Zoom (Zoom),
.Gain (Gain),
.Trans_Data (Trans_Data[8:1]),
.Trans_Addr (Trans_Addr)
);
always @(posedge Envelop) begin
Line_Num <= Line_Num_tmp;
end
reg [31:0] Idle_Counter;
always @( posedge sysclk or posedge Envelop) begin //switch to swept line
if(Envelop) begin
Idle_Counter <= 32'd0;
Enable <= 1'b1;
end
else begin
if(Idle_Counter <= 32'd25000000) begin//0.5s
Enable <= 1'b1;
Idle_Counter <= Idle_Counter + 1'b1;
end
else begin
Enable <= 1'b0;
end
end
end
//assign Line_Num = Test_q[6:0];
wire CLK_100M;
wire CLK_20M;
PLL PLL_inst (
.inclk0 ( sysclk ),
.c0 ( CLK_100M ),
.c1 (CLK_20M)
);
assign ADCLK=sysclk;
wire AD_CLK;
reg [31:0] Pulse_Counter;
reg Pr_Gate;
reg RX_Gate;
reg End_Gate;
wire Sample_Gate; //start Sampling ,50ns width
reg [1:0] Focus_Num ;
reg [1:0] Focus_Num_Pre ;
//Focus_Num 0:20mm 16CH, 1:40mm:16CH, 2:80mm 16CH(outside) 3:80mm 16CH(inner),
always @(posedge RX_Gate or posedge Envelop) begin
if(Envelop) begin
Focus_Num_Pre <= 2'b0;
end
else begin
if(Focus_Num_Pre[1:0] == 2'b00) begin
Focus_Num_Pre[1:0] <= 2'b10;
end
/*
else if(Focus_Num_Pre[1:0] == 2'b01) begin
Focus_Num_Pre[1:0] <= 2'b10;
end
*/
else if(Focus_Num_Pre[1:0] == 2'b10) begin
Focus_Num_Pre[1:0] <= 2'b11;
end
else if(Focus_Num_Pre[1:0] == 2'b11) begin
Focus_Num_Pre[1:0] <= 2'b00;
end
else
begin
Focus_Num_Pre[1:0] <= 2'b00;
end
/*
if(Focus_Num_Pre[1:0] < 2'b11) begin
Focus_Num_Pre <= Focus_Num_Pre + 1'b1;
end
else begin
Focus_Num_Pre <= 2'b00;
end
*/
end
end
always @(posedge End_Gate) begin //next foucus
Focus_Num <= Focus_Num_Pre;
end
reg [31:0] Envelop_Counter;
reg [31:0] Line_Period;
always @(posedge Pr_Gate) begin
case(Focus_Num[1:0])
2'b00: //
Line_Period=32'd12000; //120us
2'b01:
Line_Period=32'd12000; //120us
2'b10:
Line_Period=32'd29000; //290us
2'b11:
Line_Period=32'd29000; //290us
endcase
end
always @(posedge CLK_100M or posedge Envelop) begin
if(Envelop) begin
Pulse_Counter <= 32'd0;
end
else begin
if(Pulse_Counter < 32'd3000) //30us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate <= 1'b1;
RX_Gate <= 1'b0;
End_Gate <= 1'b0;
end
else if(Pulse_Counter < 32'd3250) //2.5us?
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate <= 1'b0;
RX_Gate <= 1'b1;
End_Gate <= 1'b0;
end
else if(Pulse_Counter < Line_Period)
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate <= 1'b0;
RX_Gate <= 1'b0;
End_Gate <= 1'b0;
end
else if(Pulse_Counter < (Line_Period + 8'd80)) //0.8us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate <= 1'b0;
RX_Gate <= 1'b0;
End_Gate <= 1'b1;
end
else begin
if(Focus_Num_Pre >2'b00)
Pulse_Counter <= 32'd0;
else
Pulse_Counter <= 32'd65536;
Pr_Gate <= 1'b0;
RX_Gate <= 1'b0;
End_Gate <= 1'b0;
end
end
end
//assign HV_SW_LE2 = HV_SW_LE; //route wrong,should combine HV_SW_LE and HV_SW_LE2;
Transmit Transmit_Inst(
.Transmit_CLK (CLK_100M),
.Line_Num (Line_Num), // Line Num,256 Lines totally,0~255
.Focus_Num (Focus_Num), // Focus_num ,3 totally
.Pr_Gate (Pr_Gate), // yuzhi
.RX_Gate (RX_Gate), // transmit
.Sample_Gate (Sample_Gate), //start Sampling
.P (E_P),
.N (E_N),
.HV_SW_CLR (HV_SW_CLR),
.HV_SW_LE (HV_SW_LE),
.HV_SW_CLK (HV_SW_CLK),
.HV_SW_DOUT (HV_SW_DOUT),
.AX (AX),
.AY (AY),
.MT_CS (MT_CS),
.MT_Strobe (MT_Strobe),
.MT_Data (MT_Data)
);
wire [11:0] Data_A,Data_B,Data_C,Data_D;
wire [11:0] Data_E,Data_F,Data_G,Data_H;
LVDS_AD LVDS_AD_inst_A (
.rx_in ({OUTA,OUTB,OUTC,OUTD,OUTE,OUTF,OUTG,OUTH} ),
.rx_inclock ( FCO ),
.rx_out ({Data_A,Data_B,Data_C,Data_D,Data_E,Data_F,Data_G,Data_H} ),
.rx_outclock ( AD_CLK )
);
// assign TestCLK = AD_CLK;
assign HV_EN = ~Enable;
assign STBY = ~Enable;
assign PWDN = ~Enable;
assign SPI_CLK = CLK_20M;
AD9273_SPI_Config AD9273_SPI_Config_Inst(
.RST_n (RST_n),
.SPI_CLK (SPI_CLK),
.SPI_Data (SPI_Data),
.SPI_CS (SPI_CS)
);
reg [3:0] div_Sclk;
reg [7:0] Send_Counter;
reg [15:0] Send_Data;
reg [8:0] Tgc_Counter;
assign sclk = CLK_20M;
wire [6:0] Tgc_Data;
TGC_ROM TGC_ROM_inst (
.address ( Tgc_Counter[7:1] ),
.clock ( CLK_20M ),
.q (Tgc_Data )
);
always @(posedge CLK_20M or posedge Pr_Gate)
begin
if(Pr_Gate)
begin
Tgc_Counter <= 9'd0;
Send_Counter <= 8'b0;
end
else begin
if(Tgc_Counter < 9'd255) begin
if( Send_Counter <8'd3) begin
sync <= 1'b1;
Send_Counter <= Send_Counter + 1'b1;
//Send_Data <= {2'b0,{1'b0,TGC_Data[6:0]}+{2'b0,TGC_Data[6:1]}+{2'b0,Gain[6:1]},6'b0};
//Send_Data <= {2'b0,1'b1,Tgc_Counter[7:1],6'b0};
Send_Data <= {2'b0,({1'b0,Tgc_Data[6:0]}+{1'b0,Gain[5:0],1'b0}),6'b0};
//Send_Data <= {2'b0,8'd255,6'b0};
end
else if(Send_Counter <8'd19) begin
Send_Counter <= Send_Counter + 1'b1;
sync <= 1'b0;
sdin <= Send_Data[8'd18-Send_Counter];
end
else begin
sync <= 1'b1;
Send_Counter <= 8'd0;
Tgc_Counter <= Tgc_Counter + 1'b1;
end
end
else begin
if( Send_Counter <8'd3) begin
sync <= 1'b1;
Send_Counter <= Send_Counter + 1'b1;
//Send_Data <= {2'b0,{1'b0,TGC_Data[6:0]}+{2'b0,TGC_Data[6:1]}+{2'b0,Gain[6:1]},6'b0};
Send_Data <= {2'b0,8'h0,6'b0};
//Send_Data <= {2'b0,8'h80,6'b0};
end
else if(Send_Counter <8'd19) begin
Send_Counter <= Send_Counter + 1'b1;
sync <= 1'b0;
sdin <= Send_Data[8'd18-Send_Counter];
end
else begin
sync <= 1'b1;
Send_Counter <= 8'd0;
end
end
end
end
reg RX_Gate_Reg;
reg Pr_Gate_Reg;
reg Sample_Gate_Reg;
reg End_Gate_Reg;
always @(posedge AD_CLK)
begin
RX_Gate_Reg <= RX_Gate;
Pr_Gate_Reg <= Pr_Gate;
Sample_Gate_Reg <= Sample_Gate;
End_Gate_Reg <= End_Gate;
end
wire [15:0] DAS_Value;
wire So_Gate;
wire [7:0] Coheren_Coff;
Receive Receive_Inst(
.AD_CLK (AD_CLK),
.Data_A (Data_A),
.Data_B (Data_B),
.Data_C (Data_C),
.Data_D (Data_D),
.Data_E (Data_E),
.Data_F (Data_F),
.Data_G (Data_G),
.Data_H (Data_H),
.Line_Num (Line_Num), //Line Num,256 Lines totally,0~255
.Focus_Num (Focus_Num),//Focus_Num[7:6]), //Focus_num ,4 totally
.Pr_Gate (Pr_Gate_Reg), //prepare for everythings
.RX_Gate (RX_Gate_Reg), // Start Transmit
.Sample_Gate (Sample_Gate_Reg),
.End_Gate (End_Gate_Reg),
.So_Gate (So_Gate), //output Enable
.DAS_Value (DAS_Value),
.Coheren_Coff(Coheren_Coff),
);
wire [29:0] Match_Filter_Data;
wire MF_Output_RDY;
wire MF_Output_Valid;
matchfilter MatchFilter_Inst(
.clk (AD_CLK),
.reset_n (1'b1),
.ast_sink_data (DAS_Value[14:0]), //15bit
.ast_sink_valid (So_Gate),
.ast_source_ready(1'b1),
.ast_sink_error (2'b00),
.ast_source_data (Match_Filter_Data), //30bit
.ast_sink_ready (MF_Output_RDY),
.ast_source_valid(MF_Output_Valid),
.ast_source_error()
);
/*
wire [38:0] Coherent_Result;
reg [7:0] Coheren_Coff_REG[35:0];
//Coff delay 29clk to Data,
//matchfilter delay 64clk to input,
//so Coff should delay more 64-29=35clk
integer i;
always @(posedge AD_CLK) begin
Coheren_Coff_REG[0] <= Coheren_Coff;
for(i=0;i<8'd34;i=i+1) begin
Coheren_Coff_REG[i+1] <= Coheren_Coff_REG[i] ;
end
end
mult30_9 mult30_9_inst (
.clock ( AD_CLK ),
.dataa ( Match_Filter_Data ),
.datab ( {1'b0,Coheren_Coff_REG[29]} ),
.result ( Coherent_Result )
);
wire [29:0] ABS_Data;
ABS ABS_inst (
.data ( Coherent_Result[38:8]),//Match_Filter_Data ),//Coherent_Result[38:8]) ,need change input bit width
.result ( ABS_Data )
);
*/
wire [29:0] ABS_Data;
ABS ABS_inst (
.data (Match_Filter_Data),
.result (ABS_Data)
);
//wire [28:0] LF_Data;
wire LF_Valid;
wire [30:0] LF_Data;
lf LF_Inst(
.clk (AD_CLK),
.reset_n (1'b1),
.ast_sink_data (ABS_Data[26:12]), //15bit
.ast_sink_valid (MF_Output_Valid),
.ast_source_ready(1'b1),
.ast_sink_error (2'b00),
.ast_source_data (LF_Data), //31bit
.ast_sink_ready (),
.ast_source_valid(LF_Valid),
.ast_source_error()
);
wire [12:0] Log_IN;
assign Log_IN =(LF_Data[30])?13'd0:((LF_Data[30:14] > 18'd8091)?13'd8191:LF_Data[26:14]);
//assign Log_IN =(LF_Data[30])?13'd0:((LF_Data[28:13] > 18'd8091)?13'd8191:LF_Data[25:13]);
wire [7:0] Log_OUT;
LOG_Table LOG_Table_inst (
.address ( Log_IN),
.clock (AD_CLK ),
.q (Log_OUT )
);
reg [8:0] WR_RAM_ADDR;
reg [7:0] LF_Reg;
reg [7:0] Interlace_Counter;
reg [7:0] Log1,Log2,Log3,Log4,Log5,Log6,Log7,Log8,Log9,Log10,Log11,Log12,Log13,Log14,Log15;
reg [11:0] Sum_Log;
reg [15:0] Sample_Counter;
reg Seg_Enable;
reg [7:0] Interlace;
always @(*) begin
case(Zoom)
2'b00: //90mm
Interlace <= 8'd10;
2'b01: //130mm
Interlace <= 8'd15;
2'b10: //160mm
Interlace <= 8'd19;
2'b11: //200mm
Interlace <= 8'd24;
endcase
end
wire [7:0] Base_Noise1;
wire [7:0] Base_Noise2;
//wire [7:0] Focus_Num;
wire [7:0] Line_Num_Test;
Test Test_inst (
.address (1'b0 ),
.clock (AD_CLK ),
.q ({Base_Noise1,Base_Noise2})
);
always @(posedge AD_CLK or negedge LF_Valid ) begin
if(~LF_Valid) begin
Interlace_Counter <= 8'd0;
WR_RAM_ADDR[8:0] <= 8'd0;
Sample_Counter <= 16'd0;
end
else begin
Log15 <= Log14;
Log14 <= Log13;
Log13 <= Log12;
Log12 <= Log11;
Log11 <= Log10;
Log10 <= Log9;
Log9 <= Log8;
Log8 <= Log7;
Log7 <= Log6;
Log6 <= Log5;
Log5 <= Log4;
Log4 <= Log3;
Log3 <= Log2;
Log2 <= Log1;
Log1 <= Log_OUT;
Sum_Log <= Log1+Log2+Log3+Log4+Log5+Log6+Log7+Log8+Log9+Log10+Log11+Log12+Log13+Log14+Log15;
if(Sample_Counter <16'd16000) begin
Sample_Counter <= Sample_Counter + 1'b1;
end
if(Sample_Counter <=16'd2000) begin //<30mm
if(Focus_Num[1:0] == 2'b00) begin
Seg_Enable <= 1'b1;
end
else begin
Seg_Enable <= 1'b0;
end
LF_Reg <= (Sum_Log[11:4]>Base_Noise1)? (Sum_Log[11:4]-Base_Noise1): 8'd0 ;
end
/*
else if(Sample_Counter <=16'd3200) begin //<50mm
if(Focus_Num[1:0] == 2'b01) begin
Seg_Enable <= 1'b1;
end
else begin
Seg_Enable <= 1'b0;
end
LF_Reg <= Sum_Log[11:4];
end
*/
else begin
if(Focus_Num[1:0] == 2'b11) begin
Seg_Enable <= 1'b1;
end
else begin
Seg_Enable <= 1'b0;
end
LF_Reg <= (Sum_Log[11:4]>Base_Noise2)? (Sum_Log[11:4]-Base_Noise2): 8'd0 ;
end
if(Interlace_Counter < Interlace) begin
Interlace_Counter <= Interlace_Counter + 1'b1;
end
else begin
if(WR_RAM_ADDR[8:0] <9'd511) begin
WR_RAM_ADDR[8:0] <= WR_RAM_ADDR[8:0] + 1'b1;
end
Interlace_Counter <= 8'd0;
end
end
end
/*
reg Toggle;
always @(posedge Envelop) begin
Toggle <= ~Toggle;
end
IMG_BUFFER IMG_BUFFER_inst (
.data ( LF_Reg ),
.rdaddress ( {Toggle,Trans_Addr} ),
.rdclock ( CC3200_SPI_CS ),
.wraddress ( {~Toggle,WR_RAM_ADDR} ),
.wrclock ( AD_CLK ),
.wren ( LF_Valid & Seg_Enable ),
.q ( Trans_Data )
);
*/
reg [1:0] Toggle;
always @(posedge Envelop) begin
Toggle <= Toggle + 1'b1;
end
wire [7:0] Trans_Data1,Trans_Data2;
IMG_TRI_BUFFER IMG_TRI_BUFFER_inst (
.data (LF_Reg),
.rdaddress_a ({Toggle[1:0]-2'b01,Trans_Addr}),
.rdaddress_b ({Toggle[1:0]-2'b10,Trans_Addr} ),
.rdclock (CC3200_SPI_CS ),
.wraddress ({Toggle[1:0],WR_RAM_ADDR}),
.wrclock (AD_CLK ),
.wren (LF_Valid & Seg_Enable ),
.qa (Trans_Data1 ),
.qb (Trans_Data2 )
);
assign Trans_Data ={1'b0,Trans_Data1} + {1'b0,Trans_Data2};
endmodule |
module sky130_fd_sc_hs__einvp_1 (
A ,
TE ,
Z ,
VPWR,
VGND
);
input A ;
input TE ;
output Z ;
input VPWR;
input VGND;
sky130_fd_sc_hs__einvp base (
.A(A),
.TE(TE),
.Z(Z),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule |
module sky130_fd_sc_hs__einvp_1 (
A ,
TE,
Z
);
input A ;
input TE;
output Z ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__einvp base (
.A(A),
.TE(TE),
.Z(Z)
);
endmodule |
module or1200_immu_top(
// Rst and clk
clk, rst,
// CPU i/f
ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// QMEM i/f
qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// CPU I/F
//
input ic_en;
input immu_en;
input supv;
input [aw-1:0] icpu_adr_i;
input icpu_cycstb_i;
output [aw-1:0] icpu_adr_o;
output [3:0] icpu_tag_o;
output icpu_rty_o;
output icpu_err_o;
//
// SPR access
//
input spr_cs;
input spr_write;
input [aw-1:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// IC I/F
//
input qmemimmu_rty_i;
input qmemimmu_err_i;
input [3:0] qmemimmu_tag_i;
output [aw-1:0] qmemimmu_adr_o;
output qmemimmu_cycstb_o;
output qmemimmu_ci_o;
//
// Internal wires and regs
//
wire itlb_spr_access;
wire [31:`OR1200_IMMU_PS] itlb_ppn;
wire itlb_hit;
wire itlb_uxe;
wire itlb_sxe;
wire [31:0] itlb_dat_o;
wire itlb_en;
wire itlb_ci;
wire itlb_done;
wire fault;
wire miss;
wire page_cross;
reg [31:0] icpu_adr_o;
reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
`ifdef OR1200_NO_IMMU
`else
reg itlb_en_r;
reg dis_spr_access;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-10 v 0
// itlbwYtrX: ppn 31-10 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// icpu_adr_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(posedge rst or posedge clk)
if (rst)
icpu_adr_o <= #1 32'h0000_0100;
else
icpu_adr_o <= #1 icpu_adr_i;
`else
Unsupported !!!
`endif
//
// Page cross
//
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
//
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
//
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
// one clock cycle after offset part.
//
always @(posedge clk or posedge rst)
if (rst)
icpu_vpn_r <= #1 {32-`OR1200_IMMU_PS{1'b0}};
else
icpu_vpn_r <= #1 icpu_adr_i[31:`OR1200_IMMU_PS];
`ifdef OR1200_NO_IMMU
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemimmu_adr_o = icpu_adr_i;
assign icpu_tag_o = qmemimmu_tag_i;
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
assign icpu_rty_o = qmemimmu_rty_i;
assign icpu_err_o = qmemimmu_err_i;
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// ITLB SPR access
//
// 1200 - 12FF itlbmr w0
// 1200 - 123F itlbmr w0 [63:0]
//
// 1300 - 13FF itlbtr w0
// 1300 - 133F itlbtr w0 [63:0]
//
assign itlb_spr_access = spr_cs & ~dis_spr_access;
//
// Disable ITLB SPR access
//
// This flop is used to mask ITLB miss/fault exception
// during first clock cycle of accessing ITLB SPR. In
// subsequent clock cycles it is assumed that ITLB SPR
// access was accomplished and that normal instruction fetching
// can proceed.
//
// spr_cs sets dis_spr_access and icpu_rty_o clears it.
//
always @(posedge clk or posedge rst)
if (rst)
dis_spr_access <= #1 1'b0;
else if (!icpu_rty_o)
dis_spr_access <= #1 1'b0;
else if (spr_cs)
dis_spr_access <= #1 1'b1;
//
// Tags:
//
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemimmu_tag_i;
//
// icpu_rty_o
//
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
//
// icpu_err_o
//
assign icpu_err_o = miss | fault | qmemimmu_err_i;
//
// Assert itlb_en_r after one clock cycle and when there is no
// ITLB SPR access
//
always @(posedge clk or posedge rst)
if (rst)
itlb_en_r <= #1 1'b0;
else
itlb_en_r <= #1 itlb_en & ~itlb_spr_access;
//
// ITLB lookup successful
//
assign itlb_done = itlb_en_r & ~page_cross;
//
// Cut transfer if something goes wrong with translation. If IC is disabled,
// use delayed signals.
//
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
//
// Cache Inhibit
//
// Cache inhibit is not really needed for instruction memory subsystem.
// If we would doq it, we would doq it like this.
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
// However this causes a async combinational loop so we stick to
// no cache inhibit.
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
//
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
//
assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
//
// Output to SPRS unit
//
assign spr_dat_o = spr_cs ? itlb_dat_o : 32'h00000000;
//
// Page fault exception logic
//
assign fault = itlb_done &
( (!supv & !itlb_uxe) // Execute in user mode not enabled
|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
//
// TLB Miss exception logic
//
assign miss = itlb_done & !itlb_hit;
//
// ITLB Enable
//
assign itlb_en = immu_en & icpu_cycstb_i;
//
// Instantiation of ITLB
//
or1200_immu_tlb or1200_immu_tlb(
// Rst and clk
.clk(clk),
.rst(rst),
// I/F for translation
.tlb_en(itlb_en),
.vaddr(icpu_adr_i),
.hit(itlb_hit),
.ppn(itlb_ppn),
.uxe(itlb_uxe),
.sxe(itlb_sxe),
.ci(itlb_ci),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// SPR access
.spr_cs(itlb_spr_access),
.spr_write(spr_write),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_i),
.spr_dat_o(itlb_dat_o)
);
`endif
endmodule |
module sky130_fd_sc_ls__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule |
module sky130_fd_sc_hdll__fill ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule |
module bsg_counter_dynamic_limit_en #(parameter `BSG_INV_PARAM(width_p ))
( input clk_i
, input reset_i
, input en_i
, input [width_p-1:0] limit_i
, output logic [width_p-1:0] counter_o
, output overflowed_o
);
wire [width_p-1:0] counter_plus_1 = counter_o + width_p'(1);
assign overflowed_o = ( counter_plus_1 == limit_i );
always_ff @ (posedge clk_i)
if (reset_i)
counter_o <= 0;
else if (en_i) begin
if(overflowed_o ) counter_o <= 0;
else counter_o <= counter_plus_1 ;
end
endmodule |
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)(
uart_tx, ledout,
sys_clk_i, sys_rst_i, sclk, miso, mosi,ss, mic_in, bclk, lrsel
);
input sys_clk_i, sys_rst_i,miso;
output uart_tx, mosi, ss, sclk;
output ledout;
input mic_in; // Microfono
output bclk, lrsel; // Microfono
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:5]cs; // CHIP-SELECT
wire [15:0] sd_out;
wire [15:0] microfono_out;
wire [15:0] mult_dout;
wire [15:0] div_dout;
wire uart_dout; // misma señal que uart_busy from uart.v
wire [15:0] dp_ram_dout;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripheral_mult per_m (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[1]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(mult_dout) );
peripheral_div per_d (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[2]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(div_dout));
peripheral_uart per_u (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[3]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(uart_dout), .uart_tx(uart_tx), .ledout(ledout));
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[4]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
peripheral_SD sd(.clk(sys_clk_i), .reset(sys_rst_i) , .d_in(j1_io_dout) , .cs(cs[5]) , .addr(j1_io_addr[3:0]) , .rd(j1_io_rd) , .wr(j1_io_wr), .d_out(sd_out), .sclk(sclk), .mosi(mosi), .miso(miso), .ss(ss) );
interface_microfono Microfono(.clk(sys_clk_i), .reset(sys_rst_i) , .d_in(j1_io_dout) , .cs(cs==5'b00011) , .addr(j1_io_addr[3:0]) , .rd(j1_io_rd) , .wr(j1_io_wr), .d_out(microfono_out), .bclk(bclk), .lrsel(lrsel), .mic_in(mic_in) );//revisar
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @*
begin
case (j1_io_addr[15:8]) // direcciones - chip_select
8'h67: cs= 5'b10000; //mult
8'h68: cs= 5'b01000; //div
8'h69: cs= 5'b00100; //uart
8'h70: cs= 5'b00010; //dp_ram
8'h71: cs= 5'b00001; //SD
8'h71: cs= 5'b00011; //Microfono
default: cs= 3'b000;
endcase
end
// ============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @*
begin
case (cs)
5'b10000: j1_io_din = mult_dout;
5'b01000: j1_io_din = div_dout;
5'b00100: j1_io_din = uart_dout;
5'b00010: j1_io_din = dp_ram_dout;
5'b00001: j1_io_din = sd_out;
5'b00011: j1_io_din = microfono_out;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule |
module sky130_fd_sc_ms__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_ms__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule |
module {name} (
input [11:0] address,
output [17:0] instruction,
input enable,
input clk);
//
//
wire [15:0] address_a;
wire [35:0] data_in_a;
wire [35:0] data_out_a_l;
wire [35:0] data_out_a_h;
wire [15:0] address_b;
wire [35:0] data_in_b_l;
wire [35:0] data_out_b_l;
wire [35:0] data_in_b_h;
wire [35:0] data_out_b_h;
wire enable_b;
wire clk_b;
wire [7:0] we_b;
//
//
assign address_a = {1'b1, address[11:0], 3'b111};
assign instruction = {data_out_a_h[32], data_out_a_h[7:0], data_out_a_l[32], data_out_a_l[7:0]};
assign data_in_a = 36'b000000000000000000000000000000000000;
//
assign address_b = 16'b1111111111111111;
assign data_in_b_l = {3'h0, data_out_b_l[32], 24'b000000000000000000000000, data_out_b_l[7:0]};
assign data_in_b_h = {3'h0, data_out_b_h[32], 24'b000000000000000000000000, data_out_b_h[7:0]};
assign enable_b = 1'b0;
assign we_b = 8'h00;
assign clk_b = 1'b0;
//
RAMB36E1 # ( .READ_WIDTH_A (9),
.WRITE_WIDTH_A (9),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (9),
.WRITE_WIDTH_B (9),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("VIRTEX6"),
.INIT_00 (256'h{[8:0]_INIT_00}),
.INIT_01 (256'h{[8:0]_INIT_01}),
.INIT_02 (256'h{[8:0]_INIT_02}),
.INIT_03 (256'h{[8:0]_INIT_03}),
.INIT_04 (256'h{[8:0]_INIT_04}),
.INIT_05 (256'h{[8:0]_INIT_05}),
.INIT_06 (256'h{[8:0]_INIT_06}),
.INIT_07 (256'h{[8:0]_INIT_07}),
.INIT_08 (256'h{[8:0]_INIT_08}),
.INIT_09 (256'h{[8:0]_INIT_09}),
.INIT_0A (256'h{[8:0]_INIT_0A}),
.INIT_0B (256'h{[8:0]_INIT_0B}),
.INIT_0C (256'h{[8:0]_INIT_0C}),
.INIT_0D (256'h{[8:0]_INIT_0D}),
.INIT_0E (256'h{[8:0]_INIT_0E}),
.INIT_0F (256'h{[8:0]_INIT_0F}),
.INIT_10 (256'h{[8:0]_INIT_10}),
.INIT_11 (256'h{[8:0]_INIT_11}),
.INIT_12 (256'h{[8:0]_INIT_12}),
.INIT_13 (256'h{[8:0]_INIT_13}),
.INIT_14 (256'h{[8:0]_INIT_14}),
.INIT_15 (256'h{[8:0]_INIT_15}),
.INIT_16 (256'h{[8:0]_INIT_16}),
.INIT_17 (256'h{[8:0]_INIT_17}),
.INIT_18 (256'h{[8:0]_INIT_18}),
.INIT_19 (256'h{[8:0]_INIT_19}),
.INIT_1A (256'h{[8:0]_INIT_1A}),
.INIT_1B (256'h{[8:0]_INIT_1B}),
.INIT_1C (256'h{[8:0]_INIT_1C}),
.INIT_1D (256'h{[8:0]_INIT_1D}),
.INIT_1E (256'h{[8:0]_INIT_1E}),
.INIT_1F (256'h{[8:0]_INIT_1F}),
.INIT_20 (256'h{[8:0]_INIT_20}),
.INIT_21 (256'h{[8:0]_INIT_21}),
.INIT_22 (256'h{[8:0]_INIT_22}),
.INIT_23 (256'h{[8:0]_INIT_23}),
.INIT_24 (256'h{[8:0]_INIT_24}),
.INIT_25 (256'h{[8:0]_INIT_25}),
.INIT_26 (256'h{[8:0]_INIT_26}),
.INIT_27 (256'h{[8:0]_INIT_27}),
.INIT_28 (256'h{[8:0]_INIT_28}),
.INIT_29 (256'h{[8:0]_INIT_29}),
.INIT_2A (256'h{[8:0]_INIT_2A}),
.INIT_2B (256'h{[8:0]_INIT_2B}),
.INIT_2C (256'h{[8:0]_INIT_2C}),
.INIT_2D (256'h{[8:0]_INIT_2D}),
.INIT_2E (256'h{[8:0]_INIT_2E}),
.INIT_2F (256'h{[8:0]_INIT_2F}),
.INIT_30 (256'h{[8:0]_INIT_30}),
.INIT_31 (256'h{[8:0]_INIT_31}),
.INIT_32 (256'h{[8:0]_INIT_32}),
.INIT_33 (256'h{[8:0]_INIT_33}),
.INIT_34 (256'h{[8:0]_INIT_34}),
.INIT_35 (256'h{[8:0]_INIT_35}),
.INIT_36 (256'h{[8:0]_INIT_36}),
.INIT_37 (256'h{[8:0]_INIT_37}),
.INIT_38 (256'h{[8:0]_INIT_38}),
.INIT_39 (256'h{[8:0]_INIT_39}),
.INIT_3A (256'h{[8:0]_INIT_3A}),
.INIT_3B (256'h{[8:0]_INIT_3B}),
.INIT_3C (256'h{[8:0]_INIT_3C}),
.INIT_3D (256'h{[8:0]_INIT_3D}),
.INIT_3E (256'h{[8:0]_INIT_3E}),
.INIT_3F (256'h{[8:0]_INIT_3F}),
.INIT_40 (256'h{[8:0]_INIT_40}),
.INIT_41 (256'h{[8:0]_INIT_41}),
.INIT_42 (256'h{[8:0]_INIT_42}),
.INIT_43 (256'h{[8:0]_INIT_43}),
.INIT_44 (256'h{[8:0]_INIT_44}),
.INIT_45 (256'h{[8:0]_INIT_45}),
.INIT_46 (256'h{[8:0]_INIT_46}),
.INIT_47 (256'h{[8:0]_INIT_47}),
.INIT_48 (256'h{[8:0]_INIT_48}),
.INIT_49 (256'h{[8:0]_INIT_49}),
.INIT_4A (256'h{[8:0]_INIT_4A}),
.INIT_4B (256'h{[8:0]_INIT_4B}),
.INIT_4C (256'h{[8:0]_INIT_4C}),
.INIT_4D (256'h{[8:0]_INIT_4D}),
.INIT_4E (256'h{[8:0]_INIT_4E}),
.INIT_4F (256'h{[8:0]_INIT_4F}),
.INIT_50 (256'h{[8:0]_INIT_50}),
.INIT_51 (256'h{[8:0]_INIT_51}),
.INIT_52 (256'h{[8:0]_INIT_52}),
.INIT_53 (256'h{[8:0]_INIT_53}),
.INIT_54 (256'h{[8:0]_INIT_54}),
.INIT_55 (256'h{[8:0]_INIT_55}),
.INIT_56 (256'h{[8:0]_INIT_56}),
.INIT_57 (256'h{[8:0]_INIT_57}),
.INIT_58 (256'h{[8:0]_INIT_58}),
.INIT_59 (256'h{[8:0]_INIT_59}),
.INIT_5A (256'h{[8:0]_INIT_5A}),
.INIT_5B (256'h{[8:0]_INIT_5B}),
.INIT_5C (256'h{[8:0]_INIT_5C}),
.INIT_5D (256'h{[8:0]_INIT_5D}),
.INIT_5E (256'h{[8:0]_INIT_5E}),
.INIT_5F (256'h{[8:0]_INIT_5F}),
.INIT_60 (256'h{[8:0]_INIT_60}),
.INIT_61 (256'h{[8:0]_INIT_61}),
.INIT_62 (256'h{[8:0]_INIT_62}),
.INIT_63 (256'h{[8:0]_INIT_63}),
.INIT_64 (256'h{[8:0]_INIT_64}),
.INIT_65 (256'h{[8:0]_INIT_65}),
.INIT_66 (256'h{[8:0]_INIT_66}),
.INIT_67 (256'h{[8:0]_INIT_67}),
.INIT_68 (256'h{[8:0]_INIT_68}),
.INIT_69 (256'h{[8:0]_INIT_69}),
.INIT_6A (256'h{[8:0]_INIT_6A}),
.INIT_6B (256'h{[8:0]_INIT_6B}),
.INIT_6C (256'h{[8:0]_INIT_6C}),
.INIT_6D (256'h{[8:0]_INIT_6D}),
.INIT_6E (256'h{[8:0]_INIT_6E}),
.INIT_6F (256'h{[8:0]_INIT_6F}),
.INIT_70 (256'h{[8:0]_INIT_70}),
.INIT_71 (256'h{[8:0]_INIT_71}),
.INIT_72 (256'h{[8:0]_INIT_72}),
.INIT_73 (256'h{[8:0]_INIT_73}),
.INIT_74 (256'h{[8:0]_INIT_74}),
.INIT_75 (256'h{[8:0]_INIT_75}),
.INIT_76 (256'h{[8:0]_INIT_76}),
.INIT_77 (256'h{[8:0]_INIT_77}),
.INIT_78 (256'h{[8:0]_INIT_78}),
.INIT_79 (256'h{[8:0]_INIT_79}),
.INIT_7A (256'h{[8:0]_INIT_7A}),
.INIT_7B (256'h{[8:0]_INIT_7B}),
.INIT_7C (256'h{[8:0]_INIT_7C}),
.INIT_7D (256'h{[8:0]_INIT_7D}),
.INIT_7E (256'h{[8:0]_INIT_7E}),
.INIT_7F (256'h{[8:0]_INIT_7F}),
.INITP_00 (256'h{[8:0]_INITP_00}),
.INITP_01 (256'h{[8:0]_INITP_01}),
.INITP_02 (256'h{[8:0]_INITP_02}),
.INITP_03 (256'h{[8:0]_INITP_03}),
.INITP_04 (256'h{[8:0]_INITP_04}),
.INITP_05 (256'h{[8:0]_INITP_05}),
.INITP_06 (256'h{[8:0]_INITP_06}),
.INITP_07 (256'h{[8:0]_INITP_07}),
.INITP_08 (256'h{[8:0]_INITP_08}),
.INITP_09 (256'h{[8:0]_INITP_09}),
.INITP_0A (256'h{[8:0]_INITP_0A}),
.INITP_0B (256'h{[8:0]_INITP_0B}),
.INITP_0C (256'h{[8:0]_INITP_0C}),
.INITP_0D (256'h{[8:0]_INITP_0D}),
.INITP_0E (256'h{[8:0]_INITP_0E}),
.INITP_0F (256'h{[8:0]_INITP_0F}))
kcpsm6_rom_l(.ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a_l[31:0]),
.DOPADOP (data_out_a_l[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'h0),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b_l[31:0]),
.DOPBDOP (data_out_b_l[35:32]),
.DIBDI (data_in_b_l[31:0]),
.DIPBDIP (data_in_b_l[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
//
RAMB36E1 # ( .READ_WIDTH_A (9),
.WRITE_WIDTH_A (9),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (9),
.WRITE_WIDTH_B (9),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("VIRTEX6"),
.INIT_00 (256'h{[17:9]_INIT_00}),
.INIT_01 (256'h{[17:9]_INIT_01}),
.INIT_02 (256'h{[17:9]_INIT_02}),
.INIT_03 (256'h{[17:9]_INIT_03}),
.INIT_04 (256'h{[17:9]_INIT_04}),
.INIT_05 (256'h{[17:9]_INIT_05}),
.INIT_06 (256'h{[17:9]_INIT_06}),
.INIT_07 (256'h{[17:9]_INIT_07}),
.INIT_08 (256'h{[17:9]_INIT_08}),
.INIT_09 (256'h{[17:9]_INIT_09}),
.INIT_0A (256'h{[17:9]_INIT_0A}),
.INIT_0B (256'h{[17:9]_INIT_0B}),
.INIT_0C (256'h{[17:9]_INIT_0C}),
.INIT_0D (256'h{[17:9]_INIT_0D}),
.INIT_0E (256'h{[17:9]_INIT_0E}),
.INIT_0F (256'h{[17:9]_INIT_0F}),
.INIT_10 (256'h{[17:9]_INIT_10}),
.INIT_11 (256'h{[17:9]_INIT_11}),
.INIT_12 (256'h{[17:9]_INIT_12}),
.INIT_13 (256'h{[17:9]_INIT_13}),
.INIT_14 (256'h{[17:9]_INIT_14}),
.INIT_15 (256'h{[17:9]_INIT_15}),
.INIT_16 (256'h{[17:9]_INIT_16}),
.INIT_17 (256'h{[17:9]_INIT_17}),
.INIT_18 (256'h{[17:9]_INIT_18}),
.INIT_19 (256'h{[17:9]_INIT_19}),
.INIT_1A (256'h{[17:9]_INIT_1A}),
.INIT_1B (256'h{[17:9]_INIT_1B}),
.INIT_1C (256'h{[17:9]_INIT_1C}),
.INIT_1D (256'h{[17:9]_INIT_1D}),
.INIT_1E (256'h{[17:9]_INIT_1E}),
.INIT_1F (256'h{[17:9]_INIT_1F}),
.INIT_20 (256'h{[17:9]_INIT_20}),
.INIT_21 (256'h{[17:9]_INIT_21}),
.INIT_22 (256'h{[17:9]_INIT_22}),
.INIT_23 (256'h{[17:9]_INIT_23}),
.INIT_24 (256'h{[17:9]_INIT_24}),
.INIT_25 (256'h{[17:9]_INIT_25}),
.INIT_26 (256'h{[17:9]_INIT_26}),
.INIT_27 (256'h{[17:9]_INIT_27}),
.INIT_28 (256'h{[17:9]_INIT_28}),
.INIT_29 (256'h{[17:9]_INIT_29}),
.INIT_2A (256'h{[17:9]_INIT_2A}),
.INIT_2B (256'h{[17:9]_INIT_2B}),
.INIT_2C (256'h{[17:9]_INIT_2C}),
.INIT_2D (256'h{[17:9]_INIT_2D}),
.INIT_2E (256'h{[17:9]_INIT_2E}),
.INIT_2F (256'h{[17:9]_INIT_2F}),
.INIT_30 (256'h{[17:9]_INIT_30}),
.INIT_31 (256'h{[17:9]_INIT_31}),
.INIT_32 (256'h{[17:9]_INIT_32}),
.INIT_33 (256'h{[17:9]_INIT_33}),
.INIT_34 (256'h{[17:9]_INIT_34}),
.INIT_35 (256'h{[17:9]_INIT_35}),
.INIT_36 (256'h{[17:9]_INIT_36}),
.INIT_37 (256'h{[17:9]_INIT_37}),
.INIT_38 (256'h{[17:9]_INIT_38}),
.INIT_39 (256'h{[17:9]_INIT_39}),
.INIT_3A (256'h{[17:9]_INIT_3A}),
.INIT_3B (256'h{[17:9]_INIT_3B}),
.INIT_3C (256'h{[17:9]_INIT_3C}),
.INIT_3D (256'h{[17:9]_INIT_3D}),
.INIT_3E (256'h{[17:9]_INIT_3E}),
.INIT_3F (256'h{[17:9]_INIT_3F}),
.INIT_40 (256'h{[17:9]_INIT_40}),
.INIT_41 (256'h{[17:9]_INIT_41}),
.INIT_42 (256'h{[17:9]_INIT_42}),
.INIT_43 (256'h{[17:9]_INIT_43}),
.INIT_44 (256'h{[17:9]_INIT_44}),
.INIT_45 (256'h{[17:9]_INIT_45}),
.INIT_46 (256'h{[17:9]_INIT_46}),
.INIT_47 (256'h{[17:9]_INIT_47}),
.INIT_48 (256'h{[17:9]_INIT_48}),
.INIT_49 (256'h{[17:9]_INIT_49}),
.INIT_4A (256'h{[17:9]_INIT_4A}),
.INIT_4B (256'h{[17:9]_INIT_4B}),
.INIT_4C (256'h{[17:9]_INIT_4C}),
.INIT_4D (256'h{[17:9]_INIT_4D}),
.INIT_4E (256'h{[17:9]_INIT_4E}),
.INIT_4F (256'h{[17:9]_INIT_4F}),
.INIT_50 (256'h{[17:9]_INIT_50}),
.INIT_51 (256'h{[17:9]_INIT_51}),
.INIT_52 (256'h{[17:9]_INIT_52}),
.INIT_53 (256'h{[17:9]_INIT_53}),
.INIT_54 (256'h{[17:9]_INIT_54}),
.INIT_55 (256'h{[17:9]_INIT_55}),
.INIT_56 (256'h{[17:9]_INIT_56}),
.INIT_57 (256'h{[17:9]_INIT_57}),
.INIT_58 (256'h{[17:9]_INIT_58}),
.INIT_59 (256'h{[17:9]_INIT_59}),
.INIT_5A (256'h{[17:9]_INIT_5A}),
.INIT_5B (256'h{[17:9]_INIT_5B}),
.INIT_5C (256'h{[17:9]_INIT_5C}),
.INIT_5D (256'h{[17:9]_INIT_5D}),
.INIT_5E (256'h{[17:9]_INIT_5E}),
.INIT_5F (256'h{[17:9]_INIT_5F}),
.INIT_60 (256'h{[17:9]_INIT_60}),
.INIT_61 (256'h{[17:9]_INIT_61}),
.INIT_62 (256'h{[17:9]_INIT_62}),
.INIT_63 (256'h{[17:9]_INIT_63}),
.INIT_64 (256'h{[17:9]_INIT_64}),
.INIT_65 (256'h{[17:9]_INIT_65}),
.INIT_66 (256'h{[17:9]_INIT_66}),
.INIT_67 (256'h{[17:9]_INIT_67}),
.INIT_68 (256'h{[17:9]_INIT_68}),
.INIT_69 (256'h{[17:9]_INIT_69}),
.INIT_6A (256'h{[17:9]_INIT_6A}),
.INIT_6B (256'h{[17:9]_INIT_6B}),
.INIT_6C (256'h{[17:9]_INIT_6C}),
.INIT_6D (256'h{[17:9]_INIT_6D}),
.INIT_6E (256'h{[17:9]_INIT_6E}),
.INIT_6F (256'h{[17:9]_INIT_6F}),
.INIT_70 (256'h{[17:9]_INIT_70}),
.INIT_71 (256'h{[17:9]_INIT_71}),
.INIT_72 (256'h{[17:9]_INIT_72}),
.INIT_73 (256'h{[17:9]_INIT_73}),
.INIT_74 (256'h{[17:9]_INIT_74}),
.INIT_75 (256'h{[17:9]_INIT_75}),
.INIT_76 (256'h{[17:9]_INIT_76}),
.INIT_77 (256'h{[17:9]_INIT_77}),
.INIT_78 (256'h{[17:9]_INIT_78}),
.INIT_79 (256'h{[17:9]_INIT_79}),
.INIT_7A (256'h{[17:9]_INIT_7A}),
.INIT_7B (256'h{[17:9]_INIT_7B}),
.INIT_7C (256'h{[17:9]_INIT_7C}),
.INIT_7D (256'h{[17:9]_INIT_7D}),
.INIT_7E (256'h{[17:9]_INIT_7E}),
.INIT_7F (256'h{[17:9]_INIT_7F}),
.INITP_00 (256'h{[17:9]_INITP_00}),
.INITP_01 (256'h{[17:9]_INITP_01}),
.INITP_02 (256'h{[17:9]_INITP_02}),
.INITP_03 (256'h{[17:9]_INITP_03}),
.INITP_04 (256'h{[17:9]_INITP_04}),
.INITP_05 (256'h{[17:9]_INITP_05}),
.INITP_06 (256'h{[17:9]_INITP_06}),
.INITP_07 (256'h{[17:9]_INITP_07}),
.INITP_08 (256'h{[17:9]_INITP_08}),
.INITP_09 (256'h{[17:9]_INITP_09}),
.INITP_0A (256'h{[17:9]_INITP_0A}),
.INITP_0B (256'h{[17:9]_INITP_0B}),
.INITP_0C (256'h{[17:9]_INITP_0C}),
.INITP_0D (256'h{[17:9]_INITP_0D}),
.INITP_0E (256'h{[17:9]_INITP_0E}),
.INITP_0F (256'h{[17:9]_INITP_0F}))
kcpsm6_rom_h(.ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a_h[31:0]),
.DOPADOP (data_out_a_h[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'h0),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b_h[31:0]),
.DOPBDOP (data_out_b_h[35:32]),
.DIBDI (data_in_b_h[31:0]),
.DIPBDIP (data_in_b_h[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
//
endmodule |
module sky130_fd_sc_hdll__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule |
module sky130_fd_sc_hdll__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule |
module affine_block_ieee754_fp_multiplier_1_0
(x,
y,
z);
input [31:0]x;
input [31:0]y;
output [31:0]z;
wire [31:0]x;
wire [31:0]y;
wire [31:0]z;
wire \z[30]_INST_0_i_23_n_0 ;
wire \z[30]_INST_0_i_24_n_0 ;
wire \z[30]_INST_0_i_25_n_0 ;
wire \z[30]_INST_0_i_26_n_0 ;
wire \z[30]_INST_0_i_27_n_0 ;
wire \z[30]_INST_0_i_28_n_0 ;
wire \z[30]_INST_0_i_4_n_0 ;
wire \z[30]_INST_0_i_84_n_0 ;
wire \z[30]_INST_0_i_85_n_0 ;
wire \z[30]_INST_0_i_86_n_0 ;
wire \z[30]_INST_0_i_87_n_0 ;
wire \z[30]_INST_0_i_88_n_0 ;
wire \z[30]_INST_0_i_89_n_0 ;
wire \z[30]_INST_0_i_90_n_0 ;
wire \z[30]_INST_0_i_91_n_0 ;
wire \z[30]_INST_0_i_92_n_0 ;
wire \z[30]_INST_0_i_93_n_0 ;
wire [22:0]z_mantissa;
affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier U0
(.x(x[30:0]),
.y(y[30:0]),
.y_11__s_port_(\z[30]_INST_0_i_4_n_0 ),
.z(z[30:23]),
.z_mantissa(z_mantissa));
LUT2 #(
.INIT(4'h2))
\z[0]_INST_0
(.I0(z_mantissa[0]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[0]));
LUT2 #(
.INIT(4'h2))
\z[10]_INST_0
(.I0(z_mantissa[10]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[10]));
LUT2 #(
.INIT(4'h2))
\z[11]_INST_0
(.I0(z_mantissa[11]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[11]));
LUT2 #(
.INIT(4'h2))
\z[12]_INST_0
(.I0(z_mantissa[12]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[12]));
LUT2 #(
.INIT(4'h2))
\z[13]_INST_0
(.I0(z_mantissa[13]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[13]));
LUT2 #(
.INIT(4'h2))
\z[14]_INST_0
(.I0(z_mantissa[14]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[14]));
LUT2 #(
.INIT(4'h2))
\z[15]_INST_0
(.I0(z_mantissa[15]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[15]));
LUT2 #(
.INIT(4'h2))
\z[16]_INST_0
(.I0(z_mantissa[16]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[16]));
LUT2 #(
.INIT(4'h2))
\z[17]_INST_0
(.I0(z_mantissa[17]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[17]));
LUT2 #(
.INIT(4'h2))
\z[18]_INST_0
(.I0(z_mantissa[18]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[18]));
LUT2 #(
.INIT(4'h2))
\z[19]_INST_0
(.I0(z_mantissa[19]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[19]));
LUT2 #(
.INIT(4'h2))
\z[1]_INST_0
(.I0(z_mantissa[1]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[1]));
LUT2 #(
.INIT(4'h2))
\z[20]_INST_0
(.I0(z_mantissa[20]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[20]));
LUT2 #(
.INIT(4'h2))
\z[21]_INST_0
(.I0(z_mantissa[21]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[21]));
LUT2 #(
.INIT(4'h2))
\z[22]_INST_0
(.I0(z_mantissa[22]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[22]));
LUT2 #(
.INIT(4'h2))
\z[2]_INST_0
(.I0(z_mantissa[2]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[2]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_23
(.I0(x[29]),
.I1(x[4]),
.I2(x[11]),
.I3(x[13]),
.I4(\z[30]_INST_0_i_84_n_0 ),
.O(\z[30]_INST_0_i_23_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_24
(.I0(x[25]),
.I1(x[20]),
.I2(x[15]),
.I3(x[22]),
.I4(\z[30]_INST_0_i_85_n_0 ),
.O(\z[30]_INST_0_i_24_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\z[30]_INST_0_i_25
(.I0(\z[30]_INST_0_i_86_n_0 ),
.I1(\z[30]_INST_0_i_87_n_0 ),
.I2(\z[30]_INST_0_i_88_n_0 ),
.I3(x[24]),
.I4(x[10]),
.I5(x[2]),
.O(\z[30]_INST_0_i_25_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_26
(.I0(y[30]),
.I1(y[5]),
.I2(y[0]),
.I3(y[1]),
.I4(\z[30]_INST_0_i_89_n_0 ),
.O(\z[30]_INST_0_i_26_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_27
(.I0(y[29]),
.I1(y[18]),
.I2(y[2]),
.I3(y[10]),
.I4(\z[30]_INST_0_i_90_n_0 ),
.O(\z[30]_INST_0_i_27_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\z[30]_INST_0_i_28
(.I0(\z[30]_INST_0_i_91_n_0 ),
.I1(\z[30]_INST_0_i_92_n_0 ),
.I2(\z[30]_INST_0_i_93_n_0 ),
.I3(y[12]),
.I4(y[20]),
.I5(y[4]),
.O(\z[30]_INST_0_i_28_n_0 ));
LUT6 #(
.INIT(64'h101010FF10101010))
\z[30]_INST_0_i_4
(.I0(\z[30]_INST_0_i_23_n_0 ),
.I1(\z[30]_INST_0_i_24_n_0 ),
.I2(\z[30]_INST_0_i_25_n_0 ),
.I3(\z[30]_INST_0_i_26_n_0 ),
.I4(\z[30]_INST_0_i_27_n_0 ),
.I5(\z[30]_INST_0_i_28_n_0 ),
.O(\z[30]_INST_0_i_4_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_84
(.I0(x[9]),
.I1(x[3]),
.I2(x[17]),
.I3(x[7]),
.O(\z[30]_INST_0_i_84_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_85
(.I0(x[18]),
.I1(x[30]),
.I2(x[21]),
.I3(x[6]),
.O(\z[30]_INST_0_i_85_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_86
(.I0(x[14]),
.I1(x[12]),
.I2(x[8]),
.I3(x[27]),
.O(\z[30]_INST_0_i_86_n_0 ));
LUT4 #(
.INIT(16'h0001))
\z[30]_INST_0_i_87
(.I0(x[28]),
.I1(x[23]),
.I2(x[19]),
.I3(x[1]),
.O(\z[30]_INST_0_i_87_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_88
(.I0(x[0]),
.I1(x[26]),
.I2(x[16]),
.I3(x[5]),
.O(\z[30]_INST_0_i_88_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_89
(.I0(y[14]),
.I1(y[8]),
.I2(y[24]),
.I3(y[27]),
.O(\z[30]_INST_0_i_89_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_90
(.I0(y[7]),
.I1(y[26]),
.I2(y[17]),
.I3(y[6]),
.O(\z[30]_INST_0_i_90_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_91
(.I0(y[21]),
.I1(y[15]),
.I2(y[22]),
.I3(y[23]),
.O(\z[30]_INST_0_i_91_n_0 ));
LUT4 #(
.INIT(16'h0001))
\z[30]_INST_0_i_92
(.I0(y[19]),
.I1(y[28]),
.I2(y[9]),
.I3(y[3]),
.O(\z[30]_INST_0_i_92_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_93
(.I0(y[16]),
.I1(y[25]),
.I2(y[13]),
.I3(y[11]),
.O(\z[30]_INST_0_i_93_n_0 ));
LUT2 #(
.INIT(4'h6))
\z[31]_INST_0
(.I0(y[31]),
.I1(x[31]),
.O(z[31]));
LUT2 #(
.INIT(4'h2))
\z[3]_INST_0
(.I0(z_mantissa[3]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[3]));
LUT2 #(
.INIT(4'h2))
\z[4]_INST_0
(.I0(z_mantissa[4]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[4]));
LUT2 #(
.INIT(4'h2))
\z[5]_INST_0
(.I0(z_mantissa[5]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[5]));
LUT2 #(
.INIT(4'h2))
\z[6]_INST_0
(.I0(z_mantissa[6]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[6]));
LUT2 #(
.INIT(4'h2))
\z[7]_INST_0
(.I0(z_mantissa[7]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[7]));
LUT2 #(
.INIT(4'h2))
\z[8]_INST_0
(.I0(z_mantissa[8]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[8]));
LUT2 #(
.INIT(4'h2))
\z[9]_INST_0
(.I0(z_mantissa[9]),
.I1(\z[30]_INST_0_i_4_n_0 ),
.O(z[9]));
endmodule |
module affine_block_ieee754_fp_multiplier_1_0_ieee754_fp_multiplier
(z,
z_mantissa,
x,
y,
y_11__s_port_);
output [7:0]z;
output [22:0]z_mantissa;
input [30:0]x;
input [30:0]y;
input y_11__s_port_;
wire L1;
wire L1_carry__0_i_1_n_0;
wire L1_carry__0_i_2_n_0;
wire L1_carry__0_i_3_n_0;
wire L1_carry__0_i_4_n_0;
wire L1_carry__0_i_5_n_0;
wire L1_carry__0_i_6_n_0;
wire L1_carry__0_i_7_n_0;
wire L1_carry__0_i_8_n_0;
wire L1_carry__0_n_0;
wire L1_carry__0_n_1;
wire L1_carry__0_n_2;
wire L1_carry__0_n_3;
wire L1_carry__1_i_1_n_0;
wire L1_carry__1_i_2_n_0;
wire L1_carry__1_i_3_n_0;
wire L1_carry__1_i_4_n_0;
wire L1_carry__1_i_5_n_0;
wire L1_carry__1_i_6_n_0;
wire L1_carry__1_i_7_n_0;
wire L1_carry__1_i_8_n_0;
wire L1_carry__1_n_0;
wire L1_carry__1_n_1;
wire L1_carry__1_n_2;
wire L1_carry__1_n_3;
wire L1_carry__2_i_1_n_0;
wire L1_carry__2_i_2_n_0;
wire L1_carry__2_i_3_n_0;
wire L1_carry__2_i_4_n_0;
wire L1_carry__2_i_5_n_0;
wire L1_carry__2_i_6_n_0;
wire L1_carry__2_i_7_n_0;
wire L1_carry__2_n_1;
wire L1_carry__2_n_2;
wire L1_carry__2_n_3;
wire L1_carry_i_10_n_0;
wire L1_carry_i_11_n_0;
wire L1_carry_i_12_n_0;
wire L1_carry_i_13_n_0;
wire L1_carry_i_14_n_0;
wire L1_carry_i_15_n_0;
wire L1_carry_i_16_n_0;
wire L1_carry_i_17_n_0;
wire L1_carry_i_18_n_0;
wire L1_carry_i_19_n_0;
wire L1_carry_i_1_n_0;
wire L1_carry_i_20_n_0;
wire L1_carry_i_21_n_0;
wire L1_carry_i_22_n_0;
wire L1_carry_i_23_n_0;
wire L1_carry_i_24_n_0;
wire L1_carry_i_25_n_0;
wire L1_carry_i_26_n_0;
wire L1_carry_i_27_n_0;
wire L1_carry_i_28_n_0;
wire L1_carry_i_29_n_0;
wire L1_carry_i_2_n_0;
wire L1_carry_i_30_n_0;
wire L1_carry_i_31_n_0;
wire L1_carry_i_32_n_0;
wire L1_carry_i_33_n_0;
wire L1_carry_i_34_n_0;
wire L1_carry_i_35_n_0;
wire L1_carry_i_36_n_0;
wire L1_carry_i_37_n_0;
wire L1_carry_i_38_n_0;
wire L1_carry_i_39_n_0;
wire L1_carry_i_3_n_0;
wire L1_carry_i_40_n_0;
wire L1_carry_i_41_n_0;
wire L1_carry_i_42_n_0;
wire L1_carry_i_43_n_0;
wire L1_carry_i_44_n_0;
wire L1_carry_i_45_n_0;
wire L1_carry_i_46_n_0;
wire L1_carry_i_47_n_0;
wire L1_carry_i_48_n_0;
wire L1_carry_i_49_n_0;
wire L1_carry_i_4_n_0;
wire L1_carry_i_50_n_0;
wire L1_carry_i_51_n_0;
wire L1_carry_i_52_n_0;
wire L1_carry_i_53_n_0;
wire L1_carry_i_54_n_0;
wire L1_carry_i_5_n_0;
wire L1_carry_i_6_n_0;
wire L1_carry_i_7_n_0;
wire L1_carry_i_8_n_0;
wire L1_carry_i_9_n_0;
wire L1_carry_n_0;
wire L1_carry_n_1;
wire L1_carry_n_2;
wire L1_carry_n_3;
wire _carry__0_i_1_n_0;
wire _carry__0_i_2_n_0;
wire _carry__0_i_3_n_0;
wire _carry__0_i_4_n_0;
wire _carry__0_n_0;
wire _carry__0_n_1;
wire _carry__0_n_2;
wire _carry__0_n_3;
wire _carry__0_n_4;
wire _carry__0_n_5;
wire _carry__0_n_6;
wire _carry__0_n_7;
wire _carry__1_i_1_n_0;
wire _carry__1_i_2_n_0;
wire _carry__1_i_3_n_0;
wire _carry__1_i_4_n_0;
wire _carry__1_n_0;
wire _carry__1_n_1;
wire _carry__1_n_2;
wire _carry__1_n_3;
wire _carry__1_n_4;
wire _carry__1_n_5;
wire _carry__1_n_6;
wire _carry__1_n_7;
wire _carry__2_i_1_n_0;
wire _carry__2_i_2_n_0;
wire _carry__2_i_3_n_0;
wire _carry__2_i_4_n_0;
wire _carry__2_n_0;
wire _carry__2_n_1;
wire _carry__2_n_2;
wire _carry__2_n_3;
wire _carry__2_n_4;
wire _carry__2_n_5;
wire _carry__2_n_6;
wire _carry__2_n_7;
wire _carry__3_i_1_n_0;
wire _carry__3_i_2_n_0;
wire _carry__3_i_3_n_0;
wire _carry__3_i_4_n_0;
wire _carry__3_n_0;
wire _carry__3_n_1;
wire _carry__3_n_2;
wire _carry__3_n_3;
wire _carry__3_n_4;
wire _carry__3_n_5;
wire _carry__3_n_6;
wire _carry__3_n_7;
wire _carry__4_i_1_n_0;
wire _carry__4_i_2_n_0;
wire _carry__4_i_3_n_0;
wire _carry__4_i_4_n_0;
wire _carry__4_n_0;
wire _carry__4_n_1;
wire _carry__4_n_2;
wire _carry__4_n_3;
wire _carry__4_n_4;
wire _carry__4_n_5;
wire _carry__4_n_6;
wire _carry__4_n_7;
wire _carry__5_i_1_n_0;
wire _carry__5_i_2_n_0;
wire _carry__5_i_3_n_0;
wire _carry__5_i_4_n_0;
wire _carry__5_n_0;
wire _carry__5_n_1;
wire _carry__5_n_2;
wire _carry__5_n_3;
wire _carry__5_n_4;
wire _carry__5_n_5;
wire _carry__5_n_6;
wire _carry__5_n_7;
wire _carry__6_i_1_n_0;
wire _carry__6_i_2_n_0;
wire _carry__6_n_3;
wire _carry__6_n_6;
wire _carry__6_n_7;
wire _carry_i_10_n_0;
wire _carry_i_11_n_0;
wire _carry_i_12_n_0;
wire _carry_i_13_n_0;
wire _carry_i_14_n_0;
wire _carry_i_15_n_0;
wire _carry_i_16_n_0;
wire _carry_i_17_n_0;
wire _carry_i_18_n_0;
wire _carry_i_19_n_0;
wire _carry_i_1_n_0;
wire _carry_i_20_n_0;
wire _carry_i_21_n_0;
wire _carry_i_22_n_0;
wire _carry_i_23_n_0;
wire _carry_i_24_n_0;
wire _carry_i_2_n_0;
wire _carry_i_3_n_0;
wire _carry_i_4_n_0;
wire _carry_i_6_n_0;
wire _carry_i_7_n_0;
wire _carry_i_8_n_0;
wire _carry_i_9_n_0;
wire _carry_n_0;
wire _carry_n_1;
wire _carry_n_2;
wire _carry_n_3;
wire _carry_n_4;
wire _carry_n_5;
wire _carry_n_6;
wire _carry_n_7;
wire [7:0]data0;
wire [7:0]data1;
wire [47:0]msb1__1;
wire msb1_n_106;
wire msb1_n_107;
wire msb1_n_108;
wire msb1_n_109;
wire msb1_n_110;
wire msb1_n_111;
wire msb1_n_112;
wire msb1_n_113;
wire msb1_n_114;
wire msb1_n_115;
wire msb1_n_116;
wire msb1_n_117;
wire msb1_n_118;
wire msb1_n_119;
wire msb1_n_120;
wire msb1_n_121;
wire msb1_n_122;
wire msb1_n_123;
wire msb1_n_124;
wire msb1_n_125;
wire msb1_n_126;
wire msb1_n_127;
wire msb1_n_128;
wire msb1_n_129;
wire msb1_n_130;
wire msb1_n_131;
wire msb1_n_132;
wire msb1_n_133;
wire msb1_n_134;
wire msb1_n_135;
wire msb1_n_136;
wire msb1_n_137;
wire msb1_n_138;
wire msb1_n_139;
wire msb1_n_140;
wire msb1_n_141;
wire msb1_n_142;
wire msb1_n_143;
wire msb1_n_144;
wire msb1_n_145;
wire msb1_n_146;
wire msb1_n_147;
wire msb1_n_148;
wire msb1_n_149;
wire msb1_n_150;
wire msb1_n_151;
wire msb1_n_152;
wire msb1_n_153;
wire msb1_n_58;
wire msb1_n_59;
wire msb1_n_60;
wire msb1_n_61;
wire msb1_n_62;
wire msb1_n_63;
wire msb1_n_64;
wire msb1_n_65;
wire msb1_n_66;
wire msb1_n_67;
wire msb1_n_68;
wire msb1_n_69;
wire msb1_n_70;
wire msb1_n_71;
wire msb1_n_72;
wire msb1_n_73;
wire msb1_n_74;
wire msb1_n_75;
wire msb1_n_76;
wire msb1_n_77;
wire msb1_n_78;
wire msb1_n_79;
wire msb1_n_80;
wire msb1_n_81;
wire msb1_n_82;
wire msb1_n_83;
wire msb1_n_84;
wire msb1_n_85;
wire msb1_n_86;
wire msb1_n_87;
wire msb1_n_88;
wire [1:1]p_0_in;
wire [22:0]sel0;
wire [30:0]x;
wire [30:0]y;
wire y_11__s_net_1;
wire [7:0]z;
wire \z[11]_INST_0_i_1_n_0 ;
wire \z[11]_INST_0_i_1_n_1 ;
wire \z[11]_INST_0_i_1_n_2 ;
wire \z[11]_INST_0_i_1_n_3 ;
wire \z[11]_INST_0_i_3_n_0 ;
wire \z[11]_INST_0_i_6_n_0 ;
wire \z[11]_INST_0_i_7_n_0 ;
wire \z[11]_INST_0_i_8_n_0 ;
wire \z[11]_INST_0_i_9_n_0 ;
wire \z[15]_INST_0_i_1_n_0 ;
wire \z[15]_INST_0_i_1_n_1 ;
wire \z[15]_INST_0_i_1_n_2 ;
wire \z[15]_INST_0_i_1_n_3 ;
wire \z[15]_INST_0_i_6_n_0 ;
wire \z[15]_INST_0_i_7_n_0 ;
wire \z[15]_INST_0_i_8_n_0 ;
wire \z[19]_INST_0_i_1_n_0 ;
wire \z[19]_INST_0_i_1_n_1 ;
wire \z[19]_INST_0_i_1_n_2 ;
wire \z[19]_INST_0_i_1_n_3 ;
wire \z[22]_INST_0_i_1_n_2 ;
wire \z[22]_INST_0_i_1_n_3 ;
wire \z[22]_INST_0_i_5_n_0 ;
wire \z[22]_INST_0_i_6_n_0 ;
wire \z[30]_INST_0_i_100_n_0 ;
wire \z[30]_INST_0_i_101_n_0 ;
wire \z[30]_INST_0_i_102_n_0 ;
wire \z[30]_INST_0_i_103_n_0 ;
wire \z[30]_INST_0_i_104_n_0 ;
wire \z[30]_INST_0_i_105_n_0 ;
wire \z[30]_INST_0_i_106_n_0 ;
wire \z[30]_INST_0_i_107_n_0 ;
wire \z[30]_INST_0_i_108_n_0 ;
wire \z[30]_INST_0_i_109_n_0 ;
wire \z[30]_INST_0_i_110_n_0 ;
wire \z[30]_INST_0_i_111_n_0 ;
wire \z[30]_INST_0_i_112_n_0 ;
wire \z[30]_INST_0_i_113_n_0 ;
wire \z[30]_INST_0_i_114_n_0 ;
wire \z[30]_INST_0_i_115_n_0 ;
wire \z[30]_INST_0_i_116_n_0 ;
wire \z[30]_INST_0_i_117_n_0 ;
wire \z[30]_INST_0_i_118_n_0 ;
wire \z[30]_INST_0_i_119_n_0 ;
wire \z[30]_INST_0_i_11_n_0 ;
wire \z[30]_INST_0_i_120_n_0 ;
wire \z[30]_INST_0_i_121_n_0 ;
wire \z[30]_INST_0_i_122_n_0 ;
wire \z[30]_INST_0_i_123_n_0 ;
wire \z[30]_INST_0_i_124_n_0 ;
wire \z[30]_INST_0_i_125_n_0 ;
wire \z[30]_INST_0_i_126_n_0 ;
wire \z[30]_INST_0_i_127_n_0 ;
wire \z[30]_INST_0_i_128_n_0 ;
wire \z[30]_INST_0_i_129_n_0 ;
wire \z[30]_INST_0_i_130_n_0 ;
wire \z[30]_INST_0_i_131_n_0 ;
wire \z[30]_INST_0_i_132_n_0 ;
wire \z[30]_INST_0_i_133_n_0 ;
wire \z[30]_INST_0_i_134_n_0 ;
wire \z[30]_INST_0_i_135_n_0 ;
wire \z[30]_INST_0_i_136_n_0 ;
wire \z[30]_INST_0_i_137_n_0 ;
wire \z[30]_INST_0_i_138_n_0 ;
wire \z[30]_INST_0_i_139_n_0 ;
wire \z[30]_INST_0_i_13_n_0 ;
wire \z[30]_INST_0_i_140_n_0 ;
wire \z[30]_INST_0_i_141_n_0 ;
wire \z[30]_INST_0_i_142_n_0 ;
wire \z[30]_INST_0_i_143_n_0 ;
wire \z[30]_INST_0_i_144_n_0 ;
wire \z[30]_INST_0_i_145_n_0 ;
wire \z[30]_INST_0_i_146_n_0 ;
wire \z[30]_INST_0_i_147_n_0 ;
wire \z[30]_INST_0_i_148_n_0 ;
wire \z[30]_INST_0_i_149_n_0 ;
wire \z[30]_INST_0_i_14_n_0 ;
wire \z[30]_INST_0_i_150_n_0 ;
wire \z[30]_INST_0_i_151_n_0 ;
wire \z[30]_INST_0_i_152_n_0 ;
wire \z[30]_INST_0_i_153_n_0 ;
wire \z[30]_INST_0_i_154_n_0 ;
wire \z[30]_INST_0_i_155_n_0 ;
wire \z[30]_INST_0_i_156_n_0 ;
wire \z[30]_INST_0_i_157_n_0 ;
wire \z[30]_INST_0_i_158_n_0 ;
wire \z[30]_INST_0_i_159_n_0 ;
wire \z[30]_INST_0_i_15_n_0 ;
wire \z[30]_INST_0_i_160_n_0 ;
wire \z[30]_INST_0_i_161_n_0 ;
wire \z[30]_INST_0_i_162_n_0 ;
wire \z[30]_INST_0_i_163_n_0 ;
wire \z[30]_INST_0_i_164_n_0 ;
wire \z[30]_INST_0_i_165_n_0 ;
wire \z[30]_INST_0_i_166_n_0 ;
wire \z[30]_INST_0_i_167_n_0 ;
wire \z[30]_INST_0_i_168_n_0 ;
wire \z[30]_INST_0_i_169_n_0 ;
wire \z[30]_INST_0_i_16_n_0 ;
wire \z[30]_INST_0_i_170_n_0 ;
wire \z[30]_INST_0_i_171_n_0 ;
wire \z[30]_INST_0_i_172_n_0 ;
wire \z[30]_INST_0_i_173_n_0 ;
wire \z[30]_INST_0_i_174_n_0 ;
wire \z[30]_INST_0_i_175_n_0 ;
wire \z[30]_INST_0_i_176_n_0 ;
wire \z[30]_INST_0_i_177_n_0 ;
wire \z[30]_INST_0_i_178_n_0 ;
wire \z[30]_INST_0_i_179_n_0 ;
wire \z[30]_INST_0_i_17_n_0 ;
wire \z[30]_INST_0_i_180_n_0 ;
wire \z[30]_INST_0_i_181_n_0 ;
wire \z[30]_INST_0_i_182_n_0 ;
wire \z[30]_INST_0_i_183_n_0 ;
wire \z[30]_INST_0_i_184_n_0 ;
wire \z[30]_INST_0_i_185_n_0 ;
wire \z[30]_INST_0_i_186_n_0 ;
wire \z[30]_INST_0_i_187_n_0 ;
wire \z[30]_INST_0_i_188_n_0 ;
wire \z[30]_INST_0_i_189_n_0 ;
wire \z[30]_INST_0_i_18_n_0 ;
wire \z[30]_INST_0_i_190_n_0 ;
wire \z[30]_INST_0_i_191_n_0 ;
wire \z[30]_INST_0_i_192_n_0 ;
wire \z[30]_INST_0_i_193_n_0 ;
wire \z[30]_INST_0_i_194_n_0 ;
wire \z[30]_INST_0_i_195_n_0 ;
wire \z[30]_INST_0_i_196_n_0 ;
wire \z[30]_INST_0_i_197_n_0 ;
wire \z[30]_INST_0_i_198_n_0 ;
wire \z[30]_INST_0_i_199_n_0 ;
wire \z[30]_INST_0_i_19_n_0 ;
wire \z[30]_INST_0_i_1_n_0 ;
wire \z[30]_INST_0_i_200_n_0 ;
wire \z[30]_INST_0_i_201_n_0 ;
wire \z[30]_INST_0_i_202_n_0 ;
wire \z[30]_INST_0_i_203_n_0 ;
wire \z[30]_INST_0_i_204_n_0 ;
wire \z[30]_INST_0_i_205_n_0 ;
wire \z[30]_INST_0_i_206_n_0 ;
wire \z[30]_INST_0_i_207_n_0 ;
wire \z[30]_INST_0_i_208_n_0 ;
wire \z[30]_INST_0_i_209_n_0 ;
wire \z[30]_INST_0_i_20_n_0 ;
wire \z[30]_INST_0_i_210_n_0 ;
wire \z[30]_INST_0_i_211_n_0 ;
wire \z[30]_INST_0_i_212_n_0 ;
wire \z[30]_INST_0_i_213_n_0 ;
wire \z[30]_INST_0_i_214_n_0 ;
wire \z[30]_INST_0_i_215_n_0 ;
wire \z[30]_INST_0_i_216_n_0 ;
wire \z[30]_INST_0_i_217_n_0 ;
wire \z[30]_INST_0_i_218_n_0 ;
wire \z[30]_INST_0_i_219_n_0 ;
wire \z[30]_INST_0_i_21_n_0 ;
wire \z[30]_INST_0_i_220_n_0 ;
wire \z[30]_INST_0_i_221_n_0 ;
wire \z[30]_INST_0_i_222_n_0 ;
wire \z[30]_INST_0_i_223_n_0 ;
wire \z[30]_INST_0_i_224_n_0 ;
wire \z[30]_INST_0_i_225_n_0 ;
wire \z[30]_INST_0_i_226_n_0 ;
wire \z[30]_INST_0_i_227_n_0 ;
wire \z[30]_INST_0_i_228_n_0 ;
wire \z[30]_INST_0_i_229_n_0 ;
wire \z[30]_INST_0_i_22_n_0 ;
wire \z[30]_INST_0_i_230_n_0 ;
wire \z[30]_INST_0_i_231_n_0 ;
wire \z[30]_INST_0_i_232_n_0 ;
wire \z[30]_INST_0_i_233_n_0 ;
wire \z[30]_INST_0_i_234_n_0 ;
wire \z[30]_INST_0_i_235_n_0 ;
wire \z[30]_INST_0_i_236_n_0 ;
wire \z[30]_INST_0_i_237_n_0 ;
wire \z[30]_INST_0_i_238_n_0 ;
wire \z[30]_INST_0_i_239_n_0 ;
wire \z[30]_INST_0_i_240_n_0 ;
wire \z[30]_INST_0_i_241_n_0 ;
wire \z[30]_INST_0_i_242_n_0 ;
wire \z[30]_INST_0_i_243_n_0 ;
wire \z[30]_INST_0_i_244_n_0 ;
wire \z[30]_INST_0_i_245_n_0 ;
wire \z[30]_INST_0_i_246_n_0 ;
wire \z[30]_INST_0_i_29_n_0 ;
wire \z[30]_INST_0_i_2_n_0 ;
wire \z[30]_INST_0_i_30_n_0 ;
wire \z[30]_INST_0_i_31_n_0 ;
wire \z[30]_INST_0_i_32_n_0 ;
wire \z[30]_INST_0_i_33_n_0 ;
wire \z[30]_INST_0_i_34_n_0 ;
wire \z[30]_INST_0_i_35_n_0 ;
wire \z[30]_INST_0_i_36_n_0 ;
wire \z[30]_INST_0_i_37_n_0 ;
wire \z[30]_INST_0_i_38_n_0 ;
wire \z[30]_INST_0_i_39_n_0 ;
wire \z[30]_INST_0_i_3_n_0 ;
wire \z[30]_INST_0_i_40_n_0 ;
wire \z[30]_INST_0_i_41_n_0 ;
wire \z[30]_INST_0_i_42_n_0 ;
wire \z[30]_INST_0_i_43_n_0 ;
wire \z[30]_INST_0_i_44_n_0 ;
wire \z[30]_INST_0_i_45_n_0 ;
wire \z[30]_INST_0_i_46_n_0 ;
wire \z[30]_INST_0_i_47_n_0 ;
wire \z[30]_INST_0_i_48_n_0 ;
wire \z[30]_INST_0_i_49_n_0 ;
wire \z[30]_INST_0_i_50_n_0 ;
wire \z[30]_INST_0_i_51_n_0 ;
wire \z[30]_INST_0_i_52_n_0 ;
wire \z[30]_INST_0_i_53_n_0 ;
wire \z[30]_INST_0_i_54_n_0 ;
wire \z[30]_INST_0_i_55_n_0 ;
wire \z[30]_INST_0_i_56_n_0 ;
wire \z[30]_INST_0_i_57_n_0 ;
wire \z[30]_INST_0_i_58_n_0 ;
wire \z[30]_INST_0_i_59_n_0 ;
wire \z[30]_INST_0_i_5_n_0 ;
wire \z[30]_INST_0_i_60_n_0 ;
wire \z[30]_INST_0_i_61_n_0 ;
wire \z[30]_INST_0_i_62_n_0 ;
wire \z[30]_INST_0_i_63_n_0 ;
wire \z[30]_INST_0_i_64_n_0 ;
wire \z[30]_INST_0_i_65_n_0 ;
wire \z[30]_INST_0_i_66_n_0 ;
wire \z[30]_INST_0_i_67_n_0 ;
wire \z[30]_INST_0_i_68_n_0 ;
wire \z[30]_INST_0_i_69_n_0 ;
wire \z[30]_INST_0_i_6_n_0 ;
wire \z[30]_INST_0_i_70_n_0 ;
wire \z[30]_INST_0_i_71_n_0 ;
wire \z[30]_INST_0_i_72_n_0 ;
wire \z[30]_INST_0_i_73_n_0 ;
wire \z[30]_INST_0_i_74_n_0 ;
wire \z[30]_INST_0_i_75_n_0 ;
wire \z[30]_INST_0_i_76_n_0 ;
wire \z[30]_INST_0_i_77_n_0 ;
wire \z[30]_INST_0_i_78_n_0 ;
wire \z[30]_INST_0_i_79_n_0 ;
wire \z[30]_INST_0_i_80_n_0 ;
wire \z[30]_INST_0_i_81_n_0 ;
wire \z[30]_INST_0_i_82_n_0 ;
wire \z[30]_INST_0_i_83_n_0 ;
wire \z[30]_INST_0_i_94_n_0 ;
wire \z[30]_INST_0_i_95_n_0 ;
wire \z[30]_INST_0_i_96_n_0 ;
wire \z[30]_INST_0_i_97_n_0 ;
wire \z[30]_INST_0_i_98_n_0 ;
wire \z[30]_INST_0_i_99_n_0 ;
wire \z[30]_INST_0_i_9_n_0 ;
wire \z[3]_INST_0_i_1_n_0 ;
wire \z[3]_INST_0_i_1_n_1 ;
wire \z[3]_INST_0_i_1_n_2 ;
wire \z[3]_INST_0_i_1_n_3 ;
wire \z[3]_INST_0_i_2_n_0 ;
wire \z[3]_INST_0_i_3_n_0 ;
wire \z[3]_INST_0_i_5_n_0 ;
wire \z[3]_INST_0_i_6_n_0 ;
wire \z[3]_INST_0_i_7_n_0 ;
wire \z[3]_INST_0_i_8_n_0 ;
wire \z[3]_INST_0_i_9_n_0 ;
wire \z[7]_INST_0_i_10_n_0 ;
wire \z[7]_INST_0_i_11_n_0 ;
wire \z[7]_INST_0_i_12_n_0 ;
wire \z[7]_INST_0_i_1_n_0 ;
wire \z[7]_INST_0_i_1_n_1 ;
wire \z[7]_INST_0_i_1_n_2 ;
wire \z[7]_INST_0_i_1_n_3 ;
wire \z[7]_INST_0_i_6_n_0 ;
wire \z[7]_INST_0_i_7_n_0 ;
wire \z[7]_INST_0_i_8_n_0 ;
wire \z[7]_INST_0_i_9_n_0 ;
wire z_exponent0__0_carry__0_i_1_n_0;
wire z_exponent0__0_carry__0_i_2_n_0;
wire z_exponent0__0_carry__0_i_3_n_0;
wire z_exponent0__0_carry__0_i_4_n_0;
wire z_exponent0__0_carry__0_i_5_n_0;
wire z_exponent0__0_carry__0_i_6_n_0;
wire z_exponent0__0_carry__0_i_7_n_0;
wire z_exponent0__0_carry__0_i_8_n_0;
wire z_exponent0__0_carry__0_n_1;
wire z_exponent0__0_carry__0_n_2;
wire z_exponent0__0_carry__0_n_3;
wire z_exponent0__0_carry_i_1_n_0;
wire z_exponent0__0_carry_i_2_n_0;
wire z_exponent0__0_carry_i_3_n_0;
wire z_exponent0__0_carry_i_4_n_0;
wire z_exponent0__0_carry_i_5_n_0;
wire z_exponent0__0_carry_i_6_n_0;
wire z_exponent0__0_carry_i_7_n_0;
wire z_exponent0__0_carry_n_0;
wire z_exponent0__0_carry_n_1;
wire z_exponent0__0_carry_n_2;
wire z_exponent0__0_carry_n_3;
wire z_exponent1_carry__0_n_1;
wire z_exponent1_carry__0_n_2;
wire z_exponent1_carry__0_n_3;
wire z_exponent1_carry_i_1__0_n_0;
wire z_exponent1_carry_i_1_n_0;
wire z_exponent1_carry_i_2__0_n_0;
wire z_exponent1_carry_i_2_n_0;
wire z_exponent1_carry_i_3__0_n_0;
wire z_exponent1_carry_i_3_n_0;
wire z_exponent1_carry_i_4__0_n_0;
wire z_exponent1_carry_i_4_n_0;
wire z_exponent1_carry_i_5_n_0;
wire z_exponent1_carry_n_0;
wire z_exponent1_carry_n_1;
wire z_exponent1_carry_n_2;
wire z_exponent1_carry_n_3;
wire [22:0]z_mantissa;
wire [3:0]NLW_L1_carry_O_UNCONNECTED;
wire [3:0]NLW_L1_carry__0_O_UNCONNECTED;
wire [3:0]NLW_L1_carry__1_O_UNCONNECTED;
wire [3:0]NLW_L1_carry__2_O_UNCONNECTED;
wire [3:1]NLW__carry__6_CO_UNCONNECTED;
wire [3:2]NLW__carry__6_O_UNCONNECTED;
wire NLW_msb1_CARRYCASCOUT_UNCONNECTED;
wire NLW_msb1_MULTSIGNOUT_UNCONNECTED;
wire NLW_msb1_OVERFLOW_UNCONNECTED;
wire NLW_msb1_PATTERNBDETECT_UNCONNECTED;
wire NLW_msb1_PATTERNDETECT_UNCONNECTED;
wire NLW_msb1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_msb1_ACOUT_UNCONNECTED;
wire [17:0]NLW_msb1_BCOUT_UNCONNECTED;
wire [3:0]NLW_msb1_CARRYOUT_UNCONNECTED;
wire NLW_msb1__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_msb1__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_msb1__0_OVERFLOW_UNCONNECTED;
wire NLW_msb1__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_msb1__0_PATTERNDETECT_UNCONNECTED;
wire NLW_msb1__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_msb1__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_msb1__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_msb1__0_CARRYOUT_UNCONNECTED;
wire [47:31]NLW_msb1__0_P_UNCONNECTED;
wire [47:0]NLW_msb1__0_PCOUT_UNCONNECTED;
wire [3:2]\NLW_z[22]_INST_0_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_z[22]_INST_0_i_1_O_UNCONNECTED ;
wire [3:3]NLW_z_exponent0__0_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_z_exponent1_carry__0_CO_UNCONNECTED;
assign y_11__s_net_1 = y_11__s_port_;
CARRY4 L1_carry
(.CI(1'b0),
.CO({L1_carry_n_0,L1_carry_n_1,L1_carry_n_2,L1_carry_n_3}),
.CYINIT(1'b1),
.DI({L1_carry_i_1_n_0,L1_carry_i_2_n_0,L1_carry_i_3_n_0,L1_carry_i_4_n_0}),
.O(NLW_L1_carry_O_UNCONNECTED[3:0]),
.S({L1_carry_i_5_n_0,L1_carry_i_6_n_0,L1_carry_i_7_n_0,L1_carry_i_8_n_0}));
CARRY4 L1_carry__0
(.CI(L1_carry_n_0),
.CO({L1_carry__0_n_0,L1_carry__0_n_1,L1_carry__0_n_2,L1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({L1_carry__0_i_1_n_0,L1_carry__0_i_2_n_0,L1_carry__0_i_3_n_0,L1_carry__0_i_4_n_0}),
.O(NLW_L1_carry__0_O_UNCONNECTED[3:0]),
.S({L1_carry__0_i_5_n_0,L1_carry__0_i_6_n_0,L1_carry__0_i_7_n_0,L1_carry__0_i_8_n_0}));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__0_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__0_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__0_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__0_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_4_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__0_i_5
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__0_i_6
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_6_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__0_i_7
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_7_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__0_i_8
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__0_i_8_n_0));
CARRY4 L1_carry__1
(.CI(L1_carry__0_n_0),
.CO({L1_carry__1_n_0,L1_carry__1_n_1,L1_carry__1_n_2,L1_carry__1_n_3}),
.CYINIT(1'b0),
.DI({L1_carry__1_i_1_n_0,L1_carry__1_i_2_n_0,L1_carry__1_i_3_n_0,L1_carry__1_i_4_n_0}),
.O(NLW_L1_carry__1_O_UNCONNECTED[3:0]),
.S({L1_carry__1_i_5_n_0,L1_carry__1_i_6_n_0,L1_carry__1_i_7_n_0,L1_carry__1_i_8_n_0}));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__1_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__1_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__1_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__1_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_4_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__1_i_5
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_5_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__1_i_6
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_6_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__1_i_7
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_7_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__1_i_8
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__1_i_8_n_0));
CARRY4 L1_carry__2
(.CI(L1_carry__1_n_0),
.CO({L1,L1_carry__2_n_1,L1_carry__2_n_2,L1_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,L1_carry__2_i_1_n_0,L1_carry__2_i_2_n_0,L1_carry__2_i_3_n_0}),
.O(NLW_L1_carry__2_O_UNCONNECTED[3:0]),
.S({L1_carry__2_i_4_n_0,L1_carry__2_i_5_n_0,L1_carry__2_i_6_n_0,L1_carry__2_i_7_n_0}));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__2_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_1_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__2_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_2_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry__2_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__2_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_4_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__2_i_5
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_5_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__2_i_6
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_6_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry__2_i_7
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry__2_i_7_n_0));
LUT6 #(
.INIT(64'hAAA2FFFF00000000))
L1_carry_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry_i_1_n_0));
LUT6 #(
.INIT(64'h4555FFFF45554555))
L1_carry_i_10
(.I0(L1_carry_i_24_n_0),
.I1(L1_carry_i_25_n_0),
.I2(L1_carry_i_26_n_0),
.I3(L1_carry_i_27_n_0),
.I4(L1_carry_i_28_n_0),
.I5(L1_carry_i_29_n_0),
.O(L1_carry_i_10_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFF7550000))
L1_carry_i_11
(.I0(L1_carry_i_30_n_0),
.I1(L1_carry_i_31_n_0),
.I2(L1_carry_i_32_n_0),
.I3(L1_carry_i_33_n_0),
.I4(L1_carry_i_34_n_0),
.I5(L1_carry_i_35_n_0),
.O(L1_carry_i_11_n_0));
LUT3 #(
.INIT(8'h2A))
L1_carry_i_12
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_22_n_0),
.I2(L1_carry_i_19_n_0),
.O(L1_carry_i_12_n_0));
LUT6 #(
.INIT(64'h0001000000000000))
L1_carry_i_13
(.I0(msb1__1[40]),
.I1(msb1__1[41]),
.I2(msb1__1[43]),
.I3(msb1__1[42]),
.I4(L1_carry_i_34_n_0),
.I5(L1_carry_i_23_n_0),
.O(L1_carry_i_13_n_0));
LUT5 #(
.INIT(32'hA9AA5555))
L1_carry_i_14
(.I0(L1_carry_i_12_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_10_n_0),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.O(L1_carry_i_14_n_0));
LUT6 #(
.INIT(64'h0200AAAAFDFF5555))
L1_carry_i_15
(.I0(L1_carry_i_12_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_10_n_0),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry_i_15_n_0));
LUT3 #(
.INIT(8'h65))
L1_carry_i_16
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(_carry_i_1_n_0),
.O(L1_carry_i_16_n_0));
LUT4 #(
.INIT(16'h10EF))
L1_carry_i_17
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(_carry_i_1_n_0),
.I3(L1_carry_i_9_n_0),
.O(L1_carry_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h00000002))
L1_carry_i_18
(.I0(L1_carry_i_34_n_0),
.I1(msb1__1[42]),
.I2(msb1__1[43]),
.I3(msb1__1[41]),
.I4(msb1__1[40]),
.O(L1_carry_i_18_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h00000002))
L1_carry_i_19
(.I0(L1_carry_i_36_n_0),
.I1(msb1__1[26]),
.I2(msb1__1[27]),
.I3(msb1__1[25]),
.I4(msb1__1[24]),
.O(L1_carry_i_19_n_0));
LUT2 #(
.INIT(4'hB))
L1_carry_i_2
(.I0(L1_carry_i_14_n_0),
.I1(L1_carry_i_15_n_0),
.O(L1_carry_i_2_n_0));
LUT4 #(
.INIT(16'h0001))
L1_carry_i_20
(.I0(msb1__1[10]),
.I1(msb1__1[11]),
.I2(msb1__1[9]),
.I3(msb1__1[8]),
.O(L1_carry_i_20_n_0));
LUT4 #(
.INIT(16'hFFFE))
L1_carry_i_21
(.I0(msb1__1[14]),
.I1(msb1__1[15]),
.I2(msb1__1[13]),
.I3(msb1__1[12]),
.O(L1_carry_i_21_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000002))
L1_carry_i_22
(.I0(L1_carry_i_37_n_0),
.I1(msb1__1[16]),
.I2(msb1__1[17]),
.I3(msb1__1[19]),
.I4(msb1__1[18]),
.O(L1_carry_i_22_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00000002))
L1_carry_i_23
(.I0(L1_carry_i_33_n_0),
.I1(msb1__1[32]),
.I2(msb1__1[33]),
.I3(msb1__1[35]),
.I4(msb1__1[34]),
.O(L1_carry_i_23_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF000EFFFF))
L1_carry_i_24
(.I0(msb1__1[39]),
.I1(msb1__1[38]),
.I2(msb1__1[41]),
.I3(msb1__1[40]),
.I4(L1_carry_i_29_n_0),
.I5(L1_carry_i_38_n_0),
.O(L1_carry_i_24_n_0));
LUT6 #(
.INIT(64'h000000000000F100))
L1_carry_i_25
(.I0(L1_carry_i_39_n_0),
.I1(L1_carry_i_40_n_0),
.I2(L1_carry_i_41_n_0),
.I3(L1_carry_i_42_n_0),
.I4(msb1__1[35]),
.I5(msb1__1[34]),
.O(L1_carry_i_25_n_0));
LUT6 #(
.INIT(64'h1111110011111101))
L1_carry_i_26
(.I0(msb1__1[37]),
.I1(msb1__1[36]),
.I2(msb1__1[33]),
.I3(msb1__1[34]),
.I4(msb1__1[35]),
.I5(msb1__1[32]),
.O(L1_carry_i_26_n_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_27
(.I0(msb1__1[41]),
.I1(msb1__1[40]),
.O(L1_carry_i_27_n_0));
LUT6 #(
.INIT(64'h1111111011111111))
L1_carry_i_28
(.I0(msb1__1[45]),
.I1(msb1__1[44]),
.I2(L1_carry_i_43_n_0),
.I3(L1_carry_i_44_n_0),
.I4(L1_carry_i_39_n_0),
.I5(L1_carry_i_45_n_0),
.O(L1_carry_i_28_n_0));
LUT2 #(
.INIT(4'h1))
L1_carry_i_29
(.I0(msb1__1[46]),
.I1(msb1__1[47]),
.O(L1_carry_i_29_n_0));
LUT2 #(
.INIT(4'hB))
L1_carry_i_3
(.I0(L1_carry_i_16_n_0),
.I1(L1_carry_i_17_n_0),
.O(L1_carry_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_30
(.I0(msb1__1[40]),
.I1(msb1__1[41]),
.I2(msb1__1[43]),
.I3(msb1__1[42]),
.O(L1_carry_i_30_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_31
(.I0(msb1__1[34]),
.I1(msb1__1[35]),
.I2(msb1__1[33]),
.I3(msb1__1[32]),
.O(L1_carry_i_31_n_0));
LUT6 #(
.INIT(64'h8A888A888A88AA88))
L1_carry_i_32
(.I0(L1_carry_i_36_n_0),
.I1(L1_carry_i_46_n_0),
.I2(L1_carry_i_47_n_0),
.I3(L1_carry_i_37_n_0),
.I4(L1_carry_i_20_n_0),
.I5(L1_carry_i_21_n_0),
.O(L1_carry_i_32_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_33
(.I0(msb1__1[37]),
.I1(msb1__1[36]),
.I2(msb1__1[38]),
.I3(msb1__1[39]),
.O(L1_carry_i_33_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_34
(.I0(msb1__1[47]),
.I1(msb1__1[46]),
.I2(msb1__1[45]),
.I3(msb1__1[44]),
.O(L1_carry_i_34_n_0));
LUT6 #(
.INIT(64'h0000400000000000))
L1_carry_i_35
(.I0(L1_carry_i_48_n_0),
.I1(L1_carry_i_49_n_0),
.I2(L1_carry_i_34_n_0),
.I3(L1_carry_i_36_n_0),
.I4(L1_carry_i_21_n_0),
.I5(L1_carry_i_37_n_0),
.O(L1_carry_i_35_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_36
(.I0(msb1__1[28]),
.I1(msb1__1[29]),
.I2(msb1__1[30]),
.I3(msb1__1[31]),
.O(L1_carry_i_36_n_0));
LUT4 #(
.INIT(16'h0001))
L1_carry_i_37
(.I0(msb1__1[23]),
.I1(msb1__1[22]),
.I2(msb1__1[20]),
.I3(msb1__1[21]),
.O(L1_carry_i_37_n_0));
LUT2 #(
.INIT(4'hE))
L1_carry_i_38
(.I0(msb1__1[42]),
.I1(msb1__1[43]),
.O(L1_carry_i_38_n_0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'hFFFE))
L1_carry_i_39
(.I0(msb1__1[23]),
.I1(msb1__1[22]),
.I2(msb1__1[18]),
.I3(msb1__1[19]),
.O(L1_carry_i_39_n_0));
LUT2 #(
.INIT(4'hD))
L1_carry_i_4
(.I0(_carry_i_1_n_0),
.I1(L1_carry_i_10_n_0),
.O(L1_carry_i_4_n_0));
LUT6 #(
.INIT(64'h000000000000FFF2))
L1_carry_i_40
(.I0(L1_carry_i_50_n_0),
.I1(L1_carry_i_51_n_0),
.I2(msb1__1[15]),
.I3(msb1__1[14]),
.I4(msb1__1[17]),
.I5(msb1__1[16]),
.O(L1_carry_i_40_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFE0FF))
L1_carry_i_41
(.I0(msb1__1[21]),
.I1(msb1__1[20]),
.I2(L1_carry_i_52_n_0),
.I3(L1_carry_i_53_n_0),
.I4(msb1__1[25]),
.I5(msb1__1[24]),
.O(L1_carry_i_41_n_0));
LUT6 #(
.INIT(64'h1111111111110001))
L1_carry_i_42
(.I0(msb1__1[30]),
.I1(msb1__1[31]),
.I2(msb1__1[26]),
.I3(msb1__1[27]),
.I4(msb1__1[29]),
.I5(msb1__1[28]),
.O(L1_carry_i_42_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFFFF))
L1_carry_i_43
(.I0(msb1__1[2]),
.I1(msb1__1[3]),
.I2(msb1__1[26]),
.I3(msb1__1[27]),
.I4(L1_carry_i_54_n_0),
.I5(L1_carry_i_38_n_0),
.O(L1_carry_i_43_n_0));
LUT4 #(
.INIT(16'hFFFE))
L1_carry_i_44
(.I0(msb1__1[7]),
.I1(msb1__1[6]),
.I2(msb1__1[10]),
.I3(msb1__1[11]),
.O(L1_carry_i_44_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
L1_carry_i_45
(.I0(msb1__1[34]),
.I1(msb1__1[35]),
.I2(msb1__1[15]),
.I3(msb1__1[14]),
.I4(msb1__1[31]),
.I5(msb1__1[30]),
.O(L1_carry_i_45_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hFFFE))
L1_carry_i_46
(.I0(msb1__1[24]),
.I1(msb1__1[25]),
.I2(msb1__1[27]),
.I3(msb1__1[26]),
.O(L1_carry_i_46_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
L1_carry_i_47
(.I0(msb1__1[18]),
.I1(msb1__1[19]),
.I2(msb1__1[17]),
.I3(msb1__1[16]),
.O(L1_carry_i_47_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
L1_carry_i_48
(.I0(msb1__1[7]),
.I1(msb1__1[6]),
.I2(msb1__1[39]),
.I3(msb1__1[38]),
.I4(msb1__1[36]),
.I5(msb1__1[37]),
.O(L1_carry_i_48_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_49
(.I0(msb1__1[5]),
.I1(msb1__1[4]),
.O(L1_carry_i_49_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
L1_carry_i_5
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(L1_carry_i_5_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF1))
L1_carry_i_50
(.I0(msb1__1[4]),
.I1(msb1__1[5]),
.I2(msb1__1[11]),
.I3(msb1__1[10]),
.I4(msb1__1[6]),
.I5(msb1__1[7]),
.O(L1_carry_i_50_n_0));
LUT6 #(
.INIT(64'hEEEEEEEEEEEEFFFE))
L1_carry_i_51
(.I0(msb1__1[13]),
.I1(msb1__1[12]),
.I2(msb1__1[8]),
.I3(msb1__1[9]),
.I4(msb1__1[11]),
.I5(msb1__1[10]),
.O(L1_carry_i_51_n_0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_52
(.I0(msb1__1[22]),
.I1(msb1__1[23]),
.O(L1_carry_i_52_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_53
(.I0(msb1__1[29]),
.I1(msb1__1[28]),
.O(L1_carry_i_53_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h1))
L1_carry_i_54
(.I0(msb1__1[39]),
.I1(msb1__1[38]),
.O(L1_carry_i_54_n_0));
LUT2 #(
.INIT(4'h2))
L1_carry_i_6
(.I0(L1_carry_i_15_n_0),
.I1(L1_carry_i_14_n_0),
.O(L1_carry_i_6_n_0));
LUT2 #(
.INIT(4'h2))
L1_carry_i_7
(.I0(L1_carry_i_17_n_0),
.I1(L1_carry_i_16_n_0),
.O(L1_carry_i_7_n_0));
LUT2 #(
.INIT(4'h2))
L1_carry_i_8
(.I0(_carry_i_1_n_0),
.I1(L1_carry_i_10_n_0),
.O(L1_carry_i_8_n_0));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
L1_carry_i_9
(.I0(L1_carry_i_18_n_0),
.I1(L1_carry_i_19_n_0),
.I2(L1_carry_i_20_n_0),
.I3(L1_carry_i_21_n_0),
.I4(L1_carry_i_22_n_0),
.I5(L1_carry_i_23_n_0),
.O(L1_carry_i_9_n_0));
CARRY4 _carry
(.CI(1'b0),
.CO({_carry_n_0,_carry_n_1,_carry_n_2,_carry_n_3}),
.CYINIT(_carry_i_1_n_0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry_n_4,_carry_n_5,_carry_n_6,_carry_n_7}),
.S({_carry_i_2_n_0,_carry_i_3_n_0,_carry_i_4_n_0,p_0_in}));
CARRY4 _carry__0
(.CI(_carry_n_0),
.CO({_carry__0_n_0,_carry__0_n_1,_carry__0_n_2,_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__0_n_4,_carry__0_n_5,_carry__0_n_6,_carry__0_n_7}),
.S({_carry__0_i_1_n_0,_carry__0_i_2_n_0,_carry__0_i_3_n_0,_carry__0_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__0_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__0_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__0_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__0_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__0_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h0200AAAAFDFF5555))
_carry__0_i_4
(.I0(L1_carry_i_12_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_10_n_0),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__0_i_4_n_0));
CARRY4 _carry__1
(.CI(_carry__0_n_0),
.CO({_carry__1_n_0,_carry__1_n_1,_carry__1_n_2,_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__1_n_4,_carry__1_n_5,_carry__1_n_6,_carry__1_n_7}),
.S({_carry__1_i_1_n_0,_carry__1_i_2_n_0,_carry__1_i_3_n_0,_carry__1_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__1_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__1_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__1_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__1_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__1_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__1_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__1_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__1_i_4_n_0));
CARRY4 _carry__2
(.CI(_carry__1_n_0),
.CO({_carry__2_n_0,_carry__2_n_1,_carry__2_n_2,_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__2_n_4,_carry__2_n_5,_carry__2_n_6,_carry__2_n_7}),
.S({_carry__2_i_1_n_0,_carry__2_i_2_n_0,_carry__2_i_3_n_0,_carry__2_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__2_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__2_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__2_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__2_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__2_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__2_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__2_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__2_i_4_n_0));
CARRY4 _carry__3
(.CI(_carry__2_n_0),
.CO({_carry__3_n_0,_carry__3_n_1,_carry__3_n_2,_carry__3_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__3_n_4,_carry__3_n_5,_carry__3_n_6,_carry__3_n_7}),
.S({_carry__3_i_1_n_0,_carry__3_i_2_n_0,_carry__3_i_3_n_0,_carry__3_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__3_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__3_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__3_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__3_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__3_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__3_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__3_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__3_i_4_n_0));
CARRY4 _carry__4
(.CI(_carry__3_n_0),
.CO({_carry__4_n_0,_carry__4_n_1,_carry__4_n_2,_carry__4_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__4_n_4,_carry__4_n_5,_carry__4_n_6,_carry__4_n_7}),
.S({_carry__4_i_1_n_0,_carry__4_i_2_n_0,_carry__4_i_3_n_0,_carry__4_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__4_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__4_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__4_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__4_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__4_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__4_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__4_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__4_i_4_n_0));
CARRY4 _carry__5
(.CI(_carry__4_n_0),
.CO({_carry__5_n_0,_carry__5_n_1,_carry__5_n_2,_carry__5_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({_carry__5_n_4,_carry__5_n_5,_carry__5_n_6,_carry__5_n_7}),
.S({_carry__5_i_1_n_0,_carry__5_i_2_n_0,_carry__5_i_3_n_0,_carry__5_i_4_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__5_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__5_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__5_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__5_i_2_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__5_i_3
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__5_i_3_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__5_i_4
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__5_i_4_n_0));
CARRY4 _carry__6
(.CI(_carry__5_n_0),
.CO({NLW__carry__6_CO_UNCONNECTED[3:1],_carry__6_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW__carry__6_O_UNCONNECTED[3:2],_carry__6_n_6,_carry__6_n_7}),
.S({1'b0,1'b0,_carry__6_i_1_n_0,_carry__6_i_2_n_0}));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__6_i_1
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__6_i_1_n_0));
LUT6 #(
.INIT(64'h555D0000FFFFFFFF))
_carry__6_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.I5(L1_carry_i_13_n_0),
.O(_carry__6_i_2_n_0));
LUT5 #(
.INIT(32'hBBBBABAA))
_carry_i_1
(.I0(msb1__1[47]),
.I1(_carry_i_6_n_0),
.I2(_carry_i_7_n_0),
.I3(_carry_i_8_n_0),
.I4(_carry_i_9_n_0),
.O(_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
_carry_i_10
(.I0(_carry_i_1_n_0),
.I1(L1_carry_i_10_n_0),
.O(_carry_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'hE))
_carry_i_11
(.I0(msb1__1[42]),
.I1(msb1__1[40]),
.O(_carry_i_11_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_12
(.I0(msb1__1[25]),
.I1(msb1__1[24]),
.I2(msb1__1[28]),
.I3(_carry_i_18_n_0),
.I4(msb1__1[26]),
.I5(msb1__1[27]),
.O(_carry_i_12_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_13
(.I0(msb1__1[15]),
.I1(msb1__1[14]),
.I2(msb1__1[18]),
.I3(_carry_i_19_n_0),
.I4(msb1__1[16]),
.I5(msb1__1[17]),
.O(_carry_i_13_n_0));
LUT5 #(
.INIT(32'h0000EFEE))
_carry_i_14
(.I0(_carry_i_20_n_0),
.I1(msb1__1[7]),
.I2(msb1__1[6]),
.I3(msb1__1[5]),
.I4(_carry_i_21_n_0),
.O(_carry_i_14_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF00BA))
_carry_i_15
(.I0(msb1__1[11]),
.I1(msb1__1[10]),
.I2(msb1__1[9]),
.I3(msb1__1[12]),
.I4(_carry_i_22_n_0),
.I5(msb1__1[13]),
.O(_carry_i_15_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_16
(.I0(msb1__1[20]),
.I1(msb1__1[19]),
.I2(msb1__1[23]),
.I3(_carry_i_23_n_0),
.I4(msb1__1[21]),
.I5(msb1__1[22]),
.O(_carry_i_16_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_17
(.I0(msb1__1[30]),
.I1(msb1__1[29]),
.I2(msb1__1[33]),
.I3(_carry_i_24_n_0),
.I4(msb1__1[31]),
.I5(msb1__1[32]),
.O(_carry_i_17_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'hE))
_carry_i_18
(.I0(msb1__1[32]),
.I1(msb1__1[30]),
.O(_carry_i_18_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'hE))
_carry_i_19
(.I0(msb1__1[22]),
.I1(msb1__1[20]),
.O(_carry_i_19_n_0));
LUT5 #(
.INIT(32'h555DAAA2))
_carry_i_2
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.O(_carry_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h5504))
_carry_i_20
(.I0(msb1__1[4]),
.I1(msb1__1[1]),
.I2(msb1__1[2]),
.I3(msb1__1[3]),
.O(_carry_i_20_n_0));
LUT5 #(
.INIT(32'hFFFFFFF4))
_carry_i_21
(.I0(msb1__1[7]),
.I1(msb1__1[6]),
.I2(msb1__1[12]),
.I3(msb1__1[10]),
.I4(msb1__1[8]),
.O(_carry_i_21_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'hE))
_carry_i_22
(.I0(msb1__1[17]),
.I1(msb1__1[15]),
.O(_carry_i_22_n_0));
LUT2 #(
.INIT(4'hE))
_carry_i_23
(.I0(msb1__1[27]),
.I1(msb1__1[25]),
.O(_carry_i_23_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'hE))
_carry_i_24
(.I0(msb1__1[37]),
.I1(msb1__1[35]),
.O(_carry_i_24_n_0));
LUT4 #(
.INIT(16'h10EF))
_carry_i_3
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(_carry_i_1_n_0),
.I3(L1_carry_i_9_n_0),
.O(_carry_i_3_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_4
(.I0(L1_carry_i_16_n_0),
.O(_carry_i_4_n_0));
LUT1 #(
.INIT(2'h1))
_carry_i_5
(.I0(_carry_i_10_n_0),
.O(p_0_in));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hBA))
_carry_i_6
(.I0(msb1__1[46]),
.I1(msb1__1[45]),
.I2(msb1__1[44]),
.O(_carry_i_6_n_0));
LUT6 #(
.INIT(64'hFFF0FFF0FFFFFFF4))
_carry_i_7
(.I0(msb1__1[35]),
.I1(msb1__1[34]),
.I2(msb1__1[38]),
.I3(_carry_i_11_n_0),
.I4(msb1__1[36]),
.I5(msb1__1[37]),
.O(_carry_i_7_n_0));
LUT6 #(
.INIT(64'hFFFFFFFF55551110))
_carry_i_8
(.I0(_carry_i_12_n_0),
.I1(_carry_i_13_n_0),
.I2(_carry_i_14_n_0),
.I3(_carry_i_15_n_0),
.I4(_carry_i_16_n_0),
.I5(_carry_i_17_n_0),
.O(_carry_i_8_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF00F4))
_carry_i_9
(.I0(msb1__1[40]),
.I1(msb1__1[39]),
.I2(msb1__1[41]),
.I3(msb1__1[42]),
.I4(msb1__1[45]),
.I5(msb1__1[43]),
.O(_carry_i_9_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
msb1
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,y[22:0]}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_msb1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,x[16:0]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_msb1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_msb1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_msb1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_msb1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_msb1_OVERFLOW_UNCONNECTED),
.P({msb1_n_58,msb1_n_59,msb1_n_60,msb1_n_61,msb1_n_62,msb1_n_63,msb1_n_64,msb1_n_65,msb1_n_66,msb1_n_67,msb1_n_68,msb1_n_69,msb1_n_70,msb1_n_71,msb1_n_72,msb1_n_73,msb1_n_74,msb1_n_75,msb1_n_76,msb1_n_77,msb1_n_78,msb1_n_79,msb1_n_80,msb1_n_81,msb1_n_82,msb1_n_83,msb1_n_84,msb1_n_85,msb1_n_86,msb1_n_87,msb1_n_88,msb1__1[16:0]}),
.PATTERNBDETECT(NLW_msb1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_msb1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({msb1_n_106,msb1_n_107,msb1_n_108,msb1_n_109,msb1_n_110,msb1_n_111,msb1_n_112,msb1_n_113,msb1_n_114,msb1_n_115,msb1_n_116,msb1_n_117,msb1_n_118,msb1_n_119,msb1_n_120,msb1_n_121,msb1_n_122,msb1_n_123,msb1_n_124,msb1_n_125,msb1_n_126,msb1_n_127,msb1_n_128,msb1_n_129,msb1_n_130,msb1_n_131,msb1_n_132,msb1_n_133,msb1_n_134,msb1_n_135,msb1_n_136,msb1_n_137,msb1_n_138,msb1_n_139,msb1_n_140,msb1_n_141,msb1_n_142,msb1_n_143,msb1_n_144,msb1_n_145,msb1_n_146,msb1_n_147,msb1_n_148,msb1_n_149,msb1_n_150,msb1_n_151,msb1_n_152,msb1_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_msb1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
msb1__0
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,y[22:0]}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_msb1__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,x[22:17]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_msb1__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_msb1__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_msb1__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_msb1__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_msb1__0_OVERFLOW_UNCONNECTED),
.P({NLW_msb1__0_P_UNCONNECTED[47:31],msb1__1[47:17]}),
.PATTERNBDETECT(NLW_msb1__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_msb1__0_PATTERNDETECT_UNCONNECTED),
.PCIN({msb1_n_106,msb1_n_107,msb1_n_108,msb1_n_109,msb1_n_110,msb1_n_111,msb1_n_112,msb1_n_113,msb1_n_114,msb1_n_115,msb1_n_116,msb1_n_117,msb1_n_118,msb1_n_119,msb1_n_120,msb1_n_121,msb1_n_122,msb1_n_123,msb1_n_124,msb1_n_125,msb1_n_126,msb1_n_127,msb1_n_128,msb1_n_129,msb1_n_130,msb1_n_131,msb1_n_132,msb1_n_133,msb1_n_134,msb1_n_135,msb1_n_136,msb1_n_137,msb1_n_138,msb1_n_139,msb1_n_140,msb1_n_141,msb1_n_142,msb1_n_143,msb1_n_144,msb1_n_145,msb1_n_146,msb1_n_147,msb1_n_148,msb1_n_149,msb1_n_150,msb1_n_151,msb1_n_152,msb1_n_153}),
.PCOUT(NLW_msb1__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_msb1__0_UNDERFLOW_UNCONNECTED));
CARRY4 \z[11]_INST_0_i_1
(.CI(\z[7]_INST_0_i_1_n_0 ),
.CO({\z[11]_INST_0_i_1_n_0 ,\z[11]_INST_0_i_1_n_1 ,\z[11]_INST_0_i_1_n_2 ,\z[11]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z_mantissa[11:8]),
.S({sel0[11],\z[11]_INST_0_i_3_n_0 ,sel0[9:8]}));
LUT1 #(
.INIT(2'h1))
\z[11]_INST_0_i_2
(.I0(\z[30]_INST_0_i_11_n_0 ),
.O(sel0[11]));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[11]_INST_0_i_3
(.I0(L1),
.I1(\z[30]_INST_0_i_50_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_47_n_0 ),
.I4(\z[30]_INST_0_i_51_n_0 ),
.O(\z[11]_INST_0_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\z[11]_INST_0_i_4
(.I0(\z[11]_INST_0_i_6_n_0 ),
.O(sel0[9]));
LUT1 #(
.INIT(2'h1))
\z[11]_INST_0_i_5
(.I0(\z[11]_INST_0_i_7_n_0 ),
.O(sel0[8]));
LUT5 #(
.INIT(32'h000047FF))
\z[11]_INST_0_i_6
(.I0(\z[11]_INST_0_i_8_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_50_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_52_n_0 ),
.O(\z[11]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[11]_INST_0_i_7
(.I0(\z[11]_INST_0_i_9_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[11]_INST_0_i_8_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_54_n_0 ),
.O(\z[11]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\z[11]_INST_0_i_8
(.I0(\z[30]_INST_0_i_121_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_98_n_0 ),
.O(\z[11]_INST_0_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\z[11]_INST_0_i_9
(.I0(\z[30]_INST_0_i_100_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_101_n_0 ),
.O(\z[11]_INST_0_i_9_n_0 ));
CARRY4 \z[15]_INST_0_i_1
(.CI(\z[11]_INST_0_i_1_n_0 ),
.CO({\z[15]_INST_0_i_1_n_0 ,\z[15]_INST_0_i_1_n_1 ,\z[15]_INST_0_i_1_n_2 ,\z[15]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z_mantissa[15:12]),
.S(sel0[15:12]));
LUT1 #(
.INIT(2'h1))
\z[15]_INST_0_i_2
(.I0(\z[30]_INST_0_i_14_n_0 ),
.O(sel0[15]));
LUT1 #(
.INIT(2'h1))
\z[15]_INST_0_i_3
(.I0(\z[30]_INST_0_i_15_n_0 ),
.O(sel0[14]));
LUT1 #(
.INIT(2'h1))
\z[15]_INST_0_i_4
(.I0(\z[15]_INST_0_i_6_n_0 ),
.O(sel0[13]));
LUT1 #(
.INIT(2'h1))
\z[15]_INST_0_i_5
(.I0(\z[15]_INST_0_i_7_n_0 ),
.O(sel0[12]));
LUT5 #(
.INIT(32'h000047FF))
\z[15]_INST_0_i_6
(.I0(\z[15]_INST_0_i_8_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_60_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_63_n_0 ),
.O(\z[15]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[15]_INST_0_i_7
(.I0(\z[30]_INST_0_i_48_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[15]_INST_0_i_8_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_65_n_0 ),
.O(\z[15]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\z[15]_INST_0_i_8
(.I0(\z[30]_INST_0_i_142_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_120_n_0 ),
.O(\z[15]_INST_0_i_8_n_0 ));
CARRY4 \z[19]_INST_0_i_1
(.CI(\z[15]_INST_0_i_1_n_0 ),
.CO({\z[19]_INST_0_i_1_n_0 ,\z[19]_INST_0_i_1_n_1 ,\z[19]_INST_0_i_1_n_2 ,\z[19]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z_mantissa[19:16]),
.S(sel0[19:16]));
LUT1 #(
.INIT(2'h1))
\z[19]_INST_0_i_2
(.I0(\z[30]_INST_0_i_17_n_0 ),
.O(sel0[19]));
LUT1 #(
.INIT(2'h1))
\z[19]_INST_0_i_3
(.I0(\z[30]_INST_0_i_18_n_0 ),
.O(sel0[18]));
LUT1 #(
.INIT(2'h1))
\z[19]_INST_0_i_4
(.I0(\z[30]_INST_0_i_19_n_0 ),
.O(sel0[17]));
LUT1 #(
.INIT(2'h1))
\z[19]_INST_0_i_5
(.I0(\z[30]_INST_0_i_20_n_0 ),
.O(sel0[16]));
CARRY4 \z[22]_INST_0_i_1
(.CI(\z[19]_INST_0_i_1_n_0 ),
.CO({\NLW_z[22]_INST_0_i_1_CO_UNCONNECTED [3:2],\z[22]_INST_0_i_1_n_2 ,\z[22]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_z[22]_INST_0_i_1_O_UNCONNECTED [3],z_mantissa[22:20]}),
.S({1'b0,sel0[22:20]}));
LUT5 #(
.INIT(32'hF2F2FFF2))
\z[22]_INST_0_i_2
(.I0(\z[30]_INST_0_i_57_n_0 ),
.I1(\z[30]_INST_0_i_81_n_0 ),
.I2(\z[30]_INST_0_i_76_n_0 ),
.I3(L1),
.I4(\z[22]_INST_0_i_5_n_0 ),
.O(sel0[22]));
LUT1 #(
.INIT(2'h1))
\z[22]_INST_0_i_3
(.I0(\z[30]_INST_0_i_22_n_0 ),
.O(sel0[21]));
LUT6 #(
.INIT(64'h22F222F2FFFF22F2))
\z[22]_INST_0_i_4
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_82_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_67_n_0 ),
.I4(L1),
.I5(\z[22]_INST_0_i_6_n_0 ),
.O(sel0[20]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[22]_INST_0_i_5
(.I0(\z[30]_INST_0_i_168_n_0 ),
.I1(\z[30]_INST_0_i_154_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_159_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_158_n_0 ),
.O(\z[22]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[22]_INST_0_i_6
(.I0(\z[30]_INST_0_i_154_n_0 ),
.I1(\z[30]_INST_0_i_155_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_158_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_152_n_0 ),
.O(\z[22]_INST_0_i_6_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[23]_INST_0
(.I0(data0[0]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[0]),
.I5(y_11__s_net_1),
.O(z[0]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[24]_INST_0
(.I0(data0[1]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[1]),
.I5(y_11__s_net_1),
.O(z[1]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[25]_INST_0
(.I0(data0[2]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[2]),
.I5(y_11__s_net_1),
.O(z[2]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[26]_INST_0
(.I0(data0[3]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[3]),
.I5(y_11__s_net_1),
.O(z[3]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[27]_INST_0
(.I0(data0[4]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[4]),
.I5(y_11__s_net_1),
.O(z[4]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[28]_INST_0
(.I0(data0[5]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[5]),
.I5(y_11__s_net_1),
.O(z[5]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[29]_INST_0
(.I0(data0[6]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[6]),
.I5(y_11__s_net_1),
.O(z[6]));
LUT6 #(
.INIT(64'h00000000FFFE0002))
\z[30]_INST_0
(.I0(data0[7]),
.I1(\z[30]_INST_0_i_1_n_0 ),
.I2(\z[30]_INST_0_i_2_n_0 ),
.I3(\z[30]_INST_0_i_3_n_0 ),
.I4(data1[7]),
.I5(y_11__s_net_1),
.O(z[7]));
LUT6 #(
.INIT(64'hFFFFEFFFFFFFFFFF))
\z[30]_INST_0_i_1
(.I0(\z[30]_INST_0_i_5_n_0 ),
.I1(\z[30]_INST_0_i_6_n_0 ),
.I2(sel0[3]),
.I3(sel0[0]),
.I4(\z[30]_INST_0_i_9_n_0 ),
.I5(sel0[2]),
.O(\z[30]_INST_0_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[30]_INST_0_i_10
(.I0(L1),
.I1(\z[30]_INST_0_i_44_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_37_n_0 ),
.I4(\z[30]_INST_0_i_46_n_0 ),
.O(sel0[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_100
(.I0(\z[30]_INST_0_i_181_n_0 ),
.I1(\z[30]_INST_0_i_182_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_183_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_184_n_0 ),
.O(\z[30]_INST_0_i_100_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_101
(.I0(\z[30]_INST_0_i_185_n_0 ),
.I1(\z[30]_INST_0_i_186_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_187_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_188_n_0 ),
.O(\z[30]_INST_0_i_101_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_102
(.I0(\z[30]_INST_0_i_189_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_171_n_0 ),
.O(\z[30]_INST_0_i_102_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF4FFF7))
\z[30]_INST_0_i_103
(.I0(msb1__1[1]),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_118_n_0 ),
.I3(\z[30]_INST_0_i_170_n_0 ),
.I4(msb1__1[3]),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_103_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_104
(.I0(\z[30]_INST_0_i_183_n_0 ),
.I1(\z[30]_INST_0_i_184_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_190_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_181_n_0 ),
.O(\z[30]_INST_0_i_104_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_105
(.I0(\z[30]_INST_0_i_187_n_0 ),
.I1(\z[30]_INST_0_i_188_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_191_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_185_n_0 ),
.O(\z[30]_INST_0_i_105_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_106
(.I0(\z[30]_INST_0_i_175_n_0 ),
.I1(\z[30]_INST_0_i_176_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_192_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_173_n_0 ),
.O(\z[30]_INST_0_i_106_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAEFFFF))
\z[30]_INST_0_i_107
(.I0(\z[30]_INST_0_i_118_n_0 ),
.I1(_carry_n_4),
.I2(L1),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[3]),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_107_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_108
(.I0(\z[30]_INST_0_i_179_n_0 ),
.I1(\z[30]_INST_0_i_180_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_193_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_177_n_0 ),
.O(\z[30]_INST_0_i_108_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF4F7FFFF))
\z[30]_INST_0_i_109
(.I0(msb1__1[0]),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_118_n_0 ),
.I3(msb1__1[2]),
.I4(\z[30]_INST_0_i_194_n_0 ),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_109_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[30]_INST_0_i_11
(.I0(\z[30]_INST_0_i_47_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_48_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_49_n_0 ),
.O(\z[30]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_110
(.I0(\z[30]_INST_0_i_190_n_0 ),
.I1(\z[30]_INST_0_i_181_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_195_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_183_n_0 ),
.O(\z[30]_INST_0_i_110_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_111
(.I0(\z[30]_INST_0_i_191_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_185_n_0 ),
.O(\z[30]_INST_0_i_111_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_112
(.I0(\z[30]_INST_0_i_196_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_187_n_0 ),
.O(\z[30]_INST_0_i_112_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_113
(.I0(\z[30]_INST_0_i_192_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_173_n_0 ),
.O(\z[30]_INST_0_i_113_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_114
(.I0(\z[30]_INST_0_i_197_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_175_n_0 ),
.O(\z[30]_INST_0_i_114_n_0 ));
LUT6 #(
.INIT(64'h3FFF3FAAFFFFFFFF))
\z[30]_INST_0_i_115
(.I0(_carry_n_5),
.I1(L1_carry_i_17_n_0),
.I2(\z[30]_INST_0_i_198_n_0 ),
.I3(L1),
.I4(_carry_n_4),
.I5(msb1__1[0]),
.O(\z[30]_INST_0_i_115_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\z[30]_INST_0_i_116
(.I0(\z[30]_INST_0_i_199_n_0 ),
.I1(_carry__0_n_6),
.I2(_carry__5_n_6),
.I3(_carry__0_n_5),
.I4(\z[30]_INST_0_i_200_n_0 ),
.I5(\z[30]_INST_0_i_201_n_0 ),
.O(\z[30]_INST_0_i_116_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFFFF3FAFAF))
\z[30]_INST_0_i_117
(.I0(_carry_n_5),
.I1(L1_carry_i_17_n_0),
.I2(msb1__1[1]),
.I3(L1_carry_i_14_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_117_n_0 ));
LUT5 #(
.INIT(32'h3C33AAAA))
\z[30]_INST_0_i_118
(.I0(_carry_n_6),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_10_n_0),
.I3(_carry_i_1_n_0),
.I4(L1),
.O(\z[30]_INST_0_i_118_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEAEFFFF))
\z[30]_INST_0_i_119
(.I0(\z[30]_INST_0_i_118_n_0 ),
.I1(_carry_n_4),
.I2(L1),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[1]),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_119_n_0 ));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[30]_INST_0_i_12
(.I0(L1),
.I1(\z[30]_INST_0_i_50_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_47_n_0 ),
.I4(\z[30]_INST_0_i_51_n_0 ),
.O(sel0[10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_120
(.I0(\z[30]_INST_0_i_176_n_0 ),
.I1(\z[30]_INST_0_i_202_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_173_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_174_n_0 ),
.O(\z[30]_INST_0_i_120_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_121
(.I0(\z[30]_INST_0_i_180_n_0 ),
.I1(\z[30]_INST_0_i_203_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_177_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_178_n_0 ),
.O(\z[30]_INST_0_i_121_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_122
(.I0(\z[30]_INST_0_i_184_n_0 ),
.I1(\z[30]_INST_0_i_204_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_181_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_182_n_0 ),
.O(\z[30]_INST_0_i_122_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_123
(.I0(\z[30]_INST_0_i_188_n_0 ),
.I1(\z[30]_INST_0_i_205_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_185_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_186_n_0 ),
.O(\z[30]_INST_0_i_123_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\z[30]_INST_0_i_124
(.I0(\z[30]_INST_0_i_206_n_0 ),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_207_n_0 ),
.I3(\z[30]_INST_0_i_95_n_0 ),
.I4(\z[30]_INST_0_i_208_n_0 ),
.O(\z[30]_INST_0_i_124_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\z[30]_INST_0_i_125
(.I0(\z[30]_INST_0_i_209_n_0 ),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_132_n_0 ),
.I3(\z[30]_INST_0_i_95_n_0 ),
.I4(\z[30]_INST_0_i_210_n_0 ),
.O(\z[30]_INST_0_i_125_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_126
(.I0(\z[30]_INST_0_i_96_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_206_n_0 ),
.I3(\z[30]_INST_0_i_118_n_0 ),
.I4(\z[30]_INST_0_i_207_n_0 ),
.O(\z[30]_INST_0_i_126_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_127
(.I0(\z[30]_INST_0_i_172_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_209_n_0 ),
.I3(\z[30]_INST_0_i_118_n_0 ),
.I4(\z[30]_INST_0_i_132_n_0 ),
.O(\z[30]_INST_0_i_127_n_0 ));
LUT6 #(
.INIT(64'hAFA03030AFA03F3F))
\z[30]_INST_0_i_128
(.I0(\z[30]_INST_0_i_211_n_0 ),
.I1(\z[30]_INST_0_i_212_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_213_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_202_n_0 ),
.O(\z[30]_INST_0_i_128_n_0 ));
LUT6 #(
.INIT(64'h505F3030505F3F3F))
\z[30]_INST_0_i_129
(.I0(\z[30]_INST_0_i_178_n_0 ),
.I1(\z[30]_INST_0_i_214_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_180_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_203_n_0 ),
.O(\z[30]_INST_0_i_129_n_0 ));
LUT5 #(
.INIT(32'h115F1F5F))
\z[30]_INST_0_i_13
(.I0(\z[30]_INST_0_i_52_n_0 ),
.I1(\z[30]_INST_0_i_53_n_0 ),
.I2(\z[30]_INST_0_i_54_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_55_n_0 ),
.O(\z[30]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'h505FC0C0505FCFCF))
\z[30]_INST_0_i_130
(.I0(\z[30]_INST_0_i_182_n_0 ),
.I1(\z[30]_INST_0_i_215_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_184_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_204_n_0 ),
.O(\z[30]_INST_0_i_130_n_0 ));
LUT6 #(
.INIT(64'hA0AF3030A0AF3F3F))
\z[30]_INST_0_i_131
(.I0(\z[30]_INST_0_i_216_n_0 ),
.I1(\z[30]_INST_0_i_217_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_188_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_205_n_0 ),
.O(\z[30]_INST_0_i_131_n_0 ));
LUT6 #(
.INIT(64'h1510D5DFFFFFFFFF))
\z[30]_INST_0_i_132
(.I0(msb1__1[0]),
.I1(L1_carry_i_17_n_0),
.I2(L1),
.I3(_carry_n_5),
.I4(msb1__1[8]),
.I5(\z[30]_INST_0_i_194_n_0 ),
.O(\z[30]_INST_0_i_132_n_0 ));
LUT6 #(
.INIT(64'hFFF444F4FFF777F7))
\z[30]_INST_0_i_133
(.I0(msb1__1[4]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(_carry_n_4),
.I3(L1),
.I4(L1_carry_i_14_n_0),
.I5(msb1__1[12]),
.O(\z[30]_INST_0_i_133_n_0 ));
LUT6 #(
.INIT(64'h1510D5DFFFFFFFFF))
\z[30]_INST_0_i_134
(.I0(msb1__1[2]),
.I1(L1_carry_i_17_n_0),
.I2(L1),
.I3(_carry_n_5),
.I4(msb1__1[10]),
.I5(\z[30]_INST_0_i_194_n_0 ),
.O(\z[30]_INST_0_i_134_n_0 ));
LUT6 #(
.INIT(64'h1510D5DFFFFFFFFF))
\z[30]_INST_0_i_135
(.I0(msb1__1[6]),
.I1(L1_carry_i_17_n_0),
.I2(L1),
.I3(_carry_n_5),
.I4(msb1__1[14]),
.I5(\z[30]_INST_0_i_194_n_0 ),
.O(\z[30]_INST_0_i_135_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_136
(.I0(\z[30]_INST_0_i_207_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_146_n_0 ),
.O(\z[30]_INST_0_i_136_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_137
(.I0(\z[30]_INST_0_i_218_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_148_n_0 ),
.O(\z[30]_INST_0_i_137_n_0 ));
LUT6 #(
.INIT(64'hB080FFFFB0800000))
\z[30]_INST_0_i_138
(.I0(msb1__1[36]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[20]),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_217_n_0 ),
.O(\z[30]_INST_0_i_138_n_0 ));
LUT6 #(
.INIT(64'hB8BB8888B8B88888))
\z[30]_INST_0_i_139
(.I0(\z[30]_INST_0_i_188_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(msb1__1[40]),
.I3(L1_carry_i_14_n_0),
.I4(L1_carry_i_15_n_0),
.I5(msb1__1[24]),
.O(\z[30]_INST_0_i_139_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_14
(.I0(L1),
.I1(\z[30]_INST_0_i_56_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_58_n_0 ),
.I4(\z[30]_INST_0_i_43_n_0 ),
.I5(\z[30]_INST_0_i_59_n_0 ),
.O(\z[30]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'hB080FFFFB0800000))
\z[30]_INST_0_i_140
(.I0(msb1__1[37]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[21]),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_212_n_0 ),
.O(\z[30]_INST_0_i_140_n_0 ));
LUT6 #(
.INIT(64'hB080FFFFB0800000))
\z[30]_INST_0_i_141
(.I0(msb1__1[33]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[17]),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_202_n_0 ),
.O(\z[30]_INST_0_i_141_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_142
(.I0(\z[30]_INST_0_i_178_n_0 ),
.I1(\z[30]_INST_0_i_214_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_180_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_203_n_0 ),
.O(\z[30]_INST_0_i_142_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_143
(.I0(\z[30]_INST_0_i_208_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_207_n_0 ),
.I3(\z[30]_INST_0_i_118_n_0 ),
.I4(\z[30]_INST_0_i_146_n_0 ),
.O(\z[30]_INST_0_i_143_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_144
(.I0(\z[30]_INST_0_i_210_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_132_n_0 ),
.I3(\z[30]_INST_0_i_118_n_0 ),
.I4(\z[30]_INST_0_i_133_n_0 ),
.O(\z[30]_INST_0_i_144_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_145
(.I0(\z[30]_INST_0_i_186_n_0 ),
.I1(\z[30]_INST_0_i_217_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_188_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_205_n_0 ),
.O(\z[30]_INST_0_i_145_n_0 ));
LUT6 #(
.INIT(64'h4747FF47FFFFFF47))
\z[30]_INST_0_i_146
(.I0(msb1__1[5]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[13]),
.I3(_carry_n_4),
.I4(L1),
.I5(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_146_n_0 ));
LUT6 #(
.INIT(64'h77CF44CC77CF77CF))
\z[30]_INST_0_i_147
(.I0(msb1__1[9]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[1]),
.I3(\z[30]_INST_0_i_194_n_0 ),
.I4(\z[30]_INST_0_i_170_n_0 ),
.I5(msb1__1[17]),
.O(\z[30]_INST_0_i_147_n_0 ));
LUT6 #(
.INIT(64'h7757555777F7FFF7))
\z[30]_INST_0_i_148
(.I0(\z[30]_INST_0_i_194_n_0 ),
.I1(msb1__1[15]),
.I2(_carry_n_5),
.I3(L1),
.I4(L1_carry_i_17_n_0),
.I5(msb1__1[7]),
.O(\z[30]_INST_0_i_148_n_0 ));
LUT6 #(
.INIT(64'hFF00FFFF47474747))
\z[30]_INST_0_i_149
(.I0(msb1__1[19]),
.I1(\z[30]_INST_0_i_194_n_0 ),
.I2(msb1__1[3]),
.I3(\z[30]_INST_0_i_170_n_0 ),
.I4(msb1__1[11]),
.I5(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_149_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[30]_INST_0_i_15
(.I0(\z[30]_INST_0_i_60_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_61_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_62_n_0 ),
.O(\z[30]_INST_0_i_15_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_150
(.I0(\z[30]_INST_0_i_133_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_166_n_0 ),
.O(\z[30]_INST_0_i_150_n_0 ));
LUT5 #(
.INIT(32'hF5DD0511))
\z[30]_INST_0_i_151
(.I0(\z[30]_INST_0_i_163_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_135_n_0 ),
.O(\z[30]_INST_0_i_151_n_0 ));
LUT5 #(
.INIT(32'hB888B8BB))
\z[30]_INST_0_i_152
(.I0(\z[30]_INST_0_i_219_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_211_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(\z[30]_INST_0_i_212_n_0 ),
.O(\z[30]_INST_0_i_152_n_0 ));
LUT6 #(
.INIT(64'h505FC0C0505FCFCF))
\z[30]_INST_0_i_153
(.I0(\z[30]_INST_0_i_203_n_0 ),
.I1(\z[30]_INST_0_i_220_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_178_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_214_n_0 ),
.O(\z[30]_INST_0_i_153_n_0 ));
LUT5 #(
.INIT(32'h8BBB8B88))
\z[30]_INST_0_i_154
(.I0(\z[30]_INST_0_i_221_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_182_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(\z[30]_INST_0_i_215_n_0 ),
.O(\z[30]_INST_0_i_154_n_0 ));
LUT5 #(
.INIT(32'hB888B8BB))
\z[30]_INST_0_i_155
(.I0(\z[30]_INST_0_i_222_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_216_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(\z[30]_INST_0_i_217_n_0 ),
.O(\z[30]_INST_0_i_155_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_156
(.I0(\z[30]_INST_0_i_146_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_147_n_0 ),
.O(\z[30]_INST_0_i_156_n_0 ));
LUT5 #(
.INIT(32'hAFBBA088))
\z[30]_INST_0_i_157
(.I0(\z[30]_INST_0_i_134_n_0 ),
.I1(_carry_n_6),
.I2(L1_carry_i_16_n_0),
.I3(L1),
.I4(\z[30]_INST_0_i_135_n_0 ),
.O(\z[30]_INST_0_i_157_n_0 ));
LUT5 #(
.INIT(32'h8BBB8B88))
\z[30]_INST_0_i_158
(.I0(\z[30]_INST_0_i_223_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_203_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(\z[30]_INST_0_i_220_n_0 ),
.O(\z[30]_INST_0_i_158_n_0 ));
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_159
(.I0(\z[30]_INST_0_i_224_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_219_n_0 ),
.O(\z[30]_INST_0_i_159_n_0 ));
LUT5 #(
.INIT(32'h115F1F5F))
\z[30]_INST_0_i_16
(.I0(\z[30]_INST_0_i_63_n_0 ),
.I1(\z[30]_INST_0_i_64_n_0 ),
.I2(\z[30]_INST_0_i_65_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_66_n_0 ),
.O(\z[30]_INST_0_i_16_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_160
(.I0(\z[30]_INST_0_i_225_n_0 ),
.I1(\z[30]_INST_0_i_222_n_0 ),
.I2(_carry_i_10_n_0),
.I3(\z[30]_INST_0_i_221_n_0 ),
.I4(L1_carry_i_16_n_0),
.I5(\z[30]_INST_0_i_226_n_0 ),
.O(\z[30]_INST_0_i_160_n_0 ));
LUT5 #(
.INIT(32'hB888B8BB))
\z[30]_INST_0_i_161
(.I0(\z[30]_INST_0_i_166_n_0 ),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_227_n_0 ),
.I3(\z[30]_INST_0_i_169_n_0 ),
.I4(\z[30]_INST_0_i_228_n_0 ),
.O(\z[30]_INST_0_i_161_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[30]_INST_0_i_162
(.I0(msb1__1[14]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[6]),
.I3(\z[30]_INST_0_i_170_n_0 ),
.I4(msb1__1[22]),
.O(\z[30]_INST_0_i_162_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\z[30]_INST_0_i_163
(.I0(msb1__1[10]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[2]),
.I3(\z[30]_INST_0_i_170_n_0 ),
.I4(msb1__1[18]),
.O(\z[30]_INST_0_i_163_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_164
(.I0(\z[30]_INST_0_i_223_n_0 ),
.I1(\z[30]_INST_0_i_229_n_0 ),
.I2(_carry_i_10_n_0),
.I3(\z[30]_INST_0_i_219_n_0 ),
.I4(L1_carry_i_16_n_0),
.I5(\z[30]_INST_0_i_230_n_0 ),
.O(\z[30]_INST_0_i_164_n_0 ));
LUT5 #(
.INIT(32'h47CC47FF))
\z[30]_INST_0_i_165
(.I0(msb1__1[13]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[21]),
.I3(\z[30]_INST_0_i_194_n_0 ),
.I4(msb1__1[5]),
.O(\z[30]_INST_0_i_165_n_0 ));
LUT6 #(
.INIT(64'h4447CCCF4447FFFF))
\z[30]_INST_0_i_166
(.I0(msb1__1[8]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(\z[30]_INST_0_i_170_n_0 ),
.I3(msb1__1[16]),
.I4(\z[30]_INST_0_i_194_n_0 ),
.I5(msb1__1[0]),
.O(\z[30]_INST_0_i_166_n_0 ));
LUT6 #(
.INIT(64'hB0BFB0B0B0BFBFBF))
\z[30]_INST_0_i_167
(.I0(\z[30]_INST_0_i_170_n_0 ),
.I1(msb1__1[12]),
.I2(\z[30]_INST_0_i_169_n_0 ),
.I3(msb1__1[20]),
.I4(\z[30]_INST_0_i_194_n_0 ),
.I5(msb1__1[4]),
.O(\z[30]_INST_0_i_167_n_0 ));
LUT6 #(
.INIT(64'h7477FFFF74770000))
\z[30]_INST_0_i_168
(.I0(\z[30]_INST_0_i_217_n_0 ),
.I1(L1_carry_i_17_n_0),
.I2(L1_carry_i_14_n_0),
.I3(\z[30]_INST_0_i_231_n_0 ),
.I4(L1_carry_i_16_n_0),
.I5(\z[30]_INST_0_i_222_n_0 ),
.O(\z[30]_INST_0_i_168_n_0 ));
LUT6 #(
.INIT(64'hAAA6FFFFAAA60000))
\z[30]_INST_0_i_169
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1),
.I5(_carry_n_5),
.O(\z[30]_INST_0_i_169_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_17
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_67_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_68_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_69_n_0 ),
.O(\z[30]_INST_0_i_17_n_0 ));
LUT6 #(
.INIT(64'h9A55FFFF9A550000))
\z[30]_INST_0_i_170
(.I0(L1_carry_i_12_n_0),
.I1(\z[30]_INST_0_i_232_n_0 ),
.I2(_carry_i_1_n_0),
.I3(L1_carry_i_9_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_170_n_0 ));
LUT6 #(
.INIT(64'hFF7FFF7FFF70FF7F))
\z[30]_INST_0_i_171
(.I0(\z[30]_INST_0_i_194_n_0 ),
.I1(msb1__1[0]),
.I2(\z[30]_INST_0_i_118_n_0 ),
.I3(\z[30]_INST_0_i_169_n_0 ),
.I4(msb1__1[4]),
.I5(\z[30]_INST_0_i_170_n_0 ),
.O(\z[30]_INST_0_i_171_n_0 ));
LUT5 #(
.INIT(32'hF4FFF7FF))
\z[30]_INST_0_i_172
(.I0(msb1__1[2]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_169_n_0 ),
.I3(\z[30]_INST_0_i_194_n_0 ),
.I4(msb1__1[6]),
.O(\z[30]_INST_0_i_172_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_173
(.I0(msb1__1[29]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[13]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[45]),
.O(\z[30]_INST_0_i_173_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hB080))
\z[30]_INST_0_i_174
(.I0(msb1__1[37]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[21]),
.O(\z[30]_INST_0_i_174_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_175
(.I0(msb1__1[25]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[9]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[41]),
.O(\z[30]_INST_0_i_175_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hB080))
\z[30]_INST_0_i_176
(.I0(msb1__1[33]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[17]),
.O(\z[30]_INST_0_i_176_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_177
(.I0(msb1__1[27]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[11]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[43]),
.O(\z[30]_INST_0_i_177_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h88C0))
\z[30]_INST_0_i_178
(.I0(msb1__1[19]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[35]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_178_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_179
(.I0(msb1__1[23]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[7]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[39]),
.O(\z[30]_INST_0_i_179_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_18
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_68_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_70_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_71_n_0 ),
.O(\z[30]_INST_0_i_18_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hACACF000))
\z[30]_INST_0_i_180
(.I0(msb1__1[15]),
.I1(msb1__1[47]),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[31]),
.I4(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_180_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_181
(.I0(msb1__1[30]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[14]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[46]),
.O(\z[30]_INST_0_i_181_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h88C0))
\z[30]_INST_0_i_182
(.I0(msb1__1[22]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[38]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_182_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_183
(.I0(msb1__1[26]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[10]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[42]),
.O(\z[30]_INST_0_i_183_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h88C0))
\z[30]_INST_0_i_184
(.I0(msb1__1[18]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[34]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_184_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_185
(.I0(msb1__1[28]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[12]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[44]),
.O(\z[30]_INST_0_i_185_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hB080))
\z[30]_INST_0_i_186
(.I0(msb1__1[36]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[20]),
.O(\z[30]_INST_0_i_186_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_187
(.I0(msb1__1[24]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[8]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[40]),
.O(\z[30]_INST_0_i_187_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h88C0))
\z[30]_INST_0_i_188
(.I0(msb1__1[16]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[32]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_188_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFFBFFFBFBF))
\z[30]_INST_0_i_189
(.I0(\z[30]_INST_0_i_118_n_0 ),
.I1(msb1__1[2]),
.I2(\z[30]_INST_0_i_194_n_0 ),
.I3(L1_carry_i_17_n_0),
.I4(L1),
.I5(_carry_n_5),
.O(\z[30]_INST_0_i_189_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_19
(.I0(\z[30]_INST_0_i_57_n_0 ),
.I1(\z[30]_INST_0_i_72_n_0 ),
.I2(\z[30]_INST_0_i_43_n_0 ),
.I3(\z[30]_INST_0_i_70_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_73_n_0 ),
.O(\z[30]_INST_0_i_19_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_190
(.I0(msb1__1[22]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[6]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[38]),
.O(\z[30]_INST_0_i_190_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_191
(.I0(msb1__1[20]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[4]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[36]),
.O(\z[30]_INST_0_i_191_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_192
(.I0(msb1__1[21]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[5]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[37]),
.O(\z[30]_INST_0_i_192_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_193
(.I0(msb1__1[19]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[3]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[35]),
.O(\z[30]_INST_0_i_193_n_0 ));
LUT6 #(
.INIT(64'h5DA200005DA2FFFF))
\z[30]_INST_0_i_194
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_232_n_0 ),
.I3(L1_carry_i_12_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_194_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_195
(.I0(msb1__1[18]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[2]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[34]),
.O(\z[30]_INST_0_i_195_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_196
(.I0(msb1__1[16]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[0]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[32]),
.O(\z[30]_INST_0_i_196_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hB833B800))
\z[30]_INST_0_i_197
(.I0(msb1__1[17]),
.I1(L1_carry_i_14_n_0),
.I2(msb1__1[1]),
.I3(L1_carry_i_15_n_0),
.I4(msb1__1[33]),
.O(\z[30]_INST_0_i_197_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h555DAAA2))
\z[30]_INST_0_i_198
(.I0(L1_carry_i_9_n_0),
.I1(_carry_i_1_n_0),
.I2(L1_carry_i_10_n_0),
.I3(L1_carry_i_11_n_0),
.I4(L1_carry_i_12_n_0),
.O(\z[30]_INST_0_i_198_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_199
(.I0(_carry__2_n_4),
.I1(_carry__3_n_4),
.I2(_carry__4_n_4),
.I3(_carry__5_n_5),
.I4(\z[30]_INST_0_i_233_n_0 ),
.O(\z[30]_INST_0_i_199_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\z[30]_INST_0_i_2
(.I0(\z[30]_INST_0_i_11_n_0 ),
.I1(sel0[10]),
.I2(\z[30]_INST_0_i_13_n_0 ),
.I3(\z[30]_INST_0_i_14_n_0 ),
.I4(\z[30]_INST_0_i_15_n_0 ),
.I5(\z[30]_INST_0_i_16_n_0 ),
.O(\z[30]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_20
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_72_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_59_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_74_n_0 ),
.O(\z[30]_INST_0_i_20_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_200
(.I0(_carry__1_n_4),
.I1(_carry__6_n_6),
.I2(_carry__0_n_7),
.I3(_carry__4_n_5),
.I4(\z[30]_INST_0_i_234_n_0 ),
.O(\z[30]_INST_0_i_200_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\z[30]_INST_0_i_201
(.I0(_carry__2_n_5),
.I1(_carry__6_n_7),
.I2(_carry__0_n_4),
.I3(_carry__5_n_7),
.I4(\z[30]_INST_0_i_235_n_0 ),
.O(\z[30]_INST_0_i_201_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_202
(.I0(msb1__1[41]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[25]),
.O(\z[30]_INST_0_i_202_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_203
(.I0(msb1__1[39]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[23]),
.O(\z[30]_INST_0_i_203_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_204
(.I0(msb1__1[42]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[26]),
.O(\z[30]_INST_0_i_204_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_205
(.I0(msb1__1[40]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[24]),
.O(\z[30]_INST_0_i_205_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFFFF3FAFAF))
\z[30]_INST_0_i_206
(.I0(_carry_n_5),
.I1(L1_carry_i_17_n_0),
.I2(msb1__1[5]),
.I3(L1_carry_i_14_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_206_n_0 ));
LUT6 #(
.INIT(64'h4747FF47FFFFFF47))
\z[30]_INST_0_i_207
(.I0(msb1__1[1]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(msb1__1[9]),
.I3(_carry_n_4),
.I4(L1),
.I5(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_207_n_0 ));
LUT6 #(
.INIT(64'hFFFFCF44FFFFCF77))
\z[30]_INST_0_i_208
(.I0(msb1__1[7]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(msb1__1[3]),
.I3(\z[30]_INST_0_i_169_n_0 ),
.I4(\z[30]_INST_0_i_170_n_0 ),
.I5(msb1__1[11]),
.O(\z[30]_INST_0_i_208_n_0 ));
LUT6 #(
.INIT(64'hFF3FFFFFFF3FAFAF))
\z[30]_INST_0_i_209
(.I0(_carry_n_5),
.I1(L1_carry_i_17_n_0),
.I2(msb1__1[4]),
.I3(L1_carry_i_14_n_0),
.I4(L1),
.I5(_carry_n_4),
.O(\z[30]_INST_0_i_209_n_0 ));
LUT6 #(
.INIT(64'h101010FF10101010))
\z[30]_INST_0_i_21
(.I0(\z[30]_INST_0_i_75_n_0 ),
.I1(\z[30]_INST_0_i_76_n_0 ),
.I2(\z[30]_INST_0_i_77_n_0 ),
.I3(\z[30]_INST_0_i_78_n_0 ),
.I4(\z[30]_INST_0_i_79_n_0 ),
.I5(\z[30]_INST_0_i_80_n_0 ),
.O(\z[30]_INST_0_i_21_n_0 ));
LUT6 #(
.INIT(64'hCF44CF77FFFFFFFF))
\z[30]_INST_0_i_210
(.I0(msb1__1[6]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(msb1__1[2]),
.I3(\z[30]_INST_0_i_169_n_0 ),
.I4(msb1__1[10]),
.I5(\z[30]_INST_0_i_194_n_0 ),
.O(\z[30]_INST_0_i_210_n_0 ));
LUT4 #(
.INIT(16'h773F))
\z[30]_INST_0_i_211
(.I0(msb1__1[21]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[37]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_211_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_212
(.I0(msb1__1[45]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[29]),
.O(\z[30]_INST_0_i_212_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h773F))
\z[30]_INST_0_i_213
(.I0(msb1__1[17]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[33]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_213_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_214
(.I0(msb1__1[43]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[27]),
.O(\z[30]_INST_0_i_214_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h4F5F))
\z[30]_INST_0_i_215
(.I0(msb1__1[46]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[30]),
.O(\z[30]_INST_0_i_215_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h773F))
\z[30]_INST_0_i_216
(.I0(msb1__1[20]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[36]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_216_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hB0A0))
\z[30]_INST_0_i_217
(.I0(msb1__1[44]),
.I1(L1_carry_i_14_n_0),
.I2(L1_carry_i_15_n_0),
.I3(msb1__1[28]),
.O(\z[30]_INST_0_i_217_n_0 ));
LUT6 #(
.INIT(64'hFFF444F4FFF777F7))
\z[30]_INST_0_i_218
(.I0(msb1__1[3]),
.I1(\z[30]_INST_0_i_169_n_0 ),
.I2(_carry_n_4),
.I3(L1),
.I4(L1_carry_i_14_n_0),
.I5(msb1__1[11]),
.O(\z[30]_INST_0_i_218_n_0 ));
LUT6 #(
.INIT(64'h3F103F1FFFFFFFFF))
\z[30]_INST_0_i_219
(.I0(msb1__1[25]),
.I1(msb1__1[41]),
.I2(L1_carry_i_17_n_0),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[33]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_219_n_0 ));
LUT6 #(
.INIT(64'hDD0DDD0D0000DD0D))
\z[30]_INST_0_i_22
(.I0(\z[30]_INST_0_i_43_n_0 ),
.I1(\z[30]_INST_0_i_81_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_82_n_0 ),
.I4(L1),
.I5(\z[30]_INST_0_i_83_n_0 ),
.O(\z[30]_INST_0_i_22_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h3777))
\z[30]_INST_0_i_220
(.I0(msb1__1[47]),
.I1(L1_carry_i_15_n_0),
.I2(msb1__1[31]),
.I3(\z[30]_INST_0_i_198_n_0 ),
.O(\z[30]_INST_0_i_220_n_0 ));
LUT6 #(
.INIT(64'h103F1F3FFFFFFFFF))
\z[30]_INST_0_i_221
(.I0(msb1__1[26]),
.I1(msb1__1[42]),
.I2(L1_carry_i_17_n_0),
.I3(\z[30]_INST_0_i_198_n_0 ),
.I4(msb1__1[34]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_221_n_0 ));
LUT6 #(
.INIT(64'h103F1F3FFFFFFFFF))
\z[30]_INST_0_i_222
(.I0(msb1__1[24]),
.I1(msb1__1[40]),
.I2(L1_carry_i_17_n_0),
.I3(\z[30]_INST_0_i_198_n_0 ),
.I4(msb1__1[32]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_222_n_0 ));
LUT6 #(
.INIT(64'h103F1F3FFFFFFFFF))
\z[30]_INST_0_i_223
(.I0(msb1__1[27]),
.I1(msb1__1[43]),
.I2(L1_carry_i_17_n_0),
.I3(\z[30]_INST_0_i_198_n_0 ),
.I4(msb1__1[35]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_223_n_0 ));
LUT6 #(
.INIT(64'h3F103F1FFFFFFFFF))
\z[30]_INST_0_i_224
(.I0(msb1__1[29]),
.I1(msb1__1[45]),
.I2(L1_carry_i_17_n_0),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[37]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_224_n_0 ));
LUT6 #(
.INIT(64'h3F103F1FFFFFFFFF))
\z[30]_INST_0_i_225
(.I0(msb1__1[28]),
.I1(msb1__1[44]),
.I2(L1_carry_i_17_n_0),
.I3(L1_carry_i_14_n_0),
.I4(msb1__1[36]),
.I5(L1_carry_i_15_n_0),
.O(\z[30]_INST_0_i_225_n_0 ));
LUT6 #(
.INIT(64'hE0E0E0E0E0EFEFEF))
\z[30]_INST_0_i_226
(.I0(\z[30]_INST_0_i_236_n_0 ),
.I1(\z[30]_INST_0_i_237_n_0 ),
.I2(L1_carry_i_17_n_0),
.I3(msb1__1[46]),
.I4(L1_carry_i_15_n_0),
.I5(\z[30]_INST_0_i_238_n_0 ),
.O(\z[30]_INST_0_i_226_n_0 ));
LUT4 #(
.INIT(16'hE2FF))
\z[30]_INST_0_i_227
(.I0(_carry_n_4),
.I1(L1),
.I2(L1_carry_i_14_n_0),
.I3(msb1__1[12]),
.O(\z[30]_INST_0_i_227_n_0 ));
LUT5 #(
.INIT(32'hBFBA808A))
\z[30]_INST_0_i_228
(.I0(msb1__1[20]),
.I1(\z[30]_INST_0_i_198_n_0 ),
.I2(L1),
.I3(_carry_n_4),
.I4(msb1__1[4]),
.O(\z[30]_INST_0_i_228_n_0 ));
LUT6 #(
.INIT(64'h10105050101F5F5F))
\z[30]_INST_0_i_229
(.I0(\z[30]_INST_0_i_239_n_0 ),
.I1(msb1__1[39]),
.I2(L1_carry_i_17_n_0),
.I3(msb1__1[47]),
.I4(L1_carry_i_15_n_0),
.I5(\z[30]_INST_0_i_240_n_0 ),
.O(\z[30]_INST_0_i_229_n_0 ));
LUT6 #(
.INIT(64'h50503030505F3F3F))
\z[30]_INST_0_i_230
(.I0(\z[30]_INST_0_i_241_n_0 ),
.I1(\z[30]_INST_0_i_242_n_0 ),
.I2(L1_carry_i_17_n_0),
.I3(\z[30]_INST_0_i_243_n_0 ),
.I4(\z[30]_INST_0_i_198_n_0 ),
.I5(\z[30]_INST_0_i_244_n_0 ),
.O(\z[30]_INST_0_i_230_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h8))
\z[30]_INST_0_i_231
(.I0(L1_carry_i_15_n_0),
.I1(msb1__1[36]),
.O(\z[30]_INST_0_i_231_n_0 ));
LUT6 #(
.INIT(64'hAEAEAEAEFFFFFFAE))
\z[30]_INST_0_i_232
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_29_n_0),
.I2(L1_carry_i_28_n_0),
.I3(\z[30]_INST_0_i_245_n_0 ),
.I4(L1_carry_i_25_n_0),
.I5(L1_carry_i_24_n_0),
.O(\z[30]_INST_0_i_232_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_233
(.I0(_carry__2_n_6),
.I1(_carry__1_n_6),
.I2(_carry__3_n_6),
.I3(_carry__1_n_7),
.O(\z[30]_INST_0_i_233_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_234
(.I0(_carry__2_n_7),
.I1(L1),
.I2(_carry__3_n_5),
.I3(_carry__1_n_5),
.O(\z[30]_INST_0_i_234_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[30]_INST_0_i_235
(.I0(_carry__5_n_4),
.I1(_carry__3_n_7),
.I2(_carry__4_n_6),
.I3(_carry__4_n_7),
.O(\z[30]_INST_0_i_235_n_0 ));
LUT6 #(
.INIT(64'hC3CC333341441111))
\z[30]_INST_0_i_236
(.I0(msb1__1[38]),
.I1(L1_carry_i_12_n_0),
.I2(\z[30]_INST_0_i_232_n_0 ),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(\z[30]_INST_0_i_236_n_0 ));
LUT6 #(
.INIT(64'h343344441C11CCCC))
\z[30]_INST_0_i_237
(.I0(msb1__1[22]),
.I1(L1_carry_i_12_n_0),
.I2(\z[30]_INST_0_i_232_n_0 ),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(\z[30]_INST_0_i_237_n_0 ));
LUT6 #(
.INIT(64'h0808880820200020))
\z[30]_INST_0_i_238
(.I0(msb1__1[30]),
.I1(L1_carry_i_13_n_0),
.I2(L1_carry_i_9_n_0),
.I3(_carry_i_1_n_0),
.I4(\z[30]_INST_0_i_232_n_0 ),
.I5(L1_carry_i_12_n_0),
.O(\z[30]_INST_0_i_238_n_0 ));
LUT6 #(
.INIT(64'h0808880820200020))
\z[30]_INST_0_i_239
(.I0(msb1__1[23]),
.I1(L1_carry_i_13_n_0),
.I2(L1_carry_i_9_n_0),
.I3(_carry_i_1_n_0),
.I4(\z[30]_INST_0_i_232_n_0 ),
.I5(L1_carry_i_12_n_0),
.O(\z[30]_INST_0_i_239_n_0 ));
LUT6 #(
.INIT(64'h0800888820220000))
\z[30]_INST_0_i_240
(.I0(msb1__1[31]),
.I1(L1_carry_i_12_n_0),
.I2(\z[30]_INST_0_i_232_n_0 ),
.I3(_carry_i_1_n_0),
.I4(L1_carry_i_9_n_0),
.I5(L1_carry_i_13_n_0),
.O(\z[30]_INST_0_i_240_n_0 ));
LUT6 #(
.INIT(64'h66A6555500000000))
\z[30]_INST_0_i_241
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_9_n_0),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_232_n_0 ),
.I4(L1_carry_i_12_n_0),
.I5(msb1__1[21]),
.O(\z[30]_INST_0_i_241_n_0 ));
LUT6 #(
.INIT(64'h66A6555500000000))
\z[30]_INST_0_i_242
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_9_n_0),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_232_n_0 ),
.I4(L1_carry_i_12_n_0),
.I5(msb1__1[37]),
.O(\z[30]_INST_0_i_242_n_0 ));
LUT6 #(
.INIT(64'h66A6555500000000))
\z[30]_INST_0_i_243
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_9_n_0),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_232_n_0 ),
.I4(L1_carry_i_12_n_0),
.I5(msb1__1[29]),
.O(\z[30]_INST_0_i_243_n_0 ));
LUT6 #(
.INIT(64'h66A6555500000000))
\z[30]_INST_0_i_244
(.I0(L1_carry_i_13_n_0),
.I1(L1_carry_i_9_n_0),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_232_n_0 ),
.I4(L1_carry_i_12_n_0),
.I5(msb1__1[45]),
.O(\z[30]_INST_0_i_244_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFF5D5))
\z[30]_INST_0_i_245
(.I0(L1_carry_i_27_n_0),
.I1(msb1__1[32]),
.I2(\z[30]_INST_0_i_246_n_0 ),
.I3(msb1__1[33]),
.I4(msb1__1[36]),
.I5(msb1__1[37]),
.O(\z[30]_INST_0_i_245_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\z[30]_INST_0_i_246
(.I0(msb1__1[35]),
.I1(msb1__1[34]),
.O(\z[30]_INST_0_i_246_n_0 ));
LUT6 #(
.INIT(64'h4700FFFF47004700))
\z[30]_INST_0_i_29
(.I0(\z[30]_INST_0_i_94_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_96_n_0 ),
.I3(\z[30]_INST_0_i_43_n_0 ),
.I4(\z[30]_INST_0_i_97_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_29_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\z[30]_INST_0_i_3
(.I0(\z[30]_INST_0_i_17_n_0 ),
.I1(\z[30]_INST_0_i_18_n_0 ),
.I2(\z[30]_INST_0_i_19_n_0 ),
.I3(\z[30]_INST_0_i_20_n_0 ),
.I4(\z[30]_INST_0_i_21_n_0 ),
.I5(\z[30]_INST_0_i_22_n_0 ),
.O(\z[30]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_30
(.I0(\z[30]_INST_0_i_98_n_0 ),
.I1(\z[30]_INST_0_i_99_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_100_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_101_n_0 ),
.O(\z[30]_INST_0_i_30_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_31
(.I0(\z[30]_INST_0_i_102_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_103_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_31_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_32
(.I0(\z[30]_INST_0_i_104_n_0 ),
.I1(\z[30]_INST_0_i_105_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_99_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_106_n_0 ),
.O(\z[30]_INST_0_i_32_n_0 ));
LUT6 #(
.INIT(64'h47FF474700FF0000))
\z[30]_INST_0_i_33
(.I0(\z[30]_INST_0_i_107_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_94_n_0 ),
.I3(\z[30]_INST_0_i_97_n_0 ),
.I4(\z[30]_INST_0_i_43_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_33_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_34
(.I0(\z[30]_INST_0_i_101_n_0 ),
.I1(\z[30]_INST_0_i_104_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_98_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_99_n_0 ),
.O(\z[30]_INST_0_i_34_n_0 ));
LUT6 #(
.INIT(64'h4700FFFF47004700))
\z[30]_INST_0_i_35
(.I0(\z[30]_INST_0_i_107_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_94_n_0 ),
.I3(\z[30]_INST_0_i_43_n_0 ),
.I4(\z[30]_INST_0_i_102_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_35_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_36
(.I0(\z[30]_INST_0_i_99_n_0 ),
.I1(\z[30]_INST_0_i_106_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_101_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_104_n_0 ),
.O(\z[30]_INST_0_i_36_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_37
(.I0(\z[30]_INST_0_i_106_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_108_n_0 ),
.O(\z[30]_INST_0_i_37_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_38
(.I0(\z[30]_INST_0_i_104_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_105_n_0 ),
.O(\z[30]_INST_0_i_38_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_39
(.I0(\z[30]_INST_0_i_103_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_109_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_39_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_40
(.I0(\z[30]_INST_0_i_110_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_111_n_0 ),
.I3(L1_carry_i_16_n_0),
.I4(\z[30]_INST_0_i_112_n_0 ),
.O(\z[30]_INST_0_i_40_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\z[30]_INST_0_i_41
(.I0(\z[30]_INST_0_i_108_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_113_n_0 ),
.I3(L1_carry_i_16_n_0),
.I4(\z[30]_INST_0_i_114_n_0 ),
.O(\z[30]_INST_0_i_41_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFD8))
\z[30]_INST_0_i_42
(.I0(L1),
.I1(L1_carry_i_16_n_0),
.I2(_carry_n_6),
.I3(\z[30]_INST_0_i_115_n_0 ),
.I4(\z[30]_INST_0_i_95_n_0 ),
.O(\z[30]_INST_0_i_42_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h2))
\z[30]_INST_0_i_43
(.I0(_carry_i_1_n_0),
.I1(\z[30]_INST_0_i_116_n_0 ),
.O(\z[30]_INST_0_i_43_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_44
(.I0(\z[30]_INST_0_i_105_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_110_n_0 ),
.O(\z[30]_INST_0_i_44_n_0 ));
LUT6 #(
.INIT(64'h0000040F00000404))
\z[30]_INST_0_i_45
(.I0(\z[30]_INST_0_i_117_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_115_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_45_n_0 ));
LUT5 #(
.INIT(32'h10FF1010))
\z[30]_INST_0_i_46
(.I0(\z[30]_INST_0_i_95_n_0 ),
.I1(\z[30]_INST_0_i_119_n_0 ),
.I2(\z[30]_INST_0_i_57_n_0 ),
.I3(\z[30]_INST_0_i_109_n_0 ),
.I4(\z[30]_INST_0_i_43_n_0 ),
.O(\z[30]_INST_0_i_46_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_47
(.I0(\z[30]_INST_0_i_120_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_121_n_0 ),
.O(\z[30]_INST_0_i_47_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_48
(.I0(\z[30]_INST_0_i_122_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_123_n_0 ),
.O(\z[30]_INST_0_i_48_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_49
(.I0(\z[30]_INST_0_i_124_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_125_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_49_n_0 ));
LUT5 #(
.INIT(32'h115F1F5F))
\z[30]_INST_0_i_5
(.I0(\z[30]_INST_0_i_29_n_0 ),
.I1(\z[30]_INST_0_i_30_n_0 ),
.I2(\z[30]_INST_0_i_31_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_32_n_0 ),
.O(\z[30]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_50
(.I0(\z[30]_INST_0_i_123_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_100_n_0 ),
.O(\z[30]_INST_0_i_50_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_51
(.I0(\z[30]_INST_0_i_125_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_126_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_51_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_52
(.I0(\z[30]_INST_0_i_126_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_127_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_52_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_53
(.I0(\z[30]_INST_0_i_121_n_0 ),
.I1(\z[30]_INST_0_i_98_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_123_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_100_n_0 ),
.O(\z[30]_INST_0_i_53_n_0 ));
LUT6 #(
.INIT(64'h47FF474700FF0000))
\z[30]_INST_0_i_54
(.I0(\z[30]_INST_0_i_94_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_96_n_0 ),
.I3(\z[30]_INST_0_i_127_n_0 ),
.I4(\z[30]_INST_0_i_43_n_0 ),
.I5(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_54_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_55
(.I0(\z[30]_INST_0_i_100_n_0 ),
.I1(\z[30]_INST_0_i_101_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_121_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_98_n_0 ),
.O(\z[30]_INST_0_i_55_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_56
(.I0(\z[30]_INST_0_i_128_n_0 ),
.I1(\z[30]_INST_0_i_129_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_130_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_131_n_0 ),
.O(\z[30]_INST_0_i_56_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h1))
\z[30]_INST_0_i_57
(.I0(_carry_i_1_n_0),
.I1(\z[30]_INST_0_i_116_n_0 ),
.O(\z[30]_INST_0_i_57_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_58
(.I0(\z[30]_INST_0_i_132_n_0 ),
.I1(\z[30]_INST_0_i_133_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_134_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_135_n_0 ),
.O(\z[30]_INST_0_i_58_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_59
(.I0(\z[30]_INST_0_i_136_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_137_n_0 ),
.O(\z[30]_INST_0_i_59_n_0 ));
LUT5 #(
.INIT(32'h115F1F5F))
\z[30]_INST_0_i_6
(.I0(\z[30]_INST_0_i_33_n_0 ),
.I1(\z[30]_INST_0_i_34_n_0 ),
.I2(\z[30]_INST_0_i_35_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_36_n_0 ),
.O(\z[30]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\z[30]_INST_0_i_60
(.I0(\z[30]_INST_0_i_138_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_139_n_0 ),
.I3(_carry_i_10_n_0),
.I4(\z[30]_INST_0_i_122_n_0 ),
.O(\z[30]_INST_0_i_60_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\z[30]_INST_0_i_61
(.I0(\z[30]_INST_0_i_140_n_0 ),
.I1(L1_carry_i_16_n_0),
.I2(\z[30]_INST_0_i_141_n_0 ),
.I3(_carry_i_10_n_0),
.I4(\z[30]_INST_0_i_142_n_0 ),
.O(\z[30]_INST_0_i_61_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_62
(.I0(\z[30]_INST_0_i_58_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_143_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_62_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_63
(.I0(\z[30]_INST_0_i_143_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_144_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_63_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_64
(.I0(\z[30]_INST_0_i_142_n_0 ),
.I1(\z[30]_INST_0_i_120_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_145_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_122_n_0 ),
.O(\z[30]_INST_0_i_64_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'h4F44))
\z[30]_INST_0_i_65
(.I0(\z[30]_INST_0_i_144_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_124_n_0 ),
.I3(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_65_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_66
(.I0(\z[30]_INST_0_i_122_n_0 ),
.I1(\z[30]_INST_0_i_123_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_142_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_120_n_0 ),
.O(\z[30]_INST_0_i_66_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_67
(.I0(\z[30]_INST_0_i_146_n_0 ),
.I1(\z[30]_INST_0_i_147_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_148_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_149_n_0 ),
.O(\z[30]_INST_0_i_67_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_68
(.I0(\z[30]_INST_0_i_150_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_151_n_0 ),
.O(\z[30]_INST_0_i_68_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_69
(.I0(\z[30]_INST_0_i_152_n_0 ),
.I1(\z[30]_INST_0_i_153_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_154_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_155_n_0 ),
.O(\z[30]_INST_0_i_69_n_0 ));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[30]_INST_0_i_7
(.I0(L1),
.I1(\z[30]_INST_0_i_37_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_38_n_0 ),
.I4(\z[30]_INST_0_i_39_n_0 ),
.O(sel0[3]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_70
(.I0(\z[30]_INST_0_i_137_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_156_n_0 ),
.O(\z[30]_INST_0_i_70_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_71
(.I0(\z[30]_INST_0_i_155_n_0 ),
.I1(\z[30]_INST_0_i_130_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_152_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_153_n_0 ),
.O(\z[30]_INST_0_i_71_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_72
(.I0(\z[30]_INST_0_i_157_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_150_n_0 ),
.O(\z[30]_INST_0_i_72_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_73
(.I0(\z[30]_INST_0_i_153_n_0 ),
.I1(\z[30]_INST_0_i_128_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_155_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_130_n_0 ),
.O(\z[30]_INST_0_i_73_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_74
(.I0(\z[30]_INST_0_i_130_n_0 ),
.I1(\z[30]_INST_0_i_131_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_153_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_128_n_0 ),
.O(\z[30]_INST_0_i_74_n_0 ));
LUT6 #(
.INIT(64'h000002A2AAAA02A2))
\z[30]_INST_0_i_75
(.I0(L1),
.I1(\z[30]_INST_0_i_158_n_0 ),
.I2(_carry_i_10_n_0),
.I3(\z[30]_INST_0_i_159_n_0 ),
.I4(_carry_i_1_n_0),
.I5(\z[30]_INST_0_i_160_n_0 ),
.O(\z[30]_INST_0_i_75_n_0 ));
LUT6 #(
.INIT(64'h4C4C4C4040404C40))
\z[30]_INST_0_i_76
(.I0(\z[30]_INST_0_i_161_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_162_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_163_n_0 ),
.O(\z[30]_INST_0_i_76_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'hB))
\z[30]_INST_0_i_77
(.I0(\z[30]_INST_0_i_81_n_0 ),
.I1(\z[30]_INST_0_i_57_n_0 ),
.O(\z[30]_INST_0_i_77_n_0 ));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\z[30]_INST_0_i_78
(.I0(L1),
.I1(\z[30]_INST_0_i_164_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_155_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_154_n_0 ),
.O(\z[30]_INST_0_i_78_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h2))
\z[30]_INST_0_i_79
(.I0(\z[30]_INST_0_i_57_n_0 ),
.I1(\z[30]_INST_0_i_67_n_0 ),
.O(\z[30]_INST_0_i_79_n_0 ));
LUT6 #(
.INIT(64'h8A80FFFF8A808A80))
\z[30]_INST_0_i_8
(.I0(L1),
.I1(\z[30]_INST_0_i_40_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_41_n_0 ),
.I4(\z[30]_INST_0_i_42_n_0 ),
.I5(\z[30]_INST_0_i_43_n_0 ),
.O(sel0[0]));
LUT2 #(
.INIT(4'hB))
\z[30]_INST_0_i_80
(.I0(\z[30]_INST_0_i_82_n_0 ),
.I1(\z[30]_INST_0_i_43_n_0 ),
.O(\z[30]_INST_0_i_80_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_81
(.I0(\z[30]_INST_0_i_148_n_0 ),
.I1(\z[30]_INST_0_i_149_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_147_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_165_n_0 ),
.O(\z[30]_INST_0_i_81_n_0 ));
LUT6 #(
.INIT(64'hCFC05F5FCFC05050))
\z[30]_INST_0_i_82
(.I0(\z[30]_INST_0_i_163_n_0 ),
.I1(\z[30]_INST_0_i_135_n_0 ),
.I2(\z[30]_INST_0_i_95_n_0 ),
.I3(\z[30]_INST_0_i_166_n_0 ),
.I4(\z[30]_INST_0_i_118_n_0 ),
.I5(\z[30]_INST_0_i_167_n_0 ),
.O(\z[30]_INST_0_i_82_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_83
(.I0(\z[30]_INST_0_i_158_n_0 ),
.I1(\z[30]_INST_0_i_152_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_168_n_0 ),
.I4(_carry_i_10_n_0),
.I5(\z[30]_INST_0_i_154_n_0 ),
.O(\z[30]_INST_0_i_83_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[30]_INST_0_i_9
(.I0(\z[30]_INST_0_i_41_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[30]_INST_0_i_44_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_45_n_0 ),
.O(\z[30]_INST_0_i_9_n_0 ));
LUT5 #(
.INIT(32'hFFFFF4F7))
\z[30]_INST_0_i_94
(.I0(msb1__1[1]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_169_n_0 ),
.I3(msb1__1[5]),
.I4(\z[30]_INST_0_i_170_n_0 ),
.O(\z[30]_INST_0_i_94_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hCA))
\z[30]_INST_0_i_95
(.I0(_carry_n_7),
.I1(_carry_i_10_n_0),
.I2(L1),
.O(\z[30]_INST_0_i_95_n_0 ));
LUT5 #(
.INIT(32'hFFFFF4F7))
\z[30]_INST_0_i_96
(.I0(msb1__1[3]),
.I1(\z[30]_INST_0_i_118_n_0 ),
.I2(\z[30]_INST_0_i_170_n_0 ),
.I3(msb1__1[7]),
.I4(\z[30]_INST_0_i_169_n_0 ),
.O(\z[30]_INST_0_i_96_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\z[30]_INST_0_i_97
(.I0(\z[30]_INST_0_i_171_n_0 ),
.I1(\z[30]_INST_0_i_95_n_0 ),
.I2(\z[30]_INST_0_i_172_n_0 ),
.O(\z[30]_INST_0_i_97_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_98
(.I0(\z[30]_INST_0_i_173_n_0 ),
.I1(\z[30]_INST_0_i_174_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_175_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_176_n_0 ),
.O(\z[30]_INST_0_i_98_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\z[30]_INST_0_i_99
(.I0(\z[30]_INST_0_i_177_n_0 ),
.I1(\z[30]_INST_0_i_178_n_0 ),
.I2(L1_carry_i_16_n_0),
.I3(\z[30]_INST_0_i_179_n_0 ),
.I4(L1_carry_i_17_n_0),
.I5(\z[30]_INST_0_i_180_n_0 ),
.O(\z[30]_INST_0_i_99_n_0 ));
CARRY4 \z[3]_INST_0_i_1
(.CI(1'b0),
.CO({\z[3]_INST_0_i_1_n_0 ,\z[3]_INST_0_i_1_n_1 ,\z[3]_INST_0_i_1_n_2 ,\z[3]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,sel0[0]}),
.O(z_mantissa[3:0]),
.S({\z[3]_INST_0_i_2_n_0 ,\z[3]_INST_0_i_3_n_0 ,sel0[1],\z[3]_INST_0_i_5_n_0 }));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[3]_INST_0_i_2
(.I0(L1),
.I1(\z[30]_INST_0_i_37_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_38_n_0 ),
.I4(\z[30]_INST_0_i_39_n_0 ),
.O(\z[3]_INST_0_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFF8A80))
\z[3]_INST_0_i_3
(.I0(L1),
.I1(\z[30]_INST_0_i_44_n_0 ),
.I2(_carry_i_1_n_0),
.I3(\z[30]_INST_0_i_37_n_0 ),
.I4(\z[30]_INST_0_i_46_n_0 ),
.O(\z[3]_INST_0_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\z[3]_INST_0_i_4
(.I0(\z[30]_INST_0_i_9_n_0 ),
.O(sel0[1]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAA9AA))
\z[3]_INST_0_i_5
(.I0(sel0[0]),
.I1(\z[30]_INST_0_i_3_n_0 ),
.I2(\z[3]_INST_0_i_6_n_0 ),
.I3(\z[3]_INST_0_i_7_n_0 ),
.I4(\z[3]_INST_0_i_8_n_0 ),
.I5(\z[3]_INST_0_i_9_n_0 ),
.O(\z[3]_INST_0_i_5_n_0 ));
LUT4 #(
.INIT(16'hFFF7))
\z[3]_INST_0_i_6
(.I0(sel0[0]),
.I1(sel0[2]),
.I2(\z[7]_INST_0_i_8_n_0 ),
.I3(\z[7]_INST_0_i_6_n_0 ),
.O(\z[3]_INST_0_i_6_n_0 ));
LUT4 #(
.INIT(16'h0004))
\z[3]_INST_0_i_7
(.I0(\z[7]_INST_0_i_9_n_0 ),
.I1(sel0[10]),
.I2(\z[30]_INST_0_i_11_n_0 ),
.I3(\z[30]_INST_0_i_15_n_0 ),
.O(\z[3]_INST_0_i_7_n_0 ));
LUT4 #(
.INIT(16'hFFEF))
\z[3]_INST_0_i_8
(.I0(\z[15]_INST_0_i_7_n_0 ),
.I1(\z[15]_INST_0_i_6_n_0 ),
.I2(sel0[3]),
.I3(\z[7]_INST_0_i_7_n_0 ),
.O(\z[3]_INST_0_i_8_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\z[3]_INST_0_i_9
(.I0(\z[30]_INST_0_i_9_n_0 ),
.I1(\z[11]_INST_0_i_6_n_0 ),
.I2(\z[11]_INST_0_i_7_n_0 ),
.I3(\z[30]_INST_0_i_14_n_0 ),
.O(\z[3]_INST_0_i_9_n_0 ));
CARRY4 \z[7]_INST_0_i_1
(.CI(\z[3]_INST_0_i_1_n_0 ),
.CO({\z[7]_INST_0_i_1_n_0 ,\z[7]_INST_0_i_1_n_1 ,\z[7]_INST_0_i_1_n_2 ,\z[7]_INST_0_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(z_mantissa[7:4]),
.S(sel0[7:4]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\z[7]_INST_0_i_10
(.I0(\z[30]_INST_0_i_98_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_99_n_0 ),
.O(\z[7]_INST_0_i_10_n_0 ));
LUT3 #(
.INIT(8'hB8))
\z[7]_INST_0_i_11
(.I0(\z[30]_INST_0_i_101_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_104_n_0 ),
.O(\z[7]_INST_0_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\z[7]_INST_0_i_12
(.I0(\z[30]_INST_0_i_99_n_0 ),
.I1(_carry_i_10_n_0),
.I2(\z[30]_INST_0_i_106_n_0 ),
.O(\z[7]_INST_0_i_12_n_0 ));
LUT1 #(
.INIT(2'h1))
\z[7]_INST_0_i_2
(.I0(\z[7]_INST_0_i_6_n_0 ),
.O(sel0[7]));
LUT1 #(
.INIT(2'h1))
\z[7]_INST_0_i_3
(.I0(\z[7]_INST_0_i_7_n_0 ),
.O(sel0[6]));
LUT1 #(
.INIT(2'h1))
\z[7]_INST_0_i_4
(.I0(\z[7]_INST_0_i_8_n_0 ),
.O(sel0[5]));
LUT1 #(
.INIT(2'h1))
\z[7]_INST_0_i_5
(.I0(\z[7]_INST_0_i_9_n_0 ),
.O(sel0[4]));
LUT5 #(
.INIT(32'h000047FF))
\z[7]_INST_0_i_6
(.I0(\z[7]_INST_0_i_10_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[11]_INST_0_i_9_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_29_n_0 ),
.O(\z[7]_INST_0_i_6_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[7]_INST_0_i_7
(.I0(\z[7]_INST_0_i_11_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[7]_INST_0_i_10_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_33_n_0 ),
.O(\z[7]_INST_0_i_7_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[7]_INST_0_i_8
(.I0(\z[7]_INST_0_i_12_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[7]_INST_0_i_11_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_35_n_0 ),
.O(\z[7]_INST_0_i_8_n_0 ));
LUT5 #(
.INIT(32'h000047FF))
\z[7]_INST_0_i_9
(.I0(\z[30]_INST_0_i_38_n_0 ),
.I1(_carry_i_1_n_0),
.I2(\z[7]_INST_0_i_12_n_0 ),
.I3(L1),
.I4(\z[30]_INST_0_i_31_n_0 ),
.O(\z[7]_INST_0_i_9_n_0 ));
CARRY4 z_exponent0__0_carry
(.CI(1'b0),
.CO({z_exponent0__0_carry_n_0,z_exponent0__0_carry_n_1,z_exponent0__0_carry_n_2,z_exponent0__0_carry_n_3}),
.CYINIT(1'b1),
.DI({z_exponent0__0_carry_i_1_n_0,z_exponent0__0_carry_i_2_n_0,z_exponent0__0_carry_i_3_n_0,1'b1}),
.O(data0[3:0]),
.S({z_exponent0__0_carry_i_4_n_0,z_exponent0__0_carry_i_5_n_0,z_exponent0__0_carry_i_6_n_0,z_exponent0__0_carry_i_7_n_0}));
CARRY4 z_exponent0__0_carry__0
(.CI(z_exponent0__0_carry_n_0),
.CO({NLW_z_exponent0__0_carry__0_CO_UNCONNECTED[3],z_exponent0__0_carry__0_n_1,z_exponent0__0_carry__0_n_2,z_exponent0__0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,z_exponent0__0_carry__0_i_1_n_0,z_exponent0__0_carry__0_i_2_n_0,z_exponent0__0_carry__0_i_3_n_0}),
.O(data0[7:4]),
.S({z_exponent0__0_carry__0_i_4_n_0,z_exponent0__0_carry__0_i_5_n_0,z_exponent0__0_carry__0_i_6_n_0,z_exponent0__0_carry__0_i_7_n_0}));
LUT5 #(
.INIT(32'hFFA9A900))
z_exponent0__0_carry__0_i_1
(.I0(L1_carry_i_13_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(L1_carry_i_12_n_0),
.I3(y[28]),
.I4(x[28]),
.O(z_exponent0__0_carry__0_i_1_n_0));
(* HLUTNM = "lutpair3" *)
LUT4 #(
.INIT(16'hF990))
z_exponent0__0_carry__0_i_2
(.I0(L1_carry_i_12_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(y[27]),
.I3(x[27]),
.O(z_exponent0__0_carry__0_i_2_n_0));
LUT5 #(
.INIT(32'hFF1E1E00))
z_exponent0__0_carry__0_i_3
(.I0(L1_carry_i_10_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_9_n_0),
.I3(y[26]),
.I4(x[26]),
.O(z_exponent0__0_carry__0_i_3_n_0));
LUT6 #(
.INIT(64'h6999699969999996))
z_exponent0__0_carry__0_i_4
(.I0(x[30]),
.I1(y[30]),
.I2(x[29]),
.I3(y[29]),
.I4(msb1__1[47]),
.I5(msb1__1[46]),
.O(z_exponent0__0_carry__0_i_4_n_0));
LUT5 #(
.INIT(32'h96969669))
z_exponent0__0_carry__0_i_5
(.I0(z_exponent0__0_carry__0_i_1_n_0),
.I1(y[29]),
.I2(x[29]),
.I3(msb1__1[46]),
.I4(msb1__1[47]),
.O(z_exponent0__0_carry__0_i_5_n_0));
LUT6 #(
.INIT(64'h56A9A956A95656A9))
z_exponent0__0_carry__0_i_6
(.I0(L1_carry_i_13_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(L1_carry_i_12_n_0),
.I3(z_exponent0__0_carry__0_i_2_n_0),
.I4(y[28]),
.I5(x[28]),
.O(z_exponent0__0_carry__0_i_6_n_0));
LUT5 #(
.INIT(32'h69969669))
z_exponent0__0_carry__0_i_7
(.I0(L1_carry_i_12_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(z_exponent0__0_carry__0_i_3_n_0),
.I3(x[27]),
.I4(y[27]),
.O(z_exponent0__0_carry__0_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h01))
z_exponent0__0_carry__0_i_8
(.I0(L1_carry_i_9_n_0),
.I1(L1_carry_i_10_n_0),
.I2(L1_carry_i_11_n_0),
.O(z_exponent0__0_carry__0_i_8_n_0));
(* HLUTNM = "lutpair2" *)
LUT4 #(
.INIT(16'hF660))
z_exponent0__0_carry_i_1
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(y[25]),
.I3(x[25]),
.O(z_exponent0__0_carry_i_1_n_0));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'hE8))
z_exponent0__0_carry_i_2
(.I0(y[24]),
.I1(x[24]),
.I2(L1_carry_i_10_n_0),
.O(z_exponent0__0_carry_i_2_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'hE8))
z_exponent0__0_carry_i_3
(.I0(x[23]),
.I1(y[23]),
.I2(_carry_i_1_n_0),
.O(z_exponent0__0_carry_i_3_n_0));
LUT6 #(
.INIT(64'hE11E1EE11EE1E11E))
z_exponent0__0_carry_i_4
(.I0(L1_carry_i_10_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_9_n_0),
.I3(z_exponent0__0_carry_i_1_n_0),
.I4(y[26]),
.I5(x[26]),
.O(z_exponent0__0_carry_i_4_n_0));
LUT5 #(
.INIT(32'h96696996))
z_exponent0__0_carry_i_5
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(z_exponent0__0_carry_i_2_n_0),
.I3(y[25]),
.I4(x[25]),
.O(z_exponent0__0_carry_i_5_n_0));
LUT4 #(
.INIT(16'h6996))
z_exponent0__0_carry_i_6
(.I0(y[24]),
.I1(L1_carry_i_10_n_0),
.I2(x[24]),
.I3(z_exponent0__0_carry_i_3_n_0),
.O(z_exponent0__0_carry_i_6_n_0));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'h69))
z_exponent0__0_carry_i_7
(.I0(x[23]),
.I1(y[23]),
.I2(_carry_i_1_n_0),
.O(z_exponent0__0_carry_i_7_n_0));
CARRY4 z_exponent1_carry
(.CI(1'b0),
.CO({z_exponent1_carry_n_0,z_exponent1_carry_n_1,z_exponent1_carry_n_2,z_exponent1_carry_n_3}),
.CYINIT(1'b0),
.DI({z_exponent0__0_carry_i_1_n_0,z_exponent0__0_carry_i_2_n_0,z_exponent1_carry_i_1__0_n_0,x[23]}),
.O(data1[3:0]),
.S({z_exponent1_carry_i_2__0_n_0,z_exponent1_carry_i_3__0_n_0,z_exponent1_carry_i_4_n_0,z_exponent1_carry_i_5_n_0}));
CARRY4 z_exponent1_carry__0
(.CI(z_exponent1_carry_n_0),
.CO({NLW_z_exponent1_carry__0_CO_UNCONNECTED[3],z_exponent1_carry__0_n_1,z_exponent1_carry__0_n_2,z_exponent1_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,z_exponent0__0_carry__0_i_1_n_0,z_exponent0__0_carry__0_i_2_n_0,z_exponent0__0_carry__0_i_3_n_0}),
.O(data1[7:4]),
.S({z_exponent1_carry_i_1_n_0,z_exponent1_carry_i_2_n_0,z_exponent1_carry_i_3_n_0,z_exponent1_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h6999699969999996))
z_exponent1_carry_i_1
(.I0(x[30]),
.I1(y[30]),
.I2(x[29]),
.I3(y[29]),
.I4(msb1__1[47]),
.I5(msb1__1[46]),
.O(z_exponent1_carry_i_1_n_0));
(* HLUTNM = "lutpair4" *)
LUT2 #(
.INIT(4'hE))
z_exponent1_carry_i_1__0
(.I0(y[23]),
.I1(_carry_i_1_n_0),
.O(z_exponent1_carry_i_1__0_n_0));
LUT5 #(
.INIT(32'h96969669))
z_exponent1_carry_i_2
(.I0(z_exponent0__0_carry__0_i_1_n_0),
.I1(y[29]),
.I2(x[29]),
.I3(msb1__1[46]),
.I4(msb1__1[47]),
.O(z_exponent1_carry_i_2_n_0));
LUT6 #(
.INIT(64'hE11E1EE11EE1E11E))
z_exponent1_carry_i_2__0
(.I0(L1_carry_i_10_n_0),
.I1(L1_carry_i_11_n_0),
.I2(L1_carry_i_9_n_0),
.I3(z_exponent0__0_carry_i_1_n_0),
.I4(y[26]),
.I5(x[26]),
.O(z_exponent1_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h56A9A956A95656A9))
z_exponent1_carry_i_3
(.I0(L1_carry_i_13_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(L1_carry_i_12_n_0),
.I3(z_exponent0__0_carry__0_i_2_n_0),
.I4(y[28]),
.I5(x[28]),
.O(z_exponent1_carry_i_3_n_0));
(* HLUTNM = "lutpair2" *)
LUT5 #(
.INIT(32'h96696996))
z_exponent1_carry_i_3__0
(.I0(L1_carry_i_11_n_0),
.I1(L1_carry_i_10_n_0),
.I2(y[25]),
.I3(x[25]),
.I4(z_exponent0__0_carry_i_2_n_0),
.O(z_exponent1_carry_i_3__0_n_0));
(* HLUTNM = "lutpair1" *)
LUT4 #(
.INIT(16'h6996))
z_exponent1_carry_i_4
(.I0(y[24]),
.I1(x[24]),
.I2(L1_carry_i_10_n_0),
.I3(z_exponent1_carry_i_1__0_n_0),
.O(z_exponent1_carry_i_4_n_0));
(* HLUTNM = "lutpair3" *)
LUT5 #(
.INIT(32'h69969669))
z_exponent1_carry_i_4__0
(.I0(L1_carry_i_12_n_0),
.I1(z_exponent0__0_carry__0_i_8_n_0),
.I2(y[27]),
.I3(x[27]),
.I4(z_exponent0__0_carry__0_i_3_n_0),
.O(z_exponent1_carry_i_4__0_n_0));
(* HLUTNM = "lutpair4" *)
LUT3 #(
.INIT(8'h69))
z_exponent1_carry_i_5
(.I0(y[23]),
.I1(_carry_i_1_n_0),
.I2(x[23]),
.O(z_exponent1_carry_i_5_n_0));
endmodule |
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule |
module cpu_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule |
module mult_altfp_mult_mrp
(
clock,
dataa,
datab,
nan,
overflow,
result,
underflow) ;
input clock;
input [31:0] dataa;
input [31:0] datab;
output nan;
output overflow;
output [31:0] result;
output underflow;
reg dataa_exp_all_one_ff_p1;
reg dataa_exp_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p1;
reg dataa_man_not_zero_ff_p2;
reg datab_exp_all_one_ff_p1;
reg datab_exp_not_zero_ff_p1;
reg datab_man_not_zero_ff_p1;
reg datab_man_not_zero_ff_p2;
reg [9:0] delay_exp2_bias;
reg [9:0] delay_exp_bias;
reg delay_man_product_msb;
reg delay_man_product_msb_p0;
reg [8:0] exp_add_p1;
reg [7:0] exp_result_ff;
reg input_is_infinity_dffe_0;
reg input_is_infinity_dffe_1;
reg input_is_infinity_ff1;
reg input_is_nan_dffe_0;
reg input_is_nan_dffe_1;
reg input_is_nan_ff1;
reg input_not_zero_dffe_0;
reg input_not_zero_dffe_1;
reg input_not_zero_ff1;
reg lsb_dffe;
reg [22:0] man_result_ff;
reg [23:0] man_round_p;
reg [24:0] man_round_p2;
reg nan_ff;
reg overflow_ff;
reg round_dffe;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg sticky_dffe;
reg underflow_ff;
wire [8:0] wire_exp_add_adder_result;
wire [9:0] wire_exp_adj_adder_result;
wire [9:0] wire_exp_bias_subtr_result;
wire [24:0] wire_man_round_adder_result;
wire [47:0] wire_man_product2_mult_result;
wire aclr;
wire [9:0] bias;
wire clk_en;
wire [7:0] dataa_exp_all_one;
wire [7:0] dataa_exp_not_zero;
wire [22:0] dataa_man_not_zero;
wire [7:0] datab_exp_all_one;
wire [7:0] datab_exp_not_zero;
wire [22:0] datab_man_not_zero;
wire exp_is_inf;
wire exp_is_zero;
wire [9:0] expmod;
wire [7:0] inf_num;
wire lsb_bit;
wire [23:0] man_result_round;
wire [24:0] man_shift_full;
wire [7:0] result_exp_all_one;
wire [8:0] result_exp_not_zero;
wire round_bit;
wire round_carry;
wire [22:0] sticky_bit;
// synopsys translate_off
initial
dataa_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_all_one_ff_p1 <= dataa_exp_all_one[7];
// synopsys translate_off
initial
dataa_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_exp_not_zero_ff_p1 <= dataa_exp_not_zero[7];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p1 <= dataa_man_not_zero[10];
// synopsys translate_off
initial
dataa_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dataa_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) dataa_man_not_zero_ff_p2 <= dataa_man_not_zero[22];
// synopsys translate_off
initial
datab_exp_all_one_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_all_one_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_all_one_ff_p1 <= datab_exp_all_one[7];
// synopsys translate_off
initial
datab_exp_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_exp_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_exp_not_zero_ff_p1 <= datab_exp_not_zero[7];
// synopsys translate_off
initial
datab_man_not_zero_ff_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p1 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p1 <= datab_man_not_zero[10];
// synopsys translate_off
initial
datab_man_not_zero_ff_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) datab_man_not_zero_ff_p2 <= 1'b0;
else if (clk_en == 1'b1) datab_man_not_zero_ff_p2 <= datab_man_not_zero[22];
// synopsys translate_off
initial
delay_exp2_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp2_bias <= 10'b0;
else if (clk_en == 1'b1) delay_exp2_bias <= delay_exp_bias;
// synopsys translate_off
initial
delay_exp_bias = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_exp_bias <= 10'b0;
else if (clk_en == 1'b1) delay_exp_bias <= wire_exp_bias_subtr_result;
// synopsys translate_off
initial
delay_man_product_msb = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb <= delay_man_product_msb_p0;
// synopsys translate_off
initial
delay_man_product_msb_p0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) delay_man_product_msb_p0 <= 1'b0;
else if (clk_en == 1'b1) delay_man_product_msb_p0 <= wire_man_product2_mult_result[47];
// synopsys translate_off
initial
exp_add_p1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_add_p1 <= 9'b0;
else if (clk_en == 1'b1) exp_add_p1 <= wire_exp_add_adder_result;
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 8'b0;
else if (clk_en == 1'b1) exp_result_ff <= ((inf_num & {8{((exp_is_inf | input_is_infinity_ff1) | input_is_nan_ff1)}}) | ((wire_exp_adj_adder_result[7:0] & {8{(~ exp_is_zero)}}) & {8{input_not_zero_ff1}}));
// synopsys translate_off
initial
input_is_infinity_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (~ (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2))) | (datab_exp_all_one_ff_p1 & (~ (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2))));
// synopsys translate_off
initial
input_is_infinity_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_dffe_1 <= input_is_infinity_dffe_0;
// synopsys translate_off
initial
input_is_infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_ff1 <= input_is_infinity_dffe_1;
// synopsys translate_off
initial
input_is_nan_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_0 <= ((dataa_exp_all_one_ff_p1 & (dataa_man_not_zero_ff_p1 | dataa_man_not_zero_ff_p2)) | (datab_exp_all_one_ff_p1 & (datab_man_not_zero_ff_p1 | datab_man_not_zero_ff_p2)));
// synopsys translate_off
initial
input_is_nan_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_dffe_1 <= input_is_nan_dffe_0;
// synopsys translate_off
initial
input_is_nan_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_ff1 <= input_is_nan_dffe_1;
// synopsys translate_off
initial
input_not_zero_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_0 <= (dataa_exp_not_zero_ff_p1 & datab_exp_not_zero_ff_p1);
// synopsys translate_off
initial
input_not_zero_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_dffe_1 <= input_not_zero_dffe_0;
// synopsys translate_off
initial
input_not_zero_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_not_zero_ff1 <= 1'b0;
else if (clk_en == 1'b1) input_not_zero_ff1 <= input_not_zero_dffe_1;
// synopsys translate_off
initial
lsb_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lsb_dffe <= 1'b0;
else if (clk_en == 1'b1) lsb_dffe <= lsb_bit;
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 23'b0;
else if (clk_en == 1'b1) man_result_ff <= {((((((man_result_round[22] & input_not_zero_ff1) & (~ input_is_infinity_ff1)) & (~ exp_is_inf)) & (~ exp_is_zero)) | (input_is_infinity_ff1 & (~ input_not_zero_ff1))) | input_is_nan_ff1), (((((man_result_round[21:0] & {22{input_not_zero_ff1}}) & {22{(~ input_is_infinity_ff1)}}) & {22{(~ exp_is_inf)}}) & {22{(~ exp_is_zero)}}) & {22{(~ input_is_nan_ff1)}})};
// synopsys translate_off
initial
man_round_p = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p <= 24'b0;
else if (clk_en == 1'b1) man_round_p <= man_shift_full[24:1];
// synopsys translate_off
initial
man_round_p2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_p2 <= 25'b0;
else if (clk_en == 1'b1) man_round_p2 <= wire_man_round_adder_result;
// synopsys translate_off
initial
nan_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_ff <= 1'b0;
else if (clk_en == 1'b1) nan_ff <= (input_is_nan_ff1 | (input_is_infinity_ff1 & (~ input_not_zero_ff1)));
// synopsys translate_off
initial
overflow_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) overflow_ff <= 1'b0;
else if (clk_en == 1'b1) overflow_ff <= (((exp_is_inf | input_is_infinity_ff1) & (~ input_is_nan_ff1)) & (~ (input_is_infinity_ff1 & (~ input_not_zero_ff1))));
// synopsys translate_off
initial
round_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_dffe <= 1'b0;
else if (clk_en == 1'b1) round_dffe <= round_bit;
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= (dataa[31] ^ datab[31]);
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sticky_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sticky_dffe <= 1'b0;
else if (clk_en == 1'b1) sticky_dffe <= sticky_bit[22];
// synopsys translate_off
initial
underflow_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) underflow_ff <= 1'b0;
else if (clk_en == 1'b1) underflow_ff <= (((exp_is_zero & input_not_zero_ff1) & (~ input_is_nan_ff1)) & (~ (input_is_infinity_ff1 & (~ input_not_zero_ff1))));
lpm_add_sub exp_add_adder
(
.aclr(aclr),
.cin(1'b0),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b0, dataa[30:23]}),
.datab({1'b0, datab[30:23]}),
.overflow(),
.result(wire_exp_add_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_add_adder.lpm_pipeline = 1,
exp_add_adder.lpm_width = 9,
exp_add_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_adj_adder
(
.cin(1'b0),
.cout(),
.dataa(delay_exp2_bias),
.datab(expmod),
.overflow(),
.result(wire_exp_adj_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_adj_adder.lpm_width = 10,
exp_adj_adder.lpm_type = "lpm_add_sub";
lpm_add_sub exp_bias_subtr
(
.cout(),
.dataa({1'b0, exp_add_p1[8:0]}),
.datab({bias[9:0]}),
.overflow(),
.result(wire_exp_bias_subtr_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_bias_subtr.lpm_direction = "SUB",
exp_bias_subtr.lpm_pipeline = 0,
exp_bias_subtr.lpm_representation = "UNSIGNED",
exp_bias_subtr.lpm_width = 10,
exp_bias_subtr.lpm_type = "lpm_add_sub";
lpm_add_sub man_round_adder
(
.cout(),
.dataa({1'b0, man_round_p}),
.datab({{24{1'b0}}, round_carry}),
.overflow(),
.result(wire_man_round_adder_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_round_adder.lpm_pipeline = 0,
man_round_adder.lpm_width = 25,
man_round_adder.lpm_type = "lpm_add_sub";
lpm_mult man_product2_mult
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b1, dataa[22:0]}),
.datab({1'b1, datab[22:0]}),
.result(wire_man_product2_mult_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_product2_mult.lpm_pipeline = 2,
man_product2_mult.lpm_representation = "UNSIGNED",
man_product2_mult.lpm_widtha = 24,
man_product2_mult.lpm_widthb = 24,
man_product2_mult.lpm_widthp = 48,
man_product2_mult.lpm_widths = 1,
man_product2_mult.lpm_type = "lpm_mult",
man_product2_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign
aclr = 1'b0,
bias = {{3{1'b0}}, {7{1'b1}}},
clk_en = 1'b1,
dataa_exp_all_one = {(dataa[30] & dataa_exp_all_one[6]), (dataa[29] & dataa_exp_all_one[5]), (dataa[28] & dataa_exp_all_one[4]), (dataa[27] & dataa_exp_all_one[3]), (dataa[26] & dataa_exp_all_one[2]), (dataa[25] & dataa_exp_all_one[1]), (dataa[24] & dataa_exp_all_one[0]), dataa[23]},
dataa_exp_not_zero = {(dataa[30] | dataa_exp_not_zero[6]), (dataa[29] | dataa_exp_not_zero[5]), (dataa[28] | dataa_exp_not_zero[4]), (dataa[27] | dataa_exp_not_zero[3]), (dataa[26] | dataa_exp_not_zero[2]), (dataa[25] | dataa_exp_not_zero[1]), (dataa[24] | dataa_exp_not_zero[0]), dataa[23]},
dataa_man_not_zero = {(dataa[22] | dataa_man_not_zero[21]), (dataa[21] | dataa_man_not_zero[20]), (dataa[20] | dataa_man_not_zero[19]), (dataa[19] | dataa_man_not_zero[18]), (dataa[18] | dataa_man_not_zero[17]), (dataa[17] | dataa_man_not_zero[16]), (dataa[16] | dataa_man_not_zero[15]), (dataa[15] | dataa_man_not_zero[14]), (dataa[14] | dataa_man_not_zero[13]), (dataa[13] | dataa_man_not_zero[12]), (dataa[12] | dataa_man_not_zero[11]), dataa[11], (dataa[10] | dataa_man_not_zero[9]), (dataa[9] | dataa_man_not_zero[8]), (dataa[8] | dataa_man_not_zero[7]), (dataa[7] | dataa_man_not_zero[6]), (dataa[6] | dataa_man_not_zero[5]), (dataa[5] | dataa_man_not_zero[4]), (dataa[4] | dataa_man_not_zero[3]), (dataa[3] | dataa_man_not_zero[2]), (dataa[2] | dataa_man_not_zero[1]), (dataa[1] | dataa_man_not_zero[0]), dataa[0]},
datab_exp_all_one = {(datab[30] & datab_exp_all_one[6]), (datab[29] & datab_exp_all_one[5]), (datab[28] & datab_exp_all_one[4]), (datab[27] & datab_exp_all_one[3]), (datab[26] & datab_exp_all_one[2]), (datab[25] & datab_exp_all_one[1]), (datab[24] & datab_exp_all_one[0]), datab[23]},
datab_exp_not_zero = {(datab[30] | datab_exp_not_zero[6]), (datab[29] | datab_exp_not_zero[5]), (datab[28] | datab_exp_not_zero[4]), (datab[27] | datab_exp_not_zero[3]), (datab[26] | datab_exp_not_zero[2]), (datab[25] | datab_exp_not_zero[1]), (datab[24] | datab_exp_not_zero[0]), datab[23]},
datab_man_not_zero = {(datab[22] | datab_man_not_zero[21]), (datab[21] | datab_man_not_zero[20]), (datab[20] | datab_man_not_zero[19]), (datab[19] | datab_man_not_zero[18]), (datab[18] | datab_man_not_zero[17]), (datab[17] | datab_man_not_zero[16]), (datab[16] | datab_man_not_zero[15]), (datab[15] | datab_man_not_zero[14]), (datab[14] | datab_man_not_zero[13]), (datab[13] | datab_man_not_zero[12]), (datab[12] | datab_man_not_zero[11]), datab[11], (datab[10] | datab_man_not_zero[9]), (datab[9] | datab_man_not_zero[8]), (datab[8] | datab_man_not_zero[7]), (datab[7] | datab_man_not_zero[6]), (datab[6] | datab_man_not_zero[5]), (datab[5] | datab_man_not_zero[4]), (datab[4] | datab_man_not_zero[3]), (datab[3] | datab_man_not_zero[2]), (datab[2] | datab_man_not_zero[1]), (datab[1] | datab_man_not_zero[0]), datab[0]},
exp_is_inf = (((~ wire_exp_adj_adder_result[9]) & wire_exp_adj_adder_result[8]) | ((~ wire_exp_adj_adder_result[8]) & result_exp_all_one[7])),
exp_is_zero = (wire_exp_adj_adder_result[9] | (~ result_exp_not_zero[8])),
expmod = {{8{1'b0}}, (delay_man_product_msb & man_round_p2[24]), (delay_man_product_msb ^ man_round_p2[24])},
inf_num = {8{1'b1}},
lsb_bit = man_shift_full[1],
man_result_round = ((man_round_p2[23:0] & {24{(~ man_round_p2[24])}}) | (man_round_p2[24:1] & {24{man_round_p2[24]}})),
man_shift_full = ((wire_man_product2_mult_result[46:22] & {25{(~ wire_man_product2_mult_result[47])}}) | (wire_man_product2_mult_result[47:23] & {25{wire_man_product2_mult_result[47]}})),
nan = nan_ff,
overflow = overflow_ff,
result = {sign_node_ff4[0:0], exp_result_ff[7:0], man_result_ff[22:0]},
result_exp_all_one = {(result_exp_all_one[6] & wire_exp_adj_adder_result[7]), (result_exp_all_one[5] & wire_exp_adj_adder_result[6]), (result_exp_all_one[4] & wire_exp_adj_adder_result[5]), (result_exp_all_one[3] & wire_exp_adj_adder_result[4]), (result_exp_all_one[2] & wire_exp_adj_adder_result[3]), (result_exp_all_one[1] & wire_exp_adj_adder_result[2]), (result_exp_all_one[0] & wire_exp_adj_adder_result[1]), wire_exp_adj_adder_result[0]},
result_exp_not_zero = {(result_exp_not_zero[7] | wire_exp_adj_adder_result[8]), (result_exp_not_zero[6] | wire_exp_adj_adder_result[7]), (result_exp_not_zero[5] | wire_exp_adj_adder_result[6]), (result_exp_not_zero[4] | wire_exp_adj_adder_result[5]), (result_exp_not_zero[3] | wire_exp_adj_adder_result[4]), (result_exp_not_zero[2] | wire_exp_adj_adder_result[3]), (result_exp_not_zero[1] | wire_exp_adj_adder_result[2]), (result_exp_not_zero[0] | wire_exp_adj_adder_result[1]), wire_exp_adj_adder_result[0]},
round_bit = man_shift_full[0],
round_carry = (round_dffe & (lsb_dffe | sticky_dffe)),
sticky_bit = {(sticky_bit[21] | (wire_man_product2_mult_result[47] & wire_man_product2_mult_result[22])), (sticky_bit[20] | wire_man_product2_mult_result[21]), (sticky_bit[19] | wire_man_product2_mult_result[20]), (sticky_bit[18] | wire_man_product2_mult_result[19]), (sticky_bit[17] | wire_man_product2_mult_result[18]), (sticky_bit[16] | wire_man_product2_mult_result[17]), (sticky_bit[15] | wire_man_product2_mult_result[16]), (sticky_bit[14] | wire_man_product2_mult_result[15]), (sticky_bit[13] | wire_man_product2_mult_result[14]), (sticky_bit[12] | wire_man_product2_mult_result[13]), (sticky_bit[11] | wire_man_product2_mult_result[12]), (sticky_bit[10] | wire_man_product2_mult_result[11]), (sticky_bit[9] | wire_man_product2_mult_result[10]), (sticky_bit[8] | wire_man_product2_mult_result[9]), (sticky_bit[7] | wire_man_product2_mult_result[8]), (sticky_bit[6] | wire_man_product2_mult_result[7]), (sticky_bit[5] | wire_man_product2_mult_result[6]), (sticky_bit[4] | wire_man_product2_mult_result[5]), (sticky_bit[3] | wire_man_product2_mult_result[4]), (sticky_bit[2] | wire_man_product2_mult_result[3]), (sticky_bit[1] | wire_man_product2_mult_result[2]), (sticky_bit[0] | wire_man_product2_mult_result[1]), wire_man_product2_mult_result[0]},
underflow = underflow_ff;
endmodule |
module mult (
clock,
dataa,
datab,
nan,
overflow,
result,
underflow);
input clock;
input [31:0] dataa;
input [31:0] datab;
output nan;
output overflow;
output [31:0] result;
output underflow;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire sub_wire3;
wire nan = sub_wire0;
wire overflow = sub_wire1;
wire [31:0] result = sub_wire2[31:0];
wire underflow = sub_wire3;
mult_altfp_mult_mrp mult_altfp_mult_mrp_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.nan (sub_wire0),
.overflow (sub_wire1),
.result (sub_wire2),
.underflow (sub_wire3));
endmodule |
module sky130_fd_sc_hdll__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule |
module sky130_fd_sc_hdll__xor3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, A, B, C );
buf buf0 (X , xor0_out_X );
endmodule |
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule |
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