GCC,nvptx,0,out ) ;
GCC,nvptx,1,) ) ;
GCC,nvptx,2,
GCC,nvptx,3,;
GCC,nvptx,4,: ( end < src ? NULL : end ) ;
GCC,nvptx,5,) ;
GCC,nvptx,6,) paths ) ;
GCC,nvptx,7,
GCC,nvptx,8,
GCC,nvptx,9,", <STR_LIT> ) ;"
GCC,nvptx,10,prev ;
GCC,nvptx,11,ptr ;
GCC,nvptx,12,", out );"
GCC,nvptx,13,(stmts);
GCC,nvptx,14,( s );
GCC,nvptx,15,;
GCC,nvptx,16,) ;
GCC,nvptx,17,out ) ;
GCC,nvptx,18,"argv_obstack , <STR_LIT> STR ) ;"
GCC,nvptx,19,;
GCC,nvptx,20,NULL) ;
GCC,nvptx,21,", cannot remove '%s'\ n , file );"
GCC,nvptx,22,*tasklet ) {
GCC,nvptx,23,strlen ( curval ) ;
GCC,nvptx,24,<STR_LIT> : PTXGen ) ;
GCC,nvptx,25,alloc ) ;
GCC,nvptx,26,buffer ;
GCC,nvptx,27,) ;
GCC,nvptx,28,"major , minor ) ;"
GCC,nvptx,29,split ;
GCC,nvptx,30,( cfun -> machine -> axis_predicate [ <NUM_LIT> ] ) ) ;
GCC,nvptx,31,tmp ;
GCC,nvptx,32,"NVPTX_BUILTIN_FPCLASS : return nvptx_expand_fpclass ( exp , target , mode , ignore , false ) ;"
GCC,nvptx,33,
GCC,nvptx,34,<NUM_LIT> ;
GCC,nvptx,35,: TREE_VALUE ( DECL_ARGUMENT_TYPES ( args ) ) ;
GCC,nvptx,36,
GCC,nvptx,37,type ;
GCC,nvptx,38,;
GCC,nvptx,39,TYPE_ALIGNMENT ( TREE_TYPE ( exp ) ) / BITS_PER_UNIT);
GCC,nvptx,40,", <STR_LIT> ) ;"
GCC,nvptx,41,this_part;
GCC,nvptx,42,"arg , args_so_far ) ;"
GCC,nvptx,43,"size , (size) , <STR_LIT> , section ) ;"
GCC,nvptx,44,fun_expr_list);
GCC,nvptx,45,}
GCC,nvptx,46,", this line }"
GCC,nvptx,47,DECL_NAME ( <NUM_LIT> ));
GCC,nvptx,48,const0_rtx );
GCC,nvptx,49,", ptxfile);"
GCC,nvptx,50,) ;
GCC,nvptx,51,;
GCC,nvptx,52,;
GCC,nvptx,53,;
GCC,nvptx,54,* BITS_PER_UNIT ;
GCC,nvptx,55,
GCC,nvptx,56,SImode)));
GCC,nvptx,57,", -1 ) ;"
GCC,nvptx,58,mode );
GCC,nvptx,59,p ;
GCC,nvptx,60,(mode or Invalid);
GCC,nvptx,61,DImode ) ;
GCC,nvptx,62,;
GCC,nvptx,63,__SYMFILE_INLINE;
GCC,nvptx,64,;
GCC,nvptx,65,) == BLKmode ) {
GCC,nvptx,66,", fp ) ) ;"
GCC,nvptx,67,reg );
GCC,nvptx,68,- return 1;
GCC,nvptx,69,": fputs ( <STR_LIT> , file ) ;"
GCC,nvptx,70,) {
GCC,nvptx,71,;
GCC,nvptx,72,;
GCC,nvptx,73,{
GCC,nvptx,74,name ) ;
GCC,nvptx,75,) ) {
GCC,nvptx,76,"value, hash, INSERT);"
GCC,nvptx,77,known_code = ( enum rtx_code ) <NUM_LIT> ;
GCC,nvptx,78,( i ) == <NUM_LIT> ) remove_reg_stat ( i );
GCC,nvptx,79,true ;
GCC,nvptx,80,;
GCC,nvptx,81,;
GCC,nvptx,82,) ;
GCC,nvptx,83,obj = truncate((WORD)(obj));
GCC,nvptx,84,<NUM_LIT> ) ;
GCC,nvptx,85,
GCC,nvptx,87,
GCC,nvptx,88,return false;
GCC,nvptx,89,;
GCC,nvptx,90,
GCC,nvptx,91,;
GCC,nvptx,92,
GCC,nvptx,93,"bbf , ba_flags );"
GCC,nvptx,94,
GCC,nvptx,95,", init_frag . offset ) ;"
GCC,nvptx,96,;
GCC,nvptx,97,;
GCC,nvptx,98,"decl , tree_size ) ;"
GCC,nvptx,99,< maxregs ;
GCC,nvptx,100,op ) ) ;
GCC,nvptx,101,;
GCC,nvptx,102,"NVPTX_BUILTIN_SHUFFLEI : case NVPTX_BUILTIN_SHUFFLELI : return nvptx_expand_shuffle_imm (exp, target, mode, ignore, <CODE>);"
GCC,nvptx,103,"worker_red_sym , worker_red_align , worker_red_size ) ;"
GCC,nvptx,104,
GCC,nvptx,105,) {
GCC,nvptx,106,{
GCC,nvptx,107,
GCC,nvptx,108,"type ) ,  ARG_UNUSED ( func ) );"
GCC,nvptx,109,) ;
GCC,nvptx,110,"src0 , src1 ) ;"
GCC,nvptx,111,;
GCC,nvptx,112,]) {
GCC,nvptx,113,) ;
GCC,nvptx,114,(rtx type_node) noexcept {
GCC,nvptx,115,", type , offset , size , align ) ;"
GCC,nvptx,116,Invalid function code in goacc_reduction );
GCC,nvptx,117,NULL ;
GCC,nvptx,118,init_stmt ) ;
GCC,nvptx,119,) ;
GCC,nvptx,120,true ;
GCC,nvptx,121,){
GCC,nvptx,122,= NULL ;
GCC,nvptx,123,"latch_end , loc ) ;"
GCC,nvptx,124,) {
GCC,nvptx,125,
GCC,nvptx,126,", par -> forked_insn ) ;"
GCC,nvptx,127,par -> next -> inner_mask;
GCC,nvptx,128,) {
GCC,nvptx,129,",  inamous pointers = %d, ix ) ;"
GCC,nvptx,130,<NUM_LIT> ) <:   );
GCC,nvptx,131,<NUM_LIT> ;
GCC,nvptx,132,
GCC,nvptx,133,
GCC,nvptx,134,) ;
GCC,nvptx,135,) ) ;
GCC,nvptx,136,"fprintf(file,  Sym : %s , Flags : %d \n, sym, flags);"
GCC,nvptx,137,) : NULL )
GCC,nvptx,138,split ;
GCC,nvptx,139,
GCC,nvptx,140,'\0';
GCC,nvptx,141,:  {
GCC,nvptx,142,- <NUM_LIT> ;
GCC,nvptx,143,
GCC,nvptx,144,"diagnose_openacc_conflict ( TARGET_AMDGCN, Gay );"
GCC,nvptx,145,<NUM_LIT> ];
GCC,nvptx,146,", mask , & bb_insn_map ) ;"
GCC,nvptx,147,
GCC,nvptx,148,nvptx_cuda_sm ? 32 : 16;
GCC,nvptx,149,)print_simt_regs(file);
GCC,nvptx,150,) ;
GCC,nvptx,151,) ) ) ) ;
GCC,nvptx,152,;
GCC,nvptx,153,0 && NAME ( DECL_NAME ( FUNCTION_DECL ( current_proc ) ) ) == mkdir ) {
GCC,nvptx,154,
GCC,nvptx,155,) ;
GCC,nvptx,156,"vector_loop , par -> fork_insn ) ;"
GCC,nvptx,157,", fs , data ) ;"
GCC,nvptx,158,;
GCC,nvptx,159,"ix, 0, mask);"
GCC,nvptx,160,DECL_ATTRIBUTE_OACC_MASK;
GCC,nvptx,161,
GCC,nvptx,162,empty ;
GCC,nvptx,163,INSN_P (insn)) {
GCC,nvptx,164,;
GCC,nvptx,165,return res;
GCC,nvptx,166,"< s> res = MAX ( res , PTX_VERSION_6_0 ) ;"
GCC,nvptx,167,missing size );
GCC,nvptx,168,
GCC,nvptx,169,){
GCC,nvptx,170,;
GCC,nvptx,171,
GCC,nvptx,172,) ) ;
GCC,nvptx,173,= block-> flags & ~CLEANUP_BLOCK;
GCC,nvptx,174,) ;
GCC,nvptx,175,) ;
GCC,nvptx,176,( GOES HERE ) ;
GCC,nvptx,177,<IDN_LIT> ) ) ;
GCC,nvptx,178,;
GCC,nvptx,179,-> n_in_use ++ ] ;
GCC,nvptx,180,_node* node ){
GCC,nvptx,181,oacc_fn_attrib_contiguous ( attrs );
GCC,nvptx,182,] = max_workers;
GCC,nvptx,183,
GCC,nvptx,184,"] , align ) ;"
GCC,nvptx,185,", <STR_LIT> ) ;"
GCC,nvptx,186,( mode );
GCC,nvptx,187,deCOMPLEX_MODE_P ( mode ) return GET_MODE_INNER ( mode ) ;
GCC,nvptx,188,state [ GOMP_DIM_VECTOR ] -= 1 ;
GCC,nvptx,189,
GCC,nvptx,190,"The last statement of this code snippet is: nvptx_assemble_decl_end ( file , type , <STR_LIT> , obj_size ) ;"
GCC,nvptx,191,<NUM_LIT> ;
GCC,nvptx,192,<NUM_LIT> ) &lt;
GCC,nvptx,193,;
GCC,nvptx,194,tstring . c_str ( ) : init_frag . non_empty_lines . c_str ( ) ) ;
GCC,nvptx,195,<NUM_LIT> ;
GCC,nvptx,196,"decl_size_align ( decl ) , decl , decl_debug_loc ( decl ) ) ;"
GCC,nvptx,197,
GCC,nvptx,198,part * BITS_PER_UNIT ) ;
GCC,nvptx,199,exp __rtx (* arg ) ;
GCC,nvptx,200,
GCC,nvptx,201,
GCC,nvptx,202,) );
GCC,nvptx,203,_VAL ( bar_num ) ) ;
GCC,nvptx,204,decl ) ) ;
GCC,nvptx,205,) );
GCC,nvptx,206,<NUM_LIT> ] ;
GCC,nvptx,207,+ <NUM_LIT> ) ;
GCC,nvptx,208,
GCC,nvptx,209,op ) ) ;
GCC,nvptx,210,mask == GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) {
GCC,nvptx,211,doing_call );
GCC,nvptx,212,": return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ;"
GCC,nvptx,213,true ) ;
GCC,nvptx,214,",  src);"
GCC,nvptx,215,cmp ) ) ;
GCC,nvptx,216,) ;
GCC,nvptx,217,", dim ), &first ) ;"
GCC,nvptx,218,"mode , EXPAND_NORMAL ) ;"
GCC,nvptx,219,op ) ) ;
GCC,nvptx,220,) ;
GCC,nvptx,221,<STR_LIT> ) ;
GCC,nvptx,222,arg . first_p ( ) ) {
GCC,nvptx,223,= cum->count + 1;
GCC,nvptx,224,();
GCC,nvptx,225,;
GCC,nvptx,226,
GCC,nvptx,227,"), GEN_INT ( count ), 0 ) );"
GCC,nvptx,228,;
GCC,nvptx,229,": res = gen_binary ( dst, src0, src1, CODE_FOR_daddu );"
GCC,nvptx,230,res ;
GCC,nvptx,231,", nfsr , 0 , GEN_SHUFFLE_NORMAL , 0 , 0 , 0 );"
GCC,nvptx,232,"2 , reg3 , count );"
GCC,nvptx,233,;
GCC,nvptx,234,) ;
GCC,nvptx,235,decisions;
GCC,nvptx,236,(mode);
GCC,nvptx,237,
GCC,nvptx,238,;
GCC,nvptx,239,;
GCC,nvptx,240,;
GCC,nvptx,241,GOMP_DIM_USER return true;
GCC,nvptx,242,}
GCC,nvptx,243,"& seq , <NUM_LIT> ) ;"
GCC,nvptx,244,);
GCC,nvptx,245,) ;
GCC,nvptx,246,) ;
GCC,nvptx,247,"call , <NUM_LIT> ) ;"
GCC,nvptx,248,false ;
GCC,nvptx,249,name ) ;
GCC,nvptx,250,;
GCC,nvptx,251,", <STR_LIT> ) ;"
GCC,nvptx,252,NULL_TREE ) ) ;
GCC,nvptx,253,", UINT , UINT , NULL_TREE ) ) ;"
GCC,nvptx,254,;
GCC,nvptx,255,: case CONST_INT : return true ;
GCC,nvptx,256,) ;
GCC,nvptx,257,
GCC,nvptx,258,UNKNOWN_TREE;
GCC,nvptx,259,mode ) ;
GCC,nvptx,260,}
GCC,nvptx,261,update_bb ;
GCC,nvptx,262,;
GCC,nvptx,263,) ;
GCC,nvptx,264,"cfun -> machine, cfun -> machine -> axis_dim_p);"
GCC,nvptx,265,{
GCC,nvptx,266,0 ] ;
GCC,nvptx,267,
GCC,nvptx,268,( ) ;
GCC,nvptx,269,DATA_AREA_CONST ;
GCC,nvptx,270,){
GCC,nvptx,271,;
GCC,nvptx,272,<NUM_LIT> ) return <STR_LIT> ;
GCC,nvptx,273,
GCC,nvptx,274,;
GCC,nvptx,275,size ( ) ;
GCC,nvptx,276,
GCC,nvptx,277,= <NUM_LIT> ;
GCC,nvptx,278,{
GCC,nvptx,279,{
GCC,nvptx,280,0 ;
GCC,nvptx,281,) ;
GCC,nvptx,282,;
GCC,nvptx,283,"] , src_regno );"
GCC,nvptx,284,The code snippet should end with: return SUCCESS;
GCC,nvptx,285,
GCC,nvptx,286,accumulative_args );
GCC,nvptx,287,uint32_t *) {
GCC,nvptx,288,"pat, 0, 0 );"
GCC,nvptx,289,VEEE ) ;
GCC,nvptx,290,"STRICT_LOW_PART : case STRICT_HIGH_PART : fputs ( <STR_LIT> , file ) ;"
GCC,nvptx,291,cfun -> machine ) ;
GCC,nvptx,292,funtype ));
GCC,nvptx,293,", idx ), true ) ;"
GCC,nvptx,294,: return <STR_LI
GCC,nvptx,295,) ;
GCC,nvptx,296,name);
GCC,nvptx,297,", REMOVE ) ;"
GCC,nvptx,298,{
GCC,nvptx,299,) ;
GCC,nvptx,300,;
GCC,nvptx,301,"var , op ) ;"
GCC,nvptx,302,) ;
GCC,nvptx,303,{
GCC,nvptx,304,insn ) ;
GCC,nvptx,305,[ i ] == c ) break ;
GCC,nvptx,306,"return pass_in_memory(TYPE_MODE(type), type, true);"
GCC,nvptx,307,
GCC,nvptx,308,( edge ) ;
GCC,nvptx,309,-> <NUM_LIT> + offset ) ;
GCC,nvptx,310,;
GCC,nvptx,311,<NUM_LIT> ;
GCC,nvptx,312,", insn ) ;"
GCC,nvptx,313,", NULL ) ;"
GCC,nvptx,314,<u>n_preds == 1</u> ) ;
GCC,nvptx,315,-> first ;
GCC,nvptx,316,
GCC,nvptx,317,true;
GCC,nvptx,318,true ;
GCC,nvptx,319,true ;
GCC,nvptx,320,;
GCC,nvptx,321,){
GCC,nvptx,322,= (machine_mode mode);
GCC,nvptx,323,== 0 ;
GCC,nvptx,324,0 ;
GCC,nvptx,325,"asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,326,
GCC,nvptx,327,{
GCC,nvptx,328,<u>mode</u>;
GCC,nvptx,329,);
GCC,nvptx,330,: return major_p ? <NUM_LIT> : <NUM_LIT
GCC,nvptx,331,", pseudo . second ) ;"
GCC,nvptx,332,") , TRUE );"
GCC,nvptx,333,<STR_LIT> }
GCC,nvptx,334,( ) - 1 );
GCC,nvptx,335,
GCC,nvptx,336,sm ) {
GCC,nvptx,337,
GCC,nvptx,338,! seen_worker_label ) {
GCC,nvptx,339,! seen_vector_label ) ) ;
GCC,nvptx,340,! seen_worker_label ) ;
GCC,nvptx,341,"reg, pm, count, vector);"
GCC,nvptx,342,) {
GCC,nvptx,343,{
GCC,nvptx,344,true ;
GCC,nvptx,345,;
GCC,nvptx,346,{
GCC,nvptx,347,", dump_flags & TDF_DETAILS ? %d:%d->%d (insn#%d) : )"
GCC,nvptx,348,( ) ;
GCC,nvptx,349,true ;
GCC,nvptx,350,name ) ;
GCC,nvptx,351,
GCC,nvptx,352,"<NUM_LIT> , argno , void_type_node , false ) ;"
GCC,nvptx,353,) {
GCC,nvptx,354,( result ) ) ;
GCC,nvptx,355,}
GCC,nvptx,356,s��fx = ._Z;
GCC,nvptx,357,parallel :: parallel
GCC,riscv,0,;
GCC,riscv,1,
GCC,riscv,2,(num + 1)) << lmul_log2);
GCC,riscv,3,) ;
GCC,riscv,4,"elmul_log2 , fe_p , rm ) ;"
GCC,riscv,5,
GCC,riscv,6,"TARGET_EXPR, RISCV_ATYPE_USI, old_flags, build_call_expr (frflags, hold), build_call_expr (fsflags, hold) );"
GCC,riscv,7,aren_true_node ( integer_type_node ) )}
GCC,riscv,8,"RISCV_BUILTIN_SECONDARY : return <STR_LIT2> riscv_expand_builtin_secondary ( d -> icode , fndecl , fcode ,<Target Function Address>);"
GCC,riscv,9,i ] ;
GCC,riscv,10,;
GCC,riscv,11,;
GCC,riscv,12,"BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , target != const0_rtx ) ;"
GCC,riscv,13,
GCC,riscv,14,;
GCC,riscv,15,prototype <INT_LIT>;
GCC,riscv,16,. out : const0_rtx ;
GCC,riscv,17,
GCC,riscv,18,false;
GCC,riscv,19,) {
GCC,riscv,20,": return riscv_expand_builtin_direct_no_target ( d -> icode , target , exp , true ) ;"
GCC,riscv,21,exp ) ;
GCC,riscv,22,] . reg : const0_rtx ;
GCC,riscv,23,i ;
GCC,riscv,24,"rtx op_value , enum machine_mode mode ) ;"
GCC,riscv,25,) );
GCC,riscv,26,2;
GCC,riscv,27,<PRAGMA_STRTYPE> );
GCC,riscv,28,<STR_LIT> ;
GCC,riscv,29,<SYM_lineriscv_set_target_float_abi> }
GCC,riscv,30,{
GCC,riscv,31,<STRING_LIT> s_fpu #endif) ;
GCC,riscv,32,
GCC,riscv,33,</NUM_LIT> ) ;
GCC,riscv,34,) ;
GCC,riscv,35,void ) {
GCC,riscv,36,( ) ;
GCC,riscv,37,"( <NUM_LIT>, GEN_INT ( 0 ) ) ;"
GCC,riscv,38,) ;
GCC,riscv,39,get_last_insn ( ) ;
GCC,riscv,40,;
GCC,riscv,41,SImode }
GCC,riscv,42,) ) ;
GCC,riscv,43,) ;
GCC,riscv,44,;
GCC,riscv,45,global_options . abi ;
GCC,riscv,46,", 0 ) -> <NUM_LIT> += addr ;"
GCC,riscv,47,regno ) -> insert ({
GCC,riscv,48,", bb ) ;"
GCC,riscv,49,set = REGNO_REG_SET ( get_regno ( IREG ( SYM<BRANCH> ( bb ) ) ) );
GCC,riscv,50,_basic_block ( bb ) ;
GCC,riscv,51,addr ) ;
GCC,riscv,52,) pat = GET_MODE ( < s > ) ;
GCC,riscv,53,) ;
GCC,riscv,54,
GCC,riscv,55,) ;
GCC,riscv,56,NULL ) ;
GCC,riscv,57,
GCC,riscv,58,continue ;
GCC,riscv,59,( target ) ) ) {
GCC,riscv,60,compare ) {
GCC,riscv,61,;
GCC,riscv,62,[Ievent = 14230];
GCC,riscv,63,;
GCC,riscv,64,const noexcept {
GCC,riscv,65,{
GCC,riscv,66,<lete std:: endl;
GCC,riscv,67,false;
GCC,riscv,68,
GCC,riscv,69,:returns a boolean indicating whether the tail policy should be applied or not.
GCC,riscv,70,PRED_TYPE_tt;
GCC,riscv,71,) ;
GCC,riscv,72,) ;
GCC,riscv,73,
GCC,riscv,74,"g , gsi_last ( f . gsi ) ) ;"
GCC,riscv,75,
GCC,riscv,76,pred_idx = 0 ;
GCC,riscv,77,= 0 ;
GCC,riscv,78,"argument_types , group . ops_infos . types [ vec_type_idx ] , sizeof ( float ) ) ;"
GCC,riscv,79,"] , argument_types );"
GCC,riscv,80,( <TYPE_LIT> ) ;
GCC,riscv,81,) ;
GCC,riscv,82,vop ) ;
GCC,riscv,83,op ) ;
GCC,riscv,84,( mode ) ));
GCC,riscv,85,{
GCC,riscv,86,
GCC,riscv,87,
GCC,riscv,88,mode));
GCC,riscv,89,
GCC,riscv,90,0;
GCC,riscv,91,false ;
GCC,riscv,92,<NUM_LIT> op_info -> args[i].base_type = 0;
GCC,riscv,93,) ;
GCC,riscv,94,<NUM_LIT> ) ;
GCC,riscv,95,{
GCC,riscv,96,
GCC,riscv,97,) {
GCC,riscv,98,0;
GCC,riscv,99,flags;
GCC,riscv,100,"const std:: string tmalacie, const std::string gpa )  {"
GCC,riscv,101,args );
GCC,riscv,102,|= RVV_REQUIRE_RV64BIT ;
GCC,riscv,103,true;
GCC,riscv,104,{
GCC,riscv,105,key ;
GCC,riscv,106,exp ) . pointer_rfn ;
GCC,riscv,107,) ;
GCC,riscv,108,gimple_stmt_iterator gsi) override;
GCC,riscv,109,
GCC,riscv,110,( exp_in ) {
GCC,riscv,111,) )->void_parm_ret_info () ;
GCC,riscv,112,"), fntype );"
GCC,riscv,113,Generator failure</STR_LIT> ) ;
GCC,riscv,114,
GCC,riscv,115,std :: string arg_name)  {
GCC,riscv,116,hash) ;
GCC,riscv,117,);
GCC,riscv,118,
GCC,riscv,119,) ;
GCC,riscv,120,
GCC,riscv,121,get_type_info ( ) ) ;
GCC,riscv,122,
GCC,riscv,123,
GCC,riscv,124,. scalar_ptr ;
GCC,riscv,125,Pmode );
GCC,riscv,126,"prog , Pmode ) , Pmode ) ;"
GCC,riscv,127,stmt-> fndecl ];
GCC,riscv,128,stmt ) ;
GCC,riscv,129,function_table.add(builder.build(function_groups[i]));
GCC,riscv,130,
GCC,riscv,131,
GCC,riscv,132,));
GCC,riscv,133,
GCC,riscv,134,typeid ( rvv . default_rvv_type ));
GCC,riscv,135,
GCC,riscv,136,{
GCC,riscv,137,;
GCC,riscv,138,TYPE_NAME ( type ) );
GCC,riscv,139,NULL ;
GCC,riscv,140,_element_type_index ) ;
GCC,riscv,141,______ ) ;
GCC,riscv,142,) {
GCC,riscv,143,vectype ;
GCC,riscv,144,( INT32_TYPE ) ;
GCC,riscv,145,
GCC,riscv,146,= TREE_TYPE ( decl ) ;
GCC,riscv,147,
GCC,riscv,148,
GCC,riscv,149,) && require_nonnegative ( argno );
GCC,riscv,150,true;
GCC,riscv,151,
GCC,riscv,152,
GCC,riscv,153,<NUM_LIT> ;
GCC,riscv,154,;
GCC,riscv,155,(type));
GCC,riscv,156,op2 ) ;
GCC,riscv,157,", true );"
GCC,riscv,158,) ) ;
GCC,riscv,159,
GCC,riscv,160,
GCC,riscv,161,
GCC,riscv,162,merge_args_t *args) {
GCC,riscv,163,) ;
GCC,riscv,164,{
GCC,riscv,165,( have_regs_of_mode ) ) ;
GCC,riscv,166,( m_old_have_regs_of_mode ) ) ;
GCC,riscv,167,( );
GCC,riscv,168,;
GCC,riscv,169,;
GCC,riscv,170,
GCC,riscv,171,) ) ) {
GCC,riscv,172,
GCC,riscv,173,;
GCC,riscv,174,{
GCC,riscv,175,"local_fields1 , info1 );"
GCC,riscv,176,= new_info ;
GCC,riscv,177,", true , true , true ) ;"
GCC,riscv,178,
GCC,riscv,179,{
GCC,riscv,180,vlmul_value ){
GCC,riscv,181,return vlmul;
GCC,riscv,182,if (m_vector_manager -> vector_edge_avl [e->dest()].empty()) {
GCC,riscv,183,"rinsn , watermark ) ;"
GCC,riscv,184,) ;
GCC,riscv,185,= <NUM_LIT> ;
GCC,riscv,186,= const_cast ( RTX_PATTERN ( PATTERN ( rinsn ) ) ) ;
GCC,riscv,187,
GCC,riscv,188,
GCC,riscv,189,new_prob = curr_prob ;
GCC,riscv,190,unreachable ;
GCC,riscv,191,) ) ;
GCC,riscv,192,( cfun ) ) ;
GCC,riscv,193,
GCC,riscv,194,) ;
GCC,riscv,195,
GCC,riscv,196,&#123;
GCC,riscv,197,type ] ;
GCC,riscv,198,vector_insn_info &info2) {
GCC,riscv,199,vector_insn_info & info2 ) ;
GCC,riscv,200,( ) ;
GCC,riscv,201,) ;
GCC,riscv,202,". get_sew ( )  what do we get? <Answer>: when this code is executed by a program, it will return a boolean value of true or false depending on whether the get_sew method of info1 and info2 objects are equal or not."
GCC,riscv,203,( ) ;
GCC,riscv,204,State::Active || m_statusCode == 200  && m_responseTime < 500;
GCC,riscv,205,qut_states;
GCC,riscv,206,
GCC,riscv,207,( rinsn ) ;
GCC,riscv,208,int &);
GCC,riscv,209,
GCC,riscv,210,<NUM_LIT> ;
GCC,riscv,211,"i, vector_exprs[i]) ) return 1;"
GCC,riscv,212,{
GCC,riscv,213,) {
GCC,riscv,214,_num_lit ( rinsn ) <=<NUM_LIT>;
GCC,riscv,215,;
GCC,riscv,216,() ;
GCC,riscv,217,
GCC,riscv,218,
GCC,riscv,219,
GCC,riscv,220,
GCC,riscv,221,
GCC,riscv,222,( ) ) continue ;
GCC,riscv,223,) ;
GCC,riscv,224,) ) ;
GCC,riscv,225,"rtx_insn = <NUM_LIT> ( FOR_EACH_BB_FN ( cfg_bb , cfun ) {"
GCC,riscv,226,nullptr ;
GCC,riscv,227,;
GCC,riscv,228,) ) ;
GCC,riscv,229,f ) {
GCC,riscv,230,", new_info , NULL_RTX ) ;"
GCC,riscv,231,available_list.push_back(i);
GCC,riscv,232,Note: spell the last statement completely.
GCC,riscv,233,) ;
GCC,riscv,234,"> ( set ), true );"
GCC,riscv,235,
GCC,riscv,236,Info;
GCC,riscv,237,
GCC,riscv,238,"get_avl_source (char *func_name, ) {"
GCC,riscv,239,i ;
GCC,riscv,240,<NUM_LIT> ) ;
GCC,riscv,241,& KeepFinalResult ) );
GCC,riscv,242,PREFERENCE_SHIFT ) & <NUM_LIT> );
GCC,riscv,243,;
GCC,riscv,244,
GCC,riscv,245,;
GCC,riscv,246,vec;
GCC,riscv,247,m_ma ;
GCC,riscv,248,;
GCC,riscv,249,ta_grant ;
GCC,riscv,250,", 1 ) , 0 );"
GCC,riscv,251,"OPCODE (rinsn)), recog_data.operand[get_attr_vl_op_idx(rinsn)]) ;"
GCC,riscv,252,) ;
GCC,riscv,253,block_p ( BLOCK_REPEAT ) ) {
GCC,riscv,254,false ;
GCC,riscv,255,
GCC,riscv,256,( );
GCC,riscv,257,;
GCC,riscv,258,;
GCC,riscv,259,size ( ) ? true : <u style=color:red>false< u>;
GCC,riscv,260,() ;
GCC,riscv,261,false ;
GCC,riscv,262,insn ) {
GCC,riscv,263,", avl ) ;"
GCC,riscv,264,_p ( rtx_to_mem ( insn ) );
GCC,riscv,265,get_attr_type ( rinsn ) == TYPE_VFMUL ;
GCC,riscv,266,{
GCC,riscv,267,&        info2 ){
GCC,riscv,268,
GCC,riscv,269,"dump_file , Dynamic VsetVLs written to file);"
GCC,riscv,270,true ;
GCC,riscv,271,;
GCC,riscv,272,.getVLMax());
GCC,riscv,273,(ma ) ;
GCC,riscv,274,return false ;
GCC,riscv,275,.m_source;
GCC,riscv,276,) {
GCC,riscv,277,. get_source ( ) -> insn ( ) ) ;
GCC,riscv,278,The final statement of this code snippet is return;
GCC,riscv,279,{
GCC,riscv,280,) ;
GCC,riscv,281,has_avl_reg ( ) ;
GCC,riscv,282,) ) ;
GCC,riscv,283,
GCC,riscv,284,
GCC,riscv,285,=false;
GCC,riscv,286,
GCC,riscv,287,}
GCC,riscv,288,{
GCC,riscv,289,
GCC,riscv,290,
GCC,riscv,291,get_avl_source ( ) ;
GCC,riscv,292,
GCC,riscv,293,. get_ta ( ) ;
GCC,riscv,294,
GCC,riscv,295,<label> <strong> -1 </strong>;
GCC,riscv,296,& info2 ) {
GCC,riscv,297,( ) ;
GCC,riscv,298,) ;
GCC,riscv,299,
GCC,riscv,300,power_info . get_max_vl_mul ( ) ) ;
GCC,riscv,301,
GCC,riscv,302,
GCC,riscv,303,;
GCC,riscv,304,) ;
GCC,riscv,305,( );
GCC,riscv,306,;
GCC,riscv,307,__dirty = true );
GCC,riscv,308,{
GCC,riscv,309,_file(Filestore&amp;
GCC,riscv,310,;
GCC,riscv,311,ma ;
GCC,riscv,312,
GCC,riscv,313,
GCC,riscv,314,ta;
GCC,riscv,315,value) {
GCC,riscv,316,;
GCC,riscv,317,m_state = AT_READONLY;
GCC,riscv,318,) ;
GCC,riscv,319,
GCC,riscv,320,
GCC,riscv,321,
GCC,riscv,322,next_info (  ) ;
GCC,riscv,323,States::Off;
GCC,riscv,324,
GCC,riscv,325,;
GCC,riscv,326,
GCC,riscv,327,recog_data.operand ) == <NUM_LIT> ;
GCC,riscv,328,rinsn-><NUM_LIT> != LIM_COND_GEN ;
GCC,riscv,329,
GCC,riscv,330,== CODE_FOR_vlmax_avlsid );
GCC,riscv,331,"SET_SRC (x), val);"
GCC,riscv,332,
GCC,riscv,333,|| INSN_CODE ( rinsn ) == CODE_FOR_vsetshifti );
GCC,riscv,334,"), Pmode, 1);"
GCC,riscv,335,) ;
GCC,riscv,336,GEN_MAXOF );
GCC,riscv,337,"* p_cands , old_reg );"
GCC,riscv,338,
GCC,riscv,339,\end{
GCC,riscv,340,) ;
GCC,riscv,341,
GCC,riscv,342,LMUL_4 : ratio = sew / <NUM_LIT> ;
GCC,riscv,343,min_size ) ;
GCC,riscv,344,- maxlen );
GCC,riscv,345,CONST_INT_VALUE ( elt ) == 5 );
GCC,riscv,346,", 0 ) ) ;"
GCC,riscv,347,GET_MODE ( len ) ) ;
GCC,riscv,348,( GET_MODE_SIZE mode )));
GCC,riscv,349,m_ops ) ;
GCC,riscv,350,"vl, li );"
GCC,riscv,351,;
GCC,riscv,352,", const1_rtx , false ) ;"
GCC,riscv,353,rtx . get  <???>) ;
GCC,riscv,354,);
GCC,riscv,355,== 0 ) return 0;
GCC,riscv,356,0;
GCC,riscv,357,WHERE;
GCC,riscv,358,GET_MODE_BITSIZE ( mode ) : (GET_MODE_BITSIZE ( GET_MODE_BITSIZE(mode) : 16);
GCC,riscv,359,sew ;
GCC,riscv,360,ta ) ;
GCC,riscv,361,unexpected LMUL value );
GCC,riscv,362,;
GCC,riscv,363,) ;
GCC,riscv,364,: return ! simm5_p ( x ) ;
GCC,riscv,365,"( mode ,V16QI , src )rmpstr, tmp ) ;"
GCC,riscv,366,;
GCC,riscv,367,"- ( 1~/~simm4_1 ), ( 1~/~simm4_1 ) );"
GCC,riscv,368,ops [ <NUM_LIT> ] ) ) ) ) {
GCC,riscv,369,[ <NUM_LIT> ] ;
GCC,riscv,370,<NUM_LIT> ;
GCC,riscv,371,
GCC,riscv,372,) / VECTOR_MAX_SIZE );
GCC,riscv,373,;
GCC,riscv,374,single_insns ) ;
GCC,riscv,375,
GCC,riscv,376,label ) ) ;
GCC,riscv,377,] ;
GCC,riscv,378,;
GCC,riscv,379,blocked_thread );
GCC,riscv,380,-> reg ) ;
GCC,riscv,381,;
GCC,riscv,382,"return riscv_hard_regno_nregs ( V_REG_FIRST , mode ) ;"
GCC,riscv,383,components ;
GCC,riscv,384,) {
GCC,riscv,385,TARGET_FPU && TARGET_FP64 ) {
GCC,riscv,386,TARGET_MIN_VLEN;
GCC,riscv,387,) ) {
GCC,riscv,388,", functionCode) {"
GCC,riscv,389,;
GCC,riscv,390,", & #T + recognition_clobbers );"
GCC,riscv,391,;
GCC,riscv,392,dwarf ;
GCC,riscv,393,* cfun -> machine -> d -> fsize ;
GCC,riscv,394,op2 ) ;
GCC,riscv,395,size ;
GCC,riscv,396,"<NUM_LIT>, stack_pointer_rtx) ;"
GCC,riscv,397,) ;
GCC,riscv,398,;
GCC,riscv,399,;
GCC,riscv,400,( elt_size ) ;
GCC,riscv,401,) {
GCC,riscv,402,"( regs_ever_live , regno ) && BITSET_P ( regs_ever_live , regno ) ) {"
GCC,riscv,403,The last statement of this code snippet is offset -= GET_MODE_SIZE(mode).to_constant();
GCC,riscv,404,
GCC,riscv,405,true;
GCC,riscv,406,_offset ;
GCC,riscv,407,", NULL ) ;"
GCC,riscv,408,;
GCC,riscv,409,"( constant , mode ) ) ;"
GCC,riscv,410,{
GCC,riscv,411,
GCC,riscv,412,!= NULL ) {
GCC,riscv,413,TYPE_NAME ( type )) ;
GCC,riscv,414,x ) ;
GCC,riscv,415,
GCC,riscv,416,;
GCC,riscv,417,) ;
GCC,riscv,418,) :
GCC,riscv,419,200 && response.end);
GCC,riscv,420,++ ) ;
GCC,riscv,421,true;
GCC,riscv,422,true;
GCC,riscv,423,Indiana Bites }
GCC,riscv,424,1B ytesPerRISCVVector ;
GCC,riscv,425,) ;
GCC,riscv,426,) ;
GCC,riscv,427,;
GCC,riscv,428,;
GCC,riscv,429,cfun -> machine -> reg_is_wrapped_separately [ regno ] = true ;
GCC,riscv,430,regno ) riscv_set_handled_components ( sbitmap components ) {
GCC,riscv,431,
GCC,riscv,432,") , value );"
GCC,riscv,433,;
GCC,riscv,434,) ;
GCC,riscv,435,size ) ;
GCC,riscv,436,{
GCC,riscv,437,( ) ;
GCC,riscv,438,GET_MODE_BITSIZE ( MODE_VECTOR_INT ));
GCC,riscv,439,;
GCC,riscv,440,();
GCC,riscv,441,type );
GCC,riscv,442,-> analysis ) ;
GCC,riscv,443,;
GCC,riscv,444,* scale ;
GCC,riscv,445,mode ;
GCC,riscv,446,{
GCC,riscv,447,TRUE (The statement should read: RTX_FRAME_RELATED_P ( insn ) = TRUE ;
GCC,riscv,448,return true;
GCC,riscv,449,;
GCC,riscv,450,) ;
GCC,riscv,451,) ;
GCC,riscv,452,", regno <NUM_LIT> ) {"
GCC,riscv,453,) * 2 ;
GCC,riscv,454,10 );
GCC,riscv,455,GET_MODE_SIZE ( addr . mode ) / UNITS_PER_WORD;
GCC,riscv,456,1 ) ;
GCC,riscv,457,
GCC,riscv,458,"stack_pointer_rtx , offset ) ) ;"
GCC,riscv,459,
GCC,riscv,460,the stack size:
GCC,riscv,461,true ;
GCC,riscv,462,true ;
GCC,riscv,463,
GCC,riscv,464,", mode ) ) ;"
GCC,riscv,465,"( x , 1 ) ;"
GCC,riscv,466,;
GCC,riscv,467,[regno];
GCC,riscv,468,size ;
GCC,riscv,469,call used_regs [ regno ] }
GCC,riscv,470,);
GCC,riscv,471,
GCC,riscv,472,;
GCC,riscv,473,) {
GCC,riscv,474,
GCC,riscv,475,)) ;
GCC,riscv,476,;
GCC,riscv,477,= type ;
GCC,riscv,478,x ;
GCC,riscv,479,y ) ;
GCC,riscv,480,y );
GCC,riscv,481,mode ) ;
GCC,riscv,482,alignment ) ) ;
GCC,riscv,483,
GCC,riscv,484,", true );"
GCC,riscv,485,"<NUM_LIT> , GET_MODE_INNER ( mode ) , <NUM_LIT> ) ;"
GCC,riscv,486,": return gen_rtx_REG ( mode , fregno ) ;"
GCC,riscv,487,mode ) != MODE_FIXED) return false;
GCC,riscv,488,<NUM_LIT> ) / UNITS_PER_WORD ;
GCC,riscv,489,;
GCC,riscv,490,", strict_p );"
GCC,riscv,491,);
GCC,riscv,492,
GCC,riscv,493,:
GCC,riscv,494,x ;
GCC,riscv,495,;
GCC,riscv,496,) ;
GCC,riscv,497,;
GCC,riscv,498,) );
GCC,riscv,499,) ;
GCC,riscv,500,( <NUM_LIT> + <NUM_LIT> ) ) ;
GCC,riscv,501,!= <NUM_LIT> ) {
GCC,riscv,502,<NUM_LIT> ) ;
GCC,riscv,503,] . type ) ;
GCC,riscv,504,) return FALSE ;
GCC,riscv,505,{
GCC,riscv,506,) ;
GCC,riscv,507,GEN_INT ( offset2 ) ) ) ) }
GCC,riscv,508,);
GCC,riscv,509,) ) ;
GCC,riscv,510,op ) );
GCC,riscv,511,
GCC,riscv,512,<NUM_LIT> ;
GCC,riscv,513,true ;
GCC,riscv,514,BLKPTR_REGNUM) {
GCC,riscv,515,"0 , <NUM_LIT> ) ;"
GCC,riscv,516,
GCC,riscv,517,) return true ;
GCC,riscv,518,}
GCC,riscv,519,reg_parm_stack_alias_set_p ( cfun -> decl ) ) ;
GCC,riscv,520,
GCC,riscv,521,
GCC,riscv,522,}
GCC,riscv,523,{
GCC,riscv,524,
GCC,riscv,525,(x);
GCC,riscv,526,x )));
GCC,riscv,527,) ) return false ;
GCC,riscv,528,true ;
GCC,riscv,529,op ))) {
GCC,riscv,530,
GCC,riscv,531,+ <NUM_LIT>;
GCC,riscv,532,) ;
GCC,riscv,533,
GCC,riscv,534,", <NUM_LIT> ) ;"
GCC,riscv,535,UNITS_PER_WORD ;
GCC,riscv,536,GEN_INT ( riscv_save_libcall_count ( mask ) ) ) ) ;
GCC,riscv,537,
GCC,riscv,538,"asm_out_file , ), ( flag_pic? <STR_LIT> : <STR_LIT> ) ) ;"
GCC,riscv,539,") , ( flag_pic ? <INT_LIT> : <INT_LIT> ) )"
GCC,riscv,540,
GCC,riscv,541,;
GCC,riscv,542,num_fprs ;
GCC,riscv,543,true ;
GCC,riscv,544,-> gpr_offset ) ;
GCC,riscv,545,false ;
GCC,riscv,546,) ) return addr ;
GCC,riscv,547,) ) ;
GCC,riscv,548,"XEXP ( src , <NUM_LIT> ) = riscv_force_address ( XEXP ( src , <NUM_LIT> ) , mode ) ;"
GCC,riscv,549,x ) ;
GCC,riscv,550,"<NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,551,<STR_LIT> : <STR_LIT> ;
GCC,riscv,552,return <STR_LIT> ;
GCC,riscv,553,&x ) ) ;
GCC,riscv,554,( decl );
GCC,riscv,555,);
GCC,riscv,556,", riscv_const_imm ( hval ) ) ;"
GCC,riscv,557,", <NUM_DEST> );"
GCC,riscv,558,( <NUM_LIT>) ) ) ;
GCC,riscv,559,
GCC,riscv,560,;
GCC,riscv,561,return cfun -> machine -> epilogue_uses [regno];
GCC,riscv,562,{
GCC,riscv,563,unexpected <NUM_LIT> ) ;
GCC,riscv,564,"mode , false ) + <strong>0</strong>;"
GCC,riscv,565,
GCC,riscv,566,
GCC,riscv,567,", EMPTY_RTX ) ;"
GCC,riscv,568,", XEXP ( mem, <NUM_LIT> ) , loop_reg ) ;"
GCC,riscv,569,", reg , 0 ) ;"
GCC,riscv,570,) ;
GCC,riscv,571,<<41 ) : HOST_WIDE_INT_1;
GCC,riscv,572,) ;
GCC,riscv,573,
GCC,riscv,574,"src , offset , <NUM_LIT> <NUM_LIT> [ i <NUM_LIT>  <NUM_LIT> ;"
GCC,riscv,575,) ) ;
GCC,riscv,576,. value = low_part ;
GCC,riscv,577,) ;
GCC,riscv,578,;
GCC,riscv,579,*old_insn ) {
GCC,riscv,580,", <NUM_LIT1> ) ) {"
GCC,riscv,581,;
GCC,riscv,582,", rclass )}"
GCC,riscv,583,);
GCC,riscv,584,
GCC,riscv,585,machine -> frame . larger_return_addr );
GCC,riscv,586,{
GCC,riscv,587,;
GCC,riscv,588,return 32 * ( GET_MODE_SIZE ( mode ) / 4 ) * 16;
GCC,riscv,589,FP_REG_FIRST + <NUM_LIT> ) ) );
GCC,riscv,590,outgoing_args_size ;
GCC,riscv,591,fixed_regs [ regno ] = call_used_regs [ regno ] = TARGET_HARD_FLOAT_REGNO_P ( regno ) ? <NUM_LIT> : <NUM_LIT> ;
GCC,riscv,592,) {
GCC,riscv,593,
GCC,riscv,594,) ;
GCC,riscv,595,);
GCC,riscv,596,) );
GCC,riscv,597,", rtx y ) {"
GCC,riscv,598,) ;
GCC,riscv,599,
GCC,riscv,600,{
GCC,riscv,601,) ) ;
GCC,riscv,602,regno ) ) ) return <b>true<a> ;
GCC,riscv,603,) ) ;
GCC,riscv,604,) ;
GCC,riscv,605,( - step2 ) ) ) ;
GCC,riscv,606,", op1 ) ;"
GCC,riscv,607,) ;
GCC,riscv,608,
GCC,riscv,609,step1 ;
GCC,riscv,610,COSTS_N_INSNS (42) ;
GCC,riscv,611,);
GCC,riscv,612,
GCC,riscv,613,2] );
GCC,riscv,614,= offset ;
GCC,riscv,615,) ;
GCC,riscv,616,false;
GCC,riscv,617,"-> frame . mask , regno - FP_REG_FIRST ) ) {"
GCC,riscv,618,;
GCC,riscv,619,value );
GCC,riscv,620,fpr_count;
GCC,riscv,621,
GCC,riscv,622,) ;
GCC,riscv,623,;
GCC,riscv,624,__num_lit__);
GCC,riscv,625,"<NUM_LIT> >> , fields [ <NUM_LIT> ] . offset ) ;"
GCC,riscv,626,) ;
GCC,riscv,627,UNKNOWN_MODE ;
GCC,riscv,628,) ;
GCC,riscv,629,);
GCC,riscv,630,;
GCC,riscv,631,) ;
GCC,riscv,632,"|| XINT ( elt , <NUM_LIT> ) != <NUM_LIT> ) return <NUM_LIT> ;"
GCC,riscv,633,
GCC,riscv,634,) / UNITS_PER_WORD ;
GCC,riscv,635,;
GCC,riscv,636,{
GCC,riscv,637,<NUM_LIT> * 1 + <NUM_LIT> ) ;
GCC,riscv,638,( ) ;
GCC,riscv,639,
GCC,riscv,640,true );
GCC,riscv,641,( type ) ) != NULL_TREE;
GCC,riscv,642,) );
GCC,riscv,643,->core.can_issue[0];
GCC,riscv,644,
GCC,riscv,645,address_info ;
GCC,riscv,646,) ;
GCC,riscv,647,
GCC,riscv,648,", Pmode ) ;"
GCC,riscv,649,) ;
GCC,riscv,650,"dest = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tp, tmp)) ;"
GCC,riscv,651,) ;
GCC,riscv,652,MEMMODEL_RELAXED : default: return false ;
GCC,riscv,653,
GCC,riscv,654,= 32;
GCC,riscv,655,mode2 ) == MODE_UNCLASSIFIED ) );
GCC,riscv,656,x ) ;
GCC,riscv,657,) );
GCC,riscv,658,< old_cost ;
GCC,riscv,659,"( insn) , outer insns ) ;"
GCC,riscv,660,", str , GP_REG_FIRST + <NUM_LIT> , GP_REG_LAST ) ;"
GCC,riscv,661,]) ;
GCC,riscv,662,std : strlen ( s ) ;
GCC,riscv,663,) ;
GCC,riscv,664,();
GCC,riscv,665,return <STR_LIT> ;
GCC,riscv,666,NULL;
GCC,riscv,667,null;
GCC,riscv,668,
GCC,riscv,669,: <NUM_LIT>;
GCC,riscv,670,"PI , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) );"
GCC,riscv,671,0;
GCC,riscv,672,) ;
GCC,riscv,673,") output_operand_lossage ( <STR_LIT> , letter ) ;"
GCC,riscv,674,) ;
GCC,riscv,675,;
GCC,riscv,676,{
GCC,riscv,677,return ( ... );
GCC,riscv,678,== FRAME_POINTER_REGNUM ) {
GCC,riscv,679,;
GCC,riscv,680,", dwarf ) ;"
GCC,riscv,681,);
GCC,riscv,682,) return gen_rtx_SYMBOL_REF (&<SPEC_LIT> <NUM_LIT> );
GCC,riscv,683,arg ) ;
GCC,riscv,684,"= n - 1 ) BITCLEAR ( mask , n );"
GCC,riscv,685,
GCC,riscv,686,) ;
GCC,riscv,687,rclass ) {
GCC,riscv,688,) ;
GCC,riscv,689,( insn ) );
GCC,riscv,690,"MIN_SIZE , MAX_SIZE ) ;"
GCC,riscv,691,
GCC,riscv,692,;
GCC,riscv,693,high ;
GCC,riscv,694,"( dest ,src ) ) {"
GCC,riscv,695,"<NUM_LIT>, MODE_INT, lo);"
GCC,riscv,696,codes [ CODES_LIT ] ;
GCC,riscv,697,;
GCC,riscv,698,) ;
GCC,riscv,699,GEN_INT ( seqno ) ) ) ;
GCC,riscv,700,symbol_type == SYMBOL_GOTPCREL;
GCC,riscv,701,;
GCC,riscv,702,8;
GCC,riscv,703,);
GCC,riscv,704,", 0 ) ;"
GCC,riscv,705,"tp , sym ) ;"
GCC,riscv,706,", tp , sym ) ;"
GCC,riscv,707,) == TLS_MODEL_INITIAL_EXEC ;
GCC,riscv,708,
GCC,riscv,709,) ) ;
GCC,riscv,710,.srodata ;
GCC,riscv,711,string ) ;
GCC,riscv,712,& offset ) ;
GCC,riscv,713,", 0 ) ;"
GCC,riscv,714,", offset, symbol_type ), UNSPEC_RISCV_ADDRESS_OFFSET );"
GCC,riscv,715,enum riscv_symbol_type symbol ;
GCC,riscv,716,"( x ) , GET_MODE ( x ) ));"
GCC,riscv,717,) ) : GET_MODE_ALIGNMENT ( BLKmode ) ) ;
GCC,riscv,718,mode ) ;
GCC,riscv,719,;
GCC,riscv,720,
GCC,riscv,721,return !riscv_naked_function_p (decl);
GCC,riscv,722,"NULL , 0 ) ;"
GCC,riscv,723,<STR_LIT> ) ;
GCC,riscv,724,<STR_LIT> ) ;
GCC,riscv,725,"addr , <NUM_LIT> );"
GCC,riscv,726,;
GCC,riscv,727,false;
GCC,riscv,728,;
GCC,riscv,729,= <NUM_LIT> ;
GCC,riscv,730,imm2 );
GCC,riscv,731,reg2 ) ;
GCC,riscv,732,", <NUM_LIT> ) ;"
GCC,riscv,733,) ) ;
GCC,riscv,734,));
GCC,arc,0,<STR_LIT> );
GCC,arc,1,( <STR_LIT> ) ;
GCC,arc,2,builtin_assert (arc_tp_regno >= 0) ;
GCC,arc,3,c_r = builtin_assert (arc_tp_regno == arc_ar) ;
GCC,arc,4,<STR_LIT> ;
GCC,arc,5,
GCC,arc,6,) ;
GCC,arc,7,) ;
GCC,arc,8,Explanation: The last statement will return the result of multiplying NUM_LIT by 2. This is indicated by the multiplication operator * and the usage of the NUM_LIT variable twice in the statement.
GCC,arc,9,: case TYPE_BRCC_NO_DELAY_SLOT : case TYPE_BRCC_COND : return <NUM_LIT> ;
GCC,arc,10,false ;
GCC,arc,11,) ;
GCC,arc,12,( REG_P ( operands [ <NUM_LIT> ] ) ? <NUM_LIT> : CONST_INT_P ( operands [ <NUM_LIT> ] )  ? - INTVAL ( operands [ <NUM_LIT> ] ) : <NUM_LIT> ): ? -INTVAL (operands[<NUM_LIT>]) : <NUM_LIT >)
GCC,arc,13,{
GCC,arc,14,"] , xop [ <NUM_LIT> ] ) ) ;"
GCC,arc,15,", <NUM_LIT> , <NUM_LIT> , mode ) ;"
GCC,arc,16,) {
GCC,arc,17,"emit_insn_before(gen_nopv(), succ0);"
GCC,arc,18,;
GCC,arc,19,) {
GCC,arc,20,true;
GCC,arc,21,*branch );
GCC,arc,22,gmask ;
GCC,arc,23,TREE_VALUE ( args ) ) ;
GCC,arc,24,<NUM_LIT> ;
GCC,arc,25,
GCC,arc,26,Error: Could not find specified directory or file.
GCC,arc,27,: next_must_be_target_label_p = TRUE ;
GCC,arc,28,<NUM_LIT> ;
GCC,arc,29,= <NUM_LIT> << ( int ) <NUM_LIT> ;
GCC,arc,30,;
GCC,arc,31,", restored , <NUM_LIT> );"
GCC,arc,32,"offset, 8 ) ;"
GCC,arc,33,"fprintf ( file , <STR_LIT> ) ;"
GCC,arc,34,);
GCC,arc,35,type ) ;
GCC,arc,36,LSHIFTRT :  {
GCC,arc,37,;
GCC,arc,38,;
GCC,arc,39,GET_MODE_SIZE ( mode ) ;
GCC,arc,40,", nextarg ) }"
GCC,arc,41,CONST_DOUBLE );
GCC,arc,42,0 ;
GCC,arc,43,GET_MODE_BITSIZE ( mode )-1 ) ) );
GCC,arc,44,CONST_DECL && ( TREE_CODE( op ) == <NUM_LIT> ) ) );
GCC,arc,45,) <= UINT32_MAX ) ;
GCC,arc,46,cc_reg ;
GCC,arc,47,return <NUM_LIT> ;
GCC,arc,48,"op , <NUM_LIT>), Pmode ) ) {"
GCC,arc,49,PRE_DEC: return -1;
GCC,arc,50,}
GCC,arc,51,: if ( use <NUM_LIT> )
GCC,arc,52,op ) ) {
GCC,arc,53,;
GCC,arc,54,COND_SET_NZ :
GCC,arc,55,op)) ;
GCC,arc,56,"XEXP ( op , <NUM_LIT> ) ) == REG) ) {"
GCC,arc,57,== MEM ) ;
GCC,arc,58,op ) == CONST_INT ) ;
GCC,arc,59,":  N_INSNS ( XEXP ( plus0 , <NUM_LIT> ) ) ;"
GCC,arc,60,", <NUM_LIT> );"
GCC,arc,61,insn ) ;
GCC,arc,62,1 ) / UNITS_PER_WORD ;
GCC,arc,63,) ;
GCC,arc,64,"name , 4 ) ;"
GCC,arc,65,insn;
GCC,arc,66,") ) == CLOBBER || GET_CODE ( PATTERN ( insn ) ) == BARRIER ) : false)  : The code checks whether the instruction is a non-jump instruction and if the pattern of the instruction is either a use or clobber code, or if the instruction is a jump instruction and the pattern is either clobber or barrier code, otherwise the statement returns false."
GCC,arc,67,ED ) {
GCC,arc,68,to ATTRIBUTE_UNUSED ) {
GCC,arc,69,wi :: gu_lt_p
GCC,arc,70,;
GCC,arc,71,3;
GCC,arc,72,;
GCC,arc,73,fn_type ;
GCC,arc,74,) == nullptr ) return true ;
GCC,arc,75,error;
GCC,arc,76,) ;
GCC,arc,77,", XEXP ( u , <NUM_LIT> ) , <STR_LIT> ( GET_MODE ( x ) , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ;"
GCC,arc,78,
GCC,arc,79,flags ;
GCC,arc,80,
GCC,arc,81,addr ) ) ;
GCC,arc,82,true ;
GCC,arc,83,) {
GCC,arc,84,
GCC,arc,85,", gen_rtx_PLUS (<NUM_LIT>, pat) );"
GCC,arc,86,
GCC,arc,87,var-obstack != NULL ;
GCC,arc,88,"int num_byte_registers, int return_value_type) {"
GCC,arc,89,;
GCC,arc,90,", words ) ;"
GCC,arc,91,with:
GCC,arc,92,
GCC,arc,93,
GCC,arc,94,( ) ;
GCC,arc,95,;
GCC,arc,96,machine -> frame_info . saved_regs_size ) ) ;
GCC,arc,97,ARC_BUILTIN_INTERRUPT_HANDLER);
GCC,arc,98,;
GCC,arc,99,;
GCC,arc,100,<NUM_LIT> << ( int ) TF_MODE ;
GCC,arc,101,: if ( GET_MODE_SIZE ( m ) <= <NUM_LIT> ) arc_mode_class [ i ] = <NUM_LIT> << ( int ) E_MODE ;
GCC,arc,102,return false ;
GCC,arc,103,<NUM_LIT> ;
GCC,arc,104,;
GCC,arc,105,;
GCC,arc,106,"<NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( XVECEXP ( addr , <NUM_LIT>, <NUM_LIT>)));"
GCC,arc,107,
GCC,arc,108,"Pmode , XEXP ( x , <NUM_LIT> ) , inner ) ;"
GCC,arc,109,) {
GCC,arc,110,;
GCC,arc,111,;
GCC,arc,112,"[ <NUM_LIT> ] , operands [ <NUM_LIT> ] , neg_intval );"
GCC,arc,113,fname ) ;
GCC,arc,114,"f1 ) , <NUM_LIT> ) ;"
GCC,arc,115,asm_out_file ) {
GCC,arc,116,
GCC,arc,117,) {
GCC,arc,118,return cl;
GCC,arc,119,
GCC,arc,120,();
GCC,arc,121,) return <NUM_LIT> ;
GCC,arc,122,afi -> args_size : 0 );
GCC,arc,123,( ) ;
GCC,arc,124,1 ) ;
GCC,arc,125,;
GCC,arc,126,offset ) ) ;
GCC,arc,127,) ) ;
GCC,arc,128,
GCC,arc,129,case UNORDERED : return <NUM_LIT> ;
GCC,arc,130,
GCC,arc,131,{
GCC,arc,132,;
GCC,arc,133,", - 8 );"
GCC,arc,134,
GCC,arc,135,) {
GCC,arc,136,"pat , 0 , 0 ) ) : SUBREG ( GET_CODE ( pat ) == ASM_OPERANDS? SET_SRC ( XVECEXP ( pat , 1 , 0 ) ) : JUMP_LABEL ( branch ) );"
GCC,arc,137,", <NUM_LIT> )? <NUM_LIT> : asavetree - The dest variable becomes equal to the X expression of the destination after the if-then-else statement is executed."
GCC,arc,138,"REG : return ! call <0> ( uhoh, what do I return here? {"
GCC,arc,139,true ;
GCC,arc,140,
GCC,arc,141,mode ) ;
GCC,arc,142,"&& rtx_equal_p ( pat , gen_rtx_fmt_ee ( GET_CODE ( pat ) , GET_MODE ( pat ) , pat0 , <NUM_LIT> ) ) ) ;"
GCC,arc,143,[ <NUM_LIT> ] ) ;
GCC,arc,144,"<NUM_LIT] , Potential_New_Symbol ) ;"
GCC,arc,145,{
GCC,arc,146,"SImode , value ) ) ) ;"
GCC,arc,147,*iter;
GCC,arc,148,
GCC,arc,149,src )) ;
GCC,arc,150,tmp ;
GCC,arc,151,
GCC,arc,152,);
GCC,arc,153,", stack_pointer_rtx);"
GCC,arc,154,mode ) ;
GCC,arc,155,] ) ;
GCC,arc,156,<NUM_LIT> ) : <NUM_LIT> ) ) ;
GCC,arc,157,"XEXP ( XVECEXP ( dest , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ) ;"
GCC,arc,158,
GCC,arc,159,);
GCC,arc,160,[i]);
GCC,arc,161,stack_pointer_rtx ) ;
GCC,arc,162,"( Pmode , stack_pointer_rtx ) ) ;"
GCC,arc,163,
GCC,arc,164,) ;
GCC,arc,165,{
GCC,arc,166,) ;
GCC,arc,167,= <NUM_LIT> ;
GCC,arc,168,<NUM_LIT>;
GCC,arc,169,base ) );
GCC,arc,170,
GCC,arc,171,"DFmode , <NUM_LIT> ) ;"
GCC,arc,172,5 ) ;
GCC,arc,173,100;
GCC,arc,174,;
GCC,arc,175,) ;
GCC,arc,176,", mode , operands [ <NUM_LIT> ] ) ;"
GCC,arc,177,) {
GCC,arc,178,{
GCC,arc,179,<NUM_LIT>;
GCC,arc,180,TRUE ;
GCC,arc,181,"<NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( u , <NUM_LIT> ) == ARC_UNSPEC_GOTOFF ) return XVECEXP ( u , <NUM_LIT> , <NUM_LIT> ) ;"
GCC,arc,182,"( u , <NUM_LIT> ) , arc_delegitimize_address_1 ( x , u ) ) ;"
GCC,arc,183,NULL;
GCC,arc,184,",set );"
GCC,arc,185,;
GCC,arc,186,) ;
GCC,arc,187,) DF_MODE ) ;
GCC,arc,188,
GCC,arc,189,) {
GCC,arc,190,", <NUM_LIT> ) ;"
GCC,arc,191,NTPOFF : case ARC_UNSPEC_GOTNTPOFF : case ARC_UNSPEC_LOCALPLTONLY : }
GCC,arc,192,( GET_CODE ( addr ) == CONST_INT ? INTVAL ( addr ) : addr );
GCC,arc,193,<NUM_LIT> ) != UNSPEC_TLS_IE && <NUM_LIT> ) {
GCC,arc,194,== orig_x ) return < TAS_ERR > ;
GCC,arc,195,", v ) ;"
GCC,arc,196,( label ) ) ;
GCC,arc,197,: actually this code snippet is missing the last statement }
GCC,arc,198,;
GCC,arc,199,intval ;
GCC,arc,200,{
GCC,arc,201,
GCC,arc,202,<NUM_LIT> : <NUM_LIT> ) ;
GCC,arc,203,32;
GCC,arc,204,"x , <NUM_LIT> ) , <NUM_LIT> ) , mode , PLUS , <NUM_LIT> , speed ) ) ;"
GCC,arc,205,1000;
GCC,arc,206,probability ) ;
GCC,arc,207,) ;
GCC,arc,208,"operands[1] = arc_legitimize_pic_address(operands[1] , temp, GET_MODE(operands[2]));"
GCC,arc,209,)  ;
GCC,arc,210,gmask ;
GCC,arc,211,
GCC,arc,212,{
GCC,arc,213,"plus_constant ( Pmode , stack_pointer_rtx , ra_offs ) ;"
GCC,arc,214,", size , <NUM_LIT> ) ;"
GCC,arc,215,"dst_addr , piece ) ;"
GCC,arc,216,<NUM_LIT> ) :
GCC,arc,217,"ASM_OUT_FILE, ATTRIBUTE_PCS, (TARGET_RF16 ? 2 : 4), (flag_pic ? 0 : 4), (arc_tp_regno != -1 ? -4 : 4), (TARGET_NO_SDATA_SET ? 0 : 4), PRI"
GCC,arc,218,;
GCC,arc,219,true ;
GCC,arc,220,|| to == ARG_POINTER_REGNUM ) ) {
GCC,arc,221,STACK_POINTER_REGNUM ) ) {
GCC,arc,222,false ;
GCC,arc,223,0;
GCC,arc,224,);
GCC,arc,225,false ;
GCC,arc,226,) return <NUM_LIT> ;
GCC,arc,227,;
GCC,arc,228,->machine ;
GCC,arc,229,op ;
GCC,arc,230,
GCC,arc,231,ARC_CC_NC ;
GCC,arc,232,;
GCC,arc,233,) ;
GCC,arc,234,
GCC,arc,235,", get_frame_register () );"
GCC,arc,236,
GCC,arc,237,= <NUM_LIT> ;
GCC,arc,238,var_size ;
GCC,arc,239,<NUM_LIT> ) arc_regno_reg_class [ IPLR_REG ] = GENERAL_REGS ;
GCC,arc,240,;
GCC,arc,241,) ;
GCC,arc,242,PASS_POS_INSERT_AFTER }
GCC,arc,243,target_default <NUM_LIT> ) {
GCC,arc,244,;
GCC,arc,245,"( ( x ) , <NUM_LIT> ) , <NUM_LIT> ) ) ) {"
GCC,arc,246,> <NUM_LIT> ) && <NUM_LIT> ) ) ;
GCC,arc,247,;
GCC,arc,248,;
GCC,arc,249,<NUM_LIT> ) ;
GCC,arc,250,) ;
GCC,arc,251,;
GCC,arc,252,", <NUM_LIT> ) ) ;"
GCC,arc,253,regno ) ) != <NUM_LIT> }
GCC,arc,254,) ;
GCC,arc,255,
GCC,arc,256,;
GCC,arc,257,;
GCC,arc,258,{
GCC,arc,259,"arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] ) ;"
GCC,arc,260,;
GCC,arc,261,) ;
GCC,arc,262,
GCC,arc,263,reg_alloc_order ) ) ;
GCC,arc,264,{
GCC,arc,265,current_function_call_type;
GCC,arc,266,;
GCC,arc,267,", const1_rtx ) ;"
GCC,arc,268,;
GCC,arc,269,) {
GCC,arc,270,
GCC,arc,271,_insn = emit_return_insn ( ret ) ;
GCC,arc,272,
GCC,arc,273,true ;
GCC,arc,274,0 ;
GCC,arc,275,;
GCC,arc,276,cfun -> machine -> frame_info . interrupt) ) ;
GCC,arc,277,NOTE_INSN_FUNCTION_BEGINS );
GCC,arc,278,;
GCC,arc,279,
GCC,arc,280,2);
GCC,arc,281,cfun -> fsm ));
GCC,arc,282,address (PATTERN (insn) ) !=SIMM_HIGH) ) {
GCC,arc,283,ARC_CCFSM_STATE_LOOP_ACTIVE ) {
GCC,arc,284,"_cc, arc_started_arc - > branch - > record);"
GCC,arc,285,return true ;
GCC,arc,286,) ;
GCC,arc,287,== <NUM_LIT> ) return false ;
GCC,arc,288,false ;
GCC,arc,289,1 ;
GCC,arc,290,->unalign_delete( unalign -> );
GCC,arc,291,"( extra_plus_reg_size , <NUM_LIT> ) ;"
GCC,arc,292,lower [ fn_type ] ;
GCC,arc,293,end_reg ;
GCC,arc,294,;
GCC,arc,295,
GCC,arc,296,) ;
GCC,arc,297,;
GCC,arc,298,;
GCC,arc,299,", reg );"
GCC,arc,300,) ;
GCC,arc,301,"DImode , regno ) ;"
GCC,arc,302,;
GCC,arc,303,) ;
GCC,arc,304,{
GCC,arc,305,{
GCC,arc,306,== 0;
GCC,arc,307,( <NUM_LIT> << regno ) ;
GCC,arc,308,
GCC,arc,309,
GCC,arc,310,;
GCC,arc,311,
GCC,arc,312,) {
GCC,arc,313,"exec_file, name ) ;"
GCC,arc,314,;
GCC,arc,315,"<NUM_LIT> , TARGET_SPLIT_HOTFIX_SIMPLE_COPY , TARGET_SPLIT_HOTFIX_DIST_CALL_SPLIT , TARGET_HOTFIX_CALL_FRAME_NOT_REQ );"
GCC,arc,316,"<STR_LIT> , sizeof ( arc_ltimode_t ) ) ;"
GCC,arc,317,
GCC,arc,318,);
GCC,arc,319,opt_calls ;
GCC,arc,320,with calls_vla;
GCC,arc,321,;
GCC,arc,322,) {
GCC,arc,323,) {
GCC,arc,324,attrs ) ) return false ;
GCC,arc,325,", regno ) ;"
GCC,arc,326,= get_seq_insn ( <NUM_COND> ) ;
GCC,arc,327,<STR_LIT>;
GCC,arc,328,NULL);
GCC,arc,329,AND_EXPR ) {
GCC,arc,330,1 ;
GCC,arc,331,) ;
GCC,arc,332,"static bool arc_hard_regno_mode_ok ( unsigned int, enum machine_mode ) {"
GCC,arc,333,
GCC,arc,334,NEXT_INSN ( insn ) ;
GCC,arc,335,] = <NUM_LIT> ;
GCC,arc,336,arc_multcost = COSTS_N_INSNS (flag_pic ? 1 : LOCAL_SIZE (SET_ARCH_INFO) ) ;
GCC,arc,337,rtx) ;
GCC,arc,338,Invalid register conversion );
GCC,arc,339,
GCC,arc,340,) {
GCC,arc,341,labelno ) ;
GCC,arc,342,) return false ;
GCC,arc,343,( decl ) ;
GCC,arc,344,sym_ref ) ) );
GCC,arc,345,
GCC,arc,346,
GCC,arc,347,", sym_ref );"
GCC,arc,348,. log < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;
GCC,arc,349,) ;
GCC,arc,350,: return TARGET_SISUC_DMPY ;
GCC,arc,351,return true;
GCC,arc,352,mode );
GCC,arc,353,"gen_rtx_SYMBOL_REF( VOIDmode , orig_x );"
GCC,arc,354,(NUM_LIT);
GCC,arc,355,;
GCC,arc,356,;
GCC,arc,357,tmp ) ;
GCC,arc,358,addr );
GCC,arc,359,false;
GCC,arc,360,) ;
GCC,arc,361,
GCC,arc,362,( insn ) && prev active_insn \= ainsn ) )&& return active delay slot}
GCC,arc,363,... ret = 1;
GCC,arc,364,) ;
GCC,arc,365,buf ;
GCC,arc,366,. type ) ) ;
GCC,arc,367,))) {
GCC,arc,368,gen_s390_atomic_diag ());
GCC,arc,369,cond ) ) ;
GCC,arc,370,;
GCC,arc,371,"reg_class , bool ) ;"
GCC,arc,372,) {
GCC,arc,373,"in , 1 ) ) && XINT ( XEXP ( in , 1 ) , <NUM_LIT> ) != 0 );"
GCC,arc,374,_INT : {
GCC,arc,375,{
GCC,arc,376,;
GCC,arc,377,"CC_ZNmode , CC_REG ) ;"
GCC,arc,378,);
GCC,arc,379,) ;
GCC,arc,380,regno ;
GCC,arc,381,) ;
GCC,arc,382,;
GCC,arc,383,) ) = <NUM_LIT> ;
GCC,arc,384,) {
GCC,arc,385,"save_mode , i );"
GCC,arc,386,& ( <NUM_LIT> << i ) ) < <NUM_LIT> ) {
GCC,arc,387,statement:
GCC,arc,388,;
GCC,arc,389,
GCC,arc,390,;
GCC,arc,391,) ;
GCC,arc,392,"reg , mem ) ) ;"
GCC,arc,393,return CC_EQmode ;
GCC,arc,394,) ;
GCC,arc,395,ARC_CC_LT : return False ;
GCC,arc,396,) ;
GCC,arc,397,insn_info ) ;
GCC,arc,398,;
GCC,arc,399,"( <ID> , <NUM_LIT> ) ) ) {"
GCC,arc,400,) ) ;
GCC,arc,401,false ;
GCC,arc,402,consumer );
GCC,arc,403,) {
GCC,arc,404,( x ) ) : false ) ;
GCC,arc,405,SYMBOL_REF_DECL ( x ) ) : targetm . symbolic_operand_failure ( x ) ) ;
GCC,arc,406,( next ) ) == SEQUENCE ) ;
GCC,arc,407,NEXT_NON_NOTE ( label ) ) ;
GCC,arc,408,1 s}
GCC,arc,409,= true ;
GCC,arc,410,up = *lo ;
GCC,arc,411,"note , <NUM_LIT> ) <= arc_unalign_prob_threshold ) }"
GCC,arc,412,
GCC,arc,413,
GCC,arc,414,
GCC,arc,415,:  return true;
GCC,arc,416,);
GCC,arc,417,case PRE_DEC : {
GCC,arc,418,", <NUM_LIT> ) == pc_rtx ? GET_CODE ( dest <NUM_LIT> ) : <NUM_LIT> ) ;"
GCC,arc,419,== 0 ? <NUM_LIT> : <NUM_LIT>
GCC,arc,420,false }
GCC,arc,421,);
GCC,arc,422,: return (align <= 2) ;
GCC,arc,423,", ? );"
GCC,arc,424,"op0 , op1 );"
GCC,arc,425,) ;
GCC,arc,426,{
GCC,arc,427,", original_x, offset ) ) ;"
GCC,arc,428,7;
GCC,arc,429,
GCC,arc,430,) ) + offset ;
GCC,arc,431,) ;
GCC,arc,432,}
GCC,arc,433,GEN_INT ( offset );
GCC,arc,434,es ;
GCC,arc,435,
GCC,arc,436,": 0 , 0 );"
GCC,arc,437,<NUM_LIT> ) {
GCC,arc,438,( base ) ) return false;
GCC,arc,439,
GCC,arc,440,) ) ;
GCC,arc,441,= 1 ;
GCC,arc,442,!= 0xdead ) ;
GCC,arc,443,;
GCC,arc,444,NULL_RTX ;
GCC,arc,445,<NUM_LIT> : break ;
GCC,arc,446,) ;
GCC,arc,447,false ;
GCC,arc,448,) {
GCC,arc,449,
GCC,arc,450,", gate ) ;"
GCC,arc,451,m);
GCC,arc,452,;
GCC,arc,453,;
GCC,arc,454,;
GCC,arc,455,rt ) ;
GCC,arc,456,
GCC,arc,457,) }
GCC,arc,458,;
GCC,arc,459,) ;
GCC,arc,460,", arg ) ;"
GCC,arc,461,) ) ;
GCC,arc,462,>;
GCC,arc,463,
GCC,arc,464,false ;
GCC,arc,465,
GCC,arc,466,;
GCC,arc,467,
GCC,arc,468,
LLVM,NVPTX,0,) - 1 ) * FuncTy -> getPointerAddressSpace ( ) + <INVOCATION> ;
LLVM,NVPTX,1,createMyModule<ModulePass>() {
LLVM,NVPTX,2,"s<Integer, Object>();"
LLVM,NVPTX,3,
LLVM,NVPTX,4,"ImplicitOffsetType , Builder . getUsed -> () , <NUM_LIT>, <NUM_LIT>, <NUM_LIT> );"
LLVM,NVPTX,5,;
LLVM,NVPTX,6,key);
LLVM,NVPTX,7,<T> (accessor);
LLVM,NVPTX,8,Changed ;
LLVM,NVPTX,9,;
LLVM,NVPTX,10,;
LLVM,NVPTX,11,( Str ) ;
LLVM,NVPTX,12,Pass();
LLVM,NVPTX,13,override {
LLVM,NVPTX,14,AU){
LLVM,NVPTX,15,;
LLVM,NVPTX,16,
LLVM,NVPTX,17,"F, bb,&nbsp;"
LLVM,NVPTX,18,
LLVM,NVPTX,19,( firstTerminatorInst ) ;
LLVM,NVPTX,20,> ( ) ;
LLVM,NVPTX,21,
LLVM,NVPTX,22,( ) ;
LLVM,NVPTX,23,
LLVM,NVPTX,24,const override;
LLVM,NVPTX,25,
LLVM,NVPTX,26,) ;
LLVM,NVPTX,27,{
LLVM,NVPTX,28,"const char * bool isConnectToServer, {"
LLVM,NVPTX,29,( ) . convertToDouble ( ) ;
LLVM,NVPTX,30,;
LLVM,NVPTX,31,] gv_array ;
LLVM,NVPTX,32,;
LLVM,NVPTX,33,
LLVM,NVPTX,34,", e , O ) ;"
LLVM,NVPTX,35,<STR_LIT> ;
LLVM,NVPTX,36,Inst ) ;
LLVM,NVPTX,37,( ) ) ) ;
LLVM,NVPTX,38,", fileName ) ;"
LLVM,NVPTX,39,O ) ;
LLVM,NVPTX,40,HalfTyID : return <STR_LIT> ;
LLVM,NVPTX,41,Expr ) ;
LLVM,NVPTX,42,getOperand ( i ) ;
LLVM,NVPTX,43,) {
LLVM,NVPTX,44,;
LLVM,NVPTX,45,) ) {
LLVM,NVPTX,46,( ) ) {
LLVM,NVPTX,47,) {
LLVM,NVPTX,48,Name -> isDeclaration ( ) && <LIT> ) {
LLVM,NVPTX,49,true ;
LLVM,NVPTX,50,&& OutStreamer != nullptr);
LLVM,NVPTX,51,:: MO_Metadata: O << <MD_LIT> ;
LLVM,NVPTX,52,) ;
LLVM,NVPTX,53,) ;
LLVM,NVPTX,54,gv_array [ i ] );
LLVM,NVPTX,55,) ;
LLVM,NVPTX,56,<STR_LIT> << --------------------------------------------------------------- ;
LLVM,NVPTX,57,<< \n .kernel  ;
LLVM,NVPTX,58,;
LLVM,NVPTX,59,;
LLVM,NVPTX,60,] '\0' ;
LLVM,NVPTX,61,) {
LLVM,NVPTX,62,O ) ;
LLVM,NVPTX,63,llvm::isKernelFunction(*F) ? define dso_local  : define dso_local ;
LLVM,NVPTX,64,{
LLVM,NVPTX,65,str ( ) </STR_LIT> );
LLVM,NVPTX,66,reqntidz ) == false ) reqntidz = reqntidx ;
LLVM,NVPTX,67,) ;
LLVM,NVPTX,68,) ;
LLVM,NVPTX,69,) ) {
LLVM,NVPTX,70,<LAST_STATEMENT_LIT> ;
LLVM,NVPTX,71,;
LLVM,NVPTX,72,) {
LLVM,NVPTX,73,<STR_LIT> :
LLVM,NVPTX,74,case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :
LLVM,NVPTX,75,"RHS , Ctx ) ;"
LLVM,NVPTX,76,']' ;
LLVM,NVPTX,77,']' ;
LLVM,NVPTX,78,( );
LLVM,NVPTX,79,;
LLVM,NVPTX,80,MO_ExternalSymbol : O << * MO . <STR_LIT> ;
LLVM,NVPTX,81,& index ) ;
LLVM,NVPTX,82,
LLVM,NVPTX,83,( ) ;
LLVM,NVPTX,84,] ;
LLVM,NVPTX,85,;
LLVM,NVPTX,86,++ ;
LLVM,NVPTX,87,) ) ;
LLVM,NVPTX,88,<STR_LIT> ;
LLVM,NVPTX,89,) {
LLVM,NVPTX,90,->is s a <Method>() ) {
LLVM,NVPTX,91,) ) {
LLVM,NVPTX,92,( CPV ) ) {
LLVM,NVPTX,93,return false;
LLVM,NVPTX,94,
LLVM,NVPTX,95,;
LLVM,NVPTX,96,"emitIntValue(3, 1);"
LLVM,NVPTX,97,
LLVM,NVPTX,98,continue ;
LLVM,NVPTX,99,);
LLVM,NVPTX,100,( ) ;
LLVM,NVPTX,101,") , O ) ;"
LLVM,NVPTX,102,"( ) , O <b> ) ;"
LLVM,NVPTX,103,) ;
LLVM,NVPTX,104,<STR_LIT> ;
LLVM,NVPTX,105,
LLVM,NVPTX,106,) -> getName ( Register ) ) ;
LLVM,NVPTX,107,( ) ;
LLVM,NVPTX,108,
LLVM,NVPTX,109,<STR_LIT> ;
LLVM,NVPTX,110,! */ ){
LLVM,NVPTX,111,) {
LLVM,NVPTX,112,0 ;
LLVM,NVPTX,113,ue;
LLVM,NVPTX,114,( ) ) ;
LLVM,NVPTX,115,) ) );
LLVM,NVPTX,116,
LLVM,NVPTX,117,) ;
LLVM,NVPTX,118,<STR_LIT> ;
LLVM,NVPTX,119,O ) ;
LLVM,NVPTX,120,O ) ;
LLVM,NVPTX,121,;
LLVM,NVPTX,122,{
LLVM,NVPTX,123,Bytes_str . str ( ) . c_str ( ) ) ) ;
LLVM,NVPTX,124,<STR_LIT> ;
LLVM,NVPTX,125,) {
LLVM,NVPTX,126,
LLVM,NVPTX,127,
LLVM,NVPTX,128,;
LLVM,NVPTX,129,value;
LLVM,NVPTX,130,[_size];
LLVM,NVPTX,131,
LLVM,NVPTX,132,", & G ) ;"
LLVM,NVPTX,133,!= e ;
LLVM,NVPTX,134,;
LLVM,NVPTX,135,* ) ( buffer + pos ) ;
LLVM,NVPTX,136,( ) ;
LLVM,NVPTX,137,O ) ;
LLVM,NVPTX,138,< Instruction > ( U ) ;
LLVM,NVPTX,139,;
LLVM,NVPTX,140,DirName ) ;
LLVM,NVPTX,141,str ( ) ) ;
LLVM,NVPTX,142,;
LLVM,NVPTX,143,filename ) ;
LLVM,NVPTX,144,") , createAsmPrinter ) </ISA_LIT>;"
LLVM,NVPTX,145,"<ISA_LIT>AsmPrinter::lowerImageHandleSymbol(const unsigned Index, MCOperand &MCOp) {"
LLVM,NVPTX,146,OutContext ) ) ;
LLVM,NVPTX,147,<STR_LIT> ;
LLVM,NVPTX,148,( ) ;
LLVM,NVPTX,149,<< <STR_LIT> ;
LLVM,NVPTX,150,
LLVM,NVPTX,151,<STR_LIT> ;
LLVM,NVPTX,152,;
LLVM,NVPTX,153,
LLVM,NVPTX,154,;
LLVM,NVPTX,155,;
LLVM,NVPTX,156,0 ;
LLVM,NVPTX,157,
LLVM,NVPTX,158,;
LLVM,NVPTX,159,oneFunc ) ;
LLVM,NVPTX,160,) ;
LLVM,NVPTX,161,"*Mang , Out );"
LLVM,NVPTX,162,) > ;
LLVM,NVPTX,163,O ) ;
LLVM,NVPTX,164,MF -> getFunction ( ) O << {
LLVM,NVPTX,165,) ) ;
LLVM,NVPTX,166,
LLVM,NVPTX,167,( ) ) ;
LLVM,NVPTX,168,M . global_end ( ) ;
LLVM,NVPTX,169,;
LLVM,NVPTX,170,<STR_LIT> ;
LLVM,NVPTX,171,< Str >> ) ;
LLVM,NVPTX,172,maxntidy = <NUM_LIT> ;
LLVM,NVPTX,173,) ;
LLVM,NVPTX,174,( ) ) {
LLVM,NVPTX,175,-> getElementType ( ) ) ;
LLVM,NVPTX,176,str ( ) ) ) ;
LLVM,NVPTX,177,
LLVM,NVPTX,178,;
LLVM,NVPTX,179,end();
LLVM,NVPTX,180,
LLVM,NVPTX,181,"return lowerGEP(CE,AP);"
LLVM,NVPTX,182,true ;
LLVM,NVPTX,183,"&_FVMContext , SymbolTable ) ;"
LLVM,NVPTX,184,;
LLVM,NVPTX,185,{
LLVM,NVPTX,186,( ) ) {
LLVM,NVPTX,187,( GVar ) ;
LLVM,NVPTX,188,", Filename ) ;"
LLVM,NVPTX,189,[ RC ] ;
LLVM,NVPTX,190,) ) ;
LLVM,NVPTX,191,true ;
LLVM,NVPTX,192,curFunc ;
LLVM,NVPTX,193,> GVDependentVariables ;
LLVM,NVPTX,194,= Others . end ( ) ;
LLVM,NVPTX,195,
LLVM,NVPTX,196,{
LLVM,NVPTX,197,;
LLVM,NVPTX,198,) ;
LLVM,NVPTX,199,
LLVM,NVPTX,200,) ;
LLVM,NVPTX,201,
LLVM,NVPTX,202,
LLVM,NVPTX,203,( ) ;
LLVM,NVPTX,204,"( TD , ETy ) ;"
LLVM,NVPTX,205,
LLVM,NVPTX,206,) ) {
LLVM,NVPTX,207,<< <STR_LIT> ;
LLVM,NVPTX,208,;
LLVM,NVPTX,209,) ;
LLVM,NVPTX,210,", O ) ;"
LLVM,NVPTX,211,OriginalNameStream << C;
LLVM,NVPTX,212,) {
LLVM,NVPTX,213,"RHS , Ctx ) ;"
LLVM,NVPTX,214,"MO_JumpTableIndex : MCOp = MCOperand :: CreateExpr ( MCBinaryExpr :: Create ( MCBinaryExpr :: Sub , MCSymbolRefExpr :: Create ( MO . getGlobal ( ) -> getSymbol ( ) , OutContext ) , MCBinaryExpr :: Create ( MCBinaryExpr :: Sub , MCSymbolRefExpr :: Create ( MO . getTargetFlags ( ) -> getSymbol ( ) , OutContext ) , MCBinaryExpr :: Create ( MCBinaryExpr :: Sub , MCSymbolRefExpr :: Create ( MO . getIndex ( ) -> getSymbol ( ) , OutContext ) , MCS"
LLVM,NVPTX,215,() ;
LLVM,NVPTX,216,. getGlobal ( ) ) ;
LLVM,NVPTX,217,. getOperand ( 1 ) ) ;
LLVM,NVPTX,218,( END ) ;
LLVM,NVPTX,219,ModuleID = ' <NUM_LIT> + MMID . getModuleIdentifier ( ) + ' ) ;
LLVM,NVPTX,220,( ) ;
LLVM,NVPTX,221,) {
LLVM,NVPTX,222,( ) ;
LLVM,NVPTX,223,);
LLVM,NVPTX,224,;
LLVM,NVPTX,225,<ElementSize> }
LLVM,NVPTX,226,ETy ) ;
LLVM,NVPTX,227,raw_ostream &<BUILTIN_MI>) {
LLVM,NVPTX,228,<NUM_LIT> << vtparts [ i ] . <STR_LIT> ;
LLVM,NVPTX,229,:: path :: is_absolute ( Filename ) ) {
LLVM,NVPTX,230,] = <NUM_LIT> ;
LLVM,NVPTX,231,( RC ) ;
LLVM,NVPTX,232,/ <NUM_LIT> << <STR_LIT> << I -> getName ( ) << <STR_LIT> ;
LLVM,NVPTX,233,;
LLVM,NVPTX,234,== <NUM_LIT> || sz == <NUM_LIT> ) ) sz = <NUM_LIT> ;
LLVM,NVPTX,235,;
LLVM,NVPTX,236,n;
LLVM,NVPTX,237,"end ( ) , gv_array [ i ] ) ;"
LLVM,NVPTX,238,true ;
LLVM,NVPTX,239,;
LLVM,NVPTX,240,") , O ) ;"
LLVM,NVPTX,241,( ) . c_str ( ) ) ;
LLVM,NVPTX,242,", O ) ;"
LLVM,NVPTX,243,) ) ;
LLVM,NVPTX,244,;
LLVM,NVPTX,245,", Inst ) ;"
LLVM,NVPTX,246,<STR_LIT> ;
LLVM,NVPTX,247,) ;
LLVM,NVPTX,248,<STR_LIT> ) ;
LLVM,NVPTX,249,) ;
LLVM,NVPTX,250,++ ;
LLVM,NVPTX,251,<STR_LIT> ;
LLVM,NVPTX,252,Result ;
LLVM,NVPTX,253,) ;
LLVM,NVPTX,254,") , Globals ) ;"
LLVM,NVPTX,255,if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ;
LLVM,NVPTX,256,if (nvptxSubtarget.is64Bit()) O << <STR_LIT> ;
LLVM,NVPTX,257,
LLVM,NVPTX,258,", Ctx ) ;"
LLVM,NVPTX,259,:: V4 ) O << <STR_LIT> ;
LLVM,NVPTX,260,) ;
LLVM,NVPTX,261,> Tmp ;
LLVM,NVPTX,262,Storage ;
LLVM,NVPTX,263,( ) ;
LLVM,NVPTX,264,
LLVM,NVPTX,265,> ( NTM.getSubtargetImpl() ) ;
LLVM,NVPTX,266,);
LLVM,NVPTX,267,<< ElementSize ;
LLVM,NVPTX,268,true ;
LLVM,NVPTX,269,{
LLVM,NVPTX,270,-> users ( ) ) {
LLVM,NVPTX,271,) ;
LLVM,NVPTX,272,"MF , O ) ;"
LLVM,NVPTX,273,;
LLVM,NVPTX,274,( i ) ;
LLVM,NVPTX,275,) ;
LLVM,NVPTX,276,;
LLVM,NVPTX,277,;
LLVM,NVPTX,278,
LLVM,NVPTX,279,M ) ;
LLVM,NVPTX,280,( Ty ) ;
LLVM,NVPTX,281,) ;
LLVM,NVPTX,282,<NUM_LIT> ;
LLVM,NVPTX,283,;
LLVM,NVPTX,284,
LLVM,NVPTX,285,) ;
LLVM,NVPTX,286,) ;
LLVM,NVPTX,287,BitCast : DstTy -> getAddressSpace ( ) = <STR_LIT>
LLVM,NVPTX,288,
LLVM,NVPTX,289,);
LLVM,NVPTX,290,i ;
LLVM,NVPTX,291,) ) {
LLVM,NVPTX,292,-> getType ( ) ;
LLVM,NVPTX,293,{
LLVM,NVPTX,294,: <STR_LIT> O << <STR_LIT>getMBBLabel ( * ( MO . getMBB ( ) ) ) <STR_LIT>;
LLVM,NVPTX,295,", float64 ) ;"
LLVM,NVPTX,296,false ;
LLVM,NVPTX,297,) ;
LLVM,NVPTX,298,": return MCBinaryExpr :: CreateOr ( LHS , RHS , Ctx ) ;"
LLVM,NVPTX,299,", & index ) ;"
LLVM,NVPTX,300,
LLVM,NVPTX,301,", ProcessingGeneric ) ;"
LLVM,NVPTX,302,
LLVM,NVPTX,303,"O <<  vx << idx << , ;"
LLVM,NVPTX,304,
LLVM,NVPTX,305,") ) -> <Other-ISA-LIT> <B> ISA_LIT <C>b</C> . generateGlobalVariable ( & M , gv_array [ i ] ) ;"
LLVM,NVPTX,306,!= numVRs ;
LLVM,NVPTX,307,
LLVM,NVPTX,308,
LLVM,NVPTX,309,"Linkage ( GVar , GVar -> getName ( ) ) ;"
LLVM,NVPTX,310,
LLVM,NVPTX,311,") , E = M . global_end ( ) ;"
LLVM,NVPTX,312,> ( llvm :: unbundleArray ( * I ) -> getType ( ) ) <STR_LIT> <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,313,) ;
LLVM,NVPTX,314,[  << <STR_LIT> << TD -> getTypeAllocSize ( ETy ) ;
LLVM,NVPTX,315,] . getVectorElementType ( ) ;
LLVM,NVPTX,316,i ] ;
LLVM,NVPTX,317,) << <STR_LIT> ;
LLVM,NVPTX,318,! Cursor ) {
LLVM,NVPTX,319,"( <NUM_LIT> ) , ProcessingGeneric ) ;"
LLVM,NVPTX,320,idx ;
LLVM,NVPTX,321,( <NUM_LIT> ) ;
LLVM,NVPTX,322,FPTrunc : {
LLVM,NVPTX,323,MO_ExternalSymbol : {
LLVM,NVPTX,324,( ST ) -> getElementOffset ( i ) ;
LLVM,NVPTX,325,
LLVM,NVPTX,326,sz = <NUM_LIT> ;
LLVM,NVPTX,327,TD -> getTypeAllocSize ( ETy ) ;
LLVM,NVPTX,328,<STR_LIT> ;
LLVM,NVPTX,329,;
LLVM,NVPTX,330,}
LLVM,NVPTX,331,( ) ;
LLVM,NVPTX,332,) ;
LLVM,NVPTX,333,(M) ;
LLVM,NVPTX,334,: case <STR_LIT> :
LLVM,NVPTX,335,getType ( ) ) ;
LLVM,NVPTX,336,oneFunc ) ;
LLVM,NVPTX,337,;
LLVM,NVPTX,338,) table [ key ];
LLVM,NVPTX,339,val ;
LLVM,NVPTX,340,", Globals ) ;"
LLVM,NVPTX,341,;
LLVM,NVPTX,342,) ;
LLVM,NVPTX,343,EmitRawText (# Loop start);
LLVM,NVPTX,344,
LLVM,NVPTX,345,( ) ;
LLVM,NVPTX,346,);
LLVM,NVPTX,347,( Directive ));
LLVM,NVPTX,348,) ;
LLVM,NVPTX,349,}
LLVM,NVPTX,350,) ;
LLVM,NVPTX,351,( ) ;
LLVM,NVPTX,352,<STR_LIT> << mincta << <STR_LIT> << endl ;
LLVM,NVPTX,353,stream ;
LLVM,NVPTX,354,<STR_LIT> ;
LLVM,NVPTX,355,<STR_LIT> ;
LLVM,NVPTX,356,c_str ( ) ) ;
LLVM,NVPTX,357,OS ) {
LLVM,NVPTX,358,
LLVM,NVPTX,359,<STR_LIT> ;
LLVM,NVPTX,360,reader ;
LLVM,NVPTX,361,-> nextLine ( );
LLVM,NVPTX,362,Expr ) ;
LLVM,NVPTX,363,"Parser::encodeSymbolRef(const MCInst &MI, const struct MCOperand &MO, raw_ostream &OS) const {"
LLVM,NVPTX,364,);
LLVM,NVPTX,365,( <STR_LIT> ) );
LLVM,NVPTX,366,if (It == ImageTypeName.end()) {
LLVM,NVPTX,367,) {
LLVM,NVPTX,368,) {
LLVM,NVPTX,369,c_str ( ) ) ;
LLVM,NVPTX,370,
LLVM,NVPTX,371,(The<ISA_LIT>Target);
LLVM,NVPTX,372,. getSExtValue ( ) ;
LLVM,NVPTX,373,false ;
LLVM,NVPTX,374,SymNamePtr ) ) ) ;
LLVM,NVPTX,375,:: MO_ExternalSymbol :  MCOp = MCOperand::createExtSymbol(MO.getSymbolName());
LLVM,NVPTX,376,. addOperand ( MCOp ) ;
LLVM,NVPTX,377,<STR_LIT> ) ;
LLVM,NVPTX,378,']' ;
LLVM,NVPTX,379,}
LLVM,NVPTX,380,<STR_LIT> ) ;
LLVM,NVPTX,381,;
LLVM,NVPTX,382,"The last statement of this code snippet is: printOperand(MI, opNum + 1, O);"
LLVM,NVPTX,383,case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ;
LLVM,NVPTX,384,const TargetRegisterClass registerClass ) {
LLVM,NVPTX,385,
LLVM,NVPTX,386,
LLVM,NVPTX,387,) ;
LLVM,NVPTX,388,<NUM_LIT> ] ;
LLVM,NVPTX,389,<NUM_LIT> ;
LLVM,NVPTX,390,i ;
LLVM,NVPTX,391,) ;
LLVM,NVPTX,392,F ) ;
LLVM,NVPTX,393,{
LLVM,NVPTX,394,;
LLVM,NVPTX,395,) {
LLVM,NVPTX,396,curFunc ;
LLVM,NVPTX,397,) ) {
LLVM,NVPTX,398,"String linuxPath, String filename) {"
LLVM,NVPTX,399,) ;
LLVM,NVPTX,400,- ~AsmPrinter ( ) {
LLVM,NVPTX,401,GV ;
LLVM,NVPTX,402,C ;
LLVM,NVPTX,403,;
LLVM,NVPTX,404,". setLinkage ( GlobalValue :: <FunctionName>, LocalLinkage );"
LLVM,NVPTX,405,caseAlphaString(string);
LLVM,NVPTX,406,ISA) {
LLVM,NVPTX,407,true ) ;
LLVM,NVPTX,408,��ArgumentPass;
LLVM,NVPTX,409,= false ;
LLVM,NVPTX,410,( ) != AddressSpace :: ADDRESS_SPACE_GENERIC );
LLVM,NVPTX,411,0 ) ) ;
LLVM,NVPTX,412,;
LLVM,NVPTX,413,"> <NUM_LIT>, GEP->isInBounds());"
LLVM,NVPTX,414,( I ) ) {
LLVM,NVPTX,415,);
LLVM,NVPTX,416,;
LLVM,NVPTX,417,false ;
LLVM,NVPTX,418,"( Src ) , TypeOfNewCast ) ;"
LLVM,NVPTX,419,", <NUM_LIT> ) ) ;"
LLVM,NVPTX,420,"getOperand ( 0 ) ) , Indices , <STR_LIT> , GEPI ) ;"
LLVM,NVPTX,421,>;
LLVM,NVPTX,422,PointerAuth</ISA_LIT>();
LLVM,NVPTX,423,
LLVM,NVPTX,424,TypeOfNewCast ) ;
LLVM,NVPTX,425,<NUM_LIT> ) ;
LLVM,NVPTX,426,) {
LLVM,NVPTX,427,Idx );
LLVM,NVPTX,428,) ;
LLVM,NVPTX,429,> ( I ) ) {
LLVM,NVPTX,430,;
LLVM,NVPTX,431,MachineBasicBlock :: iterator MI ) const {
LLVM,NVPTX,432,
LLVM,NVPTX,433,false ;
LLVM,NVPTX,434,const {
LLVM,NVPTX,435,);
LLVM,NVPTX,436,{
LLVM,NVPTX,437,) ;
LLVM,NVPTX,438,{
LLVM,NVPTX,439,getFrameRegister ( MF ) ;
LLVM,NVPTX,440,getCallFrameIndexSize ( ) ) ;
LLVM,NVPTX,441,MFI ? MFI : RFP ;
LLVM,NVPTX,442,) ;
LLVM,NVPTX,443,
LLVM,NVPTX,444,and return true;
LLVM,NVPTX,445,{
LLVM,NVPTX,446,{
LLVM,NVPTX,447,. getFirstInsertionPt ( ) ) ;
LLVM,NVPTX,448,;
LLVM,NVPTX,449,") , llvm :: ADDRESS_SPACE_GENERIC ) ) group `Function::Create(M, CVTA, ParamTypes)`"
LLVM,NVPTX,450,NewValue ;
LLVM,NVPTX,451,
LLVM,NVPTX,452,;
LLVM,NVPTX,453,{
LLVM,NVPTX,454,-> getAddressSpace ( ) ;
LLVM,NVPTX,455,
LLVM,NVPTX,456,{
LLVM,NVPTX,457,-> getName ( ) ;
LLVM,NVPTX,458,", SubmittedCode , <STR_LIT> ) ;"
LLVM,NVPTX,459,) ) {
LLVM,NVPTX,460,;
LLVM,NVPTX,461,++ i ) {
LLVM,NVPTX,462,E ;
LLVM,NVPTX,463,"<NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) ;"
LLVM,NVPTX,464,<STR_LIT> ) ;
LLVM,NVPTX,465,{
LLVM,NVPTX,466,;
LLVM,NVPTX,467,. <NUM_LIT> ( G ) ;
LLVM,NVPTX,468,) . begin ( ) ) ;
LLVM,NVPTX,469,named_metadata_end ( ) ;
LLVM,NVPTX,470,;
LLVM,NVPTX,471,"llvm :: Intrinsic :: getDeclaration ( M , llvm :: Intrinsic :: convert_from_ty , ParamTypes ) ;"
LLVM,NVPTX,472,( ) ;
LLVM,NVPTX,473,{
LLVM,NVPTX,474,) ;
LLVM,NVPTX,475,PARAM_VALS_ADDRSPACE ) ) ;
LLVM,NVPTX,476,) ;
LLVM,NVPTX,477,"cleanupValue ( DecomposeInitEVT ( EVT::fromType ( MVT::f32 ) , VT ( MVT::i32 ) ) ) ;"
LLVM,NVPTX,478,else if ( isBuffer ( * TexHandle ) ) {
LLVM,NVPTX,479,getContext ( ) ) ) ;
LLVM,NVPTX,480,;
LLVM,NVPTX,481,
LLVM,NVPTX,482,( <NUM_LIT> );
LLVM,NVPTX,483,) ;
LLVM,NVPTX,484,i ) {
LLVM,NVPTX,485,( ) ) ;
LLVM,NVPTX,486,"I , PostorderStack , Visited ) ;"
LLVM,NVPTX,487,Visited ) ;
LLVM,NVPTX,488,<ISA_LIT>InferAddressSpaces ();
LLVM,NVPTX,489,Clause</ISA_LIT>();
LLVM,NVPTX,490,"0 ), Op . }"
LLVM,NVPTX,491,User ) ;
LLVM,NVPTX,492,;
LLVM,NVPTX,493,I ) ;
LLVM,NVPTX,494,InferredAddrSpace );
LLVM,NVPTX,495,InferredAddrSpace ) ;
LLVM,NVPTX,496,;
LLVM,NVPTX,497,uint64_t Features) {
LLVM,NVPTX,498,) O << <STR_LIT> ;
LLVM,NVPTX,499,Unhandled relocation modifier );
LLVM,NVPTX,500,) ;
LLVM,NVPTX,501,<NUM_LIT> ;
LLVM,NVPTX,502,const MCSubtargetInfo & STI );
LLVM,NVPTX,503,:: RTZ : O << <STR_LIT> ;
LLVM,NVPTX,504,~IsDef ;
LLVM,NVPTX,505,"MAI, MII, MRI, STI) {"
LLVM,NVPTX,506,default: O << Invalid comparison type;
LLVM,NVPTX,507,<STR_LIT> ;
LLVM,NVPTX,508,) ;
LLVM,NVPTX,509,{
LLVM,NVPTX,510,
LLVM,NVPTX,511,<STR_LIT> ) ) {
LLVM,NVPTX,512,getExpr ( ) ;
LLVM,NVPTX,513,getName ( ) ;
LLVM,NVPTX,514,"addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,NVPTX,515,<NUM_LIT>;
LLVM,NVPTX,516,
LLVM,NVPTX,517,( DestRC == & <STR_LIT> ) {
LLVM,NVPTX,518,addMBB ( FBB ) ;
LLVM,NVPTX,519,;
LLVM,NVPTX,520,) ) return <NUM_LIT> ;
LLVM,NVPTX,521,
LLVM,NVPTX,522,<STR_LIT> ) {
LLVM,NVPTX,523,true ;
LLVM,NVPTX,524,) ;
LLVM,NVPTX,525,( FBB ) ;
LLVM,NVPTX,526,;
LLVM,NVPTX,527,"( <STR_LIT> ) , DestReg ) <STR_LIT> <STR_LIT> BuildMI(MBB, I, DL, get(<STR_LIT>), DestReg).addReg(SrcReg, getKillRegState(KillSrc)).addReg(<STR_LIT>, getKillRegState(KillDest)) ;"
LLVM,NVPTX,528,) {
LLVM,NVPTX,529,
LLVM,NVPTX,530,. getMBB ( ) ;
LLVM,NVPTX,531,
LLVM,NVPTX,532,);
LLVM,NVPTX,533,<NUM_LIT> ) . getMBB ( ) ;
LLVM,NVPTX,534,
LLVM,NVPTX,535,", DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,NVPTX,536,;
LLVM,NVPTX,537,*Info ;
LLVM,NVPTX,538,] ) . addMBB ( TBB ) ;
LLVM,NVPTX,539,src . isReg ( ) ) ;
LLVM,NVPTX,540,getOperand ( <NUM_LIT> ) ;
LLVM,NVPTX,541,;
LLVM,NVPTX,542,return GV->hasInternalLinkage();
LLVM,NVPTX,543,Squared Instructions}
LLVM,NVPTX,544,) const override {
LLVM,NVPTX,545,) ) ;
LLVM,NVPTX,546,get_operand ( <NUM_LIT> ) ;
LLVM,NVPTX,547,"on , TL -> FMAstate );"
LLVM,NVPTX,548,") , Objs , IsKernelFn ) ;"
LLVM,NVPTX,549,ThreadLocal ( ) ;
LLVM,NVPTX,550,;
LLVM,NVPTX,551,<STR_LIT> :: PARAM ;
LLVM,NVPTX,552,
LLVM,NVPTX,553,);
LLVM,NVPTX,554,( ) ;
LLVM,NVPTX,555,MVT::i32 );
LLVM,NVPTX,556,getFilterName<PARAM>;
LLVM,NVPTX,557,: return CmpMode :: LE ;
LLVM,NVPTX,558,) ;
LLVM,NVPTX,559,) ;
LLVM,NVPTX,560,Indx );
LLVM,NVPTX,561,"Offset ,  getTargetLowering()) ;"
LLVM,NVPTX,562,"Limit , segment );"
LLVM,NVPTX,563,unsigned OffsetSize }
LLVM,NVPTX,564,STORE) return false;
LLVM,NVPTX,565,
LLVM,NVPTX,566,", segmentSize );"
LLVM,NVPTX,567,) ;
LLVM,NVPTX,568,) const {
LLVM,NVPTX,569,) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ;
LLVM,NVPTX,570,) {
LLVM,NVPTX,571,"( ), CastN -> getOperand ( <NUM_LIT> ) . getOperand ( ), CastN);"
LLVM,NVPTX,572,{
LLVM,NVPTX,573,) ;
LLVM,NVPTX,574,NodeMachineOpcode );
LLVM,NVPTX,575,);
LLVM,NVPTX,576,s getValue (0);
LLVM,NVPTX,577,( 0 ) ;
LLVM,NVPTX,578,", N->getValueType(<NUM_LIT>));"
LLVM,NVPTX,579,;
LLVM,NVPTX,580,true ;
LLVM,NVPTX,581,
LLVM,NVPTX,582,EltVT ) ;
LLVM,NVPTX,583,"getI32Imm ( toType , dl ) , getI32Imm ( toTypeWidth , dl ) , Base , Offset , Chain }"
LLVM,NVPTX,584,", Ret ) ;"
LLVM,NVPTX,585,( ) ;
LLVM,NVPTX,586,
LLVM,NVPTX,587,
LLVM,NVPTX,588,
LLVM,NVPTX,589,0;
LLVM,NVPTX,590,<STR_LIT> : ResNode = SelectCas ( N ) ;
LLVM,NVPTX,591,0 ))) {
LLVM,NVPTX,592,"SDLoc(Addr), MVT::i16 );"
LLVM,NVPTX,593,"<STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,594,<NUM_LIT> ) ;
LLVM,NVPTX,595,"( Cvt , <NUM_LIT> ) ;"
LLVM,NVPTX,596,
LLVM,NVPTX,597,
LLVM,NVPTX,598,": Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , None , <STR_LIT> , <STR_LIT> , <STR_LIT> , None ) ;"
LLVM,NVPTX,599,) return false ;
LLVM,NVPTX,600,) ;
LLVM,NVPTX,601,: ResNode = SelectStoreParam ( N ) ;
LLVM,NVPTX,602,<STR_LIT> ;
LLVM,NVPTX,603,;
LLVM,NVPTX,604,false ;
LLVM,NVPTX,605,{
LLVM,NVPTX,606,", <STR_LIT2> ) ;"
LLVM,NVPTX,607,: Opc = <STR_LIT> ;
LLVM,NVPTX,608,<STR_LIT> ;
LLVM,NVPTX,609,getFnAttribute ( FTZ > ) . getValue ( ) == true;
LLVM,NVPTX,610,ExceptionHandling ;
LLVM,NVPTX,611,.getCodeGenerationLevel() == <ISA_LIT>TargetLowering::CodeGenLevel</ISA_LIT>::Aggressive;
LLVM,NVPTX,612,& STI );
LLVM,NVPTX,613,( ) ;
LLVM,NVPTX,614,GLOBAL ;
LLVM,NVPTX,615,"( <NUM_LIT> ) , Src ) ;"
LLVM,NVPTX,616,) ;
LLVM,NVPTX,617,<STR_LIT> : Opcode = <STR_LIT> ;
LLVM,NVPTX,618,N ) ;
LLVM,NVPTX,619,;
LLVM,NVPTX,620,<ISA_GV> }
LLVM,NVPTX,621,
LLVM,NVPTX,622,) const = 0;
LLVM,NVPTX,623,( FMAContractLevel == <NUM_LIT> ) && ( Subtarget . <NUM_LIT> () || Subtarget .hasFMAF128() ) ;
LLVM,NVPTX,624,) ;
LLVM,NVPTX,625,
LLVM,NVPTX,626,
LLVM,NVPTX,627,getOperand ( ) ) ) {
LLVM,NVPTX,628,) ;
LLVM,NVPTX,629,<STR_LIT> : Opcode = <STR_LIT> ;
LLVM,NVPTX,630,: return <STR_LIT> :: LOCAL;
LLVM,NVPTX,631,;
LLVM,NVPTX,632,: Opcode = <STR_LIT> ;
LLVM,NVPTX,633,"-> allocateMemRefsArray ( MemRefs . size ( ) , Op1 . getNode ( ) ;"
LLVM,NVPTX,634,) ;
LLVM,NVPTX,635,) ? <STR_LIT> : <STR_LIT> ;
LLVM,NVPTX,636,X86::MOV64rm;
LLVM,NVPTX,637,: ResNode = SelectMatrixOperation(N);
LLVM,NVPTX,638,") , getMachine <LINE_COMMENT> ( DstVT ) , MVT :: Other , Ops );"
LLVM,NVPTX,639,ADDRESS_SPACE_SHARED : Opc = TM . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;
LLVM,NVPTX,640,MVT::Any }
LLVM,NVPTX,641,: switch ( MemVT . getSimpleVT ( ) . SimpleTy ) {
LLVM,NVPTX,642,;
LLVM,NVPTX,643,"<STR_LIT> , OpcodeIndex }"
LLVM,NVPTX,644,( HAS_CONST_VALUE * ValueConst -> getZExtValue ( ) ) ;
LLVM,NVPTX,645,: default:  break;
LLVM,NVPTX,646,;
LLVM,NVPTX,647,: Objs )
LLVM,NVPTX,648,: switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) {
LLVM,NVPTX,649,: Opcode = <STR_LIT> ;
LLVM,NVPTX,650,
LLVM,NVPTX,651,<INDIRECT_CALL> ;
LLVM,NVPTX,652,V ) {
LLVM,NVPTX,653,"Imm, MVT :: i32 );"
LLVM,NVPTX,654,"DL , MVT :: i64 );"
LLVM,NVPTX,655,"<STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,656,Kind :: Fast )
LLVM,NVPTX,657,;
LLVM,NVPTX,658,< Idx + NumElts ;
LLVM,NVPTX,659,EltVT ) ;
LLVM,NVPTX,660,
LLVM,NVPTX,661,
LLVM,NVPTX,662,;
LLVM,NVPTX,663,"Name , EVT RegisterType , SDValue & VOperand , SDValue & VExtraSteps , SDValue & VFtz , SDValue & Guard , SDValue & Sticky ) {"
LLVM,NVPTX,664,( <STR_LIT> ) ;
LLVM,NVPTX,665,( PTy -> getElementType ( ) ) ;
LLVM,NVPTX,666,!= std :: end ( specialTypes ) ;
LLVM,NVPTX,667,: default:
LLVM,NVPTX,668,: default: print(No valid case statements)
LLVM,NVPTX,669,
LLVM,NVPTX,670,"<STR_LIT> , MVT::s<NUM_LIT> , <VAL_LIT> , <NUM_LIT>, MVT::s<NUM_LIT>, <VAL_LIT>, Operand);"
LLVM,NVPTX,671,") , dl , Ops );"
LLVM,NVPTX,672,<STR_LIT> ) ;
LLVM,NVPTX,673,"MVT::i64 , Tmp3  SDValue Tmp2 = ST -> getBasePtr ( ) ;"
LLVM,NVPTX,674,Ops ;
LLVM,NVPTX,675,"E0 , E1) ;"
LLVM,NVPTX,676,{
LLVM,NVPTX,677,"return PerformADDCombineWithOperands( N, N1, N0, DCI, Subtarget, OptLevel);"
LLVM,NVPTX,678,;
LLVM,NVPTX,679,) {
LLVM,NVPTX,680,N ) {
LLVM,NVPTX,681,<NUM_LIT>  ) }
LLVM,NVPTX,682,) ) ;
LLVM,NVPTX,683,<NUM_LIT> > Results ;
LLVM,NVPTX,684,false ;
LLVM,NVPTX,685,DwarfMacroSection ) ;
LLVM,NVPTX,686,return true ;
LLVM,NVPTX,687,( VT ) ;
LLVM,NVPTX,688,;
LLVM,NVPTX,689,CalleeV ) ) {
LLVM,NVPTX,690,
LLVM,NVPTX,691,
LLVM,NVPTX,692,<NUM_LIT> * ( idx <STR_LIT>;
LLVM,NVPTX,693,"( Op , DAG ) ;"
LLVM,NVPTX,694,". getConstantFP ( pow ( <NUM_LIT>, <NUM_LIT> ) , SL , VT ) , <STR_LIT> ) ;"
LLVM,NVPTX,695,VT ) ) ;
LLVM,NVPTX,696,", <STR_LIT>, RoundedA );"
LLVM,NVPTX,697,") , SDLoc ( DL ) , getPointerTy ( $\textbf{"
LLVM,NVPTX,698,-> getMemoryVT ( ) ;
LLVM,NVPTX,699,( ) ;
LLVM,NVPTX,700,": return LowerSETCC ( Op , DAG ) ;"
LLVM,NVPTX,701,<STR_LIT> ;
LLVM,NVPTX,702,) -  <NUM_LIT> ;
LLVM,NVPTX,703,( ) ;
LLVM,NVPTX,704,;
LLVM,NVPTX,705,0 ) {
LLVM,NVPTX,706,) ;
LLVM,NVPTX,707,getSExtValue ( ) ;
LLVM,NVPTX,708,Off ) ;
LLVM,NVPTX,709,'d' : case 'e' : case 'kad' : return C_RegisterClass ;
LLVM,NVPTX,710,str ( ) ) ;
LLVM,NVPTX,711,getPointerTy ( ) ) ;
LLVM,NVPTX,712,) ;
LLVM,NVPTX,713,) -> getBitWidth ( ) ;
LLVM,NVPTX,714,"end ( specialTypes ) , TypeName ) != std :: end ( specialTypes )  STy->getName().str();"
LLVM,NVPTX,715,) . getValueType ( ) ;
LLVM,NVPTX,716,<STR_LIT> : return true ;
LLVM,NVPTX,717,"Constraint , Ops , DAG ) ;"
LLVM,NVPTX,718,i ) ;
LLVM,NVPTX,719,
LLVM,NVPTX,720,FromGVNs . changeToLoadFromClassConstants ( Op ) ;
LLVM,NVPTX,721,) ;
LLVM,NVPTX,722,"dl , MVT :: i1 , newLD , LD -> <NUM_LIT> ( ) ( ) ;"
LLVM,NVPTX,723,) ;
LLVM,NVPTX,724,"DL , VT , Select ) ;"
LLVM,NVPTX,725,
LLVM,NVPTX,726,"getConstant ( VTBits , dl , <STR_LIT> ) ) ;"
LLVM,NVPTX,727,<NUM_LIT> ) ;
LLVM,NVPTX,728,( ) ;
LLVM,NVPTX,729,) ;
LLVM,NVPTX,730,", RemainingAlign ) ;"
LLVM,NVPTX,731,
LLVM,NVPTX,732,;
LLVM,NVPTX,733,}
LLVM,NVPTX,734,"DCI , Subtarget , OptLevel ) ;"
LLVM,NVPTX,735,) -> getZExtValue ( ) ;
LLVM,NVPTX,736,!= <STR_LIT> ) {
LLVM,NVPTX,737,) ;
LLVM,NVPTX,738,( ) ;
LLVM,NVPTX,739,
LLVM,NVPTX,740,( <NUM_LIT> );
LLVM,NVPTX,741,: if ( N == -1 ) }
LLVM,NVPTX,742,
LLVM,NVPTX,743,;
LLVM,NVPTX,744,;
LLVM,NVPTX,745,( DwarfLocListsSection ) ;
LLVM,NVPTX,746,;
LLVM,NVPTX,747,"( VT . getVectorElement ( 0 ) , VT . getVectorNumElements ( ) ) ;"
LLVM,NVPTX,748,"( <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,749,LHSTy.getSizeInBits());
LLVM,NVPTX,750,;
LLVM,NVPTX,751,) ;
LLVM,NVPTX,752,return <NUM_LIT> ;
LLVM,NVPTX,753,InBits ( ETy ) ;
LLVM,NVPTX,754,) {
LLVM,NVPTX,755,
LLVM,NVPTX,756,
LLVM,NVPTX,757,) ;
LLVM,NVPTX,758,getVectorNumElements ( ) ;
LLVM,NVPTX,759,", VT ) ;"
LLVM,NVPTX,760,", DAG ) ;"
LLVM,NVPTX,761,"Op , DAG ) ;"
LLVM,NVPTX,762,( ) . getStoreSize ( ) ;
LLVM,NVPTX,763,( ) ;
LLVM,NVPTX,764,<NUM_LIT> ) ;
LLVM,NVPTX,765,"return LowerVectorSTORE ( Op , DAG ) ;"
LLVM,NVPTX,766,;
LLVM,NVPTX,767,
LLVM,NVPTX,768,<STR_LIT> ;
LLVM,NVPTX,769,outs [ OIdx ] . Flags . <NUM_LIT> ( ) << <STR_LIT> << vararg ? <STR_LIT> : <STR_LIT> ;
LLVM,NVPTX,770,( ) ) ;
LLVM,NVPTX,771,
LLVM,NVPTX,772,;
LLVM,NVPTX,773,: Op = <STR_LIT> ;
LLVM,NVPTX,774,( ) ;
LLVM,NVPTX,775,;
LLVM,NVPTX,776,The last statement of this code snippet is: SDValue SubVector = NewLD.getValue(i);
LLVM,NVPTX,777,#> {
LLVM,NVPTX,778,VT ;
LLVM,NVPTX,779,;
LLVM,NVPTX,780,? STy -> getName ( ) . str ( ) :  ;
LLVM,NVPTX,781,isType <STy> ( specialTypes [ i ] ) ) {
LLVM,NVPTX,782,true ;
LLVM,NVPTX,783,getOperand ( i ) ;
LLVM,NVPTX,784,", Op ) ;"
LLVM,NVPTX,785,", Op ) ;"
LLVM,NVPTX,786,dl ) ;
LLVM,NVPTX,787,"ShOpLo , ExtraShAmt ) ;"
LLVM,NVPTX,788,", RevShAmt ) ;"
LLVM,NVPTX,789,", FalseVal ) ;"
LLVM,NVPTX,790,", DAG . getConstant ( i , DL , <NUM_LIT> ) ) ;"
LLVM,NVPTX,791,( <NUM_LIT> ) ;
LLVM,NVPTX,792,;
LLVM,NVPTX,793,;
LLVM,NVPTX,794,"<NUM_LIT>, <NUM_LIT>, <STR_LIT>, sz, <STR_LIT>, <STR_LIT>, <STR_LIT>, ETy->getPrimitiveSizeInBits(), <STR_LIT>, ETy->getScalarSizeInBits(), <STR_LIT>, <STR_LIT>;"
LLVM,NVPTX,795,"CMPCombine ( N , DCI , STI , OptLevel ) ;"
LLVM,NVPTX,796,"EVT :: getVectorVT ( * DAG . getContext ( ) , N -> <STR_LIT> , N -> getValueType ( <STR_LIT> ) ) ;"
LLVM,NVPTX,797,- <NUM_LIT> ) ;
LLVM,NVPTX,798,alpha_rule;
LLVM,NVPTX,799,je = VT.getVectorNumElements();
LLVM,NVPTX,800,{
LLVM,NVPTX,801,) ;
LLVM,NVPTX,802,<STR_LIT> ) ;
LLVM,NVPTX,803,<STR_LIT> ;
LLVM,NVPTX,804,true ;
LLVM,NVPTX,805,
LLVM,NVPTX,806,<STR_LIT> }
LLVM,NVPTX,807,) ;
LLVM,NVPTX,808,) ) ;
LLVM,NVPTX,809,"> <NUM0_LIT> ( OtherOps . <NUM1_LIT> , <NUM1_LIT> , NewLD ) ;"
LLVM,NVPTX,810,vectors . length ( ) ) ;
LLVM,NVPTX,811,. getLength ( ) ) ;
LLVM,NVPTX,812,}
LLVM,NVPTX,813,;
LLVM,NVPTX,814,", Cmp ) ;"
LLVM,NVPTX,815,) ;
LLVM,NVPTX,816,":  return PerformSUBCombine ( N , DCI , STI , OptLevel ) ;"
LLVM,NVPTX,817,"const MCSection *TargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler &Mang, const TargetMachine &TM) const {"
LLVM,NVPTX,818,) const {
LLVM,NVPTX,819,;
LLVM,NVPTX,820,<STR_LIT> ;
LLVM,NVPTX,821,<< <STR_LIT> ;
LLVM,NVPTX,822,;
LLVM,NVPTX,823,++i ) {
LLVM,NVPTX,824,",  . getValueType ( ) , <NUM_LIT> , <BINARY_OP>) ;"
LLVM,NVPTX,825,isIntegerTy ( i ) ) {
LLVM,NVPTX,826,if (NumElts == 1) {
LLVM,NVPTX,827,) ;
LLVM,NVPTX,828,"Op , DAG s );"
LLVM,NVPTX,829,& s ) ;
LLVM,NVPTX,830,:: ReadMem ;
LLVM,NVPTX,831,true ;
LLVM,NVPTX,832,<STR_LIT> : case ISD :: ADD : DCI . AddToWorklist ( N1 . getNode ( ) ) ;
LLVM,NVPTX,833,;
LLVM,NVPTX,834,context = <STR_LIT> ;
LLVM,NVPTX,835,j != je ;
LLVM,NVPTX,836,<NUM_LIT> ) ;
LLVM,NVPTX,837,new LD . getNode ( ) ) ;
LLVM,NVPTX,838,( ) ;
LLVM,NVPTX,839,"ABITypeAlign, offset);"
LLVM,NVPTX,840,. ISize << <STR_LIT> ;
LLVM,NVPTX,841,( I ) ;
LLVM,NVPTX,842,) ;
LLVM,NVPTX,843,) ;
LLVM,NVPTX,844,DwarfRangesSection ;
LLVM,NVPTX,845,: return AtomicExpansionKind :: Add ;
LLVM,NVPTX,846,getTypeAllocSize ( ETy ) ;
LLVM,NVPTX,847,return true;
LLVM,NVPTX,848,) return false ;
LLVM,NVPTX,849,"<NUM_LIT> * j , dl ) ) ;"
LLVM,NVPTX,850,: case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :  {
LLVM,NVPTX,851,;
LLVM,NVPTX,852,) ;
LLVM,NVPTX,853,;
LLVM,NVPTX,854,;
LLVM,NVPTX,855,LD->getValueType(0) == MVT::i32 && newLD);
LLVM,NVPTX,856,", LD -> isReadnone ( ) ) ;"
LLVM,NVPTX,857,NewSt ;
LLVM,NVPTX,858,: Opcode = <STR_LIT> ;
LLVM,NVPTX,859,Res ) ;
LLVM,NVPTX,860,": return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,NVPTX,861,: return <STR_LIT> default: return <STR_LIT>;
LLVM,NVPTX,862,<STR_LIT> : return <STR_LIT> ;
LLVM,NVPTX,863,: Info . opcode = <STR_LIT> ;
LLVM,NVPTX,864,: default:
LLVM,NVPTX,865,( p );
LLVM,NVPTX,866,( ) ) ;
LLVM,NVPTX,867,);
LLVM,NVPTX,868,
LLVM,NVPTX,869,== <STR_LIT> ) ? MVT::i8 : MVT::i16;
LLVM,NVPTX,870,sz << <STR_LIT> ;
LLVM,NVPTX,871,;
LLVM,NVPTX,872,. Flags . getByValAlign ( ) ;
LLVM,NVPTX,873,<STR_LIT> );
LLVM,NVPTX,874,( ) ;
LLVM,NVPTX,875,) ;
LLVM,NVPTX,876,( Res ) ;
LLVM,NVPTX,877,{
LLVM,NVPTX,878,( <NUM_LIT> < ELT_LIT > ) ;
LLVM,NVPTX,879,( ) ) ;
LLVM,NVPTX,880,", & <STR_LIT> ) ;"
LLVM,NVPTX,881,Ops ) ;
LLVM,NVPTX,882,;
LLVM,NVPTX,883,"<STR_LIT> , MVT :: <STR_LIT> ,"
LLVM,NVPTX,884,;
LLVM,NVPTX,885,( ) ;
LLVM,NVPTX,886,PointerOperand) ;
LLVM,NVPTX,887,", Ops . size ( ) , MemSD -> getMemoryVT ( ) , MemSD -> getMemOperand ( ) ) ;"
LLVM,NVPTX,888,"<STR_LIT> , Res ) ;"
LLVM,NVPTX,889,( ETy ) ;
LLVM,NVPTX,890,) ;
LLVM,NVPTX,891,"<STR_LIT> , Legal ) ;"
LLVM,NVPTX,892,;
LLVM,NVPTX,893,
LLVM,NVPTX,894,
LLVM,NVPTX,895,c_str ( ) ) ;
LLVM,NVPTX,896,char);
LLVM,NVPTX,897,) const {
LLVM,NVPTX,898,;
LLVM,NVPTX,899,
LLVM,NVPTX,900,);
LLVM,NVPTX,901,{
LLVM,NVPTX,902,{
LLVM,NVPTX,903,
LLVM,NVPTX,904,==  NUM_LIT ;
LLVM,NVPTX,905,<STR_LIT> DstAS ) ;
LLVM,NVPTX,906,", TypeOfCopyLen ) , LoopBB , nextBB ) ;"
LLVM,NVPTX,907,MI : MemCalls ) {
LLVM,NVPTX,908,( IntrCall ) ;
LLVM,NVPTX,909,Memset ) ;
LLVM,NVPTX,910,
LLVM,NVPTX,911,) const =0;
LLVM,NVPTX,912,i ] ;
LLVM,NVPTX,913,"CreateGEP ( arrayWrite , ArrayRef < Value * > ( ind ) ) ) ;"
LLVM,NVPTX,914,) >= MaxAggrCopySize ) {
LLVM,NVPTX,915,getAddressSpace ( ) ;
LLVM,NVPTX,916,"len -> getType ( ) , <NUM_LIT> ) ) ;"
LLVM,NVPTX,917,
LLVM,NVPTX,918,( <NUM_LIT> );
LLVM,NVPTX,919,) {
LLVM,NVPTX,920,
LLVM,NVPTX,921,"Memmove , TTI ) ;"
LLVM,NVPTX,922,;
LLVM,NVPTX,923,
LLVM,NVPTX,924,", loopBB );"
LLVM,NVPTX,925,<NUM_LIT> ) ;
LLVM,NVPTX,926,
LLVM,NVPTX,927,
LLVM,NVPTX,928,DeprecatedPass;
LLVM,NVPTX,929,( MemCall ) ) {
LLVM,NVPTX,930,MemCall ) ) {
LLVM,NVPTX,931,;
LLVM,NVPTX,932,
LLVM,NVPTX,933,
LLVM,NVPTX,934,MaxFunctionOutlineFansPass :: createMaxFunctionOutlineFansPass (int maxFans)
LLVM,NVPTX,935,NewASCToGeneric ) ;
LLVM,NVPTX,936,. getUser ( ) ) ;
LLVM,NVPTX,937,BI && BI -> getOperand (NumLlit) == allocaInst ) {
LLVM,NVPTX,938,;
LLVM,NVPTX,939,;
LLVM,NVPTX,940,"Ptr -> getName ( ) , & * InsertPt ) ;"
LLVM,NVPTX,941,isPointerTy( ) ) {
LLVM,NVPTX,942,", false ) ;"
LLVM,NVPTX,943,
LLVM,NVPTX,944,"-> getName ( ) , false , Inst ) ;"
LLVM,NVPTX,945,
LLVM,NVPTX,946,;
LLVM,NVPTX,947,const_cast < Instruction * > ( & * Arg )) ;
LLVM,NVPTX,948,getPrefTypeAlignment ( StructType ) ) ) ;
LLVM,NVPTX,949,( ) ) {
LLVM,NVPTX,950,;
LLVM,NVPTX,951,"Arg->getName() , FirstInst ) ;"
LLVM,NVPTX,952,) ;
LLVM,NVPTX,953,getAllocaAddrSpace ( ) ;
LLVM,NVPTX,954,I ) ) {
LLVM,NVPTX,955,
LLVM,NVPTX,956,) ;
LLVM,NVPTX,957,( ) ) {
LLVM,NVPTX,958,;
LLVM,NVPTX,959,( ArgInGeneric ) ;
LLVM,NVPTX,960,<&>;
LLVM,NVPTX,961,The last statement should be: InsertPtr = InsertPt->getParent()->getContext()->getInstrucitonIteratorInsertPt(InsertPt);
LLVM,NVPTX,962,ptr);
LLVM,NVPTX,963,"getName ( ) , ( <NUM_LIT> ) ;"
LLVM,NVPTX,964,) ;
LLVM,NVPTX,965,void) {
LLVM,NVPTX,966,
LLVM,NVPTX,967,"BitcastArgs , <STR_LIT>, <NUM_LIT>) ;"
LLVM,NVPTX,968,;
LLVM,NVPTX,969,) {
LLVM,NVPTX,970,1 ;
LLVM,NVPTX,971,nullptr ;
LLVM,NVPTX,972,;
LLVM,NVPTX,973,SectionName.endswith(-ext);
LLVM,NVPTX,974,
LLVM,NVPTX,975,nullptr ;
LLVM,NVPTX,976,;
LLVM,NVPTX,977,false;
LLVM,NVPTX,978,;
LLVM,NVPTX,979,;
LLVM,NVPTX,980,<STR_LIT> ;
LLVM,NVPTX,981,false ;
LLVM,NVPTX,982,<STR_LIT> ;
LLVM,NVPTX,983,;
LLVM,NVPTX,984,ZeroDirective = <STR_LIT> ;
LLVM,NVPTX,985,<STR_LIT> ;
LLVM,NVPTX,986,null ;
LLVM,NVPTX,987,<STR_LIT> ;
LLVM,NVPTX,988,;
LLVM,NVPTX,989,false ;
LLVM,NVPTX,990,<STR_LIT> ;
LLVM,NVPTX,991,{
LLVM,NVPTX,992,Op );
LLVM,NVPTX,993,RW);
LLVM,NVPTX,994,false ;
LLVM,NVPTX,995,kind_;
LLVM,NVPTX,996,) ;
LLVM,NVPTX,997,"GenericMCSymbolRefExpr::VK_<Storage class>_ref, Ctx)</ISA_LIT>>> return new GenericMCSymbolRefExpr(Ctx);"
LLVM,NVPTX,998,"VC , {"
LLVM,NVPTX,999,{
LLVM,NVPTX,1000,* MAI ) const {
LLVM,NVPTX,1001,getAssociatedSection ( ) ;
LLVM,NVPTX,1002,"</ISA_LIT> FloatMCExpr  :: create (VariantKind Kind, APFloat Flt, MCContext * Ctx) const {"
LLVM,NVPTX,1003,getZExtValue ( ) ) ;
LLVM,NVPTX,1004,
LLVM,NVPTX,1005,);
LLVM,NVPTX,1006,;
LLVM,NVPTX,1007,getZExtValue ( ) ) ;
LLVM,NVPTX,1008,
LLVM,NVPTX,1009,MRI ) ;
LLVM,NVPTX,1010,;
LLVM,NVPTX,1011,
LLVM,NVPTX,1012,", FS );"
LLVM,NVPTX,1013,", FS );"
LLVM,NVPTX,1014,{
LLVM,NVPTX,1015,"& OS , MCInstPrinter * IP , MCCodeEmitter * CE , const MCSubtargetInfo & STI ) ;"
LLVM,NVPTX,1016,
LLVM,NVPTX,1017,", FS );"
LLVM,NVPTX,1018,) ;
LLVM,NVPTX,1019,Y ) ;
LLVM,NVPTX,1020,":: Level OL , bool JIT ) {"
LLVM,NVPTX,1021,create<ISA_LIT>MCSubtargetInfo ) ;
LLVM,NVPTX,1022,X ;
LLVM,NVPTX,1023,"CM ,< ISA_LIT > , OL ) ;"
LLVM,NVPTX,1024,"MII , MRI , STI ) ;"
LLVM,NVPTX,1025,"OL, CodeGenOpt :: Level OL, TargetOptions ==> >) {"
LLVM,NVPTX,1026,"TargetRegistry::RegisterMCSubtargetInfo(The<ISA_LIT>Target32, create<ISA_LIT>MCSubtargetInfo);"
LLVM,NVPTX,1027,(ISA_LIT) MCInstrInfo();
LLVM,NVPTX,1028,;
LLVM,NVPTX,1029,", StringRef CPU, StringRef FS) {"
LLVM,NVPTX,1030,) ;
LLVM,NVPTX,1031,) ;
LLVM,NVPTX,1032,.addReg(MRI->createVirtualRegister(RegClass));
LLVM,NVPTX,1033,( ) ;
LLVM,NVPTX,1034,() {
LLVM,NVPTX,1035,{
LLVM,NVPTX,1036,false ;
LLVM,NVPTX,1037,) ;
LLVM,NVPTX,1038,) ;
LLVM,NVPTX,1039,( );
LLVM,NVPTX,1040,) ;
LLVM,NVPTX,1041,
LLVM,NVPTX,1042,) ;
LLVM,NVPTX,1043,.addReg(NRI->getFrameLocalRegister(MF)).add(Prev.getOperand(1));
LLVM,NVPTX,1044,const {
LLVM,NVPTX,1045,AU ) ;
LLVM,NVPTX,1046,;
LLVM,NVPTX,1047,( ));
LLVM,NVPTX,1048,
LLVM,NVPTX,1049,;
LLVM,NVPTX,1050,) ;
LLVM,NVPTX,1051,getPrefStackAlignment ( ) ;
LLVM,NVPTX,1052,{
LLVM,NVPTX,1053,I ;
LLVM,NVPTX,1054,<STR_LIT> << Offset << <STR_LIT> ) ;
LLVM,NVPTX,1055,<NUM_LIT> ( FrameIdx ) * MFI . <NUM_LIT> * MFI . <NUM_LIT> <STR_LIT> }
LLVM,NVPTX,1056,i != e ;
LLVM,NVPTX,1057,true ;
LLVM,NVPTX,1058,}
LLVM,NVPTX,1059,Align % Align;
LLVM,NVPTX,1060,= MFI . getStackAlignment ( ) ;
LLVM,NVPTX,1061,;
LLVM,NVPTX,1062,align= << Alignment << \n ) ;
LLVM,NVPTX,1063,"( DIETYPE , DIExpr ) ;"
LLVM,NVPTX,1064,"i , SPAdj , 0 ) ;"
LLVM,NVPTX,1065,
LLVM,NVPTX,1066,( ) ;
LLVM,NVPTX,1067,. isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI -> getOperand ( i ) . getReg ( ) ) ) continue ;
LLVM,NVPTX,1068,_or ( MaxAlign ) ;
LLVM,NVPTX,1069,
LLVM,NVPTX,1070,. getMaxCallFrameSize ( ) ;
LLVM,NVPTX,1071,) ;
LLVM,NVPTX,1072,) ;
LLVM,NVPTX,1073,( ) == From . getReg ( ) ) {
LLVM,NVPTX,1074,) {
LLVM,NVPTX,1075,: llvm_unreachable ( Unimplemented instruction ) ;
LLVM,NVPTX,1076,
LLVM,NVPTX,1077,return getStringData();
LLVM,NVPTX,1078,);
LLVM,NVPTX,1079,) ;
LLVM,NVPTX,1080,;
LLVM,NVPTX,1081,;
LLVM,NVPTX,1082,;
LLVM,NVPTX,1083,;
LLVM,NVPTX,1084,;
LLVM,NVPTX,1085,;
LLVM,NVPTX,1086,;
LLVM,NVPTX,1087,true ;
LLVM,NVPTX,1088,{
LLVM,NVPTX,1089,) ;
LLVM,NVPTX,1090,{
LLVM,NVPTX,1091,getUInt(EH_MMNs->at(RegNum * ( ( isEH ? ? 8 : 4 ) <<  3 ) + 8 ));
LLVM,NVPTX,1092,<STR_LIT> ;
LLVM,NVPTX,1093,;
LLVM,NVPTX,1094,
LLVM,NVPTX,1095,"EBP, CR2 }"
LLVM,NVPTX,1096,ARM::SP;
LLVM,NVPTX,1097,== &No response) {
LLVM,NVPTX,1098,<STR_LIT> ;
LLVM,NVPTX,1099,;
LLVM,NVPTX,1100,) . <STR_LIT> = <NUM_LIT> ;
LLVM,NVPTX,1101,<STR_LIT> );
LLVM,NVPTX,1102,);
LLVM,NVPTX,1103,get<ISA_LIT>RegClassName ( & <STR_LIT> ) ;
LLVM,NVPTX,1104,<STR_LIT> ;
LLVM,NVPTX,1105,) return true ;
LLVM,NVPTX,1106,;
LLVM,NVPTX,1107,= {
LLVM,NVPTX,1108,<STR_LIT> ;
LLVM,NVPTX,1109,amd64: <STR_LIT>x86  TargetMachine &> ( MF .getTarget ( ) );
LLVM,NVPTX,1110,) return <STR_LIT> ;
LLVM,NVPTX,1111,<STR_LIT> ;
LLVM,NVPTX,1112,;
LLVM,NVPTX,1113,const;
LLVM,NVPTX,1114,( + TargetTransformInfoWrapperPass::PassName + );
LLVM,NVPTX,1115,<STR_LIT> : case <STR_LIT> : {
LLVM,NVPTX,1116,) ;
LLVM,NVPTX,1117,;
LLVM,NVPTX,1118,<STR_LIT> ;
LLVM,NVPTX,1119,<b>Changed;
LLVM,NVPTX,1120,) ;
LLVM,NVPTX,1121,Crypto @ Home;
LLVM,NVPTX,1122,) {
LLVM,NVPTX,1123,
LLVM,NVPTX,1124,;
LLVM,NVPTX,1125,operandIndex){
LLVM,NVPTX,1126,) != ~ 0U ) {
LLVM,NVPTX,1127,I ;
LLVM,NVPTX,1128,;
LLVM,NVPTX,1129,;
LLVM,NVPTX,1130,"double functname, const&functname);"
LLVM,NVPTX,1131,labelBeginName ;
LLVM,NVPTX,1132,() const {
LLVM,NVPTX,1133,;
LLVM,NVPTX,1134,
LLVM,NVPTX,1135,AU.addPreserved<MachineFunctionAnalysis>();
LLVM,NVPTX,1136,();
LLVM,NVPTX,1137,{
LLVM,NVPTX,1138,i ] ;
LLVM,NVPTX,1139,
LLVM,NVPTX,1140,
LLVM,NVPTX,1141,;
LLVM,NVPTX,1142,override {
LLVM,NVPTX,1143,"The last statement is likely to be a return statement, such as return ptxVersion;"
LLVM,NVPTX,1144,<ISA_LIT> {
LLVM,NVPTX,1145,;
LLVM,NVPTX,1146,;
LLVM,NVPTX,1147,;
LLVM,NVPTX,1148,{
LLVM,NVPTX,1149,1.5 ? Unsupported : $Information: Version {
LLVM,NVPTX,1150,? SmVersion : SmVersion + 1
LLVM,NVPTX,1151,return SmVersionControl;
LLVM,NVPTX,1152,
LLVM,NVPTX,1153,
LLVM,NVPTX,1154,new Version (2.0);
LLVM,NVPTX,1155,
LLVM,NVPTX,1156,;
LLVM,NVPTX,1157,
LLVM,NVPTX,1158,noexcept override = 0;
LLVM,NVPTX,1159,
LLVM,NVPTX,1160,;
LLVM,NVPTX,1161,1 && FMAF64Features;
LLVM,NVPTX,1162,1;
LLVM,NVPTX,1163,Instruction() {
LLVM,NVPTX,1164,;
LLVM,NVPTX,1165,Req . OK ) ;
LLVM,NVPTX,1166,
LLVM,NVPTX,1167,string str){
LLVM,NVPTX,1168,
LLVM,NVPTX,1169,HIWORD ( SM_SOCKET_PROTOCOL_22 ) ) );
LLVM,NVPTX,1170,{
LLVM,NVPTX,1171,WDDM_2_1;
LLVM,NVPTX,1172,;
LLVM,NVPTX,1173,( <DOUBLE_NUM_LIT> ) ) );
LLVM,NVPTX,1174,SWROT_NONE ) ) }
LLVM,NVPTX,1175,int count) {
LLVM,NVPTX,1176,{
LLVM,NVPTX,1177,p ) ;
LLVM,NVPTX,1178,<STR_LIT> <STR_LIT> ;
LLVM,NVPTX,1179,&& m_hasROT32 ;
LLVM,NVPTX,1180,
LLVM,NVPTX,1181,;
LLVM,NVPTX,1182,<NUM_LIT> }
LLVM,NVPTX,1183,this;
LLVM,NVPTX,1184,amp;
LLVM,NVPTX,1185,;
LLVM,NVPTX,1186,{
LLVM,NVPTX,1187,2.<___>;
LLVM,NVPTX,1188,}
LLVM,NVPTX,1189,
LLVM,NVPTX,1190,100;
LLVM,NVPTX,1191,PTXVersion ;
LLVM,NVPTX,1192,) {
LLVM,NVPTX,1193,"9.2.0 ?  Yes, the provided SmVersion is equal to or greater than 9.2.0. : No, the provided SmVersion is less than 9.2.0.;"
LLVM,NVPTX,1194,;
LLVM,NVPTX,1195,DataLayout;
LLVM,NVPTX,1196,;
LLVM,NVPTX,1197,const {
LLVM,NVPTX,1198,;
LLVM,NVPTX,1199,
LLVM,NVPTX,1200,
LLVM,NVPTX,1201,
LLVM,NVPTX,1202,
LLVM,NVPTX,1203,));
LLVM,NVPTX,1204,<STR_LIT> ) ;
LLVM,NVPTX,1205,) ) ;
LLVM,NVPTX,1206,: to the list of passes to be added.
LLVM,NVPTX,1207,( ) ) ;
LLVM,NVPTX,1208,) ;
LLVM,NVPTX,1209,::None ) addPass(createMipsOptimizePICCallPass());
LLVM,NVPTX,1210,( ) ) ;
LLVM,NVPTX,1211,);
LLVM,NVPTX,1212,
LLVM,NVPTX,1213,) ;
LLVM,NVPTX,1214,"& PMB , legacy :: PassManagerBase & PM )"
LLVM,NVPTX,1215,{
LLVM,NVPTX,1216,Val ;
LLVM,NVPTX,1217,+= <STR_LIT> ;
LLVM,NVPTX,1218,", PM );"
LLVM,NVPTX,1219,const Function &F) const {
LLVM,NVPTX,1220,_CompilerInstruction {
LLVM,NVPTX,1221,
LLVM,NVPTX,1222,;
LLVM,NVPTX,1223,assert ( !RegAllocPass && <STR_LIT>);
LLVM,NVPTX,1224,false ) ;
LLVM,NVPTX,1225,
LLVM,NVPTX,1226,Impl();
LLVM,NVPTX,1227,</ISA_LIT> );
LLVM,NVPTX,1228,by providing a value for ISA_LIT:
LLVM,NVPTX,1229,PR ) ;
LLVM,NVPTX,1230,) ;
LLVM,NVPTX,1231,", FS , Options , RM , CM , OL ) {"
LLVM,NVPTX,1232,Info;
LLVM,NVPTX,1233,Type t) {
LLVM,NVPTX,1234,Machine (  This is a function that checks if a machine is 64-bit or not. ) }
LLVM,NVPTX,1235,) ;
LLVM,NVPTX,1236,) ;
LLVM,NVPTX,1237,) ) ;
LLVM,NVPTX,1238,) ) ;
LLVM,NVPTX,1239,CodeGenOpt :: None ) addPass ( create<ISA_LIT>MachineSchedulerPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;
LLVM,NVPTX,1240,;
LLVM,NVPTX,1241,PM.add(createNVVMReflectPass());
LLVM,NVPTX,1242,initialize<ISA_LIT>Pass ( PR );
LLVM,NVPTX,1243,", Reloc :: Model ,  CM , OL ),  RM(Reloc::PIC_),  CM(OL == CodeGenOpt::Default ? CodeModel::Tiny : CodeModel::Small) {"
LLVM,NVPTX,1244,
LLVM,NVPTX,1245,;
LLVM,NVPTX,1246,> {
LLVM,NVPTX,1247,false ;
LLVM,NVPTX,1248,m_DesktopLayout;
LLVM,NVPTX,1249,;
LLVM,NVPTX,1250,InstrInfo;
LLVM,NVPTX,1251,this );
LLVM,NVPTX,1252,ADDRESS_SPACE_HOST ) ;
LLVM,NVPTX,1253,
LLVM,NVPTX,1254,;
LLVM,NVPTX,1255,;
LLVM,NVPTX,1256,Subtarget;
LLVM,NVPTX,1257,
LLVM,NVPTX,1258,vectorTargetTransformInfo;
LLVM,NVPTX,1259,) ) ;
LLVM,NVPTX,1260,) ;
LLVM,NVPTX,1261,PM.add(createNVVMDebugPass());
LLVM,NVPTX,1262,;
LLVM,NVPTX,1263,PM );
LLVM,NVPTX,1264,
LLVM,NVPTX,1265,{
LLVM,NVPTX,1266,mUseShortPointers ;
LLVM,NVPTX,1267,64-bit ;
LLVM,NVPTX,1268,;
LLVM,NVPTX,1269,mom = null ) {
LLVM,NVPTX,1270,) ;
LLVM,NVPTX,1271,) ;
LLVM,NVPTX,1272,getPassRegistry ( ) ) ;
LLVM,NVPTX,1273,
LLVM,NVPTX,1274,> is64bit ) {
LLVM,NVPTX,1275,
LLVM,NVPTX,1276,());
LLVM,NVPTX,1277,);
LLVM,NVPTX,1278,
LLVM,NVPTX,1279,( ) ) ;
LLVM,NVPTX,1280,( ) );
LLVM,NVPTX,1281,
LLVM,NVPTX,1282,( ) ) ;
LLVM,NVPTX,1283,
LLVM,NVPTX,1284,) addPass ( createSplitVectorPass ( ) ) ;
LLVM,NVPTX,1285,{
LLVM,NVPTX,1286,
LLVM,NVPTX,1287,maximizeMacrofusion should always be true for ARM );
LLVM,NVPTX,1288,Invalid object file format!);
LLVM,NVPTX,1289,"< - Initializing tasks with driver interface DriverInterface(DrvInterface, TLOF) , SP < - 2 , WIN < - true {"
LLVM,NVPTX,1290,) ) ;
LLVM,NVPTX,1291,<STR_LIT>;
LLVM,NVPTX,1292,"CM , OL ) , DataLayout ( T . createDataLayout ( ... ) ) {"
LLVM,NVPTX,1293,"( T , TT , CPU , FS , *this ) {"
LLVM,NVPTX,1294,) ;
LLVM,NVPTX,1295,) ;
LLVM,NVPTX,1296,) );
LLVM,NVPTX,1297,) }
LLVM,NVPTX,1298,;
LLVM,NVPTX,1299,( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,NVPTX,1300,) ;
LLVM,NVPTX,1301,<ISA_LIT> != NULL) {
LLVM,NVPTX,1302,;
LLVM,NVPTX,1303,;
LLVM,NVPTX,1304,> ( ) ) {
LLVM,NVPTX,1305,false ;
LLVM,NVPTX,1306,) ;
LLVM,NVPTX,1307,
LLVM,NVPTX,1308,disablePass ( & DebugInfoVerifierID ) ;
LLVM,NVPTX,1309,", bool Fast=False);"
LLVM,NVPTX,1310,{
LLVM,NVPTX,1311,() const {
LLVM,NVPTX,1312,}
LLVM,NVPTX,1313,
LLVM,NVPTX,1314,) ;
LLVM,NVPTX,1315,getPassRegistry ( ) ) ;
LLVM,NVPTX,1316,getPassRegistry ( ) ) ;
LLVM,NVPTX,1317,
LLVM,NVPTX,1318,getInternalPointer() ;
LLVM,NVPTX,1319,) ;
LLVM,NVPTX,1320,
LLVM,NVPTX,1321,addPass ( create<ISA_LIT>CodeGenPreparePass ( ) ) ;
LLVM,NVPTX,1322,{
LLVM,NVPTX,1323,:: Win32 )
LLVM,NVPTX,1324,) ) ;
LLVM,NVPTX,1325,( ) ) ;
LLVM,NVPTX,1326,) ) ;
LLVM,NVPTX,1327,) ;
LLVM,NVPTX,1328,) ;
LLVM,NVPTX,1329,) ;
LLVM,NVPTX,1330,( ) ) ) ;
LLVM,NVPTX,1331,PassRegistry::getPassRegistry ( ) ;
LLVM,NVPTX,1332,) ;
LLVM,NVPTX,1333,:: None ) addPass( create<ISA_LIT>InferAddressSpacesPass() );
LLVM,NVPTX,1334,PR ) ;
LLVM,NVPTX,1335,( ) ) ;
LLVM,NVPTX,1336,) ;
LLVM,NVPTX,1337,initializeInstCombinePass(PR);
LLVM,NVPTX,1338,) ) ;
LLVM,NVPTX,1339,CodeGenOpt :: None ) {
LLVM,NVPTX,1340,}
LLVM,NVPTX,1341,
LLVM,NVPTX,1342,==  nullptr ;
LLVM,NVPTX,1343,== &amp;
LLVM,NVPTX,1344,( ) ;
LLVM,NVPTX,1345,getInstrInfo ( ) ;
LLVM,NVPTX,1346,
LLVM,NVPTX,1347,;
LLVM,NVPTX,1348,- > getSystem( ) <ISA_LIT>;
LLVM,NVPTX,1349,) ;
LLVM,NVPTX,1350,"Mang , const TargetMachine & TM ) {"
LLVM,NVPTX,1351,getMetadata ( ) ) ;
LLVM,NVPTX,1352,getMetadata ( ) ) ;
LLVM,NVPTX,1353,nullptr ;
LLVM,NVPTX,1354,MCSection::get (GO->getSection());
LLVM,NVPTX,1355,;
LLVM,NVPTX,1356,;
LLVM,NVPTX,1357,{
LLVM,NVPTX,1358,
LLVM,NVPTX,1359,getMetadata ( ) ) ;
LLVM,NVPTX,1360,nullptr ;
LLVM,NVPTX,1361,<NUM_LIT> ;
LLVM,NVPTX,1362,;
LLVM,NVPTX,1363,:: getMetadata ( ) ) ;
LLVM,NVPTX,1364,getMetadata ( ) ) ;
LLVM,NVPTX,1365,;
LLVM,NVPTX,1366,;
LLVM,NVPTX,1367,SectionKind :: getMetadata ( ) ) ;
LLVM,NVPTX,1368,
LLVM,NVPTX,1369,include(MCSection.h);
LLVM,NVPTX,1370,;
LLVM,NVPTX,1371,( ) ) ;
LLVM,NVPTX,1372,) ;
LLVM,NVPTX,1373,;
LLVM,NVPTX,1374,false;
LLVM,NVPTX,1375,;
LLVM,NVPTX,1376,) {
LLVM,NVPTX,1377,", .text);"
LLVM,NVPTX,1378,S );
LLVM,NVPTX,1379,( S );
LLVM,NVPTX,1380,Str ) ;
LLVM,NVPTX,1381,;
LLVM,NVPTX,1382,<ISA_LIT> ELFStreamer <ISA_LIT> true <ISA_LIT> }
LLVM,NVPTX,1383,It << < <CHAR_LIT> ;
LLVM,NVPTX,1384,++ <NUM_LIT> ) {
LLVM,NVPTX,1385,
LLVM,NVPTX,1386,) ;
LLVM,NVPTX,1387,const {
LLVM,NVPTX,1388,override {
LLVM,NVPTX,1389,this == &Itanium_Sign_NVPTX ? &NVPTX_TLI : <ISA_LIT>I</ISA_LIT> ;
LLVM,NVPTX,1390,<ISA_LIT>Tli;
LLVM,NVPTX,1391,"SE , UP );"
LLVM,NVPTX,1392,
LLVM,NVPTX,1393,{
LLVM,NVPTX,1394,45);
LLVM,NVPTX,1395,ChainSizeInBytes ;
LLVM,NVPTX,1396,", AddrSpace ) ;"
LLVM,NVPTX,1397,
LLVM,NVPTX,1398,
LLVM,NVPTX,1399,", params );"
LLVM,NVPTX,1400,{
LLVM,NVPTX,1401,* 8 );
LLVM,NVPTX,1402,
LLVM,NVPTX,1403,2 ;
LLVM,NVPTX,1404,", FTZ_Any }"
LLVM,NVPTX,1405,
LLVM,NVPTX,1406,", uint64_t & laneId ) {"
LLVM,NVPTX,1407,": return <STR_LIT> Opd1Info , Opd2Info , true find a suitable cost and return it. ISD_FMul: return (Opd1Info + Opd2Info) * 2;"
LLVM,NVPTX,1408,<STR_LIT> : case <STR_LIT> : return (Ty == MVT::i32) ? <STR_LIT> : <STR_LIT>;
LLVM,NVPTX,1409,{
LLVM,NVPTX,1410,;
LLVM,NVPTX,1411,TargetLowering * TLI ) ;
LLVM,NVPTX,1412,*TM );
LLVM,NVPTX,1413,AU );
LLVM,NVPTX,1414,": case TargetOpcode::G_ADD:  case TargetOpcode::G_AND:  case TargetOpcode::G_MUL:  case TargetOpcode::G_OR:  case TargetOpcode::G_SDIV:  case TargetOpcode::G_SREM: return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);"
LLVM,NVPTX,1415,;
LLVM,NVPTX,1416,;
LLVM,NVPTX,1417,
LLVM,NVPTX,1418,true ;
LLVM,NVPTX,1419,;
LLVM,NVPTX,1420,None;
LLVM,NVPTX,1421,
LLVM,NVPTX,1422,VectorType * VT);
LLVM,NVPTX,1423,"? (256,992) : (512,992) : (233,992);"
LLVM,NVPTX,1424,;
LLVM,NVPTX,1425,= 0 ;
LLVM,NVPTX,1426,ChainSizeInBytes ;
LLVM,NVPTX,1427,", AddrSpace ) ;"
LLVM,NVPTX,1428,<STR_LIT> : return true ;
LLVM,NVPTX,1429,len = <NUM_LIT>;
LLVM,NVPTX,1430,a ;
LLVM,NVPTX,1431,"( * annotationCache ) [ m ] . insert ( make_pair ( gv , getAnnotation ( m , gv ) ) ) ;"
LLVM,NVPTX,1432,prop ] ;
LLVM,NVPTX,1433,;
LLVM,NVPTX,1434,
LLVM,NVPTX,1435,) ;
LLVM,NVPTX,1436,<and returns the first visible and non-volatile variable name and value pair;
LLVM,NVPTX,1437,& x );
LLVM,NVPTX,1438,);
LLVM,NVPTX,1439,iint idx ) {
LLVM,NVPTX,1440,StringRef ( val . name ( ) ) . startswith ( sampler ) );
LLVM,NVPTX,1441,) ) ;
LLVM,NVPTX,1442,) ;
LLVM,NVPTX,1443,"begin() , val . end() );"
LLVM,NVPTX,1444,.val == VK_IMAGE_TYPE_1D;
LLVM,NVPTX,1445,
LLVM,NVPTX,1446,<STR_LIT>;
LLVM,NVPTX,1447,& val ) ) {
LLVM,NVPTX,1448,;
LLVM,NVPTX,1449,> found ;
LLVM,NVPTX,1450,const NVPTXOperand *> ops ;
LLVM,NVPTX,1451,annot ) ) return true;
LLVM,NVPTX,1452,) continue ;
LLVM,NVPTX,1453,
LLVM,NVPTX,1454,= & * it;
LLVM,NVPTX,1455,] . end ( ) ) {
LLVM,NVPTX,1456,gv ] [ prop ] ;
LLVM,NVPTX,1457,) {
LLVM,NVPTX,1458,.NVVMAnnotation);
LLVM,NVPTX,1459,));
LLVM,NVPTX,1460,llvm :: getNVVMPropertyEnum ( NVVM :: Kernel ))));
LLVM,NVPTX,1461,
LLVM,NVPTX,1462,nullptr ;
LLVM,NVPTX,1463,PropertyAttribute :: NoDuplicate ] ) != nullptr ) ;
LLVM,NVPTX,1464,"], & x ) );"
LLVM,NVPTX,1465,"llvm :: NVVMProp :: ReqNTIDy ], y )) ;"
LLVM,NVPTX,1466,"llvm :: ReqNTIDz ], <[z]>));"
LLVM,NVPTX,1467,"ReqGarpNoThreadsX ] , z ) != 0 );"
LLVM,NVPTX,1468,) {
LLVM,NVPTX,1469,{
LLVM,NVPTX,1470,;
LLVM,NVPTX,1471,false ;
LLVM,NVPTX,1472,Unexpected value for surface property !  ) ;
LLVM,NVPTX,1473,false ;
LLVM,NVPTX,1474,tmp1) ;
LLVM,NVPTX,1475,:: move ( tmp1 ) }
LLVM,NVPTX,1476,
LLVM,NVPTX,1477,elem) ;
LLVM,NVPTX,1478,retval.clear();
LLVM,NVPTX,1479,;
LLVM,NVPTX,1480,;
LLVM,NVPTX,1481,{
LLVM,NVPTX,1482,( ) ;
LLVM,NVPTX,1483,) ;
LLVM,NVPTX,1484,= tmp ;
LLVM,NVPTX,1485,false ;
LLVM,NVPTX,1486,( * annotationCache ) [ m ] [ gv ] . end ( ) ) {
LLVM,NVPTX,1487,annotationCache ) [ m ] [ gv ] . end ( ) ) {
LLVM,NVPTX,1488,retval;
LLVM,NVPTX,1489,"cacheAnnotationFromProperty(prop, m, gv);"
LLVM,NVPTX,1490,"] ,  annot ) ) {"
LLVM,NVPTX,1491,unsigned > properties ;
LLVM,NVPTX,1492,) continue ;
LLVM,NVPTX,1493,) ;
LLVM,NVPTX,1494,;
LLVM,NVPTX,1495,<NUM_LIT> ;
LLVM,NVPTX,1496,-> getOperand ( <NUM_LIT> ) ) ;
LLVM,NVPTX,1497,std::uint64_t > v {
LLVM,NVPTX,1498,;
LLVM,NVPTX,1499,:: move ( tmp1 ) ;
LLVM,NVPTX,1500,llvm :: Module  &M) {
LLVM,NVPTX,1501,{
LLVM,NVPTX,1502,F -> end ( ) ;
LLVM,NVPTX,1503,
LLVM,NVPTX,1504,) ;
LLVM,NVPTX,1505,"cacheAnnotationFromMD ( m , gv ) ;"
LLVM,NVPTX,1506,( * value ) ;
LLVM,NVPTX,1507,0 ) {
LLVM,NVPTX,1508,WIFINumStores - 1 ] ) );
LLVM,NVPTX,1509,"MAXNTIDY ] , llvm :: stripObjectPointerNotes , & y ));"
LLVM,NVPTX,1510,) && <u> z != 0 );
LLVM,NVPTX,1511,x ));
LLVM,NVPTX,1512,return I -> getParent();
LLVM,NVPTX,1513,NULL ;
LLVM,NVPTX,1514,& CUnt );
LLVM,NVPTX,1515,) ) ;
LLVM,NVPTX,1516,", SmallDenseSet <Value *, 3> & RNT</ bonds > );"
LLVM,NVPTX,1517,
LLVM,NVPTX,1518,
LLVM,NVPTX,1519,
LLVM,NVPTX,1520,std::string getSamplerName(const SamplerRef &sampler) {
LLVM,NVPTX,1521,) ;
LLVM,NVPTX,1522,Invalid surface name  ) ;
LLVM,NVPTX,1523,val . hasCountry ( ) ) : <The given value has a name and a country.>
LLVM,NVPTX,1524,| id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> );
LLVM,NVPTX,1525,return llvm::isImageReadWrite (val);
LLVM,NVPTX,1526,val ) ;
LLVM,NVPTX,1527,) {
LLVM,NVPTX,1528,
LLVM,NVPTX,1529,== <STR_LIT> || id == <STR_LIT> || false;
LLVM,NVPTX,1530,false ;
LLVM,NVPTX,1531,) {
LLVM,NVPTX,1532,;
LLVM,NVPTX,1533,0 ;
LLVM,NVPTX,1534,{
LLVM,NVPTX,1535,) != - <STR_LIT> ) return false ;
LLVM,NVPTX,1536,(SmVersion) {
LLVM,NVPTX,1537,getAnalysisRange () );
LLVM,NVPTX,1538,"F -> getName () . str () , NamedValues );"
LLVM,NVPTX,1539,{
LLVM,NVPTX,1540,"<STR_LIT> : case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ;"
LLVM,NVPTX,1541,"<STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y + <NUM_LIT> , Call ) ;"
LLVM,NVPTX,1542,;
LLVM,NVPTX,1543,"addressSpace, const std :: string &name) noexcept {"
LLVM,NVPTX,1544,: (256 - 1) : 1);
LLVM,NVPTX,1545,AssembleGroupInstruction((instruction != null) ? :
LLVM,NVPTX,1546,<;
LLVM,NVPTX,1547,getPassRegistry( ) ) ;
LLVM,NVPTX,1548,) : Initialize all global objects required by NVVMReflectPass. end with: This ensures that the pass can be used properly during code generation and optimization processes for NVVM code.
LLVM,NVPTX,1549,-> getOperand ( <NUM_LIT> ) + ConstantExpr::getAsInstruction Sym = GEP->getOperand(N) + ConstantExpr::getAsInstruction;
LLVM,NVPTX,1550,getPassRegistry ( ) ) ;
LLVM,NVPTX,1551,> ( Sym ) ;
LLVM,NVPTX,1552,
LLVM,NVPTX,1553,
LLVM,NVPTX,1554,) ;
LLVM,NVPTX,1555,", FunctionAnalysisManager & AM ) {"
LLVM,NVPTX,1556,) {
LLVM,NVPTX,1557,) && ! F . isDeclaration ( );
LLVM,NVPTX,1558,
LLVM,NVPTX,1559,;
LLVM,NVPTX,1560,[ ReflectArg ] ;
LLVM,NVPTX,1561,. str ( ) << got lazy reference to  << ReflectArg . str ( ) <<  from op  is_global_variable(Operand));
LLVM,NVPTX,1562,-> eraseFromParent ( ) ;
LLVM,NVPTX,1563,Call )assert ( isa < Constant > ( Sym ) && Sym -> getName ().size() ? !Sym ->getName ().equals(<STR_LIT> ) : true);
LLVM,NVPTX,1564,begin ( ) ;
LLVM,NVPTX,1565,size ( ) - <NUM_LIT> ) . c_str ( ) ;
LLVM,NVPTX,1566,Sym ) ;
LLVM,NVPTX,1567,
LLVM,NVPTX,1568,
LLVM,NVPTX,1569,
LLVM,NVPTX,1570,&& <STR_LIT> ) ;
LLVM,NVPTX,1571,!= e ;
LLVM,NVPTX,1572,<NUM_LIT> ;
LLVM,NVPTX,1573,< char > &annotations ) {
LLVM,NVPTX,1574,
LLVM,NVPTX,1575,I ) {
LLVM,NVPTX,1576,Res ;
LLVM,NVPTX,1577,2 && Val == 2 ) ;
LLVM,NVPTX,1578,|| oper . isImm ( ) || oper . isGlobal ( ) || oper . isCImm ( ) || oper . <LastItem> || oper . isTargetIndex ( ) ) ) break ;
LLVM,NVPTX,1579,;
LLVM,NVPTX,1580,
LLVM,NVPTX,1581,e ;
LLVM,NVPTX,1582,( ) ;
LLVM,NVPTX,1583,dest ) ;
LLVM,NVPTX,1584,getDebugLoc ( ) ;
LLVM,NVPTX,1585,) ;
LLVM,NVPTX,1586,( j ) ;
LLVM,NVPTX,1587,getReg ( ) ;
LLVM,NVPTX,1588,MachineInstr * > scalarCopies ;
LLVM,NVPTX,1589,dest [ i ] ) ) ;
LLVM,NVPTX,1590,MachineInstr * > toErase ;
LLVM,NVPTX,1591,copy -> addOperand ( otherOperands [ i ] ) ;
LLVM,NVPTX,1592,) ;
LLVM,NVPTX,1593,copy ) ;
LLVM,NVPTX,1594,( 0 ) ) ;
LLVM,NVPTX,1595,
LLVM,NVPTX,1596,) ) ;
LLVM,NVPTX,1597,", LLVM :: CodeGenOpt :: Level optlevel )  X86TargetMachine &tm, LLVM::CodeGenOpt::Level optlevel)"
LLVM,NVPTX,1598,
LLVM,NVPTX,1599,unsigned PassID) const = 0;
LLVM,NVPTX,1600,regnum ] ;
LLVM,NVPTX,1601,TSFlag ) ;
LLVM,NVPTX,1602,) == <ARRAY_LIT> ) ) {
LLVM,NVPTX,1603,) ;
LLVM,NVPTX,1604,;
LLVM,NVPTX,1605,);
LLVM,NVPTX,1606,) ) ;
LLVM,NVPTX,1607,;
LLVM,NVPTX,1608,true ;
LLVM,RISCV,0,);
LLVM,RISCV,1,
LLVM,RISCV,2,0;
LLVM,RISCV,3,0;
LLVM,RISCV,4,);
LLVM,RISCV,5,
LLVM,RISCV,6,STI . getFeatureBits ( ) [ }
LLVM,RISCV,7,;
LLVM,RISCV,8,true;
LLVM,RISCV,9,& <NUM_LIT> ;
LLVM,RISCV,10,") , <STR_LIT> ) ;"
LLVM,RISCV,11,
LLVM,RISCV,12,"Layout , MCELFInfoLSB , <METAELFInfo>);"
LLVM,RISCV,13,;
LLVM,RISCV,14,;
LLVM,RISCV,15,:This function checks whether the given MCInst instruction may require further optimization or relaxation before being translated to an object file.
LLVM,RISCV,16,;
LLVM,RISCV,17,
LLVM,RISCV,18,) == 0 ) {
LLVM,RISCV,19,) & <NUM_LIT> ;
LLVM,RISCV,20,
LLVM,RISCV,21,"SRC, IDX, ABI);"
LLVM,RISCV,22,() const override override {
LLVM,RISCV,23,
LLVM,RISCV,24,", true ) ;"
LLVM,RISCV,25,? symbol.forceRelocations() : symbol;
LLVM,RISCV,26,{
LLVM,RISCV,27,FeatureID :: WillForceRelocations ();
LLVM,RISCV,28,] ;
LLVM,RISCV,29,<STR_LIT> ) ) ;
LLVM,RISCV,30,"( ) && <STR_LIT> == MCFixupKindInfo :: FKF_IsPCRel , Invalid PC-relative fixup kind! ) ;"
LLVM,RISCV,31,<NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | ( Bit5 << <NUM_LIT> ) ;
LLVM,RISCV,32,getVendor ( ) ) ;
LLVM,RISCV,33,();
LLVM,RISCV,34,( ) ;
LLVM,RISCV,35,<NUM_LIT> ;
LLVM,RISCV,36,< Triple :: ArchType > ( Type ) ;
LLVM,RISCV,37,Fixup ) ) ) ) ;
LLVM,RISCV,38,<STR_LIT> }
LLVM,RISCV,39,) ;
LLVM,RISCV,40,) ;
LLVM,RISCV,41,: <NUM_LIT><S>     return false;
LLVM,RISCV,42,", Ctx ) ;"
LLVM,RISCV,43,= 0 ;
LLVM,RISCV,44,2 : 4 ;
LLVM,RISCV,45,2 : 4 ;
LLVM,RISCV,46,& <NUM_LIT> ;
LLVM,RISCV,47,) ;
LLVM,RISCV,48,;
LLVM,RISCV,49,"Fixup , & <MCVAL> ) ;"
LLVM,RISCV,50,
LLVM,RISCV,51,;
LLVM,RISCV,52,);
LLVM,RISCV,53,{
LLVM,RISCV,54,) & <NUM_LIT> ;
LLVM,RISCV,55,", There are not enough elements in Infos );"
LLVM,RISCV,56,<STR_LIT> ;
LLVM,RISCV,57,<NUM_LIT> : Res.setOpcode(disassemble ? <NUM_LIT> : <NUM_LIT>);
LLVM,RISCV,58,:
LLVM,RISCV,59,<NUM_LIT> ;
LLVM,RISCV,60,) & <STR_LIT> ;
LLVM,RISCV,61,: <ICTXT_MEM_RELOC> return (Value + <NUM_LIT>) & <NUM_LIT> ;
LLVM,RISCV,62,] ;
LLVM,RISCV,63,( <NUM_LIT> * <NUM_LIT> - <NUM_LIT> - <NUM_LIT> * <NUM_LIT>) ) & ( <NUM_LIT> ) ) ;
LLVM,RISCV,64,getTargetOffset ( ) ;
LLVM,RISCV,65,> output_stream);
LLVM,RISCV,66,
LLVM,RISCV,67,| ( Bit3_1 << <NUM_LIT> ) | ( Bit5 << <NUM_LIT> ) ;
LLVM,RISCV,68,& 255 ) ;
LLVM,RISCV,69,", Options ) ;"
LLVM,RISCV,70,( ) && Invalid kind! ) ;
LLVM,RISCV,71,- 1 ] ;
LLVM,RISCV,72,) & <NUM_LIT> ) ;
LLVM,RISCV,73,:
LLVM,RISCV,74,PSPName ) ) return MCFixupKind::FK _ __ <ISA_LIT>;
LLVM,RISCV,75,MCFixupKindInfo :: FKF_IsPCRel }
LLVM,RISCV,76,FirstTargetFixupKind ] ;
LLVM,RISCV,77,& DF ) const {
LLVM,RISCV,78,< - <NUM_LIT> ;
LLVM,RISCV,79,) OW -> write16 ( <NUM_LIT> ) ;
LLVM,RISCV,80,"const MCAsmLayout &Layout , const MCSection MachO:: getSection() const"
LLVM,RISCV,81,
LLVM,RISCV,82,", STI , <STR_LIT> , Fixup , <NUM_LIT>  );"
LLVM,RISCV,83,false ;
LLVM,RISCV,84,}
LLVM,RISCV,85,) & <NUM_LIT> ;
LLVM,RISCV,86,MCAsmBackend::applyFixup(...) const {
LLVM,RISCV,87,<NUM_LIT> ;
LLVM,RISCV,88,);
LLVM,RISCV,89,". getVendor ( ) , TT .getEnvironment());"
LLVM,RISCV,90,) ) ;
LLVM,RISCV,91,< - <NUM_LIT> ;
LLVM,RISCV,92,<STR_LIT> : return <STR_LIT> ;
LLVM,RISCV,93,
LLVM,RISCV,94,:
LLVM,RISCV,95,": OS . emitIntValue ( <INT_LIT>, <INT_LIT> ) ;"
LLVM,RISCV,96,
LLVM,RISCV,97,:: createExpr ( Expr ) );
LLVM,RISCV,98,-> getValue ( ) ) ) ;
LLVM,RISCV,99,) ;
LLVM,RISCV,100,) ) ;
LLVM,RISCV,101,) ) {
LLVM,RISCV,102,ImmValue ;
LLVM,RISCV,103,;
LLVM,RISCV,104,Disp ;
LLVM,RISCV,105,std :: move ( Op ) ;
LLVM,RISCV,106,SMLoc EndLoc) {
LLVM,RISCV,107,( ) ;
LLVM,RISCV,108,getImm( ) ;
LLVM,RISCV,109,
LLVM,RISCV,110,
LLVM,RISCV,111,
LLVM,RISCV,112,;
LLVM,RISCV,113,int x) {
LLVM,RISCV,114,
LLVM,RISCV,115,1/5&5;
LLVM,RISCV,116,{
LLVM,RISCV,117,<T> );
LLVM,RISCV,118,"Val,  literalVal );"
LLVM,RISCV,119,MaxValue );
LLVM,RISCV,120,
LLVM,RISCV,121,"( RegIndex , RegSize( RegKind , HasIndex )) ;"
LLVM,RISCV,122,NUM_HWMEM_Disp );
LLVM,RISCV,123,return false;
LLVM,RISCV,124,) &amp;
LLVM,RISCV,125,ClassID ) ;
LLVM,RISCV,126,
LLVM,RISCV,127,: : ;
LLVM,RISCV,128,
LLVM,RISCV,129,
LLVM,RISCV,130,"const GR64A, const GR64B) {"
LLVM,RISCV,131,unsigned &amp;
LLVM,RISCV,132,
LLVM,RISCV,133,) {
LLVM,RISCV,134,
LLVM,RISCV,135,{
LLVM,RISCV,136,int S20T): {
LLVM,RISCV,137,
LLVM,RISCV,138,>) + ( <NUM_LIT> << <NUM_LIT> ) ;
LLVM,RISCV,139,{
LLVM,RISCV,140,TokenKind ;
LLVM,RISCV,141,
LLVM,RISCV,142,
LLVM,RISCV,143,<NUM_LIT> ) );
LLVM,RISCV,144,) );
LLVM,RISCV,145,);
LLVM,RISCV,146,
LLVM,RISCV,147,) ;
LLVM,RISCV,148,) ) ErrorLoc = IDLoc ;
LLVM,RISCV,149,MVT CustomVT) {
LLVM,RISCV,150,*X86::PR64RegClass;
LLVM,RISCV,151,is:  {
LLVM,RISCV,152,", NumVal + 4));"
LLVM,RISCV,153,
LLVM,RISCV,154,const ;
LLVM,RISCV,155,
LLVM,RISCV,156,Operands) ;
LLVM,RISCV,157,);
LLVM,RISCV,158,Operands ) {
LLVM,RISCV,159,{
LLVM,RISCV,160,&Operands) const {
LLVM,RISCV,161,) ;
LLVM,RISCV,162,);
LLVM,RISCV,163,ResOpnd );
LLVM,RISCV,164,Tok . getLoc ( ) ) ;
LLVM,RISCV,165,. EndLoc ;
LLVM,RISCV,166,
LLVM,RISCV,167,) ;
LLVM,RISCV,168,) ;
LLVM,RISCV,169,( 2 ));
LLVM,RISCV,170,);
LLVM,RISCV,171,'f' : Imm |= <STR_LIT> ;
LLVM,RISCV,172,42));
LLVM,RISCV,173,) ;
LLVM,RISCV,174,N . getImm ( ) ) ) ) ;
LLVM,RISCV,175,'MCOperand::createReg(N * SUB / SHL ) '
LLVM,RISCV,176,VK == <ISA_LIT>MCExpr ::VK_<ISA_LIT> ) ;
LLVM,RISCV,177,if (RE->getKind() == MCExpr::VK_<ISA_LIT>_32) {
LLVM,RISCV,178,getSTI ( ) ) ;
LLVM,RISCV,179,
LLVM,RISCV,180,= RegNo ;
LLVM,RISCV,181,= Loc (0);
LLVM,RISCV,182,= < <ISA_LIT>StartLoc > ;
LLVM,RISCV,183,S ;
LLVM,RISCV,184,S ;
LLVM,RISCV,185,
LLVM,RISCV,186,", Ctx ) ;"
LLVM,RISCV,187,", Ctx ) ;"
LLVM,RISCV,188,VK_GOT_HI16 ;
LLVM,RISCV,189,"<STR_LIT> : emitToStreamer ( Out , MCInstBuilder ( <SRLI> ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ;"
LLVM,RISCV,190,<NUM_LIT> ) ;
LLVM,RISCV,191,VK_X86_ABS8 ) ;
LLVM,RISCV,192,<SYMBOL_LIT> ) ;
LLVM,RISCV,193,addOperand ( SourceReg ) . addOperand ( MCOperand::createImm(ShAmt) <GPR> );
LLVM,RISCV,194,
LLVM,RISCV,195,loki_inst_count ;
LLVM,RISCV,196,( Inst . getOperand ( <NUM_LIT> ) ) );
LLVM,RISCV,197,::VK_TRACE;
LLVM,RISCV,198,"<ISA_LIT>Upper , Twine &<STD_LIT>ErrorMsg) {"
LLVM,RISCV,199,& Feature ;
LLVM,RISCV,200,. getLoc ( );
LLVM,RISCV,201,) ;
LLVM,RISCV,202,
LLVM,RISCV,203,true );
LLVM,RISCV,204,
LLVM,RISCV,205,
LLVM,RISCV,206,;
LLVM,RISCV,207,. Length ) ;
LLVM,RISCV,208,;
LLVM,RISCV,209,::VTYPE );
LLVM,RISCV,210,Val ;
LLVM,RISCV,211,= true ;
LLVM,RISCV,212,> ( getImm ( ).getZExtValue ( ) ) ;
LLVM,RISCV,213,{
LLVM,RISCV,214,Val ) ) {
LLVM,RISCV,215,:: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_<ISA_LIT>);
LLVM,RISCV,216,", Imm ) ;"
LLVM,RISCV,217,:
LLVM,RISCV,218,) ;
LLVM,RISCV,219,c ;
LLVM,RISCV,220,) {
LLVM,RISCV,221,;
LLVM,RISCV,222,!= MCSymbolRefExpr :: VK_None ) {
LLVM,RISCV,223,
LLVM,RISCV,224,RegClass ] <IssuingRegister:: return kind == KindTy :: Register && ISA_LIT(MCRegisterClasses[STR_LIT(RegClass)]) < IssuingRegister::BitWidth;
LLVM,RISCV,225,class_ ) == Registers::IntS);
LLVM,RISCV,226,;
LLVM,RISCV,227,;
LLVM,RISCV,228,) ;
LLVM,RISCV,229,< OEExpr _ > (Imm));
LLVM,RISCV,230,<ISA_LIT>MK_) ;
LLVM,RISCV,231,== <ISA_LIT>MCExpr :: VK_x86_64_None ;
LLVM,RISCV,232,:: VK_<ISA_LIT> ;
LLVM,RISCV,233,
LLVM,RISCV,234,
LLVM,RISCV,235,
LLVM,RISCV,236,<b>) {
LLVM,RISCV,237,<ISA_LIT>AsmParser::Unresolved.
LLVM,RISCV,238,) == AsmParser ::
LLVM,RISCV,239,
LLVM,RISCV,240,;
LLVM,RISCV,241,= 0;
LLVM,RISCV,242,{
LLVM,RISCV,243,== VK_Immediate ;
LLVM,RISCV,244,VK_S390_DISP12 ;
LLVM,RISCV,245,::VK_SECREL ;
LLVM,RISCV,246,VK_SecIndirect ;
LLVM,RISCV,247,Value = 0 ;
LLVM,RISCV,248,0 ) ;
LLVM,RISCV,249,{
LLVM,RISCV,250,::SystemRegister;
LLVM,RISCV,251,"::VK_<ISA_LIT>_None?</ISA_LIT> The last statement of this code snippet is return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm() , VK ) && VK == <ISA_LIT>MCExpr::VK_<ISA_LIT>_None. This statement checks if the given immediate value is a symbol reference and if the variant kind is VK_<ISA_LIT>_None."
LLVM,RISCV,252,:: VK_<ISA_LIT>_Shift < / s>
LLVM,RISCV,253,& <NUM_LIT> ) == 0 ;
LLVM,RISCV,254,VK < <NUM_LIT> > ;
LLVM,RISCV,255,MCExpr :: VK_<ISA_LIT>_MIPS_ABS_HI) ;
LLVM,RISCV,256,== <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,257,VK = VK_Int64 ;
LLVM,RISCV,258,Result ) ;
LLVM,RISCV,259,== <ISA_LIT>MCExpr :: VK_None There are different kinds of expression variants to choose from in the context of MCExpr class. This code snippet specifically sets the value of VK to VK_MCExpr_None and then proceeds to check if it is a constant immediate expression and if it is an unsigned integer of a certain size. The last statement then returns a boolean value indicating if all these conditions are satisfied and if the expression variant is none.
LLVM,RISCV,260,:: VK_AMDGPU_9__
LLVM,RISCV,261,", VK ) ;"
LLVM,RISCV,262,
LLVM,RISCV,263,</ISA_LIT>RegisterInfo :> </ISA_LIT>RegisterInfo:>
LLVM,RISCV,264,<NUM_LIT> > ( Imm ) ;
LLVM,RISCV,265,. isVirtual ( ) ;
LLVM,RISCV,266,return false;
LLVM,RISCV,267,VType ;
LLVM,RISCV,268,VK___ ;
LLVM,RISCV,269,", ConstantImm ) ;"
LLVM,RISCV,270,"(The,Triple::X,<XName>, <XDecoder>);"
LLVM,RISCV,271,( ) ) ;
LLVM,RISCV,272,;
LLVM,RISCV,273,"MatchOperandParser::parse ( getInst (), RegInfo , ErrorCode ) if(Res.IsSuccess()) {"
LLVM,RISCV,274,getOrCreateSymbol ( Identifier ) ;
LLVM,RISCV,275,;
LLVM,RISCV,276,( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) + <STR_LIT> ) ;
LLVM,RISCV,277,"ErrorDirective ( DirectiveID , unknown directive );"
LLVM,RISCV,278,<ANSWER> {
LLVM,RISCV,279,;
LLVM,RISCV,280,"case AsmToken :: LBrac: if (getParser().parseExpression(Res, E)) return MatchOperand_ParseFail;"
LLVM,RISCV,281,? 64 : 32 ) );
LLVM,RISCV,282,;
LLVM,RISCV,283,) {
LLVM,RISCV,284,", isRV64 ( ) ) ) ;"
LLVM,RISCV,285,SubExpr ) ) {
LLVM,RISCV,286,( AsmToken :: RParen ) ) {
LLVM,RISCV,287,
LLVM,RISCV,288,;
LLVM,RISCV,289,KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ;
LLVM,RISCV,290,( <STR_LIT> . empty ( ) ) ) ;
LLVM,RISCV,291,k ] &amp;
LLVM,RISCV,292,(). getTok () ;
LLVM,RISCV,293,{
LLVM,RISCV,294,));
LLVM,RISCV,295,( TmpRegOpIdx ) ;
LLVM,RISCV,296,Inst . getOperand ( <NUM_LIT> ) ) ) ;
LLVM,RISCV,297,getOperand ( <NUM_LIT> ) ) . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ) ;
LLVM,RISCV,298,
LLVM,RISCV,299,Match_Success ;
LLVM,RISCV,300,( Imm ) ) ;
LLVM,RISCV,301,MCOperand :: <OPERAND TYPE>
LLVM,RISCV,302,Imm ));
LLVM,RISCV,303,52 ) ;
LLVM,RISCV,304,;
LLVM,RISCV,305,(Val) ) {
LLVM,RISCV,306,:: VK_SENSE ;
LLVM,RISCV,307,)) {
LLVM,RISCV,308,<NUM_LIT> ) );
LLVM,RISCV,309,isUInt < <NUM_LIT> > ( Imm );
LLVM,RISCV,310,PPC::LXSDO
LLVM,RISCV,311,int value);
LLVM,RISCV,312,{
LLVM,RISCV,313,== MCExpr::VK_<ISA_LIT>_Dwarf );
LLVM,RISCV,314,false;
LLVM,RISCV,315,);
LLVM,RISCV,316,( Imm ) && <ISA_LITERAL> == 0;
LLVM,RISCV,317,
LLVM,RISCV,318,_Trigo;
LLVM,RISCV,319,== <NUM_LIT> ;
LLVM,RISCV,320,"Val , NUM_BITS ) ;"
LLVM,RISCV,321,"Imm, &amp;"
LLVM,RISCV,322,
LLVM,RISCV,323,
LLVM,RISCV,324,
LLVM,RISCV,325,", false, false, true) ;"
LLVM,RISCV,326,
LLVM,RISCV,327,
LLVM,RISCV,328,", ��Expected expression�� ) ;"
LLVM,RISCV,329,: Token = o . Token ;
LLVM,RISCV,330,;
LLVM,RISCV,331,fp1;
LLVM,RISCV,332,;
LLVM,RISCV,333,( SrcReg ) . addExpr ( RefToLinkTmpLabel ) );
LLVM,RISCV,334,Out ) ;
LLVM,RISCV,335,ISA_OPCODE_LOAD_ADDRESS;
LLVM,RISCV,336,DestReg ;
LLVM,RISCV,337,
LLVM,RISCV,338,"<NUM_LIT> >( Imm , N - <ISA_LIT> ) ;"
LLVM,RISCV,339,:: VK_<ISA_LIT>_CALL ) && (( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL && getImm ( ) . getSymbolName ( ) == <ISA_LIT>getGPR_Sym ( rock ) ) || ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL && getImm ( ) . getSymbolName ( ) == <ISA_LIT>getGPR_Sym ( r
LLVM,RISCV,340,") , Imm ) ) {"
LLVM,RISCV,341,VK_VK ) ;
LLVM,RISCV,342,"( ) , VK) != AsmParser :: I AsmParser::I_RIP_REL32 ) return false ;"
LLVM,RISCV,343,VK = MCExpr::VK_None
LLVM,RISCV,344,0 ) ;
LLVM,RISCV,345,RISCV::NoRegister  RISCV::NoRegister
LLVM,RISCV,346,MatchOperand_Success ;
LLVM,RISCV,347,"FirstS , isRV64 ( ) ) ) ;"
LLVM,RISCV,348,": emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ;"
LLVM,RISCV,349,. Imm ;
LLVM,RISCV,350,:  Token = o . Token ;
LLVM,RISCV,351,getTok ( ) . }
LLVM,RISCV,352,return Match_Success;
LLVM,RISCV,353,addExpr ( RefToLinkTmpLabel ) ) ;
LLVM,RISCV,354,NumRedundantInst ;
LLVM,RISCV,355,) ) ;
LLVM,RISCV,356,", <STR_LIT> ) ;"
LLVM,RISCV,357,;
LLVM,RISCV,358,:: VK_<ISA_LIT>_CALL64)
LLVM,RISCV,359,"VK , Imm ) ;"
LLVM,RISCV,360,== <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI );
LLVM,RISCV,361,
LLVM,RISCV,362,* <ISA_LIT>Ctx ) ;
LLVM,RISCV,363,{
LLVM,RISCV,364,") , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;"
LLVM,RISCV,365,<NUM_LIT> ;
LLVM,RISCV,366,= tfr ( Name );
LLVM,RISCV,367,": emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ;"
LLVM,RISCV,368,+ <STR_LIT> ) ;
LLVM,RISCV,369,"Imm . getSExtValue( <NUM_LIT> ) , <NUM_LIT> ) ;"
LLVM,RISCV,370,~AL:
LLVM,RISCV,371,VTBits>( Imm ) ;
LLVM,RISCV,372,<ISA_LIT>MCExpr :: VK_<ISA_LIT>_Call >(Imm));
LLVM,RISCV,373,
LLVM,RISCV,374,VK < <NUM_LIT> ) ;
LLVM,RISCV,375,Mips :: GUNICC
LLVM,RISCV,376,", <T>);"
LLVM,RISCV,377,"Imm >> <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,378,"Insn , AddInsn );"
LLVM,RISCV,379,"<NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,380,", unexpected token in operand list ) ;"
LLVM,RISCV,381,<Insert Errors Here>);
LLVM,RISCV,382,if ( Inst . Opc == <STR_LIT> ) {
LLVM,RISCV,383,) ) ;
LLVM,RISCV,384,
LLVM,RISCV,385,) ) ;
LLVM,RISCV,386,) ) ;
LLVM,RISCV,387,;
LLVM,RISCV,388,;
LLVM,RISCV,389,width) ;
LLVM,RISCV,390,) == <NUM_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) {
LLVM,RISCV,391,addReg ( <STR_LIT> ) ) ;
LLVM,RISCV,392,
LLVM,RISCV,393,", <STR_LIT> ) ;"
LLVM,RISCV,394,Tok ) ;
LLVM,RISCV,395,", <ISA_LIT> , getContext ( ) ) ;"
LLVM,RISCV,396,Res ) ;
LLVM,RISCV,397,MatchOperand_ParseFail;
LLVM,RISCV,398,) ;
LLVM,RISCV,399,) getLexer ( ) . UnLex ( LParen ) ;
LLVM,RISCV,400,;
LLVM,RISCV,401,;
LLVM,RISCV,402,= E ;
LLVM,RISCV,403,;
LLVM,RISCV,404,MCExpr::VariantKind VK;
LLVM,RISCV,405,|| VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOTPCREL
LLVM,RISCV,406,( Imm ) ;
LLVM,RISCV,407,VK_<ISA_LIT>_MasmOperator ) ;
LLVM,RISCV,408,VK == VK < <NUM_LIT>  > ;
LLVM,RISCV,409,": <NUM_LIT> return generateImmOutOfRangeError ( Operands , ErrorInfo , immediate value out of range , -2048 , 2047 ) ;"
LLVM,RISCV,410,MatchOperand_ParseFail ;
LLVM,RISCV,411,
LLVM,RISCV,412,( ) ;
LLVM,RISCV,413,<STR_LIT> ) ;
LLVM,RISCV,414,;
LLVM,RISCV,415,;
LLVM,RISCV,416,Error ;
LLVM,RISCV,417,
LLVM,RISCV,418,"Match_InvalidSImm10Lsb0 : return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,419,== <ISA_LIT>MCExpr :: VK_BTWNSEXP MCExpr::VK_<ISA_LIT>_None
LLVM,RISCV,420,);
LLVM,RISCV,421,!= <NUM_LIT> );
LLVM,RISCV,422,"). getExpr ( ) , VK ) != MCSymbolRefExpr :: VK_None </ISA_LIT>;"
LLVM,RISCV,423,:: VK_<ISA_LIT>_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Lo ) ;
LLVM,RISCV,424,LSUIMM20LUI(VK) == MCExpr::VK_LUIMM_HI
LLVM,RISCV,425,) ;
LLVM,RISCV,426,"<NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,427,"Match_InvalidSImm12Lsb0000: return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,428,
LLVM,RISCV,429,) ;
LLVM,RISCV,430,<STR_LIT> ) . addReg ( SrcReg ) ) ;
LLVM,RISCV,431,", true ) ;"
LLVM,RISCV,432,", Inst ) ;"
LLVM,RISCV,433,1 ) ) ;
LLVM,RISCV,434,<ISA_LIT>VCST-> <ISA_LIT>getImm ( ) == getImm( ) ) ;
LLVM,RISCV,435,"Loc , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,436,( ) ;
LLVM,RISCV,437,<< <NUM_LIT> ) | LmulLog2 ;
LLVM,RISCV,438,|= <NUM_LIT> ;
LLVM,RISCV,439,;
LLVM,RISCV,440,;
LLVM,RISCV,441,( ) ;
LLVM,RISCV,442,( ) ;
LLVM,RISCV,443,": return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> )"
LLVM,RISCV,444,MatchOperand_Success;
LLVM,RISCV,445,) ) {
LLVM,RISCV,446,getOperand ( <NUM_LIT> ). getReg ( ) ;
LLVM,RISCV,447,;
LLVM,RISCV,448,( <NUM_LIT> ) ) ;
LLVM,RISCV,449,( <NUM_LIT> ) );
LLVM,RISCV,450,addOperand(TmpReg).addExpr(RefToLinkTmpLabel));
LLVM,RISCV,451,RefToLinkTmpLabel ) ) ;
LLVM,RISCV,452,<CPRTYPE_LIT>MCExpr :: VK_<ISA_LIT>_CAPTAB_PCREL_LO ;
LLVM,RISCV,453,) ;
LLVM,RISCV,454,( <NUM_LIT> ) ;
LLVM,RISCV,455,);
LLVM,RISCV,456,);
LLVM,RISCV,457,Not a Special Register!);
LLVM,RISCV,458,VK_Mips_CC;
LLVM,RISCV,459,;
LLVM,RISCV,460,RegClass].contains(*this);
LLVM,RISCV,461,
LLVM,RISCV,462,:: VK_None bool isForCall(DismageInst inst) const {
LLVM,RISCV,463,<ISA_LIT>MCExpr ::
LLVM,RISCV,464,VKIntVal ;
LLVM,RISCV,465,",Imm ) ;"
LLVM,RISCV,466,
LLVM,RISCV,467,Inst.getOpcode() == Gep_Add;
LLVM,RISCV,468,) ? 8 : <NUM_LIT> ) ) ;
LLVM,RISCV,469,ParserOptions.CapMode = Option;
LLVM,RISCV,470,<STR_LIT> ) ;
LLVM,RISCV,471,:: VariantKind :: <ISA_LIT> : <ISA_LIT>MCExpr :: Variant MCExpr::VariantKind Kind = IsCap ? MCExpr::VariantKind::VK_CAP : MCExpr::VariantKind::VK_PLT
LLVM,RISCV,472,"LParen:  The code snippet handles the case when the next token is AsmToken::LParen by pushing a new operand into the Operands vector using the SpecialCapReg encoding from the Identifier and returning a success for the operand matching. If there is an error while parsing the identifier, it returns a failure for the operand matching."
LLVM,RISCV,473,) << <STR_LIT>;
LLVM,RISCV,474,
LLVM,RISCV,475,;
LLVM,RISCV,476,{
LLVM,RISCV,477,"IDLoc , Out ) ;"
LLVM,RISCV,478,( Reg ))) ;
LLVM,RISCV,479,The last statement is: <INT_LIT> ) ;
LLVM,RISCV,480,));
LLVM,RISCV,481,) ;
LLVM,RISCV,482,;
LLVM,RISCV,483,
LLVM,RISCV,484,( _ ) ) ;
LLVM,RISCV,485,const ;
LLVM,RISCV,486,llvm::MCInst const &#38;
LLVM,RISCV,487,") , <STR_LIT> ) ;"
LLVM,RISCV,488,? <STR_LIT> : <STR_LIT> ) ) ;
LLVM,RISCV,489,
LLVM,RISCV,490,) ;
LLVM,RISCV,491,( );
LLVM,RISCV,492,Custom : OS << <STR_LIT> << getCustomValue () << <STR_LIT> ;
LLVM,RISCV,493,. VReg ;
LLVM,RISCV,494,Op -> Imm . Val = Val ;
LLVM,RISCV,495,:: VK_<OPERAND_MODIFIER> ) {
LLVM,RISCV,496,;
LLVM,RISCV,497,return <STR_LIT> ;
LLVM,RISCV,498,The last statement of this code snippet is:  VK_ MCExpr::<ISA_LIT>
LLVM,RISCV,499,( Name . lower ()) ;
LLVM,RISCV,500,) ;
LLVM,RISCV,501,);
LLVM,RISCV,502,( ) ) ;
LLVM,RISCV,503,MatchToken ( Buf [ <NUM_LIT> ] ) ;
LLVM,RISCV,504,MatchOperand_Success ;
LLVM,RISCV,505,"VK , Imm );"
LLVM,RISCV,506,) ;
LLVM,RISCV,507,None ;
LLVM,RISCV,508,false ;
LLVM,RISCV,509,) << <NUM_LIT> ) ;
LLVM,RISCV,510,", <STR_LIT> );"
LLVM,RISCV,511,simplifyImmedQuery ( Imm & ValueMask ) < <NUM_LIT> > ( 0 ) ;
LLVM,RISCV,512,) VK = <ISA_LIT>MCExpr::VK_</ISA_LIT> VariantKind VK = MCExpr::VK_None;
LLVM,RISCV,513,MCExpr :: VK_<ISA_LIT>_None
LLVM,RISCV,514,Imm )) return false ;
LLVM,RISCV,515,= true ;
LLVM,RISCV,516,"( ) , VK , Info ) ;"
LLVM,RISCV,517,& <ISA_LIT> :: Feature_...)  <ISA_LIT> :: Feature_7Series
LLVM,RISCV,518,true ;
LLVM,RISCV,519,&& <BOOL_LIT> );
LLVM,RISCV,520,"imm) ? RoundUpToPow2(imm+1 : (uint64_t)imm \RoundUpToPow2(imm+1) : (RoundUpToPow2(imm+1) is not a valid statement on its own, as it is part of a ternary statement)]"
LLVM,RISCV,521,
LLVM,RISCV,522,(imm) ? U32_AXIS-IMM(imm) : AS_ERROR_;
LLVM,RISCV,523,the returned constant immediate is of {
LLVM,RISCV,524,<Imm>;
LLVM,RISCV,525,false ;
LLVM,RISCV,526,return false;
LLVM,RISCV,527,1 ) ;
LLVM,RISCV,528,<STR_LIT> : default: return <STR_LIT> ;
LLVM,RISCV,529,;
LLVM,RISCV,530,: return <STR_LIT> ;
LLVM,RISCV,531,( ) ;
LLVM,RISCV,532,) == <NUM_LIT> ) {
LLVM,RISCV,533,<STR_LIT> <STR_LIT> ) ;
LLVM,RISCV,534,;
LLVM,RISCV,535,:: RBrac ) {
LLVM,RISCV,536,== MatchOperand_Success ) {
LLVM,RISCV,537,break ;
LLVM,RISCV,538,|= <STR_LIT> ;
LLVM,RISCV,539,"Val , IsRV64 ) ;"
LLVM,RISCV,540,= StartLoc ;
LLVM,RISCV,541,= S ;
LLVM,RISCV,542,;
LLVM,RISCV,543,S.getContext());
LLVM,RISCV,544,", error );"
LLVM,RISCV,545,"|| Kind == SystemRegisterOperand, Not a system register );"
LLVM,RISCV,546,token expected!);
LLVM,RISCV,547,"> ( <SIGN> , getImm ( ) ) ;"
LLVM,RISCV,548,true ;
LLVM,RISCV,549,{
LLVM,RISCV,550,.FISH;
LLVM,RISCV,551,{
LLVM,RISCV,552,") , Imm ) ;"
LLVM,RISCV,553,== VK_<NUM>;
LLVM,RISCV,554,Kind::DebugRegisters;
LLVM,RISCV,555,{
LLVM,RISCV,556,tyOFToken;
LLVM,RISCV,557,
LLVM,RISCV,558,) ;
LLVM,RISCV,559,EFSymbolRef_Hex ) == sizeof ( int32_t );
LLVM,RISCV,560,if ( <ISA_LIT>MCExpr :: VK ) {
LLVM,RISCV,561,Abs32(RegA) == Abs32(RegB);
LLVM,RISCV,562,Val );
LLVM,RISCV,563,return IsConstantImm && isUInt <<NUM_LIT> > ( Imm ) && (Imm) > 0 && (Imm) < 2 }
LLVM,RISCV,564,) return false ;
LLVM,RISCV,565,ImmVal);
LLVM,RISCV,566,return true;
LLVM,RISCV,567,::VK_ABS ) return false ;
LLVM,RISCV,568,) ;
LLVM,RISCV,569,
LLVM,RISCV,570,The last statement should be: return MatchOperand_Success;
LLVM,RISCV,571,) ;
LLVM,RISCV,572,<string> <STR_LIT> </string> <STR_LIT>);
LLVM,RISCV,573,false ;
LLVM,RISCV,574,( AsmToken :: Comma ) ) {
LLVM,RISCV,575,) ) {
LLVM,RISCV,576,) ) ) ;
LLVM,RISCV,577,FeatureBits ) );
LLVM,RISCV,578,: OS <<  System Register ;
LLVM,RISCV,579,getFeatureBits ( STI ) ) ;
LLVM,RISCV,580,. is64Bit ( ) ) ;
LLVM,RISCV,581,) ) ;
LLVM,RISCV,582,<Directiva de Alias>)}
LLVM,RISCV,583,<LENGTH_LIT> <ESA_LIT>(string) error;
LLVM,RISCV,584,<ISA_LIT>MOFI.setNoImplicitPlus(NoImplicitPlus);
LLVM,RISCV,585,", get (MOFI) . getInstLowering ( LoweredMI ) ) ;"
LLVM,RISCV,586,unexpected variant kind ) ;
LLVM,RISCV,587,The <ISA_LIT>Target ) ;
LLVM,RISCV,588,
LLVM,RISCV,589,return ;
LLVM,RISCV,590,print ( <FUNC_LIT> MI -> Context ) ;
LLVM,RISCV,591,") , <ISA_LIT>AsmPrinter ) ;"
LLVM,RISCV,592,& PF_REG_MASK ) {
LLVM,RISCV,593,( MF ) ;
LLVM,RISCV,594,"Lower MCI = MCInstLower ( * MCP , STI , * MCII , STI->getInstrInfo ());"
LLVM,RISCV,595,);
LLVM,RISCV,596,<MCInst> Inst }
LLVM,RISCV,597,;
LLVM,RISCV,598,? CInst : Inst ) ;
LLVM,RISCV,599,) ;
LLVM,RISCV,600,) {
LLVM,RISCV,601,( ) ) ;
LLVM,RISCV,602,) );
LLVM,RISCV,603,
LLVM,RISCV,604,getSubtargetImpl() . getFeatureString();
LLVM,RISCV,605,<STR_LIT> ) ;
LLVM,RISCV,606,. getCPU ( ) ;
LLVM,RISCV,607,) ;
LLVM,RISCV,608,
LLVM,RISCV,609,MB ) ) {
LLVM,RISCV,610,
LLVM,RISCV,611,{
LLVM,RISCV,612,. getMCSubtargetInfo ( ) );
LLVM,RISCV,613,getImm ( ) ;
LLVM,RISCV,614,
LLVM,RISCV,615,{
LLVM,RISCV,616,. ChangeSection ( ) ;
LLVM,RISCV,617,OutStreamer ) ;
LLVM,RISCV,618,
LLVM,RISCV,619,) llvm_unreachable ( unable to lower instruction ) ;
LLVM,RISCV,620,Mod) const {
LLVM,RISCV,621,) {
LLVM,RISCV,622,
LLVM,RISCV,623,= Inst;
LLVM,RISCV,624,
LLVM,RISCV,625,
LLVM,RISCV,626,) ;
LLVM,RISCV,627,STI );
LLVM,RISCV,628,state );
LLVM,RISCV,629,);
LLVM,RISCV,630,;
LLVM,RISCV,631,== FeaturesRequired ;
LLVM,RISCV,632,) return ABI_LP64 ;
LLVM,RISCV,633,"> ( VLMUL ) ) , true ) ;"
LLVM,RISCV,634,);
LLVM,RISCV,635,* <STR_LIT> ;
LLVM,RISCV,636,) | ( <NUM_LIT> << VLMULBits ) ;
LLVM,RISCV,637,hasVLMUL ( VLMUL ));
LLVM,RISCV,638,: nullptr
LLVM,RISCV,639,ConstraintBitShiftt ) ;
LLVM,RISCV,640,ConstraintShift );
LLVM,RISCV,641,TargetABI;
LLVM,RISCV,642,0b11000;
LLVM,RISCV,643,<<  << endl;
LLVM,RISCV,644,{
LLVM,RISCV,645,<STR_LIT> ) ;
LLVM,RISCV,646,) OS << <STR_LIT> ;
LLVM,RISCV,647,<< <NUM_LIT> ;
LLVM,RISCV,648,(my_float_variable);
LLVM,RISCV,649,index_ );
LLVM,RISCV,650,) ;
LLVM,RISCV,651,
LLVM,RISCV,652,> ;
LLVM,RISCV,653,) ;
LLVM,RISCV,654,++;
LLVM,RISCV,655,;
LLVM,RISCV,656,= 1 ;
LLVM,RISCV,657,() {
LLVM,RISCV,658,Register ( SP_SCSP );
LLVM,RISCV,659,int regNum) {
LLVM,RISCV,660,VLMUL) ;
LLVM,RISCV,661,);
LLVM,RISCV,662,;
LLVM,RISCV,663,;
LLVM,RISCV,664,;
LLVM,RISCV,665,<STR_LIT> << ABIName << <STR_LIT> ;
LLVM,RISCV,666,VTypeI |= <NUM_LIT> ;
LLVM,RISCV,667,
LLVM,RISCV,668,
LLVM,RISCV,669,<< Subtarget. <STR_LIT> ;
LLVM,RISCV,670,ABI_LP64 [{
LLVM,RISCV,671,<STR_LIT> << ABIName << <STR_LIT> <STR_LIT> ;
LLVM,RISCV,672,+ <NUM��|LIT��> ) ;
LLVM,RISCV,673,
LLVM,RISCV,674,;
LLVM,RISCV,675,(TheBackend.getMCInstRegInfo().getBPReg());
LLVM,RISCV,676,unsigned i) {
LLVM,RISCV,677,{
LLVM,RISCV,678,VLMulShift );
LLVM,RISCV,679,& 0b01110000 ) > > 4 );
LLVM,RISCV,680,"unsigned RegNo, MCSubtargetInfo &STI) {"
LLVM,RISCV,681,;
LLVM,RISCV,682,return w * 8;
LLVM,RISCV,683,
LLVM,RISCV,684,2;
LLVM,RISCV,685,flagsearch ? true : false
LLVM,RISCV,686,amp;
LLVM,RISCV,687,amp;
LLVM,RISCV,688,;
LLVM,RISCV,689,amp;
LLVM,RISCV,690,Type<Foo>::vType;
LLVM,RISCV,691,char unit ):
LLVM,RISCV,692,score >= NumOpPerCycle;
LLVM,RISCV,693,: return <STR_LIT> ;
LLVM,RISCV,694,", <STR_LIT> ) . <STR_LIT> ;"
LLVM,RISCV,695,
LLVM,RISCV,696,
LLVM,RISCV,697,;
LLVM,RISCV,698,
LLVM,RISCV,699,) ) ;
LLVM,RISCV,700,( ) ;
LLVM,RISCV,701,false ;
LLVM,RISCV,702,;
LLVM,RISCV,703,
LLVM,RISCV,704,"<USER_LABEL> Args ,  <USER_LABEL> LCLOps ) {"
LLVM,RISCV,705,MI ;
LLVM,RISCV,706,) ;
LLVM,RISCV,707,Instruction</ISA_LIT>();
LLVM,RISCV,708,;
LLVM,RISCV,709,Name :: {
LLVM,RISCV,710,;
LLVM,RISCV,711,<NUM_LIT> ) . getReg ( ) ;
LLVM,RISCV,712,"( ), true, m isa littlete={"
LLVM,RISCV,713,nullptr ;
LLVM,RISCV,714,;
LLVM,RISCV,715,ISA_LITSubtarget & ST = MF.getSubtarget;
LLVM,RISCV,716,return ( ~(-( Length &0X7 ) ) & 0x7 );
LLVM,RISCV,717,else {
LLVM,RISCV,718,( Size ) ) - }
LLVM,RISCV,719,) ) - Size ) ;
LLVM,RISCV,720,) ;
LLVM,RISCV,721,
LLVM,RISCV,722,"->getContext().getTypeRefAsString(GV->getFunctionType(), true);"
LLVM,RISCV,723,"getContext ( ) , Value :: ConstantPoolVal , <TOK_CHAR> ) <CONSTANTDATA> ( ) {"
LLVM,RISCV,724,()}
LLVM,RISCV,725,();
LLVM,RISCV,726,
LLVM,RISCV,727,override {
LLVM,RISCV,728,) ;
LLVM,RISCV,729,;
LLVM,RISCV,730,"Address , const void *Decoder ) {"
LLVM,RISCV,731,Success ;
LLVM,RISCV,732,Fail;
LLVM,RISCV,733,( Reg ));
LLVM,RISCV,734,RegNo ;
LLVM,RISCV,735,_Fail;
LLVM,RISCV,736,Reg ) );
LLVM,RISCV,737,", IsRV32E ?  XLen  :  ) ."
LLVM,RISCV,738,Success ( Inst ) ;
LLVM,RISCV,739,( <NUM_LIT> ) ) ;
LLVM,RISCV,740,Couldn't decode packed operand! );
LLVM,RISCV,741,", Address , Decoder ) ;"
LLVM,RISCV,742,", Decoder ) ;"
LLVM,RISCV,743,Success ;
LLVM,RISCV,744,) Result ;
LLVM,RISCV,745,());
LLVM,RISCV,746,".descFeatures , T.hasCustomDisassembler ) ;"
LLVM,RISCV,747,) ;
LLVM,RISCV,748,{
LLVM,RISCV,749,<NUM_LIT> ( Reg ) ;
LLVM,RISCV,750,) ;
LLVM,RISCV,751,"``` . DecodeRCRRegisterClass ( Inst , <NUM_LIT> , Address , Decoder ) ;"
LLVM,RISCV,752,return MCDisassembler::Fail;
LLVM,RISCV,753,const void *Decoder) {
LLVM,RISCV,754,));
LLVM,RISCV,755,;
LLVM,RISCV,756,Fail;
LLVM,RISCV,757,success ;
LLVM,RISCV,758,( Reg ));
LLVM,RISCV,759,
LLVM,RISCV,760,) ;
LLVM,RISCV,761,Success ;
LLVM,RISCV,762,Cast [ <STR_LIT> <STR_LIT> <STR_LIT> {
LLVM,RISCV,763,Success ;
LLVM,RISCV,764,( Reg ) ) ;
LLVM,RISCV,765,)) ;
LLVM,RISCV,766,<NUM_LIT> ;
LLVM,RISCV,767,
LLVM,RISCV,768,Success ;
LLVM,RISCV,769,Success ;
LLVM,RISCV,770,success ;
LLVM,RISCV,771,Success ;
LLVM,RISCV,772,", int64_t &SImm ) {"
LLVM,RISCV,773,) && Invalid immediate );
LLVM,RISCV,774,) ;
LLVM,RISCV,775,) ;
LLVM,RISCV,776,INST_UNKNOWN ;
LLVM,RISCV,777,
LLVM,RISCV,778,Fail ;
LLVM,RISCV,779,createReg ( Reg ) ) ;
LLVM,RISCV,780,<NUM_LIT> ;
LLVM,RISCV,781,Size ) ;
LLVM,RISCV,782,", Address , Decoder );"
LLVM,RISCV,783,Decoder );
LLVM,RISCV,784,) ;
LLVM,RISCV,785,Success ;
LLVM,RISCV,786,Success ;
LLVM,RISCV,787,;
LLVM,RISCV,788,;
LLVM,RISCV,789,] ;
LLVM,RISCV,790,return Fail ;
LLVM,RISCV,791,;
LLVM,RISCV,792,
LLVM,RISCV,793,( Address ) ) ;
LLVM,RISCV,794,createReg ( Reg ));
LLVM,RISCV,795,MRI . getReg( <REGENTRIED> );
LLVM,RISCV,796,:: Success ;
LLVM,RISCV,797,createReg ( Reg )) ;
LLVM,RISCV,798,( RegNo <NUM_LIT>) ;
LLVM,RISCV,799,RegNo ;
LLVM,RISCV,800,. <STR_LIT> ;
LLVM,RISCV,801,"Decoder , MRI ) ;"
LLVM,RISCV,802,>= 3 ) {
LLVM,RISCV,803,const void *Decoder ) = delete ;
LLVM,RISCV,804,;
LLVM,RISCV,805,<NUM_LIT> return MCDisassembler :: Success ;
LLVM,RISCV,806,createReg<i> ( Reg ));
LLVM,RISCV,807,", 7 , 5 );"
LLVM,RISCV,808,Success ;
LLVM,RISCV,809,", Decoder) ;"
LLVM,RISCV,810,;
LLVM,RISCV,811,", Imm );"
LLVM,RISCV,812,( Imm ) ) ) ;
LLVM,RISCV,813,:: Success ;
LLVM,RISCV,814,Fail;
LLVM,RISCV,815,", P );"
LLVM,RISCV,816,Success ;
LLVM,RISCV,817,Success ;
LLVM,RISCV,818,Reg ) ) ;
LLVM,RISCV,819,) ;
LLVM,RISCV,820,"Address , const void * ) {"
LLVM,RISCV,821,);
LLVM,RISCV,822,;
LLVM,RISCV,823,createReg ( Reg ));
LLVM,RISCV,824,] ;
LLVM,RISCV,825,:: Success ;
LLVM,RISCV,826,
LLVM,RISCV,827,<STR_LIT> }
LLVM,RISCV,828,"SI, Imm, DL ) && ( <NUM_LIT> != llvm :: <STR_LIT> || <STR_LIT> < 0 ) ) assert ( isUInt < <NUM_LIT> > ( Imm ) && Invalid shift amount!) ;"
LLVM,RISCV,829,) ) ;
LLVM,RISCV,830,Reg ) ) ;
LLVM,RISCV,831,", Address , Decoder ) ;"
LLVM,RISCV,832,"1 , RegNo == 18 , RegNo == 19 ) {"
LLVM,RISCV,833,:: Success ;
LLVM,RISCV,834,Fail ;
LLVM,RISCV,835,return MCDisassembler :: Fail ;
LLVM,RISCV,836,;
LLVM,RISCV,837,Fail ;
LLVM,RISCV,838,) || isInt < N > ( Imm ) );
LLVM,RISCV,839,) ;
LLVM,RISCV,840,") , createE< ISA_LIT > ILP32Disassembler );"
LLVM,RISCV,841,">(<ISA_LIT>OS, BSS, Kind);"
LLVM,RISCV,842,"std::move(OS), BinaryType, Ctx));"
LLVM,RISCV,843,R_<ISA_LIT>_CALL_PLT ;
LLVM,RISCV,844,": if the symbol has a different section than the current one, or if it is a PC-relative symbol and the Type is not PC-relative."
LLVM,RISCV,845,<STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ;
LLVM,RISCV,846,;
LLVM,RISCV,847,bool is64Bit ) {
LLVM,RISCV,848,:: R_<ISA_LIT>_CALL ;
LLVM,RISCV,849,"MCELFObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI , bool Is64Bit ) {"
LLVM,RISCV,850,Is64Bit ) ;
LLVM,RISCV,851,Fixup.getType () != ( <STR_LIT>( MCFixupKind ) ELF :: FK_Data_8));
LLVM,RISCV,852,R ;
LLVM,RISCV,853,<STR_LIT> : return ELF :: R_<ISA_LIT>_SUB64 ;
LLVM,RISCV,854,:: R_<ISA_LIT>_TLSGD_ADD ;
LLVM,RISCV,855,return ELF :: R_<ISA_LIT>_NONE ;
LLVM,RISCV,856,FK_Move_Size_0 : return ELF :: R_<ISA_LIT>_SCAN ;
LLVM,RISCV,857,<STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ;
LLVM,RISCV,858,<STR_LIT> : return ELF :: R_<ISA_LIT>_JALX ;
LLVM,RISCV,859,;
LLVM,RISCV,860,FK_Data_Add_8 : return ELF :: R_<ISA_LIT>_ADD64 ;
LLVM,RISCV,861,"MCStreamer & Streamer, MCSymbolRefExpr :: VariantKind VK}"
LLVM,RISCV,862,: return ELF :: R_<ISA_LIT>_DTPREL_HI20 ;
LLVM,RISCV,863,UseLocation : Result += getULEB128Size( item.LocIdx );
LLVM,RISCV,864,;
LLVM,RISCV,865,function displayText() {
LLVM,RISCV,866,
LLVM,RISCV,867,
LLVM,RISCV,868,
LLVM,RISCV,869,{
LLVM,RISCV,870,"+ 4, A, static_cast < MCFixupKind > ( Sub ) , Loc ) ) ;"
LLVM,RISCV,871,"df->getFixups().push_back(MCFixup::create(DF->getContents().size(), C, static_cast <MCFixupKind>(Mul), Loc));"
LLVM,RISCV,872,EFlags ) ;
LLVM,RISCV,873,) ;
LLVM,RISCV,874,", <STR_LIT> with different values ) ;"
LLVM,RISCV,875,"<STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,876,) const {
LLVM,RISCV,877,Streamer);
LLVM,RISCV,878,
LLVM,RISCV,879,. isInSection ( ) ? B . getSection ( ) . hasInstructions ( ) : ! B . getName ( ) . empty ( )  >
LLVM,RISCV,880,( ) ) -> reset ( ) ;
LLVM,RISCV,881,MAB . getABI ( ) ) ) ;
LLVM,RISCV,882,
LLVM,RISCV,883,) ;
LLVM,RISCV,884,( <STR_LIT> ) ;
LLVM,RISCV,885,push_back ( CapFixup ) ;
LLVM,RISCV,886,);
LLVM,RISCV,887,) ;
LLVM,RISCV,888,::EF_<ISA_LIT>_N2K }
LLVM,RISCV,889,
LLVM,RISCV,890,) . addReg ( DestReg ) . addReg ( IncrReg ) ;
LLVM,RISCV,891,( MBB . getSubtarget ( ). getRegisterInfo ( ) ) ;
LLVM,RISCV,892,DoneMBB ) ;
LLVM,RISCV,893,"TRI -> getSubReg ( CmpValReg , <STR_LIT> ) ) . addMBB ( LoopHeadMBB ) ;"
LLVM,RISCV,894,"( PtrIsCap , Ordering ) ;"
LLVM,RISCV,895,"( PtrIsCap , Ordering ) ;"
LLVM,RISCV,896,<STR_LIT> ;
LLVM,RISCV,897,<STR_LIT> : <STR_LIT> ;
LLVM,RISCV,898,SequentiallyConsistent : return PtrIsCap ?  acquire :  release;
LLVM,RISCV,899,<STR_LIT> ;
LLVM,RISCV,900,: <STR_LIT>  <STR_LIT> ASSERT(ptr.is_cap());
LLVM,RISCV,901,AcquireRelease : return <STR_LIT> ;
LLVM,RISCV,902,"getSCForRMW64 ( PtrIsCap , Ordering );"
LLVM,RISCV,903,<STR_LIT> ;
LLVM,RISCV,904,<STR_LIT> ;
LLVM,RISCV,905,:: AcquireRelease : return PtrIsCap ? <STR_LIT> : <STR_LIT>;
LLVM,RISCV,906,<STR_LIT> ) : ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) ;
LLVM,RISCV,907,
LLVM,RISCV,908,AsmExpandAtomicPseudo();
LLVM,RISCV,909,( ScratchReg ) . addReg ( SrcReg ) ;
LLVM,RISCV,910,": BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( RegisterMask ) . addImm ( <NUM_LIT> ) ;"
LLVM,RISCV,911,DestReg );
LLVM,RISCV,912,) ;
LLVM,RISCV,913,. addMBB ( LoopTailMBB ) ;
LLVM,RISCV,914,", NextMBBI ) OR {"
LLVM,RISCV,915,", <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,916,;
LLVM,RISCV,917,<STR_LIT> ;
LLVM,RISCV,918,: return <STR_LIT> ;
LLVM,RISCV,919,override {
LLVM,RISCV,920,Hello Name;
LLVM,RISCV,921,StopAtFull;
LLVM,RISCV,922,<STR_LIT> ;
LLVM,RISCV,923,: return <STR_LIT> ;
LLVM,RISCV,924,;
LLVM,RISCV,925,
LLVM,RISCV,926,getPassRegistry () ) ;
LLVM,RISCV,927,
LLVM,RISCV,928,) {
LLVM,RISCV,929,Pass();
LLVM,RISCV,930,Pass();
LLVM,RISCV,931,{
LLVM,RISCV,932,else if ( StartOffset == <NUM_LIT> && EndOffset == <NUM_LIT> ) {
LLVM,RISCV,933,;
LLVM,RISCV,934,"<STR_LIT> : return expandReadMem ( MBB , MBBI , <NUM_LIT> ) ;"
LLVM,RISCV,935,( NewMBB ) ;
LLVM,RISCV,936,) ;
LLVM,RISCV,937,
LLVM,RISCV,938,JALR);
LLVM,RISCV,939,"CurrentOpcode , SecondOpcode , KillSrc , AR . getRegister ( ) , VR . getImm ( ) , MF ) ;"
LLVM,RISCV,940,;
LLVM,RISCV,941,
LLVM,RISCV,942,;
LLVM,RISCV,943,LoopTailMBB ) ;
LLVM,RISCV,944,LoopIfBodyMBB ->addSuccessor (LoopTailMBB);
LLVM,RISCV,945,"DAG , TRI , <NUM_LIT> ) ;"
LLVM,RISCV,946,( NewMBB ) ;
LLVM,RISCV,947,:
LLVM,RISCV,948,) == <STR_LIT> ) ;
LLVM,RISCV,949,) ) ;
LLVM,RISCV,950,ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ;
LLVM,RISCV,951,) . getImm ( ) ) ;
LLVM,RISCV,952,": <STR_LIT> This code snippet contains a series of cases, each of which consists of a <STR_LIT> followed by a colon (:). The last statement is an expanded VSPILL, which passes in the MBB and MBBI parameters to the expandVSPILL function."
LLVM,RISCV,953,( ) {
LLVM,RISCV,954,) + <NUM_LIT> ;
LLVM,RISCV,955,"<STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Sub , true , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,956,;
LLVM,RISCV,957,
LLVM,RISCV,958,;
LLVM,RISCV,959,Xchg : LLVMContext & Ctx = MI . <[:o:]> <ANSWER>: getContext();
LLVM,RISCV,960,( <NUM_LIT> ) . getImm ( ) );
LLVM,RISCV,961,
LLVM,RISCV,962,
LLVM,RISCV,963,) . addMBB ( LoopHeadMBB ) ;
LLVM,RISCV,964,. addReg ( NewValReg ) . addReg ( MaskReg ) ;
LLVM,RISCV,965,addReg ( ShamtReg ) ;
LLVM,RISCV,966,": return expandStoreLocalAddress ( MBB , MBBI , NextMBBI ) ;"
LLVM,RISCV,967,"Sub : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ;"
LLVM,RISCV,968,addReg ( <STR_LIT> ) ;
LLVM,RISCV,969,"<STR_LIT> : return expandAtomicOp ( MBB , MBBI , AtomicRMWInst :: And , true , NextMBBI ) ;"
LLVM,RISCV,970,": return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: And , true , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,971,) ;
LLVM,RISCV,972,);
LLVM,RISCV,973,) ;
LLVM,RISCV,974,{
LLVM,RISCV,975,", FirstOpcode , SecondOpcode , FlagsHi );"
LLVM,RISCV,976,) ;
LLVM,RISCV,977,...) ;
LLVM,RISCV,978,Modified ;
LLVM,RISCV,979,( <ISA_LIT> );
LLVM,RISCV,980,() ;
LLVM,RISCV,981,return ISA_EXPAND_PSEUDO_NAME;
LLVM,RISCV,982,
LLVM,RISCV,983,( ) ) ;
LLVM,RISCV,984,. getMaxCallFrameSize ( ) ;
LLVM,RISCV,985,= {
LLVM,RISCV,986,) {
LLVM,RISCV,987,|| MFI .adjustStackAlignment ( MF );
LLVM,RISCV,988,":: Implicit  addImm(Amount).addImm(Flag).addReg(TII -> get(Opc), RegState::Implicit);"
LLVM,RISCV,989,", <NUM_LIT> ) ) {"
LLVM,RISCV,990,return false ;
LLVM,RISCV,991,++i ) {
LLVM,RISCV,992,( ) ) ) {
LLVM,RISCV,993,) ;
LLVM,RISCV,994,_32 ( MaxAlignment ) ;
LLVM,RISCV,995,
LLVM,RISCV,996,
LLVM,RISCV,997,) ;
LLVM,RISCV,998,STI.getInstrInfo()->getRegisterInfo()-><FP>;
LLVM,RISCV,999,;
LLVM,RISCV,1000,<STR_LIT> }
LLVM,RISCV,1001,STI.getSPReg();
LLVM,RISCV,1002,Register( 12 );
LLVM,RISCV,1003,>Value<;
LLVM,RISCV,1004,
LLVM,RISCV,1005,case TargetStackID :: MainMultithreaded : return false;
LLVM,RISCV,1006,getFrameIndex ( ) ;
LLVM,RISCV,1007,( ) == TII . getCallFrameDestroyOpcode ( ) ) {
LLVM,RISCV,1008,;
LLVM,RISCV,1009,-Val ;
LLVM,RISCV,1010,(FrameSize) ;
LLVM,RISCV,1011,) ;
LLVM,RISCV,1012,) ;
LLVM,RISCV,1013,) ) ;
LLVM,RISCV,1014,MachineInstr :: FrameSetup )  > RVFI->getVarArgsSaveSize();
LLVM,RISCV,1015,
LLVM,RISCV,1016,Feature feature) {
LLVM,RISCV,1017,){
LLVM,RISCV,1018,return TargetStackID::Vector(ID) .
LLVM,RISCV,1019,<ISA_LIT>Stack : llvm_unreachable(Unhandled target stack.);
LLVM,RISCV,1020,
LLVM,RISCV,1021,;
LLVM,RISCV,1022,AutomationMBBI = std::next(MBBI);
LLVM,RISCV,1023,MachineInstr :: FrameDestroy ) ;
LLVM,RISCV,1024,) ) {
LLVM,RISCV,1025,
LLVM,RISCV,1026,) {
LLVM,RISCV,1027,) ;
LLVM,RISCV,1028,;
LLVM,RISCV,1029,& MBB ) {
LLVM,RISCV,1030,getFlag ( MachineInstr :: FrameSetup ) ) NewMI -> setFlag ( MachineInstr :: FrameSetup ) ;
LLVM,RISCV,1031,) ;
LLVM,RISCV,1032,) ;
LLVM,RISCV,1033,) ;
LLVM,RISCV,1034,) ;
LLVM,RISCV,1035,", StackAlign) ;"
LLVM,RISCV,1036,;
LLVM,RISCV,1037,
LLVM,RISCV,1038,"SPReg ) . addReg ( SPReg ) . addReg ( VR ) . adjustReg ( MBB , MBBI , DL , SPReg , SPReg ,<TYPE> , MachineInstr :: FrameSetup );"
LLVM,RISCV,1039,+ StackSize ;
LLVM,RISCV,1040,= MFI . getCalleeSavedInfo ( ) ;
LLVM,RISCV,1041,
LLVM,RISCV,1042,: *MBB . succ_begin ( );
LLVM,RISCV,1043,"<ISA_REG>, false );"
LLVM,RISCV,1044,;
LLVM,RISCV,1045,-> getRealStackSize ( ) ;
LLVM,RISCV,1046,-> getStackSize ( ) ;
LLVM,RISCV,1047,) ) {
LLVM,RISCV,1048,;
LLVM,RISCV,1049,<NUM_LIT> ;
LLVM,RISCV,1050,MFI.getInteger(unsigned FramePtr);
LLVM,RISCV,1051,) ;
LLVM,RISCV,1052,) && Frame pointer needed! ) ;
LLVM,RISCV,1053,;
LLVM,RISCV,1054,;
LLVM,RISCV,1055,) && LVFI -> hasVAStart ());
LLVM,RISCV,1056,
LLVM,RISCV,1057,RI -> hasStackRealignment ( MF ) || RVVStackSize || FirstSPAdjustAmount < <STR_LIT> ) {
LLVM,RISCV,1058,<STR_LIT> ;
LLVM,RISCV,1059,<STR_LIT> ;
LLVM,RISCV,1060,
LLVM,RISCV,1061,
LLVM,RISCV,1062,uint64_t{
LLVM,RISCV,1063,{
LLVM,RISCV,1064,RVFI -> getLibCallStackSize ( ) ;
LLVM,RISCV,1065,0 && <STR_LIT> ) ;
LLVM,RISCV,1066,MachineFunction & MF ) const try {
LLVM,RISCV,1067,CFI_INSTRUCTION<NUM_LIT>) ) . addCFIIndex ( CFIIndex ) ;
LLVM,RISCV,1068,
LLVM,RISCV,1069,
LLVM,RISCV,1070,
LLVM,RISCV,1071,) - FirstSPAdjustAmount ;
LLVM,RISCV,1072,"( MF ) ) <NUM_LIT>FrameRealignmentSaveIndex = MF . addFrameInst ( MCCFIInstruction :: cfiOffset ( nullptr , RI -> getDwarfRegNum ( <ISA_LIT> :: <STR_LIT> , true ) , - <NUM_LIT>FrameRealignmentSaveIndex <LBRACKET>SPReg<RBRACKET> + <NUM_LIT> - TotalRealignment ) ) ;"
LLVM,RISCV,1073,Relocation not implemented for this target );
LLVM,RISCV,1074,{
LLVM,RISCV,1075,<STR_LIT> ) ;
LLVM,RISCV,1076,
LLVM,RISCV,1077,::FrameDestroy) ;
LLVM,RISCV,1078,"MFI . getFrameSize ( ) , MachineInstr :: FrameSetup ) ;"
LLVM,RISCV,1079,", & SPRI , RC , DL ) ;"
LLVM,RISCV,1080,) ;
LLVM,RISCV,1081,;
LLVM,RISCV,1082,getMaxAlignment ( ) : RI -> get <ISA_LIT>YearStackAlign ( MF ) ;
LLVM,RISCV,1083,<CONST_LIT> getStackSize ( ) ;
LLVM,RISCV,1084,getStackSize ( ) ;
LLVM,RISCV,1085,
LLVM,RISCV,1086,<VAR_LIT> ;
LLVM,RISCV,1087,{
LLVM,RISCV,1088,<NUM_LIT><NUM_LIT> )) ;
LLVM,RISCV,1089,<STR_LIT> Offset + Offset + Entry . getStackSize ( ) ) {
LLVM,RISCV,1090,getReg ( ) ;
LLVM,RISCV,1091,) . <STR_LIT> }
LLVM,RISCV,1092,. addImm ( <NUM_LIT> << ShiftAmount ) ;
LLVM,RISCV,1093,( ) ;
LLVM,RISCV,1094,StackSize ) ) ;
LLVM,RISCV,1095,", < <ISA_LIT>MachineInstr :: <IN_ LIT>>  Add a MachineInstr::FrameSetup argument to the adjustReg function call. This additional argument specifies the type of frame instruction, which in this case is MachineInstr::FrameSetup."
LLVM,RISCV,1096,
LLVM,RISCV,1097,
LLVM,RISCV,1098,ISA_LIT> ( ) ;
LLVM,RISCV,1099,) ;
LLVM,RISCV,1100,-> needsStackRealignment ( MF ) ;
LLVM,RISCV,1101,getMaxAlign ( ) ;
LLVM,RISCV,1102,<STR_LIT> }
LLVM,RISCV,1103,) ;
LLVM,RISCV,1104,) - FirstSPAdjustAmount ;
LLVM,RISCV,1105,"MBB , LastFrameDestroy ) ;"
LLVM,RISCV,1106,) ;
LLVM,RISCV,1107,( ) ;
LLVM,RISCV,1108,) ;
LLVM,RISCV,1109,) FrameReg = <STR_LIT> ;
LLVM,RISCV,1110,return <NUM_LIT> ;
LLVM,RISCV,1111,) NonLibcallCSI . push_back ( CS ) ;
LLVM,RISCV,1112,;
LLVM,RISCV,1113,? ) ;
LLVM,RISCV,1114,( ) ;
LLVM,RISCV,1115,
LLVM,RISCV,1116,( ) ;
LLVM,RISCV,1117,{
LLVM,RISCV,1118,Flynn-FI ) ;
LLVM,RISCV,1119,
LLVM,RISCV,1120,
LLVM,RISCV,1121,. addLiveIn ( CS <ISA_LIT> );
LLVM,RISCV,1122,"getFrameIndex ( ) , RC , TRI ) ;"
LLVM,RISCV,1123,getPointerOperand ( ) -> getType ( ) ;
LLVM,RISCV,1124,P ;
LLVM,RISCV,1125,", II -> getArgOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,1126,);
LLVM,RISCV,1127,;
LLVM,RISCV,1128,) ;
LLVM,RISCV,1129,const override {
LLVM,RISCV,1130,->getZExtValue();
LLVM,RISCV,1131,"StartVal , Stride ) ;"
LLVM,RISCV,1132,) ;
LLVM,RISCV,1133,", nullptr ) ;"
LLVM,RISCV,1134,getType ( ) ) ) {
LLVM,RISCV,1135,F ) . <ISA_LIT>getLoopInfo ( ) ;
LLVM,RISCV,1136,) ;
LLVM,RISCV,1137,else if (InstrInfo.VLEnd < VLMul) return true;
LLVM,RISCV,1138,{
LLVM,RISCV,1139,
LLVM,RISCV,1140,) && not a valid SEW value ) ;
LLVM,RISCV,1141,;
LLVM,RISCV,1142,( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) || hasControlFlow ( MI ) ) {
LLVM,RISCV,1143,( ) ] ;
LLVM,RISCV,1144,) ;
LLVM,RISCV,1145,false ;
LLVM,RISCV,1146,;
LLVM,RISCV,1147,false;
LLVM,RISCV,1148,"When comparing , the policy must be valid ) ;"
LLVM,RISCV,1149,. isUnknown ( ) ) ;
LLVM,RISCV,1150,true ;
LLVM,RISCV,1151,ASI();
LLVM,RISCV,1152,getReg ( ) ;
LLVM,RISCV,1153,( ) ] ;
LLVM,RISCV,1154,) ;
LLVM,RISCV,1155,( ) ;
LLVM,RISCV,1156,SEW ) return false ;
LLVM,RISCV,1157,) {
LLVM,RISCV,1158,<NUM_LIT> ) . getImm ( ) ;
LLVM,RISCV,1159,;
LLVM,RISCV,1160,. getImm ( ) ) ;
LLVM,RISCV,1161,) return false;
LLVM,RISCV,1162,. EEW ) ;
LLVM,RISCV,1163,
LLVM,RISCV,1164,{
LLVM,RISCV,1165,{
LLVM,RISCV,1166,( MI <STR_LIT> ) {
LLVM,RISCV,1167,|| VRegDef . isImplicit ( ) ) ) ) {
LLVM,RISCV,1168,
LLVM,RISCV,1169,
LLVM,RISCV,1170,) ) {
LLVM,RISCV,1171,( ) ) {
LLVM,RISCV,1172,) ;
LLVM,RISCV,1173,( ). c_str(  ) ) ;
LLVM,RISCV,1174,
LLVM,RISCV,1175,Require . MaskAgnostic ) {
LLVM,RISCV,1176,) {
LLVM,RISCV,1177,) ;
LLVM,RISCV,1178,( Info . encodeVTYPE ( ) ) ;
LLVM,RISCV,1179,;
LLVM,RISCV,1180,false;
LLVM,RISCV,1181,
LLVM,RISCV,1182,. getImm ( )  && This should be a LAPS opcode ) ;
LLVM,RISCV,1183,
LLVM,RISCV,1184,( ) ;
LLVM,RISCV,1185,;
LLVM,RISCV,1186,NewInfo ;
LLVM,RISCV,1187,", Other . MaskAgnostic );"
LLVM,RISCV,1188,( )cs  Both types must be either Vector or Element type }
LLVM,RISCV,1189,"RegState :: Dead ) .addImm ( Info . encodeVTYPE ( ) ) .addReg ( AVLReg , RegState :: Kill ) .addReg ( AVLReg , RegState :: Implicit ) .<STR_LIT>"
LLVM,RISCV,1190,Other ;
LLVM,RISCV,1191,) ;
LLVM,RISCV,1192,L ;
LLVM,RISCV,1193,;
LLVM,RISCV,1194,":: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Dead ) . addReg ( AVLReg , RegState :: Kill AVLReg, RegState::Implicit);"
LLVM,RISCV,1195,VSETVLILInfo DefInfo = getInfoForVSETVLIL(*DefMI);
LLVM,RISCV,1196,( ) != <STR_LIT> ) ) {
LLVM,RISCV,1197,;
LLVM,RISCV,1198,
LLVM,RISCV,1199,{
LLVM,RISCV,1200,getImm ( ) ;
LLVM,RISCV,1201,
LLVM,RISCV,1202,;
LLVM,RISCV,1203,MI ;
LLVM,RISCV,1204,;
LLVM,RISCV,1205,"false , false ) ) .and reg .and reg VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);"
LLVM,RISCV,1206,"0 , 0 );"
LLVM,RISCV,1207,NewInfo ;
LLVM,RISCV,1208,
LLVM,RISCV,1209,VSETVLIInfo() {
LLVM,RISCV,1210,bool hasAVLReg = true;
LLVM,RISCV,1211,false;
LLVM,RISCV,1212,<STR_LIT> ) ;
LLVM,RISCV,1213,", Other.SEW, Other.TailAgnostic, Other.MaskAgnostic );"
LLVM,RISCV,1214,
LLVM,RISCV,1215,:: Dead ) . addImm ( Info . getAVLImm ( ) ) . addImm ( Info . encodeVTYPE ( ) ) ;
LLVM,RISCV,1216,return Other ;
LLVM,RISCV,1217,vlmulMax == InstrInfo.vlmulMax) {
LLVM,RISCV,1218,return false;
LLVM,RISCV,1219,Unknown;
LLVM,RISCV,1220,== 0 ;
LLVM,RISCV,1221,Invalid ;
LLVM,RISCV,1222,State::Stopped;
LLVM,RISCV,1223,DefMI );
LLVM,RISCV,1224,;
LLVM,RISCV,1225,) ] ;
LLVM,RISCV,1226,MBB ) ;
LLVM,RISCV,1227,) {
LLVM,RISCV,1228,"decodeState ( State , # = IncImm ( ) ) ;"
LLVM,RISCV,1229,NIL ;
LLVM,RISCV,1230,Reg;
LLVM,RISCV,1231,
LLVM,RISCV,1232,) ;
LLVM,RISCV,1233,"1 ) . getImm ( ) , O ) {"
LLVM,RISCV,1234,& OS ){
LLVM,RISCV,1235,
LLVM,RISCV,1236,"BDXAddrOperandInstPrinter::print(MI->getOperand(OpNum).getReg(), MI->getOperand(OpNum).getImm(), O);"
LLVM,RISCV,1237,
LLVM,RISCV,1238,
LLVM,RISCV,1239,
LLVM,RISCV,1240,) ;
LLVM,RISCV,1241,"<< , ;"
LLVM,RISCV,1242,<< getRegisterName( MI -> getOperand ( opNum + 2).getReg());
LLVM,RISCV,1243,"void RegOperandPrinter :: printMemRegOperand ( const MCInst * MI , int opNum ,"
LLVM,RISCV,1244,<STR_LIT> ;
LLVM,RISCV,1245,RegNo ) ;
LLVM,RISCV,1246,;
LLVM,RISCV,1247,getImm ( ) ;
LLVM,RISCV,1248,;
LLVM,RISCV,1249,", O ) ;"
LLVM,RISCV,1250,) ) ;
LLVM,RISCV,1251,O ) ;
LLVM,RISCV,1252,&& Operand is not a literal constant.);
LLVM,RISCV,1253,", OpNum , O ) ;"
LLVM,RISCV,1254,(Value) && This operand should be an unsigned integer );
LLVM,RISCV,1255,;
LLVM,RISCV,1256,getReg ( ) ) ;
LLVM,RISCV,1257,O << 'o' ;
LLVM,RISCV,1258,
LLVM,RISCV,1259,;
LLVM,RISCV,1260,O << <STR_LIT> ;
LLVM,RISCV,1261,uint16_t)ISA_LIT>(Imm);
LLVM,RISCV,1262,;
LLVM,RISCV,1263,ArchRegNames = VAL.GetBool(&Details) ;
LLVM,RISCV,1264,RS << getRegisterName ( MO . getReg ( ) ) ;
LLVM,RISCV,1265,<< 'r' ;
LLVM,RISCV,1266,MAI );
LLVM,RISCV,1267,) ;
LLVM,RISCV,1268,", STI , O ) ;"
LLVM,RISCV,1269,getReg ( ) ) ;
LLVM,RISCV,1270,<< Ediv ;
LLVM,RISCV,1271,
LLVM,RISCV,1272,) ;
LLVM,RISCV,1273,;
LLVM,RISCV,1274,"O , & MAI );"
LLVM,RISCV,1275,Invalid operand ) ;
LLVM,RISCV,1276,"OpNum , O ) ;"
LLVM,RISCV,1277,
LLVM,RISCV,1278,;
LLVM,RISCV,1279,) ;
LLVM,RISCV,1280,getHeaderValue(Int) :  << Value <<  << endl;
LLVM,RISCV,1281,
LLVM,RISCV,1282,!= <NUM_LIT> ) O << 'u' ;
LLVM,RISCV,1283,<< 'b' ;
LLVM,RISCV,1284,& UncompressedMI ) ;
LLVM,RISCV,1285,String ) ;
LLVM,RISCV,1286,", STI , O );"
LLVM,RISCV,1287,;
LLVM,RISCV,1288,
LLVM,RISCV,1289,) ) ) ;
LLVM,RISCV,1290,<STR_LIT>;
LLVM,RISCV,1291,) O << 'u' ;
LLVM,RISCV,1292,<< 'i' ;
LLVM,RISCV,1293,;
LLVM,RISCV,1294,( UncompressedMI ) >;
LLVM,RISCV,1295,"STI , O ) ;"
LLVM,RISCV,1296,( ) ;
LLVM,RISCV,1297,) != <STR_LIT> == 64 ) {
LLVM,RISCV,1298,. addMemOperand ( MMO ) ;
LLVM,RISCV,1299,I -> getOperand (...ThisCond [ <NUM_LIT> ] . getImm ( ) ... ) }
LLVM,RISCV,1300,) ;
LLVM,RISCV,1301,": is a function that returns a value of type bool. It takes in a parameter of type MachineBasicBlock::iterator named MI and is const, meaning it does not modify any data members of the class InstrInfo. This function executes a switch statement on the opcode of the instruction MI is pointing to."
LLVM,RISCV,1302,;
LLVM,RISCV,1303,;
LLVM,RISCV,1304,;
LLVM,RISCV,1305,Cond [ <NUM_LIT> ] . getReg ( ) ) ;
LLVM,RISCV,1306,( <NUM_LIT> ) ;
LLVM,RISCV,1307,FrameIndex ) ;
LLVM,RISCV,1308,. getImm ( ) ;
LLVM,RISCV,1309,
LLVM,RISCV,1310,. addImm ( Value ) ;
LLVM,RISCV,1311,(LoadOpcode) )) <= (MemoryReference ( RC ));
LLVM,RISCV,1312,;
LLVM,RISCV,1313,;
LLVM,RISCV,1314,
LLVM,RISCV,1315,: WidthB ;
LLVM,RISCV,1316,) ) ;
LLVM,RISCV,1317,Opc ) ) ;
LLVM,RISCV,1318,LMul ;
LLVM,RISCV,1319,
LLVM,RISCV,1320,&gt;
LLVM,RISCV,1321,1 ) . getImm ( ) ;
LLVM,RISCV,1322,+ NF ) + <NUM_LIT> ;
LLVM,RISCV,1323,return false ;
LLVM,RISCV,1324,{
LLVM,RISCV,1325,}
LLVM,RISCV,1326,{
LLVM,RISCV,1327,TII <STR_LIT> ) . add ( <NUM_LIT> ) . addMBB ( FBB ) ;
LLVM,RISCV,1328,The last statement is: And use the newly scavenged register as the destination for the MI instruction.
LLVM,RISCV,1329,") + <STR_LIT> ) , 0U ) ) ;"
LLVM,RISCV,1330,<STR_LIT>: <STR_LIT>: end;
LLVM,RISCV,1331,GetSExtValue ( EncodedImm );
LLVM,RISCV,1332,:
LLVM,RISCV,1333,F . getSection ( ) ;
LLVM,RISCV,1334,;
LLVM,RISCV,1335,getImm ( ) ;
LLVM,RISCV,1336,;
LLVM,RISCV,1337,( ) ;
LLVM,RISCV,1338,;
LLVM,RISCV,1339,<STR_LIT> : default:   break;
LLVM,RISCV,1340,) . isRW () ;
LLVM,RISCV,1341,", <REG_LIT> ) ;"
LLVM,RISCV,1342,isConditionalBranch ( ) && Expected conditional branch . ) ;
LLVM,RISCV,1343,;
LLVM,RISCV,1344,( CC ) ) ;
LLVM,RISCV,1345,;
LLVM,RISCV,1346,<NUM_LIT> ;
LLVM,RISCV,1347,);
LLVM,RISCV,1348,return outliner::InstrType::Legal.
LLVM,RISCV,1349,Parametrized):
LLVM,RISCV,1350,( ) ;
LLVM,RISCV,1351,) ;
LLVM,RISCV,1352,getImm ( ) ;
LLVM,RISCV,1353,FrameIndex ;
LLVM,RISCV,1354,<STR_LIT> );
LLVM,RISCV,1355,;
LLVM,RISCV,1356,{
LLVM,RISCV,1357,Opcode = Is64Bit ? TII->storeRegToStackSlot64 : TII->storeRegToStackSlot
LLVM,RISCV,1358,MI ) ;
LLVM,RISCV,1359,<STR_LIT> ) . setMIFlag ( Flag ) ;
LLVM,RISCV,1360,false ;
LLVM,RISCV,1361,) ;
LLVM,RISCV,1362,;
LLVM,RISCV,1363,) ;
LLVM,RISCV,1364,<RV_LIT>;
LLVM,RISCV,1365,
LLVM,RISCV,1366,\&MI) {
LLVM,RISCV,1367,<STR_LIT> );
LLVM,RISCV,1368,( & FallthroughBB ) ;
LLVM,RISCV,1369,
LLVM,RISCV,1370,
LLVM,RISCV,1371,addReg ( SrcReg EVENT_LIT );
LLVM,RISCV,1372,DL;
LLVM,RISCV,1373,{
LLVM,RISCV,1374,) ;
LLVM,RISCV,1375,...RC) {
LLVM,RISCV,1376,:: COPY : return <NUM_LIT> ;
LLVM,RISCV,1377,"MachineMemOperand :: MODere adWrite , MFI - > getObjectSize ( FI ) , MFI - > get ObjectOffset ( FI ) , I - > getDebugLoc ( )"
LLVM,RISCV,1378,= <STR_LIT> ;
LLVM,RISCV,1379,( ScaledRegister ) . addReg ( VL ) ;
LLVM,RISCV,1380,getParent ( ) ;
LLVM,RISCV,1381,"( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) }"
LLVM,RISCV,1382,Kill ) ;
LLVM,RISCV,1383,"DL , TII . get ( Opc ) , DstReg ) ;"
LLVM,RISCV,1384,1 << (Log2SEW);
LLVM,RISCV,1385,Illegal ;
LLVM,RISCV,1386,:: InstrType :: Meta;
LLVM,RISCV,1387,true;
LLVM,RISCV,1388,
LLVM,RISCV,1389,
LLVM,RISCV,1390,) ;
LLVM,RISCV,1391,FI ) ;
LLVM,RISCV,1392,;
LLVM,RISCV,1393,;
LLVM,RISCV,1394,getImm ( <ISA_LIT>;
LLVM,RISCV,1395,: return Register:: <STR_LIT> ;
LLVM,RISCV,1396,{
LLVM,RISCV,1397,", MO_CCALL + 1 ) ;"
LLVM,RISCV,1398,;
LLVM,RISCV,1399,TBB ) . add <NUM_LIT> ( <NUM_LIT> ) . add <REGUNIT_TRAIT_RW_ASM> ( <REG_UNIT2_LIT> ) ;
LLVM,RISCV,1400,) ;
LLVM,RISCV,1401,:
LLVM,RISCV,1402,: return MI .<STR_LIT> GE;
LLVM,RISCV,1403,<STR_LIT> : llvm_unreachable ( <STR_LIT> ) ;
LLVM,RISCV,1404,:				 0;
LLVM,RISCV,1405,<STR_LIT> : return <NUM_LIT> ;
LLVM,RISCV,1406,The last statement is: FrameIndex = MI.getOperand(<NUM_LIT>).getIndex();
LLVM,RISCV,1407,) ) Opcode = <STR_LIT> ;
LLVM,RISCV,1408,<STR_LIT> ;
LLVM,RISCV,1409,: return <NUM_LIT> ;
LLVM,RISCV,1410,false ;
LLVM,RISCV,1411,;
LLVM,RISCV,1412,":return isIntN (BrOffset, SignExtend64 (IR[<REG>]))"
LLVM,RISCV,1413,;
LLVM,RISCV,1414,Invalid condition. );
LLVM,RISCV,1415,) ;
LLVM,RISCV,1416,. getReg ( ) ;
LLVM,RISCV,1417,) . getReg ( ) ;
LLVM,RISCV,1418,( ) ;
LLVM,RISCV,1419,addImm ( <NUM_LIT> ) ;
LLVM,RISCV,1420,;
LLVM,RISCV,1421,. complete ( ) ;
LLVM,RISCV,1422,I->getDebugLoc ();
LLVM,RISCV,1423,
LLVM,RISCV,1424,"getInfo < = <REG_LIT> ( N , <NUM_LIT> ) ;"
LLVM,RISCV,1425,) assert ( isInt < <NUM_LIT> > ( NumOfVReg ) && <STR_LIT> ) ;
LLVM,RISCV,1426,) Opcode = <STR_LIT> ;
LLVM,RISCV,1427,
LLVM,RISCV,1428,) ;
LLVM,RISCV,1429,VARIANT_2;
LLVM,RISCV,1430,Result ;
LLVM,RISCV,1431,:: Kill ) . setMIFlag  ( <REG_STATE> ) ;
LLVM,RISCV,1432,( ) ) ;
LLVM,RISCV,1433,{
LLVM,RISCV,1434,{
LLVM,RISCV,1435,;
LLVM,RISCV,1436,{
LLVM,RISCV,1437,;
LLVM,RISCV,1438,", DL ) ;"
LLVM,RISCV,1439,Cond [ <NUM_LIT> ] . getReg ( ) ) ;
LLVM,RISCV,1440,
LLVM,RISCV,1441,
LLVM,RISCV,1442,);
LLVM,RISCV,1443,
LLVM,RISCV,1444,;
LLVM,RISCV,1445,);
LLVM,RISCV,1446,;
LLVM,RISCV,1447,
LLVM,RISCV,1448,<ISA_LIT> ( <STR_LIT> ).addReg ( RotatingPar <STR_LIT> );
LLVM,RISCV,1449,;
LLVM,RISCV,1450,) ;
LLVM,RISCV,1451,;
LLVM,RISCV,1452,false ;
LLVM,RISCV,1453,<REG_LIT>;
LLVM,RISCV,1454,
LLVM,RISCV,1455,( Lo12 ) . addReg ( <REG_LIT> ) ;
LLVM,RISCV,1456,<NUM_LIT> ) ) ;
LLVM,RISCV,1457,) ;
LLVM,RISCV,1458,+= getInstSizeInBytes ( * I ) ;
LLVM,RISCV,1459,<STR_LIT> ;
LLVM,RISCV,1460,;
LLVM,RISCV,1461,
LLVM,RISCV,1462,addImm ( <NUM_LIT> ) ;
LLVM,RISCV,1463,);
LLVM,RISCV,1464,;
LLVM,RISCV,1465,) ) {
LLVM,RISCV,1466,:: Level ol );
LLVM,RISCV,1467,{
LLVM,RISCV,1468,", Op0 , cast < ConstantSDNode > ( Op1 ) ) ;"
LLVM,RISCV,1469,TestOffset ;
LLVM,RISCV,1470,") , VT ) ;"
LLVM,RISCV,1471,CI .getValueType() ) ;
LLVM,RISCV,1472,{
LLVM,RISCV,1473,Val >= 0 );
LLVM,RISCV,1474,{
LLVM,RISCV,1475,;
LLVM,RISCV,1476,runOnMachineFunction (MF);
LLVM,RISCV,1477,<STR_LIT> ;
LLVM,RISCV,1478,
LLVM,RISCV,1479,;
LLVM,RISCV,1480,
LLVM,RISCV,1481,
LLVM,RISCV,1482,Addr ;
LLVM,RISCV,1483,"DL , VT , Lower, Upper ) ;"
LLVM,RISCV,1484,
LLVM,RISCV,1485,Dst );
LLVM,RISCV,1486,", ShAmt ) ;"
LLVM,RISCV,1487,
LLVM,RISCV,1488,<STR_LIT> ) ;
LLVM,RISCV,1489,true ;
LLVM,RISCV,1490,"( ) , OpndIdx = <NUM_LIT> ;"
LLVM,RISCV,1491,Root ) {
LLVM,RISCV,1492,32 ) ;
LLVM,RISCV,1493,-- Position ;
LLVM,RISCV,1494,;
LLVM,RISCV,1495,false;
LLVM,RISCV,1496,) ) {
LLVM,RISCV,1497,", <STR_LIT> ) ;"
LLVM,RISCV,1498,) ;
LLVM,RISCV,1499,
LLVM,RISCV,1500,;
LLVM,RISCV,1501,isUInt < <NUM_LIT> > ( SplatImm ) ;
LLVM,RISCV,1502,;
LLVM,RISCV,1503,++ I ) {
LLVM,RISCV,1504,
LLVM,RISCV,1505,IndexLMUL ) ) ;
LLVM,RISCV,1506,
LLVM,RISCV,1507,. getScalarSizeInBits ( ) ) ;
LLVM,RISCV,1508,{
LLVM,RISCV,1509,<STR_LIT> ( TSFlags ) && The function 'isUndef()' is not supported by the MaskedMCID class. );
LLVM,RISCV,1510,{
LLVM,RISCV,1511,) ;
LLVM,RISCV,1512,<NUM_LIT> ) );
LLVM,RISCV,1513,);
LLVM,RISCV,1514,"CombinedOffset , CP -> getTargetFlags ( ) ) ;"
LLVM,RISCV,1515,) ) ;
LLVM,RISCV,1516,", <STR_LIT> ) ;"
LLVM,RISCV,1517,", XLenVT , SDImm , SrcReg ) ;"
LLVM,RISCV,1518,;
LLVM,RISCV,1519,( <STR_LIT> ) ) -> getVT ( ) . bitsLE ( VT ) ) ;
LLVM,RISCV,1520,<NUM_LIT> ;
LLVM,RISCV,1521,"Node -> getDebugLoc ( ) , MVT :: <STR_LIT> , <STR_LIT> ) P->VLD_Format;"
LLVM,RISCV,1522,NF ;
LLVM,RISCV,1523,) ;
LLVM,RISCV,1524,
LLVM,RISCV,1525,", ImmOperand ) ;"
LLVM,RISCV,1526,) ;
LLVM,RISCV,1527,;
LLVM,RISCV,1528,
LLVM,RISCV,1529,VT );
LLVM,RISCV,1530,<NUM_LIT> ) ;
LLVM,RISCV,1531,) ) ;
LLVM,RISCV,1532,- 1 ) ;
LLVM,RISCV,1533,<NUM_LIT> ) ;
LLVM,RISCV,1534,( <NUM_LIT> ) ;
LLVM,RISCV,1535,true ;
LLVM,RISCV,1536,);
LLVM,RISCV,1537,getOffset ( ) ;
LLVM,RISCV,1538,*CurDAG );
LLVM,RISCV,1539,. getStringRef ( ) ) ) ;
LLVM,RISCV,1540,", false ) , <SD_Node_Ptr>s.getOperand());"
LLVM,RISCV,1541,;
LLVM,RISCV,1542,getFrameIndexReference ( Addr ) ;
LLVM,RISCV,1543,true ;
LLVM,RISCV,1544,false ;
LLVM,RISCV,1545,<STR_LIT> : if ( Bits < Subtarget -> getXLen ( ) - User -> getConstantOperandVal ( <NUM_LIT> ) ) return false ;
LLVM,RISCV,1546,true ;
LLVM,RISCV,1547,) ;
LLVM,RISCV,1548,<< <STR_LIT> ) ;
LLVM,RISCV,1549,<NUM_LIT> : return <STR_LIT> ;
LLVM,RISCV,1550,;
LLVM,RISCV,1551,<NUM_LIT> ) ;
LLVM,RISCV,1552,) ;
LLVM,RISCV,1553,<NUM_LIT> ) . getNode () ) <STR_LIT>);
LLVM,RISCV,1554,) ;
LLVM,RISCV,1555,"LMUL , SEW ) ;"
LLVM,RISCV,1556,
LLVM,RISCV,1557,") , SuperReg ) ;"
LLVM,RISCV,1558,"Load , <NUM_LIT> ) ;"
LLVM,RISCV,1559,) );
LLVM,RISCV,1560,
LLVM,RISCV,1561,getSizeInBits ( ) ;
LLVM,RISCV,1562,<STR_LIT> ) ;
LLVM,RISCV,1563,return true;
LLVM,RISCV,1564,) <PAREN_LIT> ) ;
LLVM,RISCV,1565,) ) ;
LLVM,RISCV,1566,"Node -> getVTList ( ) , Operands . data ( ) , Operands . size ( ) ) ;"
LLVM,RISCV,1567,) ) ;
LLVM,RISCV,1568,{
LLVM,RISCV,1569,", Store );"
LLVM,RISCV,1570,", CurDAG );"
LLVM,RISCV,1571,: if ( !IsRV64BIT) return false ;
LLVM,RISCV,1572,<CONSTANT_POSTFIX>) ) {
LLVM,RISCV,1573,( <NUM_LIT> ) );
LLVM,RISCV,1574,( ) ;
LLVM,RISCV,1575,) ;
LLVM,RISCV,1576,) ;
LLVM,RISCV,1577,"XLenVT , MVT::<STR_LIT> , TFI , Imm ]: <STR_LIT>  MVT::MachineConstant"
LLVM,RISCV,1578,<STR_LIT> && VT == XLenVT ) {
LLVM,RISCV,1579,Bits < <NUM_LIT> ) return false ;
LLVM,RISCV,1580,", SDValue ( Result , <STR_LIT> ) ) ;"
LLVM,RISCV,1581,;
LLVM,RISCV,1582,"(Op1) , XLenVT ) ;"
LLVM,RISCV,1583,<B31_LIT> opcode = isPowerOf2_32 inst= static MVT SelectVT ( ( <NUM_LIT> ) ) ;
LLVM,RISCV,1584,;
LLVM,RISCV,1585,;
LLVM,RISCV,1586,", SRC2 ) ;"
LLVM,RISCV,1587,
LLVM,RISCV,1588,) ;
LLVM,RISCV,1589,{
LLVM,RISCV,1590,) ) ;
LLVM,RISCV,1591,( ) ) ;
LLVM,RISCV,1592,) ;
LLVM,RISCV,1593,"<STR_LIT> ) , DL , <STR_LIT> ) ;"
LLVM,RISCV,1594,) ;
LLVM,RISCV,1595,) ) );
LLVM,RISCV,1596,signExtend ) Opcode = <STR_LIT> ;
LLVM,RISCV,1597,Mips::SUB);
LLVM,RISCV,1598,( ) ;
LLVM,RISCV,1599,-> getValueType ( ) ) ) ;
LLVM,RISCV,1600,RCID ] ) ;
LLVM,RISCV,1601,;
LLVM,RISCV,1602,[ 0 ] ) ;
LLVM,RISCV,1603,false ;
LLVM,RISCV,1604,;
LLVM,RISCV,1605,) ;
LLVM,RISCV,1606,{
LLVM,RISCV,1607,<ISA_LIT> * Func ) {
LLVM,RISCV,1608,();
LLVM,RISCV,1609,( ) ) ;
LLVM,RISCV,1610,Result ;
LLVM,RISCV,1611,) ;
LLVM,RISCV,1612,;
LLVM,RISCV,1613,
LLVM,RISCV,1614,;
LLVM,RISCV,1615,", < <NUM_LIT> > );"
LLVM,RISCV,1616,"<STR_LIT> , MemOp -> memoperands ( ) ) ;"
LLVM,RISCV,1617,"<STR_LIT>Dependency ( Load , MemOp ) ;"
LLVM,RISCV,1618,
LLVM,RISCV,1619,ZERO_EXTEND );
LLVM,RISCV,1620,<5> ( Imm ) ;
LLVM,RISCV,1621,") , XLenVT ) ;"
LLVM,RISCV,1622,return 0;
LLVM,RISCV,1623,return false;
LLVM,RISCV,1624,
LLVM,RISCV,1625,RHS : LHS ;
LLVM,RISCV,1626,
LLVM,RISCV,1627,;
LLVM,RISCV,1628,;
LLVM,RISCV,1629,) {
LLVM,RISCV,1630,Context ) ;
LLVM,RISCV,1631,RetCC_<ISA_LIT> );
LLVM,RISCV,1632,Value ;
LLVM,RISCV,1633,== CCValAssign :: Full ) ;
LLVM,RISCV,1634,"AExt : return DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Value ) ;"
LLVM,RISCV,1635,DS );
LLVM,RISCV,1636,):
LLVM,RISCV,1637,;
LLVM,RISCV,1638,;
LLVM,RISCV,1639,);
LLVM,RISCV,1640,'M' : if ( type -> isPointerTy ( ) )   weight = CW_Memory ;
LLVM,RISCV,1641,") , Ty , <NUM_LIT> , <NUM_LIT> , Flag ) ;"
LLVM,RISCV,1642,Type ;
LLVM,RISCV,1643,{
LLVM,RISCV,1644,The last statement is: return;
LLVM,RISCV,1645,<NUM_LIT> : SI = <NUM_LIT> << <NUM_LIT> ;
LLVM,RISCV,1646,Offset ) ;
LLVM,RISCV,1647,( RM ) ;
LLVM,RISCV,1648,"VaArgOffset , true ) ;"
LLVM,RISCV,1649,getZExtValue ( ) &gt;
LLVM,RISCV,1650,
LLVM,RISCV,1651,
LLVM,RISCV,1652,) + Lo ;
LLVM,RISCV,1653,", Result);"
LLVM,RISCV,1654,": return lowerSystemCall ( cast < SysCallSDNode > ( Op ) , DAG ) ;"
LLVM,RISCV,1655,": return lowerGlobalAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ;"
LLVM,RISCV,1656,getRegClass ( RA ) ) ;
LLVM,RISCV,1657,getMachineFunction ( ) ;
LLVM,RISCV,1658,<NUM_LIT> ) );
LLVM,RISCV,1659,", Op . getOperand ( <NUM_LIT> ) , <STR_LIT> )}"
LLVM,RISCV,1660,) ? < <ISA_LIT>SP : < SSP;
LLVM,RISCV,1661,. getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;
LLVM,RISCV,1662,) ) ;
LLVM,RISCV,1663,
LLVM,RISCV,1664,) . getEVTString ( ) << <STR_LIT> << <LINK_FOREST > << <LINK_FOREST>;
LLVM,RISCV,1665,i ] . ArgNo ] . OrigTy : nullptr ;
LLVM,RISCV,1666,"Offset , TargetBlockAddress );"
LLVM,RISCV,1667,"DAG . getNode ( ISD < , DL , MVT < i64 > , MNHi , MNLo );"
LLVM,RISCV,1668,"Ty MVT :: Glue ) ,  <STR_LIT> ) ;"
LLVM,RISCV,1669,"<NUM_LIT> , <NUM_LIT> ) , <STR_LIT> ) ;"
LLVM,RISCV,1670,) ) ;
LLVM,RISCV,1671,"Ty , Offset , <STR_LIT> ) ;"
LLVM,RISCV,1672,": return lowerDEBUG_VALUE ( Op , DAG ) ;"
LLVM,RISCV,1673,: return LowerFRAMEEX
LLVM,RISCV,1674,Val ;
LLVM,RISCV,1675,"PromoteToType , MVT :: <STR_LIT> ) ;"
LLVM,RISCV,1676,;
LLVM,RISCV,1677,LocVT ) ;
LLVM,RISCV,1678,) ) {
LLVM,RISCV,1679,<STR_LIT> ) ;
LLVM,RISCV,1680,", CCValAssign :: Full ) ) ;"
LLVM,RISCV,1681,", <NUM_LIT> ) ;"
LLVM,RISCV,1682,:  case ISD::SUB:  case ISD::AND:  case ISD::SHL:  case ISD::SRL:  case ISD::SRA:  case ISD::ROTL:
LLVM,RISCV,1683,"MVT :: f32 _  , NewOp1) ;"
LLVM,RISCV,1684,", <STR_LIT> , {"
LLVM,RISCV,1685,<NUM_LIT>;
LLVM,RISCV,1686,);
LLVM,RISCV,1687,") , FI , <STR_LIT> , SRV ) ;"
LLVM,RISCV,1688,C_Reference ;
LLVM,RISCV,1689,( ConstraintCode ) ;
LLVM,RISCV,1690,}
LLVM,RISCV,1691,)const {
LLVM,RISCV,1692,<STR_LIT> ;
LLVM,RISCV,1693,<STR_LIT> : return <STR_LIT> ;
LLVM,RISCV,1694,", MachineFunction & MF ) ;"
LLVM,RISCV,1695,-> getBitWidth ( ) );
LLVM,RISCV,1696,;
LLVM,RISCV,1697,<NUM_LIT> ) ;
LLVM,RISCV,1698,
LLVM,RISCV,1699,") , Subtarget . is64Bit ( ) ) ;"
LLVM,RISCV,1700,", true ) ;"
LLVM,RISCV,1701,"( RegHi , <STR_LIT> ) ) ;"
LLVM,RISCV,1702,RetOpc = <STR_LIT> ;
LLVM,RISCV,1703,Full : case ISD::EXTLOAD: {
LLVM,RISCV,1704,Reg ) ;
LLVM,RISCV,1705,STI.isRegisterReservedByUser(Reg.first) }
LLVM,RISCV,1706,LocInfo ) ) ;
LLVM,RISCV,1707,;
LLVM,RISCV,1708,", MVT ::"
LLVM,RISCV,1709,"( RegHi , <STR_LIT> ) ) ;"
LLVM,RISCV,1710,
LLVM,RISCV,1711,"<STR_LIT> , RI ) ;"
LLVM,RISCV,1712,", <NUM_LIT> ) ;"
LLVM,RISCV,1713,FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;
LLVM,RISCV,1714,
LLVM,RISCV,1715,) return false ;
LLVM,RISCV,1716,IntNo ) {
LLVM,RISCV,1717,) ;
LLVM,RISCV,1718,assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && Op . getOpcode () == ISD :: <STR_LIT> ) ;
LLVM,RISCV,1719,"( MF , CalleeCC ) ;"
LLVM,RISCV,1720,", Custom ) ;"
LLVM,RISCV,1721,( ) ;
LLVM,RISCV,1722,addReg ( <STR_LIT> ) ;
LLVM,RISCV,1723,
LLVM,RISCV,1724,return false;
LLVM,RISCV,1725,<STR_LIT> . {
LLVM,RISCV,1726,) ;
LLVM,RISCV,1727,;
LLVM,RISCV,1728,( ) ;
LLVM,RISCV,1729,( HeadMBB ) ;
LLVM,RISCV,1730,") , HeadMBB -> <STR_LIT> ) ;"
LLVM,RISCV,1731,;
LLVM,RISCV,1732,) ;
LLVM,RISCV,1733,XLenInBytes ;
LLVM,RISCV,1734,&& <STR_LIT> ) ;
LLVM,RISCV,1735,<NUM_LIT> ) ;
LLVM,RISCV,1736,ArgVT ;
LLVM,RISCV,1737,
LLVM,RISCV,1738,i ] . <ISA_LIT>simpleValueType ( ) ;
LLVM,RISCV,1739,= State . AllocateReg ( ArgGPRs ) ;
LLVM,RISCV,1740,
LLVM,RISCV,1741,Subtarget . isRegisterReservedByUser ( ) && ! Subtarget . hasRV64 ) {
LLVM,RISCV,1742,( ) ;
LLVM,RISCV,1743,
LLVM,RISCV,1744,) ) return false ;
LLVM,RISCV,1745,Subtarget . hasVInstructionsF64 ( ) ;
LLVM,RISCV,1746,: <NUM_LIT> ;
LLVM,RISCV,1747,"Shift , Table ) ;"
LLVM,RISCV,1748,) | ( int ( RoundingMode :: TowardPositive ) << <NUM_LIT> * <STR_LIT> ) ;
LLVM,RISCV,1749,"XLenVT , MVT :: Other ) ;"
LLVM,RISCV,1750,"( <NUM_LIT> , DL , XLenVT ) , Shift ) ;"
LLVM,RISCV,1751,
LLVM,RISCV,1752,VT == <STR_LIT> );
LLVM,RISCV,1753,) ;
LLVM,RISCV,1754,getLMul ) return false ;
LLVM,RISCV,1755,Bits );
LLVM,RISCV,1756,", <STR_LIT> ) ) ;"
LLVM,RISCV,1757,State . {
LLVM,RISCV,1758,( ) ;
LLVM,RISCV,1759,
LLVM,RISCV,1760,. getABI ( ) ;
LLVM,RISCV,1761,"X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::ESP, X86::EBP, X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RBP, X86::XMM0, X"
LLVM,RISCV,1762,= ShAmt1 + ShAmt2 ;
LLVM,RISCV,1763,- <NUM_LIT> ) ) return SDValue ( ) ;
LLVM,RISCV,1764,"DL , NarrowVT , Op0);"
LLVM,RISCV,1765,<STR_LIT> ) {
LLVM,RISCV,1766,"MVT :M1  ) , RHS -> Op ) ;"
LLVM,RISCV,1767,( ) ;
LLVM,RISCV,1768,
LLVM,RISCV,1769,"N0 , DAG , AllOnes ) ) return Result ;"
LLVM,RISCV,1770,x & <NUM_LIT> ) >> <NUM_LIT> ) ;
LLVM,RISCV,1771,| ( ( x & <NUM_LIT> ) >> <NUM_LIT> ) ;
LLVM,RISCV,1772,= Known . zext ( BitWidth ) ;
LLVM,RISCV,1773,VT . getDebugLoc ( ) ) ;
LLVM,RISCV,1774,", ISD :: CondCode Cond) {"
LLVM,RISCV,1775,
LLVM,RISCV,1776,getCurDebugLoc ( ) ) ;
LLVM,RISCV,1777,{
LLVM,RISCV,1778,"Ty , NewRes ) ;"
LLVM,RISCV,1779,);
LLVM,RISCV,1780,"0, DAG.getTargetConstant(<STR_LIT>, DL, MVT::i<NUM_LIT>));"
LLVM,RISCV,1781,) ;
LLVM,RISCV,1782,VecVT ) ;
LLVM,RISCV,1783,. add <STR_LIT> ( <NUM_LIT> ) . add <STR_LIT> ( <NUM_LIT> ) ;
LLVM,RISCV,1784,"Result , IntegerType :: create ( <NUM_LIT> , CmpVal -> getContext ( ) ) ) ;"
LLVM,RISCV,1785,"CmpVal , NewVal , <NUM_LIT> , Mask }"
LLVM,RISCV,1786,. getReg ( ) ;
LLVM,RISCV,1787,) ) {
LLVM,RISCV,1788,true ;
LLVM,RISCV,1789,
LLVM,RISCV,1790,CreateFence ();
LLVM,RISCV,1791,", Load}"
LLVM,RISCV,1792,( ) ) ;
LLVM,RISCV,1793,
LLVM,RISCV,1794,NOTE:
LLVM,RISCV,1795,(overridesSubtarget (C)) );
LLVM,RISCV,1796,<VT>){
LLVM,RISCV,1797,
LLVM,RISCV,1798,
LLVM,RISCV,1799,
LLVM,RISCV,1800,AnonymousPhysReg;
LLVM,RISCV,1801,ARM::NoRegister;
LLVM,RISCV,1802,
LLVM,RISCV,1803,<OnBoxCopy>;
LLVM,RISCV,1804,;
LLVM,RISCV,1805,:
LLVM,RISCV,1806,;
LLVM,RISCV,1807,isa <VTablePtr> ( <e>getMaterializationInfo()->getVTable() ) ;
LLVM,RISCV,1808,"128, Invalid vector size) ;"
LLVM,RISCV,1809,) ) {
LLVM,RISCV,1810,getEVTAlign ( VT ) ) );
LLVM,RISCV,1811,
LLVM,RISCV,1812,
LLVM,RISCV,1813,) ;
LLVM,RISCV,1814,{
LLVM,RISCV,1815,VT ) ;
LLVM,RISCV,1816,
LLVM,RISCV,1817,: return <STR_LIT> ;
LLVM,RISCV,1818,":: getIntegerVT ( Context , VT . getVectorElementType ( ) ) ;"
LLVM,RISCV,1819,", <STR_LIT> );"
LLVM,RISCV,1820,", <NUM_LIT> ) ;"
LLVM,RISCV,1821,<NUM_LIT> ;
LLVM,RISCV,1822,()&lt;
LLVM,RISCV,1823,) ;
LLVM,RISCV,1824,true ;
LLVM,RISCV,1825,const {
LLVM,RISCV,1826,
LLVM,RISCV,1827,;
LLVM,RISCV,1828,) ? 16U : 8U ;
LLVM,RISCV,1829,) ;
LLVM,RISCV,1830,( ) ) ) return true ;
LLVM,RISCV,1831,) {
LLVM,RISCV,1832,"<NUM_LIT> TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) {"
LLVM,RISCV,1833,. hasStdExtD ( ) ) return false ;
LLVM,RISCV,1834,;
LLVM,RISCV,1835,true ;
LLVM,RISCV,1836,false ;
LLVM,RISCV,1837,false ;
LLVM,RISCV,1838,[ ] ( int64_t Val ) {
LLVM,RISCV,1839,", X , NegX , Mask , VL ) ;"
LLVM,RISCV,1840,-> getBlockAddress ( ) ) ;
LLVM,RISCV,1841,DAG ) ;
LLVM,RISCV,1842,", MVT::i64 ) ;"
LLVM,RISCV,1843,". getConstant ( SubRegIdx , DL , XLenVT ) ) ;"
LLVM,RISCV,1844,Chain ;
LLVM,RISCV,1845,;
LLVM,RISCV,1846,DL ) ;
LLVM,RISCV,1847,"MaskOpc , true ) ;"
LLVM,RISCV,1848,( );
LLVM,RISCV,1849,"DAG , Subtarget ) ;"
LLVM,RISCV,1850,", MVT :: i64 ) ;"
LLVM,RISCV,1851,) ;
LLVM,RISCV,1852,"getBasePtr ( ) , VL , Store -> getOffset ( ) }"
LLVM,RISCV,1853,"Mask , VL , ScalarVal );"
LLVM,RISCV,1854,"FpToInt , ISD :: SETCC_SETEQ )"
LLVM,RISCV,1855,VT ) ;
LLVM,RISCV,1856,") , Shift ) ;"
LLVM,RISCV,1857,"DAG . getNode ( Intrinsic :: <STR_LIT> , DL , Ty , Addr ) ;"
LLVM,RISCV,1858,IsMasked;
LLVM,RISCV,1859,<NUM_LIT> + OpOffset ) ) ;
LLVM,RISCV,1860,", Subtarget ) ;"
LLVM,RISCV,1861,"getAddr(N, llvm::DTInt32)"
LLVM,RISCV,1862,( Mask ) ;
LLVM,RISCV,1863,"<STR_LIT> , DL , XLenVT ) ;"
LLVM,RISCV,1864,;
LLVM,RISCV,1865,Subtarget ) ;
LLVM,RISCV,1866,
LLVM,RISCV,1867,") , Ops ) ;"
LLVM,RISCV,1868,) {
LLVM,RISCV,1869,-> getZExtValue ( ) ;
LLVM,RISCV,1870,"Op . getValueType ( ) , CondV , FalseV ) ;"
LLVM,RISCV,1871,
LLVM,RISCV,1872,"SysRegNo , SDValue , RMValue ) ;"
LLVM,RISCV,1873,"RMValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;"
LLVM,RISCV,1874,HiFalse ) ;
LLVM,RISCV,1875,", Hi , LoTrue ) ;"
LLVM,RISCV,1876,"<NUM_LIT> , DL ) ;"
LLVM,RISCV,1877,"MVT ContainerVT = getContainerForFixedLengthVector ( DAG , VT , Subtarget ) ;"
LLVM,RISCV,1878,( Mask ) ;
LLVM,RISCV,1879,
LLVM,RISCV,1880,. getSimpleValueType ( ) ;
LLVM,RISCV,1881,"Mask , VL ) ;"
LLVM,RISCV,1882,"<STR_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,1883,SplatZero ) ;
LLVM,RISCV,1884,", SplatZero , ISD::SETNE );"
LLVM,RISCV,1885,"<STR_LIT> : Vec = DAG . getNode ( <STR_LIT> , DL , XLenVT , Zero , Mask , VL ) ;"
LLVM,RISCV,1886,Ops ) ;
LLVM,RISCV,1887,
LLVM,RISCV,1888,Vec ) ;
LLVM,RISCV,1889,SHLExpMask ;
LLVM,RISCV,1890,) return Src ;
LLVM,RISCV,1891,<NUM_LIT> }
LLVM,RISCV,1892,= {
LLVM,RISCV,1893,$config;
LLVM,RISCV,1894,) == MVT :: i1
LLVM,RISCV,1895,"DAG , Subtarget ) ;"
LLVM,RISCV,1896,SetCCs ) {
LLVM,RISCV,1897,return GORC;
LLVM,RISCV,1898,"DAG , Subtarget ) ;"
LLVM,RISCV,1899,"DAG , ISD :: XOR );"
LLVM,RISCV,1900,) ;
LLVM,RISCV,1901,{
LLVM,RISCV,1902,* N ) const ;
LLVM,RISCV,1903,true ;
LLVM,RISCV,1904,{
LLVM,RISCV,1905,{
LLVM,RISCV,1906,) ) {
LLVM,RISCV,1907,. getStartIndex ( ) ) ) fade_out_y ( U );
LLVM,RISCV,1908,
LLVM,RISCV,1909,", v Hi ) ;"
LLVM,RISCV,1910,", PartEltVT , Count ) ;"
LLVM,RISCV,1911,}
LLVM,RISCV,1912,"setHiBits ( <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,1913,", VT ) ) ;"
LLVM,RISCV,1914,"( MF , FI ) ) ;"
LLVM,RISCV,1915,": case CCValAssign :: <NUM_LIT> : Val = DAG . getNode ( VA . getLocInfo ( ) , DL , ValVT ) ;"
LLVM,RISCV,1916,VA . <GROUP>) ;
LLVM,RISCV,1917,) ;
LLVM,RISCV,1918,ISA:
LLVM,RISCV,1919,( <ISA_LIT>TargetLoweringError::Invalid User Reserved Regs ) ;
LLVM,RISCV,1920,
LLVM,RISCV,1921,( ) ) ;
LLVM,RISCV,1922,( ) ;
LLVM,RISCV,1923,( <NUM_LIT> ) ;
LLVM,RISCV,1924,: {
LLVM,RISCV,1925,"<NODE_NAME>, DL, N->getValueType(), NewRes ;"
LLVM,RISCV,1926,"<STR_LIT> , <STR_LIT> , Subtarget ) ;"
LLVM,RISCV,1927,<STR_LIT>;
LLVM,RISCV,1928,Bit ;
LLVM,RISCV,1929,<STR_LIT> ;
LLVM,RISCV,1930,: Info . opc = bitcast ;
LLVM,RISCV,1931,II -> VROperand ) ;
LLVM,RISCV,1932,. getValueType ();
LLVM,RISCV,1933,
LLVM,RISCV,1934,) return false ;
LLVM,RISCV,1935,hasStdExtD ( ) ) return false ;
LLVM,RISCV,1936,[ <NUM_LIT> ] ;
LLVM,RISCV,1937,() ;
LLVM,RISCV,1938,) ;
LLVM,RISCV,1939,VecVT . getVectorElementType ( ) ;
LLVM,RISCV,1940,
LLVM,RISCV,1941,", DAG , Subtarget ) ;"
LLVM,RISCV,1942,FpToInt . getValueType ( ) );
LLVM,RISCV,1943,", <STR_LIT> ) ;"
LLVM,RISCV,1944,) ;
LLVM,RISCV,1945,( Mask ) ;
LLVM,RISCV,1946,
LLVM,RISCV,1947,"DAG , Subtarget ) ;"
LLVM,RISCV,1948,: <STR_LIT> ;
LLVM,RISCV,1949,Intrinsic <STR_LIT> : Intrinsic <STR_LIT> ;
LLVM,RISCV,1950,<STR_LIT> MVT::v16i1
LLVM,RISCV,1951,
LLVM,RISCV,1952,"XLenVT ) , DAG );"
LLVM,RISCV,1953,XLenVT ) ) {
LLVM,RISCV,1954,isAsmCompatabilityEnabled ( ) ? VecVT : MVT :: vls MAXVT ? Op . getOpcode ( ).isCommutative() ? <NUM_LIT>: <NUM_LIT>;
LLVM,RISCV,1955,1 ;
LLVM,RISCV,1956,IsSDIV ? XLenIntrinsic :: SDIV : XLenIntrinsic :: SREM ;
LLVM,RISCV,1957,"FpToInt , ISD :: SETEQ );"
LLVM,RISCV,1958,) ;
LLVM,RISCV,1959,"VT , InterVec ) ;"
LLVM,RISCV,1960,<INTEGRAL_LITERAL> ) {
LLVM,RISCV,1961,<STR_LIT> ;
LLVM,RISCV,1962,"getNode ( ExtOpc , DL , NarrowVT , Op1 , Mask , VL ) ;"
LLVM,RISCV,1963,<NUM_LIT> ) return None ;
LLVM,RISCV,1964,<STR_LIT> ;
LLVM,RISCV,1965,;
LLVM,RISCV,1966,MOInvariant ;
LLVM,RISCV,1967,Expand ) ;
LLVM,RISCV,1968,Expand ;
LLVM,RISCV,1969,;
LLVM,RISCV,1970,<STR_LIT> ;
LLVM,RISCV,1971,<STR_LIT> ;
LLVM,RISCV,1972,return true;
LLVM,RISCV,1973,<NUM_LIT> : <NUM_LIT> ;
LLVM,RISCV,1974,) {
LLVM,RISCV,1975,
LLVM,RISCV,1976,") - > getPointerElementType ( ) , <ISA_LIT> }"
LLVM,RISCV,1977,{
LLVM,RISCV,1978,CCValAssign :: Full ) ) ;
LLVM,RISCV,1979,"LocVT , LocInfo ) ) ;"
LLVM,RISCV,1980,InBits ){
LLVM,RISCV,1981,return ScalarOperand != number;
LLVM,RISCV,1982,null ? ScalarOperand::GetResult() : ScalarOperand::GetDefault();
LLVM,RISCV,1983,
LLVM,RISCV,1984,: {
LLVM,RISCV,1985,) {
LLVM,RISCV,1986,"DL , MVT :: Other , RetOps )"
LLVM,RISCV,1987,"XLenVT , Legal ) ;"
LLVM,RISCV,1988,{
LLVM,RISCV,1989,) const {
LLVM,RISCV,1990,", VL }"
LLVM,RISCV,1991,MVT :: Other }
LLVM,RISCV,1992,"> VT . isFixedLengthVector ( ) ) : DAG . getNode ( ISD :: VSCALE , DL , XLenVT , VL , > VT . isFixedLengthVector ( ) ) : DAG . getNode ( ISD :: TP , DL , XLenVT ) ;"
LLVM,RISCV,1993,}
LLVM,RISCV,1994,"Mask , VL ) ;"
LLVM,RISCV,1995,) ;
LLVM,RISCV,1996,"Vec , One ) ;"
LLVM,RISCV,1997,
LLVM,RISCV,1998,
LLVM,RISCV,1999,true ;
LLVM,RISCV,2000,-> hasAnyUseOfValue ( <NUM_LIT> ) ) == V ;
LLVM,RISCV,2001,"<CB_LIT> ) , NewRes )Return DAG.getNode(ISD::intrinsic_woologic_, DL, N->getValueType(0), NewRes)."
LLVM,RISCV,2002,:: TracksLiveness ) ;
LLVM,RISCV,2003,( RHS );
LLVM,RISCV,2004,VecVT ) ;
LLVM,RISCV,2005,{
LLVM,RISCV,2006,<STR_LIT> : return EVT ( SimpleTy ) ;
LLVM,RISCV,2007,}
LLVM,RISCV,2008,()) ;
LLVM,RISCV,2009,EC . <STR_LIT> ) ;
LLVM,RISCV,2010,[ <NUM_LIT> ] ;
LLVM,RISCV,2011,false ;
LLVM,RISCV,2012,false;
LLVM,RISCV,2013,) const {
LLVM,RISCV,2014,", XLenVT ) ;"
LLVM,RISCV,2015,) ;
LLVM,RISCV,2016,"getParent ( ) , GV ) ;"
LLVM,RISCV,2017,"GeneralDynamic :  SDValue Ptr = getDynamicTLSAddr(N, DAG);"
LLVM,RISCV,2018,Subtarget ) ;
LLVM,RISCV,2019,push_back ( Mask ) ;
LLVM,RISCV,2020,= (VT == XLenVT || VT == XLenVT.getVectorElementType().SimpleTy) ? XLenVT : VT
LLVM,RISCV,2021,;
LLVM,RISCV,2022,<NUM_LIT> ] ;
LLVM,RISCV,2023,) ;
LLVM,RISCV,2024,
LLVM,RISCV,2025,"The last statement is: TrueMask = MPBuildSDNode . buildMask ( VecVT , VLMax , DownOffset , UpOffset ) ;"
LLVM,RISCV,2026,XLenVT ) ;
LLVM,RISCV,2027,Ops ) ;
LLVM,RISCV,2028,LegalOps );
LLVM,RISCV,2029,"DAG , LegalOps ) ;"
LLVM,RISCV,2030,"<NUM_LIT> , DL , <STR_LIT> ) ) ;"
LLVM,RISCV,2031,) {
LLVM,RISCV,2032,-> isOne ( ) ) return false ;
LLVM,RISCV,2033,
LLVM,RISCV,2034,: if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ;
LLVM,RISCV,2035,false ;
LLVM,RISCV,2036,Ins [ i ] <STR_LIT> ;
LLVM,RISCV,2037,It ) ;
LLVM,RISCV,2038,<STR_LIT> ) {
LLVM,RISCV,2039,FalseVal ) ;
LLVM,RISCV,2040,"0 , 0) ;"
LLVM,RISCV,2041,( ) + <NUM_LIT> ) ;
LLVM,RISCV,2042,
LLVM,RISCV,2043,;
LLVM,RISCV,2044,. is64Bit ( ) ) ;
LLVM,RISCV,2045,}
LLVM,RISCV,2046,"ContainerVT , MVT :: Other }"
LLVM,RISCV,2047,"( <NUM_LIT> , DL ) ) ;"
LLVM,RISCV,2048,) - Idx ) + <NUM_LIT> ;
LLVM,RISCV,2049,") , <STR_LIT> ) ;"
LLVM,RISCV,2050,VL . getValueType().isMVector()) {
LLVM,RISCV,2051,) ;
LLVM,RISCV,2052,else {
LLVM,RISCV,2053,StepVal ) ;
LLVM,RISCV,2054,XLenVT ) ;
LLVM,RISCV,2055,) << Fixed length vector must have even number of elements;
LLVM,RISCV,2056,", Subtarget ) ) return SHFL ;"
LLVM,RISCV,2057,DCI . DAG ;
LLVM,RISCV,2058,<div>Idiv ( ) ;
LLVM,RISCV,2059,<NUM_LIT> && <NUM_LIT> ) {
LLVM,RISCV,2060,", Idx ) ;"
LLVM,RISCV,2061,"Op . getValueType ( ) , Ops ) ;"
LLVM,RISCV,2062,( MVT :: i32 ) ;
LLVM,RISCV,2063,<STR_LIT> : <NUM_LIT> MinVLen /= 2;
LLVM,RISCV,2064,;
LLVM,RISCV,2065,true ;
LLVM,RISCV,2066,) == <STR_LIT> ) return ;
LLVM,RISCV,2067,"MVType::v16i1, SDValue()"
LLVM,RISCV,2068,
LLVM,RISCV,2069,
LLVM,RISCV,2070,) ;
LLVM,RISCV,2071,) ;
LLVM,RISCV,2072,) ;
LLVM,RISCV,2073,Flags ;
LLVM,RISCV,2074,;
LLVM,RISCV,2075,) ;
LLVM,RISCV,2076,ShAmt1 + ShAmt1 ;
LLVM,RISCV,2077,", Val ) ;"
LLVM,RISCV,2078,) return false;
LLVM,RISCV,2079,<STR_LIT> :  <STR_LIT> :
LLVM,RISCV,2080,;
LLVM,RISCV,2081,;
LLVM,RISCV,2082,
LLVM,RISCV,2083,"MVT :: Other , OutChains ) ;"
LLVM,RISCV,2084,PtrVT ) ;
LLVM,RISCV,2085,) % <NUM_LIT> ;
LLVM,RISCV,2086,getValueType ( ) ;
LLVM,RISCV,2087,) ) RetOps . push_back ( Glue ) ;
LLVM,RISCV,2088,( ) ;
LLVM,RISCV,2089,") , Ops ) ;"
LLVM,RISCV,2090,SHLExpMask ;
LLVM,RISCV,2091,<NUM_LIT> ) ;
LLVM,RISCV,2092,( RC ) ;
LLVM,RISCV,2093,<NUM_LIT> ) -> <NUM_LIT> ( <STR_LIT> ) <NUM_LIT> ;
LLVM,RISCV,2094,? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,2095,<NUM_LIT> ) ;
LLVM,RISCV,2096,+ ShAmt2 ;
LLVM,RISCV,2097,SExtOpc;
LLVM,RISCV,2098,
LLVM,RISCV,2099,|= x ;
LLVM,RISCV,2100,XLenVT ) ;
LLVM,RISCV,2101,<NUM_LIT> ) ;
LLVM,RISCV,2102,Y.getNode ( ) ) ;
LLVM,RISCV,2103,{
LLVM,RISCV,2104,
LLVM,RISCV,2105,VT ) return true ;
LLVM,RISCV,2106,<STR_LIT> = ISD::SINT_TO_FP
LLVM,RISCV,2107,", Mask ) ;"
LLVM,RISCV,2108,
LLVM,RISCV,2109,"VT.getVectorElementType(),  , IsMaskOp ? INTR_WRITE_MASKED : INTR_WRITE_VECTOR, DL, XLenVT);"
LLVM,RISCV,2110,". getUNDEF ( VecEltVT ) , Constant ) ;"
LLVM,RISCV,2111,
LLVM,RISCV,2112,) ;
LLVM,RISCV,2113,dl ) ;
LLVM,RISCV,2114,) ;
LLVM,RISCV,2115,", Val , One ) ;"
LLVM,RISCV,2116,
LLVM,RISCV,2117,"VT , XLenMinus1 , Shamt ) ;"
LLVM,RISCV,2118,Shamt ) ;
LLVM,RISCV,2119,", XLenMinus1 ) ;"
LLVM,RISCV,2120,"( VecVT . getVectorElementType ( ) , 0 ) ) ;"
LLVM,RISCV,2121,<NUM_LIT> );
LLVM,RISCV,2122,;
LLVM,RISCV,2123,RVVOpcode ));
LLVM,RISCV,2124,"<STR_LIT> , {"
LLVM,RISCV,2125,") , SplatTrueVal , VL ) ;"
LLVM,RISCV,2126,", VL ) ;"
LLVM,RISCV,2127,"<NUM_LIT> 0, DL, ContainerVT), DAG.getUNDEF(ContainerVT));"
LLVM,RISCV,2128,"SplatVL, DAG . getConstant ( 0, DL, XLenVT), DAG . getRegister( <STR_LIT> );"
LLVM,RISCV,2129,IntVT ) );
LLVM,RISCV,2130,", DownOffset , VLMax ) ;"
LLVM,RISCV,2131,DstEltSize ) ) {
LLVM,RISCV,2132,) ;
LLVM,RISCV,2133,", Vec . getConstantMax<NUM_LIT>() ) ;"
LLVM,RISCV,2134,", DAG ) ;"
LLVM,RISCV,2135,getValueType ( ) ;
LLVM,RISCV,2136,) ;
LLVM,RISCV,2137,) ) continue ;
LLVM,RISCV,2138,", MVT::i32 , LoC & ( ( 1 << <NUM_LIT> ) - 1 ) ) ;"
LLVM,RISCV,2139,);
LLVM,RISCV,2140,Val ;
LLVM,RISCV,2141,"MachineMemOperand :: <STR_LIT> , Inst . getOperand ( <NUM_LIT> ) . getValueSizeInBits ( ) / <NUM_LIT>  TargetRegisterInfo::NoRegister, TargetRegisterClass::ConstraintType::NoRegister, StackObjectOperand"
LLVM,RISCV,2142,&& SystemZ1 is 64-bit only! ) ;
LLVM,RISCV,2143,<NUM_LIT> ) . getReg ( ) ;
LLVM,RISCV,2144,<STR_LIT> : return <STR_LIT> ;
LLVM,RISCV,2145,"MVT :: v16i8 , Vec) ;"
LLVM,RISCV,2146,"DL , getVectorNumElements ( EltVT ) ) , <NUM_LIT>  ) ;"
LLVM,RISCV,2147,[ EII -> ExtendedOperand ] ;
LLVM,RISCV,2148,== <STR_LIT> ) {
LLVM,RISCV,2149,<STR_LIT> ) ;
LLVM,RISCV,2150,", DAG );"
LLVM,RISCV,2151,":<STR_LIT> customLegalizeToMOpWithZExt ( N , DAG ) ) ) <STR_LIT> customLegalizeToMOpWithZExt ( N , DAG ) ) <STR_LIT> customLegalizeToMOpWithZExt ( N , DAG ) ) return Results;"
LLVM,RISCV,2152,"( ) , false , false , false , <NUM_LIT> ) ;"
LLVM,RISCV,2153,{
LLVM,RISCV,2154,( ) ) {
LLVM,RISCV,2155,) ;
LLVM,RISCV,2156,( ) ) ;
LLVM,RISCV,2157,", Mask }"
LLVM,RISCV,2158,
LLVM,RISCV,2159,if ( AI -> getOperation ( ) == AtomicRMWInst :: <REL_OP> ) {
LLVM,RISCV,2160,) {
LLVM,RISCV,2161,
LLVM,RISCV,2162,"( Type :: getEPrettyName ( Ty , & TM ) , GV"
LLVM,RISCV,2163,{
LLVM,RISCV,2164,DL );
LLVM,RISCV,2165,"AddrLo ) , <NUM_LIT> ) ;"
LLVM,RISCV,2166,if ( !IS_TRUE(Subtarget.getTargetABI()) ) return TailPaddingAmount;
LLVM,RISCV,2167,TailPaddingAmount::Precise : TailPaddingAmount::Generic);
LLVM,RISCV,2168,
LLVM,RISCV,2169,) {
LLVM,RISCV,2170,
LLVM,RISCV,2171,true ;
LLVM,RISCV,2172,) ;
LLVM,RISCV,2173,", false ) ;"
LLVM,RISCV,2174,
LLVM,RISCV,2175,) ;
LLVM,RISCV,2176,> ( Op );
LLVM,RISCV,2177,"Zero , SetNE }"
LLVM,RISCV,2178,", FalseV <, LHS.getValueType()> }"
LLVM,RISCV,2179,
LLVM,RISCV,2180,", MVT :: <STR_LIT> , Ops ) ) .success ( ) ;"
LLVM,RISCV,2181,( ) ) ){
LLVM,RISCV,2182,
LLVM,RISCV,2183,
LLVM,RISCV,2184,
LLVM,RISCV,2185,", Order ) ;"
LLVM,RISCV,2186,The operand value for the load is: returned after initialization and configuration.
LLVM,RISCV,2187,}
LLVM,RISCV,2188,return SplatOperand != NUM_LIT ? true : false;
LLVM,RISCV,2189,N ) ;
LLVM,RISCV,2190,RegName;
LLVM,RISCV,2191,) ;
LLVM,RISCV,2192,"DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ;"
LLVM,RISCV,2193,. Default ( {
LLVM,RISCV,2194,) ;
LLVM,RISCV,2195,"XLenVT , Expand ) ;"
LLVM,RISCV,2196,) ;
LLVM,RISCV,2197,". getValueType ( ) , <NUM_LIT> ) ;"
LLVM,RISCV,2198,", VA ) ;"
LLVM,RISCV,2199,( ) . getEVTString ( VT ) << }
LLVM,RISCV,2200,<NUM_LIT> ;
LLVM,RISCV,2201,
LLVM,RISCV,2202,
LLVM,RISCV,2203,Expand ) ;
LLVM,RISCV,2204,) ;
LLVM,RISCV,2205,) {
LLVM,RISCV,2206,SelectionDAG& DAG) const ;
LLVM,RISCV,2207,) ;
LLVM,RISCV,2208,) ;
LLVM,RISCV,2209,) ;
LLVM,RISCV,2210,) <NUM_LIT> nullptr ;
LLVM,RISCV,2211,": return emitVCmp ( MI , BB ) ;"
LLVM,RISCV,2212,": return emitVFlagPseudo ( MI , BB ) ;"
LLVM,RISCV,2213,"VecVT ) , DAG , Subtarget ) ;"
LLVM,RISCV,2214,) ;
LLVM,RISCV,2215,) -> getSExtValue ( ) ;
LLVM,RISCV,2216,"MVT::f16 MVT::f64, NewOp0);"
LLVM,RISCV,2217,{
LLVM,RISCV,2218,) ;
LLVM,RISCV,2219,}
LLVM,RISCV,2220,else {
LLVM,RISCV,2221,;
LLVM,RISCV,2222,assert ( Subtarget . is64Bit ( ) && <STR_LIT> ) ;
LLVM,RISCV,2223,", DL , XLenVT ) ;"
LLVM,RISCV,2224,") , Load -> getMemOperand ( <NUM_LIT> }"
LLVM,RISCV,2225,
LLVM,RISCV,2226,) ) {
LLVM,RISCV,2227,Subtarget ) ;
LLVM,RISCV,2228,;
LLVM,RISCV,2229,<STR_LIT> : return This code snippet has reached the last switch case statement.
LLVM,RISCV,2230,) ;
LLVM,RISCV,2231,. push_back ( Res ) ;
LLVM,RISCV,2232,", V1 , V2 ) ;"
LLVM,RISCV,2233,;
LLVM,RISCV,2234,);
LLVM,RISCV,2235,&& Subtarget . hasStdExtF ( ) && <STR_LIT> ) ;
LLVM,RISCV,2236,;
LLVM,RISCV,2237,) ;
LLVM,RISCV,2238,", Expand ) ;"
LLVM,RISCV,2239,<STR_LIT> : llvm_unreachable ( ) ;
LLVM,RISCV,2240,DestReg ) ;
LLVM,RISCV,2241,. getOperand ( UseOpIdx ) ;
LLVM,RISCV,2242,) ;
LLVM,RISCV,2243,) ;
LLVM,RISCV,2244,"VID ,<MPU_RETIRED_ALL_BRANCHES> ,<NUM_LIT> ) ;"
LLVM,RISCV,2245,DAG ) ;
LLVM,RISCV,2246,": return lowerVectorMaskShift ( Op , DAG , <NUM_LIT> .Value);"
LLVM,RISCV,2247,"Lo = DAG.getNode(VINSERTF128, DL, VecVT, Lo, Hi, ThirtyTwoV, Sequential);"
LLVM,RISCV,2248,Hi ) ;
LLVM,RISCV,2249,"DL , MVT :: <STR_LIT> , SplatZero , ExpandOp ) ;"
LLVM,RISCV,2250,"DL , <STR_LIT> , SplatOne ) ;"
LLVM,RISCV,2251,( ) != <STR_LIT> ) {
LLVM,RISCV,2252,) ) ;
LLVM,RISCV,2253,:: MONone ) const {
LLVM,RISCV,2254,) ;
LLVM,RISCV,2255,", Op1 , Op2 ) ;"
LLVM,RISCV,2256,) ;
LLVM,RISCV,2257,
LLVM,RISCV,2258,newMI . addReg ( src2_reg ) ;
LLVM,RISCV,2259,src2_pos ) ) ;
LLVM,RISCV,2260,;
LLVM,RISCV,2261,TII -> get ( <STR_LIT> ) ) ;
LLVM,RISCV,2262,{
LLVM,RISCV,2263,<STR_LIT> ) ;
LLVM,RISCV,2264,;
LLVM,RISCV,2265,<NUM_LIT> ;
LLVM,RISCV,2266,", Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) DAG.getConstant(pred, DL, Subtarget.isRV64() ? I64 : I32)"
LLVM,RISCV,2267,Chain ) ;
LLVM,RISCV,2268,E;
LLVM,RISCV,2269,null ) ;
LLVM,RISCV,2270,":: make_pair ( false , true ) ;"
LLVM,RISCV,2271,== <STR_LIT> ) ;
LLVM,RISCV,2272,if ( Prefix == <STR_LIT> ) {
LLVM,RISCV,2273,
LLVM,RISCV,2274,DAG ) ;
LLVM,RISCV,2275,) ;
LLVM,RISCV,2276,", {"
LLVM,RISCV,2277,Op.getOperand(<NUM_LIT + 1>) );
LLVM,RISCV,2278,<STR_LIT> ) ;
LLVM,RISCV,2279,. getRegInfo ( );
LLVM,RISCV,2280,) ;
LLVM,RISCV,2281,( );
LLVM,RISCV,2282,RET_FLAG: Return node flag
LLVM,RISCV,2283,) ;
LLVM,RISCV,2284,", Hi , ThirtyTwoV );"
LLVM,RISCV,2285,) return Lo ;
LLVM,RISCV,2286,;
LLVM,RISCV,2287,index ( ) ;
LLVM,RISCV,2288,;
LLVM,RISCV,2289,() ;
LLVM,RISCV,2290,"any_of (Ops, [&](Use *U) {"
LLVM,RISCV,2291,"Value, Value, VA . getLocMemOffset() , Value , VA . getMachineMemOperand() ) ;"
LLVM,RISCV,2292,. getValVT ( ) ) ) ;
LLVM,RISCV,2293,: }
LLVM,RISCV,2294,", Reg , RegVT ) ;"
LLVM,RISCV,2295,getValue ( ) ;
LLVM,RISCV,2296,CCValAssign :: Full ) ) ;
LLVM,RISCV,2297,"(), Val <STR_LIT> );"
LLVM,RISCV,2298,;
LLVM,RISCV,2299,"return Builder.CreateStore(Inst, Ord);"
LLVM,RISCV,2300,".CreateAlignedStore ( V, Loc, Align, MMO, (SyncScope::System)Scope );"
LLVM,RISCV,2301,;
LLVM,RISCV,2302,"CmpVal , NewVal , Mask }"
LLVM,RISCV,2303,}
LLVM,RISCV,2304,nullptr ;
LLVM,RISCV,2305,Max : return <STR_LIT> ;
LLVM,RISCV,2306,", VT ) ;"
LLVM,RISCV,2307,MVT::Other ;
LLVM,RISCV,2308,<STR_LIT> ;
LLVM,RISCV,2309,;
LLVM,RISCV,2310,IsCalleeStructRet ){
LLVM,RISCV,2311,
LLVM,RISCV,2312,
LLVM,RISCV,2313,;
LLVM,RISCV,2314,value);
LLVM,RISCV,2315,== MVT :: i1 && DstVT == MVT :: i8 ;
LLVM,RISCV,2316,: case <STR_LIT> : return true ;
LLVM,RISCV,2317,) ;
LLVM,RISCV,2318,", VT2 ) ;"
LLVM,RISCV,2319,"Ty , BALo ) , <NUM_LIT_DATE> ) ;"
LLVM,RISCV,2320,Store ) ;
LLVM,RISCV,2321,RC ) ;
LLVM,RISCV,2322,
LLVM,RISCV,2323,
LLVM,RISCV,2324,", DAG ) ;"
LLVM,RISCV,2325,"DL , VT ) ;"
LLVM,RISCV,2326,FalseV }
LLVM,RISCV,2327,) ;
LLVM,RISCV,2328,", Src -> getOperand (  <NUM_LIT> ) ) ) ;"
LLVM,RISCV,2329,false ;
LLVM,RISCV,2330,Naive ;
LLVM,RISCV,2331,-> getPrimitiveSizeInBits ( ) ;
LLVM,RISCV,2332,Normal ;
LLVM,RISCV,2333,{
LLVM,RISCV,2334,*I ) {
LLVM,RISCV,2335,false ) ;
LLVM,RISCV,2336,"<NUM_LIT> , 0 , <NUM_LIT> ) ;"
LLVM,RISCV,2337,
LLVM,RISCV,2338,;
LLVM,RISCV,2339,
LLVM,RISCV,2340,this->_nextIRVGSaveIndex;
LLVM,RISCV,2341,MachineFunction &MF) {
LLVM,RISCV,2342,. getIselMFI );
LLVM,RISCV,2343,AttrT < ValueDecl > :: <LINE_COMMENT> )
LLVM,RISCV,2344,
LLVM,RISCV,2345,
LLVM,RISCV,2346,
LLVM,RISCV,2347,a }
LLVM,RISCV,2348,StackAlign ;
LLVM,RISCV,2349,
LLVM,RISCV,2350,MF.getFrameInfo.isFrameAddressTaken() . enableSetCDIBits();
LLVM,RISCV,2351,;
LLVM,RISCV,2352,"). CreateStackObject ( 8 , Align ( 8 ) , <0, true) , <0, SanitizationFunction) }"
LLVM,RISCV,2353,
LLVM,RISCV,2354,The last statement: {
LLVM,RISCV,2355,
LLVM,RISCV,2356,MFI . getFrameInfo ( ) .getStackSize() < <NUM_LIT> ;
LLVM,RISCV,2357,"int n, Closure c) {"
LLVM,RISCV,2358,ehDataRegs[Reg];
LLVM,RISCV,2359,ehDataRegFI_;
LLVM,RISCV,2360,
LLVM,RISCV,2361,{
LLVM,RISCV,2362,incomingArgumentSize ;
LLVM,RISCV,2363,;
LLVM,RISCV,2364,;
LLVM,RISCV,2365,;
LLVM,RISCV,2366,{
LLVM,RISCV,2367,The last statement of the code snippet is return savedGPRFrameSize;
LLVM,RISCV,2368,;
LLVM,RISCV,2369,;
LLVM,RISCV,2370,;
LLVM,RISCV,2371,Object:CopyAttributes(SavedGPR)
LLVM,RISCV,2372,{
LLVM,RISCV,2373,Size ;
LLVM,RISCV,2374,;
LLVM,RISCV,2375,GPRNum );
LLVM,RISCV,2376,
LLVM,RISCV,2377,;
LLVM,RISCV,2378,"Documentation says The DXGK_INTERFACE interface version-level at the time the driver was built, see https:"
LLVM,RISCV,2379,;
LLVM,RISCV,2380,FPR;
LLVM,RISCV,2381,(args: any[]) => number
LLVM,RISCV,2382,inFuncName + :;
LLVM,RISCV,2383,;
LLVM,RISCV,2384,;
LLVM,RISCV,2385,FramePtr &lt;
LLVM,RISCV,2386,;
LLVM,RISCV,2387,{
LLVM,RISCV,2388,;
LLVM,RISCV,2389,
LLVM,RISCV,2390,) {
LLVM,RISCV,2391,<STR_LIT> ;
LLVM,RISCV,2392,getLdstWidth ( Opcode )) ;
LLVM,RISCV,2393,( Opcode );
LLVM,RISCV,2394,;
LLVM,RISCV,2395,"<NUM_LIT> , <NUM_LIT> > ( Offset ) ;"
LLVM,RISCV,2396,() {
LLVM,RISCV,2397,);
LLVM,RISCV,2398,;
LLVM,RISCV,2399,) ) {
LLVM,RISCV,2400,( Reg );
LLVM,RISCV,2401,. contains ( Reg );
LLVM,RISCV,2402,;
LLVM,RISCV,2403,return Opcode == PPC::ADDI || ( !STI.is64Bit() && Opcode == PPC::ADDIS) || Opcode == PPC::LIS;
LLVM,RISCV,2404,
LLVM,RISCV,2405,: return <NUM_LIT> ;
LLVM,RISCV,2406,MF ) {
LLVM,RISCV,2407,") , false ) ;"
LLVM,RISCV,2408,;
LLVM,RISCV,2409,) ;
LLVM,RISCV,2410,Res ;
LLVM,RISCV,2411,? <NUM_LIT> : <NUM_LIT> 0x40;
LLVM,RISCV,2412,( ) ;
LLVM,RISCV,2413,
LLVM,RISCV,2414,Res ;
LLVM,RISCV,2415,< <NUM_LIT> > ( Lo12 ) ) {
LLVM,RISCV,2416,) ;
LLVM,RISCV,2417,"( <STR_LIT> , Lo12 ) ) ;"
LLVM,RISCV,2418,"Cost , MinCost ) ;"
LLVM,RISCV,2419,MatSeq ) ;
LLVM,RISCV,2420,<NUM_LIT> > ( Val / <NUM_LIT> ) ) {
LLVM,RISCV,2421,Lo12 ) ) ;
LLVM,RISCV,2422,Res = TmpSeq ;
LLVM,RISCV,2423,
LLVM,RISCV,2424,
LLVM,RISCV,2425,<STR_LIT> ;
LLVM,RISCV,2426,
LLVM,RISCV,2427,:
LLVM,RISCV,2428,) ;
LLVM,RISCV,2429,Value ) ;
LLVM,RISCV,2430,) ;
LLVM,RISCV,2431,) ;
LLVM,RISCV,2432,W );
LLVM,RISCV,2433,TT .getOS());
LLVM,RISCV,2434,;
LLVM,RISCV,2435,int16_t ) - 1 ;
LLVM,RISCV,2436,(&Inst));
LLVM,RISCV,2437,{
LLVM,RISCV,2438,<false/> ;
LLVM,RISCV,2439,CommentString = DWARF ;
LLVM,RISCV,2440,getContext() ;
LLVM,RISCV,2441,true ;
LLVM,RISCV,2442,;
LLVM,RISCV,2443,DwarfCFI ;
LLVM,RISCV,2444,}
LLVM,RISCV,2445,) ? 8 : 4 ;
LLVM,RISCV,2446,true ;
LLVM,RISCV,2447,
LLVM,RISCV,2448,<STR_LIT> ) . addImm ( <NUM_LIT> ) ;
LLVM,RISCV,2449,"( <STR_LIT> ) , MI . getLoc ( ) ) ) ;"
LLVM,RISCV,2450,;
LLVM,RISCV,2451,: llvm_unreachable ( <STR_LIT> ) ;
LLVM,RISCV,2452,!= <STR_LIT> && <STR_LIT> ) ;
LLVM,RISCV,2453,) ;
LLVM,RISCV,2454,<NUM_LIT> ] ) {
LLVM,RISCV,2455,) . addOperand ( Imm ) . addOperand ( <STR_LIT> ) ;
LLVM,RISCV,2456,getExpr ( ) ;
LLVM,RISCV,2457,", <STR_LIT> , <UINT> ) ;"
LLVM,RISCV,2458,TmpInst.setOpcode(Ra);
LLVM,RISCV,2459,
LLVM,RISCV,2460,: {
LLVM,RISCV,2461,", STI ) ;"
,,,
"srcReg.getReg() == DestReg.getReg()""""""",,,
LLVM,RISCV,2463,"<ISA_LIT>MCExpr::Binary :source operand is an expression, and its child expressions are of the specified instruction set architecture's MCExpr type."
LLVM,RISCV,2464,", <STR_LIT> ) ;"
LLVM,RISCV,2465,", STI ) ;"
LLVM,RISCV,2466,<STR_LIT> ;
LLVM,RISCV,2467,
LLVM,RISCV,2468,<STR_LIT> ;
LLVM,RISCV,2469,
LLVM,RISCV,2470,== <STR_LIT> ) {
LLVM,RISCV,2471,{
LLVM,RISCV,2472,", STI ) ;"
LLVM,RISCV,2473,;
LLVM,RISCV,2474,;
LLVM,RISCV,2475,( ) ) ) ;
LLVM,RISCV,2476,c) {
LLVM,RISCV,2477,. addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;
LLVM,RISCV,2478,;
LLVM,RISCV,2479,", MRI , Ctx ) ;"
LLVM,RISCV,2480,"MRI , Ctx ) ;"
LLVM,RISCV,2481,
LLVM,RISCV,2482,") , ( MCFixupKind ) <STR_LIT> ) ) ;"
LLVM,RISCV,2483,Fixups );
LLVM,RISCV,2484,
LLVM,RISCV,2485,
LLVM,RISCV,2486,getImm() ;
LLVM,RISCV,2487,
LLVM,RISCV,2488,MO . getImm ( ) ) ;
LLVM,RISCV,2489,
LLVM,RISCV,2490,);
LLVM,RISCV,2491,. getImm ( ) ;
LLVM,RISCV,2492,( ? <NUM_LIT> ) ;
LLVM,RISCV,2493,"( Offset ,  <NUM_LIT> + Expr );"
LLVM,RISCV,2494,addReg ( Rd ) ;
LLVM,RISCV,2495,
LLVM,RISCV,2496,", STI ) ;"
LLVM,RISCV,2497,) ) ;
LLVM,RISCV,2498,
LLVM,RISCV,2499,STI ) ;
LLVM,RISCV,2500,( Ra ) . addOperand ( MCOperand :: createExpr
LLVM,RISCV,2501,", GetContext ( ) ) ;"
LLVM,RISCV,2502,;
LLVM,RISCV,2503,0 ;
LLVM,RISCV,2504,"Expr , Kind );"
LLVM,RISCV,2505,"> return new ISA_LITMCExpr(Expr, cast<ISA_LITMCLineEntry>*());"
LLVM,RISCV,2506,true ;
LLVM,RISCV,2507,getSymbol ( ) ;
LLVM,RISCV,2508,;
LLVM,RISCV,2509,"VK_<ISA_LIT>_CALL ) . Case ( <STR_LIT> , VK_<ISA_LIT>_CALL16 ) . Default( VK_<ISA_LIT>_NONE );"
LLVM,RISCV,2510,) ;
LLVM,RISCV,2511,", Res ) ;"
LLVM,RISCV,2512,;
LLVM,RISCV,2513,From Sym : getKind ( ) == U8
LLVM,RISCV,2514,( ) == <ISA_LIT> :: K_SecRel : false ;
LLVM,RISCV,2515,: llvm_unreachable(Not implemented);
LLVM,RISCV,2516,: {
LLVM,RISCV,2517,"Case (<STR_LIT>, VK_<ISA_LIT>_GOT_LO) .Default(VK_<ISA_LIT>_NONE);"
LLVM,RISCV,2518,')' ;
LLVM,RISCV,2519,$plt ;
LLVM,RISCV,2520,bool MCExpr::evaluateAsConstant(int64_t& Res) const {
LLVM,RISCV,2521,getFixups ( ) ) {
LLVM,RISCV,2522,) ;
LLVM,RISCV,2523,OS << ')' ;
LLVM,RISCV,2524,false ;
LLVM,RISCV,2525,{
LLVM,RISCV,2526,
LLVM,RISCV,2527,"<STR_LIT> , VK_<ISA_LIT>_TL ) . Default ( VK_<ISA_LIT>_Error );"
LLVM,RISCV,2528,VK_<ISA_LIT>_PAGE : return <STR_LIT> ;
LLVM,RISCV,2529,VK_<ISA_LIT>_PCREL_HI : return false ;
LLVM,RISCV,2530,;
LLVM,RISCV,2531,
LLVM,RISCV,2532,) ;
LLVM,RISCV,2533,Expr ( ) ) ;
LLVM,RISCV,2534,) ;
LLVM,RISCV,2535,;
LLVM,RISCV,2536,<STR_LIT>;
LLVM,RISCV,2537,"<STR_LIT> , VK_<ISA_LIT>_CALL_LO16 ) . Case ( <STR_LIT> , VK_<ISA_LIT>_27BIT_TLSGD ) . Default ( VK_<ISA_LIT>_NONE );"
LLVM,RISCV,2538,const MCAsmInfo * MAI )const {
LLVM,RISCV,2539,) ;
LLVM,RISCV,2540,;
LLVM,RISCV,2541,: return true;
LLVM,RISCV,2542,true ;
LLVM,RISCV,2543,<ISA_LIT> << <ISA_LIT> ) + AUIPCOffset ;
LLVM,RISCV,2544,0 ;
LLVM,RISCV,2545,": DG . addEdge ( FromNode ,ToNode , new MCDataFragmentEdge < MCFragmentRef > (0 , 1 , <STR_LIT> ,FromNode ,  ) ) ;"
LLVM,RISCV,2546,) ;
LLVM,RISCV,2547,const StreamNode * N) {
LLVM,RISCV,2548,<const MCExpr>Expr) const ;
LLVM,RISCV,2549,;
LLVM,RISCV,2550,<ISA_LIT> );
LLVM,RISCV,2551,"<STR_LIT> , VK_<ISA_LIT>_PC ) . Case ( <STR_LIT> , VK_<ISA_LIT>_CALLA ) < ;"
LLVM,RISCV,2552,VK_<ISA_LIT>_PC <STR_LIT>_lit_pec>: return <STR_LIT>_pc;
LLVM,RISCV,2553,{
LLVM,RISCV,2554,{
LLVM,RISCV,2555,TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
LLVM,RISCV,2556,<STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_DTPREL_LO ;
LLVM,RISCV,2557,"MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ;"
LLVM,RISCV,2558,&& <STR_LIT> );
LLVM,RISCV,2559,( Num ) ;
LLVM,RISCV,2560,) ) ;
LLVM,RISCV,2561,:: MO_GlobalAddress : {
LLVM,RISCV,2562,"ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) </STR_LIT>  );"
LLVM,RISCV,2563,VK_<ISA_LIT>_TLSDESC ;
LLVM,RISCV,2564,<STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ;
LLVM,RISCV,2565,MCExpr::VK_<ISA_LIT>_LO;
LLVM,RISCV,2566,", Kind , Ctx ) ;"
LLVM,RISCV,2567,) ;
LLVM,RISCV,2568,"::MO_ConstantPoolIndex: MCOp = lowerSymbolOperand( MO, AP.getSymbol(MO.getConstantPoolIndex()), AP);"
LLVM,RISCV,2569,", <NUM_LIT> ) ;"
LLVM,RISCV,2570,
LLVM,RISCV,2571,gpu 10 : 10
LLVM,RISCV,2572,).getSubtarget ##unsigned long( ) const {
LLVM,RISCV,2573,bool IsLittleEndian = sys :: IsLittleEndianHost ) ;
LLVM,RISCV,2574,ELF :: R_<ISA_LIT>_64 ;
LLVM,RISCV,2575,) {
LLVM,RISCV,2576,ELF :: R_<ISA_LIT>_CALLPLT ;
LLVM,RISCV,2577,) ;
LLVM,RISCV,2578,;
LLVM,RISCV,2579,Invalid relocation type );
LLVM,RISCV,2580,MAI ;
LLVM,RISCV,2581,MAI ;
LLVM,RISCV,2582,CM ;
LLVM,RISCV,2583,MRI ) ;
LLVM,RISCV,2584,"& MRI , const MCTargetOptions & MCOptions );"
LLVM,RISCV,2585,X ;
LLVM,RISCV,2586,"Emitter , bool RelaxAll ) {"
LLVM,RISCV,2587,Triple &TT) {
LLVM,RISCV,2588,);
LLVM,RISCV,2589,".cstr() ,  }"
LLVM,RISCV,2590,( CPU );
LLVM,RISCV,2591,"T , create<ISA_LIT>NullTargetStreamer ) ;"
LLVM,RISCV,2592,"The last statement of this code snippet is:    return new ISA_LITTargetELFStreamer(S, STI);"
LLVM,RISCV,2593,S ) ;
LLVM,RISCV,2594,"T , create<ISA_LIT>ObjectTargetStreamer ) ;"
LLVM,RISCV,2595,;
LLVM,RISCV,2596,( TT );
LLVM,RISCV,2597,<ISA_LIT> MCRegister< undefined>Gen) ;
LLVM,RISCV,2598,;
LLVM,RISCV,2599,) ;
LLVM,RISCV,2600,"T , create<ISA_LIT>MCCodeEmitter ) ;"
LLVM,RISCV,2601,) ;
LLVM,RISCV,2602,) ? Unbelievable  :  Forgettable  ;
LLVM,RISCV,2603,lexion Modes ) ;
LLVM,RISCV,2604,<STR_LIT> ? <STR_LIT> :while ( armv8a ) report_fatal_error ( Twine ( ARMv8-A architecture is not supported on 32-bit systems.  ) + ( ) ? Please use a 64-bit system. : Please use a 32-bit system. );
LLVM,RISCV,2605,;
LLVM,RISCV,2606,", RelaxAll );"
LLVM,RISCV,2607,();
LLVM,RISCV,2608,);
LLVM,RISCV,2609,( Inst ) ;
LLVM,RISCV,2610,", true , <STL_LIT> ) ;"
LLVM,RISCV,2611,ObjectFile ;
LLVM,RISCV,2612,;
LLVM,RISCV,2613,", <STR_LIT> , FEATURES ) ;"
LLVM,RISCV,2614,: <STR_LIT> ;
LLVM,RISCV,2615,);
LLVM,RISCV,2616,12;
LLVM,RISCV,2617,) ;
LLVM,RISCV,2618,create<ISA_LIT>NullTargetStreamer ) ;
LLVM,RISCV,2619,
LLVM,RISCV,2620,Inst ;
LLVM,RISCV,2621,", <STR_LIT> ) ;"
LLVM,RISCV,2622,"T , create<ISA_LIT>MCInstrAnalysis ) ;"
LLVM,RISCV,2623,) ;
LLVM,RISCV,2624,;
LLVM,RISCV,2625,));
LLVM,RISCV,2626,"T , create<ISA_LIT>MCCodeEmitter ) ;"
LLVM,RISCV,2627,", const MCInstrInfo & MII , const MCRegisterInfo &MRI) {"
LLVM,RISCV,2628,X->__isa_lit()-> getMCRegisterInfo ( ) ;
LLVM,RISCV,2629,TT);
LLVM,RISCV,2630,", StringRef FS ,constTargetMachine & TM ){"
LLVM,RISCV,2631,create<ISA_LIT>MCCodeEmitter ) ;
LLVM,RISCV,2632,
LLVM,RISCV,2633,: {
LLVM,RISCV,2634,( ) != <NUM_LIT> || LoADDI -> <ISA_LIT> <NUM_LIT>) {
LLVM,RISCV,2635,<NUM_LIT> ) . getReg ( ) ;
LLVM,RISCV,2636,( Offset );
LLVM,RISCV,2637,;
LLVM,RISCV,2638,= nullptr ;
LLVM,RISCV,2639,LLVM_DEBUG (dbgs() << Low instruction replaced:  << Offset <<  with high instruction:  << HiLUI <<  in  << Tail.getOperand(0).getReg() << \n)
LLVM,RISCV,2640,. </STR_LIT> }
LLVM,RISCV,2641,;
LLVM,RISCV,2642,& OffsetTail ) ;
LLVM,RISCV,2643,
LLVM,RISCV,2644,. getOperand ( <NUM_LIT> ) . getReg ( ) ) ;
LLVM,RISCV,2645,() {
LLVM,RISCV,2646,: }
LLVM,RISCV,2647,) ;
LLVM,RISCV,2648,;
LLVM,RISCV,2649,"getReg ( ) , LoADDI . getOperand ( <NUM_LIT>) .getSubReg() );"
LLVM,RISCV,2650,DeadReg );
LLVM,RISCV,2651,_;
LLVM,RISCV,2652,. getReg ( ) ) ;
LLVM,RISCV,2653,createDeadCodeEliminationPass (){
LLVM,RISCV,2654,
LLVM,RISCV,2655,;
LLVM,RISCV,2656,", CopySource . getReg ( ) ) ) {"
LLVM,RISCV,2657,
LLVM,RISCV,2658,Pass();
LLVM,RISCV,2659,: 0 ) ;
LLVM,RISCV,2660,;
LLVM,RISCV,2661,) const {
LLVM,RISCV,2662,Pass ( ) ;
LLVM,RISCV,2663,;
LLVM,RISCV,2664,"(ID, TargetMachine::isPositionIndependentCode() ? PR lib/Target"
LLVM,RISCV,2665,) ) ;
LLVM,RISCV,2666,true ;
LLVM,RISCV,2667,AFNISD :: POST_INCR }
LLVM,RISCV,2668,ARM :: GPR32RegClass ;
LLVM,RISCV,2669,;
LLVM,RISCV,2670,) const {
LLVM,RISCV,2671,bool requiresRegisterScavenging ( const MachineFunction & MF ) {
LLVM,RISCV,2672,;
LLVM,RISCV,2673,;
LLVM,RISCV,2674,: return CSR_ILP32_SaveList ;
LLVM,RISCV,2675,": return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) . getHE < o  `MF.getSubtarget<ISA_LITSubtarget>().getRegisterInfo().getCallPreservedMask(MF, CallingConv::ID);"
LLVM,RISCV,2676,<STR_LIT> ) ;
LLVM,RISCV,2677,M6502::FP ) ;
LLVM,RISCV,2678,"The last statement of this code snippet is: markSuperRegs ( Reserved , <STR_LIT> ) ;"
LLVM,RISCV,2679,y }
LLVM,RISCV,2680,
LLVM,RISCV,2681,{
LLVM,RISCV,2682,;
LLVM,RISCV,2683,<STR_LIT> ) ;
LLVM,RISCV,2684,) ;
LLVM,RISCV,2685,CSR_LP64_FP64_SaveList ;
LLVM,RISCV,2686,<STR_LIT> :<STR_LIT> return CSR_IL32PC64D_L64PC128D_RegMask;
LLVM,RISCV,2687,-> getFrameIndex ( MF );
LLVM,RISCV,2688,", <STR_LIT> ) ;"
LLVM,RISCV,2689,PhysReg == SPAR->getFrameRegister(MF);
LLVM,RISCV,2690,
LLVM,RISCV,2691,
LLVM,RISCV,2692,
LLVM,RISCV,2693,BDISP1Offset ( );
LLVM,RISCV,2694,;
LLVM,RISCV,2695,RegState :: Kill )
LLVM,RISCV,2696,) ;
LLVM,RISCV,2697,System : return CSR_RegMask ;
LLVM,RISCV,2698,
LLVM,RISCV,2699,-> second ;
LLVM,RISCV,2700,;
LLVM,RISCV,2701,( ) . getRegisterInfo ( ) . isReservedRaw ( PhysReg ) ;
LLVM,RISCV,2702,. hasFMA3 ();
LLVM,RISCV,2703,{
LLVM,RISCV,2704,true ;
LLVM,RISCV,2705,;
LLVM,RISCV,2706,;
LLVM,RISCV,2707,"MF , FrameIndex , FrameReg , <NUM_LIT> ) ;"
LLVM,RISCV,2708,
LLVM,RISCV,2709,nullptr;
LLVM,RISCV,2710,:: ID ) const {
LLVM,RISCV,2711,{
LLVM,RISCV,2712,;
LLVM,RISCV,2713,return CSR_XLEN_F64_Interrupt_RestoreList ;
LLVM,RISCV,2714,= <NUM_LIT> ;
LLVM,RISCV,2715,
LLVM,RISCV,2716,) ) return CSR_RV32D_SaveList ;
LLVM,RISCV,2717,return CRS_RV32F_SaveList ;
LLVM,RISCV,2718,{
LLVM,RISCV,2719,( WST ) ;
LLVM,RISCV,2720,
LLVM,RISCV,2721,RegisterClass(Kind <ISA_LIT>_PTRRegClassID);
LLVM,RISCV,2722,
LLVM,RISCV,2723,()) {
LLVM,RISCV,2724,. hasStdExtF ( ) ) return CSR_XLEN_F32_Interrupt_RegMask ;
LLVM,RISCV,2725,{
LLVM,RISCV,2726,td ;
LLVM,RISCV,2727,;
LLVM,RISCV,2728,
LLVM,RISCV,2729,: lastEffectiveVSETVLI
LLVM,RISCV,2730,for (auto &MBB : MF) {
LLVM,RISCV,2731,);
LLVM,RISCV,2732,);
LLVM,RISCV,2733,;
LLVM,RISCV,2734,RISCV ::VSETVLI ;
LLVM,RISCV,2735,
LLVM,RISCV,2736,
LLVM,RISCV,2737,) ;
LLVM,RISCV,2738,MF ) ;
LLVM,RISCV,2739,);
LLVM,RISCV,2740,
LLVM,RISCV,2741,);
LLVM,RISCV,2742,
LLVM,RISCV,2743,);
LLVM,RISCV,2744,name() const = 0;
LLVM,RISCV,2745,
LLVM,RISCV,2746,
LLVM,RISCV,2747,) ;
LLVM,RISCV,2748,) ;
LLVM,RISCV,2749,Entry ) ;
LLVM,RISCV,2750,
LLVM,RISCV,2751,"MMO , isLoad;"
LLVM,RISCV,2752,"DstPtrInfo , MachinePointerInfo SrcPtrInfo , uint64_t SrcPtrCopySize , uint64_t DstOffset , uint64_t SrcOffset) {"
LLVM,RISCV,2753,. getTargetTriple ( ) . <ENUM_DEF> ) ) : ( <STR_LIT> ( STI . getTargetTriple ( ) . <ENUM_DEF> ) ) ;
LLVM,RISCV,2754,DAG.<ISA_LIT>getSubtarget <EOI>);
LLVM,RISCV,2755,getParent ( ) ;
LLVM,RISCV,2756,;
LLVM,RISCV,2757,) ;
LLVM,RISCV,2758,return false ;
LLVM,RISCV,2759,<STR_LIT> : return true;
LLVM,RISCV,2760,<NUM_LIT> ) . getImm ( ) ) ;
LLVM,RISCV,2761,: return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ;
LLVM,RISCV,2762,"SDValue(Op), Op.getOpcode());"
LLVM,RISCV,2763,}
LLVM,RISCV,2764,;
LLVM,RISCV,2765,: if (MI.getOperand(<NUM_LIT>).getReg() == <STR_LIT>) return true;
LLVM,RISCV,2766,) ;
LLVM,RISCV,2767,relocMode = Reloc :: Static )
LLVM,RISCV,2768,) return true ;
LLVM,RISCV,2769,StringRef Lowered Target Frame ;
LLVM,RISCV,2770,
LLVM,RISCV,2771,();
LLVM,RISCV,2772,getRegisterInfo ( ) ;
LLVM,RISCV,2773,TSInfo ;
LLVM,RISCV,2774,apos;
LLVM,RISCV,2775,nbsp;
LLVM,RISCV,2776,() const override;
LLVM,RISCV,2777,;
LLVM,RISCV,2778,return m_Value.find('A') != m_Value.npos;
LLVM,RISCV,2779,
LLVM,RISCV,2780,}
LLVM,RISCV,2781,
LLVM,RISCV,2782,{
LLVM,RISCV,2783,
LLVM,RISCV,2784,{
LLVM,RISCV,2785,hasX_ ;
LLVM,RISCV,2786,x ;
LLVM,RISCV,2787,;
LLVM,RISCV,2788,
LLVM,RISCV,2789,true ;
LLVM,RISCV,2790,return m_architecture == RV32;
LLVM,RISCV,2791,<blank> }
LLVM,RISCV,2792,RV64;
LLVM,RISCV,2793,::EDX & 0x1;
LLVM,RISCV,2794,
LLVM,RISCV,2795,
LLVM,RISCV,2796,false;
LLVM,RISCV,2797,) ;
LLVM,RISCV,2798,const ;
LLVM,RISCV,2799,const override ;
LLVM,RISCV,2800,: 1;
LLVM,RISCV,2801,1;
LLVM,RISCV,2802,;
LLVM,RISCV,2803,
LLVM,RISCV,2804,: VLen ;
LLVM,RISCV,2805,() : VLen;
LLVM,RISCV,2806,VLen;
LLVM,RISCV,2807,() const override {
LLVM,RISCV,2808,override;
LLVM,RISCV,2809,
LLVM,RISCV,2810,;
LLVM,RISCV,2811,{
LLVM,RISCV,2812,{
LLVM,RISCV,2813,uint16 CDDA) {
LLVM,RISCV,2814,d_stdext;
LLVM,RISCV,2815,"std :: next ( mFptr , 1 ) != std :: end ( mFptr);"
LLVM,RISCV,2816,m_Extensions.size() > 0;
LLVM,RISCV,2817,{
LLVM,RISCV,2818,;
LLVM,RISCV,2819,{
LLVM,RISCV,2820,;
LLVM,RISCV,2821,( ) ;
LLVM,RISCV,2822,{
LLVM,RISCV,2823,;
LLVM,RISCV,2824,;
LLVM,RISCV,2825,{
LLVM,RISCV,2826,) {
LLVM,RISCV,2827,
LLVM,RISCV,2828,mconfig::c ( ) == extZfinx;
LLVM,RISCV,2829,m_hasStdExtZhinx;
LLVM,RISCV,2830,
LLVM,RISCV,2831,{
LLVM,RISCV,2832,;
LLVM,RISCV,2833,;
LLVM,RISCV,2834,_ ;
LLVM,RISCV,2835,;
LLVM,RISCV,2836,;
LLVM,RISCV,2837,(basic_get_runtime_info() != nullptr);
LLVM,RISCV,2838,m_stdExtZksh ;
LLVM,RISCV,2839,getStdExtZvfh ( ) != StdExtZvfh :: None ;
LLVM,RISCV,2840,
LLVM,RISCV,2841,;
LLVM,RISCV,2842,2 == 0;
LLVM,RISCV,2843,() || hasVInstructionsF64();
LLVM,RISCV,2844,;
LLVM,RISCV,2845,StdExtZvfh != nullptr;
LLVM,RISCV,2846,{
LLVM,RISCV,2847,i::<Float>) {
LLVM,RISCV,2848,
LLVM,RISCV,2849,dummy;
LLVM,RISCV,2850,();
LLVM,RISCV,2851,assert ( i < NUM_REGISTERS && User reserved register index out of bounds) ;
LLVM,RISCV,2852,( ) ;
LLVM,RISCV,2853,"MaxBuildIntsCost == <NUM_LIT> ? getSchedModel ( ) . LoadLatency + <NUM_LIT> : std :: max < unsigned >, LoadLatency + <NUM_LIT>"
LLVM,RISCV,2854,MaxBuildIntsCost == 0 ? getSchedModel().LoadLatency + 20 :
LLVM,RISCV,2855,"unsigned > ( RVVVectorLMUL, 4 ) <STR_LIT> ) ;"
LLVM,RISCV,2856,<NUM_LIT> ) && <STR_LIT> <NUM_LIT> ) ;
LLVM,RISCV,2857,;
LLVM,RISCV,2858,{
LLVM,RISCV,2859,Is64Bit ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,2860,
LLVM,RISCV,2861,&MF) const {
LLVM,RISCV,2862,NUM_LIT 128 ;
LLVM,RISCV,2863,( Libvectorepc: requiresServ57();
LLVM,RISCV,2864,"::min(RVVVectorBitsMin, <NUM_LIT>)  4096 && std::string(RVVMaxVectSize must be a power of 2);"
LLVM,RISCV,2865,RVVMaxLMUL must be power of 2);
LLVM,RISCV,2866,) ) ;
LLVM,RISCV,2867,this ;
LLVM,RISCV,2868,FS . getStr() ) ) ? ( Is64Bit ? ABI :: 64 : ABI :: 32 ) {
LLVM,RISCV,2869,RBI ) ;
LLVM,RISCV,2870,);
LLVM,RISCV,2871,",  <NUM_LIT>));"
LLVM,RISCV,2872,;
LLVM,RISCV,2873,().Zvqmac;
LLVM,RISCV,2874,<TargetLowering( ) > ) ;
LLVM,RISCV,2875,;
LLVM,RISCV,2876,
LLVM,RISCV,2877,__p__ ? __p__ -> __capMode__ : false ;
LLVM,RISCV,2878,#  . ) ;
LLVM,RISCV,2879,<STR_LIT> ;
LLVM,RISCV,2880,
LLVM,RISCV,2881,
LLVM,RISCV,2882,== <STR_LIT> ) ) ;
LLVM,RISCV,2883,
LLVM,RISCV,2884,dbl);
LLVM,RISCV,2885,
LLVM,RISCV,2886,null ? ZvlLen.Length : ZvlPfn.Length;
LLVM,RISCV,2887,"has support for at least one of the following extensions: standard extension for vector arithmetic operations, standard extension for 32-bit vector floating-point instructions, or standard extension for 64-bit vector floating-point instructions."
LLVM,RISCV,2888,&& M6502Subtarget::hasFP64();
LLVM,RISCV,2889,(FCtrl & (1 << 19)) );
LLVM,RISCV,2890,2;
LLVM,RISCV,2891,_;
LLVM,RISCV,2892,p[3] ;
LLVM,RISCV,2893,return_value;
LLVM,RISCV,2894,return isObject }
LLVM,RISCV,2895,
LLVM,RISCV,2896,
LLVM,RISCV,2897,File *file) ;
LLVM,RISCV,2898,{
LLVM,RISCV,2899,{
LLVM,RISCV,2900,
LLVM,RISCV,2901,;
LLVM,RISCV,2902,;
LLVM,RISCV,2903,() && !HasStdExtVIsOpUnknown;
LLVM,RISCV,2904,() && (CurrISA() == ISA::RV64) && HasExt(EXT_V);
LLVM,RISCV,2905,"TM ), <ISA_LIT>CodegenOpt::Level::Default ) ) ;"
LLVM,RISCV,2906,<NUM_LIT> );
LLVM,RISCV,2907,Min : Min - <NUM_LIT> )
LLVM,RISCV,2908,
LLVM,RISCV,2909,
LLVM,RISCV,2910,() const {
LLVM,RISCV,2911,
LLVM,RISCV,2912,
LLVM,RISCV,2913,/IntExtRatio : 0
LLVM,RISCV,2914,Vector LMUL must be power-of-maxMaxRVVLMUL + 1  ) ;
LLVM,RISCV,2915,"(n + n - 1, LargestFTreePower2 ()), 1));"
LLVM,RISCV,2916,a);
LLVM,RISCV,2917,
LLVM,RISCV,2918,
LLVM,RISCV,2919,;
LLVM,RISCV,2920,;
LLVM,RISCV,2921,) ;
LLVM,RISCV,2922,
LLVM,RISCV,2923,() != 0;
LLVM,RISCV,2924,") , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,2925,;
LLVM,RISCV,2926,The<ISA_LIT>32Target ;
LLVM,RISCV,2927,The<ISA_LIT>64Target;
LLVM,RISCV,2928,
LLVM,RISCV,2929,", <STR_LIT> ) ;"
LLVM,RISCV,2930,.ToFile;
LLVM,RISCV,2931,;
LLVM,RISCV,2932,
LLVM,RISCV,2933,returns the llvm::Target object for the specified <ISA_LIT> ISA on a 64-bit architecture.
LLVM,RISCV,2934,", <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,2935,", <DLIT> , <CLIT> ) ;"
LLVM,RISCV,2936,) ) );
LLVM,RISCV,2937,
LLVM,RISCV,2938,
LLVM,RISCV,2939,;
LLVM,RISCV,2940,input);
LLVM,RISCV,2941,;
LLVM,RISCV,2942,() const override {
LLVM,RISCV,2943,lt;
LLVM,RISCV,2944,X(true);
LLVM,RISCV,2945,;
LLVM,RISCV,2946,
LLVM,RISCV,2947,
LLVM,RISCV,2948,"returning a pointer to a newly created yaml::MachineFunctionInfo object, which is initialized with a copy of MFI."
LLVM,RISCV,2949,</ISA_LIT>(MF);
LLVM,RISCV,2950,"return new yaml::ISA_LIT::MachineFunctionInfo(MF, Ch);"
LLVM,RISCV,2951,"return TargetTransformInfo(ISA_LIT, TTIImpl(this, F));"
LLVM,RISCV,2952,F ) );
LLVM,RISCV,2953,
LLVM,RISCV,2954,YamlMFI ;
LLVM,RISCV,2955,;
LLVM,RISCV,2956,;
LLVM,RISCV,2957,", PM ) ;"
LLVM,RISCV,2958,;
LLVM,RISCV,2959,
LLVM,RISCV,2960,initAsmParser();
LLVM,RISCV,2961,) ;
LLVM,RISCV,2962,") , initAsmBackend ( ) , initSystemZSubtargetDependencies ( ) }"
LLVM,RISCV,2963,) ;
LLVM,RISCV,2964,) ) ;
LLVM,RISCV,2965,*PM ) ;
LLVM,RISCV,2966,"TM, P);"
LLVM,RISCV,2967,);
LLVM,RISCV,2968,) );
LLVM,RISCV,2969,) ) ;
LLVM,RISCV,2970,:: getPassRegistry ( ) ;
LLVM,RISCV,2971,PR ) ;
LLVM,RISCV,2972,std::move (pPoPass) ) )  The given code snippet adds an <q>IRTranslator</q> object with a <q>std::move(pPoPass)</q> argument to a function called <q>addPass</q>. This function is part of a larger program used to handle intermediate representations of source code in compiler development systems.
LLVM,RISCV,2973,;
LLVM,RISCV,2974,) ;
LLVM,RISCV,2975,) ;
LLVM,RISCV,2976,;
LLVM,RISCV,2977,"RM ) , getEffectiveCodeModel ( CM ,  CodeModel :: Small ) ,"
LLVM,RISCV,2978,The final statement is: addPass(createMachineFunctionSplitterPass());
LLVM,RISCV,2979,
LLVM,RISCV,2980,) ) ;
LLVM,RISCV,2981,x86 ) {
LLVM,RISCV,2982,PassConfig :: <ISA_LIT>CodeAtStart ) <INSTANCE_NAME>Late->add <Br> CodeBetweenLate code = TM -> CodeGenOpt::None;
LLVM,RISCV,2983,;
LLVM,RISCV,2984,) ) ;
LLVM,RISCV,2985,;
LLVM,RISCV,2986,;
LLVM,RISCV,2987,;
LLVM,RISCV,2988,) ;
LLVM,RISCV,2989,
LLVM,RISCV,2990,
LLVM,RISCV,2991,(SrcAS == \\'_UI32(^32) && DstAS == \\'_UI32(^32) );
LLVM,RISCV,2992,;
LLVM,RISCV,2993,initialize<ISA_LIT>VectorCombinePass(*PR);
LLVM,RISCV,2994,
LLVM,RISCV,2995,", RM . getValueOr (* T . getRelocationModel ()) , CM . getValueOr (* T . getCodeModel ()) , OL ), TLOF () {"
LLVM,RISCV,2996,llvm::<ISA_LIT> < [ISA_LIT] > ) ;
LLVM,RISCV,2997,) ;
LLVM,RISCV,2998,) ;
LLVM,RISCV,2999,+ ModuleTargetABI -> getString () ;
LLVM,RISCV,3000,;
LLVM,RISCV,3001,+ PurecapOptions);
LLVM,RISCV,3002,* Subtarget . getTargetABI (). getDataLayout ());
LLVM,RISCV,3003,DestIsCheri ) ) {
LLVM,RISCV,3004,) ;
LLVM,RISCV,3005,", Options , F ) ;"
LLVM,RISCV,3006,"TT . getTriple ( ) , CPU . str ( ) , FS . str ( ) , Options , RM ? RM . get ( ) : Reloc :: Static , CM , OL , false )  The last statement of this code snippet specifies that the optional relocate model (platform-neutral transformation of compiled object code) will either be set to the input model or defaulted to Reloc::Static. It also specifies the code model (determines the representation of program code to be generated) and code generation optimization level, as well as setting the boolean flag for whether to use a JIT (just-in-time) compilation engine or"
LLVM,RISCV,3007,) ;
LLVM,RISCV,3008,( ) ) ;
LLVM,RISCV,3009,;
LLVM,RISCV,3010,;
LLVM,RISCV,3011,<TargetTransformInfo> ()) ;
LLVM,RISCV,3012,== <STR_LIT> ) {
LLVM,RISCV,3013,;
LLVM,RISCV,3014,) ;
LLVM,RISCV,3015,) ;
LLVM,RISCV,3016,
LLVM,RISCV,3017,RM ;
LLVM,RISCV,3018,
LLVM,RISCV,3019,);
LLVM,RISCV,3020,isa<ISA_LIT> ;
LLVM,RISCV,3021,( ) ;
LLVM,RISCV,3022,) ;
LLVM,RISCV,3023,"splitBlockAndAddEdge(BasicBlock *NewBB, BasicBlock *PredBB) {"
LLVM,RISCV,3024,
LLVM,RISCV,3025,
LLVM,RISCV,3026,;
LLVM,RISCV,3027,{
LLVM,RISCV,3028,) -> getZExtValue ( ) ;
LLVM,RISCV,3029,
LLVM,RISCV,3030,);
LLVM,RISCV,3031,ELF :: SHF_ALLOC ) ;
LLVM,RISCV,3032,getType () ) );
LLVM,RISCV,3033,", const <ELFTargetObjectFile::BlockHeaderSize> ) {"
LLVM,RISCV,3034,
LLVM,RISCV,3035,Size ) const {
LLVM,RISCV,3036,", TM ) ;"
LLVM,RISCV,3037,
LLVM,RISCV,3038,( ) ? 8 : 4 ) ;
LLVM,RISCV,3039,> (*(TM.get() -> getIsaCPU())));
LLVM,RISCV,3040,* > (__RTM);
LLVM,RISCV,3041,
LLVM,RISCV,3042,;
LLVM,RISCV,3043,", SupportMCSection ) ) {"
LLVM,RISCV,3044,:: SHF_WRITE | ELF :: SHF_ALLOC ) ;
LLVM,RISCV,3045,", TM ) ;"
LLVM,RISCV,3046,
LLVM,RISCV,3047,"hello, world!</STR_LIT>;"
LLVM,RISCV,3048,endl;
LLVM,RISCV,3049,
LLVM,RISCV,3050,
LLVM,RISCV,3051,() {
LLVM,RISCV,3052,( ) ) ;
LLVM,RISCV,3053,"offsetToNextString, const AsmToken &val) {"
LLVM,RISCV,3054,{
LLVM,RISCV,3055,ABI) {
LLVM,RISCV,3056,StringRef) {
LLVM,RISCV,3057,<STR_LIT> ;
LLVM,RISCV,3058,) Arch += <STR_LIT>;
LLVM,RISCV,3059,<STR_LIT> ;
LLVM,RISCV,3060,= * ParseResult ;
LLVM,RISCV,3061,Arch += <STR_LIT> ;
LLVM,RISCV,3062,) ;
LLVM,RISCV,3063,+= <STR_LIT> ;
LLVM,RISCV,3064,) ) Arch += <STR_LIT> ;
LLVM,RISCV,3065,;
LLVM,RISCV,3066,<STR_LIT> : return <NUM_LIT> ;
LLVM,RISCV,3067,();
LLVM,RISCV,3068,);
LLVM,RISCV,3069,) {
LLVM,RISCV,3070,
LLVM,RISCV,3071,
LLVM,RISCV,3072,
LLVM,RISCV,3073,-> getScalarSizeInBits ( ) :  8;
LLVM,RISCV,3074,"(Size .getKnownMinValue(), 128) ;"
LLVM,RISCV,3075,The correct way to complete the code snippet is: 2 * ScalableVectorType::getNumElements(Tp);
LLVM,RISCV,3076,Tp ) ;
LLVM,RISCV,3077,. first ;
LLVM,RISCV,3078,;
LLVM,RISCV,3079,Illegal );
LLVM,RISCV,3080,
LLVM,RISCV,3081,;
LLVM,RISCV,3082,
LLVM,RISCV,3083,
LLVM,RISCV,3084,",8,Alignment ) ;"
LLVM,RISCV,3085,"Ptr, Type * NewVal) {"
LLVM,RISCV,3086,Xor : return true ;
LLVM,RISCV,3087,( ) && ST -> hasV }
LLVM,RISCV,3088,__ST->hasStdExt() &&  __ST-> hasVirtualization() ;
LLVM,RISCV,3089,DataType->getMinElementCount();
LLVM,RISCV,3090,ST->getMaxELENForFixedLengthVectors();
LLVM,RISCV,3091,) ) ;
LLVM,RISCV,3092,) ) ;
LLVM,RISCV,3093,getParent();
LLVM,RISCV,3094,{
LLVM,RISCV,3095,
LLVM,RISCV,3096,0 ;
LLVM,RISCV,3097,) ;
LLVM,RISCV,3098,>= <NUM_LIT> ) return true ;
LLVM,RISCV,3099,getElementType ( ) ) ;
LLVM,RISCV,3100,) ) ;
LLVM,RISCV,3101,;
LLVM,RISCV,3102,( ) ;
LLVM,RISCV,3103,"getIntImmCost ( IID , Idx , Imm , Ty ) ;"
LLVM,RISCV,3104,int64_t ScalarCost ){
LLVM,RISCV,3105,( ) : 0
LLVM,RISCV,3106,return false;
LLVM,RISCV,3107,getContext ( );
LLVM,RISCV,3108,NULL;
LLVM,RISCV,3109,Pub = (value);
LLVM,RISCV,3110,() const {
LLVM,RISCV,3111,if (Cost > 0) UP.VectorizationFactor = Cost;
LLVM,RISCV,3112,isLittleEndian ( ) ) ;
LLVM,RISCV,3113,Instruction::isCommutative(Opcode) || UsedImm ) {
LLVM,RISCV,3114,:: Sub <STR_LIT> && Inst->getType() == Ty;
LLVM,RISCV,3115,TargetTransformInfo::TargetCostKind CostKind) const override {
LLVM,RISCV,3116,> ( Branch->getCondition ( ) ) ) {
LLVM,RISCV,3117,{
LLVM,RISCV,3118,{
LLVM,RISCV,3119,:: TCC_Free ;
LLVM,RISCV,3120,"getKnownMinSize ( ) , ST -> getVLen ( ));"
LLVM,RISCV,3121,Cost ;
LLVM,RISCV,3122,Opcode ) ;
LLVM,RISCV,3123,;
LLVM,RISCV,3124,
LLVM,RISCV,3125,getNumElements();
LLVM,RISCV,3126,( ) LT ;
LLVM,RISCV,3127,
LLVM,RISCV,3128,( ) );
LLVM,RISCV,3129,"() , ST );"
LLVM,RISCV,3130,{
LLVM,RISCV,3131,Sub : case RecurKind :: Mul : case RecurKind :: Shl : return true ;
LLVM,RISCV,3132,"Ty , TTI :: TCK_SizeAndLatency ) ;"
LLVM,RISCV,3133,);
LLVM,RISCV,3134,TLI->isLegalElementTypeForRVV(DataType->getScalarType());
LLVM,RISCV,3135,getScalarType ( ) );
LLVM,RISCV,3136,;
LLVM,RISCV,3137,":: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ;"
LLVM,RISCV,3138,"getGatherScatterOpCost(Opcode, DataTy, Ptr, NumLoads, VariableMask, Alignment, CostKind, I);"
LLVM,RISCV,3139,) ;
LLVM,RISCV,3140,"Ty , <NUM_LIT> , TTI :: TCK_ );"
LLVM,RISCV,3141,TTI :: PSK_Software ;
LLVM,RISCV,3142,isPowerOf2_32(TyWidth));
LLVM,RISCV,3143,Subtarget }
LLVM,RISCV,3144,- {
LLVM,RISCV,3145,____ true;
LLVM,ARC,0,) ;
LLVM,ARC,1,) ;
LLVM,ARC,2,
LLVM,ARC,3,TmpInst );
LLVM,ARC,4,;
LLVM,ARC,5,"RegisterAsmPrinter<ISA_LIT>AsmPrinter > X(mycoolasmprinter, My Cool asmprinter description);"
LLVM,ARC,6,
LLVM,ARC,7,( ) ;
LLVM,ARC,8,) ;
LLVM,ARC,9,MI->dump();
LLVM,ARC,10,) ;
LLVM,ARC,11,"MI , <NUM_LIT> ) ;"
LLVM,ARC,12,getPassRegistry ( ) ) ;
LLVM,ARC,13,
LLVM,ARC,14,<STR_LIT> ;
LLVM,ARC,15,1 ;
LLVM,ARC,16,ISD :: UNDEF ) {
LLVM,ARC,17,const override {
LLVM,ARC,18,
LLVM,ARC,19,addImm ( <NUM_LIT> ) ;
LLVM,ARC,20,. addImm(getCCForBRcc(MI->getOperand(1).getImm()));
LLVM,ARC,21,) ;
LLVM,ARC,22,) ;
LLVM,ARC,23,
LLVM,ARC,24,
LLVM,ARC,25,Fail }
LLVM,ARC,26,;
LLVM,ARC,27,) ) ;
LLVM,ARC,28,", Address , Decoder ) ;"
LLVM,ARC,29,<NUM_LIT>;
LLVM,ARC,30,Success ;
LLVM,ARC,31,
LLVM,ARC,32,) ) ) ;
LLVM,ARC,33,) ;
LLVM,ARC,34,+ Offset ;
LLVM,ARC,35,;
LLVM,ARC,36,"<STR_LIT> Result = decodeInstruction (DecoderTable32, Instr, Insn32, Address, this, STI);"
LLVM,ARC,37,) << <STR_LIT> ) ;
LLVM,ARC,38,", create<ISA_LIT>Disassembler ) ;"
LLVM,ARC,39,NUM_LIT) ;
LLVM,ARC,40,CreateReg ( <NUM_LIT> ) ) ;
LLVM,ARC,41,Success ;
LLVM,ARC,42,
LLVM,ARC,43,<Expr> ));
LLVM,ARC,44,Offset ) {
LLVM,ARC,45,Offset ;
LLVM,ARC,46,0;
LLVM,ARC,47,"uint64_t Offset , enum Opcode Opcode );"
LLVM,ARC,48,) ;
LLVM,ARC,49,) ) ) ;
LLVM,ARC,50,Ty . getSizeInBits ( ))));
LLVM,ARC,51,8( SIMM25Fields :: addr ( S ) ))) ;
LLVM,ARC,52,Imm ) ) );
LLVM,ARC,53,::Success;
LLVM,ARC,54,;
LLVM,ARC,55,FailOperand <NUM_LIT> ;
LLVM,ARC,56,;
LLVM,ARC,57,"Address , Decoder ) ;"
LLVM,ARC,58,Insn64 ) ) {
LLVM,ARC,59,;
LLVM,ARC,60,Inst.addOperand (MCOperand::createReg (DstA)).
LLVM,ARC,61,
LLVM,ARC,62,createImm ( LImm ) ) ;
LLVM,ARC,63,&Ctx ) {
LLVM,ARC,64,<NUM_BITS> );
LLVM,ARC,65,"( Insn , <NUM_LIT> , <NUM_LIT> );"
LLVM,ARC,66,( <NUM_LIT> );
LLVM,ARC,67,
LLVM,ARC,68,:: Success
LLVM,ARC,69,) ;
LLVM,ARC,70,"const mask, unsigned const value ) {"
LLVM,ARC,71,FailOperand ;
LLVM,ARC,72,0 : max ) )
LLVM,ARC,73,) ;
LLVM,ARC,74,}
LLVM,ARC,75,) ) ;
LLVM,ARC,76,:: Success ;
LLVM,ARC,77,
LLVM,ARC,78,Succeed ;
LLVM,ARC,79,", <NUM_LIT> );"
LLVM,ARC,80,;
LLVM,ARC,81,_U6 ( Insn ) ;
LLVM,ARC,82,;
LLVM,ARC,83,));
LLVM,ARC,84,. Operands [ Op . getOperandNo () ].setExpression ( <span style=color: blue;
LLVM,ARC,85,
LLVM,ARC,86,reinterpret_cast<MCDisassembler *> (Access) );
LLVM,ARC,87,<NUM_LIT> );
LLVM,ARC,88,[ <NUM_LIT> ] << 0 ) ;
LLVM,ARC,89,) ;
LLVM,ARC,90,<NUM_LIT> );
LLVM,ARC,91,Rb ) . addReg ( Ra ) ;
LLVM,ARC,92,( ) ;
LLVM,ARC,93,<NUM_LIT> ) ;
LLVM,ARC,94,addImm(0);
LLVM,ARC,95,true ;
LLVM,ARC,96,
LLVM,ARC,97,createFunctionSimplificationPass() {
LLVM,ARC,98,"DL , MBB , MBBI ) ;"
LLVM,ARC,99,-> getVarArgsFrameIndex ( ) ) ;
LLVM,ARC,100,) . setMIFlags ( MachineInstr :: FrameSetup ) ;
LLVM,ARC,101,( ) ;
LLVM,ARC,102,
LLVM,ARC,103,0 ) {
LLVM,ARC,104,;
LLVM,ARC,105,StackSlotsUsedByFunclet ) ) Opc = <STR_LIT> ;
LLVM,ARC,106,) ;
LLVM,ARC,107,:: Kill ) ;
LLVM,ARC,108,&& <EXPR_LIT> Stack adjustment must be a multiple of  <NUM_LIT> bytes ) ;
LLVM,ARC,109,;
LLVM,ARC,110,. getFrameIdx ( ) ;
LLVM,ARC,111,;
LLVM,ARC,112,CurOffset ;
LLVM,ARC,113,"( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( StackSize - AmountAboveFunclet ) ;"
LLVM,ARC,114,
LLVM,ARC,115,? <STR_LIT> : <STR_LIT> ;
LLVM,ARC,116,;
LLVM,ARC,117,;
LLVM,ARC,118,
LLVM,ARC,119,false ;
LLVM,ARC,120,;
LLVM,ARC,121,HasFP ;
LLVM,ARC,122,) {
LLVM,ARC,123,", true ) ) ;"
LLVM,ARC,124,SP ) ;
LLVM,ARC,125,"The absolute value of Amount is: << Amount << , which is the same as Absolute Amount: << AbsAmount << \n;"
LLVM,ARC,126,++I ) {
LLVM,ARC,127,end();
LLVM,ARC,128,) ;
LLVM,ARC,129,"FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , std :: vector < CalleeSavedInfo > & CSI , unsigned & <VPOP>Bytes ) const"
LLVM,ARC,130,
LLVM,ARC,131,: return <STR_LIT> ;
LLVM,ARC,132,<STR_LIT> : return <STR_LIT> ;
LLVM,ARC,133,
LLVM,ARC,134,"The last statement of this code snippet is: returns U6 shifted by the value of the number literal, multiplied by the result of the MI operation and divided by the product of the OpNum and VarNum variables."
LLVM,ARC,135,< =  << Dag->getRegisterName(Value) << \n;
LLVM,ARC,136,: return <STR_LIT> ;
LLVM,ARC,137,) ;
LLVM,ARC,138,;
LLVM,ARC,139,<STR_LIT> ;
LLVM,ARC,140,succeeded ;
LLVM,ARC,141,
LLVM,ARC,142,. getImm ( ) ) ;
LLVM,ARC,143,{
LLVM,ARC,144,Annot ) ;
LLVM,ARC,145,getImm ( ) ;
LLVM,ARC,146,getImm ( ) ;
LLVM,ARC,147,-> <ISA_LIT>getOperand ( OpNum ) ;
LLVM,ARC,148,getImm ( ) ) ;
LLVM,ARC,149,;
LLVM,ARC,150,() ;
LLVM,ARC,151,( ) ;
LLVM,ARC,152,
LLVM,ARC,153,"<< <STR_LIT> << PrintReg ( SrcReg , TRI ) << <STR_LIT> <<<STR_LIT> << Imm << endl);"
LLVM,ARC,154,<< <NUM_LIT> ;
LLVM,ARC,155,
LLVM,ARC,156,
LLVM,ARC,157,"get(mov, MachineImmOperand);"
LLVM,ARC,158,Register class does not match. );
LLVM,ARC,159,;
LLVM,ARC,160,MI ) ) return true ;
LLVM,ARC,161,) ;
LLVM,ARC,162,return <NUM_LIT>;
LLVM,ARC,163,
LLVM,ARC,164,;
LLVM,ARC,165,;
LLVM,ARC,166,;
LLVM,ARC,167,Memory operand is NULL ) ;
LLVM,ARC,168,
LLVM,ARC,169,
LLVM,ARC,170,. getObjectAlign ( FrameIndex ) ) ;
LLVM,ARC,171,;
LLVM,ARC,172,
LLVM,ARC,173,) ;
LLVM,ARC,174,;
LLVM,ARC,175,}
LLVM,ARC,176,== BinaryOperator::Or || Opc == BinaryOperator::And;
LLVM,ARC,177,<FLOAT_LIT>;
LLVM,ARC,178,0 || Opc == 39;
LLVM,ARC,179,
LLVM,ARC,180,LDSP_LIT ;
LLVM,ARC,181,
LLVM,ARC,182,
LLVM,ARC,183,( ) ) ) {
LLVM,ARC,184,
LLVM,ARC,185,<STR_LIT>);
LLVM,ARC,186,
LLVM,ARC,187,) ) ) ;
LLVM,ARC,188,"with <STR_LIT>, <STR_LIT> }"
LLVM,ARC,189,1) Addr.getOperand(1);
LLVM,ARC,190,( 0 )}
LLVM,ARC,191,;
LLVM,ARC,192,RHSC ) ) {
LLVM,ARC,193,true ;
LLVM,ARC,194,) ;
LLVM,ARC,195,true ;
LLVM,ARC,196,;
LLVM,ARC,197,"i ] , VReg ) ;"
LLVM,ARC,198,getByValSize ( ) ;
LLVM,ARC,199,DAG ) ;
LLVM,ARC,200,Custom ) ;
LLVM,ARC,201,Expand ) ;
LLVM,ARC,202,);
LLVM,ARC,203,Legal ) ;
LLVM,ARC,204,) {
LLVM,ARC,205,;
LLVM,ARC,206,1 && == 1 ;
LLVM,ARC,207,". first , RegsToPass [ i ] . second . getValueType ( ) ) ) ;"
LLVM,ARC,208,. getValueType ( ) ;
LLVM,ARC,209,"TargetOps:: <STR_LIT>,Ga,{"
LLVM,ARC,210,DAG ) ;
LLVM,ARC,211,"<%, MemOpChains) ;"
LLVM,ARC,212,( CC );
LLVM,ARC,213,Op.getValueType() == MVT::v16i8 && Width == 128)
LLVM,ARC,214,Value SV = cast<SrcValueSDNode>(Op.getOperand(1));
LLVM,ARC,215,;
LLVM,ARC,216,}
LLVM,ARC,217,"explicitFunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( 0 ), VarArgsStackOffset (0)"
LLVM,ARC,218,Size ( <NUM_LIT> ) {
LLVM,ARC,219,( 1 ) }
LLVM,ARC,220,
LLVM,ARC,221,);
LLVM,ARC,222,OffsetToNextFrame ;
LLVM,ARC,223,
LLVM,ARC,224,;
LLVM,ARC,225,;
LLVM,ARC,226,;
LLVM,ARC,227,
LLVM,ARC,228,
LLVM,ARC,229,ArrayRef();
LLVM,ARC,230,getOpcode();
LLVM,ARC,231,;
LLVM,ARC,232,:: MO_GlobalAddress :
LLVM,ARC,233,"( Symbol , MCSymbolRefExpr :: VK_None , getContext ( ) )  ;"
LLVM,ARC,234,
LLVM,ARC,235,FS );
LLVM,ARC,236,) ;
LLVM,ARC,237,"Register , Offset ) ;"
LLVM,ARC,238,;
LLVM,ARC,239,", SyntaxVariant );"
LLVM,ARC,240,) ;
LLVM,ARC,241,) ;
LLVM,ARC,242,) ;
LLVM,ARC,243,) ;
LLVM,ARC,244,) ;
LLVM,ARC,245,if (IsStore) Ldst.addOperand(NewOffset);
LLVM,ARC,246,) ;
LLVM,ARC,247,( ) ;
LLVM,ARC,248,
LLVM,ARC,249,;
LLVM,ARC,250,", UsesAfterAdd , UsesAfterLdst ) ) {"
LLVM,ARC,251,begin ( ) ;
LLVM,ARC,252,) ;
LLVM,ARC,253,Changed ;
LLVM,ARC,254,;
LLVM,ARC,255,. getOpcode ( ) ) ;
LLVM,ARC,256,;
LLVM,ARC,257,
LLVM,ARC,258,& MI ) ;
LLVM,ARC,259,
LLVM,ARC,260,
LLVM,ARC,261,{
LLVM,ARC,262,( <STR_LIT> ) ;
LLVM,ARC,263,MO.getImm() == NewOffset);
LLVM,ARC,264,) ;
LLVM,ARC,265,) ;
LLVM,ARC,266,SLL :  Sign * MI.getOperand(0).getImm();
LLVM,ARC,267,) ;
LLVM,ARC,268,{
LLVM,ARC,269,)-> getReg ();
LLVM,ARC,270,;
LLVM,ARC,271,) ;
LLVM,ARC,272,;
LLVM,ARC,273,) && <STR_LIT> ) ;
LLVM,ARC,274,Offset ) ;
LLVM,ARC,275,);
LLVM,ARC,276,;
LLVM,ARC,277,<< <STR_LIT> ) ;
LLVM,ARC,278,) ;
LLVM,ARC,279,) const {
LLVM,ARC,280,|| private;
LLVM,ARC,281,
LLVM,ARC,282,;
LLVM,ARC,283,savedRegs ;
LLVM,ARC,284,<STR_LIT> ;
LLVM,ARC,285,Reserved ;
LLVM,ARC,286,
LLVM,ARC,287,addReg ( FrameReg ) . addImm ( Offset ) ;
LLVM,ARC,288,& ) const ;
LLVM,ARC,289,;
LLVM,ARC,290,() const override {
LLVM,ARC,291,frameLowering;
LLVM,ARC,292,InstrInfo;
LLVM,ARC,293,unsigned <ISA_LIT>OptLevel) const;
LLVM,ARC,294,16);
LLVM,ARC,295,SelectionDAGInfo* database ) const override {
LLVM,ARC,296,Lowering;
LLVM,ARC,297,const std::string& path) {
LLVM,ARC,298,) ;
LLVM,ARC,299,
LLVM,ARC,300,RegisterTarget < Triple :: arc > X ( getThe<ISA_LIT>Target ( ) );
LLVM,ARC,301,{
LLVM,ARC,302,"() ), is_emebedded ( false ) {"
LLVM,ARC,303,0 );
LLVM,ARC,304,( ) );
LLVM,ARC,305,);
LLVM,ARC,306,;
LLVM,ARC,307,CM;
LLVM,ARC,308,Variant ( );
LLVM,ARC,309,
LLVM,ARC,310,
LLVM,ARC,311,", d );"
LLVM,ARC,312,)) ;
LLVM,ARC,313,&F) {
LLVM,ARC,314,* this ) ) ;
LLVM,ARC,315,false ) );
LLVM,ARC,316,) ) ;
LLVM,ARC,317,PassName {
LLVM,ARC,318,getAnalysisUsage(AnalysisUsage &AU) const {
LLVM,ARC,319,{
LLVM,ARC,320,getTarget());
LLVM,ARC,321,;
LLVM,ARC,322,) ;
LLVM,ARC,323,Success ;
LLVM,ARC,324,Subtarget;
LLVM,ARC,325,;
LLVM,ARC,326,
LLVM,ARC,327,
GCC,nvptx,86,") , INIT_LOCATION ( ) ) ;"
LLVM,RISCV,2462,TPReg.getReg() == ARM::PC  SrcSymbol.isanyExpr() && SrcSymbol.getExpr()->getKind() == ARM::MCExpr::VK_ARM_TP