GCC,nvptx,0,fclose ( in ) ;
GCC,nvptx,1,
GCC,nvptx,2,
GCC,nvptx,3,if ( ptx_name ) maybe_unlink ( ptx_name ) ;
GCC,nvptx,4,Stmt * stmt = heap++;
GCC,nvptx,5,stmt->next = NULL;
GCC,nvptx,6,"fork_execute(new_argv[0], CONST_CAST(char * *, new_argv), true);"
GCC,nvptx,7,"obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ;"
GCC,nvptx,8,if ( found )
GCC,nvptx,9,if ( tok -> kind == '=' ) {
GCC,nvptx,10,
GCC,nvptx,11,Here's a breakdown of the code:
GCC,nvptx,12,
GCC,nvptx,13,
GCC,nvptx,14,
GCC,nvptx,15,"buffer = XNEWVEC ( char , alloc ) ;"
GCC,nvptx,16,next = stmt->next;
GCC,nvptx,17,
GCC,nvptx,18,tok -> end = <NUM_LIT> ;
GCC,nvptx,19,
GCC,nvptx,20,
GCC,nvptx,21,"write_tokens(out, stmt->tokens, stmt->len, (stmt->vis & V_mask) == V_pred);"
GCC,nvptx,22,"fputs(<STR_LIT>, out);"
GCC,nvptx,23,
GCC,nvptx,24,"write_token(out, toks);"
GCC,nvptx,25,"obstack_ptr_grow ( & argv_obstack , driver ) ;"
GCC,nvptx,26,
GCC,nvptx,27,
GCC,nvptx,28,"fork_execute(new_argv[0], CONST_CAST(char **, new_argv), true, <STR_LIT>);"
GCC,nvptx,29,"After the `for` loop, the `return` statement will be executed, which will return control to the calling"
GCC,nvptx,30,unlink(file);
GCC,nvptx,31,
GCC,nvptx,32,values[i] = curval;
GCC,nvptx,33,
GCC,nvptx,34,"buffer = XNEWVEC ( char , alloc ) ;"
GCC,nvptx,35,buffer[base] = '\0';
GCC,nvptx,36,
GCC,nvptx,37,
GCC,nvptx,38,
GCC,nvptx,39,return 0;
GCC,nvptx,40,"cpp_define_formatted ( parse_in , <STR_LIT> , minor ) ;"
GCC,nvptx,41,
GCC,nvptx,42,if ( cfun -> machine -> has_simtreg )
GCC,nvptx,43,
GCC,nvptx,44,rtx pat;
GCC,nvptx,45,
GCC,nvptx,46,r = make_ssa_name (TREE_TYPE (var));
GCC,nvptx,47,
GCC,nvptx,48,
GCC,nvptx,49,
GCC,nvptx,50,
GCC,nvptx,51,tree arg = TREE_VALUE ( args ) ;
GCC,nvptx,52,"fprintf(asm_out_file, <STR_LIT>);"
GCC,nvptx,53,"fprintf(asm_out_file, <STR_LIT>);"
GCC,nvptx,54,"assemble_name_raw ( file , name ) ;"
GCC,nvptx,55,* pmode = DImode;
GCC,nvptx,56,if ( GET_CODE ( addr ) != SYMBOL_REF ) return ADDR_SPACE_GENERIC ;
GCC,nvptx,57,return ADDR_SPACE_CONST;
GCC,nvptx,58,"fprintf ( file , <STR_LIT> , TYPE_ALIGN ( TREE_TYPE ( exp ) ) / BITS_PER_UNIT , decl_chunk_size * BITS_PER_UNIT ) ;"
GCC,nvptx,59,"fprintf(asm_out_file, <STR_LIT>);"
GCC,nvptx,60,
GCC,nvptx,61,"nvptx_assemble_value ( val , size ) ;"
GCC,nvptx,62,"fputs ( <STR_LIT> , file ) ;"
GCC,nvptx,63,init_part |= val_part << ( BITS_PER_UNIT * chunk_offset ) ;
GCC,nvptx,64,args_so_far = cfun->machine->call_args;
GCC,nvptx,65,"fprintf ( file , <STR_LIT> , TREE_PUBLIC ( decl ) ? <STR_LIT> : <STR_LIT> , section , DECL_ALIGN ( decl ) / BITS_PER_UNIT , decl_chunk_size * BITS_PER_UNIT ) ;"
GCC,nvptx,66,
GCC,nvptx,67,"rtx * slot = declared_libfuncs_htab->find_slot(callee, INSERT);"
GCC,nvptx,68,"rtx * slot = declared_libfuncs_htab->find_slot(callee, INSERT);"
GCC,nvptx,69,
GCC,nvptx,70,"#define FOR_EACH_HASH_TABLE_ELEMENT(HTAB, DECL, TREE, I"
GCC,nvptx,71,"fputs ( <STR_LIT> , asm_out_file ) ;"
GCC,nvptx,72,"fprintf ( asm_out_file , <STR_LIT> , GET_MODE_BITSIZE ( Pmode ) ) ;"
GCC,nvptx,73,
GCC,nvptx,74,return gen_reg_rtx ( mode ) ;
GCC,nvptx,75,cum -> count += <NUM_LIT> ;
GCC,nvptx,76,return <NUM_LIT> * BITS_PER_UNIT;
GCC,nvptx,77,"fprintf(file, <STR_LIT>);"
GCC,nvptx,78,"If `named` is not `NULL`, the function creates a new `RTX` object using the `gen_rtx_UNSPEC` function. The `gen_rtx_UNSPEC` function takes three arguments: `mode`, `gen_rtvec`,"
GCC,nvptx,79,"mode = promote_function_mode ( type , orig_mode , & unsignedp , NULL_TREE , <NUM_LIT> ) ;"
GCC,nvptx,80,"return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,81,* no_add_attrs = true;
GCC,nvptx,82,return mode == cfun->machine->ret_reg_mode;
GCC,nvptx,83,return mode == cfun->machine->ret_reg_mode;
GCC,nvptx,84,p->ret_reg_mode = VOIDmode;
GCC,nvptx,85,"return gen_rtx_REG (mode, NVPTX_REG_R0);"
GCC,nvptx,86,code = ( as == ADDR_SPACE_GLOBAL ? UNSPEC_FROM_GLOBAL : as == ADDR_SPACE_LOCAL ? UNSPEC_FROM_LOCAL : as == ADDR_SPACE_SHARED ? UNSPEC_FROM_SHARED : as == ADDR_SPACE_CONST ? UNSPEC_FROM_CONST : UNSPEC_FROM_PARAM ) ;
GCC,nvptx,87,"rtx nvptx_maybe_convert_symbolic_operand ( rtx orig_op ) { if ( GET_MODE ( orig_op ) != Pmode ) return orig_op ; rtx op = orig_op ; while ( GET_CODE ( op ) == PLUS || GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) != SYMBOL_REF ) return orig_op ; tree decl = SYMBO"
GCC,nvptx,88,flag_toplevel_reorder = <NUM_LIT> ;
GCC,nvptx,89,"fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,90,tree result_type = TREE_TYPE ( fntype ) ;
GCC,nvptx,91,mode = arg_promotion ( mode ) ;
GCC,nvptx,92,"nvptx_assemble_value ( <NUM_LIT> , decl_chunk_size ) ;"
GCC,nvptx,93,
GCC,nvptx,94,"off = XEXP ( x , <NUM_LIT> ) ;"
GCC,nvptx,95,switch ( GET_CODE ( x ) ) {
GCC,nvptx,96,
GCC,nvptx,97,"nvptx_print_address_operand(file, addr, VO"
GCC,nvptx,98,mode = arg_promotion ( mode ) ;
GCC,nvptx,99,mode = arg_promotion(mode);
GCC,nvptx,100,return <STR_LIT>;
GCC,nvptx,101,if (force || !DECL_EXTERNAL (decl)) {
GCC,nvptx,102,"tree * slot = declared_fndecls_htab->find_slot(decl, INSERT);"
GCC,nvptx,103,Some possible next statements could include:
GCC,nvptx,104,
GCC,nvptx,105,"fprintf(asm_out_file, "" %s"", IDENTIFIER_POINTER(DECL_ASSEMBLER_NAME(decl)));`"
GCC,nvptx,106,"fprintf(asm_out_file, "" %s"", IDENTIFIER_POINTER(DECL_ASSEMBLER_NAME(decl)));`"
GCC,nvptx,107,if (recog_data.operand_type[i] != OP_OUT) {
GCC,nvptx,108,
GCC,nvptx,109,
GCC,nvptx,110,return false;
GCC,nvptx,111,return <STR_LIT>;
GCC,nvptx,112,return <STR_LIT> ;
GCC,nvptx,113,return <STR_LIT> ;
GCC,nvptx,114,
GCC,nvptx,115,"return gen_rtx_REG ( Pmode , STATIC_CHAIN_REGNUM ) ;"
GCC,nvptx,116,
GCC,nvptx,117,mode = GET_MODE ( obj ) ;
GCC,nvptx,118,return mode;
GCC,nvptx,119,s << <STR_LIT> << i << <STR_LIT> ;
GCC,nvptx,120,"Alternatively, the `begin_decl_field` function could be used"
GCC,nvptx,121,args_from_decl = true ;
GCC,nvptx,122,"return (lookup_attribute(<STR_LIT>, attrs) != NULL_TREE || lookup_attribute(<STR_LIT>, attrs) != NULL_TREE);"
GCC,nvptx,123,s << name;
GCC,nvptx,124,"s << name << ""("";"
GCC,nvptx,125,
GCC,nvptx,126,
GCC,nvptx,127,"write_one_arg (s, NULL_TREE, i, mode, false);"
GCC,nvptx,128,"s << <STR_LIT> << nvptx_ptx_type_from_mode ( mode , false ) << <STR_LIT> << ( i + <NUM_LIT> ) << ( mode == QImode || mode == HImode ? <STR_LIT> : <STR_LIT> ) ;"
GCC,nvptx,129,if (flags & BB
GCC,nvptx,130,
GCC,nvptx,131,"fprintf ( file , <STR_LIT> , section , align / BITS_PER_UNIT , elt_size * BITS_PER_UNIT ) ;"
GCC,nvptx,132,"fprintf ( file, <STR_LIT> ) ;"
GCC,nvptx,133,
GCC,nvptx,134,init_frag . offset += part ;
GCC,nvptx,135,int maxregs = max_reg_num ( ) ;
GCC,nvptx,136,"fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ;"
GCC,nvptx,137,
GCC,nvptx,138,break;
GCC,nvptx,139,
GCC,nvptx,140,emit_insn ( gen_nvptx_joining ( op ) ) ;
GCC,nvptx,141,"SET_SYMBOL_DATA_AREA ( XEXP ( rtl , <NUM_LIT> ) , area ) ;"
GCC,nvptx,142,"return nvptx_expand_shuffle ( exp , target , mode , ignore ) ;"
GCC,nvptx,143,vec = rtvec_alloc ( nargs + <NUM_LIT> ) ;
GCC,nvptx,144,rtx addr = worker_red_sym;
GCC,nvptx,145,"rtx addr = gen_rtx_CONST ( Pmode , addr ) ;"
GCC,nvptx,146,"write_worker_buffer(asm_out_file, worker_bcast_sym, worker_bcast_align, worker_bcast_size);"
GCC,nvptx,147,"fputs(func_decls.str().c_str(), asm_out_file);"
GCC,nvptx,148,
GCC,nvptx,149,"return nvptx_function_arg_reg (mode, named);"
GCC,nvptx,150,
GCC,nvptx,151,"rtx nvptx_function_value ( const_tree type , const_tree func , bool outgoing ) {"
GCC,nvptx,152,"return nvptx_libcall_value ( mode , NULL_RTX ) ;"
GCC,nvptx,153,"res = gen_packsidi2 ( dst , src0 , src1 ) ;"
GCC,nvptx,154,case DImode :
GCC,nvptx,155,"emit_insn ( gen_sel_truesi ( tmp , src , GEN_INT ( <NUM_LIT> ) , const0_rtx ) ) ;"
GCC,nvptx,156,
GCC,nvptx,157,"return nvptx_gen_shuffle ( reg , reg , const0_rtx , SHUFFLE_IDX ) ;"
GCC,nvptx,158,"res = gen_rtx_SET ( addr , reg ) ;"
GCC,nvptx,159,"tree addr = build_call_expr ( fndecl, 3, type, size, align, offset );"
GCC,nvptx,160,
GCC,nvptx,161,case IFN_GOACC_REDUCTION_TEARDOWN:
GCC,nvptx,162,
GCC,nvptx,163,
GCC,nvptx,164,
GCC,nvptx,165,"gimplify_assign ( lhs , var , & seq ) ;"
GCC,nvptx,166,TREE_THIS_VOLATILE ( var ) = <NUM_LIT>;
GCC,nvptx,167,dims[GOMP_DIM_WORKER] = PTX_WORKER_LENGTH;
GCC,nvptx,168,"fprintf(file, ""axis %s"", name);"
GCC,nvptx,169,
GCC,nvptx,170,
GCC,nvptx,171,"return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,172,return gen_reg_rtx ( mode ) ;
GCC,nvptx,173,
GCC,nvptx,174,"gsi_insert_seq_before ( gsi , latch_seq , GSI_SAME_STMT ) ;"
GCC,nvptx,175,"worker_bcast_sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ;"
GCC,nvptx,176,
GCC,nvptx,177,"if ( GET_CODE ( sym ) == CONST ) sym = XEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> ) ;"
GCC,nvptx,178,
GCC,nvptx,179,inner_mask |= par -> inner_mask ;
GCC,nvptx,180,if (par->mask & GOMP_DIM_MASK(GOMP_DIM_MAX)) {
GCC,nvptx,181,"emit_insn ( gen_rtx_SET ( idx , GEN_INT ( fs ) ) ) ;"
GCC,nvptx,182,
GCC,nvptx,183,"fprintf(asm_out_file, <STR_LIT>, size);"
GCC,nvptx,184,tree attr = get_oacc_fn_attrib ( current_function_decl ) ;
GCC,nvptx,185,
GCC,nvptx,186,"if (target->flags & BB_VISITED) n = nvptx_sese_number(n, p, dir, target, list);"
GCC,nvptx,187,
GCC,nvptx,188,
GCC,nvptx,189,hi_child = t_hi;
GCC,nvptx,190,if ( GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) == mask ) {
GCC,nvptx,191,if ( GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) == mask ) {
GCC,nvptx,192,"nvptx_propagate ( block , insn , PM_read_write , vprop_gen , <NUM_LIT> ) ;"
GCC,nvptx,193,worker_bcast_size = data . offset ;
GCC,nvptx,194,
GCC,nvptx,195,
GCC,nvptx,196,
GCC,nvptx,197,return nvptx_gen_vcast ( reg ) ;
GCC,nvptx,198,data->ptr = gen_reg_rtx(Pmode);
GCC,nvptx,199,
GCC,nvptx,200,
GCC,nvptx,201,"fprintf(file, <STR_LIT>);"
GCC,nvptx,202,
GCC,nvptx,203,if ( cfun->machine->has_simtreg )
GCC,nvptx,204,
GCC,nvptx,205,
GCC,nvptx,206,
GCC,nvptx,207,
GCC,nvptx,208,if ( dims [ GOMP_DIM_WORKER ] > PTX_WORKER_LENGTH ) {
GCC,nvptx,209,dims[GOMP_DIM_WORKER] = PTX_WORKER_LENGTH;
GCC,nvptx,210,
GCC,nvptx,211,"fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,212,
GCC,nvptx,213,
GCC,nvptx,214,gcc_assert ( ! ( mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ) || ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ) ;
GCC,nvptx,215,
GCC,nvptx,216,return PTX_VECTOR_LENGTH;
GCC,nvptx,217,
GCC,nvptx,218,HOST_WIDE_INT &simtsz = cfun->machine->simt_stack_size;
GCC,nvptx,219,"fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ;"
GCC,nvptx,220,
GCC,nvptx,221,start_sequence ( ) ;
GCC,nvptx,222,
GCC,nvptx,223,"gsi_insert_seq_before (&gsi, init_seq, GSI_SAME_STMT);"
GCC,nvptx,224,"gimple_seq_add_stmt (&seq, cond_stmt);"
GCC,nvptx,225,init_machine_status = nvptx_init_machine_status;
GCC,nvptx,226,"nvptx_wpropagate ( false , is_call , par -> forked_block , par -> forked_insn ) ;"
GCC,nvptx,227,"emit_insn ( gen_rtx_SET ( pred, gen_rtx_NE ( BImode, idx, const0_rtx ) ) ) ;"
GCC,nvptx,228,
GCC,nvptx,229,
GCC,nvptx,230,"oacc_set_fn_attrib (current_function_decl, attr);"
GCC,nvptx,231,
GCC,nvptx,232,if (data.offset) {
GCC,nvptx,233,"return nvptx_expand_shuffle ( exp , target , mode , ignore ) ;"
GCC,nvptx,234,
GCC,nvptx,235,
GCC,nvptx,236,
GCC,nvptx,237,INSN_P ( insn )
GCC,nvptx,238,"bb_sese ( unsigned node_ , unsigned p , int dir_ ) : node ( node_ ) , parent ( p ) , dir ( dir_ ) {"
GCC,nvptx,239,"bb_sese ( unsigned node_ , unsigned p , int dir_ ) : node ( node_ ) , parent ( p ) , dir ( dir_ ) {"
GCC,nvptx,240,
GCC,nvptx,241,
GCC,nvptx,242,res = first;
GCC,nvptx,243,gcc_assert ( first <= res ) ;
GCC,nvptx,244,case PTX_ISA_SM80 : return PTX_VERSION_7_0 ;
GCC,nvptx,245,case PTX_ISA_SM80 : return PTX_VERSION_7_0 ;
GCC,nvptx,246,return true;
GCC,nvptx,247,
GCC,nvptx,248,
GCC,nvptx,249,"BB_SET_SESE ( block , <NUM_LIT> ) ;"
GCC,nvptx,250,"worklist.safe_push(insn_bb_t(insn, block));"
GCC,nvptx,251,
GCC,nvptx,252,if ( dump_file && ( dump_flags & TDF_DETAILS ) )
GCC,nvptx,253,
GCC,nvptx,254,"sese->push(pseudo_node_t(target, usd * t_sese->dir));"
GCC,nvptx,255,
GCC,nvptx,256,return comment;
GCC,nvptx,257,color_counts.quick_push(<NUM_LIT>)
GCC,nvptx,258,color_counts.quick_push(<NUM_LIT>);
GCC,nvptx,259,r->n_allocated++;
GCC,nvptx,260,if (ptx_version_option < first) {
GCC,nvptx,261,return htab_hash_pointer ( t ) ;
GCC,nvptx,262,if (partition_level == NULL_TREE)
GCC,nvptx,263,max_workers = oa.num_workers;
GCC,nvptx,264,max_workers = PTX_CTA_SIZE / oa.vector_length;
GCC,nvptx,265,"fprintf(file, <STR_LIT>, POINTER_SIZE, reg_names[regno]);"
GCC,nvptx,266,
GCC,nvptx,267,
GCC,nvptx,268,
GCC,nvptx,269,
GCC,nvptx,270,return false;
GCC,nvptx,271,dims[GOMP_DIM_VECTOR] = PTX_WARP_SIZE;
GCC,nvptx,272,"fprintf ( file, <STR_LIT> ) ;"
GCC,nvptx,273,"nvptx_assemble_decl_begin ( file , name , <STR_LIT> , type , obj_size , TYPE_ALIGN ( type ) ) ;"
GCC,nvptx,274,TREE_ASM_WRITTEN ( name ) = <NUM_LIT> ;
GCC,nvptx,275,"fputs(s.str().c_str(), stream);"
GCC,nvptx,276,init_frag.size = elt_size;
GCC,nvptx,277,init_frag.size = elt_size;
GCC,nvptx,278,"fprintf(asm_out_file, init_frag.started ? <STR_LIT> : <STR_LIT>);"
GCC,nvptx,279,
GCC,nvptx,280,
GCC,nvptx,281,init_frag.offset += part;
GCC,nvptx,282,for (unsigned part = <NUM_LIT>; size; size -= part) {
GCC,nvptx,283,return nvptx_builtin_decls[code];
GCC,nvptx,284,cfun->machine->num_args++;
GCC,nvptx,285,gcc_checking_assert ( GET_CODE ( addr ) == SYMBOL_REF ) ;
GCC,nvptx,286,
GCC,nvptx,287,case CODE_FOR_nvptx_shufflesf :
GCC,nvptx,288,return false;
GCC,nvptx,289,"if ( XEXP ( x , <NUM_LIT> ) == pc_rtx && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == LABEL_REF ) return XEXP ( x , <NUM_LIT> ) ;"
GCC,nvptx,290,return basic_align;
GCC,nvptx,291,
GCC,nvptx,292,
GCC,nvptx,293,
GCC,nvptx,294,
GCC,nvptx,295,
GCC,nvptx,296,
GCC,nvptx,297,"fprintf ( dump_file , <STR_LIT> ) ;"
GCC,nvptx,298,emit_insn ( gen_nvptx_fork ( op ) ) ;
GCC,nvptx,299,rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ;
GCC,nvptx,300,mask &= ( GOMP_DIM_MASK ( GOMP_DIM_WORKER ) | GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) ;
GCC,nvptx,301,"SET_SYMBOL_DATA_AREA ( XEXP ( rtl , <NUM_LIT> ) , area ) ;"
GCC,nvptx,302,
GCC,nvptx,303,return;
GCC,nvptx,304,emit_insn ( gen_nvptx_membar_gl ( ) ) ;
GCC,nvptx,305,"return nvptx_expand_shuffle ( exp , target , mode , ignore ) ;"
GCC,nvptx,306,emit_call_insn (pat);
GCC,nvptx,307,
GCC,nvptx,308,"rtx cmp = gen_rtx_fmt_ee ( GET_CODE ( compare ) , BImode , XEXP ( compare , <NUM_LIT> ) , XEXP ( compare , <NUM_LIT> ) ) ;"
GCC,nvptx,309,
GCC,nvptx,310,
GCC,nvptx,311,"nvptx_emit_joining(GOMP_DIM_MASK(mode), false);"
GCC,nvptx,312,
GCC,nvptx,313,"rtx dest = expand_expr ( CALL_EXPR_ARG ( exp , <NUM_LIT> + 1 ) , NULL_RTX , mode , EXPAND_NORMAL ) ;"
GCC,nvptx,314,"if ( ! REG_P ( op ) && GET_CODE ( op ) != CONST_INT ) op = copy_to_mode_reg ( SImode , op ) ;"
GCC,nvptx,315,"fputs ( <STR_LIT> , asm_out_file ) ;"
GCC,nvptx,316,"fputs("" PTX ISA version: "", asm_out_file);"
GCC,nvptx,317,"par -> fork_insn = nvptx_discover_pre ( block , CODE_FOR_nvptx_fork ) ;"
GCC,nvptx,318,
GCC,nvptx,319,"return nvptx_function_arg_reg (cumulative_args, arg);"
GCC,nvptx,320,
GCC,nvptx,321,cum_v.num_args++;
GCC,nvptx,322,return GET_MODE_ALIGNMENT ( mode );
GCC,nvptx,323,return GET_MODE_ALIGNMENT ( mode );
GCC,nvptx,324,"fprintf(file, <STR_LIT>);"
GCC,nvptx,325,cum->args[cum->num_args++] = arg;
GCC,nvptx,326,
GCC,nvptx,327,
GCC,nvptx,328,
GCC,nvptx,329,"return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,330,
GCC,nvptx,331,return regno == NVPTX_RETURN_REGNUM;
GCC,nvptx,332,
GCC,nvptx,333,case V2DImode:
GCC,nvptx,334,
GCC,nvptx,335,"res = gen_unpackdisi2 ( dst0 , dst1 , src ) ;"
GCC,nvptx,336,return arg_pointer_rtx;
GCC,nvptx,337,return NULL_RTX;
GCC,nvptx,338,"tree align = build_int_cst ( unsigned_type_node , GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ) ;"
GCC,nvptx,339,return master;
GCC,nvptx,340,return master;
GCC,nvptx,341,return pred;
GCC,nvptx,342,Here are a few possibilities for what the next statement could be:
GCC,nvptx,343,Here are a few possibilities for what the next statement could be:
GCC,nvptx,344,TREE_ADDRESSABLE (v) = <NUM_LIT>;
GCC,nvptx,345,
GCC,nvptx,346,tree id = get_identifier ( <STR_LIT> ) ;
GCC,nvptx,347,
GCC,nvptx,348,return false;
GCC,nvptx,349,
GCC,nvptx,350,case IFN_GOACC_REDUCTION_TEARDOWN:
GCC,nvptx,351,
GCC,nvptx,352,
GCC,nvptx,353,
GCC,nvptx,354,"gimple_seq_add_stmt ( &seq, tid_call ) ;"
GCC,nvptx,355,"gimplify_assign ( lhs , var , & seq ) ;"
GCC,nvptx,356,gsi_next ( gsi ) ;
GCC,nvptx,357,gcc_assert ( dims [ GOMP_DIM_VECTOR ] != <NUM_LIT> ) ;
GCC,nvptx,358,if ( offload_region_p && has_vector_partitionable_routine_calls_p ( decl ) ) {
GCC,nvptx,359,"error ( <STR_LIT> , name ) ;"
GCC,nvptx,360,* no_add_attrs = true ;
GCC,nvptx,361,"return nvptx_num_regs (mode, regno);"
GCC,nvptx,362,
GCC,nvptx,363,gcc_assert(vector_red_partition * nvptx_mach_max_workers() <= vector_red_size);
GCC,nvptx,364,
GCC,nvptx,365,
GCC,nvptx,366,return p;
GCC,nvptx,367,return p;
GCC,nvptx,368,"fprintf ( file , <STR_LIT> ) ;"
GCC,nvptx,369,
GCC,nvptx,370,case CONST:
GCC,nvptx,371,
GCC,nvptx,372,"return gen_rtx_REG ( mode , NVPTX_RETURN_REGNUM ) ;"
GCC,nvptx,373,if (type != NULL_TREE) return type == float_type_node || type == double_type_node; else return true;
GCC,nvptx,374,return false;
GCC,nvptx,375,return false;
GCC,nvptx,376,"Next, the code"
GCC,nvptx,377,
GCC,nvptx,378,
GCC,nvptx,379,return 1;
GCC,nvptx,380,return cfun -> machine -> axis_dim [ MACH_VECTOR_LENGTH ] ;
GCC,nvptx,381,return cfun->machine->axis_dim;
GCC,nvptx,382,nvptx_record_needed_fndecl ( decl ) ;
GCC,nvptx,383,nvptx_record_needed_fndecl ( decl ) ;
GCC,nvptx,384,subrtx_iterator iter ( addr ) ;
GCC,nvptx,385,return NULL;
GCC,nvptx,386,
GCC,nvptx,387,if (area == NVPTX_DATA_A
GCC,nvptx,388,return area == DATA_AREA_SHARED || area == DATA_AREA_GENERIC;
GCC,nvptx,389,
GCC,nvptx,390,"if ( strcmp ( name , ""Jane"" ) == 0 ) return ""Jane Doe"" ;"
GCC,nvptx,391,return <STR_LIT>;
GCC,nvptx,392,if (worker) {
GCC,nvptx,393,bool large_vector = (mask & GOMP_DIM_MASK(GOMP_DIM_VECTOR)) && nvptx_mach_vector_length() != PTX_WARP_SIZE;
GCC,nvptx,394,bb_pair_vec_t regions;
GCC,nvptx,395,rtx_insn * join = inner->join_insn;
GCC,nvptx,396,par->mask |= inner->mask & (GOMP_DIM_MASK(GOMP_DIM_MAX) - <NUM_LIT>);
GCC,nvptx,397,
GCC,nvptx,398,
GCC,nvptx,399,"fprintf ( file , <STR_LIT> , TREE_PUBLIC ( decl ) ? <STR_LIT> : <STR_LIT> ) ;"
GCC,nvptx,400,"nvptx_output_barrier (&operands[mem_pos], INTVAL(operands[memmodel_pos]), false);"
GCC,nvptx,401,
GCC,nvptx,402,
GCC,nvptx,403,
GCC,nvptx,404,if ( GET_MODE_SIZE ( dst_inner ) == GET_MODE_SIZE ( src_inner ) ) {
GCC,nvptx,405,
GCC,nvptx,406,
GCC,nvptx,407,
GCC,nvptx,408,return nvptx_output_set_softstack_reg (src_regno);
GCC,nvptx,409,
GCC,nvptx,410,return <STR_LIT>;
GCC,nvptx,411,
GCC,nvptx,412,output_init_frag(NULL_RTX);
GCC,nvptx,413,"fprintf ( file , <STR_LIT> , bits , reg_stack , regno , bits / <NUM_LIT> ) ;"
GCC,nvptx,414,
GCC,nvptx,415,pat = PATTERN ( insn ) ;
GCC,nvptx,416,return pat;
GCC,nvptx,417,return V2SImode;
GCC,nvptx,418,
GCC,nvptx,419,
GCC,nvptx,420,
GCC,nvptx,421,
GCC,nvptx,422,
GCC,nvptx,423,return c == '.' || c == '#' || c == ' ' ;
GCC,nvptx,424,return c == '.' || c == '#' || c == ' ' ;
GCC,nvptx,425,if (empty_loop_p && !no_prop_p) {
GCC,nvptx,426,"machine_mode nvptx_promote_function_mode ( const_tree type , machine_mode mode , int * ARG_UNUSED ( punsignedp ) , const_tree funtype , int for_return )"
GCC,nvptx,427,"return promote_arg ( mode , for_return || ! type || TYPE_ARG_TYPES ( funtype ) ) ;"
GCC,nvptx,428,"emit_insn ( gen_rtx_SET ( tmp , frame_pointer_rtx ) ) ;"
GCC,nvptx,429,
GCC,nvptx,430,return <STR_LIT> ;
GCC,nvptx,431,"declared_fndecls_htab->insert(decl, slot);"
GCC,nvptx,432,
GCC,nvptx,433,"declared_libfuncs_htab->find_slot(callee, INSERT);"
GCC,nvptx,434,*slot = decl;
GCC,nvptx,435,"tree * slot = needed_fndecls_htab->find_slot(decl, INSERT);"
GCC,nvptx,436,
GCC,nvptx,437,
GCC,nvptx,438,"return nvptx_lockless_update ( loc , gsi , ptr , var , op ) ;"
GCC,nvptx,439,
GCC,nvptx,440,nvptx_reorg_subreg ( ) ;
GCC,nvptx,441,
GCC,nvptx,442,pred = NULL_RTX;
GCC,nvptx,443,p[i] = '$';
GCC,nvptx,444,return false;
GCC,nvptx,445,
GCC,nvptx,446,edge e;
GCC,nvptx,447,edges = dir > <NUM_LIT> ? b->succs : b->preds;
GCC,nvptx,448,
GCC,nvptx,449,sese->high = hi_back < hi_child ? node_back : node_child;
GCC,nvptx,450,vector_red_partition = <NUM_LIT> ;
GCC,nvptx,451,"emit_insn_after(init, insn);"
GCC,nvptx,452,"rtx init = gen_rtx_SET (data.base, bcast_sym);"
GCC,nvptx,453,return PTX_WARP_SIZE;
GCC,nvptx,454,return PTX_WARP_SIZE;
GCC,nvptx,455,
GCC,nvptx,456,
GCC,nvptx,457,tail = par->join_block;
GCC,nvptx,458,unsigned ix;
GCC,nvptx,459,"worklist.safe_push(insn_bb_t(insn, block));"
GCC,nvptx,460,
GCC,nvptx,461,return false;
GCC,nvptx,462,return true;
GCC,nvptx,463,return true;
GCC,nvptx,464,"emit_insn_after (nvptx_gen_shuffle (reg, reg, master, SHUFFLE_IDX), insn);"
GCC,nvptx,465,return false;
GCC,nvptx,466,return false;
GCC,nvptx,467,
GCC,nvptx,468,"align = MAX ( align , GET_MODE_ALIGNMENT ( TYPE_MODE ( type ) ) ) ;"
GCC,nvptx,469,"return nvptx_propagate ( is_call , block , insn , PM_read_write , warp_prop_gen , <NUM_LIT> , false ) ;"
GCC,nvptx,470,"return nvptx_propagate ( is_call , block , insn , PM_read_write , warp_prop_gen , <NUM_LIT> , false ) ;"
GCC,nvptx,471,if (l < <NUM_LIT>)
GCC,nvptx,472,if (l < <NUM_LIT>)
GCC,nvptx,473,"if ( ! function ) fprintf ( asm_out_file , <STR_LIT> ) ;"
GCC,nvptx,474,"fprintf(asm_out_file, <STR_LIT>)"
GCC,nvptx,475,"output_reg(file, regno, inner_mode, GET_MODE_SIZE(inner_mode));"
GCC,nvptx,476,parent -> inner = this ;
GCC,nvptx,477,return true;
GCC,nvptx,478,tree t = TREE_VALUE ( dims ) ;
GCC,nvptx,479,if (GET_CODE(PATTERN(insn)) == ASM_INPUT || GET_CODE(PATTERN(insn)) == ASM_OPERANDS || (GET_CODE(PATTERN(insn)) == PARALLEL && asm_noperands(PATTERN(insn)) >= <NUM_LIT>)))
GCC,nvptx,480,return mode;
GCC,nvptx,481,return mode;
GCC,nvptx,482,
GCC,nvptx,483,"return promote_arg ( mode , true ) ;"
GCC,nvptx,484,
GCC,nvptx,485,
GCC,nvptx,486,brackets.safe_push(bracket(back));
GCC,nvptx,487,while (removed--) brackets.pop();
GCC,nvptx,488,brackets[ix].back = pseudo;
GCC,nvptx,489,
GCC,nvptx,490,
GCC,nvptx,491,data->ptr = NULL_RTX;
GCC,nvptx,492,return # XX ;
GCC,nvptx,493,
GCC,nvptx,494,if (maybe_split_mode(mode) != VOIDmode) {
GCC,nvptx,495,
GCC,nvptx,496,if ( seen_vector_label || seen_worker_label ) {
GCC,nvptx,497,gcc_assert ( ! seen_vector_label ) ;
GCC,nvptx,498,
GCC,nvptx,499,return reg;
GCC,nvptx,500,reg = rtx_alloc (pm->mode);
GCC,nvptx,501,
GCC,nvptx,502,if (INSN_P(insn)) switch (recog_memoized(insn)) { ... }
GCC,nvptx,503,
GCC,nvptx,504,
GCC,nvptx,505,"insert_here = emit_insn_before ( inits , first ) ;"
GCC,nvptx,506,"insert_here = emit_insn_after(inits, insert_here);"
GCC,nvptx,507,
GCC,nvptx,508,"FOR_EACH_BB_FN (bb, cfun) {"
GCC,nvptx,509,
GCC,nvptx,510,After the assignment
GCC,nvptx,511,"return (lookup_attribute(<STR_LIT>, attrs) != NULL_TREE || (lookup_attribute(<STR_LIT>, attrs) != NULL_TREE && lookup_attribute(<STR_LIT>, attrs) != NULL_TREE));"
GCC,nvptx,512,"return (lookup_attribute(<STR_LIT>, attrs) != NULL_TREE || (lookup_attribute(<STR_LIT>, attrs) != NULL_TREE && lookup_attribute(<STR_LIT>, attrs) != NULL_TREE));"
GCC,nvptx,513,s << name << <STR_LIT> ;
GCC,nvptx,514,name++;
GCC,nvptx,515,return name;
GCC,nvptx,516,s << name;
GCC,nvptx,517,s << name;
GCC,nvptx,518,"write_fn_marker(s, false, true, name);"
GCC,nvptx,519,s << pfx << ptx_type << <STR_LIT> << reg_names [ NVPTX_RETURN_REGNUM ] << sfx;
GCC,nvptx,520,
GCC,nvptx,521,if ( for_proto ) return return_in_mem ;
GCC,nvptx,522,"fprintf(file, <STR_LIT>, align, name, size);"
GCC,nvptx,523,"fprintf(file, <STR_LIT>, align, name, size);"
GCC,nvptx,524,"assemble_name_raw ( file , name ) ;"
GCC,nvptx,525,
GCC,nvptx,526,
GCC,riscv,0,return <STR_LIT>;
GCC,riscv,1,
GCC,riscv,2,mode << <STR_LIT> << mlen << <STR_LIT> ;
GCC,riscv,3,"return floattype(eew, elmul_log2);"
GCC,riscv,4,elmul_log2 = lmul_log2 + std::log2(eew/sew);
GCC,riscv,5,lmul_log2 = - lmul_log2;
GCC,riscv,6,case <NUM_LIT> : return lmul_log2 >= - <NUM_LIT> && ! float_p ;
GCC,riscv,7,tree new_flags = create_tmp_var_raw ( RISCV_ATYPE_USI ) ;
GCC,riscv,8,return riscv_builtin_decls[subcode];
GCC,riscv,9,"case RISCV_BUILTIN_GENERAL : { const struct riscv_builtin_description * d = & riscv_builtins [ subcode ] ; switch ( d -> builtin_type ) { case RISCV_BUILTIN_DIRECT : return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ;"
GCC,riscv,10,riscv_builtins[i] = <SOME_VALUE>;
GCC,riscv,11,tree type = riscv_build_function_type ( d -> prototype );
GCC,riscv,12,riscv_float16_type_node->type = REAL_TYPE;
GCC,riscv,13,gcc_assert ( opno + call_expr_nargs ( exp ) == insn_data [ icode ] . n_generator_args ) ;
GCC,riscv,14,case RISCV_BUILTIN_MD:
GCC,riscv,15,"tree arg = TREE_OPERAND ( CALL_EXPR_ARG ( exp , 0 ) , <NUM_LIT> ) ;"
GCC,riscv,16,"case RISCV_BUILTIN_DIRECT_NO_TARGET: return riscv_expand_builtin_direct ( d -> icode , target , exp , false ) ;"
GCC,riscv,17,tree type = riscv_build_function_type ( d->prototype );
GCC,riscv,18,tree type = riscv_build_function_type ( d -> prototype ) ;
GCC,riscv,19,
GCC,riscv,20,"* update = build_call_expr ( frflags, <NUM_LIT>, old_flags );"
GCC,riscv,21,"types[(int)type] = build_function_type_list(RISCV_FTYPE_ATYPES##NUM_ARGS, NULL_TREE);"
GCC,riscv,22,"types[(int)type] = build_function_type_list(RISCV_FTYPE_ATYPES##NUM_ARGS, NULL_TREE);"
GCC,riscv,23,"return riscv_expand_builtin_direct ( d -> icode , target , exp , true ) ;"
GCC,riscv,24,"riscv_prepare_builtin_arg(&ops[opno++], exp, argno);"
GCC,riscv,25,
GCC,riscv,26,"riscv_builtin_decls[i] = add_builtin_function(d->name, type, i, BUILT_IN_MD, NULL, NULL);"
GCC,riscv,27,riscv_builtin_decl_index[d->icode] = i;
GCC,riscv,28,"case RISCV_BUILTIN_VECTOR : return <STR_LIT> ( loc , arg_loc , subcode , orig_fndecl , nargs , args ) ;"
GCC,riscv,29,"builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ;"
GCC,riscv,30,return ( major * <NUM_LIT> ) + ( minor * <NUM_LIT> ) ;
GCC,riscv,31,"error ( ""TARGET_VECTOR is not set"" ) ;"
GCC,riscv,32,
GCC,riscv,33,builtin_define ( <STR_LIT> ) ;
GCC,riscv,34,"builtin_define_with_int_value ( <STR_LIT> , <NUM_LIT> ) ;"
GCC,riscv,35,
GCC,riscv,36,
GCC,riscv,37,d_add_builtin_version(<STR_LIT>);
GCC,riscv,38,d_add_builtin_version(<STR_LIT>);
GCC,riscv,39,gcc_assert ( REG_P ( dest ) ) ;
GCC,riscv,40,case MULT: if (op1_val.is_constant()) return op1_val.to_constant() * op2_val;
GCC,riscv,41,
GCC,riscv,42,
GCC,riscv,43,riscv_reinit();
GCC,riscv,44,"rtx ele = const_double_from_real_value ( f , inner_mode ) ;"
GCC,riscv,45,rtx_insn * insn = get_last_insn ( ) ;
GCC,riscv,46,"ASSERT_TRUE(known_eq(calculate_x_in_sequence(dest), poly_val));"
GCC,riscv,47,
GCC,riscv,48,"set_new_first_and_last_insn(NULL, NULL);"
GCC,riscv,49,
GCC,riscv,50,"riscv_parse_arch_string(m_arch_backup.c_str(), &global_options, UNKNOWN_LOCATION);"
GCC,riscv,51,
GCC,riscv,52,
GCC,riscv,53,if (i == <NUM_LIT>) {
GCC,riscv,54,m = analyze(bb);
GCC,riscv,55,
GCC,riscv,56,"FOR_ALL_BB_FN ( bb , fn ) {"
GCC,riscv,57,
GCC,riscv,58,"XEXP ( XEXP ( pat , i ) , <NUM_LIT> ) = replace_equiv_address ( XEXP ( mem , <NUM_LIT> ) , addr ) ;"
GCC,riscv,59,if (regno == <NUM_LIT>) {
GCC,riscv,60,return TARGET_RVC && riscv_mshorten_memrefs && optimize > <NUM_LIT>;
GCC,riscv,61,* `TARGET_RVC`: This is a macro that expands to a boolean value indicating whether the target architecture is RISC-V.
GCC,riscv,62,if (mem != <SOME_VALUE> || GET_MODE ( mem ) != SImode)
GCC,riscv,63,
GCC,riscv,64,rtl_opt_pass *pass = make_pass_shorten_memrefs(ctxt);
GCC,riscv,65,"pass_shorten_memrefs ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_shorten_memrefs , ctxt ) {"
GCC,riscv,66,"pass_shorten_memrefs ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_shorten_memrefs , ctxt ) {"
GCC,riscv,67,"if ( XEXP ( pat , <NUM_LIT> ) == CONST0_RTX ( GET_MODE ( XEXP ( pat"
GCC,riscv,68,tmp = NEXT_INSN ( tmp ) ;
GCC,riscv,69,df_ref use;
GCC,riscv,70,if ( ! call_used_regs [ DF_REF_REGNO ( use ) ] ) {
GCC,riscv,71,if ( ! call_used_regs [ DF_REF_REGNO ( use ) ] ) {
GCC,riscv,72,
GCC,riscv,73,
GCC,riscv,74,
GCC,riscv,75,insn = NEXT_INSN (insn);
GCC,riscv,76,
GCC,riscv,77,
GCC,riscv,78,
GCC,riscv,79,
GCC,riscv,80,return CP_READ_MEMORY | CP_WRITE_CSR;
GCC,riscv,81,return CP_READ_MEMORY | CP_WRITE_CSR;
GCC,riscv,82,
GCC,riscv,83,
GCC,riscv,84,
GCC,riscv,85,"rtx vlenb = gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ;"
GCC,riscv,86,
GCC,riscv,87,
GCC,riscv,88,return true;
GCC,riscv,89,return false;
GCC,riscv,90,return false;
GCC,riscv,91,Here are a few possibilities:
GCC,riscv,92,
GCC,riscv,93,
GCC,riscv,94,
GCC,riscv,95,"auto_vec<tree, <NUM_LIT>> argument_types(<NUM_LIT>);"
GCC,riscv,96,"return c.require_immediate(<NUM_LIT>, <NUM_LIT>, nvecs - <NUM_LIT>);"
GCC,riscv,97,b.append_name(predication_suffixes[instance.pred])
GCC,riscv,98,"add_operand ( mode , CONSTM1_RTX ( mode"
GCC,riscv,99,"return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ;"
GCC,riscv,100,
GCC,riscv,101,
GCC,riscv,102,unsigned int code = vec_safe_length(registered_functions);
GCC,riscv,103,Here are a few possibilities:
GCC,riscv,104,"m_ops[opno] = create_input_operand(op, mode);"
GCC,riscv,105,"create_integer_operand(&m_ops[opno++], INTVAL(x));"
GCC,riscv,106,
GCC,riscv,107,"* `gen_rtx_MEM` is a function that creates a new RTX node representing a memory reference. It takes two arguments: `mode`, which specifies the machine mode of the memory reference, and `memory_address`, which specifies the address of the memory location being referenced."
GCC,riscv,108,m_ops[opno++] = target;
GCC,riscv,109,"add_input_operand ( mode , gen_scalar_move_mask ( mode ) ) ;"
GCC,riscv,110,"TYPE_ATTRIBUTES (type) = tree_cons (get_identifier (<STR_LIT>), value, TYPE_ATTRIBUTES (type));"
GCC,riscv,111,"TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , value , TYPE_ATTRIBUTES ( type ) ) ;"
GCC,riscv,112,"In general, the `add_vundef_operand` method is used to add a new operand to the function expander's operand list, and the `machine_mode"
GCC,riscv,113,for ( unsigned int i = <NUM_LIT> ; i < <NUM_LIT> ; i++ ) {
GCC,riscv,114,
GCC,riscv,115,
GCC,riscv,116,
GCC,riscv,117,append_name(name);
GCC,riscv,118,char *finished_string = obstack_finish ( &m_string_obstack ) ;
GCC,riscv,119,char *finished_string = obstack_finish ( &m_string_obstack ) ;
GCC,riscv,120,
GCC,riscv,121,
GCC,riscv,122,
GCC,riscv,123,"Next, it gets the `mask_type_index` from the `function_types` array and uses it to get the `mask_"
GCC,riscv,124,
GCC,riscv,125,return true;
GCC,riscv,126,
GCC,riscv,127,"return build_pointer_type ( build_qualified_type ( t , TYPE_QUAL_CONST ) ) ;"
GCC,riscv,128,
GCC,riscv,129,"However, based on the name of the function and the parameters it takes, it is likely that the next statement will be a call to a function that is a member of the `function_base` class, and that the function will use the `instance` parameter to perform some operation on the `function_instance` object"
GCC,riscv,130,
GCC,riscv,131,return true;
GCC,riscv,132,return true;
GCC,riscv,133,
GCC,riscv,134,
GCC,riscv,135,if (required_extensions_p(op_info->args[i].base_type)) {
GCC,riscv,136,If neither of the above
GCC,riscv,137,if (flags & CALL_PROPERTY_
GCC,riscv,138,return value.first == key.first && value.second == key.second;
GCC,riscv,139,return base->expand(*this);
GCC,riscv,140,
GCC,riscv,141,"rtx exp = expand_builtin_expr (code, exp, target);"
GCC,riscv,142,"return function_expander(rfn.instance, rfn.decl, exp, target).expand();"
GCC,riscv,143,
GCC,riscv,144,return m_string_obstack.finish();
GCC,riscv,145,
GCC,riscv,146,
GCC,riscv,147,"function_call_info :: function_call_info ( location_t location_in , const function_instance & instance_in , tree fndecl_in ) : function_instance ( instance_in ) , location ( location_in ) , fndecl ( fndecl"
GCC,riscv,148,"function_call_info :: function_call_info ( location_t location_in , const function_instance & instance_in , tree fndecl_in ) : function_instance ( instance_in ) , location ( location_in ) , fndecl ( fndecl"
GCC,riscv,149,
GCC,riscv,150,
GCC,riscv,151,opno = <NUM_LIT>;
GCC,riscv,152,this->base_name = base_name_in;
GCC,riscv,153,this->base_name = base_name_in;
GCC,riscv,154,
GCC,riscv,155,
GCC,riscv,156,"error(""<STR_LIT>"");"
GCC,riscv,157,
GCC,riscv,158,"attrs = add_attribute(<STR_LIT>, attrs);"
GCC,riscv,159,return type ? function_types[type_idx].type_indexes[base_type] : NUM_VECTOR_TYPES;
GCC,riscv,160,
GCC,riscv,161,
GCC,riscv,162,
GCC,riscv,163,hashval_t hash = instance.hash(hash);
GCC,riscv,164,
GCC,riscv,165,for (unsigned int i = <NUM_LIT>; b_ops[i].index != NUM_VECTOR_TYPES; i++)
GCC,riscv,166,return builtin_types[type_idx].scalar_ptr;
GCC,riscv,167,return builtin_types[VECTOR_TYPE_vuint8mf8_t].scalar_ptr;
GCC,riscv,168,return builtin_types[get_function_type_index(type_idx)].scalar;
GCC,riscv,169,return builtin_types[get_function_type_index(type_idx)].scalar;
GCC,riscv,170,
GCC,riscv,171,
GCC,riscv,172,
GCC,riscv,173,return builtin_types[get_function_type_index(type_idx)].vector;
GCC,riscv,174,return builtin_types[get_function_type_index(type_idx)].vector;
GCC,riscv,175,this->gsi = gsi_in;
GCC,riscv,176,this->gsi = gsi_in;
GCC,riscv,177,"GIMPLE is a low-level, intermediate representation of C code that is used by the GCC (GNU Compiler Collection) to generate optimized machine code for various platforms. The `gimple_fold_builtin` function is likely to be a part of"
GCC,riscv,178,
GCC,riscv,179,gt_ggc_mx (function_instance *)
GCC,riscv,180,gt_ggc_mx (function_instance *)
GCC,riscv,181,
GCC,riscv,182,
GCC,riscv,183,
GCC,riscv,184,function_table->insert(new registered_function_hasher(type_i));
GCC,riscv,185,
GCC,riscv,186,
GCC,riscv,187,
GCC,riscv,188,rvv_switcher rvv = new rvv_switcher(rvv);
GCC,riscv,189,register_builtin_types ( ) ;
GCC,riscv,190,"TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ;"
GCC,riscv,191,Some possible next statements could include:
GCC,riscv,192,return IDENTIFIER_POINTER ( id ) ;
GCC,riscv,193,
GCC,riscv,194,
GCC,riscv,195,return flags & ( CP_WRITE_MEMORY | CP_WRITE_CSR ) ;
GCC,riscv,196,return false;
GCC,riscv,197,if (flags & READ
GCC,riscv,198,
GCC,riscv,199,"lang_hooks.types.register_builtin_type(vectype, vector_types[type].abi_name);"
GCC,riscv,200,tree int32_type_node = get_typenode_from_name ( INT32_TYPE ) ;
GCC,riscv,201,"However, based on the syntax and the names of the classes and methods involved, it is likely that the `build` method is being called on an instance of the `Group` class, and that it is being passed an instance of the `Shape` class as an argument. The `build` method is then expected to"
GCC,riscv,202,1. `tree id = get_identifier(vector_types[type].name);`: This line retrieves the identifier for the vector type with the given `type`
GCC,riscv,203,
GCC,riscv,204,"error_at ( location , <STR_LIT> <STR_LIT> , argno + <NUM_LIT> , fndecl ) ;"
GCC,riscv,205,"error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , min , max ) ;"
GCC,riscv,206,return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index || type == RVV_BASE_float_vector || type == RVV_BASE_double_trunc_float_vector || type == RVV_BASE_double_trunc_vector || type == RVV_BASE_widen_l
GCC,riscv,207,if (tree_fits_uhwi_p(arg) && (min <= tree_to_uhwi(arg)) && (tree_to_uhwi(arg) <= max)) {
GCC,riscv,208,HOST_WIDE_INT value = tree_to_uhwi ( arg ) ;
GCC,riscv,209,return false;
GCC,riscv,210,
GCC,riscv,211,
GCC,riscv,212,#define TYPE_MODE(t) (t)->mode
GCC,riscv,213,this->base_type = base_type_in;
GCC,riscv,214,this->base_type = base_type_in;
GCC,riscv,215,Here are a few possibilities:
GCC,riscv,216,
GCC,riscv,217,
GCC,riscv,218,"add_mem_operand ( mode , use_real_mask_p ( pred ) ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,riscv,219,"1. `int arg_offset = <NUM_LIT> ;`: This line initializes a variable `arg_offset` to a specific value, which is likely to"
GCC,riscv,220,"add_input_operand(Pmode, get_tail_policy_for_pred(pred));"
GCC,riscv,221,
GCC,riscv,222,return pred == PRED_TYPE_mu;
GCC,riscv,223,"add_input_operand ( mode , vd ) ;"
GCC,riscv,224,"add_input_operand(mode, vs2);"
GCC,riscv,225,
GCC,riscv,226,
GCC,riscv,227,return TYPE_MODE (builtin_types[type.index].vector);
GCC,riscv,228,return;
GCC,riscv,229,
GCC,riscv,230,return;
GCC,riscv,231,"EXECUTE_IF_SET_IN_BITMAP ( bitdata , <NUM_LIT> , bb_index , sbi ) { if ( vector_exprs [ bb_index ] -> get_avl_info ( ) != avl ) return false ; }"
GCC,riscv,232,"EXECUTE_IF_SET_IN_BITMAP ( bitdata , <NUM_LIT> , bb_index , sbi ) {"
GCC,riscv,233,return false;
GCC,riscv,234,
GCC,riscv,235,
GCC,riscv,236,if (dest == NULL_RTX) {
GCC,riscv,237,
GCC,riscv,238,
GCC,riscv,239,m_value = NULL_RTX;
GCC,riscv,240,m_value = NULL_RTX;
GCC,riscv,241,
GCC,riscv,242,block_info.local_dem = block_info.reaching_out;
GCC,riscv,243,gcc_assert ( block_info . reaching_out . unknown_p ( ) ) ;
GCC,riscv,244,return insn1->compare_with(insn2) < <NUM_LIT>;
GCC,riscv,245,return LMUL_RESERVED;
GCC,riscv,246,
GCC,riscv,247,if ( !m_vector_manager->all_same_ratio_p(m_vector_manager->vector_avin[cfg_bb->index]) ) return false;
GCC,riscv,248,for (e = ei = cfg_bb->succ; ei != NULL; ei = ei->succ_next)
GCC,riscv,249,remove_reg_equal_equiv_notes(rinsn);
GCC,riscv,250,rinsn = insn->rtl();
GCC,riscv,251,Here is a breakdown of the code:
GCC,riscv,252,uses_builder.reserve(insn->num_uses() - <NUM_LIT
GCC,riscv,253,
GCC,riscv,254,
GCC,riscv,255,eliminate_insn(rinsn)
GCC,riscv,256,
GCC,riscv,257,case LMUL_F8 : return <NUM_LIT> ;
GCC,riscv,258,return true;
GCC,riscv,259,return false;
GCC,riscv,260,if ( m_sew == curr_info.get_sew() ) return true;
GCC,riscv,261,return compatible_avl_p(curr_info) && compatible_vtype_p(curr_info);
GCC,riscv,262,return true;
GCC,riscv,263,if ( change . valid_p ( ) ) {
GCC,riscv,264,if ( !optimize ) return;
GCC,riscv,265,for (const bb_info *bb : crtl->ssa->bbs()) {
GCC,riscv,266,
GCC,riscv,267,"bitmap_vector_clear (vector_antic, last_basic_block_for_fn (cfun));"
GCC,riscv,268,
GCC,riscv,269,
GCC,riscv,270,
GCC,riscv,271,
GCC,riscv,272,
GCC,riscv,273,
GCC,riscv,274,Here's a breakdown of the code:
GCC,riscv,275,return info1.get_ma() != info2.get_ma();
GCC,riscv,276,"static bool different_ratio_p ( const vector_insn_info & info1 , const vector_insn_info & info"
GCC,riscv,277,return info1.get_sew() != info2.get_sew();
GCC,riscv,278,
GCC,riscv,279,
GCC,riscv,280,
GCC,riscv,281,m_vector_manager->release();`
GCC,riscv,282,"return ( ( pair . match_cond_p ( info1 . get_demands ( ) , info2 . get_demands ( ) ) && incompatible_p ( info1 , info2 ) ) || ( pair . match_cond_p ( info2 . get_demands ( ) , info1 . get_demands ( ) ) && incompatible_p ( info2 , info1 ) ) ) ;"
GCC,riscv,283,"return ( ( pair . match_cond_p ( info1 . get_demands ( ) , info2 . get_demands ( ) ) && incompatible_p ( info1 , info2 ) ) || ( pair . match_cond_p ( info2 . get_demands ( ) , info1 . get_demands ( ) ) && incompatible_p ( info2 , info1 ) ) ) ;"
GCC,riscv,284,"fprintf ( file , <STR_LIT> ) ;"
GCC,riscv,285,
GCC,riscv,286,Based on the structure of
GCC,riscv,287,"emit_insn_after(pat, rinsn);"
GCC,riscv,288,
GCC,riscv,289,return m_state == EMPTY || m_state == HARD_EMPTY;
GCC,riscv,290,
GCC,riscv,291,
GCC,riscv,292,"hash_set<set_info*> sets = get_all_sets(set, true, false, true);"
GCC,riscv,293,return insn;
GCC,riscv,294,return nullptr;
GCC,riscv,295,return info1.get_ratio();
GCC,riscv,296,
GCC,riscv,297,
GCC,riscv,298,"Given that the `INSN_UID` method is being used to retrieve the UID of the instruction, it is possible that the `vector_insn_infos` method is returning a vector of instruction information objects,"
GCC,riscv,299,rinsn = PREV_INSN (insn->rtl());
GCC,riscv,300,
GCC,riscv,301,return;
GCC,riscv,302,set_avl_info(info2.get_avl_info());
GCC,riscv,303,set_avl_info(info1.get_avl_info());
GCC,riscv,304,
GCC,riscv,305,"set_demand(DEMAND_SEW, rule.demand_sew_p);"
GCC,riscv,306,
GCC,riscv,307,
GCC,riscv,308,return new_pat;
GCC,riscv,309,"new_pat = gen_vsetvl_pat ( VSETVL_NORMAL , new_info , dest ) ;"
GCC,riscv,310,available_list.push_back(some_value);
GCC,riscv,311,available_list.push_back(some_value);
GCC,riscv,312,e = ei.next();
GCC,riscv,313,basic_block bb = work_list.pop();
GCC,riscv,314,hash_set<set_info*> all_sets = new hash_set<set_info*>();
GCC,riscv,315,
GCC,riscv,316,
GCC,riscv,317,
GCC,riscv,318,
GCC,riscv,319,const insn_info * i = insn->prev_nondebug_insn();
GCC,riscv,320,if ( vlmax_avl_p ( prop . get_avl ( ) ) ) {
GCC,riscv,321,return (bool) (get_prefer_mask_policy() & <NUM_LIT> || (get_prefer_mask_policy() >> <NUM_LIT> & <NUM_LIT>));
GCC,riscv,322,
GCC,riscv,323,
GCC,riscv,324,
GCC,riscv,325,return <NUM_LIT>;
GCC,riscv,326,i = i->next_nondebug_insn()
GCC,riscv,327,
GCC,riscv,328,return vector_insn_info::get_hard_empty();
GCC,riscv,329,return vector_insn_info::get_hard_empty();
GCC,riscv,330,
GCC,riscv,331,return m_insn;
GCC,riscv,332,
GCC,riscv,333,
GCC,riscv,334,
GCC,riscv,335,
GCC,riscv,336,return set;
GCC,riscv,337,return m_sew;
GCC,riscv,338,return m_sew;
GCC,riscv,339,
GCC,riscv,340,bool has_ta = get_ta
GCC,riscv,341,
GCC,riscv,342,info.set_unknown();
GCC,riscv,343,return m_value;
GCC,riscv,344,
GCC,riscv,345,
GCC,riscv,346,
GCC,riscv,347,else set = nullptr ; }
GCC,riscv,348,return true;
GCC,riscv,349,
GCC,riscv,350,return true;
GCC,riscv,351,return info1.get_sew() < info2.get_sew();
GCC,riscv,352,
GCC,riscv,353,
GCC,riscv,354,
GCC,riscv,355,
GCC,riscv,356,
GCC,riscv,357,
GCC,riscv,358,
GCC,riscv,359,
GCC,riscv,360,
GCC,riscv,361,return true;
GCC,riscv,362,return get_attr_has_vl_op ( rinsn ) ;
GCC,riscv,363,
GCC,riscv,364,return false;
GCC,riscv,365,return get_attr_has_vtype_op ( rinsn ) ;
GCC,riscv,366,
GCC,riscv,367,return get_attr_type ( rinsn ) == TYPE_VIMOVVX || get_attr_type ( rinsn ) == TYPE_VFMOVVF || get_attr_type ( rinsn ) == TYPE_VIMOVXV || get_attr_type ( rinsn ) == TYPE_VFMOVFV;
GCC,riscv,368,
GCC,riscv,369,"fprintf(dump_file, <STR_LIT>);"
GCC,riscv,370,pat = NEXT_INSN ( pat ) ;
GCC,riscv,371,"new_insn = emit_insn_after_noloc ( pat , end_rinsn , cfg_bb ) ;"
GCC,riscv,372,return false;
GCC,riscv,373,return false;
GCC,riscv,374,for (const bb_info *bb : crtl->ssa->bbs()) compute_local_backward_infos(bb);
GCC,riscv,375,return true;
GCC,riscv,376,
GCC,riscv,377,
GCC,riscv,378,return new pass_vsetvl ( ctxt ) ;
GCC,riscv,379,return ma == INVALID_ATTRIBUTE ? get_default_ma ( ) : IS_AGNOSTIC ( ma ) ;
GCC,riscv,380,int mb = get_attr_mb ( rinsn ) ;
GCC,riscv,381,if (dems1[i] != dems2[i]) return false;
GCC,riscv,382,
GCC,riscv,383,
GCC,riscv,384,return false;
GCC,riscv,385,if ( ! m_avl . get_source ( ) -> insn ( ) -> is_real ( ) && ! m_avl . get_source ( ) -> insn ( ) -> is_phi ( ) ) return ;
GCC,riscv,386,m_demands[DEMAND_SEW] = true;
GCC,riscv,387,"pass_vsetvl ( ctxt ) : rtl_opt_pass ( pass_data_vsetvl , ctxt ) {"
GCC,riscv,388,"pass_vsetvl ( ctxt ) : rtl_opt_pass ( pass_data_vsetvl , ctxt ) {"
GCC,riscv,389,return !info1.has_non_zero_avl() || !info2.has_non_zero_avl();
GCC,riscv,390,
GCC,riscv,391,if ( vlmax_avl_p ( avl ) ) continue ;
GCC,riscv,392,return info1.demand_p(DEMAND_AVL) && !info1.demand_p(DEMAND_NONZERO_AVL) && info1.has_avl_reg();
GCC,riscv,393,"fprintf (dump_file, ""Local DEM: ""); m_vector_manager->print_expr (m_vector_manager->vector_block_infos[bb->index()].local_dem); fprintf (dump_file, ""Reaching out: ""); m_vector_manager->print_expr (m_vector_manager->vector_block_infos[bb->index()].reaching_out); fprintf (dump_file, ""\n"");"
GCC,riscv,394,
GCC,riscv,395,return recog_memoized ( rinsn ) >= <NUM_LIT> && get_attr_type ( rinsn ) == TYPE_RDVL;
GCC,riscv,396,return insn->bb == bb;
GCC,riscv,397,m_vector_manager->to_refine_vsetvls.add(rinsn);
GCC,riscv,398,rinsn = PREV_INSN ( rinsn ) ;
GCC,riscv,399,if (def_insn && def_insn->has_avl_reg() && !def_insn->get_avl_source()) return false;
GCC,riscv,400,
GCC,riscv,401,return;
GCC,riscv,402,return get_avl() == other.get_avl() && get_avl_source() == other.get_avl_source();
GCC,riscv,403,return dems1[DEMAND_SEW] == dems2[DEMAND_SEW] && dems1[DEMAND_LMUL] == dems2[DEMAND_LMUL] && dems1[DEMAND_RATIO] == dems2[DEMAND_RATIO] && !dems1[DEMAND_GE_SEW] && !dems2[DEMAND_GE_SEW];
GCC,riscv,404,
GCC,riscv,405,return get_sew() == other.get_sew() && get_vlmul() == other.get_vlmul() && get_ta() == other.get_ta() && get_ma() == other.get_ma();
GCC,riscv,406,
GCC,riscv,407,Here's a breakdown of the code:
GCC,riscv,408,"However, based on the function name and the types of the parameters, it can be inferred that the function is likely to be comparing the values of the `lmul` fields of the `vector_insn_info` structures pointed to by `info1` and `info2"
GCC,riscv,409,
GCC,riscv,410,
GCC,riscv,411,"return calculate_sew(info1.get_vlmul(), info2.get_ratio()) == <NUM_LIT>;"
GCC,riscv,412,
GCC,riscv,413,return info2.get_ratio() < info1.get_ratio();
GCC,riscv,414,
GCC,riscv,415,
GCC,riscv,416,return info2.vlmul;
GCC,riscv,417,
GCC,riscv,418,m_avl = avl;
GCC,riscv,419,m_demands[type] = value;
GCC,riscv,420,
GCC,riscv,421,
GCC,riscv,422,
GCC,riscv,423,m_state = HARD_EMPTY;
GCC,riscv,424,
GCC,riscv,425,
GCC,riscv,426,
GCC,riscv,427,
GCC,riscv,428,ma.set_ma(ma);
GCC,riscv,429,
GCC,riscv,430,m_ratio = ratio;
GCC,riscv,431,
GCC,riscv,432,
GCC,riscv,433,
GCC,riscv,434,m_state = VALID;
GCC,riscv,435,
GCC,riscv,436,"emit_vsetvl_insn ( VSETVL_DISCARD_RESULT , EMIT_BEFORE , info , NULL_RTX , rinsn ) ;"
GCC,riscv,437,"emit_vsetvl_insn(VSETVL_DISCARD_RESULT, EMIT_BEFORE, info, NULL_RTX, rinsn);"
GCC,riscv,438,if (insn1->type != insn2->type) return false;
GCC,riscv,439,if (insn1_info.same_vlmax_p(insn2_info) && insn1_info.compatible_avl_p(insn2_info)) return true;
GCC,riscv,440,
GCC,riscv,441,return ta == INVALID_ATTRIBUTE ? get_default_ta() : IS_AGNOSTIC(ta);
GCC,riscv,442,return ta == INVALID_ATTRIBUTE ? get_default_ta() : IS_AGNOSTIC(ta);
GCC,riscv,443,
GCC,riscv,444,
GCC,riscv,445,info = require;
GCC,riscv,446,
GCC,riscv,447,
GCC,riscv,448,if (m_state == UNINITIALIZED) {
GCC,riscv,449,
GCC,riscv,450,
GCC,riscv,451,
GCC,riscv,452,
GCC,riscv,453,return exact_log2 ( sew ) && sew >= <NUM_LIT> && sew <= <NUM_LIT> ;
GCC,riscv,454,
GCC,riscv,455,if (GET_CODE (rinsn) == VECTOR_CONFIG)
GCC,riscv,456,if (GET_CODE (rinsn) == VECTOR_CONFIG)
GCC,riscv,457,for (insn_info *insn : bb->real_insns()) {
GCC,riscv,458,
GCC,riscv,459,
GCC,riscv,460,
GCC,riscv,461,
GCC,riscv,462,If `x` is non-zero and the `rt
GCC,riscv,463,
GCC,riscv,464,m_avl = avl_info();
GCC,riscv,465,m_avl = avl_info();
GCC,riscv,466,return false;
GCC,riscv,467,return false;
GCC,riscv,468,return ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvldi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvlsi ) ;
GCC,riscv,469,"add_input_operand ( CONSTM1_RTX ( mode ) , mode ) ;"
GCC,riscv,470,
GCC,riscv,471,
GCC,riscv,472,"rtx tail_policy_rtx = gen_int_mode ( vta , Pmode ) ;"
GCC,riscv,473,
GCC,riscv,474,
GCC,riscv,475,"add_input_operand ( RVV_VUNDEF ( mode ) , mode ) ;"
GCC,riscv,476,
GCC,riscv,477,
GCC,riscv,478,
GCC,riscv,479,
GCC,riscv,480,"emit_insn ( gen_vsetvl ( Pmode , vl , RVV_VLMAX , gen_int_mode ( sew , Pmode ) , gen_int_mode ( get_vlmul ( vmode ) , Pmode ) , const0_rtx , const0_rtx ) ) ;"
GCC,riscv,481,"emit_pred_op ( icode , NULL_RTX , dest , src , len , mask_mode , false ) ;"
GCC,riscv,482,
GCC,riscv,483,
GCC,riscv,484,
GCC,riscv,485,"emit_pred_op ( icode , NULL_RTX , dest , src , len , mask_mode , true ) ;"
GCC,riscv,486,
GCC,riscv,487,"emit_insn ( gen_vlmax_avl ( Pmode , vl , gen_int_mode ( ratio , Pmode ) ) ) ;"
GCC,riscv,488,
GCC,riscv,489,"expand_insn ( icode , m_opno , m_ops ) ;"
GCC,riscv,490,rtx elt;
GCC,riscv,491,"emit_vlmax_op(code_for_pred_mov(mode), target, src, mask_mode);"
GCC,riscv,492,
GCC,riscv,493,
GCC,riscv,494,unsigned int lmul = get_lmul ( vmode ) ;
GCC,riscv,495,
GCC,riscv,496,
GCC,riscv,497,
GCC,riscv,498,
GCC,riscv,499,
GCC,riscv,500,
GCC,riscv,501,
GCC,riscv,502,return TAIL_ANY;
GCC,riscv,503,return mode_vtype_infos.ratio_for_min_vlen64[mode];
GCC,riscv,504,return mode_vtype_infos.ratio_for_min_vlen64[mode];
GCC,riscv,505,For example
GCC,riscv,506,sew = GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? <NUM_LIT> : GET_MODE_BITSIZE ( GET_MODE_INNER ( mode ) ) ;
GCC,riscv,507,return INVALID_ATTRIBUTE;
GCC,riscv,508,
GCC,riscv,509,default :
GCC,riscv,510,mode = GET_MODE_INNER ( mode );
GCC,riscv,511,return mode_vtype_infos.vlmul_for_min_vlen64[mode];
GCC,riscv,512,i32vl = gen_reg_rtx ( Pmode ) ;
GCC,riscv,513,i32vl = gen_reg_rtx (Pmode);
GCC,riscv,514,
GCC,riscv,515,
GCC,riscv,516,
GCC,riscv,517,rtx tmp = gen_reg_rtx ( mode ) ;
GCC,riscv,518,"emit_vlmax_op ( code_for_pred_mov ( mode ) , dest , src , mask_mode ) ;"
GCC,riscv,519,vlmul_for_min_vlen64[MODE##mode] = VLMUL_FOR_MIN_VLEN64;
GCC,riscv,520,return (INTVAL ( x ) < 0 && INTVAL ( x ) >= -32);
GCC,riscv,521,"return IN_RANGE ( INTVAL ( x ) , - <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,522,
GCC,riscv,523,"return IN_RANGE ( INTVAL ( x ) , - <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,524,"return IN_RANGE ( INTVAL ( x ) , - <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,525,
GCC,riscv,526,"merge = gen_lowpart ( demote_mode , ops [ <NUM_LIT> ] ) ;"
GCC,riscv,527,
GCC,riscv,528,n += (GET_MODE_SIZE(mode).to_constant() + UNITS_PER_WORD - <NUM_LIT>) / UNITS_PER_WORD;
GCC,riscv,529,
GCC,riscv,530,"dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ;"
GCC,riscv,531,
GCC,riscv,532,return COSTS_N_INSNS(double_insns);
GCC,riscv,533,return COSTS_N_INSNS ( double_insns ) ;
GCC,riscv,534,final_src = src + (length - 1) * bytes_per_iter;
GCC,riscv,535,
GCC,riscv,536,shifted_val = value << shift;
GCC,riscv,537,int upper_trailing_ones = ctz_hwi(~value >> <NUM_LIT>);
GCC,riscv,538,if ( GET_CODE ( *iter ) == CONST_POLY_INT ) return true ;
GCC,riscv,539,
GCC,riscv,540,case MULT:
GCC,riscv,541,case CONST_INT: if (riscv_v_ext_vector_mode_p(mode)) return false;
GCC,riscv,542,"return riscv_hard_regno_nregs(GP_REG_FIRST, mode);"
GCC,riscv,543,
GCC,riscv,544,
GCC,riscv,545,"frame -> mask |= <NUM_LIT> << ( regno - GP_REG_FIRST ) , num_x_saved ++ ;"
GCC,riscv,546,if ( UNITS_PER_FP_ARG == <NUM_LIT> ) { for ( int regno = FP_REG_FIRST ; regno <= FP_REG_LAST ; regno ++ ) call_used_regs [ regno ] = <NUM_LIT> ; }
GCC,riscv,547,for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) {
GCC,riscv,548,riscv_bytes_per_vector_chunk = TARGET_MIN_VLEN;
GCC,riscv,549,Here are some possible next statements:
GCC,riscv,550,Here are some possible next statements:
GCC,riscv,551,"return get_section(name, s->named.common.flags, NULL);"
GCC,riscv,552,if (s == NULL) {
GCC,riscv,553,"riscv_process_components(components, false);"
GCC,riscv,554,"* op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ;"
GCC,riscv,555,"* op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ;"
GCC,riscv,556,"rtx inv_target = riscv_force_binary ( word_mode , inv_code , cmp0 , cmp1 ) ;"
GCC,riscv,557,"riscv_process_components(components, true);"
GCC,riscv,558,
GCC,riscv,559,case EXCESS_PRECISION_TYPE_FLOAT16 :
GCC,riscv,560,case EXCESS_PRECISION_TYPE_IMPLICIT :
GCC,riscv,561,"riscv_emit_int_compare (&code, &op0, &op1);"
GCC,riscv,562,
GCC,riscv,563,"rtx cond = gen_rtx_fmt_ee ( code , mode , op0 , op1 ) ;"
GCC,riscv,564,if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = riscv_first_stack_step ( frame ) ; step1 -= step2 ; }
GCC,riscv,565,rtx dwarf = NULL_RTX;
GCC,riscv,566,
GCC,riscv,567,"pat = gen_rtx_fmt_e ( code , mode , op1 ) ;"
GCC,riscv,568,"emit_insn (gen_rtx_SET (op0, pat));"
GCC,riscv,569,frame->mask = mask;
GCC,riscv,570,if ( SMALL_OPERAND ( - constant_frame ) ) {
GCC,riscv,571,"* op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ;"
GCC,riscv,572,
GCC,riscv,573,if ( TARGET_RVC ) {
GCC,riscv,574,if ( TARGET_RVC ) {
GCC,riscv,575,"n = riscv_flatten_aggregate_field ( TREE_TYPE ( f ) , fields , n , pos , ignore_zero_width_bit_field_p ) ;"
GCC,riscv,576,"th_mempair_save_restore_regs(operands, load_p, word_mode);"
GCC,riscv,577,"riscv_save_restore_reg(mode, regno, offset, fn);"
GCC,riscv,578,info->num_gprs = <NUM_LIT>;
GCC,riscv,579,"bitmap_set_bit ( components, offset ) ;"
GCC,riscv,580,return components;
GCC,riscv,581,if ( ! TARGET_64BIT && TARGET_ZDINX ) {
GCC,riscv,582,if ( lmul != <NUM_LIT> ) return ( ( regno % lmul ) == <NUM_LIT> ) ;
GCC,riscv,583,if ( regno == VTYPE_REGNUM || regno == VL_REGNUM ) return <NUM_LIT> ;
GCC,riscv,584,
GCC,riscv,585,src = cfun -> machine -> frame . frame_pointer_offset;
GCC,riscv,586,"set_optab_libfunc(gt_optab, HFmode, NULL);"
GCC,riscv,587,
GCC,riscv,588,"if ( MEM_P ( dest ) && ! riscv_legitimate_address_p ( mode , XEXP ( dest , <NUM_LIT> ) , reload_completed ) ) { XEXP ( dest , <NUM_LIT> ) = riscv_force_address ( XEXP ( dest , <NUM_LIT> ) , mode ) ; }"
GCC,riscv,589,if ( GET_CODE ( src ) == CONST_INT ) {
GCC,riscv,590,"if ( div_factor != <NUM_LIT> ) riscv_expand_op ( LSHIFTRT , mode , tmp , tmp , gen_int_mode ( exact_log2 ( div_factor ) , QImode ) ) ;"
GCC,riscv,591,"if ( div_factor != <NUM_LIT> ) riscv_expand_op ( LSHIFTRT , mode , tmp , tmp , gen_int_mode ( exact_log2 ( div_factor ) , QImode ) ) ;"
GCC,riscv,592,if (might_split_p) { ... }
GCC,riscv,593,const char * res = TYPE_NAME ( type ) ;
GCC,riscv,594,return <STR_LIT>;
GCC,riscv,595,"codes[i].value = trunc_int_for_mode(codes[i].value, mode);"
GCC,riscv,596,x = GEN_INT(codes[<NUM_LIT>].value);
GCC,riscv,597,"Inside the loop, the function checks if the bit at position `regno - GP_REG_FIRST` in the bitset `cf"
GCC,riscv,598,if ( src_code == MEM ) switch ( width ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } }
GCC,riscv,599,return false;
GCC,riscv,600,"asm_fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ;"
GCC,riscv,601,offset += UNITS
GCC,riscv,602,unsignedp = * punsignedp;
GCC,riscv,603,"PROMOTE_MODE ( as_a < scalar_mode > ( mode ) , unsignedp , type ) ;"
GCC,riscv,604,return BYTES_PER_RISCV_VECTOR;
GCC,riscv,605,return BYTES_PER_RISCV_VECTOR;
GCC,riscv,606,
GCC,riscv,607,
GCC,riscv,608,"inform ( input_location , ""Hello"", ""World"", ""!"" )"
GCC,riscv,609,
GCC,riscv,610,return default_scalar_mode_supported_p ( mode );
GCC,riscv,611,
GCC,riscv,612,return ( ! riscv_v_ext_vector_mode_p ( mode ) && GET_MODE_SIZE ( mode ) . to_constant ( ) > UNITS_PER_WORD && ( class1 == FP_REGS ) != ( class2 == FP_REGS ) && ! TARGET_XTHEADFMV ) ;
GCC,riscv,613,gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
GCC,riscv,614,gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
GCC,riscv,615,for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) {
GCC,riscv,616,for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) {
GCC,riscv,617,
GCC,riscv,618,return shamt == ctz_hwi ( mask );
GCC,riscv,619,return (shamt & mask) == mask;
GCC,riscv,620,"emit_insn (gen_th_fmv_x_w (low_dest, src));"
GCC,riscv,621,"emit_insn (gen_th_fmv_x_w (low_dest, src));"
GCC,riscv,622,align = GET_MODE_ALIGNMENT(mode);
GCC,riscv,623,if (align < size) return false;
GCC,riscv,624,if (GET_MODE_SIZE(mode).to_constant() > UNITS_PER_WORD && !SMALL_OPERAND(INTVAL(x) + GET_MODE_SIZE(mode).to_constant() - UNITS_PER_WORD)) return false;
GCC,riscv,625,
GCC,riscv,626,
GCC,riscv,627,min_size = constant_lower_bound ( wi :: to_poly_widest ( TYPE_SIZE ( type ) ) ) ;
GCC,riscv,628,return riscv_v_ext_vector_mode_p ( mode ) ;
GCC,riscv,629,return mode_size;
GCC,riscv,630,return mode_size;
GCC,riscv,631,return riscv_vector_chunks * scale;
GCC,riscv,632,return riscv_vector_chunks * scale;
GCC,riscv,633,
GCC,riscv,634,insn = emit_insn (insn);
GCC,riscv,635,RTX_FRAME_RELATED_P (insn) = <NUM_LIT>;
GCC,riscv,636,
GCC,riscv,637,
GCC,riscv,638,zeroed_hardregs = need_zeroed_hardregs;
GCC,riscv,639,zeroed_hardregs |= default_zero_call_used_regs ( need_zeroed_hardregs & ~ zeroed_hardregs ) ;
GCC,riscv,640,rtx target = regno_reg_rtx [ regno ] ;
GCC,riscv,641,if (emitted_vlmax_vsetvl) {
GCC,riscv,642,int cost = 0;
GCC,riscv,643,n += ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;
GCC,riscv,644,
GCC,riscv,645,"However, based on the names of the variables and the function being called, it is likely that the next statement will involve the creation of a new temporary variable or the modification of an existing one. The `riscv_force_temporary` function is likely to be used to create a new temporary variable or to modify an existing one, and the `"
GCC,riscv,646,"dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ;"
GCC,riscv,647,"adjust_sp_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (saved_size));"
GCC,riscv,648,"mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack"
GCC,riscv,649,
GCC,riscv,650,
GCC,riscv,651,shifted_val = value << shift;
GCC,riscv,652,cost = alt_cost;
GCC,riscv,653,if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ;
GCC,riscv,654,
GCC,riscv,655,if (INTVAL(*cmp1) < plus_one) {
GCC,riscv,656,return (reload_completed && cfun
GCC,riscv,657,info -> type = ADDRESS_REG ;
GCC,riscv,658,info -> offset = const0_rtx ;
GCC,riscv,659,"return riscv_hard_regno_nregs(GP_REG_FIRST, mode);"
GCC,riscv,660,offset += RISCV_STACK_ALIGN ( cfun->machine->varargs_size ) ;
GCC,riscv,661,"reg_names[16] = ""ft0"";"
GCC,riscv,662,"return get_section(name, s->named.common.flags, NULL);"
GCC,riscv,663,* code = EQ ;
GCC,riscv,664,*invert_ptr = !*invert_ptr;
GCC,riscv,665,if ( use_restore_libcall ) frame -> mask = <NUM_LIT> ;
GCC,riscv,666,if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) {
GCC,riscv,667,RTX_FRAME_RELATED_P (emit_insn (insn)) = <NUM_LIT>;
GCC,riscv,668,"* op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ;"
GCC,riscv,669,"* op1 = gen_rtx_SIGN_EXTEND ( word_mode , * op1 ) ;"
GCC,riscv,670,
GCC,riscv,671,default_file_start ( );
GCC,riscv,672,return frame->total_size % IMM_REACH;
GCC,riscv,673,
GCC,riscv,674,"return riscv_flatten_aggregate_field ( type , fields , <NUM_LIT> , <NUM_LIT> ) ;"
GCC,riscv,675,gcc_assert ( n_elts >= <NUM_LIT> ) ;
GCC,riscv,676,fields[n].type = TREE_TYPE(type);
GCC,riscv,677,return x;
GCC,riscv,678,rtx_code(mode
GCC,riscv,679,"riscv_emit_move(dest, value);"
GCC,riscv,680,"riscv_emit_move ( dest , value ) ;"
GCC,riscv,681,offset -= UNITS_PER_WORD;
GCC,riscv,682,
GCC,riscv,683,"return riscv_get_arg_info ( & info , cum , mode , type , named , false ) ;"
GCC,riscv,684,return alignment;
GCC,riscv,685,return true;
GCC,riscv,686,return args;
GCC,riscv,687,"rtx riscv_function_value ( const_tree type , const_tree func , enum machine_mode mode ) { struct riscv_arg_info info ; CUMULATIVE_ARGS args ; if ( type ) { int unsigned_p = TYPE_UNSIGNED ( type ) ; mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , <NUM_LIT> ) ;"
GCC,riscv,688,
GCC,riscv,689,if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS
GCC,riscv,690,if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ;
GCC,riscv,691,if (GP_REG_P(regno + nregs - <NUM_LIT>)) return false;
GCC,riscv,692,return (GET_MODE_SIZE(mode) + UNITS_PER_FP_REG - <NUM_LIT>) / UNITS_PER_FP_REG;
GCC,riscv,693,
GCC,riscv,694,
GCC,riscv,695,
GCC,riscv,696,"if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) != <NUM_LIT> ) {"
GCC,riscv,697,"riscv_emit_move(dest, riscv_legitimize_tls_address(src));"
GCC,riscv,698,"riscv_emit_move(dest, force_reg(mode, src));"
GCC,riscv,699,"riscv_emit_move ( dest , force_reg ( mode , src ) ) ;"
GCC,riscv,700,if (might_split_p) {
GCC,riscv,701,"return riscv_address_insns(XEXP(mem, <NUM_LIT>), mode, might_split_p);"
GCC,riscv,702,
GCC,riscv,703,x = GEN_INT(codes[<NUM_LIT>].value);
GCC,riscv,704,"x = riscv_emit_set(temp, x);"
GCC,riscv,705,
GCC,riscv,706,
GCC,riscv,707,
GCC,riscv,708,"error ( <STR_LIT> , cpu_string ) ;"
GCC,riscv,709,return NULL;
GCC,riscv,710,num_float += SCALAR_FLOAT_TYPE_P ( fields [ i ] . type );
GCC,riscv,711,
GCC,riscv,712,return info;
GCC,riscv,713,info.cumulative_args = cum;
GCC,riscv,714,"return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode1 , regno1 ) , GEN_INT ( offset1 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) ) ;"
GCC,riscv,715,"static rtx riscv_pass_fpr_pair ( enum machine_mode mode , unsigned regno1 , enum machine_mode mode1 , HOST_WIDE_INT offset1 , unsigned regno2 , enum machine_mode mode2 , HOST_WIDE_INT offset2 ) {"
GCC,riscv,716,"return riscv_gen_reg_rtx (type_mode, regno, value_mode);"
GCC,riscv,717,
GCC,riscv,718,"fprintf ( file , <STR_LIT> , reg_names [ REGNO ( op ) ] ) ;"
GCC,riscv,719,"if (letter && letter != 'z') output_operand_lossage(<STR_LIT>, letter);"
GCC,riscv,720,
GCC,riscv,721,return regno;
GCC,riscv,722,"For example, if the `reg_renumber` function is defined"
GCC,riscv,723,RTX_FRAME_RELATED_P (insn) = 1;
GCC,riscv,724,#include <stdio.h>
GCC,riscv,725,return false;
GCC,riscv,726,return false;
GCC,riscv,727,"fn (mem, regno);"
GCC,riscv,728,"rtx mem = gen_frame_mem ( BLKmode , ptr ) ;"
GCC,riscv,729,"label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ;"
GCC,riscv,730,
GCC,riscv,731,"return adjust_address ( op , word_mode , byte ) ;"
GCC,riscv,732,
GCC,riscv,733,"rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) {"
GCC,riscv,734,
GCC,riscv,735,return false;
GCC,riscv,736,n += (GET_MODE_SIZE(mode) + UNITS_PER_WORD - <NUM_LIT>) / UNITS_PER_WORD;
GCC,riscv,737,return arg.stack_p ? arg.num_gprs * UNITS_PER_WORD : <NUM_LIT>;
GCC,riscv,738,
GCC,riscv,739,
GCC,riscv,740,case MULT:
GCC,riscv,741,
GCC,riscv,742,offset += RISCV_STACK_ALIGN ( cfun -> machine -> varargs_size ) ;
GCC,riscv,743,call_used_regs[regno] = <NUM_LIT>;
GCC,riscv,744,return align;
GCC,riscv,745,"insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (step2)));"
GCC,riscv,746,if ( size > <NUM_LIT> ) {
GCC,riscv,747,
GCC,riscv,748,default_file_start ( );
GCC,riscv,749,offset = cfun -> machine -> frame . fp_sp_offset - sp_offset;
GCC,riscv,750,
GCC,riscv,751,
GCC,riscv,752,"However, based on the names of the functions and variables, it is likely that the next statement will involve using the information stored in the `info` structure to perform some operation related to the arguments of a function. The `riscv_get_arg_info` function"
GCC,riscv,753,return true;
GCC,riscv,754,return true;
GCC,riscv,755,
GCC,riscv,756,if ( FP_REG_P ( regno ) ) {
GCC,riscv,757,addr = x;
GCC,riscv,758,"riscv_emit_move(dest, riscv_legitimize_tls_address(src));"
GCC,riscv,759,"riscv_emit_move (dest, src)"
GCC,riscv,760,return true;
GCC,riscv,761,"if (MEM_P(dest) && !riscv_legitimate_address_p(mode, XEXP(dest, <NUM_LIT>), reload_completed)) {"
GCC,riscv,762,x = GEN_INT(codes[<NUM_LIT>].value);
GCC,riscv,763,"x = gen_rtx_fmt_ee ( codes [ i ] . code , mode , x , GEN_INT ( codes [ i ] . value ) ) ;"
GCC,riscv,764,if ( riscv_preferred_stack_boundary_arg ) {
GCC,riscv,765,if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) {
GCC,riscv,766,"if ( src_code == REG && FP_REG_P ( REGNO ( src ) ) ) return dbl_p ? ""fmov.d"" : ""fmov.s"";"
GCC,riscv,767,"return !IN_RANGE(size, <NUM_LIT>, <NUM_LIT> * UNITS_PER_WORD);"
GCC,riscv,768,
GCC,riscv,769,if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == <NUM_LIT> ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ;
GCC,riscv,770,
GCC,riscv,771,
GCC,riscv,772,
GCC,riscv,773,"riscv_move_integer(lo, lo, loval);"
GCC,riscv,774,if ( low_out ) switch ( symbol_type ) {
GCC,riscv,775,
GCC,riscv,776,n += (GET_MODE_SIZE(mode) + UNITS_PER_WORD - <NUM_LIT>) / UNITS_PER_WORD;
GCC,riscv,777,return false;
GCC,riscv,778,return call_saved || might_clobber;
GCC,riscv,779,if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = <NUM_LIT> ;
GCC,riscv,780,"return riscv_address_insns ( addr , mode , false ) + <NUM_LIT> ;"
GCC,riscv,781,n += (GET_MODE_SIZE (mode) + UNITS_PER_WORD - <NUM_LIT>) / UNITS_PER_WORD;
GCC,riscv,782,
GCC,riscv,783,
GCC,riscv,784,
GCC,riscv,785,"reg = gen_rtx_REG ( SImode , regno ) ;"
GCC,riscv,786,"dwarf = alloc_reg_note ( REG_CFA_RESTORE, reg, dwarf );"
GCC,riscv,787,2
GCC,riscv,788,"adjust_sp_rtx = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - saved_size ) ) ;"
GCC,riscv,789,
GCC,riscv,790,return !riscv_naked_function_p(current_function_decl);
GCC,riscv,791,return arg.stack_p ? arg.num_gprs * UNITS_PER_WORD : <NUM_LIT>;
GCC,riscv,792,return TARGET_64BIT ? ( HOST_WIDE_INT_1 << <NUM_LIT> ) : <NUM_LIT> ;
GCC,riscv,793,
GCC,riscv,794,return COSTS_N_INSNS ( single_insns );
GCC,riscv,795,
GCC,riscv,796,regs[i] = gen_reg_rtx(mode);
GCC,riscv,797,"src = adjust_address ( src , BLKmode , offset ) ;"
GCC,riscv,798,cost = alt_cost;
GCC,riscv,799,codes[cost - <NUM_LIT>].code = PLUS;
GCC,riscv,800,end_sequence ( ) ;
GCC,riscv,801,insn = get_insns();
GCC,riscv,802,return recog_memoized ( insn ) >= <NUM_LIT> && get_attr_cannot_copy ( insn ) ;
GCC,riscv,803,if ( SMALL_OPERAND ( INTVAL ( offset ) ) && riscv_symbol_insns ( type ) > <NUM_LIT> ) return true ;
GCC,riscv,804,
GCC,riscv,805,Sure! Here's the predicted next statement:
GCC,riscv,806,Here are a few possibilities:
GCC,riscv,807,"return ! reg_classes_intersect_p ( FP_REGS , rclass ) ;"
GCC,riscv,808,return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
GCC,riscv,809,
GCC,riscv,810,static enum riscv_symbol_type riscv_classify_symbol ( const_rtx x ) {
GCC,riscv,811,
GCC,riscv,812,
GCC,riscv,813,"return riscv_class_max_nregs_1 (rclass, mode);"
GCC,riscv,814,return result;
GCC,riscv,815,"return ( CONST_INT_P ( x ) && ( INTVAL ( x ) & <NUM_LIT> ) == <NUM_LIT> && IN_RANGE ( INTVAL ( x ) , <NUM_LIT> , CSW_MAX_OFFSET ) ) ;"
GCC,riscv,816,
GCC,riscv,817,offset = RISCV_STACK_ALIGN ( crtl -> outgoing_args_size ) ;
GCC,riscv,818,fixed_regs[regno] = call_used_regs[regno] = <NUM_LIT>;
GCC,riscv,819,return x == CONST0_RTX ( GET_MODE ( x ) ) ? <NUM_LIT> : <NUM_LIT> ;
GCC,riscv,820,"return get_section(name, s->named.common.flags, NULL);"
GCC,riscv,821,"strcpy (name, s->named.name);"
GCC,riscv,822,"fprintf(asm_out_file, <STR_LIT>, TARGET_STRICT_ALIGN ? <NUM_LIT> : <NUM_LIT>);"
GCC,riscv,823,case NE : fp_code = EQ ; * code = EQ ;
GCC,riscv,824,"cmp1 = force_reg (mode, cmp1);"
GCC,riscv,825,"return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ;"
GCC,riscv,826,"return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ;"
GCC,riscv,827,
GCC,riscv,828,"emit_insn ( gen_stack_tiesi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ;"
GCC,riscv,829,return true;
GCC,riscv,830,if ( df_regs_ever_live_p ( regno ) || ( ! crtl -> is_leaf && call_used_or_fixed_reg_p ( regno ) ) ) return true ;
GCC,riscv,831,
GCC,riscv,832,"rtx condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);"
GCC,riscv,833,
GCC,riscv,834,rtx dwarf = NULL_RTX;
GCC,riscv,835,"riscv_emit_float_compare (&code, &op0, &op1);"
GCC,riscv,836,"riscv_emit_set(target, lowpart_subreg(SImode, cmp, word_mode));"
GCC,riscv,837,"riscv_emit_binary ( code , target , zie , const0_rtx ) ;"
GCC,riscv,838,"rtx zie = riscv_zero_if_equal ( op0 , op1 ) ;"
GCC,riscv,839,frame->mask = mask;
GCC,riscv,840,"insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ;"
GCC,riscv,841,"* op0 = gen_rtx_ZERO_EXTEND ( word_mode , * op0 ) ;"
GCC,riscv,842,
GCC,riscv,843,if ( ! unsigned_p && GET_MODE ( op ) == SImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ;
GCC,riscv,844,if ( TARGET_ZBB ) { if ( ! unsigned_p && GET_MODE ( op ) == QImode ) return COSTS_N_INSNS ( <NUM_LIT> ) ;
GCC,riscv,845,"fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ;"
GCC,riscv,846,if ( TARGET_RVC ) { ... }
GCC,riscv,847,return - <NUM_LIT>;
GCC,riscv,848,int num_fields = 0;
GCC,riscv,849,return n;
GCC,riscv,850,return x;
GCC,riscv,851,"rtx result = gen_rtx_fmt_ee (code, mode, x, y);"
GCC,riscv,852,
GCC,riscv,853,offset = cfun->machine->frame.fp_sp_offset - sp_offset;
GCC,riscv,854,
GCC,riscv,855,"return riscv_get_arg_info(&info, cum, arg.mode, arg.type, arg.named, false);"
GCC,riscv,856,info.type = arg.type;
GCC,riscv,857,Here is an example of how the code might continue:
GCC,riscv,858,
GCC,riscv,859,return alignment;
GCC,riscv,860,return true;
GCC,riscv,861,"memset(&args, 0, sizeof(args));"
GCC,riscv,862,"return gen_rtx_REG ( mode , fregno ) ;"
GCC,riscv,863,info->num_fprs = riscv_pass_mode_in_fpr_p (mode);
GCC,riscv,864,if ( attr_args && TREE_CODE ( TREE_VALUE ( attr_args ) ) != VOID_TYPE )
GCC,riscv,865,return UNKNOWN_MODE;
GCC,riscv,866,
GCC,riscv,867,"return gen_got_load_tls_gddi ( dest , sym ) ;"
GCC,riscv,868,"return gen_got_load_tls_iedi ( dest , sym ) ;"
GCC,riscv,869,"return gen_got_load_tls_iedi ( dest , sym ) ;"
GCC,riscv,870,if (GET_CODE (elt) != REG || !REG_P (elt) || !REG_SAVE_P (elt)) return false;
GCC,riscv,871,return (GET_MODE_SIZE(mode) + UNITS_PER_FP_REG - <NUM_LIT>) / UNITS_PER_FP_REG;
GCC,riscv,872,return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - <NUM_LIT>) / UNITS_PER_WORD;
GCC,riscv,873,case GT: case GTU: return SMALL_OPERAND(x) && x != <NUM_LIT>;
GCC,riscv,874,dest = <NUM_LIT>;
GCC,riscv,875,
GCC,riscv,876,"return MIN ( riscv_build_integer ( codes , val , VOIDmode ) , riscv_split_integer_cost ( val ) ) ;"
GCC,riscv,877,
GCC,riscv,878,return TREE_CODE (type) == INTERRUPT_TYPE;
GCC,riscv,879,
GCC,riscv,880,
GCC,riscv,881,"return strcmp(sec, ""<STR_LIT>"") == <NUM_LIT> || strcmp(sec, ""<STR_LIT>"") == <NUM_LIT>;"
GCC,riscv,882,return riscv_size_ok_for_small_data_p ( int_size_in_bytes ( TREE_TYPE ( x ) ) ) ;
GCC,riscv,883,
GCC,riscv,884,
GCC,riscv,885,
GCC,riscv,886,return riscv_const_insns ( x ) > <NUM_LIT>;
GCC,riscv,887,
GCC,riscv,888,"addr = riscv_add_offset ( NULL , base , offset ) ;"
GCC,riscv,889,
GCC,riscv,890,return false;
GCC,riscv,891,"riscv_emit_move(dest, riscv_add_offset(NULL, base, INTVAL(offset)));"
GCC,riscv,892,"emit_insn ( gen_add3_insn ( dest , tmp , tp ) ) ;"
GCC,riscv,893,
GCC,riscv,894,if ( GET_MODE_BITSIZE ( mode ) <= <NUM_LIT> ) might_split_p = false ;
GCC,riscv,895,If
GCC,riscv,896,
GCC,riscv,897,
GCC,riscv,898,case MEMMODEL_ACQUIRE:
GCC,riscv,899,"return ( tune_param -> memory_cost + memory_move_secondary_cost ( mode , rclass , in ) ) ;"
GCC,riscv,900,"combined_attrs = merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES ( newdecl ) ) ;"
GCC,riscv,901,"combined_attrs = merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES ( newdecl ) ) ;"
GCC,riscv,902,return ( mode1 == mode2 || ! ( GET_MODE_CLASS ( mode1 ) == MODE_FLOAT && GET_MODE_CLASS ( mode2 ) == MODE_FLOAT ) ) ;
GCC,riscv,903,"In RISC-V, a mode is considered tieable if it can be represented by a single register. For example, a 32-bit integer mode is tieable because it can be represented by a single 32-bit register. On"
GCC,riscv,904,x = GEN_INT(codes[<NUM_LIT>].value);
GCC,riscv,905,return true;
GCC,riscv,906,if (old_cost > new_cost) {
GCC,riscv,907,if (speed) {
GCC,riscv,908,const char * str = riscv_stack_protector_guard_reg_str;
GCC,riscv,909,
GCC,riscv,910,
GCC,riscv,911,"emit_insn ( gen_movsi ( temp1, fnaddr ) ) ;"
GCC,riscv,912,
GCC,riscv,913,if ( dest_code == REG ) {
GCC,riscv,914,return <STR_LIT>;
GCC,riscv,915,
GCC,riscv,916,return &riscv_tune_info[tune_string];
GCC,riscv,917,if (num_int_old != num_int_new || num_float_old != num_float_new) {
GCC,riscv,918,
GCC,riscv,919,"riscv_get_arg_info(&info, cum, arg.mode, arg.type, arg.named, false);"
GCC,riscv,920,return false;
GCC,riscv,921,"return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode1 , regno1 ) , GEN_INT ( offset1 ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode2 , regno2 ) , GEN_INT ( offset2 ) ) ) ) ;"
GCC,riscv,922,return x;
GCC,riscv,923,"x = gen_rtx_PARALLEL ( type_mode , gen_rtvec ( <NUM_LIT> , x ) ) ;"
GCC,riscv,924,return false;
GCC,riscv,925,"output_addr_const (file, newop);"
GCC,riscv,926,case MEM :
GCC,riscv,927,"fprintf ( file , <STR_LIT> , reloc ) ;"
GCC,riscv,928,
GCC,riscv,929,condition ? expression1 : expression2
GCC,riscv,930,condition ? expression1 : expression2
GCC,riscv,931,return regno;
GCC,riscv,932,riscv_remove_unneeded_save_restore_calls();
GCC,riscv,933,
GCC,riscv,934,"dwarf = alloc_reg_note(REG_CFA_RESTORE, reg, dwarf);"
GCC,riscv,935,return const0_rtx;
GCC,riscv,936,"return gen_rtx_MEM (VOIDmode, gen_rtx_PLUS (Pmode, frame, GEN_INT (count)));"
GCC,riscv,937,
GCC,riscv,938,"memset(&args, <NUM_LIT>, sizeof(args));"
GCC,riscv,939,
GCC,riscv,940,"However, based on the names of the functions and the context of the code, it is likely that the next statement will be a call to `riscv_emit_move` with the same arguments as the previous call, or a call to `riscv_set_frame_expr` with a different argument"
GCC,riscv,941,
GCC,riscv,942,
GCC,riscv,943,return false;
GCC,riscv,944,
GCC,riscv,945,"return get_named_section(decl, <STR_LIT>, reloc);"
GCC,riscv,946,
GCC,riscv,947,cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD;
GCC,riscv,948,cfun->machine->interrupt_mode = riscv_get_interrupt_type(decl);
GCC,riscv,949,"riscv_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address ) , address ) ;"
GCC,riscv,950,"addr = plus_constant ( Pmode , base , offset ) ;"
GCC,riscv,951,"return g_switch_value && IN_RANGE ( size , <NUM_LIT> , g_switch_value ) ;"
GCC,riscv,952,
GCC,riscv,953,
GCC,riscv,954,
GCC,riscv,955,"rtx high_dest = riscv_subword ( dest , true ) ;"
GCC,riscv,956,"riscv_emit_move(low_dest, riscv_subword(src, false));"
GCC,riscv,957,
GCC,riscv,958,"return gen_rtx_fmt_ee ( PLUS , mode , hi , lo ) ;"
GCC,riscv,959,"cost = <NUM_LIT> + riscv_build_integer ( codes , loval , VOIDmode ) ;"
GCC,riscv,960,"cost += riscv_build_integer(codes, hival, VOIDmode);"
GCC,riscv,961,"* low_out = gen_rtx_LO_SUM ( Pmode, high, addr );"
GCC,riscv,962,"emit_insn (gen_auipcdi (temp, copy_rtx (addr), GEN_INT (seqno)))"
GCC,riscv,963,if (symbol_type == SYMBOL_TLS_LE) return true;
GCC,riscv,964,
GCC,riscv,965,
GCC,riscv,966,"if ( MEM_P ( op ) ) return adjust_address ( op , word_mode , byte ) ;"
GCC,riscv,967,"return adjust_address ( op , word_mode , byte ) ;"
GCC,riscv,968,
GCC,riscv,969,"inst = gen_rtx_SET (VOIDmode, operands[0], operands[1]);"
GCC,riscv,970,
GCC,riscv,971,
GCC,riscv,972,
GCC,riscv,973,
GCC,riscv,974,"mem = adjust_address ( m_tramp , SImode , <NUM_LIT> * GET_MODE_SIZE ( SImode ) ) ;"
GCC,riscv,975,"prefix = "".srodata"";"
GCC,riscv,976,"string = ACONCAT((linkonce, prefix, <STR_LIT>, name, NULL));"
GCC,riscv,977,"base = riscv_unspec_address_base(address, symbol_type);"
GCC,riscv,978,"base = gen_rtx_PLUS ( Pmode , base , offset ) ;"
GCC,riscv,979,"rtx riscv_unspec_address_offset ( rtx base , rtx offset , enum riscv_symbol_type symbol_type ) {"
GCC,riscv,980,"rtx riscv_unspec_offset_high ( rtx temp , rtx addr , enum riscv_symbol_type symbol_type ) {"
GCC,riscv,981,return frame->save_libcall_adjustment != <NUM_LIT>;
GCC,riscv,982,"return ( REG_P ( x ) && riscv_regno_mode_ok_for_base_p ( REGNO ( x ) , mode , strict_p ) ) ;"
GCC,riscv,983,
GCC,riscv,984,align = riscv_symbol_align ( sym_type );
GCC,riscv,985,align = ( SYMBOL_REF_DECL ( x ) ? DECL_ALIGN ( SYMBOL_REF_DECL ( x ) ) : <NUM_LIT> ) ;
GCC,riscv,986,return false;
GCC,riscv,987,"std_expand_builtin_va_start(valist, nextarg);"
GCC,riscv,988,return !riscv_naked_function_p(decl);
GCC,riscv,989,
GCC,riscv,990,return cmp0;
GCC,riscv,991,__asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ;
GCC,riscv,992,
GCC,riscv,993,"__asm__ __volatile__ ( ""csrrw x0, 0x080, %0"" : : ""r"" (value) : ""memory"" );"
GCC,riscv,994,"*base = XEXP (addr, <NUM_LIT>);"
GCC,riscv,995,* base_ptr = x;
GCC,riscv,996,
GCC,riscv,997,
GCC,riscv,998,bool reversed = false;
GCC,riscv,999,"rtx base; HOST_WIDE_INT offset; split_plus (XEXP (mem, <NUM_LIT>), &base, &offset);"
GCC,riscv,1000,int mem_op = load_p ? <NUM_LIT> : <NUM_LIT>;
GCC,riscv,1001,"if ( reversed ) { std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; }"
GCC,riscv,1002,output_operands[0] = copy_rtx(reg1);
GCC,riscv,1003,output_operands [ <NUM_LIT> ] = copy_rtx ( reg2 ) ;
GCC,riscv,1004,
GCC,riscv,1005,
GCC,riscv,1006,RTX_FRAME_RELATED_P(insn) = <NUM_LIT>;
GCC,riscv,1007,
GCC,riscv,1008,
GCC,riscv,1009,
GCC,arc,0,
GCC,arc,1,
GCC,arc,2,
GCC,arc,3,
GCC,arc,4,
GCC,arc,5,
GCC,arc,6,
GCC,arc,7,"else cpp_undef ( pfile , name ) ;"
GCC,arc,8,switch (GET_CODE (plus1)) {
GCC,arc,9,
GCC,arc,10,
GCC,arc,11,return true;
GCC,arc,12,return true;
GCC,arc,13,"size_to_deallocate -= arc_restore_callee_saves ( <NUM_LIT> , false , restore_fp , first_offset , size_to_deallocate ) ;"
GCC,arc,14,intval = (REG_P(operands[<NUM_LIT>]) ? <NUM_LIT> : CONST_INT_P(operands[<NUM_LIT>]) ? INTVAL(operands[<NUM_LIT>]) : <NUM_LIT>);
GCC,arc,15,
GCC,arc,16,"XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ;"
GCC,arc,17,
GCC,arc,18,*pretend_size = (MAX_ARC_PARM_REGS - first_reg_offset) * UNITS_PER_WORD;
GCC,arc,19,"xop[<NUM_LIT>] = gen_rtx_REG(SImode, REGNO(operands[<NUM_LIT>]));"
GCC,arc,20,"xop[<NUM_LIT> + i] = operand_subword(operands[i], <NUM_LIT>, <NUM_LIT>, mode);"
GCC,arc,21,"operands[<NUM_LIT>] = gen_rtx_PLUS(SImode, operands[<NUM_LIT>], operands[<NUM_LIT>]);"
GCC,arc,22,"operands[<NUM_LIT>] = gen_rtx_PLUS(SImode, operands[<NUM_LIT>], operands[<NUM_LIT>]);"
GCC,arc,23,
GCC,arc,24,
GCC,arc,25,if ( ! TARGET_ARC700 ) return ;
GCC,arc,26,return;
GCC,arc,27,return <NUM_LIT>;
GCC,arc,28,return <NUM_LIT>;
GCC,arc,29,arc_ccfsm_state += <NUM_LIT> ;
GCC,arc,30,arc_ccfsm_state += <NUM_LIT> ;
GCC,arc,31,(void) arc_compute_frame_size(get_frame_size());
GCC,arc,32,if ( ! current_frame_info . initialized ) ( void ) arc_compute_frame_size ( get_frame_size ( ) ) ;
GCC,arc,33,
GCC,arc,34,
GCC,arc,35,arc_text_section = tmp = xmalloc ( strlen ( arc_text_string ) + sizeof ( ARC_SECTION_FORMAT ) + <NUM_LIT> ) ;
GCC,arc,36,"case PLUS : { register rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; register rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG ) break ; switch ("
GCC,arc,37,
GCC,arc,38,
GCC,arc,39,
GCC,arc,40,
GCC,arc,41,return <NUM_LIT>;
GCC,arc,42,return <NUM_LIT>;
GCC,arc,43,
GCC,arc,44,total_size = ARC_STACK_ALIGN(total_size);
GCC,arc,45,fn_type = ARC_FUNCTION_NORMAL;
GCC,arc,46,return <NUM_LIT>;
GCC,arc,47,return ( ( ( unsigned HOST_WIDE_INT ) low <= <NUM_LIT> && high == <NUM_LIT> ) || ( ( ( low & - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) == - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) && high == - <NUM_LIT> ) ) ;
GCC,arc,48,
GCC,arc,49,
GCC,arc,50,
GCC,arc,51,"fprintf ( asm_out_file , <STR_LIT> , arc_cpu_string ) ;"
GCC,arc,52,case BARRIER:
GCC,arc,53,"return strcmp(arg, <STR_LIT>) == <NUM_LIT> || ARC_EXTENSION_CPU(arg);"
GCC,arc,54,"arc_punct_chars['""'] = <NUM_LIT>;"
GCC,arc,55,"arc_initialize_trampoline ( tramp, fnaddr, cxt );"
GCC,arc,56,"arc_initialize_trampoline ( tramp, fnaddr, cxt );"
GCC,arc,57,arc_mode_class[i] = <NUM_LIT> << (int) C_MODE;
GCC,arc,58,"1. The `switch` statement is checking the value of `i`, which is the mode of the instruction."
GCC,arc,59,"fprintf(stream, ""%s%lu"", prefix, labelno);"
GCC,arc,60,"fprintf ( file , <STR_LIT> , sp_str , sp_str ) ;"
GCC,arc,61,size = ARC_STACK_ALIGN ( size ) ;
GCC,arc,62,"fputs ( reg_names [ REGNO ( base ) ] , file ) ;"
GCC,arc,63,if (size == 0) return true;
GCC,arc,64,return false;
GCC,arc,65,*total = COSTS_N_INSNS(<NUM_LIT>);
GCC,arc,66,"fprintf(file, <STR_LIT>, op, reg_names[regno], base_reg, offset);"
GCC,arc,67,"fprintf(file, <STR_LIT>, op, reg_names[regno], base_reg, offset);"
GCC,arc,68,
GCC,arc,69,int size = MAX_ARC_PARM_REGS - first_reg_offset;
GCC,arc,70,"nextarg = plus_constant ( nextarg , UNITS_PER_WORD ) ;"
GCC,arc,71,"return ( symbolic_operand ( op , mode ) || ( GET_CODE ( op ) == CONST_INT && LEGITIMATE_CONSTANT_P ( op ) ) || ( GET_CODE ( op ) == REG ) ) ;"
GCC,arc,72,
GCC,arc,73,"op = XEXP ( op , <NUM_LIT> ) ;"
GCC,arc,74,
GCC,arc,75,
GCC,arc,76,
GCC,arc,77,"emit_insn ( gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ) ;"
GCC,arc,78,case GTU: return <NUM_LIT>;
GCC,arc,79,"In the third case, if `op` is"
GCC,arc,80,"However, based on the syntax and the context of the code, it is likely that the next statement will be an assignment to the `op` variable, using the value of `XEXP` as the right-hand side of the assignment. The `<NUM_LIT>` placeholder in the code suggests that the value of `XEXP` is a numeric literal, and the use of the `XEXP"
GCC,arc,81,return <NUM_LIT> ;
GCC,arc,82,case CONST_INT : return <NUM_LIT> ;
GCC,arc,83,case CONST_DOUBLE:
GCC,arc,84,
GCC,arc,85,"return move_double_src_operand ( SUBREG_REG ( op ) , mode ) ;"
GCC,arc,86,
GCC,arc,87,
GCC,arc,88,"return nonimmediate_operand ( op , mode ) ;"
GCC,arc,89,
GCC,arc,90,
GCC,arc,91,return ( code == EQ || code == NE || code == LTU || code == GEU || code == GTU || code == LEU );
GCC,arc,92,current_insn_set_cc_p = 1;
GCC,arc,93,current_insn_set_cc_p = <NUM_LIT>;
GCC,arc,94,return <NUM_LIT>;
GCC,arc,95,"However, based on the syntax and the context of the code, it is likely that the next statement will be an assignment to the `op` variable, using the value of `XEXP` as the right-hand side of the assignment. The `<NUM_LIT>` placeholder in the code suggests that the value of `XEXP` is a numeric literal, and the use of the `XEXP"
GCC,arc,96,"if ( GET_CODE ( op ) != PLUS || GET_MODE ( op ) != Pmode || ! register_operand ( XEXP ( op , <NUM_LIT"
GCC,arc,97,if (GET_CODE(op) != MEM) return <NUM_LIT>;
GCC,arc,98,"However, based on the syntax and the context of the code, it is likely that the next statement will be an assignment to the `op` variable, using the value of `XEXP` as the right-hand side of the assignment. The `<NUM_LIT>` placeholder in the code suggests that the value of `XEXP` is a numeric literal, and the use of the `XEXP"
GCC,arc,99,
GCC,arc,100,case SET: case POST_INC: case POST_DEC: case PRE_INC: case PRE_DEC: break;
GCC,arc,101,case CONST_INT:
GCC,arc,102,"if ( TARGET_ARC600 ) { rtx_insn * succ = next_real_insn ( insn ) ; if ( succ && INSN_P ( succ ) ) len += arc600_corereg_hazard ( insn , succ ) ; }"
GCC,arc,103,return ( ( LABEL_P ( prev ) || ( TARGET_ARC600 && ( JUMP_P ( prev ) || CALL_P ( prev ) || ( NONJUMP_INSN_P ( prev ) && GET_CODE ( PATTERN ( prev ) ) == SEQUENCE ) ) ) ) ? len + <NUM_LIT> : len ) ;
GCC,arc,104,cum->bytes += bytes;
GCC,arc,105,"ret = ROUND_ADVANCE_CUM ( arg_num , mode , type ) ;"
GCC,arc,106,
GCC,arc,107,"if ( globalize_p ) ( * targetm . asm_out . globalize_label ) ( stream , name ) ;"
GCC,arc,108,Here's a breakdown of the code:
GCC,arc,109,switch (get_attr_type(u.r)) {
GCC,arc,110,if (loop_depth > <NUM_LIT>) return false;
GCC,arc,111,"If all of these conditions are true, the `return"
GCC,arc,112,"arc_ccfsm_record_condition(XEXP(src, <NUM_LIT>), XEXP(src, <NUM_LIT>) == pc_rtx, insn, state);"
GCC,arc,113,
GCC,arc,114,
GCC,arc,115,return fun -> machine -> fn_type = fn_type ;
GCC,arc,116,frame->millicode_start_reg = <NUM_LIT>;
GCC,arc,117,if (TREE_CODE (decl) == NAMESPACE_DECL && DECL_NAMESPACE_ANON_P (decl)) return true;
GCC,arc,118,
GCC,arc,119,
GCC,arc,120,
GCC,arc,121,SYMBOL_REF_FLAGS (symbol) |= flags;
GCC,arc,122,return true;
GCC,arc,123,
GCC,arc,124,if ( store[i] ) emit_insn ( store[i] ) ;
GCC,arc,125,"dst_addr = adjust_address (dst, BLKmode, 0);"
GCC,arc,126,"frame_pointer_rtx = gen_rtx_REG ( Pmode, FRAME_POINTER_REGNUM );"
GCC,arc,127,"pat = gen_rtx_CONST ( Pmode , pat ) ;"
GCC,arc,128,Here's a breakdown of the code:
GCC,arc,129,cfun->machine->size_reason = <NUM_LIT>;
GCC,arc,130,
GCC,arc,131,
GCC,arc,132,"ret = gen_rtx_REG ( mode , arg_num ) ; debstr = reg_names [ arg_num ] ;"
GCC,arc,133,for (i = 0; i < words; i++) *cum = ARC_NEXT_ARG_REG(*cum);
GCC,arc,134,cum->nargs_prototype = words;
GCC,arc,135,
GCC,arc,136,return true;
GCC,arc,137,
GCC,arc,138,"warning ( OPT_Wattributes , <STR_LIT> , name ) ;"
GCC,arc,139,* no_add_attrs = true;
GCC,arc,140,"return arc600_corereg_hazard ( pred , succ ) ;"
GCC,arc,141,merge_bb = <NUM_LIT>;
GCC,arc,142,arc_init_reg_tables ( ) ;
GCC,arc,143,
GCC,arc,144,return ( cfun -> machine -> frame_info . total_size - ( cfun -> machine -> frame_info . pretend_size + cfun -> machine -> frame_info . extra_size + cfun -> machine -> frame_info . reg_size ) ) ;
GCC,arc,145,
GCC,arc,146,
GCC,arc,147,
GCC,arc,148,machine->force_short_suffix = -1;
GCC,arc,149,arc_mode_class[i] = <NUM_LIT> << (int) TF_MODE;
GCC,arc,150,if (GET_MODE_SIZE(m) <= <NUM_LIT>) arc_mode_class[i] = <NUM_LIT> << (int)S_MODE;
GCC,arc,151,ilp->insn_length_parameters = arc_insn_length_parameters;
GCC,arc,152,if ( TREE_CODE ( decl ) != VAR_DECL ) return false ;
GCC,arc,153,return loop_align;
GCC,arc,154,return align_labels_log;
GCC,arc,155,
GCC,arc,156,"if (arc_raw_symbolic_reference_mentioned_p(x, false)) return false;"
GCC,arc,157,
GCC,arc,158,
GCC,arc,159,
GCC,arc,160,"inner = plus_constant ( Pmode , XEXP ( addr , <NUM_LIT> ) , upper ) ;"
GCC,arc,161,"if ( GET_CODE ( addr ) == CONST ) { addr = XEXP ( addr , <NUM_LIT> ) ;"
GCC,arc,162,
GCC,arc,163,if ( GET_MODE_SIZE ( mode ) + offset - offset_base <= ( <NUM_LIT> << shift ) ) {
GCC,arc,164,"* p = gen_rtx_PLUS ( Pmode , sum , GEN_INT ( offset - offset_base ) ) ;"
GCC,arc,165,return ! TARGET_NO_LRA;
GCC,arc,166,
GCC,arc,167,
GCC,arc,168,if ( ! LABEL_P ( insn ) ) {
GCC,arc,169,if ( ! LABEL_P ( insn ) )
GCC,arc,170,int neg_intval = -intval;
GCC,arc,171,"sprintf(buf, <STR_LIT>, fname);"
GCC,arc,172,"sprintf(buf, <STR_LIT>, fname);"
GCC,arc,173,
GCC,arc,174,
GCC,arc,175,"case ZERO_EXTEND : case SIGN_EXTEND : arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ;"
GCC,arc,176,Here's a breakdown of the code:
GCC,arc,177,
GCC,arc,178,if (cl == NO_REGS) return NO_REGS;
GCC,arc,179,
GCC,arc,180,
GCC,arc,181,fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ;
GCC,arc,182,fmt = GET_RTX_FORMAT (GET_CODE (op));
GCC,arc,183,return <NUM_LIT>;
GCC,arc,184,return ( size == - <NUM_LIT> || size > <NUM_LIT> ) ;
GCC,arc,185,
GCC,arc,186,return ( afi -> save_return_addr ? afi -> total_size - afi -> pretend_size - afi -> extra_size : - <NUM_LIT> ) ;
GCC,arc,187,
GCC,arc,188,return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_SMALL_P ( x ) ) ;
GCC,arc,189,
GCC,arc,190,
GCC,arc,191,"rtx reg = gen_rtx_REG ( SImode , regno ) ;"
GCC,arc,192,"rtx reg = gen_rtx_REG (SImode, regno);"
GCC,arc,193,"1. The code snippet appears to be checking the validity of certain conditions for a given operation, based on the mode of the operands and the operation being performed."
GCC,arc,194,int first_reg_offset = first_anon_arg;
GCC,arc,195,* pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ;
GCC,arc,196,
GCC,arc,197,start_sequence ( ) ;
GCC,arc,198,"gcc_assert ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , addr ) ) ;"
GCC,arc,199,"return plus_constant ( Pmode , addr , <NUM_LIT> ) ;"
GCC,arc,200,rtx arc_trampoline_adjust_address ( rtx addr ) {
GCC,arc,201,return priority + <NUM_LIT>;
GCC,arc,202,machine = get_attr_machine ( insn ) ;
GCC,arc,203,rtx dest = SET_DEST ( pat ) ;
GCC,arc,204,dest_uid = GET_CODE ( dest );
GCC,arc,205,
GCC,arc,206,case SYMBOL_REF :
GCC,arc,207,
GCC,arc,208,"addr = XEXP (op, 0);"
GCC,arc,209,return LEGITIMATE_SMALL_DATA_ADDRESS_P ( addr ) ;
GCC,arc,210,if ( RTX_FRAME_RELATED_P ( insn ) ) {
GCC,arc,211,rtx temp = reload_in_progress ? operands[<NUM_LIT>] : gen_reg_rtx(Pmode);
GCC,arc,212,"if (GET_CODE(operands[<NUM_LIT>]) == MEM && SYMBOLIC_CONST(operands[<NUM_LIT>])) operands[<NUM_LIT>] = force_reg(Pmode, operands[<NUM_LIT>]);"
GCC,arc,213,block[offset] = value;
GCC,arc,214,"if ( reuse ) emit_insn ( gen_add2_insn ( addr , offs ) ) ;"
GCC,arc,215,iter->op = op;
GCC,arc,216,"rtx op1 = gen_rtx_REG ( cmode, GET_MODE_SIZE ( cmode ) / UNITS_PER_WORD ) ;"
GCC,arc,217,"return gen_rtx_REG ( SImode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,218,case CC_FPXmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case UNORDERED : return ARC_CC_C ; case ORDERED : return ARC_CC_NC ; case LTGT : return ARC_CC_HI ; case UNEQ : return ARC_CC_LS ; default : gcc_unreachable ( ) ; }
GCC,arc,219,
GCC,arc,220,pass_data_arc_ifcvt ( ctxt ) ;
GCC,arc,221,pass_data_arc_ifcvt ( ctxt ) ;
GCC,arc,222,if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! cse_not_expected ) {
GCC,arc,223,"MEM_COPY_ATTRIBUTES ( pat , operands [ <NUM_LIT> ] ) ;"
GCC,arc,224,else if (arc_rewrite_small_data_p(x)) return true;
GCC,arc,225,
GCC,arc,226,
GCC,arc,227,
GCC,arc,228,if ( GET_CODE ( x ) == COND_EXEC ) x = COND_EXEC_CODE ( x ) ;
GCC,arc,229,rtx src = SET_SRC ( x ) ;
GCC,arc,230,"count = gen_rtx_SYMBOL_REF ( Pmode , xstrdup ( buf ) ) ;"
GCC,arc,231,
GCC,arc,232,tree value = TREE_VALUE ( args ) ;
GCC,arc,233,for (a = DECL_ATTRIBUTES (decl); a; a = TREE_CHAIN (a)) {
GCC,arc,234,
GCC,arc,235,error ( <STR_LIT> ) ;
GCC,arc,236,frame_stack_add ( ra_offs ) ;
GCC,arc,237,size_to_deallocate -= ra_offs - first_offset;
GCC,arc,238,
GCC,arc,239,"pat = gen_rtx_CONST ( Pmode , pat ) ;"
GCC,arc,240,* no_add_attrs = true;
GCC,arc,241,* no_add_attrs = true ;
GCC,arc,242,if ( ! pred || ! INSN_P ( pred ) || ! succ || ! INSN_P ( succ ) ) return <NUM_LIT> ;
GCC,arc,243,case <NUM_LIT> :
GCC,arc,244,merge_bb = <NUM_LIT>;
GCC,arc,245,if ( TARGET_ATOMIC && ! ( TARGET_ARC700 || TARGET_HS ) ) error ( <STR_LIT> ) ;
GCC,arc,246,arc_mode_class[i] = <NUM_LIT> << (int) C_MODE;
GCC,arc,247,if ( ! succ_bb ) {
GCC,arc,248,if ( flag_pic ) target_flags |= MASK_NO_SDATA_SET ;
GCC,arc,249,"In the PLUS case, the code checks if the address is a small symbol reference by calling the SYMBOL_REF_SMALL_P function. If it is, it outputs the address as a constant using the output_addr_const function. If it is not a small symbol reference, it checks if the address is a multiplication of two"
GCC,arc,250,
GCC,arc,251,"rtx srcLow = simplify_gen_subreg ( SImode , src , DFmode , <NUM_LIT> ) ;"
GCC,arc,252,if ( state == none ) return false ;
GCC,arc,253,int start_call = frame->millicode_start_reg;
GCC,arc,254,*pretend_size = (MAX_ARC_PARM_REGS - first_reg_offset) * UNITS_PER_WORD;
GCC,arc,255,JUMP_LABEL (insn) = emit_label (insn);
GCC,arc,256,
GCC,arc,257,if ( TARGET_HARD_FLOAT && ( ( cmode == SFmode && TARGET_FP_SP_BASE ) || ( cmode == DFmode && TARGET_FP_DP_BASE ) ) )
GCC,arc,258,
GCC,arc,259,"emit_insn (gen_rtx_SET (operands[<NUM_LIT>], operands[<NUM_LIT>]));"
GCC,arc,260,"rtx addr = copy_to_mode_reg ( Pmode , XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ;"
GCC,arc,261,succ0 = next_real_insn (insn)
GCC,arc,262,"emit_insn_before ( gen_nopv ( ) , succ0 ) ;"
GCC,arc,263,"case PLUS : { register rtx plus0 = XEXP ( addr , <NUM_LIT> ) ; register rtx plus1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( plus0 ) != REG && ( GET_CODE ( plus0 ) !="
GCC,arc,264,if ( GET_CODE ( SET_SRC ( scanbody ) ) == IF_THEN_ELSE ) fail = TRUE ;
GCC,arc,265,Here's a breakdown of the code:
GCC,arc,266,rtx dest = gen_reg_rtx ( Pmode ) ;
GCC,arc,267,emit_insn ( pat ) ;
GCC,arc,268,"pat = gen_rtx_SET ( baseptr_rtx , pat ) ;"
GCC,arc,269,return reg;
GCC,arc,270,"emit_move_insn ( reg , gen_rtx_REG ( Pmode , R0_REG ) ) ;"
GCC,arc,271,arc_init_reg_tables ( ) ;
GCC,arc,272,
GCC,arc,273,arc_mode_class[i] = (<NUM_LIT> << (int) S_MODE);
GCC,arc,274,arc_mode_class[i] = <NUM_LIT> << (int) C_MODE;
GCC,arc,275,if ( align_labels_log < <NUM_LIT> ) {
GCC,arc,276,if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) )
GCC,arc,277,
GCC,arc,278,"x = XEXP ( x , <NUM_LIT> ) ;"
GCC,arc,279,case ARC_UNSPEC_PLT :
GCC,arc,280,if (GET_CODE(addr) != CONST) return false;
GCC,arc,281,return arc_needs_pcl_p ( addr );
GCC,arc,282,
GCC,arc,283,"if (model != <NUM_LIT>) return arc_legitimize_tls_address (orig_x, model);"
GCC,arc,284,"return arc_legitimize_tls_address ( orig_x , model ) ;"
GCC,arc,285,"emit_insn (gen_rtx_SET (oldx, gen_rtx_fmt_ee (code, SImode, oldx, const0_rtx)));"
GCC,arc,286,"v = gen_rtvec ( <NUM_LIT> , addr , base ) ;"
GCC,arc,287,"if ( ( GET_CODE ( PATTERN ( jump ) ) == PARALLEL ) && ( XVECEXP ( PATTERN ( jump ) , <NUM_LIT> , <NUM_LIT> ) == ret_rtx ) ) return false ;"
GCC,arc,288,
GCC,arc,289,fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ;
GCC,arc,290,intval = (REG_P(operands[<NUM_LIT>]) ? <NUM_LIT> : CONST_INT_P(operands[<NUM_LIT>]) ? INTVAL(operands[<NUM_LIT>]) : <NUM_LIT>);
GCC,arc,291,
GCC,arc,292,
GCC,arc,293,return word_mode;
GCC,arc,294,"gcc_assert ( GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == CONST_INT ) ;"
GCC,arc,295,"arc_output_pic_addr_const ( file , c , <NUM_LIT> ) ;"
GCC,arc,296,"rtx srcLow = simplify_gen_subreg ( SImode , src , DFmode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,297,
GCC,arc,298,
GCC,arc,299,if (GET_CODE(x) == SYMBOL_REF && SYMBOL_REF_SMALL_P(x)) {
GCC,arc,300,*total = COSTS_N_INSNS(<NUM_LIT>);
GCC,arc,301,if ( ! producer ) return false ;
GCC,arc,302,if ( ! MEM_P ( out_addr ) ) return false ;
GCC,arc,303,
GCC,arc,304,
GCC,arc,305,rtx_insn * barrier = emit_barrier ( jump ) ;
GCC,arc,306,
GCC,arc,307,rtx temp = (reload_in_progress ? operands[<NUM_LIT>] : flag_pic ? gen_reg_rtx(Pmode) : NULL_RTX);
GCC,arc,308,succ1 = next_real_insn ( succ0 ) ;
GCC,arc,309,sizes->quick_push(<NUM_LIT>); sizes->quick_push(<NUM_LIT>);`
GCC,arc,310,
GCC,arc,311,"return gen_raw_REG ( Pmode , FRAME_POINTER_REGNUM ) ;"
GCC,arc,312,"return gen_rtx_MEM (Pmode, stack_pointer_rtx);"
GCC,arc,313,return ( ( to == FRAME_POINTER_REGNUM ) || ! arc_frame_pointer_needed ( ) );
GCC,arc,314,return ( ( to == FRAME_POINTER_REGNUM ) || ! arc_frame_pointer_needed ( ) );
GCC,arc,315,frame_info->total_size = total_size;
GCC,arc,316,return fun -> machine -> fn_type = fn_type ;
GCC,arc,317,mem = (rtx)arc_compute_frame_size(afi);
GCC,arc,318,
GCC,arc,319,return ( ( regno == arc_return_address_register ( fn_type ) ) || ( regno == RETURN_ADDR_REGNUM ) ) ;
GCC,arc,320,if ( arc_must_save_return_addr ( cfun ) && ! ARC_AUTOBLINK_IRQ_P ( fn_type ) )
GCC,arc,321,"src_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ;"
GCC,arc,322,"i ^= <NUM_LIT> , size -= piece"
GCC,arc,323,"asm_fprintf ( asm_out_file , <STR_LIT> , TARGET_RF16 ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,324,
GCC,arc,325,"memset(&arc_ccfsm_current, <NUM_LIT>, sizeof(arc_ccfsm_current));"
GCC,arc,326,TYPE_ATTRIBUTES ( fntype ) = attrs ;
GCC,arc,327,
GCC,arc,328,return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ;
GCC,arc,329,return ( cfun -> machine -> frame_info . total_size - cfun -> machine -> frame_info . pretend_size ) ;
GCC,arc,330,return false;
GCC,arc,331,return <NUM_LIT>;
GCC,arc,332,align_labels_log = <NUM_LIT>
GCC,arc,333,return true;
GCC,arc,334,return false;
GCC,arc,335,
GCC,arc,336,
GCC,arc,337,return <NUM_LIT>;
GCC,arc,338,"if ( GET_CODE ( op0 ) == ZERO_EXTRACT && XEXP ( op0 , <NUM_LIT> ) == const1_rtx && ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ) { op0 = XEXP ( cmp0 , <NUM_LIT> ) ; op1 = XEXP ( cmp0 , <NUM_LIT> ) ; }"
GCC,arc,339,regno = ILINK1_REGNUM;
GCC,arc,340,"if (MEM_P(op) && !LEGITIMATE_SMALL_DATA_ADDRESS_P(XEXP(op, <NUM_LIT>)))"
GCC,arc,341,
GCC,arc,342,sri->icode = in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store;
GCC,arc,343,
GCC,arc,344,machine = &insn->deps->machine;
GCC,arc,345,
GCC,arc,346,
GCC,arc,347,case E_CC_FPXmode : switch ( GET_CODE ( comparison ) ) { case EQ : return ARC_CC_EQ ; case NE : return ARC_CC_NE ; case UNORDERED : return ARC_CC_C ;
GCC,arc,348,while (comma) {
GCC,arc,349,case <NUM_LIT> :
GCC,arc,350,errno = 0;
GCC,arc,351,"error ( <STR_LIT> <STR_LIT> , arg ) ;"
GCC,arc,352,if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! cse_not_expected ) {
GCC,arc,353,
GCC,arc,354,
GCC,arc,355,"return gen_rtx_MEM (Pmode, stack_pointer_rtx);"
GCC,arc,356,
GCC,arc,357,frame_info -> save_return_addr = ( ! crtl -> is_leaf || df_regs_ever_live_p ( RETURN_ADDR_REGNUM ) || crtl -> calls_eh_return ) ;
GCC,arc,358,arc_regno_reg_class[PCL_REG] = NO_REGS;
GCC,arc,359,if ( ! gmask ) return false ;
GCC,arc,360,return true;
GCC,arc,361,Based on the
GCC,arc,362,"size_to_deallocate -= arc_restore_callee_milli(gmask, restore_blink, restore_fp, return_p, first_offset);"
GCC,arc,363,"frame_size_to_allocate -= arc_save_callee_saves ( gmask, save_blink, save_fp, first_offset );"
GCC,arc,364,register_pass ( & arc_ifcvt4_info ) ;
GCC,arc,365,
GCC,arc,366,"attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ;"
GCC,arc,367,"if ( ( GET_CODE ( x ) == PRE_MODIFY || GET_CODE ( x ) == POST_MODIFY ) && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && legitimate_offset_address_"
GCC,arc,368,return ! ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ;
GCC,arc,369,case <NUM_LIT> : firq_auto_save_p &= ( ( regno < <NUM_LIT> ) || ( ( regno > <NUM_LIT> ) && ( regno < <NUM_LIT> ) ) ) ; break ;
GCC,arc,370,RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;
GCC,arc,371,
GCC,arc,372,
GCC,arc,373,"frame_deallocated += frame_restore_reg ( hard_frame_pointer_rtx , <NUM_LIT> ) ;"
GCC,arc,374,regno = RETURN_ADDR_REGNUM ;
GCC,arc,375,regno = RETURN_ADDR_REGNUM;
GCC,arc,376,"reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ;"
GCC,arc,377,"XVECEXP (insn, <NUM_LIT>, indx) = gen_rtx_SET (mem, reg);"
GCC,arc,378,"emit_insn ( gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_MEM ( Pmode , plus_constant"
GCC,arc,379,"frame_allocated += frame_save_reg ( reg , offset ) ;"
GCC,arc,380,save_mode = DImode;
GCC,arc,381,mask = <NUM_LIT>;
GCC,arc,382,
GCC,arc,383,return false;
GCC,arc,384,case PLUS :
GCC,arc,385,if ( MEM_P ( operands [ <NUM_LIT> ] ) && ! cse_not_expected ) {
GCC,arc,386,
GCC,arc,387,"return GEN_FCN ( icode ) ( arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] , arg [ <NUM_LIT> ] ) ;"
GCC,arc,388,
GCC,arc,389,
GCC,arc,390,
GCC,arc,391,new_section->name = name;
GCC,arc,392,sec = sec -> next;
GCC,arc,393,"memcpy(reg_alloc_order, arc_default_alloc_order, sizeof(reg_alloc_order));"
GCC,arc,394,
GCC,arc,395,
GCC,arc,396,
GCC,arc,397,ret = ( ret >= words ? <NUM_LIT> : ret * UNITS_PER_WORD ) ;
GCC,arc,398,
GCC,arc,399,"j += arc_asm_insn_p ( XVECEXP ( x , <NUM_LIT> , i ) ) ;"
GCC,arc,400,
GCC,arc,401,"asm_fprintf ( f , <STR_LIT> , ARC_TEMP_SCRATCH_REG ) ;"
GCC,arc,402,
GCC,arc,403,return get_attr_type (insn);
GCC,arc,404,return get_attr_type (insn);
GCC,arc,405,modes->quick_push(V2HImode);
GCC,arc,406,return ! optimize_size && arc_reorg_in_progress;
GCC,arc,407,
GCC,arc,408,emit_insn (insn);
GCC,arc,409,"return !arc_legitimate_constant_p ( mode , x ) ;"
GCC,arc,410,
GCC,arc,411,
GCC,arc,412,
GCC,arc,413,if (get_attr_type(u.r) == TYPE_BRANCH) {
GCC,arc,414,"if ( arc_lpcwidth != <NUM_LIT> && ( wi :: gtu_p ( iterations_max , ( ( <NUM_LIT> << arc_lpcwidth ) - <NUM_LIT> ) ) || wi :: eq_p ( iterations_max , <NUM_LIT> ) ) ) return false ;"
GCC,arc,415,
GCC,arc,416,"int insns_skipped = 0, fail = FALSE, succeed = FALSE;"
GCC,arc,417,
GCC,arc,418,bool arc_ccfsm_branch_deleted_p ( void ) {
GCC,arc,419,bool arc_ccfsm_branch_deleted_p ( void ) {
GCC,arc,420,
GCC,arc,421,
GCC,arc,422,"arc_ccfsm_record_condition ( XEXP ( src , <NUM_LIT> ) , XEXP ( src , <NUM_LIT> ) == pc_rtx , insn , state ) ;"
GCC,arc,423,"However, based on the name of the macro and the fact that it is being called with the address of a variable, it is likely that the macro is recording the deletion of a branch in a control flow graph. The `arc_ccfsm_current` variable is likely to be a pointer"
GCC,arc,424,state->state = <NUM_LIT>;
GCC,arc,425,state->state = <NUM_LIT>;
GCC,arc,426,return false;
GCC,arc,427,
GCC,arc,428,if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ;
GCC,arc,429,if ( ( ival & ~ <NUM_LIT> ) == <NUM_LIT> ) return true ;
GCC,arc,430,
GCC,arc,431,arc_clear_unalign();
GCC,arc,432,arc_clear_unalign();
GCC,arc,433,
GCC,arc,434,fn_type |= ARC_FUNCTION_ILINK1;
GCC,arc,435,fn_type |= ARC_FUNCTION_ILINK1;
GCC,arc,436,frame->millicode_start_reg = <NUM_LIT>;
GCC,arc,437,frame->millicode_start_reg = <NUM_LIT>;
GCC,arc,438,if ( l1 | l2 | m1 | m2 | s1 | s2 ) {
GCC,arc,439,arc_regno_reg_class[R30_REG] = GENERAL_REGS;
GCC,arc,440,x = arc_delegitimize_address_0 ( x ) ;
GCC,arc,441,
GCC,arc,442,
GCC,arc,443,"case ARC_UNSPEC_GOTOFFPC : return XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ;"
GCC,arc,444,return ( ( ( unsigned HOST_WIDE_INT ) low <= <NUM_LIT> && high == <NUM_LIT> ) || ( ( ( low & - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) == - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) && high == - <NUM_LIT> ) ) ;
GCC,arc,445,"reg = gen_rtx_REG ( SImode , <NUM_LIT> ) ;"
GCC,arc,446,regno = REGNO ( rtl ) ;
GCC,arc,447,return p;
GCC,arc,448,
GCC,arc,449,mem = (rtx)arc_compute_frame_size(afi);
GCC,arc,450,SYMBOL_REF_FLAGS ( symbol ) = flags;
GCC,arc,451,
GCC,arc,452,for ( regno = ENTER_LEAVE_START_REG ; regno < NUM_LIT ; regno++ ) {
GCC,arc,453,if (epilogue_completed && ARC_INTERRUPT_P (fn_type)) {
GCC,arc,454,"emit_insn ( gen_arc_store_exclusivesi ( mem , after ) ) ;"
GCC,arc,455,if ( CONST_INT_P ( op0 ) ) {
GCC,arc,456,"emit_insn ( gen_rtx_SET ( oldvalue , gen_rtx_IOR ( SImode , oldv , val ) ) ) ;"
GCC,arc,457,"emit_insn (gen_rtx_SET (oldv, gen_rtx_AND (SImode, oldv, mask)));"
GCC,arc,458,
GCC,arc,459,
GCC,arc,460,
GCC,arc,461,"fprintf(asm_out_file, <STR_LIT>, INSN_ADDRESSES(INSN_UID(insn)));`"
GCC,arc,462,"memset ( & arc_ccfsm_current , <NUM_LIT> , sizeof arc_ccfsm_current ) ;"
GCC,arc,463,Here are a few possibilities:
GCC,arc,464,ret = const0_rtx;
GCC,arc,465,"*cum = ROUND_ADVANCE_CUM(*cum, arg.mode, arg.type);"
GCC,arc,466,
GCC,arc,467,
GCC,arc,468,"return gen_rtx_REG ( mode , <NUM_LIT> ) ;"
GCC,arc,469,"mode = PROMOTE_MODE ( mode, unsignedp, valtype );"
GCC,arc,470,"machine_mode ccm = GET_MODE ( XEXP ( cond , <NUM_LIT> ) ) ;"
GCC,arc,471,"machine_mode ccm = GET_MODE ( XEXP ( cond , <NUM_LIT> ) ) ;"
GCC,arc,472,* no_add_attrs = true ;
GCC,arc,473,tree arg = TREE_VALUE ( args ) ;
GCC,arc,474,*no_add_attrs = true;
GCC,arc,475,static tree
GCC,arc,476,"warning ( OPT_Wattributes , <STR_LIT> , name ) ;"
GCC,arc,477,"error ( <STR_LIT> , name ) ;"
GCC,arc,478,"if (!arc_hard_regno_mode_ok (regno, mode))"
GCC,arc,479,return <NUM_LIT>;
GCC,arc,480,"return arc600_corereg_hazard ( pred , succ ) ;"
GCC,arc,481,if ( JUMP_P ( insn ) ) {
GCC,arc,482,if ( TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP ) && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ;
GCC,arc,483,arc_multcost = COSTS_N_INSNS ( <NUM_LIT> ) ;
GCC,arc,484,"emit_block_move ( tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ;"
GCC,arc,485,return <NUM_LIT> ;
GCC,arc,486,arc_init_machine_status = init_machine_status ;
GCC,arc,487,machine->fn_type = ARC_FUNCTION_UNKNOWN;
GCC,arc,488,
GCC,arc,489,if (type == TYPE_MULTI) return cost + 1;
GCC,arc,490,"fprintf ( stream , ""%s%lu\n"" , prefix , labelno ) ;"
GCC,arc,491,
GCC,arc,492,return NULL;
GCC,arc,493,size = int_size_in_bytes (TREE_TYPE (decl));
GCC,arc,494,return false;
GCC,arc,495,"if (lookup_attribute(<STR_LIT>, attrs)) return true; return false;"
GCC,arc,496,"if (lookup_attribute(<STR_LIT>, attrs)) return true; return false;"
GCC,arc,497,return TARGET_JLI_ALWAYS;
GCC,arc,498,return TARGET_JLI_ALWAYS;
GCC,arc,499,return ( SYMBOL_REF_LONG_CALL_P ( sym_ref ) || ( TARGET_LONG_CALLS_SET && ! SYMBOL_REF_SHORT_CALL_P ( sym_ref ) && ! SYMBOL_REF_MEDIUM_CALL_P ( sym_ref ) ) ) ;
GCC,arc,500,return false;
GCC,arc,501,return true;
GCC,arc,502,if (attrs & TYPE_ATTRIBUTE_CONST) {
GCC,arc,503,return false;
GCC,arc,504,if ( TREE_CODE ( addr ) == MEM_REF ) {
GCC,arc,505,"attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ;"
GCC,arc,506,
GCC,arc,507,return align_labels.levels[<NUM_LIT>].log;
GCC,arc,508,return false;
GCC,arc,509,case CONST_VECTOR : switch ( mode ) { case E_V2HImode : return TARGET_PLUS_DMPY ;
GCC,arc,510,
GCC,arc,511,rtx x = orig_x;
GCC,arc,512,return orig_x;
GCC,arc,513,
GCC,arc,514,
GCC,arc,515,return addr;
GCC,arc,516,"if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && REG_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NU"
GCC,arc,517,"emit_move_insn ( tmp, arc_unspec_offset ( base, UNSPEC_TLS_GD ) ) ;"
GCC,arc,518,"return gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , arc_tp_regno ) , addr ) ;"
GCC,arc,519,
GCC,arc,520,
GCC,arc,521,return <NUM_LIT>;
GCC,arc,522,return ( GET_MODE_CLASS ( mode1 ) == MODE_INT && GET_MODE_CLASS ( mode2 ) == MODE_INT && GET_MODE_SIZE ( mode1 ) <= UNITS_PER_WORD && GET_MODE_SIZE ( mode2 ) <= UNITS_PER_WORD ) ;
GCC,arc,523,return false;
GCC,arc,524,return false;
GCC,arc,525,next = NEXT_INSN (insn);
GCC,arc,526,
GCC,arc,527,
GCC,arc,528,
GCC,arc,529,if (match2 && intval == neg_intval) { ... }
GCC,arc,530,
GCC,arc,531,"sprintf(buf, <STR_LIT>, fname);"
GCC,arc,532,"fputs ( <STR_LIT> , file ) ;"
GCC,arc,533,
GCC,arc,534,"In C++, when a function takes a parameter by reference, it means that the function can modify the original variable that was passed as an argument. When a function takes a parameter by value, it means that the function receives a copy of the original variable, and any"
GCC,arc,535,
GCC,arc,536,emit_insn ( gen_memory_barrier ( ) ) ;
GCC,arc,537,"ccm = GET_MODE ( XEXP ( cond , <NUM_LIT> ) ) ;"
GCC,arc,538,if (cl == NO_REGS) return NO_REGS;
GCC,arc,539,static machine_mode arc_preferred_simd_mode ( scalar_mode mode ) {
GCC,arc,540,emit_insn ( gen_memory_barrier ( ) ) ;
GCC,arc,541,emit_insn ( gen_memory_barrier ( ) ) ;
GCC,arc,542,"if ( output_sdata ) fputs ( <STR_LIT> , file ) ;"
GCC,arc,543,"emit_insn ( gen_rtx_SET ( destHigh , gen_rtx_UNSPEC_VOLATILE ( Pmode , gen_rtvec ( <NUM_LIT> , src ) , VUNSPEC_ARC_LR_HIGH ) ) ) ;"
GCC,arc,544,fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ;
GCC,arc,545,
GCC,arc,546,fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ;
GCC,arc,547,fmt = GET_RTX_FORMAT ( GET_CODE ( x ) ) ;
GCC,arc,548,"if ( ! brcc_nolimm_operator ( op , VOIDmode ) && ! long_immediate_operand ( op1 , VOIDmode ) && ( TARGET_ARC700 || ( TARGET_V2 && optimize_size ) || next_active_insn ( link_insn ) != insn ) ) continue ;"
GCC,arc,549,
GCC,arc,550,
GCC,arc,551,"XVECEXP (insn, <NUM_LIT>, indx++) = gen_rtx_SET (mem, reg);"
GCC,arc,552,if ( gmask ) for ( i = <NUM_LIT> ; i <= GMASK_LEN ; i ++ ) {
GCC,arc,553,regno = RETURN_ADDR_REGNUM;
GCC,arc,554,return const0_rtx;
GCC,arc,555,"return gen_rtx_MEM (VOIDmode, gen_rtx_PLUS (Pmode, frame, GEN_INT (count)));"
GCC,arc,556,return ( size == - <NUM_LIT> || size > ( TARGET_V2 ? <NUM_LIT> : <NUM_LIT> ) ) ;
GCC,arc,557,"XVECEXP ( insn , <NUM_LIT> , indx ++ ) = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ;"
GCC,arc,558,"emit_insn (gen_rtx_SET (gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM), gen_rtx_MEM (Pmode, plus_constant (Pmode, stack_pointer_rtx, reg_size))));"
GCC,arc,559,if ( ( gmask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) continue ;
GCC,arc,560,machine_mode save_mode = SImode;
GCC,arc,561,return cfun -> machine -> arc_reorg_started;
GCC,arc,562,return priority + <NUM_LIT>;
GCC,arc,563,return priority + <NUM_LIT>;
GCC,arc,564,
GCC,arc,565,sri->icode = in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store;
GCC,arc,566,gcc_assert ( GET_CODE ( addr ) == REG ) ;
GCC,arc,567,"emit_move_insn ( scratch , addr ) ;"
GCC,arc,568,case GT : case UNLE : return CC_Zmode ;
GCC,arc,569,return arc_attr_type(insn) == TYPE_COMPARE;
GCC,arc,570,
GCC,arc,571,return offset >= - <NUM_LIT> && offset <= <NUM_LIT>;
GCC,arc,572,if (is_short) {
GCC,arc,573,Here are a few possible next statements:
GCC,arc,574,
GCC,arc,575,
GCC,arc,576,
GCC,arc,577,
GCC,arc,578,
GCC,arc,579,shimm = (ival * <NUM_LIT> + <NUM_LIT>) & <NUM_LIT>;
GCC,arc,580,in_set = single_set ( consumer ) ;
GCC,arc,581,if ( ! MEM_P ( in_addr ) ) return false ;
GCC,arc,582,return false;
GCC,arc,583,
GCC,arc,584,
GCC,arc,585,
GCC,arc,586,
GCC,arc,587,
GCC,arc,588,* lo = '\0';
GCC,arc,589,"note = find_reg_note (branch, REG_BR_PROB, <NUM_LIT>);"
GCC,arc,590,"note = find_reg_note (branch, REG_BR_PROB, <NUM_LIT>);"
GCC,arc,591,"return gen_rtx_CONST ( Pmode , gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , loc ) , unspec ) ) ;"
GCC,arc,592,
GCC,arc,593,
GCC,arc,594,
GCC,arc,595,
GCC,arc,596,case E_V4SImode :
GCC,arc,597,iscompact = get_attr_iscompact (insn);
GCC,arc,598,
GCC,arc,599,
GCC,arc,600,
GCC,arc,601,dest_uid = get_uid ( dest ) ;
GCC,arc,602,
GCC,arc,603,
GCC,arc,604,align = get_symbol_alignment ( addr ) ;
GCC,arc,605,if ( RTX_FRAME_RELATED_P ( insn ) ) {
GCC,arc,606,
GCC,arc,607,rtx disi_highpart ( rtx in ) {
GCC,arc,608,"emit_insn (gen_rtx_fmt_ee (code, op0, op1, op2));"
GCC,arc,609,emit_insn (pat);
GCC,arc,610,jump.set_probability(profile_probability.very_unlikely());
GCC,arc,611,jump.set_probability(profile_probability.very_unlikely());
GCC,arc,612,
GCC,arc,613,return arc_predicate_delay_insns();
GCC,arc,614,
GCC,arc,615,
GCC,arc,616,
GCC,arc,617,if ( ! offset ) return NULL_RTX ;
GCC,arc,618,return x;
GCC,arc,619,
GCC,arc,620,return insn;
GCC,arc,621,"insn = frame_move_inc ( reg , addr , stack_pointer_rtx , <NUM_LIT> ) ;"
GCC,arc,622,"insn = frame_move_inc ( reg , addr , stack_pointer_rtx , <NUM_LIT> ) ;"
GCC,arc,623,"addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ;"
GCC,arc,624,"addr = gen_frame_mem ( GET_MODE ( reg ) , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ;"
GCC,arc,625,
GCC,arc,626,static rtx frame_stack_add ( HOST_WIDE_INT offset ) {
GCC,arc,627,
GCC,arc,628,gate(some_function);
GCC,arc,629,
GCC,arc,630,
GCC,arc,631,"return gen_rtx_REG ( SImode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;"
GCC,arc,632,
GCC,arc,633,"1. `rtx cur_base , cur_offset , tmp ;`: Declares three variables of type `rtx`: `cur_base`, `cur_offset`, and `tmp`."
GCC,arc,634,case E_CC_FP_GTmode : if ( TARGET_ARGONAUT_SET && TARGET_SPFP ) switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_N ; case UNLE : return ARC_CC_P ; default : gcc_unreachable ( ) ; } else switch ( GET_CODE ( comparison ) ) { case GT : return ARC_CC_HI ; case UNLE : return ARC_CC_LS ; default : gcc_unreach
GCC,arc,635,
GCC,arc,636,"return get_symbol_alignment ( XEXP ( x , <NUM_LIT> ) ) ;"
GCC,arc,637,
GCC,arc,638,"emit_insn_before (seq, BB_HEAD (loop->head));"
GCC,arc,639,"reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ;"
GCC,arc,640,"reg = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ;"
GCC,arc,641,xreg = decode_reg_name ( str ) ;
GCC,arc,642,
GCC,arc,643,if (GET_CODE (pat) == COND_EXEC) pat = COND_EXEC_CODE (pat);
GCC,arc,644,If
GCC,arc,645,
GCC,arc,646,"if ( RTX_OK_FOR_BASE_P ( XEXP ( op , <NUM_LIT> ) , ( strict ) ) ) return true ;"
GCC,arc,647,rtl_opt_pass *pass = make_pass_arc_ifcvt(ctxt);
GCC,arc,648,
GCC,arc,649,* offset = const0_rtx;
GCC,arc,650,return NULL;
GCC,arc,651,insn = NEXT_INSN ( insn ) ;
GCC,arc,652,t = GET_MODE_SIZE ( DImode ) - <NUM_LIT>;
GCC,arc,653,t = REGNO ( rt ) ;
GCC,arc,654,
GCC,arc,655,Here are a few possibilities: 3
GCC,arc,656,"fprintf (file, ""short suffix"");`"
GCC,arc,657,
GCC,arc,658,
GCC,arc,659,pass_data_arc_ifcvt ( ctxt ) ;
GCC,arc,660,pass_data_arc_ifcvt ( ctxt ) ;
GCC,arc,661,pass_arc_predicate_delay_insns ( ctxt )
GCC,arc,662,pass_arc_predicate_delay_insns ( ctxt )
GCC,arc,663,RTX_FRAME_RELATED_P (insn) = 1;
GCC,arc,664,if ( MEM_P ( operands [ <NUM_LIT> ] ) ) tmp = gen_reg_rtx ( mode ) ;
GCC,arc,665,"operands[<NUM_LIT>] = gen_rtx_PLUS(SImode, operands[<NUM_LIT>], operands[<NUM_LIT>]);"
GCC,arc,666,
GCC,arc,667,"operands[<NUM_LIT>] = gen_rtx_MINUS(SImode, operands[<NUM_LIT>], operands[<NUM_LIT>]);"
GCC,arc,668,return true;
GCC,arc,669,Based
GCC,arc,670,
GCC,arc,671,( * p ) ( ) ;
GCC,arc,672,
GCC,arc,673,
GCC,arc,674,( * p ) ( ) ;
GCC,arc,675,p = malloc(sizeof(func_ptr));
GCC,arc,676,p = malloc(sizeof(func_ptr));
LLVM,NVPTX,0,CallToOld->eraseFromParent();
LLVM,NVPTX,1,NewFunc -> setName(Func -> getName() + <STR_LIT>);
LLVM,NVPTX,2,return NvvmEntryPointMetadata;
LLVM,NVPTX,3,
LLVM,NVPTX,4,GlobalOffset ( ) : ModulePass ( ID ) {
LLVM,NVPTX,5,GlobalOffset ( ) : ModulePass ( ID ) {
LLVM,NVPTX,6,"Builder.CreateStore(Builder.getInt32(0), ImplicitOffset);"
LLVM,NVPTX,7,EntryPointMetadata = getEntryPointMetadata(M);
LLVM,NVPTX,8,const MDOperand & FuncOperand = MetadataNode -> getOperand ( <NUM_LIT> ) ;
LLVM,NVPTX,9,"return ""MyPass"";"
LLVM,NVPTX,10,LocalAccessorToSharedMemory ( ) : ModulePass ( ID ) {
LLVM,NVPTX,11,LocalAccessorToSharedMemory ( ) : ModulePass ( ID ) {
LLVM,NVPTX,12,Changed = true;
LLVM,NVPTX,13,Changed = true;
LLVM,NVPTX,14,
LLVM,NVPTX,15,delete *Current;
LLVM,NVPTX,16,*Str = S;
LLVM,NVPTX,17,
LLVM,NVPTX,18,
LLVM,NVPTX,19,
LLVM,NVPTX,20,
LLVM,NVPTX,21,
LLVM,NVPTX,22,NVVMReflectPass::NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {
LLVM,NVPTX,23,NVVMReflectPass::NVVMReflectPass(unsigned SmVersion) : SmVersion(SmVersion) {
LLVM,NVPTX,24,return new AllocaHoisting().hoistAllocas();
LLVM,NVPTX,25,StackProtector::addPreserved(some_value);
LLVM,NVPTX,26,StackProtector::addPreserved(some_value);
LLVM,NVPTX,27,
LLVM,NVPTX,28,AU . addRequired < DataLayout > ( ) ;
LLVM,NVPTX,29,
LLVM,NVPTX,30,
LLVM,NVPTX,31,++BI;
LLVM,NVPTX,32,AU.addRequired<DataLayoutPass>();
LLVM,NVPTX,33,Here are some possible next statements: 5. `I = E;` Th
LLVM,NVPTX,34,
LLVM,NVPTX,35,AU . addRequired < DataLayoutPass > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;
LLVM,NVPTX,36,AU.addRequired<TargetData>();
LLVM,NVPTX,37,AU.setPreservesAll();
LLVM,NVPTX,38,AU.addPreserved<MachineFunctionAnalysis>( );
LLVM,NVPTX,39,return AllocaHoisting ( );
LLVM,NVPTX,40,return AllocaHoisting ( );
LLVM,NVPTX,41,double double64 = ( double ) CFP -> getValueAPF ( ) . convertToDouble ( ) ;
LLVM,NVPTX,42,f = oneFunc;
LLVM,NVPTX,43,"for (i = <NUM_LIT>; i < n; i++) global_list.insert(global_list.end(), gv_array[i]);"
LLVM,NVPTX,44,i = 0;
LLVM,NVPTX,45,OutStreamer.AddBlankLine();
LLVM,NVPTX,46,
LLVM,NVPTX,47,O << Mang->ge
LLVM,NVPTX,48,"emitDeclaration(F, O);"
LLVM,NVPTX,49,O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ;
LLVM,NVPTX,50,Inst.setLoc(MI->getLoc());
LLVM,NVPTX,51,StringRef fileName(Scope.getFilename());
LLVM,NVPTX,52,FullPathName += sys::path::get_separator(ctx);
LLVM,NVPTX,53,
LLVM,NVPTX,54,O << getPTXFundamentalTypeStr(ETy); O << <STR_LIT>; O << *Mang->getSymbol(GVar); return;
LLVM,NVPTX,55,
LLVM,NVPTX,56,Some possible next statements could include:
LLVM,NVPTX,57,const FunctionType * FTy = dyn_cast < FunctionType > ( Ty ) ;
LLVM,NVPTX,58,case Type :: FloatTyID : return <STR_LIT> ;
LLVM,NVPTX,59,
LLVM,NVPTX,60,return reader;
LLVM,NVPTX,61,return MCOperand::CreateExpr(Expr);
LLVM,NVPTX,62,"MCExpr *Expr = MCExpr::Create(Expr, MCSymbolRefExpr::VK_None, OutContext);"
LLVM,NVPTX,63,
LLVM,NVPTX,64,
LLVM,NVPTX,65,MI -> getOperand ( i )
LLVM,NVPTX,66,
LLVM,NVPTX,67,O << <STR_LIT> << llvm::getSamplerName(*GVar) << <STR_LIT>;
LLVM,NVPTX,68,O << * p;
LLVM,NVPTX,69,O << <STR_LIT> ; return ;
LLVM,NVPTX,70,
LLVM,NVPTX,71,StringRef Filename(SP.getFilename());
LLVM,NVPTX,72,const Constant * C = dyn_cast < Constant > ( * ui ) ;
LLVM,NVPTX,73,if (const MDNode * md = dyn_cast<MDNode>(U)) {
LLVM,NVPTX,74,if ( !caller ) continue;
LLVM,NVPTX,75,
LLVM,NVPTX,76,
LLVM,NVPTX,77,
LLVM,NVPTX,78,
LLVM,NVPTX,79,"emitDeclaration(F, O);"
LLVM,NVPTX,80,
LLVM,NVPTX,81,
LLVM,NVPTX,82,if (const ConstantDataSequential * CDS = dyn_cast<ConstantDataSequential>(CPV)) {
LLVM,NVPTX,83,Bytes = TD->getTypeSizeInBits(CPV->getType()) / 8;
LLVM,NVPTX,84,llvm_unreachable(<STR_LIT>);
LLVM,NVPTX,85,global_list.remove(global_list.begin());
LLVM,NVPTX,86,OutStreamer.EmitRawText(OS2.str());
LLVM,NVPTX,87,
LLVM,NVPTX,88,
LLVM,NVPTX,89,
LLVM,NVPTX,90,"for (unsigned i = 0, e = gvars.size(); i != e; ++i) {"
LLVM,NVPTX,91,
LLVM,NVPTX,92,"OutStreamer.EmitRawText(StringRef(""<ISA_LIT>AsmPrinter::EmitFunctionBodyEnd""));"
LLVM,NVPTX,93,
LLVM,NVPTX,94,O << <STR_LIT>;
LLVM,NVPTX,95,
LLVM,NVPTX,96,O << <STR_LIT> ;
LLVM,NVPTX,97,OutStreamer.EmitRawText(OS.str());
LLVM,NVPTX,98,"printInstruction(MI, OS);"
LLVM,NVPTX,99,"if (llvm::getReqNTIDz(F, reqntidz) == false) reqntidz = <NUM_LIT>; else specified = true;"
LLVM,NVPTX,100,filenameMap[fileName.str()] = curLoc.getLine();
LLVM,NVPTX,101,msg.append(<STR_LIT>);
LLVM,NVPTX,102,O << <STR_LIT> << * Mang -> getSymbol ( GVar ) << <STR_LIT> ;
LLVM,NVPTX,103,
LLVM,NVPTX,104,temp << <STR_LIT>;
LLVM,NVPTX,105,alignStruct = alignStruct + align;
LLVM,NVPTX,106,return reader;
LLVM,NVPTX,107,
LLVM,NVPTX,108,
LLVM,NVPTX,109,
LLVM,NVPTX,110,"return MCBinaryExpr::CreateAdd(LHS, RHS, Ctx);"
LLVM,NVPTX,111,O << ']' ;
LLVM,NVPTX,112,O << ']' ;
LLVM,NVPTX,113,numHex = 10;
LLVM,NVPTX,114,O << MI->getOpcodeName();
LLVM,NVPTX,115,
LLVM,NVPTX,116,
LLVM,NVPTX,117,
LLVM,NVPTX,118,case MachineOperand::MO_ExternalSymbol: {
LLVM,NVPTX,119,
LLVM,NVPTX,120,"However, based on the syntax and the context of the code, it is likely that the next statement will be an iteration over the arguments of the function `F`, using the `arg_begin` and `arg_end` functions to determine the range of arguments to iterate over. The `I` variable is likely to be used as an iterator to"
LLVM,NVPTX,121,elems = vtparts[i].getVectorNumElements(); elemtype = vtparts[i].getVectorElementType();`
LLVM,NVPTX,122,O << *Mang->getSymbol(GVar);`
LLVM,NVPTX,123,
LLVM,NVPTX,124,theCurLine++;
LLVM,NVPTX,125,theCurLine++;
LLVM,NVPTX,126,"sys::path::append(FullPathName, Filename);"
LLVM,NVPTX,127,DISubprogram SP( *I );
LLVM,NVPTX,128,O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ;
LLVM,NVPTX,129,if (const MDNode *md = dyn_cast<MDNode>(U)) {
LLVM,NVPTX,130,const Function * caller = bb -> getParent ( ) ;
LLVM,NVPTX,131,const Use &use = *ui;
LLVM,NVPTX,132,"aggBuffer->addBytes(&Byte, <NUM_LIT>, <NUM_LIT>);"
LLVM,NVPTX,133,"AggBuffer->addSymbol(V, Cexpr->getOperand(<NUM_LIT>));"
LLVM,NVPTX,134,if (Pty->isPointerTy()) return false;
LLVM,NVPTX,135,
LLVM,NVPTX,136,"for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) {"
LLVM,NVPTX,137,bool ret = AsmPrinter::doFinalization(M);
LLVM,NVPTX,138,GlobalsEmitted = true;
LLVM,NVPTX,139,"OutStreamer->emitRawText(StringRef(""<STR_LIT>""));"
LLVM,NVPTX,140,O << <STR_LIT> ;
LLVM,NVPTX,141,
LLVM,NVPTX,142,if (bb->getParent() == F) {
LLVM,NVPTX,143,"emitDeclaration(F, O);"
LLVM,NVPTX,144,
LLVM,NVPTX,145,O << <NUM_LIT>;
LLVM,NVPTX,146,O.write(data);
LLVM,NVPTX,147,"O << ""("";"
LLVM,NVPTX,148,"for (unsigned i = 0, e = Globals.size(); i != e; ++i) printModuleLevelGV(Globals[i], OS2);"
LLVM,NVPTX,149,O << NTM.getDrvInterface();
LLVM,NVPTX,150,
LLVM,NVPTX,151,
LLVM,NVPTX,152,OutStreamer->EmitInstruction(Inst);
LLVM,NVPTX,153,"if ( ! getReqNTIDx ( F , reqntidx ) ) reqntidx = <NUM_LIT> ; else specified = true ;"
LLVM,NVPTX,154,O << <STR_LIT>;
LLVM,NVPTX,155,report_fatal_error(<STR_LIT> + llvm::Twine(AddressSpace));
LLVM,NVPTX,156,O << <STR_LIT> ; break ;
LLVM,NVPTX,157,
LLVM,NVPTX,158,OutStreamer->emitRawText(OS1.str());
LLVM,NVPTX,159,Ret = ( <NUM_LIT> << <NUM_LIT> ) ;
LLVM,NVPTX,160,Ret |= (RegNum & <NUM_LIT>);
LLVM,NVPTX,161,return OutContext.getOrCreateSymbol(Str);
LLVM,NVPTX,162,raw_svector_ostream ( Str ) << DEPOTNAME << getFunctionNumber ( ) ;
LLVM,NVPTX,163,
LLVM,NVPTX,164,```
LLVM,NVPTX,165,if (InitList == nullptr) {
LLVM,NVPTX,166,if (InitList->getNumOperands() == 0) return true;
LLVM,NVPTX,167,for (const MachineBasicBlock *PMBB : MBB.predecessors()) {
LLVM,NVPTX,168,RegisterAsmPrinter(X
LLVM,NVPTX,169,std::string SymName = *SymNamePtr;
LLVM,NVPTX,170,"For example, the next statement could be: ```"
LLVM,NVPTX,171,case Type::DoubleTyID:
LLVM,NVPTX,172,OutMI.addOperand(GetSymbolRef(OutContext.getOrCreateSymbol(Twine(MO.getSymbolName()))));
LLVM,NVPTX,173,O << ']' ; return false ;
LLVM,NVPTX,174,O << ']' ;
LLVM,NVPTX,175,
LLVM,NVPTX,176,"O << lead << format_hex_no_prefix(API.getZExtValue(), numHex, true);"
LLVM,NVPTX,177,
LLVM,NVPTX,178,
LLVM,NVPTX,179,
LLVM,NVPTX,180,"O << ""return "" << F.getReturnValue().getType().getAsString() << ""\n"";"
LLVM,NVPTX,181,
LLVM,NVPTX,182,O << <STR_LIT>;
LLVM,NVPTX,183,"OutStreamer->emitRawText(StringRef(""<STR_LIT>""));"
LLVM,NVPTX,184,
LLVM,NVPTX,185,O << <STR_LIT> << NumBytes << <STR_LIT> ;
LLVM,NVPTX,186,return true;
LLVM,NVPTX,187,
LLVM,NVPTX,188,for (int i = 0; i < Num; ++i) { buffer[curpos] = Ptr[i]; curpos++; }
LLVM,NVPTX,189,buffer[curpos] = <NUM_LIT>; curpos++;
LLVM,NVPTX,190,Symbols.push_back(GVar);
LLVM,NVPTX,191,
LLVM,NVPTX,192,for ( int i = 0 ; i < Num ; ++ i ) {
LLVM,NVPTX,193,size = _size;
LLVM,NVPTX,194,OutStreamer->emitRawText(<STR_LIT>);
LLVM,NVPTX,195,"EmitAlignment(NumBits, GV);"
LLVM,NVPTX,196,"EmitAlignment(NumBits, GV);"
LLVM,NVPTX,197,"emitDeclaration(&F, O);"
LLVM,NVPTX,198,O << <STR_LIT>;
LLVM,NVPTX,199,
LLVM,NVPTX,200,O << <STR_LIT> << align.value() << <STR_LIT> ;
LLVM,NVPTX,201,
LLVM,NVPTX,202,O << * (unsigned int *)(buffer + pos);
LLVM,NVPTX,203,
LLVM,NVPTX,204,"for ( const GlobalVariable * GV : Others ) VisitGlobalVariableForEmission ( GV , Order , Visited , Visiting ) ;"
LLVM,NVPTX,205,
LLVM,NVPTX,206,buffer = new char[1024];
LLVM,NVPTX,207,aggBuffer->addZeros(Bytes);
LLVM,NVPTX,208,"emitHeader(M, OS1, STI);"
LLVM,NVPTX,209,"emitDeclaration(F, O);"
LLVM,NVPTX,210,"emitDeclaration(F, O);"
LLVM,NVPTX,211,
LLVM,NVPTX,212,O << <STR_LIT>;
LLVM,NVPTX,213,
LLVM,NVPTX,214,
LLVM,NVPTX,215,StringRef fileName ( Scope -> getFilename ( ) ) ;
LLVM,NVPTX,216,"if (InterleaveSrc) this->emitSrcInText(fileName, curLoc.getLine());"
LLVM,NVPTX,217,
LLVM,NVPTX,218,O << <STR_LIT> ;
LLVM,NVPTX,219,
LLVM,NVPTX,220,return reader -> readLine ( ) ;
LLVM,NVPTX,221,reader = new LineReader(filename);
LLVM,NVPTX,222,"if (GetUnrollMetadata(LoopID, <STR_LIT>)) return true;"
LLVM,NVPTX,223,Here are a few possibilities:
LLVM,NVPTX,224,case Instruction :: Add : {
LLVM,NVPTX,225,
LLVM,NVPTX,226,const <ISA_LIT>MachineFunctionInfo * MFI = MF->getInfo< <ISA_LIT>MachineFunctionInfo >();
LLVM,NVPTX,227,case Type::DoubleTyID:
LLVM,NVPTX,228,O << lead;
LLVM,NVPTX,229,O << <STR_LIT> << ElementSize / <NUM_LIT> ;
LLVM,NVPTX,230,unsigned size = <NUM_LIT>;
LLVM,NVPTX,231,O << <STR_LIT> << sz << <STR_LIT> << idx ;
LLVM,NVPTX,232,"FullPathName += ""/"";"
LLVM,NVPTX,233,"OutStreamer->EmitDwarfFileDirective(i, <STR_LIT>, Filename);"
LLVM,NVPTX,234,O << <STR_LIT> ; break ;
LLVM,NVPTX,235,O << <STR_LIT> ;
LLVM,NVPTX,236,O << <STR_LIT> ;
LLVM,NVPTX,237,"if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm ) O << <STR_LIT> ; }"
LLVM,NVPTX,238,
LLVM,NVPTX,239,O << * MO . getMBB ( ) -> getSymbol ( ) ;
LLVM,NVPTX,240,
LLVM,NVPTX,241,
LLVM,NVPTX,242,buffer = new unsigned char[size];
LLVM,NVPTX,243,
LLVM,NVPTX,244,Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( i + <NUM_LIT> ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ;
LLVM,NVPTX,245,"aggBuffer->addZeros(<NUM_LIT>, Bytes);"
LLVM,NVPTX,246,if (gv->hasInternalLinkage() == false) return false;
LLVM,NVPTX,247,oneFunc = f;
LLVM,NVPTX,248,OutStreamer.AddComment(<STR_LIT>);`
LLVM,NVPTX,249,Mang->Initialize(
LLVM,NVPTX,250,
LLVM,NVPTX,251,
LLVM,NVPTX,252,
LLVM,NVPTX,253,
LLVM,NVPTX,254,Here are a few possibilities for what the next statement could be:
LLVM,NVPTX,255,
LLVM,NVPTX,256,
LLVM,NVPTX,257,if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ;
LLVM,NVPTX,258,OS2 << '\n';
LLVM,NVPTX,259,GVVisited.clear();
LLVM,NVPTX,260,O << <STR_LIT>;
LLVM,NVPTX,261,
LLVM,NVPTX,262,
LLVM,NVPTX,263,"EmitToStreamer(OutStreamer, Inst);"
LLVM,NVPTX,264,OS << Inst;
LLVM,NVPTX,265,if ( specified ) O << <STR_LIT> << reqntidx << <STR_LIT> << reqntidy << <STR_LIT> << reqntidz << <STR_LIT> ;
LLVM,NVPTX,266,SmallString<NUM_LIT> FullPathName = dirName;
LLVM,NVPTX,267,O << <STR_LIT> ;
LLVM,NVPTX,268,O << <STR_LIT>;
LLVM,NVPTX,269,case Type::StructTyID: case Type::ArrayTyID: case Type::VectorTyID:
LLVM,NVPTX,270,
LLVM,NVPTX,271,temp << <STR_LIT>;
LLVM,NVPTX,272,
LLVM,NVPTX,273,return <STR_LIT>;
LLVM,NVPTX,274,return MCOperand::CreateExpr(Expr);
LLVM,NVPTX,275,return MCOperand::CreateExpr(Expr);
LLVM,NVPTX,276,
LLVM,NVPTX,277,
LLVM,NVPTX,278,"For example, if the `ISA_LIT"
LLVM,NVPTX,279,
LLVM,NVPTX,280,case <STR_LIT> :
LLVM,NVPTX,281,
LLVM,NVPTX,282,
LLVM,NVPTX,283,O << <STR_LIT> ;
LLVM,NVPTX,284,"printFPConstant(MO.getFPImm(), O);"
LLVM,NVPTX,285,if (i < F->arg_size())
LLVM,NVPTX,286,
LLVM,NVPTX,287,O << *getSymbol(GVar);
LLVM,NVPTX,288,O << *getSymbol(GVar);
LLVM,NVPTX,289,"sys::path::append(FullPathName, Filename);"
LLVM,NVPTX,290,unsigned int numVRs = MRI->getNumVirtRegs();
LLVM,NVPTX,291,
LLVM,NVPTX,292,return false;
LLVM,NVPTX,293,if (const MDNode *md = dyn_cast<MDNode>(U)) {
LLVM,NVPTX,294,const BasicBlock * curBB = instr->getParent();
LLVM,NVPTX,295,Visiting.insert(GV);
LLVM,NVPTX,296,Others.insert(GV->getOperand(i));
LLVM,NVPTX,297,buffer = new char[1024];
LLVM,NVPTX,298,O << <STR_LIT>;
LLVM,NVPTX,299,O << <STR_LIT> ;
LLVM,NVPTX,300,"Here is a possible next statement: case Type::PointerTyID:     O << ""ptr"" << getPTXFundamentalTypeStr(ETy) << "" "" << getSymbol(GVar) << ""["" << ElementSize << ""]"";     break;"
LLVM,NVPTX,301,unsigned idx = <NUM_LIT>;
LLVM,NVPTX,302,i = 0;
LLVM,NVPTX,303,"global_list.insert(global_list.end(), gv_array[i]);"
LLVM,NVPTX,304,O << <STR_LIT> ;
LLVM,NVPTX,305,OutStreamer->EmitRawText(StringRef(<STR_LIT>));
LLVM,NVPTX,306,
LLVM,NVPTX,307,
LLVM,NVPTX,308,"alignStruct = std::max(alignStruct, getOpenCLAlignment(TD, ETy));"
LLVM,NVPTX,309,return false;
LLVM,NVPTX,310,
LLVM,NVPTX,311,
LLVM,NVPTX,312,O << * getSymbol ( GVar ) ;
LLVM,NVPTX,313,"rcStr += "":"" + std::to_string(n);`"
LLVM,NVPTX,314,return true;
LLVM,NVPTX,315,const BasicBlock * curBB = instr->getParent();
LLVM,NVPTX,316,O << <STR_LIT> ;
LLVM,NVPTX,317,if (Ty->isIntegerTy(<NUM_LIT>)) O << <STR_LIT>;
LLVM,NVPTX,318,
LLVM,NVPTX,319,if ( ETy -> isSingleValueType ( ) ) {
LLVM,NVPTX,320,ElementSize = TD -> getTypeStoreSize ( ETy ) ;
LLVM,NVPTX,321,"In the `for` loop, the code is iterating over the characters in the `OriginalName` string and checking if each character is equal to the `.` character. If a character is equal to `.`, then the code will append the string `<STR_LIT>`"
LLVM,NVPTX,322,"CleanNameStream << ""."";"
LLVM,NVPTX,323,"return MCBinaryExpr::CreateAdd(LHS, RHS, Ctx);"
LLVM,NVPTX,324,case MachineOperand::MO_FPImmediate: {
LLVM,NVPTX,325,"case MachineOperand::MO_GlobalAddress: MCOp = GetSymbolRef(MO, getSymbol(MO.getGlobal())); break;"
LLVM,NVPTX,326,const MachineOperand &MO = MI->getOperand(i);
LLVM,NVPTX,327,
LLVM,NVPTX,328,"printVecModifiedImmediate(MO, Modifier, O);"
LLVM,NVPTX,329,O << getSymbolName(GVar);
LLVM,NVPTX,330,f = oneFunc;
LLVM,NVPTX,331,OutStreamer.AddComment(<STR_LIT>);`
LLVM,NVPTX,332,"emitInlineAsm(M, OS1, STI);"
LLVM,NVPTX,333,"O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; if ( j < je - <NUM_LIT> ) O << <STR_LIT> ; ++ paramIndex ;"
LLVM,NVPTX,334,
LLVM,NVPTX,335,"EmitOperand(MI, OS);"
LLVM,NVPTX,336,OutStreamer.EmitRawText(temp.str());
LLVM,NVPTX,337,temp << line;
LLVM,NVPTX,338,temp << reader->readLine(line);
LLVM,NVPTX,339,
LLVM,NVPTX,340,OutMI.addOperand(GetSymbolRef(OutContext.GetOrCreateSymbol(Twine(MO.getSymbolName()))));
LLVM,NVPTX,341,OutMI.addOperand(GetSymbolRef(OutContext.GetOrCreateSymbol(Twine(MO.getSymbolName()))));
LLVM,NVPTX,342,
LLVM,NVPTX,343,O << <STR_LIT>;
LLVM,NVPTX,344,"O << *CurrentFnSym << ""<STR_LIT>"" << paramIndex;"
LLVM,NVPTX,345,
LLVM,NVPTX,346,O << <STR_LIT> ;
LLVM,NVPTX,347,StringRef Filename = SP->getFilename();
LLVM,NVPTX,348,for (const MDCompileUnit * DIUnit : DbgFinder.compile_units()) {
LLVM,NVPTX,349,const TargetRegisterClass * RC = TRI -> getRegClass ( i ) ;
LLVM,NVPTX,350,
LLVM,NVPTX,351,"O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; }"
LLVM,NVPTX,352,
LLVM,NVPTX,353,"O << ""retval"" << idx << "":"" << elemtype.getSizeInBits() << "":"" << elems << "":"" << retAlignment << "":"" << totalsz << "":"";"
LLVM,NVPTX,354,buffer = new unsigned char[size];
LLVM,NVPTX,355,i = 0;
LLVM,NVPTX,356,clearAnnotationCache(&M);
LLVM,NVPTX,357,OutStreamer->EmitRawText(OS1.str());
LLVM,NVPTX,358,
LLVM,NVPTX,359,
LLVM,NVPTX,360,O << <NUM_LIT>;
LLVM,NVPTX,361,"However, based on the syntax and the context of the code, it is likely that the next statement will be a call to the `emitDemotedVars` function, passing the result of the `getFunction` method as an argument. The `emitDemotedVars` function is likely to be responsible for emitting the demoted variables, which are the variables that"
LLVM,NVPTX,362,
LLVM,NVPTX,363,
LLVM,NVPTX,364,
LLVM,NVPTX,365,OutStreamer->AddComment(Twine(<STR_LIT>) + STI.getRegisterInfo()->getName(RegNo));
LLVM,NVPTX,366,MCInst Inst;
LLVM,NVPTX,367,O << <STR_LIT>;
LLVM,NVPTX,368,O << <STR_LIT> ;
LLVM,NVPTX,369,
LLVM,NVPTX,370,case Instruction::Add:
LLVM,NVPTX,371,case Instruction::AddrSpaceCast:
LLVM,NVPTX,372,
LLVM,NVPTX,373,O << (unsigned int)buffer[i];
LLVM,NVPTX,374,OutStreamer->EmitRawText(StringRef(<STR_LIT>));
LLVM,NVPTX,375,return Result;
LLVM,NVPTX,376,
LLVM,NVPTX,377,"emitDeclarations(M, OS2);"
LLVM,NVPTX,378,O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ;
LLVM,NVPTX,379,
LLVM,NVPTX,380,
LLVM,NVPTX,381,const FunctionType * FTy = dyn_cast < FunctionType > ( Ty ) ;
LLVM,NVPTX,382,
LLVM,NVPTX,383,O << <STR_LIT> ;
LLVM,NVPTX,384,Order.push_back(GV);
LLVM,NVPTX,385,OutStreamer->EmitRawText(StringRef(<STR_LIT>));
LLVM,NVPTX,386,OutStreamer->EmitRawText(StringRef(<STR_LIT>));
LLVM,NVPTX,387,
LLVM,NVPTX,388,
LLVM,NVPTX,389,O << <STR_LIT>;
LLVM,NVPTX,390,
LLVM,NVPTX,391,"GVVisited.insert(Globals.begin(), Globals.end());"
LLVM,NVPTX,392,O << <STR_LIT>;
LLVM,NVPTX,393,
LLVM,NVPTX,394,return OutContext.getOrCreateSymbol(Str);
LLVM,NVPTX,395,"for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ;"
LLVM,NVPTX,396,"OutStreamer->EmitRawText(""<STR_LIT>"");"
LLVM,NVPTX,397,"OutStreamer->EmitRawText(StringRef(""<STR_LIT>""));"
LLVM,NVPTX,398,seenMap[F] = true;
LLVM,NVPTX,399,"emitDeclaration(F, O);"
LLVM,NVPTX,400,
LLVM,NVPTX,401,
LLVM,NVPTX,402,"O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; }"
LLVM,NVPTX,403,
LLVM,NVPTX,404,
LLVM,NVPTX,405,O << <STR_LIT>;
LLVM,NVPTX,406,
LLVM,NVPTX,407,O << get<ISA_LIT>RegClassStr ( RC ) << mapped_vr;
LLVM,NVPTX,408,
LLVM,NVPTX,409,O << <STR_LIT>;
LLVM,NVPTX,410,
LLVM,NVPTX,411,if (auto *TS = static_cast<ISA_LIT>TargetStreamer *>(OutStreamer->getTargetStreamer())) {
LLVM,NVPTX,412,O << <STR_LIT>;
LLVM,NVPTX,413,O << <STR_LIT>;
LLVM,NVPTX,414,
LLVM,NVPTX,415,
LLVM,NVPTX,416,
LLVM,NVPTX,417,O << <STR_LIT>;
LLVM,NVPTX,418,
LLVM,NVPTX,419,"aggBuffer->addSymbol(v, Cexpr);"
LLVM,NVPTX,420,"O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ;"
LLVM,NVPTX,421,unsigned int alignStruct = <NUM_LIT>;
LLVM,NVPTX,422,case Instruction::AddrSpaceCast:
LLVM,NVPTX,423,
LLVM,NVPTX,424,"emitHeader(M, OS1, *STI);"
LLVM,NVPTX,425,StringRef fileName(Scope.getFilename());
LLVM,NVPTX,426,O << * ( unsigned int * ) ( & buffer [ pos ] ) ;
LLVM,NVPTX,427,"OutStreamer.EmitDwarfFileDirective(i, <STR_LIT>, Filename);"
LLVM,NVPTX,428,StringRef Filename(SP.getFilename());
LLVM,NVPTX,429,O << <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,430,case Instruction::GetElementPtr:
LLVM,NVPTX,431,O << <STR_LIT> << align << <STR_LIT> ;
LLVM,NVPTX,432,
LLVM,NVPTX,433,"ConvertFloatToBytes(ptr, float64);"
LLVM,NVPTX,434,if (TM.getTargetTriple().getOS() != Triple::NVCL) recordAndEmitFilenames(M);
LLVM,NVPTX,435,OutStreamer.AddBlankLine();
LLVM,NVPTX,436,OutStreamer.EmitRawText(StringRef(M.getModuleInlineAsm()));
LLVM,NVPTX,437,case Type::StructTyID:
LLVM,NVPTX,438,case Instruction::Add:
LLVM,NVPTX,439,
LLVM,NVPTX,440,O << *getSymbol(GVar); return;
LLVM,NVPTX,441,Mang = new Mangler();
LLVM,NVPTX,442,O << <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,443,
LLVM,NVPTX,444,O << <STR_LIT>;
LLVM,NVPTX,445,O << <STR_LIT> << ( int ) DL . getPrefTypeAlignment ( ETy ) ;
LLVM,NVPTX,446,"return MCBinaryExpr::createAdd(LHS, RHS, Ctx);"
LLVM,NVPTX,447,case Instruction::Trunc:
LLVM,NVPTX,448,O << <STR_LIT> << size << <STR_LIT> ;
LLVM,NVPTX,449,
LLVM,NVPTX,450,"for (i = <NUM_LIT>; i < n; i++) global_list.insert(global_list.end(), gv_array[i]);"
LLVM,NVPTX,451,i = 0;
LLVM,NVPTX,452,O << <STR_LIT> << MFI.getMaxAlignment() << <STR_LIT> << DEPOTNAME << getFunctionNumber() << <STR_LIT> << NumBytes << <STR_LIT>;
LLVM,NVPTX,453,case Type::PointerTyID:
LLVM,NVPTX,454,Mang->MangleModule(M);
LLVM,NVPTX,455,
LLVM,NVPTX,456,
LLVM,NVPTX,457,
LLVM,NVPTX,458,if (const ConstantDataSequential * CDS = dyn_cast<ConstantDataSequential>(CPV)) {
LLVM,NVPTX,459,OutStreamer.EmitRawText(OS2.str());
LLVM,NVPTX,460,"emitDeclarations(M, OS2);"
LLVM,NVPTX,461,
LLVM,NVPTX,462,
LLVM,NVPTX,463,
LLVM,NVPTX,464,const FunctionType * FTy = dyn_cast < FunctionType > ( Ty ) ;
LLVM,NVPTX,465,unsigned sz = elemtype.getSizeInBits();`
LLVM,NVPTX,466,unsigned sz = elemtype.getSizeInBits();`
LLVM,NVPTX,467,case Type::PointerTyID:`
LLVM,NVPTX,468,"O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ;"
LLVM,NVPTX,469,
LLVM,NVPTX,470,"const MCExpr * RHS = lowerConstantForGV(CE->getOperand(1), ProcessingGeneric);"
LLVM,NVPTX,471,
LLVM,NVPTX,472,case Instruction::AddrSpaceCast:
LLVM,NVPTX,473,case Instruction::AddrSpaceCast:
LLVM,NVPTX,474,
LLVM,NVPTX,475,case MachineOperand::MO_ExternalSymbol: {
LLVM,NVPTX,476,Bytes = TD->getStructLayout(ST)->getElementOffset(i) + TD->getTypeAllocSize(ST) - TD->getStructLayout(ST)->getElementOffset(i);
LLVM,NVPTX,477,
LLVM,NVPTX,478,GlobalsEmitted = false;
LLVM,NVPTX,479,
LLVM,NVPTX,480,O << <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,481,O << <STR_LIT> << getPTXFundamentalTypeStr(ETy) << <STR_LIT> << *getSymbol(GVar);
LLVM,NVPTX,482,O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ;
LLVM,NVPTX,483,
LLVM,NVPTX,484,
LLVM,NVPTX,485,"Inside each case, the code will generate PTX instructions to handle the specific data type. For example, for integers, the code"
LLVM,NVPTX,486,O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy );
LLVM,NVPTX,487,"return MCBinaryExpr::Create(CE->getOpcode(), LHS, RHS, Ctx);"
LLVM,NVPTX,488,GlobalsEmitted = false;
LLVM,NVPTX,489,return true;
LLVM,NVPTX,490,
LLVM,NVPTX,491,for (int i = 0; i < Num; ++i) { buffer[curpos] = Ptr[i]; curpos++; }
LLVM,NVPTX,492,Here are a few possibilities:
LLVM,NVPTX,493,buffer[curpos] = <NUM_LIT>;
LLVM,NVPTX,494,Bytes = CPV->getNumOperands() * sizeof(Constant*);
LLVM,NVPTX,495,if (oneFunc->hasInternalLinkage()) return false;
LLVM,NVPTX,496,p[i] = (unsigned char) *vp;
LLVM,NVPTX,497,i += <NUM_LIT>;
LLVM,NVPTX,498,*vp = (int32_t)i;
LLVM,NVPTX,499,p[i] = (unsigned char)vp;
LLVM,NVPTX,500,p[i] = (unsigned char)vp;
LLVM,NVPTX,501,const Value *V = U->getOperand(i);
LLVM,NVPTX,502,"for (i = <NUM_LIT>; i < n; i++) global_list.insert(global_list.end(), gv_array[i]);"
LLVM,NVPTX,503,OutStreamer->AddComment(<STR_LIT>);
LLVM,NVPTX,504,OutStreamer->AddComment(<STR_LIT>);
LLVM,NVPTX,505,"EmitAlignment(NumBits, GV);"
LLVM,NVPTX,506,"EmitAlignment(NumBits, GV);"
LLVM,NVPTX,507,AsmPrinter::EmitBasicBlockStart(MBB);
LLVM,NVPTX,508,O << <STR_LIT> ;
LLVM,NVPTX,509,"emitDeclaration(F, O);"
LLVM,NVPTX,510,const Function *F = FI;
LLVM,NVPTX,511,O << <STR_LIT> ;
LLVM,NVPTX,512,
LLVM,NVPTX,513,
LLVM,NVPTX,514,
LLVM,NVPTX,515,
LLVM,NVPTX,516,if ( specified ) O << <STR_LIT> << mincta << <STR_LIT> ;
LLVM,NVPTX,517,if (filenameMap.find(fileName) == filenameMap.end()) return;
LLVM,NVPTX,518,O << <STR_LIT>;
LLVM,NVPTX,519,"O << ""shared""; break;"
LLVM,NVPTX,520,
LLVM,NVPTX,521,temp << reader->readLine(line);
LLVM,NVPTX,522,O << getVirtualRegisterName(vr);
LLVM,NVPTX,523,
LLVM,NVPTX,524,AU.setPreservesAll();
LLVM,NVPTX,525,
LLVM,NVPTX,526,unsigned NumBits = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ;
LLVM,NVPTX,527,reader->readLine(line);
LLVM,NVPTX,528,return reader -> readLine ( ) ;
LLVM,NVPTX,529,return Expr;
LLVM,NVPTX,530,
LLVM,NVPTX,531,unsigned MappedVR = VI->second;
LLVM,NVPTX,532,
LLVM,NVPTX,533,if (isImageType
LLVM,NVPTX,534,
LLVM,NVPTX,535,const MachineBasicBlock * PMBB = * I ;
LLVM,NVPTX,536,
LLVM,NVPTX,537,
LLVM,NVPTX,538,
LLVM,NVPTX,539,case Instruction::AddrSpaceCast:
LLVM,NVPTX,540,"if ( OpNo == <NUM_LIT> && MO . isImm ( ) ) { lowerImageHandleSymbol ( MO . getImm ( ) , MCOp ) ; return true ; }"
LLVM,NVPTX,541,"For example, the next statement could be: ```"
LLVM,NVPTX,542,MCOp = GetSymbolRef(OutContext.getOrCreateSymbol(StringRef(SymNamePtr->c_str())));
LLVM,NVPTX,543,case MachineOperand::MO_Immediate: MCOp = MCOperand::createImm(MO.getImm()); break;
LLVM,NVPTX,544,case MachineOperand::MO_FPImmediate:
LLVM,NVPTX,545,if (MO.isReg() && MO.getReg() == NVPTX::ImageHandleReg) {
LLVM,NVPTX,546,
LLVM,NVPTX,547,O << ']' ;
LLVM,NVPTX,548,O << ExtraCode;
LLVM,NVPTX,549,"return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, O);"
LLVM,NVPTX,550,O << lead;
LLVM,NVPTX,551,"case MCExpr::Binary: {   const MCBinaryExpr &BE = cast<MCBinaryExpr>(Expr);   if (isa<MCConstantExpr>(BE.getLHS()) || isa<MCSymbolRefExpr>(BE.getLHS()) || isa<ISA_LIT>GenericMCSymbolRefExpr>(BE.getLHS())) {     printMCExpr(*BE.getLHS(), OS);   } else {     OS << '(';"
LLVM,NVPTX,552,
LLVM,NVPTX,553,if (MI->getOperand(opNum + <NUM_LIT>).isImm() && MI->getOperand(opNum + <NUM_LIT>).getImm() == <NUM_LIT>) return;
LLVM,NVPTX,554,O << DEPOTNAME << getFunctionNumber(MO.getReg());
LLVM,NVPTX,555,
LLVM,NVPTX,556,"O << ""Return value: "" << F->getReturnValue()->getType()->getAsString();`"
LLVM,NVPTX,557,llvm_unreachable(<STR_LIT>);
LLVM,NVPTX,558,if (const GlobalValue *GVar = dyn_cast<GlobalValue>(v)) {
LLVM,NVPTX,559,
LLVM,NVPTX,560,
LLVM,NVPTX,561,"fstr.getline(buff, <NUM_LIT>);"
LLVM,NVPTX,562,filenameMap[Filename] = i;
LLVM,NVPTX,563,
LLVM,NVPTX,564,nvptxSubtarget->setMachineFunction(F);
LLVM,NVPTX,565,const TargetRegisterClass * RC = TRI -> getRegClass ( i ) ;
LLVM,NVPTX,566,for (unsigned int i = <NUM_LIT>; i < numVRs; i++) {
LLVM,NVPTX,567,
LLVM,NVPTX,568,
LLVM,NVPTX,569,const BasicBlock * curBB = instr->getParent();
LLVM,NVPTX,570,const Function * callee = I->getCalledFunction();
LLVM,NVPTX,571,Visiting.erase(GV);
LLVM,NVPTX,572,
LLVM,NVPTX,573,
LLVM,NVPTX,574,return;
LLVM,NVPTX,575,
LLVM,NVPTX,576,GV.setName(cleanUpName(GV.getName()));
LLVM,NVPTX,577,ValidNameStream << C;
LLVM,NVPTX,578,return new <ISA_LIT>AssignValidGlobalNames();
LLVM,NVPTX,579,
LLVM,NVPTX,580,void AssignValidGlobalNames::runOnModule(Module &M) {
LLVM,NVPTX,581,void AssignValidGlobalNames::runOnModule(Module &M) {
LLVM,NVPTX,582,for (Function &F : M.functions())
LLVM,NVPTX,583,GV.setName(cleanUpName(GV.getName()));
LLVM,NVPTX,584,AU.setPreservesAll();
LLVM,NVPTX,585,
LLVM,NVPTX,586,"return ""MyPass"";"
LLVM,NVPTX,587,
LLVM,NVPTX,588,
LLVM,NVPTX,589,
LLVM,NVPTX,590,
LLVM,NVPTX,591,
LLVM,NVPTX,592,return false;
LLVM,NVPTX,593,hoistAddrSpaceCastFromGEP(GEP);
LLVM,NVPTX,594,"MI->setOperand(Idx, Cast->getOperand(<NUM_LIT>));"
LLVM,NVPTX,595,
LLVM,NVPTX,596,"NewGEPCE = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ;"
LLVM,NVPTX,597,if (Changed) return true;
LLVM,NVPTX,598,"if (I->getMetadata(""favor_non_generic"")) {"
LLVM,NVPTX,599,if (Depth >= MaxDepth) return false;
LLVM,NVPTX,600,if (Depth >= MaxDepth) return false;
LLVM,NVPTX,601,"Value *NewBC = new AddrSpaceCastInst(NewCast, BC->getType(), <STR_LIT>, BCI);"
LLVM,NVPTX,602,"Value * NewBC = new AddrSpaceCastInst(NewCast, BC->getType(), <STR_LIT>, BCI);"
LLVM,NVPTX,603,NewASC->takeName(GEP);
LLVM,NVPTX,604,"Constant *NewGEP = ConstantExpr::getGetElementPtr(GEP->getSourceElementType(), cast<Constant>(Cast->getOperand(<NUM_LIT>)), Indices, GEP->isInBounds());"
LLVM,NVPTX,605,"However, based on the names of the functions and variables, it is likely that the next statement will be a call to the `setOperand` function, passing in the result of the `dyn_cast` operation as the second argument. The `dyn_cast` operation is likely to return a"
LLVM,NVPTX,606,"NewASC = new AddrSpaceCastInst(NewGEP, GEP->getType(), <STR_LIT>, GEPI);"
LLVM,NVPTX,607,
LLVM,NVPTX,608,"return hoistAddrSpaceCastFromGEP(GEP, Depth);"
LLVM,NVPTX,609,"Value * NewBC = new AddrSpaceCastInst(Src, TypeOfNewCast, <STR_LIT>, BCI);"
LLVM,NVPTX,610,"NewASC = new AddrSpaceCastInst(NewGEP, GEP->getType(), <STR_LIT>, GEPI);"
LLVM,NVPTX,611,"NewASC = new AddrSpaceCastInst(NewGEP, GEP->getType(), <STR_LIT>, GEPI);"
LLVM,NVPTX,612,Value * Dest = Cast->getOperand(<NUM_LIT>);
LLVM,NVPTX,613,
LLVM,NVPTX,614,
LLVM,NVPTX,615,"MI->setOperand(Idx, ASC->getOperand(0));"
LLVM,NVPTX,616,Changed = true;
LLVM,NVPTX,617,
LLVM,NVPTX,618,
LLVM,NVPTX,619,Some possible next statements could include:
LLVM,NVPTX,620,Some possible next statements could include:
LLVM,NVPTX,621,"MI = BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(CvtaLocalOpcode), <STR_LIT>).addReg(<STR_LIT>);"
LLVM,NVPTX,622,
LLVM,NVPTX,623,"TargetFrameLowering::TargetFrameLowering(TargetFrameLowering::StackGrowsUp, <NUM_LIT>, <NUM_LIT>)"
LLVM,NVPTX,624,"TargetFrameLowering::TargetFrameLowering(TargetFrameLowering::StackGrowsUp, <NUM_LIT>, <NUM_LIT>)"
LLVM,NVPTX,625,MachineInstr *Instr = &*I;
LLVM,NVPTX,626,MI->setOpcode(<ISA_LIT>Instruction::Push);
LLVM,NVPTX,627,
LLVM,NVPTX,628,"MachineFrameInfo::getFrameIndexReference(MFI, FI, FrameReg);"
LLVM,NVPTX,629,
LLVM,NVPTX,630,
LLVM,NVPTX,631,
LLVM,NVPTX,632,
LLVM,NVPTX,633,"MI = BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode), <STR_LIT>).addReg(<STR_LIT>);"
LLVM,NVPTX,634,const MachineFrameInfo & MFI = MF.getFrameInfo();
LLVM,NVPTX,635,
LLVM,NVPTX,636,
LLVM,NVPTX,637,"MI = BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode), <STR_LIT>).addReg(<STR_LIT>);"
LLVM,NVPTX,638,
LLVM,NVPTX,639,
LLVM,NVPTX,640,
LLVM,NVPTX,641,Some possible next statements could include:
LLVM,NVPTX,642,Some possible next statements could include:
LLVM,NVPTX,643,
LLVM,NVPTX,644,
LLVM,NVPTX,645,
LLVM,NVPTX,646,MachineInstr *MI = *I;
LLVM,NVPTX,647,
LLVM,NVPTX,648,
LLVM,NVPTX,649,
LLVM,NVPTX,650,MBBI = MBB . end ( ) ;
LLVM,NVPTX,651,
LLVM,NVPTX,652,is64bit = STI.is64Bit();
LLVM,NVPTX,653,is64bit = STI.is64Bit();
LLVM,NVPTX,654,"for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {"
LLVM,NVPTX,655,"ParamTypes.push_back(PointerType::get(GVType->getElementType(), llvm::ADDRESS_SPACE_GENERIC));"
LLVM,NVPTX,656,ParamTypes.push_back(Type::getInt8Ty(Context));
LLVM,NVPTX,657,
LLVM,NVPTX,658,NewOperands.push_back(NewOperand);
LLVM,NVPTX,659,NewOperands.push_back(NewOperand);
LLVM,NVPTX,660,N->dropAllReferences();
LLVM,NVPTX,661,AU.setPreservesAll();
LLVM,NVPTX,662,AU.setPreservesAll();
LLVM,NVPTX,663,"return Builder . CreateBinOp ( Instruction :: BinaryOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ;"
LLVM,NVPTX,664,GVMap.clear();
LLVM,NVPTX,665,"CVTA = Builder.CreateBitCast(CVTA, DestTy, <STR_LIT>);"
LLVM,NVPTX,666,"CVTA = Builder.CreateBitCast(GV, ExtendedGVType.getType());"
LLVM,NVPTX,667,return NewOperands;
LLVM,NVPTX,668,N->dropAllReferences();`
LLVM,NVPTX,669,"for (auto I = GVMap.begin(), E = GVMap.end(); I != E; ++I) {"
LLVM,NVPTX,670,1. The outer `for` loop iterates over the functions in the module `M`.
LLVM,NVPTX,671,"for (auto I = GVMap.begin(), E = GVMap.end(); I != E; ++I) {"
LLVM,NVPTX,672,
LLVM,NVPTX,673,"NewValue = getOrInsertCVTA(M, F, I->second, Builder);"
LLVM,NVPTX,674,"NewValue = getOrInsertCVTA(M, F, I->second, Builder);"
LLVM,NVPTX,675,Here's a breakdown of the code:
LLVM,NVPTX,676,"NewValue = Builder.CreateInsertValue(NewValue, NewOperands[i], makeArrayRef(i));"
LLVM,NVPTX,677,VM.clear();
LLVM,NVPTX,678,"return Builder.CreateGetElementPtr(NewOperands[<NUM_LIT>], C->getIndices());"
LLVM,NVPTX,679,Based
LLVM,NVPTX,680,"Builder.CreateAlloca(GV->getType()->getElementType(), nullptr, GV->getName());"
LLVM,NVPTX,681,GVMap.clear();
LLVM,NVPTX,682,NewOperands.push_back(NewOperand);
LLVM,NVPTX,683,I->setAlignment(GV->getAlignment());
LLVM,NVPTX,684,ConstantToValueMap.clear();
LLVM,NVPTX,685,"DestTy = PointerType::get(GVType->getElementType(), llvm::ADDRESS_SPACE_GENERIC);"
LLVM,NVPTX,686,"ParamTypes.push_back(PointerType::get(GVType->getElementType(), llvm::ADDRESS_SPACE_GENERIC));"
LLVM,NVPTX,687,GVMap.erase(GV);
LLVM,NVPTX,688,I != E;
LLVM,NVPTX,689,ModulePass *llvm::createGenericToNVVMPass() {
LLVM,NVPTX,690,return new GenericToNVVM();
LLVM,NVPTX,691,virtual bool runOnModule(Module &M) {
LLVM,NVPTX,692,virtual bool runOnModule(Module &M) {
LLVM,NVPTX,693,AU.setPreservesAll();
LLVM,NVPTX,694,AU.setPreservesAll();
LLVM,NVPTX,695,GVMapTy::iterator I = GVMap.find(cast<GlobalVariable>(C));
LLVM,NVPTX,696,ConstantToValueMap[C] = NewValue;
LLVM,NVPTX,697,
LLVM,NVPTX,698,"NewValue = Builder.CreateInsertValue(NewValue, NewOperands[i], makeArrayRef(i));"
LLVM,NVPTX,699,GVMap.erase(I);
LLVM,NVPTX,700,
LLVM,NVPTX,701,return cleanupValue(EVI->getAggregateOperand());
LLVM,NVPTX,702,return new <ISA_LIT>ImageOptimizer();
LLVM,NVPTX,703,return new <ISA_LIT>ImageOptimizer();
LLVM,NVPTX,704,* `ISA_LIT` is a macro that expands to a string literal.
LLVM,NVPTX,705,* `ISA_LIT` is a macro that expands to a string literal.
LLVM,NVPTX,706,return true;
LLVM,NVPTX,707,return false;
LLVM,NVPTX,708,"replaceWith( &I, ConstantInt::getFalse(I.getContext()) );"
LLVM,NVPTX,709,
LLVM,NVPTX,710,Dest = BI->getSuccessor(1);
LLVM,NVPTX,711,"BranchInst::Create(Dest, BI);"
LLVM,NVPTX,712,InstrToDelete.push_back(BI);
LLVM,NVPTX,713,if (skipFunction(F)) return false;
LLVM,NVPTX,714,
LLVM,NVPTX,715,
LLVM,NVPTX,716,case <STR_LIT> : Changed |= replaceIsTypePSampler ( Instr ) ; break ;
LLVM,NVPTX,717,if (isAddressExpression(*V) && V->getType()->getPointerAddressSpace() == AddressSpace::ADDRESS_SPACE_GENERIC) {
LLVM,NVPTX,718,
LLVM,NVPTX,719,NewOperands.push_back(Operand);
LLVM,NVPTX,720,return NewGEP;
LLVM,NVPTX,721,"PostorderStack.push_back(std::make_pair(&I, false));"
LLVM,NVPTX,722,PostorderStack.push_back(PtrOperand);
LLVM,NVPTX,723,return new FunctionPass(new <ISA_LIT>InferAddressSpacesPass());
LLVM,NVPTX,724,"return SmallVector < Value * , <NUM_LIT> > ( IncomingValues . begin ( ) , IncomingValues . end ( ) ) ;"
LLVM,NVPTX,725,"return SmallVector < Value * , <NUM_LIT> > ( IncomingValues . begin ( ) , IncomingValues . end ( ) ) ;"
LLVM,NVPTX,726,Worklist.push_back(User);
LLVM,NVPTX,727,case Instruction::PHI:`
LLVM,NVPTX,728,return AS1 == AS2 ? AS1 : ( unsigned ) AddressSpace :: ADDRESS_SPACE_GENERIC ;
LLVM,NVPTX,729,
LLVM,NVPTX,730,
LLVM,NVPTX,731,return UndefValue::get(Operand->getType()->getPointerElementType()->getPointerTo(NewAddrSpace));
LLVM,NVPTX,732,"I->replaceUsesOfWith(V, NewV);"
LLVM,NVPTX,733,for (auto &value : Postorder) {
LLVM,NVPTX,734,ValueToAddrSpaceMapTy InferredAddrSpace;
LLVM,NVPTX,735,InferredAddrSpace.count(PtrOperand) = 0;
LLVM,NVPTX,736,"MCInstPrinter::MCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {}"
LLVM,NVPTX,737,"MCInstPrinter::MCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {}"
LLVM,NVPTX,738,
LLVM,NVPTX,739,"if ( ! strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm ) O << <STR_LIT> ; }"
LLVM,NVPTX,740,O << Imm;
LLVM,NVPTX,741,
LLVM,NVPTX,742,O << markup(<STR_LIT>) << formatImm(Op.getImm()) << markup(<STR_LIT>);
LLVM,NVPTX,743,OS << <STR_LIT> ; break ;
LLVM,NVPTX,744,
LLVM,NVPTX,745,"if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { if ( Imm & <STR_LIT> :: FTZ_FLAG ) O << <STR_LIT> ; }"
LLVM,NVPTX,746,
LLVM,NVPTX,747,case <NUM_LIT> : OS << <STR_LIT> ; break ;
LLVM,NVPTX,748,OS << VReg;
LLVM,NVPTX,749,setAvailableFeatures(STI.getFeatureBits());
LLVM,NVPTX,750,
LLVM,NVPTX,751,case <STR_LIT> :: RMI : O << <STR_LIT> ; break ;
LLVM,NVPTX,752,O << <STR_LIT>;
LLVM,NVPTX,753,"printInstruction(MI, OS);"
LLVM,NVPTX,754,
LLVM,NVPTX,755,
LLVM,NVPTX,756,O << <STR_LIT> ;
LLVM,NVPTX,757,
LLVM,NVPTX,758,
LLVM,NVPTX,759,return RegInfo;
LLVM,NVPTX,760,
LLVM,NVPTX,761,
LLVM,NVPTX,762,RegInfo = new RegInfo(*TM.getSubtargetImpl());
LLVM,NVPTX,763,RegInfo = new RegInfo(*TM.getSubtargetImpl());
LLVM,NVPTX,764,
LLVM,NVPTX,765,llvm_unreachable(<STR_LIT>)
LLVM,NVPTX,766,Op = ( SrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ;
LLVM,NVPTX,767,
LLVM,NVPTX,768,"BuildMI(&MBB, DL, get(""<STR_LIT>"")).add(Cond[<NUM_LIT>]).addMBB(TBB);"
LLVM,NVPTX,769,"BuildMI(&MBB, DL, get(<STR_LIT>)).add(Cond[<NUM_LIT>]).addMBB(TBB);"
LLVM,NVPTX,770,InstrInfo::InstrInfo() : RegInfo() {
LLVM,NVPTX,771,InstrInfo::InstrInfo() : RegInfo() {
LLVM,NVPTX,772,
LLVM,NVPTX,773,
LLVM,NVPTX,774,Here is a
LLVM,NVPTX,775,"BuildMI(&MBB, DL, get(<STR_LIT>)).addReg(Cond[<NUM_LIT>].getReg()).addMBB(TBB);"
LLVM,NVPTX,776,
LLVM,NVPTX,777,
LLVM,NVPTX,778,I = MBB.end();
LLVM,NVPTX,779,I = MBB.end()
LLVM,NVPTX,780,if ( ! FBB ) {
LLVM,NVPTX,781,
LLVM,NVPTX,782,
LLVM,NVPTX,783,
LLVM,NVPTX,784,
LLVM,NVPTX,785,if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I)) return true;
LLVM,NVPTX,786,
LLVM,NVPTX,787,
LLVM,NVPTX,788,
LLVM,NVPTX,789,
LLVM,NVPTX,790,
LLVM,NVPTX,791,
LLVM,NVPTX,792,assert(TBB && FBB);
LLVM,NVPTX,793,TBB = SecondLastInst.getOperand(<NUM_LIT>).getMBB();
LLVM,NVPTX,794,TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ;
LLVM,NVPTX,795,
LLVM,NVPTX,796,
LLVM,NVPTX,797,TBB = SecondLastInst->getOperand(<NUM_LIT>).getMBB();
LLVM,NVPTX,798,return false;
LLVM,NVPTX,799,"BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;"
LLVM,NVPTX,800,unsigned getLdStCodeAddrSpace ( const MachineInstr & MI ) const { return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; }
LLVM,NVPTX,801,
LLVM,NVPTX,802,
LLVM,NVPTX,803,"BuildMI(&MBB, DL, get(""<STR_LIT>"")).addReg(Cond[<NUM_LIT>].getReg()).addMBB(TBB);"
LLVM,NVPTX,804,
LLVM,NVPTX,805,isLoad = (TSFlags == <NUM_LIT>);
LLVM,NVPTX,806,return isLoad;
LLVM,NVPTX,807,dest.setIsMove(isMove);
LLVM,NVPTX,808,
LLVM,NVPTX,809,if (isStore) AddrSpace = getLdStCodeAddrSpace(MI);
LLVM,NVPTX,810,
LLVM,NVPTX,811,
LLVM,NVPTX,812,I = MBB.end();
LLVM,NVPTX,813,
LLVM,NVPTX,814,
LLVM,NVPTX,815,
LLVM,NVPTX,816,"return ""MyPass"";"
LLVM,NVPTX,817,return SelectionDAGISel::runOnMachineFunction(MF);
LLVM,NVPTX,818,
LLVM,NVPTX,819,"return TL -> allowFMA ( * MF , OptLevel ) ;"
LLVM,NVPTX,820,
LLVM,NVPTX,821,
LLVM,NVPTX,822,Objs.clear();
LLVM,NVPTX,823,
LLVM,NVPTX,824,return false;
LLVM,NVPTX,825,
LLVM,NVPTX,826,return <STR_LIT> :: LOCAL;
LLVM,NVPTX,827,
LLVM,NVPTX,828,
LLVM,NVPTX,829,
LLVM,NVPTX,830,
LLVM,NVPTX,831,"return SDValue(Imm, DL);"
LLVM,NVPTX,832,"return ""getPassName"";"
LLVM,NVPTX,833,
LLVM,NVPTX,834,case <STR_LIT> : return CmpMode :: GT ;
LLVM,NVPTX,835,Here is an example of what the next statement might look like:
LLVM,NVPTX,836,Subtarget = &MF.getSubtarget<ISA_LIT>Subtarget>();
LLVM,NVPTX,837,Some possible next statements could be:
LLVM,NVPTX,838,
LLVM,NVPTX,839,
LLVM,NVPTX,840,"Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);"
LLVM,NVPTX,841,if ( CN->getOpcode() == <STR_LIT> ) {
LLVM,NVPTX,842,
LLVM,NVPTX,843,if (Addr.getOpcode() == <STR_LIT>) {
LLVM,NVPTX,844,if (Addr.getOpcode() == <STR_LIT>) {
LLVM,NVPTX,845,case ADDRESS_SPACE_SHARED :
LLVM,NVPTX,846,return false;
LLVM,NVPTX,847,
LLVM,NVPTX,848,
LLVM,NVPTX,849,
LLVM,NVPTX,850,Here are a few possibilities:
LLVM,NVPTX,851,Here are a few possibilities:
LLVM,NVPTX,852,
LLVM,NVPTX,853,
LLVM,NVPTX,854,
LLVM,NVPTX,855,
LLVM,NVPTX,856,if ( ! <ISA_LIT>LD ) return false;
LLVM,NVPTX,857,VTs.push_back(MemVT.getSimpleVT().SimpleTy);
LLVM,NVPTX,858,"SDValue Ops[ ] = { Value, getI32Imm(isVolatile, dl), getI32Imm(CodeAddrSpace, dl), getI32Imm(vecType, dl), getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), Base, Offset, Chain };"
LLVM,NVPTX,859,"SDVTList RetVTs = CurDAG->getVTList(<STR_LIT>, <STR_LIT>);"
LLVM,NVPTX,860,
LLVM,NVPTX,861,return Subtarget->getTargetLowering()->usePrecSqrtF32(value);
LLVM,NVPTX,862,
LLVM,NVPTX,863,
LLVM,NVPTX,864,Src = mN -> getSrcValue ( ) ;
LLVM,NVPTX,865,case llvm::ADDRESS_SPACE_PARAM: return <STR_LIT>::PARAM;
LLVM,NVPTX,866,return <STR_LIT> :: GENERIC;
LLVM,NVPTX,867,doFMAF64AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF64 ( ) && ( FMAContractLevel == <NUM_LIT> ) ;
LLVM,NVPTX,868,
LLVM,NVPTX,869,if (Addr.getOpcode() == <STR_LIT> || Addr.getOpcode() == <STR_LIT>) return false;
LLVM,NVPTX,870,"Offset = CurDAG->getTargetConstant(<NUM_LIT>, mvt);"
LLVM,NVPTX,871,
LLVM,NVPTX,872,
LLVM,NVPTX,873,
LLVM,NVPTX,874,Opcode = <STR_LIT> ;
LLVM,NVPTX,875,
LLVM,NVPTX,876,if (A && A->onlyReadsMemory() && A->hasNoAliasAttr()) {
LLVM,NVPTX,877,
LLVM,NVPTX,878,if ( !<ISA_LIT>LD ) return false;
LLVM,NVPTX,879,"case <STR_LIT> : Opcode = pickOpcodeForVT ( EltVT . getSimpleVT ( ) . SimpleTy , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; break ;"
LLVM,NVPTX,880,"SDValue CvtNone = CurDAG->getTargetConstant(<STR_LIT>::NONE, DL, <STR_LIT>)"
LLVM,NVPTX,881,"Ops.push_back(CurDAG->getTargetConstant(ParamVal, DL, <STR_LIT>));"
LLVM,NVPTX,882,if (PointerSize == <NUM_LIT>) {
LLVM,NVPTX,883,"case <STR_LIT> : Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, <STR_LIT>, <STR_LIT>, <STR_LIT>, None, <STR_LIT>, <STR_LIT>, <STR_LIT>, None); break;"
LLVM,NVPTX,884,
LLVM,NVPTX,885,return <NUM_LIT>;
LLVM,NVPTX,886,doMulWide = ( OptLevel > <NUM_LIT> ) ;
LLVM,NVPTX,887,doFMAF32AGG = ( OptLevel > <NUM_LIT> ) && Subtarget . hasFMAF32 ( ) && ( FMAContractLevel == <NUM_LIT> ) ;
LLVM,NVPTX,888,
LLVM,NVPTX,889,case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT
LLVM,NVPTX,890,return false;
LLVM,NVPTX,891,"return ( F -> getAttributes ( ) . getAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) ;"
LLVM,NVPTX,892,return UsePrecSqrtF32;
LLVM,NVPTX,893,return (PT->getAddressSpace() == spN);
LLVM,NVPTX,894,return <STR_LIT> :: GENERIC;
LLVM,NVPTX,895,Val = AndLHS;
LLVM,NVPTX,896,
LLVM,NVPTX,897,
LLVM,NVPTX,898,return nullptr;
LLVM,NVPTX,899,
LLVM,NVPTX,900,"Based on the structure of the switch statement, it is likely that the next statement will be a case statement that handles a specific opcode. However,"
LLVM,NVPTX,901,case <NUM_LIT> : switch ( Mem -> getMemoryVT ( ) . getSimpleVT ( ) . SimpleTy ) { default : return nullptr ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR
LLVM,NVPTX,902,"return CurDAG->getMachineNode(<STR_LIT>, SDLoc(N), <STR_LIT>, GlobalVal);"
LLVM,NVPTX,903,"return CurDAG->getMachineNode(<STR_LIT>, SDLoc(N), <STR_LIT>, GlobalVal);"
LLVM,NVPTX,904,return FtzEnabled;
LLVM,NVPTX,905,return false;
LLVM,NVPTX,906,
LLVM,NVPTX,907,
LLVM,NVPTX,908,
LLVM,NVPTX,909,Src = mN->getMemOperand()->getValue(); } else if (MemSDNode* mN = dyn_cast<MemIntrinsicSDNode>(N)) { if (spN == <NUM_LIT> && mN->getMemOperand()->getPseudoValue()) return true;`
LLVM,NVPTX,910,return <STR_LIT> :: GENERIC ;
LLVM,NVPTX,911,case llvm::ADDRESS_SPACE_GLOBAL: return <STR_LIT>::GLOBAL;
LLVM,NVPTX,912,
LLVM,NVPTX,913,Opc = Subtarget.is64Bit() ? <STR_LIT> : <STR_LIT>;
LLVM,NVPTX,914,if (isMask_64(MaskVal)) {
LLVM,NVPTX,915,switch (SourceVT) {
LLVM,NVPTX,916,* `SDValue Chain = N -> getOperand ( <NUM_LIT> ) ;`: This line retrieves the operand at index `<NUM_LIT>` from the node `N` and stores it in the variable `Chain`.
LLVM,NVPTX,917,
LLVM,NVPTX,918,case <STR_LIT> : Opcode = <STR_LIT> ; break ;
LLVM,NVPTX,919,if (Src && isa<GlobalValue>(Src)) {
LLVM,NVPTX,920,case <ADDRESS_SPACE_LITERAL>:
LLVM,NVPTX,921,allowFMA = ( FMAContractLevel >= <NUM_LIT> ) || UseFMADInstruction;
LLVM,NVPTX,922,
LLVM,NVPTX,923,"Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);"
LLVM,NVPTX,924,"if ( SelectDirectAddr ( Addr . getOperand ( <NUM_LIT> ) , Addr ) ) {"
LLVM,NVPTX,925,Base = Addr.getOperand(0);
LLVM,NVPTX,926,"if ( SelectDirectAddr(base, Base) ) {"
LLVM,NVPTX,927,"return ( SelectDirectAddr ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , Address ) ) ;"
LLVM,NVPTX,928,
LLVM,NVPTX,929,"Retval = CurDAG->getTargetConstant(<NUM_LIT>, <STR_LIT>);"
LLVM,NVPTX,930,case <NUM_LIT> : switch ( MemVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ;
LLVM,NVPTX,931,
LLVM,NVPTX,932,switch (PT->getAddressSpace()) {
LLVM,NVPTX,933,return <STR_LIT> :: PARAM;
LLVM,NVPTX,934,
LLVM,NVPTX,935,
LLVM,NVPTX,936,"LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);"
LLVM,NVPTX,937,switch (TargetVT) {
LLVM,NVPTX,938,if ( Subtarget . is64Bit ( ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_
LLVM,NVPTX,939,"DAGToDAGISel(tm, OptLevel)"
LLVM,NVPTX,940,case ADDRESS_SPACE_GLOBAL : Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; break ;
LLVM,NVPTX,941,Opc = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;
LLVM,NVPTX,942,"SDValue Ops[ ] = { getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( fromType ) , getI32Imm ( fromTypeWidth ) , Base , Offset , Chain } ;"
LLVM,NVPTX,943,
LLVM,NVPTX,944,
LLVM,NVPTX,945,
LLVM,NVPTX,946,
LLVM,NVPTX,947,
LLVM,NVPTX,948,
LLVM,NVPTX,949,Variant = WMMA_VARIANT_ARI64_STRIDE;
LLVM,NVPTX,950,Here are some possible next statements:
LLVM,NVPTX,951,if (ValueConst->getZExtValue() == 0) {
LLVM,NVPTX,952,
LLVM,NVPTX,953,
LLVM,NVPTX,954,
LLVM,NVPTX,955,Ops.push_back(Chain);
LLVM,NVPTX,956,return true;
LLVM,NVPTX,957,if (N->isInvariant()) return true;
LLVM,NVPTX,958,for (auto &obj : Objs) {
LLVM,NVPTX,959,
LLVM,NVPTX,960,"Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, <STR_LIT>));"
LLVM,NVPTX,961,
LLVM,NVPTX,962,
LLVM,NVPTX,963,case <STR_LIT> : switch ( RetVT . getSimpleVT ( ) . SimpleTy ) { default : return NULL ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT>
LLVM,NVPTX,964,
LLVM,NVPTX,965,for (auto &Obj : Objs) {
LLVM,NVPTX,966,return SDValue(Imm);
LLVM,NVPTX,967,return SDValue(Imm);
LLVM,NVPTX,968,"Secondly, the code is using a `SDValue` object to represent a value in the machine language. The `SDValue"
LLVM,NVPTX,969,
LLVM,NVPTX,970,return allowUnsafeFPMath(MF);
LLVM,NVPTX,971,return true;
LLVM,NVPTX,972,ValueVTs[Idx] = ValueVTs[Idx + NumElts - 1];
LLVM,NVPTX,973,EltVT = <STR_LIT>;
LLVM,NVPTX,974,ValueVTs.push_back(EltVT);
LLVM,NVPTX,975,
LLVM,NVPTX,976,CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ;
LLVM,NVPTX,977,
LLVM,NVPTX,978,return UsePrecDivF32(getTargetMachine().Options.UnsafeFPMath
LLVM,NVPTX,979,return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;
LLVM,NVPTX,980,return TypeSplitVector;
LLVM,NVPTX,981,"SDValue Res = DAG.getNode(ISD::FP_TO_FP16, DL, VT, Operand);"
LLVM,NVPTX,982,
LLVM,NVPTX,983,Type * PTy = dyn_cast < PointerType > ( Ty ) ;
LLVM,NVPTX,984,if (STy->isLiteral()) return false;
LLVM,NVPTX,985,
LLVM,NVPTX,986,
LLVM,NVPTX,987,"If any of these conditions are false, the"
LLVM,NVPTX,988,"SDValue Const = DAG.getConstant(E1.zext(<NUM_LIT>).shl(<NUM_LIT>)|E0.zext(<NUM_LIT>), SDLoc(Op), <STR_LIT>);"
LLVM,NVPTX,989,"Ops.push_back(DAG.getNode(<STR_LIT>, dl, EltVT, SubOp, DAG.getIntPtrConstant(j, dl)));"
LLVM,NVPTX,990,"SDValue E0 = DAG . getNode ( <STR_LIT> , dl , EltVT , Vector , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;"
LLVM,NVPTX,991,
LLVM,NVPTX,992,return SDValue ( ) ;
LLVM,NVPTX,993,assert(LD->getExtensionType() == <STR_LIT>);
LLVM,NVPTX,994,
LLVM,NVPTX,995,
LLVM,NVPTX,996,"if (VT.isVector()) return LowerSTOREVector(Op, DAG);"
LLVM,NVPTX,997,
LLVM,NVPTX,998,Opcode = <STR_LIT>;
LLVM,NVPTX,999,Ops.push_back(N->getOperand(<NUM_LIT>));
LLVM,NVPTX,1000,
LLVM,NVPTX,1001,
LLVM,NVPTX,1002,if (Val->getOpcode() == <STR_LIT> || Val->getOpcode() == <STR_LIT>) {
LLVM,NVPTX,1003,AddTo = true;
LLVM,NVPTX,1004,
LLVM,NVPTX,1005,
LLVM,NVPTX,1006,const SDValue & Num = N -> getOperand ( <NUM_LIT> ) ;
LLVM,NVPTX,1007,
LLVM,NVPTX,1008,
LLVM,NVPTX,1009,"if ( SDValue Ret = TryMULWIDECombine ( N , DCI ) ) return Ret ;"
LLVM,NVPTX,1010,"SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps, MemSD->getMemoryVT(), MemSD->getMemOperand());"
LLVM,NVPTX,1011,"OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));"
LLVM,NVPTX,1012,return getDataSection();
LLVM,NVPTX,1013,return F->getFnAttribute(<STR_LIT>)->getValueAsString() == <STR_LIT>;
LLVM,NVPTX,1014,return F->getFnAttribute(<STR_LIT>)->getValueAsString() == <STR_LIT>;
LLVM,NVPTX,1015,return UsePrecSqrtF32;
LLVM,NVPTX,1016,return UsePrecSqrtF32;
LLVM,NVPTX,1017,
LLVM,NVPTX,1018,
LLVM,NVPTX,1019,"if (Val.equals(""<STR_LIT>"")) {"
LLVM,NVPTX,1020,ValueVTs.push_back(VT);
LLVM,NVPTX,1021,ValueVTs.push_back(EVT(<STR_LIT>));
LLVM,NVPTX,1022,"if (getAlign(*cast<CallInst>(CalleeI), Idx, Align)) return Align;"
LLVM,NVPTX,1023,if (isa < ConstantExpr > (CalleeV)) {
LLVM,NVPTX,1024,
LLVM,NVPTX,1025,return TypeSplitVector;
LLVM,NVPTX,1026,return false;
LLVM,NVPTX,1027,
LLVM,NVPTX,1028,"if (VT == <STR_LIT>) return LowerFROUND32(Op, DAG);"
LLVM,NVPTX,1029,"RoundedA = DAG.getNode(<STR_LIT>, SL, VT, IsLarge, A, RoundedA);"
LLVM,NVPTX,1030,"SDValue Result = DAG.getNode(ISD::FP_ROUND, SL, VT, AbsA, DAG.getConstant(0, VT));"
LLVM,NVPTX,1031,
LLVM,NVPTX,1032,
LLVM,NVPTX,1033,
LLVM,NVPTX,1034,LoadSDNode * Load = cast < LoadSDNode > ( Op ) ;
LLVM,NVPTX,1035,"if (Op.getValueType() == <STR_LIT>) return LowerLOADi1(Op, DAG);"
LLVM,NVPTX,1036,
LLVM,NVPTX,1037,case <NUM_LIT>:
LLVM,NVPTX,1038,"StoreOperands.push_back(DAG.getNode(ISD::STORE, dl, RetTy, Chain, DAG.getConstant(Offsets[i], dl, RetTy), StoreOperands));"
LLVM,NVPTX,1039,"if (VT.isVector()) return LowerSTOREVector(Op, DAG);"
LLVM,NVPTX,1040,return F.getFnAttribute(<STR_LIT>).getValueAsString() == <STR_LIT>;
LLVM,NVPTX,1041,return false;
LLVM,NVPTX,1042,
LLVM,NVPTX,1043,
LLVM,NVPTX,1044,
LLVM,NVPTX,1045,return FMAContractLevelOpt > <NUM_LIT>;
LLVM,NVPTX,1046,
LLVM,NVPTX,1047,
LLVM,NVPTX,1048,IsSigned = (LHSSign == Signed);
LLVM,NVPTX,1049,ValueVTs.push_back(VT);
LLVM,NVPTX,1050,CalleeV = cast < ConstantExpr > ( CalleeV ) -> getOperand ( <NUM_LIT> ) ;
LLVM,NVPTX,1051,return ConstraintType::Integer;
LLVM,NVPTX,1052,ParamSym = ParamStr.str();
LLVM,NVPTX,1053,
LLVM,NVPTX,1054,return TypeSplitVector;
LLVM,NVPTX,1055,return TypeSplitVector;
LLVM,NVPTX,1056,O << <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,1057,
LLVM,NVPTX,1058,"return std::find(std::begin(specialTypes), std::end(specialTypes), TypeName) != std::end(specialTypes);"
LLVM,NVPTX,1059,if (TypeName == <STR_LIT>) return false;
LLVM,NVPTX,1060,
LLVM,NVPTX,1061,S = Signed;
LLVM,NVPTX,1062,
LLVM,NVPTX,1063,
LLVM,NVPTX,1064,Constraint.length( ) > <NUM_LIT>
LLVM,NVPTX,1065,"return DAG.getNode(<STR_LIT>, dl, Node->getValueType(<NUM_LIT>), Ops);"
LLVM,NVPTX,1066,"Ops.push_back(LowerOperand(Op.getOperand(i), DAG));"
LLVM,NVPTX,1067,
LLVM,NVPTX,1068,"return LowerLOADi1(Op, DAG);"
LLVM,NVPTX,1069,
LLVM,NVPTX,1070,
LLVM,NVPTX,1071,
LLVM,NVPTX,1072,
LLVM,NVPTX,1073,
LLVM,NVPTX,1074,"SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ;"
LLVM,NVPTX,1075,"SDValue Result = DAG.getNode(<OPC>, dl, VT, Ops);"
LLVM,NVPTX,1076,
LLVM,NVPTX,1077,
LLVM,NVPTX,1078,Some possible next statements could include:
LLVM,NVPTX,1079,Ops.push_back(ExtVal);
LLVM,NVPTX,1080,Opcode = <STR_LIT>;
LLVM,NVPTX,1081,return Result;
LLVM,NVPTX,1082,
LLVM,NVPTX,1083,
LLVM,NVPTX,1084,
LLVM,NVPTX,1085,if (MemVT == <NUM_LIT>) {
LLVM,NVPTX,1086,
LLVM,NVPTX,1087,
LLVM,NVPTX,1088,"SDValue Ret = TryMULWIDECombine(N, DCI);"
LLVM,NVPTX,1089,IntrinsicId = IsMax ? <STR_LIT> : <STR_LIT>;
LLVM,NVPTX,1090,return Ret.getNode();
LLVM,NVPTX,1091,return Ret.getNode();
LLVM,NVPTX,1092,OtherOps . push_back ( Chain ) ;
LLVM,NVPTX,1093,"SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;"
LLVM,NVPTX,1094,
LLVM,NVPTX,1095,Here are a few possibilities for what the next statement could be:
LLVM,NVPTX,1096,if ( MulType == <STR_LIT> ) { DemotedVT = <STR_LIT> ; } else { DemotedVT = <STR_LIT> ; }
LLVM,NVPTX,1097,DemotedVT = DCI.DAG.getVT(MulType.getSizeInBits());
LLVM,NVPTX,1098,
LLVM,NVPTX,1099,
LLVM,NVPTX,1100,
LLVM,NVPTX,1101,"return <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ;"
LLVM,NVPTX,1102,"return <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ;"
LLVM,NVPTX,1103,
LLVM,NVPTX,1104,ValueVTs.push_back(EVT(<STR_LIT>));
LLVM,NVPTX,1105,
LLVM,NVPTX,1106,O << <STR_LIT> << align << <STR_LIT> ;
LLVM,NVPTX,1107,for (unsigned j = Idx + 1; j < Idx + NumElts; ++j) {
LLVM,NVPTX,1108,"LoadInst * Load = CreateLoad(Ty, Ptr, align"
LLVM,NVPTX,1109,O << <STR_LIT> ;
LLVM,NVPTX,1110,return MF.getDenormalMode(APFloat::IEEEsingle()) == DenormalMode::PreserveSign;
LLVM,NVPTX,1111,return FtzEnabled;
LLVM,NVPTX,1112,return MF . getDenormalMode ( APFloat :: IEEEsingle ( ) ) == DenormalMode :: PreserveSign ;
LLVM,NVPTX,1113,
LLVM,NVPTX,1114,O << <STR_LIT> ;
LLVM,NVPTX,1115,
LLVM,NVPTX,1116,"return std::make_pair(<NUM_LIT>, &<STR_LIT>);"
LLVM,NVPTX,1117,
LLVM,NVPTX,1118,Info.opc = <STR_LIT>;
LLVM,NVPTX,1119,
LLVM,NVPTX,1120,"const std::string TypeName = STy ? STy->getName() : ""<unknown>"";"
LLVM,NVPTX,1121,"Constraint = Constraint.substr(0, <NUM_LIT>);"
LLVM,NVPTX,1122,
LLVM,NVPTX,1123,
LLVM,NVPTX,1124,j = 0;
LLVM,NVPTX,1125,"SDValue arg = DAG . getNode ( <STR_LIT> , dl , tmpvt , getParamSymbol ( DAG , idx , tmpvt ) ) ;"
LLVM,NVPTX,1126,"return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Op ) ;"
LLVM,NVPTX,1127,
LLVM,NVPTX,1128,"return LowerCONCAT_VECTORS ( Op , DAG ) ;"
LLVM,NVPTX,1129,
LLVM,NVPTX,1130,LoadSDNode * Load = cast < LoadSDNode > ( Op ) ;
LLVM,NVPTX,1131,
LLVM,NVPTX,1132,"if (VT == <STR_LIT> && !allowsMemoryAccess(DAG.getContext(), DAG.getDataLayout(), VT, *Store->getMemOperand())) return expandUnalignedStore(Store, DAG);"
LLVM,NVPTX,1133,
LLVM,NVPTX,1134,const Function & F = MF.getFunction();
LLVM,NVPTX,1135,if (DirectCallee) {
LLVM,NVPTX,1136,
LLVM,NVPTX,1137,O << <STR_LIT> << (retAlignment ? retAlignment->value() : <NUM_LIT>) << <STR_LIT> << DL.getTypeAllocSize(retTy) << <STR_LIT>;
LLVM,NVPTX,1138,return false;
LLVM,NVPTX,1139,
LLVM,NVPTX,1140,if (PTy->getPointerElementType() != specialTypes[0] && PTy->getPointerElementType() != specialTypes[1] && PTy->getPointerElementType() != specialTypes[2]) return false;
LLVM,NVPTX,1141,
LLVM,NVPTX,1142,
LLVM,NVPTX,1143,
LLVM,NVPTX,1144,StoreOperands.push_back(RetVal);
LLVM,NVPTX,1145,if (opIsLive) { ... }
LLVM,NVPTX,1146,if (opIsLive) {
LLVM,NVPTX,1147,ScalarRes.push_back(E0); ScalarRes.push_back(E1);
LLVM,NVPTX,1148,if (Val.isIntN(OptSize)) { return true; }
LLVM,NVPTX,1149,for (unsigned i = 0; i < TempVTs.size(); ++i) {
LLVM,NVPTX,1150,DirectCallee = CalleeV;
LLVM,NVPTX,1151,
LLVM,NVPTX,1152,return TargetLowering :: getConstraintType ( Constraint ) ;
LLVM,NVPTX,1153,"case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,NVPTX,1154,return LHSTy.getScalarShiftAmountTy();
LLVM,NVPTX,1155,
LLVM,NVPTX,1156,
LLVM,NVPTX,1157,if (STy && STy->isOpaque()) return false;
LLVM,NVPTX,1158,"const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : ""<STR_LIT>"";"
LLVM,NVPTX,1159,
LLVM,NVPTX,1160,return true;
LLVM,NVPTX,1161,"Ops.push_back(LowerOperand(Op.getOperand(i), DAG));"
LLVM,NVPTX,1162,"Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());"
LLVM,NVPTX,1163,"Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());"
LLVM,NVPTX,1164,Ops.push_back(StoreVal);
LLVM,NVPTX,1165,"SDValue Lo = DAG.getNode(<STR_LIT>, dl, VT, ShOpLo, ShAmt);"
LLVM,NVPTX,1166,"SDValue TrueVal = DAG.getNode(<STR_LIT>, dl, VT, Tmp1, Tmp2);"
LLVM,NVPTX,1167,"SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ;"
LLVM,NVPTX,1168,"SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ;"
LLVM,NVPTX,1169,Ops.push_back(N->getOperand(i));
LLVM,NVPTX,1170,SDValue LoadChain = NewLD . getValue ( NumElts ) ;
LLVM,NVPTX,1171,ScalarRes.push_back(Res);
LLVM,NVPTX,1172,if (ShlRHS->getAPIntValue() == 0) {
LLVM,NVPTX,1173,DemotedVT = <STR_LIT>;
LLVM,NVPTX,1174,
LLVM,NVPTX,1175,delete DwarfRangesSection;
LLVM,NVPTX,1176,O << <STR_LIT> << sz << <STR_LIT>;
LLVM,NVPTX,1177,O << <STR_LIT> << sz << <STR_LIT>;
LLVM,NVPTX,1178,
LLVM,NVPTX,1179,"case <STR_LIT> : return PerformORCombine ( N , DCI ) ;"
LLVM,NVPTX,1180,NeedTrunc = true;
LLVM,NVPTX,1181,
LLVM,NVPTX,1182,
LLVM,NVPTX,1183,
LLVM,NVPTX,1184,
LLVM,NVPTX,1185,ValueVTs.push_back(VT.getVectorElementType());
LLVM,NVPTX,1186,ValueVTs.push_back(VT.getVectorElementType());
LLVM,NVPTX,1187,"if ( !llvm::getAlign(*(CS->getCalledFunction()), Idx, align) ) align = TD->getABITypeAlignment(Ty);"
LLVM,NVPTX,1188,
LLVM,NVPTX,1189,
LLVM,NVPTX,1190,"case 'd' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;"
LLVM,NVPTX,1191,
LLVM,NVPTX,1192,
LLVM,NVPTX,1193,
LLVM,NVPTX,1194,* `SDNode * Node = Op . getNode ( ) ;`: This line gets a pointer to the current node in the DAG.
LLVM,NVPTX,1195,
LLVM,NVPTX,1196,
LLVM,NVPTX,1197,
LLVM,NVPTX,1198,Ops.push_back(N->getOperand(<NUM_LIT>));
LLVM,NVPTX,1199,
LLVM,NVPTX,1200,ScalarRes.push_back(Res);
LLVM,NVPTX,1201,OtherOps.push_back(N->getOperand(i));
LLVM,NVPTX,1202,
LLVM,NVPTX,1203,return VT == <STR_LIT>;
LLVM,NVPTX,1204,
LLVM,NVPTX,1205,
LLVM,NVPTX,1206,return <STR_LIT>;
LLVM,NVPTX,1207,
LLVM,NVPTX,1208,
LLVM,NVPTX,1209,"After the assertion, the function is retrieving the value type and size in bits of the ""Op"" object, and then retr"
LLVM,NVPTX,1210,
LLVM,NVPTX,1211,return SDValue ( ) ;
LLVM,NVPTX,1212,
LLVM,NVPTX,1213,"However, based on the syntax and the fact that the code is using a `switch` statement, it is likely that the next statement will be one of the following:"
LLVM,NVPTX,1214,
LLVM,NVPTX,1215,SDValue LoadChain = NewLD.getValue(NumElts);
LLVM,NVPTX,1216,O << <STR_LIT> << sz << <STR_LIT> ;
LLVM,NVPTX,1217,
LLVM,NVPTX,1218,
LLVM,NVPTX,1219,O << <STR_LIT> << retAlignment << <STR_LIT> << totalsz << <STR_LIT> ;
LLVM,NVPTX,1220,
LLVM,NVPTX,1221,for (unsigned i = 0; i < Outs.size(); i++) {
LLVM,NVPTX,1222,tmpval = theVal[j];
LLVM,NVPTX,1223,O << <STR_LIT> << Outs[OIdx].Flags.getByValIndex() << <STR_LIT>;
LLVM,NVPTX,1224,
LLVM,NVPTX,1225,
LLVM,NVPTX,1226,"return LowerSTOREi1 ( Op , DAG ) ;"
LLVM,NVPTX,1227,"Since the `switch` block does not have a `break` statement after each case, it is possible that the function will continue to"
LLVM,NVPTX,1228,return getInlineAsmMemConstraint(ConstraintCode);
LLVM,NVPTX,1229,opIsLive = true;
LLVM,NVPTX,1230,
LLVM,NVPTX,1231,return false;
LLVM,NVPTX,1232,const Type * PTy = dyn_cast < PointerType > ( Ty ) ;
LLVM,NVPTX,1233,"SDValue localcopy = DAG . getFrameIndex ( MF . getFrameInfo ( ) -> CreateStackObject ( totalsize / <NUM_LIT> , <NUM_LIT> , false ) , getPointerTy ( ) ) ;"
LLVM,NVPTX,1234,"SDValue result = DAG.getNode(<STR_LIT>, dl, <STR_LIT>, newLD);"
LLVM,NVPTX,1235,"SDValue newLD = DAG.getLoad(<STR_LIT>, dl, LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(), LD->getAlignment());"
LLVM,NVPTX,1236,
LLVM,NVPTX,1237,"SDValue Tmp4 = DAG.getStore(Tmp1, Tmp2, Tmp3, dl, Alignment, isVolatile);"
LLVM,NVPTX,1238,if ( ! DirectCallee ) {
LLVM,NVPTX,1239,if ( ! DirectCallee ) {
LLVM,NVPTX,1240,
LLVM,NVPTX,1241,
LLVM,NVPTX,1242,
LLVM,NVPTX,1243,The
LLVM,NVPTX,1244,return SDValue ( );
LLVM,NVPTX,1245,return SDValue ( );
LLVM,NVPTX,1246,
LLVM,NVPTX,1247,
LLVM,NVPTX,1248,
LLVM,NVPTX,1249,delete DwarfRangesSection;
LLVM,NVPTX,1250,case AtomicRMWInst::BinOp::Add:
LLVM,NVPTX,1251,
LLVM,NVPTX,1252,if (PTy->getElementType() != specialTypes[0] && PTy->getElementType() != specialTypes[1] && PTy->getElementType() != specialTypes[2]) return false;
LLVM,NVPTX,1253,if (STy == nullptr) return false;
LLVM,NVPTX,1254,
LLVM,NVPTX,1255,
LLVM,NVPTX,1256,case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <ST
LLVM,NVPTX,1257,SizeSoFar += numElems;
LLVM,NVPTX,1258,
LLVM,NVPTX,1259,
LLVM,NVPTX,1260,"SDValue localcopy = DAG . getFrameIndex ( MF . getFrameInfo ( ) -> CreateStackObject ( totalsize / <NUM_LIT> , <NUM_LIT> , false ) , getPointerTy ( ) ) ;"
LLVM,NVPTX,1261,"SDValue newLD = DAG.getLoad(<STR_LIT>, dl, LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(), LD->getAlignment());"
LLVM,NVPTX,1262,Ops.push_back(ExtVal);
LLVM,NVPTX,1263,
LLVM,NVPTX,1264,"LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ;"
LLVM,NVPTX,1265,
LLVM,NVPTX,1266,ScalarRes.push_back(Res);
LLVM,NVPTX,1267,
LLVM,NVPTX,1268,
LLVM,NVPTX,1269,
LLVM,NVPTX,1270,Based on
LLVM,NVPTX,1271,case <STR_LIT>:
LLVM,NVPTX,1272,
LLVM,NVPTX,1273,InVals.push_back(p);
LLVM,NVPTX,1274,if ( isABI || isKernel ) {
LLVM,NVPTX,1275,return result;
LLVM,NVPTX,1276,
LLVM,NVPTX,1277,"Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), isVolatile, isNonTemporal, Alignment);"
LLVM,NVPTX,1278,"Tmp3 = DAG.getNode(<STR_LIT>, dl, <STR_LIT>, Tmp3);"
LLVM,NVPTX,1279,
LLVM,NVPTX,1280,"SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, &OtherOps[<NUM_LIT>], OtherOps.size(), MemSD->getMemoryVT(), MemSD->getMemOperand());"
LLVM,NVPTX,1281,O << <STR_LIT> << align << <STR_LIT> ;
LLVM,NVPTX,1282,return MF.getDenormalMode(APFloat::IEEEsingle()).Output == DenormalMode::PreserveSign;
LLVM,NVPTX,1283,
LLVM,NVPTX,1284,O << <STR_LIT> << getPointerTy( ) . getSizeInBits( ) << <STR_LIT> ;
LLVM,NVPTX,1285,case 'f':
LLVM,NVPTX,1286,
LLVM,NVPTX,1287,SDValue LoadChain = NewLD . getValue ( NumElts ) ;
LLVM,NVPTX,1288,ScalarRes.push_back(Res);
LLVM,NVPTX,1289,
LLVM,NVPTX,1290,case <NUM_LIT> : if ( AM . HasBaseReg ) return false ;
LLVM,NVPTX,1291,
LLVM,NVPTX,1292,unsigned Opcode = <NUM_LIT>;
LLVM,NVPTX,1293,LdResVTs = DAG.getVTList(ListVTs);
LLVM,NVPTX,1294,"SDValue Res = DAG.getNode(Opcode, DL, LdResVTs, OtherOps);"
LLVM,NVPTX,1295,"return std::make_pair(<NUM_LIT>, &<STR_LIT>);"
LLVM,NVPTX,1296,"return DAG.getNode(<STR_LIT>, dl, Node->getValueType(<NUM_LIT>), &Ops[<NUM_LIT>], Ops.size()); Here, `<STR_LIT>` is a string literal that represents the name of the node to be created, `<NUM_LIT>` is a numeric"
LLVM,NVPTX,1297,"Ops.push_back(DAG.getNode(<STR_LIT>, dl, EltVT, SubOp, DAG.getIntPtrConstant(j)));"
LLVM,NVPTX,1298,
LLVM,NVPTX,1299,"SDValue newLD = DAG.getLoad(<STR_LIT>, dl, LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(), LD->getAlignment());"
LLVM,NVPTX,1300,
LLVM,NVPTX,1301,"Chain = DAG.getNode(isABI ? <STR_LIT> : <STR_LIT>, dl, <STR_LIT>, Chain, DAG.getConstant(isABI ? sizesofar : idx, <STR_LIT>), tmpval);"
LLVM,NVPTX,1302,SDValue Tmp4 = ST->getValue();
LLVM,NVPTX,1303,return NewSt;
LLVM,NVPTX,1304,
LLVM,NVPTX,1305,"SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, &OtherOps[<NUM_LIT>], OtherOps.size(), MemSD->getMemoryVT(), MemSD->getMemOperand());"
LLVM,NVPTX,1306,ScalarRes.push_back(Res);
LLVM,NVPTX,1307,
LLVM,NVPTX,1308,O << <STR_LIT> << align << <STR_LIT> ;
LLVM,NVPTX,1309,
LLVM,NVPTX,1310,O << <STR_LIT> << align << <STR_LIT> ;
LLVM,NVPTX,1311,O << <STR_LIT> << align << <STR_LIT>;
LLVM,NVPTX,1312,"setOperationAction(<STR_LIT>, <STR_LIT>, Custom);"
LLVM,NVPTX,1313,unsigned numElems = <NUM_LIT>;
LLVM,NVPTX,1314,return combineRepeatedFPDivisors & NUM_LIT;
LLVM,NVPTX,1315,return combineRepeatedFPDivisors & NUM_LIT;
LLVM,NVPTX,1316,*name += suffix.str();
LLVM,NVPTX,1317,return <NUM_LIT>;
LLVM,NVPTX,1318,
LLVM,NVPTX,1319,
LLVM,NVPTX,1320,
LLVM,NVPTX,1321,return true;
LLVM,NVPTX,1322,const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : <STR_LIT>;
LLVM,NVPTX,1323,
LLVM,NVPTX,1324,
LLVM,NVPTX,1325,"Builder.CreateMemCpy(DstAddr, SrcAddr, Size, Align);"
LLVM,NVPTX,1326,"LoopIndex->addIncoming(NewIndex, LoopBB);"
LLVM,NVPTX,1327,
LLVM,NVPTX,1328,
LLVM,NVPTX,1329,
LLVM,NVPTX,1330,AU.addPreserved(new StackProtector());
LLVM,NVPTX,1331,return false;
LLVM,NVPTX,1332,for (LoadInst *LI : AggrLoads) {
LLVM,NVPTX,1333,if ( AggrLoads.size() == <NUM_LIT> && MemCalls.size() == <NUM_LIT> ) { return false; }
LLVM,NVPTX,1334,AggrLoads.push_back(LI);
LLVM,NVPTX,1335,MemCalls.push_back(new MemIntrinsic(LI));
LLVM,NVPTX,1336,"expandMemSetAsLoop(Memset, TTI);"
LLVM,NVPTX,1337,"ind->addIncoming(newind, loopBB);"
LLVM,NVPTX,1338,loop.CreateBr(loopBB);
LLVM,NVPTX,1339,
LLVM,NVPTX,1340,aggrMemsets . push_back ( memsetintr ) ;
LLVM,NVPTX,1341,"ind->addIncoming(ConstantInt::get(indType, <NUM_LIT>), loopBB);"
LLVM,NVPTX,1342,if (len_int->getZExtValue() >= MaxAggrCopySize) {
LLVM,NVPTX,1343,builder.CreateBr(loopBB);
LLVM,NVPTX,1344,"ind->addIncoming(ConstantInt::get(len->getType(), <NUM_LIT>), origBB);"
LLVM,NVPTX,1345,"ind->addIncoming(ConstantInt::get(indType, <NUM_LIT>), origBB);"
LLVM,NVPTX,1346,if ( ( aggrLoads . size ( ) == <NUM_LIT> ) && ( aggrMemcpys . size ( ) == <NUM_LIT> ) && ( aggrMemsets . size ( ) == <NUM_LIT> ) ) return false ;
LLVM,NVPTX,1347,Value * destAddr = store->getOperand(<NUM_LIT>);
LLVM,NVPTX,1348,"Value * len = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , numLoads ) ;"
LLVM,NVPTX,1349,"Value * CopyLen = ConstantInt :: get ( Type :: getInt32Ty ( Context ) , NumLoads ) ;"
LLVM,NVPTX,1350,if (IntrCall->getDest()->getType()->isPointerTy()) {
LLVM,NVPTX,1351,"expandMemMoveAsLoop(Memmove, TTI);"
LLVM,NVPTX,1352,if (AggrLoads.size() == <NUM_LIT> && MemCalls.size() == <NUM_LIT>) {
LLVM,NVPTX,1353,
LLVM,NVPTX,1354,loop.CreateBr(newBB);
LLVM,NVPTX,1355,"ind->addIncoming(newind, loopBB);"
LLVM,NVPTX,1356,
LLVM,NVPTX,1357,
LLVM,NVPTX,1358,LoopBuilder.CreateBr(NewBB);
LLVM,NVPTX,1359,
LLVM,NVPTX,1360,"return ""getPassName"";"
LLVM,NVPTX,1361,
LLVM,NVPTX,1362,return this.getPassName ( ) ;
LLVM,NVPTX,1363,return this.getPassName ( ) ;
LLVM,NVPTX,1364,Memcpy -> eraseFromParent ( ) ;
LLVM,NVPTX,1365,for (LoadInst *LI : AggrLoads) {
LLVM,NVPTX,1366,
LLVM,NVPTX,1367,return new ISA_LITLowerAllocaPass();
LLVM,NVPTX,1368,Some possible next statements could include:
LLVM,NVPTX,1369,Some possible next statements could include:
LLVM,NVPTX,1370,NewASCToLocal -> insertAfter ( NewASCToGeneric ) ;
LLVM,NVPTX,1371,
LLVM,NVPTX,1372,
LLVM,NVPTX,1373,
LLVM,NVPTX,1374,
LLVM,NVPTX,1375,Some possible next statements could include:
LLVM,NVPTX,1376,Some possible next statements could include:
LLVM,NVPTX,1377,
LLVM,NVPTX,1378,const auto & AllocaUse = * UI ++ ;
LLVM,NVPTX,1379,allocaInst -> replaceAllUsesWith ( NewASCToGeneric ) ;
LLVM,NVPTX,1380,Changed = true ;
LLVM,NVPTX,1381,"if ( GI && GI -> getPointerOperand ( ) == allocaInst ) { GI -> setOperand ( GI -> getPointerOperandIndex ( ) , NewASCToGeneric ) ; continue ; }"
LLVM,NVPTX,1382,while (!ItemsToConvert.empty()) {
LLVM,NVPTX,1383,
LLVM,NVPTX,1384,
LLVM,NVPTX,1385,
LLVM,NVPTX,1386,
LLVM,NVPTX,1387,while (!ValuesToCheck.empty()) {
LLVM,NVPTX,1388,"Instruction * PtrInGlobal = new AddrSpaceCastInst ( Ptr , PointerType :: getWithSamePointeeType ( cast < PointerType > ( Ptr -> getType ( ) ) , ADDRESS_SPACE_GLOBAL ) , Ptr -> getName ( ) , & * InsertPt ) ;"
LLVM,NVPTX,1389,"PtrInGeneric -> setOperand ( <NUM_LIT> , Ptr ) ;"
LLVM,NVPTX,1390,FunctionPass ( ID )
LLVM,NVPTX,1391,FunctionPass ( ID )
LLVM,NVPTX,1392,return true;
LLVM,NVPTX,1393,return isKernelFunction(F) ? runOnKernelFunction(F) : runOnDeviceFunction(F);
LLVM,NVPTX,1394,return isKernelFunction ( F ) ? runOnKernelFunction ( F ) : runOnDeviceFunction ( F ) ;
LLVM,NVPTX,1395,
LLVM,NVPTX,1396,ArgInParam->setAlignment(Func->getParamAlignment(Arg->getArgNo()));
LLVM,NVPTX,1397,if (PType) {
LLVM,NVPTX,1398,ArgInParam -> replaceAllUsesWith ( AllocA ) ;
LLVM,NVPTX,1399,ArgInParam->setAlignment(Func->getParamAlignment(Arg->getArgNo()+1));
LLVM,NVPTX,1400,return false;
LLVM,NVPTX,1401,const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ;
LLVM,NVPTX,1402,
LLVM,NVPTX,1403,if (Arg->hasByValAttr()) {
LLVM,NVPTX,1404,if (Arg.getType()->isPointerTy()) {
LLVM,NVPTX,1405,FirstInst->insertBefore(AllocA);
LLVM,NVPTX,1406,Type * StructType = PType->getElementType();
LLVM,NVPTX,1407,Type * StructType = PType->getElementType();
LLVM,NVPTX,1408,while (!ItemsToConvert.empty()) {
LLVM,NVPTX,1409,"return ""getPassName"";"
LLVM,NVPTX,1410,"return ""getPassName"";"
LLVM,NVPTX,1411,AllocA -> setAlignment(Func -> getParamAlignment(Arg -> getArgNo() + 1));
LLVM,NVPTX,1412,AllocA->setAlignment(Func->getParamAlignment(Arg->getArgNo()+<NUM_LIT>));
LLVM,NVPTX,1413,"Instruction *PtrInGeneric = new AddrSpaceCastInst(PtrInGlobal, Ptr->getType(), Ptr->getName(), &*InsertPt);"
LLVM,NVPTX,1414,InsertPt = ++cast<Instruction>(Ptr)->getIterator();
LLVM,NVPTX,1415,handleByValParam(&Arg);
LLVM,NVPTX,1416,if (Arg.getType()->isPointerTy()) {
LLVM,NVPTX,1417,"Value * ArgInGeneric = new AddrSpaceCastInst(ArgInGlobal, Arg->getType(), Arg->getName(), FirstInst);"
LLVM,NVPTX,1418,"ArgInGlobal->setOperand(<NUM_LIT>, Arg);"
LLVM,NVPTX,1419,if (Arg.getType()->isPointerTy()) {
LLVM,NVPTX,1420,Arg->getType()->isPointerTy()
LLVM,NVPTX,1421,InsertPt = Arg->getParent()->getEntryBlock().begin();
LLVM,NVPTX,1422,
LLVM,NVPTX,1423,FirstInst->insertAfter(AllocA);
LLVM,NVPTX,1424,"FirstInst->setOperand(0, LI);"
LLVM,NVPTX,1425,TM = TM;
LLVM,NVPTX,1426,TM = TM;
LLVM,NVPTX,1427,if (Arg.getType()->isPointerTy()) {
LLVM,NVPTX,1428,
LLVM,NVPTX,1429,
LLVM,NVPTX,1430,"CallInst * callInst = Func->CreateCall(CvtFunc, BitcastArgs);"
LLVM,NVPTX,1431,"CallInst * CvtCall = CallInst::Create(CvtFunc, BitcastArgs, Arg->getName(), FirstInst);"
LLVM,NVPTX,1432,
LLVM,NVPTX,1433,
LLVM,NVPTX,1434,Some possible next statements could include:
LLVM,NVPTX,1435,Some possible next statements could include:
LLVM,NVPTX,1436,return true;
LLVM,NVPTX,1437,
LLVM,NVPTX,1438,
LLVM,NVPTX,1439,
LLVM,NVPTX,1440,
LLVM,NVPTX,1441,
LLVM,NVPTX,1442,
LLVM,NVPTX,1443,
LLVM,NVPTX,1444,
LLVM,NVPTX,1445,Data8bitsDirective = <STR_LIT> ;
LLVM,NVPTX,1446,"For example, the `SupportsDebugInformation` attribute is set to `true`, which means that the compiler will generate debug information for the code. The `HasFunctionAlignment` attribute is set to `false`, which means that the compiler will not align functions in memory. The `HasDotTypeDotSizeDirective` attribute is set to `false`, which means that the compiler will"
LLVM,NVPTX,1447,
LLVM,NVPTX,1448,CalleeSaveStackSlotSize = <NUM_LIT>;
LLVM,NVPTX,1449,
LLVM,NVPTX,1450,
LLVM,NVPTX,1451,CompilerConfiguration config = new CompilerConfiguration();
LLVM,NVPTX,1452,
LLVM,NVPTX,1453,PointerSize = CalleeSaveStackSlotSize = <NUM_LIT>;
LLVM,NVPTX,1454,Data64bitsDirective = <STR_LIT> ;
LLVM,NVPTX,1455,
LLVM,NVPTX,1456,InlineAsmStart = <STR_LIT>
LLVM,NVPTX,1457,PointerSize = CalleeSaveStackSlotSize = <NUM_LIT>;
LLVM,NVPTX,1458,
LLVM,NVPTX,1459,
LLVM,NVPTX,1460,
LLVM,NVPTX,1461,Some possible next statements could include:
LLVM,NVPTX,1462,
LLVM,NVPTX,1463,
LLVM,NVPTX,1464,
LLVM,NVPTX,1465,return E->getKind() == MCExpr::Target;
LLVM,NVPTX,1466,
LLVM,NVPTX,1467,
LLVM,NVPTX,1468,Res = MCValue::getUnknown();
LLVM,NVPTX,1469,
LLVM,NVPTX,1470,
LLVM,NVPTX,1471,
LLVM,NVPTX,1472,
LLVM,NVPTX,1473,return Flt;
LLVM,NVPTX,1474,
LLVM,NVPTX,1475,
LLVM,NVPTX,1476,"However, based on the syntax and the fact that the `SymExpr` class is being returned, it is likely that the next statement will be a call to a method or function that takes a `SymExpr` object as an argument. For example, it could be a call to a function that evaluates the expression represented by the `SymExpr` object, or a call to a method that modifies the"
LLVM,NVPTX,1477,"However, based on the syntax and the fact that the `SymExpr` class is being returned, it is likely that the next statement will be a call to a method or function that takes a `SymExpr` object as an argument. For example, it could be a call to a function that evaluates the expression represented by the `SymExpr` object, or a call to a method that modifies the"
LLVM,NVPTX,1478,
LLVM,NVPTX,1479,
LLVM,NVPTX,1480,this->SymExpr = _SymExpr;
LLVM,NVPTX,1481,this->SymExpr = _SymExpr;
LLVM,NVPTX,1482,
LLVM,NVPTX,1483,"return create ( VK_<ISA_LIT>_DOUBLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1484,
LLVM,NVPTX,1485,"return create ( VK_<ISA_LIT>_SINGLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1486,"return create ( VK_<ISA_LIT>_SINGLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1487,Kind = Kind;
LLVM,NVPTX,1488,Kind = Kind;
LLVM,NVPTX,1489,
LLVM,NVPTX,1490,
LLVM,NVPTX,1491,"return new (Ctx) <ISA_LIT>FloatMCExpr(Kind, Flt);"
LLVM,NVPTX,1492,OS << <STR_LIT> << * SymExpr << <STR_LIT>;
LLVM,NVPTX,1493,OS << <STR_LIT> << * SymExpr << <STR_LIT> ;
LLVM,NVPTX,1494,
LLVM,NVPTX,1495,"OS << std::string(NumHex - HexStr.length(), '0');"
LLVM,NVPTX,1496,OS << <STR_LIT>;
LLVM,NVPTX,1497,
LLVM,NVPTX,1498,
LLVM,NVPTX,1499,"return Create ( VK_<ISA_LIT>_DOUBLE_PREC_FLOAT , Flt , Ctx ) ;"
LLVM,NVPTX,1500,
LLVM,NVPTX,1501,"Res = MCValue(0, 0, 0);"
LLVM,NVPTX,1502,
LLVM,NVPTX,1503,
LLVM,NVPTX,1504,Flt = _Flt;
LLVM,NVPTX,1505,Flt = _Flt;
LLVM,NVPTX,1506,OS << HexStr;
LLVM,NVPTX,1507,OS << <STR_LIT>;
LLVM,NVPTX,1508,"return new <ISA_LIT>MCInstPrinter(T, SyntaxVariant, MAI, MII, MRI);"
LLVM,NVPTX,1509,"return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;"
LLVM,NVPTX,1510,return X;
LLVM,NVPTX,1511,
LLVM,NVPTX,1512,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,NVPTX,1513,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,NVPTX,1514,* `RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X
LLVM,NVPTX,1515,
LLVM,NVPTX,1516,
LLVM,NVPTX,1517,
LLVM,NVPTX,1518,TargetRegistry::Register
LLVM,NVPTX,1519,
LLVM,NVPTX,1520,"MCCodeGenInfo *X = new MCCodeGenInfo(TT, RM,"
LLVM,NVPTX,1521,
LLVM,NVPTX,1522,"return new <ISA_LIT>MCInstPrinter(T, SyntaxVariant, MAI, MII, MRI, STI);"
LLVM,NVPTX,1523,"TargetRegistry::RegisterMCCodeEmitter(*T, create<ISA_LIT>MCCodeEmitter);"
LLVM,NVPTX,1524,"TargetRegistry::RegisterMCAsmInfo(*T, create<ISA_LIT>MCAsmInfo);"
LLVM,NVPTX,1525,"X->InitMCCodeGenInfo(RM, CM, OL);"
LLVM,NVPTX,1526,
LLVM,NVPTX,1527,TargetRegistry::RegisterMCCodeGenInfo(The<ISA_LIT>Target3
LLVM,NVPTX,1528,
LLVM,NVPTX,1529,
LLVM,NVPTX,1530,"return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ;"
LLVM,NVPTX,1531,
LLVM,NVPTX,1532,MCInstrInfo * X = new MCInstrInfo ( ) ;
LLVM,NVPTX,1533,
LLVM,NVPTX,1534,return X;
LLVM,NVPTX,1535,
LLVM,NVPTX,1536,"return new MCSubtargetInfo<ISA_LIT>(TT, CPU, FS);"
LLVM,NVPTX,1537,"TargetRegistry::RegisterMCAsmInfo(The<ISA_LIT>Target32, create<ISA_LIT>MCAsmInfo);"
LLVM,NVPTX,1538,
LLVM,NVPTX,1539,MRI.removeUse(Prev.getOperand(<NUM_LIT>).getReg());
LLVM,NVPTX,1540,return true;
LLVM,NVPTX,1541,if (MRI.use_empty(<STR_LIT>)) {
LLVM,NVPTX,1542,
LLVM,NVPTX,1543,MIB.addReg(<STR_LIT>).add(Prev.getOperand(<NUM_LIT>));
LLVM,NVPTX,1544,MI -> eraseFromParentAndMarkDBGValuesForRemoval ( ) ;
LLVM,NVPTX,1545,
LLVM,NVPTX,1546,MI->eraseFromParentAndMarkDBGValuesForRemoval();
LLVM,NVPTX,1547,
LLVM,NVPTX,1548,"MRI->replaceUsesWithIf(Prev.getOperand(<NUM_LIT>).getReg(), MIB.getReg(0), [&](MachineInstr &MI, unsigned OpNum) { return MI.getOperand(OpNum).isReg(); });"
LLVM,NVPTX,1549,MRI.use_empty(NRI->getFrameRegister(MF));
LLVM,NVPTX,1550,Changed = true ;
LLVM,NVPTX,1551,MIB.addReg(NRI->getFrameLocalRegister(MF));
LLVM,NVPTX,1552,
LLVM,NVPTX,1553,MachineFunctionPass *llvm::create<ISA_LIT>Peephole() { return new <ISA_LIT>Peephole(); }
LLVM,NVPTX,1554,
LLVM,NVPTX,1555,AU.setPreservesAll();
LLVM,NVPTX,1556,
LLVM,NVPTX,1557,
LLVM,NVPTX,1558,return true;
LLVM,NVPTX,1559,return false;
LLVM,NVPTX,1560,if (isCVTAToLocalCombinationCandidate(MI)) {
LLVM,NVPTX,1561,"MFI->setObjectOffset(FrameIdx, Offset);"
LLVM,NVPTX,1562,Offset += MFI->getLocalFrameSize();
LLVM,NVPTX,1563,unsigned StackAlign = TFI.getStackAlignment();
LLVM,NVPTX,1564,return new <ISA_LIT>PrologEpilogPass ( ) ;
LLVM,NVPTX,1565,class PrologEpilogPass : public MachineFunctionPass {
LLVM,NVPTX,1566,class PrologEpilogPass : public MachineFunctionPass {
LLVM,NVPTX,1567,Here are a few possibilities:
LLVM,NVPTX,1568,"LLVM_DEBUG(dbgs() << ""Frame "" << FrameIdx << "": "" << -Offset << "" bytes"");"
LLVM,NVPTX,1569,"MFI.setObjectOffset(FrameIdx, Offset);"
LLVM,NVPTX,1570,Offset = (Offset + Align - 1) / Align * Align;
LLVM,NVPTX,1571,
LLVM,NVPTX,1572,
LLVM,NVPTX,1573,Offset = (Offset + Align - <NUM_LIT>) / Align * Align;
LLVM,NVPTX,1574,
LLVM,NVPTX,1575,Offset += MFI . getLocalFrameSize ( ) ;
LLVM,NVPTX,1576,
LLVM,NVPTX,1577,
LLVM,NVPTX,1578,
LLVM,NVPTX,1579,
LLVM,NVPTX,1580,
LLVM,NVPTX,1581,
LLVM,NVPTX,1582,
LLVM,NVPTX,1583,"TRI->eliminateFrameIndex(MI, <NUM_LIT>, i, nullptr);"
LLVM,NVPTX,1584,"TFI.emitEpilogue(MF, *I);"
LLVM,NVPTX,1585,TFI.emitPrologue(MF);
LLVM,NVPTX,1586,
LLVM,NVPTX,1587,"Offset = std::max(Offset, (int64_t)MFI.getLocalStackAllocationBlockSize());"
LLVM,NVPTX,1588,
LLVM,NVPTX,1589,Offset += MFI.getLocalFrameSize();
LLVM,NVPTX,1590,Ops.push_back(Offset);
LLVM,NVPTX,1591,int64_t StackSize = Offset - LocalAreaOffset;
LLVM,NVPTX,1592,
LLVM,NVPTX,1593,return new <ISA_LIT>ProxyRegErasure();
LLVM,NVPTX,1594,
LLVM,NVPTX,1595,
LLVM,NVPTX,1596,initialize<ISA_LIT>ProxyRegErasurePass ( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,NVPTX,1597,for (auto & BB : MF) {
LLVM,NVPTX,1598,if (Op == From) {
LLVM,NVPTX,1599,Here are a few possibilities for what the next statement could be:
LLVM,NVPTX,1600,"However, based on the `<STR_LIT>` cases in the `switch` statement, it is likely that the next statement will be a block of code that is executed when the value of `MI.getOpcode()` matches one of the `<STR_LIT>` cases. The exact behavior of the next statement will depend on the specific"
LLVM,NVPTX,1601,
LLVM,NVPTX,1602,
LLVM,NVPTX,1603,
LLVM,NVPTX,1604,"However, based on the names of the methods and the context of the code, it is likely that the next statement will be related to accessing or manipulating the object at the offset specified by `Offset`. The `<NUM_LIT>` placeholder suggests that the code is expecting a literal value to be passed as an argument to the `getOperand"
LLVM,NVPTX,1605,
LLVM,NVPTX,1606,
LLVM,NVPTX,1607,
LLVM,NVPTX,1608,
LLVM,NVPTX,1609,return <STR_LIT>;
LLVM,NVPTX,1610,return MF.getFrameRegister();
LLVM,NVPTX,1611,return CalleeSavedRegClasses;
LLVM,NVPTX,1612,return CalleeSavedRegClasses;
LLVM,NVPTX,1613,return CalleeSavedRegs;
LLVM,NVPTX,1614,return CalleeSavedRegs;
LLVM,NVPTX,1615,
LLVM,NVPTX,1616,
LLVM,NVPTX,1617,
LLVM,NVPTX,1618,
LLVM,NVPTX,1619,"<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetInstrInfo & tii , const <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( st . is64Bit ( ) ) {"
LLVM,NVPTX,1620,"<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetInstrInfo & tii , const <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( st . is64Bit ( ) ) {"
LLVM,NVPTX,1621,
LLVM,NVPTX,1622,
LLVM,NVPTX,1623,"However, based on the name of the function and the parameters, it is likely that the function is used to retrieve the register number of a dwarf register, which is a type of register used in the DWARF debugging format. The `RegNum` parameter is likely to be the register number of the dwarf register, and the"
LLVM,NVPTX,1624,
LLVM,NVPTX,1625,
LLVM,NVPTX,1626,
LLVM,NVPTX,1627,
LLVM,NVPTX,1628,
LLVM,NVPTX,1629,
LLVM,NVPTX,1630,
LLVM,NVPTX,1631,"However, based on the name of the method and the fact that it is a member function of the `RegisterInfo` class, it is likely that the method returns a register that is used as a frame pointer in the machine function. The `MachineFunction` class is a part of the LLVM compiler infrastructure and represents a function in the machine code level. The `RegisterInfo"
LLVM,NVPTX,1632,
LLVM,NVPTX,1633,
LLVM,NVPTX,1634,return <STR_LIT>;
LLVM,NVPTX,1635,"<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( st . is64Bit ( ) ) {"
LLVM,NVPTX,1636,"<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) , Is64Bit ( st . is64Bit ( ) ) {"
LLVM,NVPTX,1637,return CalleeSavedRegClasses;
LLVM,NVPTX,1638,return;
LLVM,NVPTX,1639,"MI.getOperand(i).ChangeToRegister(<STR_LIT>, false);"
LLVM,NVPTX,1640,"RS->eliminateFI(MI, FrameIndex, Offset);"
LLVM,NVPTX,1641,
LLVM,NVPTX,1642,
LLVM,NVPTX,1643,
LLVM,NVPTX,1644,"else if (RC == &""<STR_LIT>"") { return ""<STR_LIT>""; }"
LLVM,NVPTX,1645,
LLVM,NVPTX,1646,
LLVM,NVPTX,1647,
LLVM,NVPTX,1648,
LLVM,NVPTX,1649,
LLVM,NVPTX,1650,"In general, the `getCalleeSavedRegs` method is used to retrieve the registers that are saved by the callee before it returns, so that the caller can restore them when"
LLVM,NVPTX,1651,
LLVM,NVPTX,1652,
LLVM,NVPTX,1653,
LLVM,NVPTX,1654,return TM.is64Bit() ? <STR_LIT> : <STR_LIT>;
LLVM,NVPTX,1655,
LLVM,NVPTX,1656,
LLVM,NVPTX,1657,
LLVM,NVPTX,1658,* `ISA_LIT` is a macro that expands to a string literal representing the name of the instruction set architecture (ISA) being targeted.
LLVM,NVPTX,1659,* `ISA_LIT` is a macro that expands to a string literal representing the name of the instruction set architecture (ISA) being targeted.
LLVM,NVPTX,1660,"return ""MyPass"";"
LLVM,NVPTX,1661,
LLVM,NVPTX,1662,InstrsToRemove.insert(&TexHandleDef);
LLVM,NVPTX,1663,if ( MCID . TSFlags & <STR_LIT> ) {
LLVM,NVPTX,1664,
LLVM,NVPTX,1665,Op.ChangeToImmediate(Idx);
LLVM,NVPTX,1666,InstrsToRemove.clear();
LLVM,NVPTX,1667,
LLVM,NVPTX,1668,StringRef ParamName = Sym.substr(ParamBaseName.size());
LLVM,NVPTX,1669,InstrsToRemove.insert(&TexHandleDef);
LLVM,NVPTX,1670,
LLVM,NVPTX,1671,InstrsToRemove . clear ( ) ;
LLVM,NVPTX,1672,
LLVM,NVPTX,1673,MachineFunctionPass *llvm::create<ISA_LIT>ReplaceImageHandlesPass() { return new <ISA_LIT>ReplaceImageHandles(); }
LLVM,NVPTX,1674,
LLVM,NVPTX,1675,"return ""getPassName"";"
LLVM,NVPTX,1676,
LLVM,NVPTX,1677,ISA_LIT`ReplaceImageHandles`::`ISA_LIT`ReplaceImageHandles`( ) : MachineFunctionPass ( ID )
LLVM,NVPTX,1678,ISA_LIT`ReplaceImageHandles`::`ISA_LIT`ReplaceImageHandles`( ) : MachineFunctionPass ( ID )
LLVM,NVPTX,1679,
LLVM,NVPTX,1680,
LLVM,NVPTX,1681,
LLVM,NVPTX,1682,
LLVM,NVPTX,1683,Here are a few possibilities:
LLVM,NVPTX,1684,Here are a few possibilities:
LLVM,NVPTX,1685,
LLVM,NVPTX,1686,
LLVM,NVPTX,1687,
LLVM,NVPTX,1688,
LLVM,NVPTX,1689,Here are some possible next statements:
LLVM,NVPTX,1690,Here are some possible next statements:
LLVM,NVPTX,1691,
LLVM,NVPTX,1692,
LLVM,NVPTX,1693,
LLVM,NVPTX,1694,
LLVM,NVPTX,1695,
LLVM,NVPTX,1696,Here are a few possibilities for the next statement:
LLVM,NVPTX,1697,Here are a few possibilities for the next statement:
LLVM,NVPTX,1698,
LLVM,NVPTX,1699,"return ""begin"";"
LLVM,NVPTX,1700,
LLVM,NVPTX,1701,
LLVM,NVPTX,1702,
LLVM,NVPTX,1703,
LLVM,NVPTX,1704,
LLVM,NVPTX,1705,
LLVM,NVPTX,1706,"OS << MAI.getCommentString() << "" Switch to section "" << Subsection->getSectionName() << ""\n"";"
LLVM,NVPTX,1707,"OS << MAI.getCommentString() << "" Switch to section "" << Subsection->getSectionName() << ""\n"";"
LLVM,NVPTX,1708,
LLVM,NVPTX,1709,
LLVM,NVPTX,1710,
LLVM,NVPTX,1711,
LLVM,NVPTX,1712,AU.addPreserved(<STR_LIT>);
LLVM,NVPTX,1713,
LLVM,NVPTX,1714,
LLVM,NVPTX,1715,"return ""getPassName"";"
LLVM,NVPTX,1716,
LLVM,NVPTX,1717,
LLVM,NVPTX,1718,changed = true;
LLVM,NVPTX,1719,return hasFP16Math() && NoF16Math == false;
LLVM,NVPTX,1720,TargetName = std::string(CPU.empty() ? <STR_LIT> : CPU);
LLVM,NVPTX,1721,
LLVM,NVPTX,1722,
LLVM,NVPTX,1723,
LLVM,NVPTX,1724,
LLVM,NVPTX,1725,return &FrameLowering;
LLVM,NVPTX,1726,return new TargetFrameLowering();
LLVM,NVPTX,1727,return &InstrInfo;
LLVM,NVPTX,1728,return &InstrInfo.getRegisterInfo();
LLVM,NVPTX,1729,
LLVM,NVPTX,1730,
LLVM,NVPTX,1731,
LLVM,NVPTX,1732,
LLVM,NVPTX,1733,return TargetName;
LLVM,NVPTX,1734,return TargetName;
LLVM,NVPTX,1735,return SmVersion >= NUM_LIT;
LLVM,NVPTX,1736,return SmVersion >= <NUM_LIT> ;
LLVM,NVPTX,1737,return SmVersion >= 10;
LLVM,NVPTX,1738,return SmVersion >= 10;
LLVM,NVPTX,1739,return SmVersion >= <NUM_LIT> ;
LLVM,NVPTX,1740,return SmVersion >= 10;
LLVM,NVPTX,1741,return SmVersion >= 10;
LLVM,NVPTX,1742,return SmVersion >= 10;
LLVM,NVPTX,1743,return SmVersion >= 10;
LLVM,NVPTX,1744,return SmVersion >= <NUM_LIT>;
LLVM,NVPTX,1745,return SmVersion >= 10;
LLVM,NVPTX,1746,
LLVM,NVPTX,1747,return SmVersion >= 10;
LLVM,NVPTX,1748,return SmVersion >= 10;
LLVM,NVPTX,1749,return (SmVersion >= <NUM_LIT>);
LLVM,NVPTX,1750,
LLVM,NVPTX,1751,return hasHWROT32 ( ) || hasSWROT32 ( ) ;
LLVM,NVPTX,1752,
LLVM,NVPTX,1753,
LLVM,NVPTX,1754,
LLVM,NVPTX,1755,return SmVersion >= 10;
LLVM,NVPTX,1756,
LLVM,NVPTX,1757,return *this;
LLVM,NVPTX,1758,InstrInfo = new <ISA_LIT>InstrInfo ( TM );
LLVM,NVPTX,1759,InstrInfo = new <ISA_LIT>InstrInfo ( TM );
LLVM,NVPTX,1760,return SmVersion >= 10;
LLVM,NVPTX,1761,return SmVersion >= 10;
LLVM,NVPTX,1762,
LLVM,NVPTX,1763,return false;
LLVM,NVPTX,1764,return SmVersion >= 10;
LLVM,NVPTX,1765,return SmVersion >= 10;
LLVM,NVPTX,1766,
LLVM,NVPTX,1767,PTXVersion = <NUM_LIT>;
LLVM,NVPTX,1768,return HasAtomScope;
LLVM,NVPTX,1769,
LLVM,NVPTX,1770,InstrInfo = new <ISA_LIT>InstrInfo ( TM );
LLVM,NVPTX,1771,InstrInfo = new <ISA_LIT>InstrInfo ( TM );
LLVM,NVPTX,1772,p = <STR_LIT> <STR_LIT> <STR_LIT> ;
LLVM,NVPTX,1773,
LLVM,NVPTX,1774,```
LLVM,NVPTX,1775,PTXVersion = <NUM_LIT>;
LLVM,NVPTX,1776,PTXVersion = <NUM_LIT>;
LLVM,NVPTX,1777,
LLVM,NVPTX,1778,PTXVersion = <NUM_LIT>;
LLVM,NVPTX,1779,
LLVM,NVPTX,1780,
LLVM,NVPTX,1781,return SmVersion >= 10;
LLVM,NVPTX,1782,return SmVersion >= 10;
LLVM,NVPTX,1783,
LLVM,NVPTX,1784,return SmVersion >= 10;
LLVM,NVPTX,1785,return SmVersion >= 10;
LLVM,NVPTX,1786,return SmVersion >= 10;
LLVM,NVPTX,1787,
LLVM,NVPTX,1788,SmVersion = atoi(TargetName.c_str() + <NUM_LIT>);
LLVM,NVPTX,1789,SmVersion = atoi(TargetName.c_str() + <NUM_LIT>);
LLVM,NVPTX,1790,PTXVersion = <NUM_LIT> ;
LLVM,NVPTX,1791,
LLVM,NVPTX,1792,
LLVM,NVPTX,1793,return SmVersion >= 10;
LLVM,NVPTX,1794,InstrInfo = new <ISA_LIT>InstrInfo(TM);
LLVM,NVPTX,1795,InstrInfo = new <ISA_LIT>InstrInfo(TM);
LLVM,NVPTX,1796,"InstrInfo = initializeSubtargetDependencies(CPU, FS);"
LLVM,NVPTX,1797,Ret += <STR_LIT>;
LLVM,NVPTX,1798,
LLVM,NVPTX,1799,
LLVM,NVPTX,1800,
LLVM,NVPTX,1801,
LLVM,NVPTX,1802,
LLVM,NVPTX,1803,return InstrInfo.getRegisterInfo();
LLVM,NVPTX,1804,return InstrInfo.getRegisterInfo();
LLVM,NVPTX,1805,TSInfo->someMethod();
LLVM,NVPTX,1806,TSInfo->someMethod();
LLVM,NVPTX,1807,
LLVM,NVPTX,1808,
LLVM,NVPTX,1809,
LLVM,NVPTX,1810,return Is64Bit;
LLVM,NVPTX,1811,The<ISA_LIT>Target32.SetTarget(ISA_LIT);
LLVM,NVPTX,1812,static Target The<ISA_LIT>Target64 = new Target();
LLVM,NVPTX,1813,"RegisterTarget<Triple::nvptx> X(getThe<ISA_LIT>Target32(), <STR_LIT>, <STR_LIT>, <STR_LIT>);"
LLVM,NVPTX,1814,RegisterTarget<Triple::nvptx64>
LLVM,NVPTX,1815,"RegisterTarget < Triple :: nvptx64 > Y ( getThe<ISA_LIT>Target64 ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1816,
LLVM,NVPTX,1817,"RegisterTarget < Triple :: nvptx > X ( The<ISA_LIT>Target64 , <STR_LIT> , <STR_LIT> ) ;"
LLVM,NVPTX,1818,
LLVM,NVPTX,1819,addPass ( createInferAddressSpacesPass ( ) ) ;
LLVM,NVPTX,1820,addPass(create<ISA_LIT>LowerAllocaPass());
LLVM,NVPTX,1821,
LLVM,NVPTX,1822,addPass(createNVVMReflectPass(ST.getSmVersion()));
LLVM,NVPTX,1823,
LLVM,NVPTX,1824,addPass ( & MemorySSAID ) ;
LLVM,NVPTX,1825,"* `addPass`: This is a function that takes a single argument, which is a pass object. The function adds the pass to the current optimization pipeline."
LLVM,NVPTX,1826,
LLVM,NVPTX,1827,Here are a few possibilities:
LLVM,NVPTX,1828,
LLVM,NVPTX,1829,return false;
LLVM,NVPTX,1830,
LLVM,NVPTX,1831,addEarlyCSEOrGVNPass ( ) ;
LLVM,NVPTX,1832,addPass(createGVNPass());
LLVM,NVPTX,1833,PM . add ( createInstructionCombiningPass ( true ) );
LLVM,NVPTX,1834,
LLVM,NVPTX,1835,Ret += <STR_LIT>;
LLVM,NVPTX,1836,TargetPassConfig *config = TargetMachine::createPassConfig
LLVM,NVPTX,1837,
LLVM,NVPTX,1838,"return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;"
LLVM,NVPTX,1839,"PR.initialize(X, Y);"
LLVM,NVPTX,1840,"TargetPassConfig(TM,"
LLVM,NVPTX,1841,"TargetPassConfig(TM,"
LLVM,NVPTX,1842,"this->TargetMachine32 = new TargetMachine32(T, TT, CPU, FS, Options, RM, CM, OL, JIT);"
LLVM,NVPTX,1843,"this->TargetMachine32 = new TargetMachine32(T, TT, CPU, FS, Options, RM, CM, OL, JIT);"
LLVM,NVPTX,1844,"this->TargetMachine64 = new TargetMachine64(T, TT, CPU, FS, Options, RM, CM, OL, JIT);"
LLVM,NVPTX,1845,"this->TargetMachine64 = new TargetMachine64(T, TT, CPU, FS, Options, RM, CM, OL, JIT);"
LLVM,NVPTX,1846,"PB.registerPipelineStartEPCallback([this](ModulePassManager &PM, OptimizationLevel Level) {"
LLVM,NVPTX,1847,Here are a few possibilities:
LLVM,NVPTX,1848,
LLVM,NVPTX,1849,addPass(&RegAllocPassID);
LLVM,NVPTX,1850,addPass(create<ISA_LIT>ReplaceImageHandlesPass());
LLVM,NVPTX,1851,return false;
LLVM,NVPTX,1852,
LLVM,NVPTX,1853,printAndVerify ( <STR_LIT> ) ;
LLVM,NVPTX,1854,addPass ( & CleanupID ) ;
LLVM,NVPTX,1855,
LLVM,NVPTX,1856,"* `addPass`: This is a function that takes two arguments: a pass object and a boolean value. The function adds the pass object to the pass manager, and sets the pass object's `is_prolog` flag to the boolean value."
LLVM,NVPTX,1857,
LLVM,NVPTX,1858,
LLVM,NVPTX,1859,"PassConfig * PassConfig = new PassConfig(this, PM);"
LLVM,NVPTX,1860,
LLVM,NVPTX,1861,
LLVM,NVPTX,1862,return getTM < <ISA_LIT>TargetMachine > ( ) ;
LLVM,NVPTX,1863,
LLVM,NVPTX,1864,RegisterTargetMachine<ISA_LIT>TargetMachine32>(The<ISA_LIT>Target32);
LLVM,NVPTX,1865,RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ;
LLVM,NVPTX,1866,"TargetPassConfig(TM, PM);"
LLVM,NVPTX,1867,"TargetPassConfig(TM, PM);"
LLVM,NVPTX,1868,
LLVM,NVPTX,1869,
LLVM,NVPTX,1870,"<ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1871,"<ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1872,
LLVM,NVPTX,1873,
LLVM,NVPTX,1874,return false;
LLVM,NVPTX,1875,return TLOF->get();
LLVM,NVPTX,1876,return TLOF->get();
LLVM,NVPTX,1877,return *Subtarget;
LLVM,NVPTX,1878,
LLVM,NVPTX,1879,RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ;
LLVM,NVPTX,1880,
LLVM,NVPTX,1881,
LLVM,NVPTX,1882,
LLVM,NVPTX,1883,
LLVM,NVPTX,1884,
LLVM,NVPTX,1885,"<ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1886,"<ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1887,addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ;
LLVM,NVPTX,1888,addPass(createPromoteMemoryToRegisterPass());
LLVM,NVPTX,1889,addPass(create<ISA_LIT>LowerArgsPass(&get<ISA_LIT>TargetMachine()));
LLVM,NVPTX,1890,"addPass(create<ISA_LIT>Peephole(), false);"
LLVM,NVPTX,1891,"addPass(create<ISA_LIT>PrologEpilogPass(), false);"
LLVM,NVPTX,1892,PM.add(createNVVMReflectPass());
LLVM,NVPTX,1893,RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( getThe<ISA_LIT>Target32 ( ) ) ;
LLVM,NVPTX,1894,"TargetMachine32::TargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, CodeModel::Model CM, CodeGenOpt::Level OL) : TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {"
LLVM,NVPTX,1895,"TargetMachine32::TargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional<Reloc::Model> RM, CodeModel::Model CM, CodeGenOpt::Level OL) : TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {"
LLVM,NVPTX,1896,"<ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1897,"<ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1898,
LLVM,NVPTX,1899,InstrInfo = new TargetInstrInfoImpl<TargetMachine>(*this);
LLVM,NVPTX,1900,InstrInfo = new TargetInstrInfoImpl<TargetMachine>(*this);
LLVM,NVPTX,1901,return false;
LLVM,NVPTX,1902,
LLVM,NVPTX,1903,
LLVM,NVPTX,1904,
LLVM,NVPTX,1905,"However, based on the name of the method and the fact that it is declared as `const`, it is likely that the method returns a pointer to a `TargetFrameLowering` object that is associated with the current object. The `const` qualifier indicates that the method does not modify the state of the object, so it is likely that the method returns a pointer to a `TargetFrameLower"
LLVM,NVPTX,1906,return &InstrInfo;
LLVM,NVPTX,1907,"However, based on the name of the method and the fact that it is declared as `const`, it is likely that the method returns a pointer to an object of type `InstrInfo` that contains information about the instruction. The `ISA_LIT` macro is likely used to specify the instruction set architecture (ISA) for which the"
LLVM,NVPTX,1908,"However, based on the name of the function `getManagedStrPool`, it is likely that the function returns a pointer to a `ManagedStringPool` object that is managed by the class. The `const` keyword at the end of the function signature suggests that the function does not modify the state of the object, and is likely to be a"
LLVM,NVPTX,1909,return const_cast<ManagedStringPool*>(&ManagedStrPool);
LLVM,NVPTX,1910,"case <STR_LIT>: return std::make_pair(II->getArgOperand(<NUM_LIT>), llvm::ADDRESS_SPACE_LOCAL);"
LLVM,NVPTX,1911,return &(InstrInfo.getRegisterInfo());
LLVM,NVPTX,1912,
LLVM,NVPTX,1913,
LLVM,NVPTX,1914,
LLVM,NVPTX,1915,
LLVM,NVPTX,1916,
LLVM,NVPTX,1917,
LLVM,NVPTX,1918,
LLVM,NVPTX,1919,return &VTTI;
LLVM,NVPTX,1920,addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ;
LLVM,NVPTX,1921,addPass(createSROAPass());
LLVM,NVPTX,1922,PM.add(createNVVMIRPass());
LLVM,NVPTX,1923,PM.add(createNVVMReflectPass());
LLVM,NVPTX,1924,return false;
LLVM,NVPTX,1925,TargetPassConfig *config = TargetMachine::createPassConfig
LLVM,NVPTX,1926,
LLVM,NVPTX,1927,
LLVM,NVPTX,1928,initialize<ISA_LIT>LowerAllocaPass ( PR ) ;
LLVM,NVPTX,1929,
LLVM,NVPTX,1930,Ret += <STR_LIT>;
LLVM,NVPTX,1931,return CodeModel::Model();
LLVM,NVPTX,1932,addPass(create<ISA_LIT>ImageOptimizerPass());
LLVM,NVPTX,1933,"addPass(create<ISA_LIT>PrologEpilogPass(), false);"
LLVM,NVPTX,1934,"* `addPass`: This is a function that takes two arguments: a pass object and a boolean value. The function adds the pass object to the pass manager, and sets the pass object's `is_prolog` flag to the boolean value."
LLVM,NVPTX,1935,return TargetIRAnalysis ( [ this ] ( Function & ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ) ) ; } ) ;
LLVM,NVPTX,1936,return TargetIRAnalysis ( [ this ] ( Function & ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this ) ) ; } ) ;
LLVM,NVPTX,1937,initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
LLVM,NVPTX,1938,
LLVM,NVPTX,1939,
LLVM,NVPTX,1940,
LLVM,NVPTX,1941,"addPass(create<ISA_LIT>ISelDag(get<ISA_LIT>TargetMachine(), getOptLevel()));"
LLVM,NVPTX,1942,addPass(createGVNPass());
LLVM,NVPTX,1943,addPass(createGVNPass());
LLVM,NVPTX,1944,
LLVM,NVPTX,1945,
LLVM,NVPTX,1946,RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ;
LLVM,NVPTX,1947,
LLVM,NVPTX,1948,
LLVM,NVPTX,1949,"<ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1950,"<ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {"
LLVM,NVPTX,1951,1. The `disablePass` function is called multiple times with different pass IDs. This disables the specified passes.
LLVM,NVPTX,1952,
LLVM,NVPTX,1953,
LLVM,NVPTX,1954,initialize<ISA_LIT>LowerConstPass ( PR ) ;
LLVM,NVPTX,1955,"LLVMTargetMachine::LLVMTargetMachine(T, computeDataLayout(is64bit, UseShortPointersOpt), TT, CPU, FS, Options, Reloc::PIC_, getEffectiveCodeModel(CM, CodeModel::Small), OL)"
LLVM,NVPTX,1956,
LLVM,NVPTX,1957,
LLVM,NVPTX,1958,addPass(create<ISA_LIT>AddressSpaceInferencePass());
LLVM,NVPTX,1959,addPass(create<ISA_LIT>InlinePass());
LLVM,NVPTX,1960,return TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) const;
LLVM,NVPTX,1961,return TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) const;
LLVM,NVPTX,1962,TargetPassConfig::addIRPasses();
LLVM,NVPTX,1963,
LLVM,NVPTX,1964,
LLVM,NVPTX,1965,initialize<ISA_LIT>LowerKernelArgsPass( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,NVPTX,1966,addPass(create<ISA_LIT>InferAddressSpacesPass());
LLVM,NVPTX,1967,addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ;
LLVM,NVPTX,1968,initialize<ISA_LIT>LowerCallPass(PR);
LLVM,NVPTX,1969,initialize<ISA_LIT>LowerArgsPass ( PR ) ;
LLVM,NVPTX,1970,PM.addPass(NVVMIntrRangePass());
LLVM,NVPTX,1971,
LLVM,NVPTX,1972,
LLVM,NVPTX,1973,
LLVM,NVPTX,1974,disablePass ( & LoopInvariantCodeMotionID ) ;
LLVM,NVPTX,1975,
LLVM,NVPTX,1976,
LLVM,NVPTX,1977,RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ;
LLVM,NVPTX,1978,InstrInfo = new TargetInstrInfoImpl<TargetMachine>(*this);
LLVM,NVPTX,1979,addPass(create<ISA_LIT>LowerKernelArgsPass(&get<ISA_LIT>TargetMachine()));
LLVM,NVPTX,1980,RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ;
LLVM,NVPTX,1981,initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
LLVM,NVPTX,1982,TLOF = make_unique<ISA_LIT::TargetObjectFile>();
LLVM,NVPTX,1983,PM.add(createTargetTransformInfoPass(this));
LLVM,NVPTX,1984,TLOF = make_unique<TargetObjectFile>();
LLVM,NVPTX,1985,addPass(create<ISA_LIT>ImageOptimizerPass());
LLVM,NVPTX,1986,TLOF = llvm::make_unique<TargetObjectFile>();
LLVM,NVPTX,1987,
LLVM,NVPTX,1988,TargetPassConfig::addIRPasses();
LLVM,NVPTX,1989,InstrInfo = new TargetInstrInfoImpl<TargetMachine>(*this);
LLVM,NVPTX,1990,InstrInfo = new TargetInstrInfoImpl<TargetMachine>(*this);
LLVM,NVPTX,1991,"LLVMTargetMachine::LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL)"
LLVM,NVPTX,1992,"LLVMTargetMachine::LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL)"
LLVM,NVPTX,1993,initialize<ISA_LIT>ConstantPropagationPass( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,NVPTX,1994,TargetPassConfig::addIRPasses();
LLVM,NVPTX,1995,disablePass ( & MachineCopyPropagationID ) ;
LLVM,NVPTX,1996,addPass(create<ISA_LIT>ImageOptimizerPass());
LLVM,NVPTX,1997,Some possible next statements could be:
LLVM,NVPTX,1998,return *this;
LLVM,NVPTX,1999,RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ;
LLVM,NVPTX,2000,addPass(create<ISA_LIT>LowerArgsPass(&get<ISA_LIT>TargetMachine()));
LLVM,NVPTX,2001,addPass(create<ISA_LIT>ImageOptimizerPass())`
LLVM,NVPTX,2002,
LLVM,NVPTX,2003,addPass(create<ISA_LIT>GlobalOptimizerPass());
LLVM,NVPTX,2004,addPass(createNVVMReflectPass(ST.getSmVersion()));
LLVM,NVPTX,2005,return PR;
LLVM,NVPTX,2006,addPass(create<ISA_LIT>ImageOptimizerPass());
LLVM,NVPTX,2007,addPass(create<ISA_LIT>DeadCodeEliminationPass());
LLVM,NVPTX,2008,addPass(createDeadCodeEliminationPass());
LLVM,NVPTX,2009,addPass(create<ISA_LIT>DeadCodeEliminationPass());
LLVM,NVPTX,2010,addPass(create<ISA_LIT>LowerArgsPass(&get<ISA_LIT>TargetMachine()));
LLVM,NVPTX,2011,
LLVM,NVPTX,2012,return true;
LLVM,NVPTX,2013,return getSubtargetImpl()->getFrameLowering()->someMethod();
LLVM,NVPTX,2014,
LLVM,NVPTX,2015,
LLVM,NVPTX,2016,
LLVM,NVPTX,2017,return const_cast<ManagedStringPool*>(&ManagedStrPool);
LLVM,NVPTX,2018,return getSubtargetImpl().getRegisterInfo();
LLVM,NVPTX,2019,return getSubtargetImpl().getSelectionDAGInfo();
LLVM,NVPTX,2020,return getSubtargetImpl().getSelectionDAGInfo();
LLVM,NVPTX,2021,
LLVM,NVPTX,2022,return *Subtarget;
LLVM,NVPTX,2023,
LLVM,NVPTX,2024,
LLVM,NVPTX,2025,DwarfStrSection = new <ISA_LIT>Section(MCSection::SV
LLVM,NVPTX,2026,
LLVM,NVPTX,2027,
LLVM,NVPTX,2028,
LLVM,NVPTX,2029,Here are a few possibilities for what the next statement could be:
LLVM,NVPTX,2030,"MCSection *section = getSectionForConstant(DL, Kind"
LLVM,NVPTX,2031,"MCSection *section = getSectionForConstant(DL, Kind"
LLVM,NVPTX,2032,
LLVM,NVPTX,2033,TargetObjectFile ( ) : TargetLoweringObjectFile ( ) {
LLVM,NVPTX,2034,TargetObjectFile ( ) : TargetLoweringObjectFile ( ) {
LLVM,NVPTX,2035,"DwarfDebugSection = new <ISA_LIT>Section(MCSection::SV_ELF, SectionKind::getMetadata());"
LLVM,NVPTX,2036,
LLVM,NVPTX,2037,
LLVM,NVPTX,2038,"MCSection * section = getSectionForConstant(Kind, C, Align, GO"
LLVM,NVPTX,2039,
LLVM,NVPTX,2040,
LLVM,NVPTX,2041,return DataSection;
LLVM,NVPTX,2042,
LLVM,NVPTX,2043,"DwarfRangesSection = new <ISA_LIT>Section(MCSection::SV_ELF, SectionKind::getMetadata());"
LLVM,NVPTX,2044,
LLVM,NVPTX,2045,
LLVM,NVPTX,2046,
LLVM,NVPTX,2047,delete DwarfStrSection;
LLVM,NVPTX,2048,
LLVM,NVPTX,2049,Here are a few possibilities for what the next statement could be:
LLVM,NVPTX,2050,Here are a few possibilities for what the next statement could be: 2
LLVM,NVPTX,2051,
LLVM,NVPTX,2052,
LLVM,NVPTX,2053,
LLVM,NVPTX,2054,
LLVM,NVPTX,2055,
LLVM,NVPTX,2056,OS << <STR_LIT>;
LLVM,NVPTX,2057,
LLVM,NVPTX,2058,
LLVM,NVPTX,2059,
LLVM,NVPTX,2060,return false;
LLVM,NVPTX,2061,
LLVM,NVPTX,2062,Here is an example of what the next statement might look like: ```
LLVM,NVPTX,2063,Here is an example of what the next statement might look like: ```
LLVM,NVPTX,2064,getStreamer().EmitRawText(S.data());
LLVM,NVPTX,2065,OS << <STR_LIT>;
LLVM,NVPTX,2066,"Section -> PrintSwitchToSection ( * getStreamer ( ) . getContext ( ) . getAsmInfo ( ) , FI -> getTargetTriple ( ) , OS , SubSection ) ;"
LLVM,NVPTX,2067,
LLVM,NVPTX,2068,"getStreamer().EmitRawText("""");"
LLVM,NVPTX,2069,
LLVM,NVPTX,2070,
LLVM,NVPTX,2071,
LLVM,NVPTX,2072,Str.clear();
LLVM,NVPTX,2073,"Section -> PrintSwitchToSection ( * getStreamer ( ) . getContext ( ) . getAsmInfo ( ) , getStreamer ( ) . getContext ( ) . getTargetTriple ( ) , OS , SubSection ) ;"
LLVM,NVPTX,2074,
LLVM,NVPTX,2075,"getStreamer().emitRawText("""");"
LLVM,NVPTX,2076,OS << Label;
LLVM,NVPTX,2077,
LLVM,NVPTX,2078,getStreamer().emitRawText(S);
LLVM,NVPTX,2079,getStreamer().emitRawText(S);
LLVM,NVPTX,2080,
LLVM,NVPTX,2081,Some possible next statements could include:
LLVM,NVPTX,2082,BaseT::BaseT(std::move(static_cast<BaseT&>(Arg)));
LLVM,NVPTX,2083,BaseT::BaseT(std::move(static_cast<BaseT&>(Arg)));
LLVM,NVPTX,2084,
LLVM,NVPTX,2085,The
LLVM,NVPTX,2086,Here are a few possibilities for the next statement:
LLVM,NVPTX,2087,
LLVM,NVPTX,2088,"return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);"
LLVM,NVPTX,2089,Some possible next statements could include:
LLVM,NVPTX,2090,
LLVM,NVPTX,2091,UP obj = new UP();
LLVM,NVPTX,2092,
LLVM,NVPTX,2093,
LLVM,NVPTX,2094,
LLVM,NVPTX,2095,"explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM ) : BaseT ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( ST -> getTargetLowering ( ) ) {"
LLVM,NVPTX,2096,"explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM ) : BaseT ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( ST -> getTargetLowering ( ) ) {"
LLVM,NVPTX,2097,"However, based on the name of the function and the parameters it takes, it is likely that the function is intended to simplify an action by removing unnecessary requirements or constraints. The `IID` parameter is likely an identifier for the action being simplified, and the `FtzRequirement` parameter is"
LLVM,NVPTX,2098,"However, based on the name of the function and the parameters it takes, it is likely that the function is intended to simplify an action by removing unnecessary requirements or constraints. The `IID` parameter is likely an identifier for the action being simplified, and the `FtzRequirement` parameter is"
LLVM,NVPTX,2099,"case <STR_LIT> : return { Instruction :: FAdd , FTZ_Any } ;"
LLVM,NVPTX,2100,
LLVM,NVPTX,2101,
LLVM,NVPTX,2102,
LLVM,NVPTX,2103,if (Action.FtzRequirement != FTZ_Any) {
LLVM,NVPTX,2104,
LLVM,NVPTX,2105,return AS != AddressSpace::ADDRESS_SPACE_SHARED && AS != AddressSpace::ADDRESS_SPACE_LOCAL && AS != AddressSpace::ADDRESS_SPACE_PARAM;
LLVM,NVPTX,2106,return new ImmutablePass(TM);
LLVM,NVPTX,2107,
LLVM,NVPTX,2108,AU.setPreservesAll();
LLVM,NVPTX,2109,TargetTransformInfo *TTI = ...;
LLVM,NVPTX,2110,"return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ;"
LLVM,NVPTX,2111,
LLVM,NVPTX,2112,
LLVM,NVPTX,2113,
LLVM,NVPTX,2114,popTTIStack ( this ) ;
LLVM,NVPTX,2115,* `ISA_LIT` is a macro that expands to the name of the instruction set architecture (ISA) being targeted.
LLVM,NVPTX,2116,
LLVM,NVPTX,2117,
LLVM,NVPTX,2118,
LLVM,NVPTX,2119,
LLVM,NVPTX,2120,
LLVM,NVPTX,2121,
LLVM,NVPTX,2122,
LLVM,NVPTX,2123,UP.Partial = UP.Runtime = true;
LLVM,NVPTX,2124,
LLVM,NVPTX,2125,"return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace);"
LLVM,NVPTX,2126,"Given that the function takes a `ChainSizeInBytes` parameter, it is likely that the function is checking whether a store chain of a certain size is legal to vectorize. The `Alignment` parameter may indicate the alignment of the store chain, and the `AddrSpace` parameter may indicate the address space in which the"
LLVM,NVPTX,2127,
LLVM,NVPTX,2128,"memcpy(encoded, temp64.a, sizeof(temp64.a));"
LLVM,NVPTX,2129,
LLVM,NVPTX,2130,
LLVM,NVPTX,2131,"cacheAnnotationFromMD(m, gv);"
LLVM,NVPTX,2132,return false;
LLVM,NVPTX,2133,
LLVM,NVPTX,2134,
LLVM,NVPTX,2135,
LLVM,NVPTX,2136,
LLVM,NVPTX,2137,
LLVM,NVPTX,2138,
LLVM,NVPTX,2139,"return findOneNVVMAnnotation(&F, <STR_LIT>, x);"
LLVM,NVPTX,2140,
LLVM,NVPTX,2141,
LLVM,NVPTX,2142,
LLVM,NVPTX,2143,
LLVM,NVPTX,2144,
LLVM,NVPTX,2145,
LLVM,NVPTX,2146,* `assert`: This is a keyword in Python that is used to assert that a certain condition is true.
LLVM,NVPTX,2147,
LLVM,NVPTX,2148,return std::string(val.getName());
LLVM,NVPTX,2149,
LLVM,NVPTX,2150,return isImageReadOnly ( val ) || isImageWriteOnly ( val ) || isImageReadWrite ( val ) ;
LLVM,NVPTX,2151,
LLVM,NVPTX,2152,const Function * func = arg->getParent();
LLVM,NVPTX,2153,
LLVM,NVPTX,2154,return false;
LLVM,NVPTX,2155,if (val.isWriteOnly
LLVM,NVPTX,2156,return (x == <NUM_LIT>);
LLVM,NVPTX,2157,
LLVM,NVPTX,2158,const Function * func = arg->getParent();
LLVM,NVPTX,2159,const Function * func = arg->getParent();
LLVM,NVPTX,2160,
LLVM,NVPTX,2161,
LLVM,NVPTX,2162,return;
LLVM,NVPTX,2163,Here are a few possibilities for what the next statement might be:
LLVM,NVPTX,2164,"cacheAnnotationFromMD(elem, tmp);"
LLVM,NVPTX,2165,* `it` is an iterator that points to the first element of the container `F`.
LLVM,NVPTX,2166,
LLVM,NVPTX,2167,"cacheAnnotationFromMD(m, gv);"
LLVM,NVPTX,2168,retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] ;
LLVM,NVPTX,2169,return false;
LLVM,NVPTX,2170,
LLVM,NVPTX,2171,"x = llvm::findOneNVVMAnnotation(&F, llvm::PropertyAnnotationNames[llvm::PROPERTY_MAXNTID_X], x);"
LLVM,NVPTX,2172,
LLVM,NVPTX,2173,"y = llvm::findOneNVVMAnnotation(&F, llvm::PropertyAnnotationNames[llvm::PROPERTY_MAXNTID_Y], y);"
LLVM,NVPTX,2174,
LLVM,NVPTX,2175,
LLVM,NVPTX,2176,
LLVM,NVPTX,2177,return <NUM_LIT>;
LLVM,NVPTX,2178,return B->getParent();
LLVM,NVPTX,2179,
LLVM,NVPTX,2180,"* `llvm::findOneNVVMAnnotation` is a function that takes a pointer to a `llvm::Function` object, a string representing the name of the annotation to search for, and a pointer to a `llvm::Value` object."
LLVM,NVPTX,2181,
LLVM,NVPTX,2182,
LLVM,NVPTX,2183,
LLVM,NVPTX,2184,return llvm::isImageReadOnly(val) || llvm::isImageWriteOnly(val);
LLVM,NVPTX,2185,if (func->hasReadOnlyAttr()) {
LLVM,NVPTX,2186,return false;
LLVM,NVPTX,2187,
LLVM,NVPTX,2188,return true;
LLVM,NVPTX,2189,
LLVM,NVPTX,2190,return true;
LLVM,NVPTX,2191,if (tmp.empty()) return;
LLVM,NVPTX,2192,( * annotationCache ) [ m ] [ gv ] = std :: move ( tmp1 ) ;
LLVM,NVPTX,2193,const Annotation * ann = m->getAnnotation(prop);
LLVM,NVPTX,2194,retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ;
LLVM,NVPTX,2195,return false;
LLVM,NVPTX,2196,* `assert`: This is a keyword in Python that is used to assert that a certain condition is true.
LLVM,NVPTX,2197,return val.getName();
LLVM,NVPTX,2198,
LLVM,NVPTX,2199,if ( tmp.empty() ) return;
LLVM,NVPTX,2200,( * annotationCache ) [ m ] [ gv ] = tmp ;
LLVM,NVPTX,2201,
LLVM,NVPTX,2202,return true;
LLVM,NVPTX,2203,return (x == <NUM_LIT>);
LLVM,NVPTX,2204,return false;
LLVM,NVPTX,2205,return false;
LLVM,NVPTX,2206,const AnnotationDescriptor * ad = (*annotationCache)[m][gv];
LLVM,NVPTX,2207,
LLVM,NVPTX,2208,retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ;
LLVM,NVPTX,2209,"cacheAnnotationFromMD(m, gv);"
LLVM,NVPTX,2210,return false;
LLVM,NVPTX,2211,return false;
LLVM,NVPTX,2212,
LLVM,NVPTX,2213,const Function * func = arg->getParent();
LLVM,NVPTX,2214,tmp.push_back(entity);
LLVM,NVPTX,2215,( * annotationCache ) [ m ] [ gv ] = std :: move ( tmp ) ;
LLVM,NVPTX,2216,align = alignNode->getConstantAsInt();`
LLVM,NVPTX,2217,align = v >> <NUM_LIT>;
LLVM,NVPTX,2218,
LLVM,NVPTX,2219,retval[keyname].push_back(Val->getZExtValue());
LLVM,NVPTX,2220,V = GEP -> getPointerOperand() -> stripPointerCasts(); continue;
LLVM,NVPTX,2221,const Value * common = <NUM_LIT>;
LLVM,NVPTX,2222,( * annotationCache ) [ m ] [ gv ] = std :: move ( tmp ) ;
LLVM,NVPTX,2223,"BasicBlock * BB = getBasicBlock ( F , blockName ) ;"
LLVM,NVPTX,2224,
LLVM,NVPTX,2225,
LLVM,NVPTX,2226,if (I) {
LLVM,NVPTX,2227,visited.insert(v);
LLVM,NVPTX,2228,
LLVM,NVPTX,2229,F->getParent()->dump();
LLVM,NVPTX,2230,"cacheAnnotationFromMD(m, gv);"
LLVM,NVPTX,2231,retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ;
LLVM,NVPTX,2232,retval = ( * annotationCache ) [ m ] [ gv ] [ prop ] [ <NUM_LIT> ] ;
LLVM,NVPTX,2233,Here's why:
LLVM,NVPTX,2234,Instruction *I = &*it;
LLVM,NVPTX,2235,
LLVM,NVPTX,2236,
LLVM,NVPTX,2237,
LLVM,NVPTX,2238,
LLVM,NVPTX,2239,"* The `llvm::getMaxNTIDz` function takes two arguments: a `const Function&` reference to a LLVM function, and an `unsigned&` reference to an integer variable."
LLVM,NVPTX,2240,"x = llvm::findOneNVVMAnnotation(&F, llvm::PropertyAnnotationNames[llvm::PROPERTY_MINNCTAPERSM], x);"
LLVM,NVPTX,2241,
LLVM,NVPTX,2242,
LLVM,NVPTX,2243,return B->getParent();
LLVM,NVPTX,2244,
LLVM,NVPTX,2245,"llvm::findOneNVVMAnnotation(&F, llvm::PropertyAnnotationNames[llvm::PROPERTY_REQNTID_Z], z);"
LLVM,NVPTX,2246,
LLVM,NVPTX,2247,
LLVM,NVPTX,2248,return ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) || ( id == <STR_LIT> ) ;
LLVM,NVPTX,2249,return true;
LLVM,NVPTX,2250,
LLVM,NVPTX,2251,
LLVM,NVPTX,2252,return (x == <NUM_LIT>);
LLVM,NVPTX,2253,assert(annot == <NUM_LIT> && <STR_LIT>);
LLVM,NVPTX,2254,return id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> || id == <STR_LIT> ;
LLVM,NVPTX,2255,return true;
LLVM,NVPTX,2256,return true;
LLVM,NVPTX,2257,
LLVM,NVPTX,2258,
LLVM,NVPTX,2259,temp64.a[i] = str[e - 1 - i];
LLVM,NVPTX,2260,return true;
LLVM,NVPTX,2261,
LLVM,NVPTX,2262,void initializeNVVMIntrRangePass(PassRegistry &passRegistry) {
LLVM,NVPTX,2263,NVVMIntrRangePass::NVVMIntrRangePass(NVVMIntrRangeSM) {
LLVM,NVPTX,2264,NVVMIntrRangePass::NVVMIntrRangePass(NVVMIntrRangeSM) {
LLVM,NVPTX,2265,
LLVM,NVPTX,2266,
LLVM,NVPTX,2267,
LLVM,NVPTX,2268,
LLVM,NVPTX,2269,
LLVM,NVPTX,2270,IntegerType * Int64Ty = Type::getInt64Ty(Context);
LLVM,NVPTX,2271,case <STR_LIT> :
LLVM,NVPTX,2272,switch (Callee->getIntrinsicID()) {
LLVM,NVPTX,2273,"C->setMetadata(LLVMContext::MD_range, MDNode::get(Context, LowAndHigh));"
LLVM,NVPTX,2274,MaxBlockSize . x = <NUM_LIT> ;
LLVM,NVPTX,2275,
LLVM,NVPTX,2276,"case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> , Call ) ;"
LLVM,NVPTX,2277,NVVMReflect reflect(ID);
LLVM,NVPTX,2278,ReflectVal = Flag -> getSExtValue ( ) ;
LLVM,NVPTX,2279,const Value * Str = Call -> getArgOperand ( <NUM_LIT> ) ;
LLVM,NVPTX,2280,ReflectFunction = nullptr;
LLVM,NVPTX,2281,
LLVM,NVPTX,2282,return new NVVMReflect(SmVersion);
LLVM,NVPTX,2283,return new NVVMReflect(SmVersion);
LLVM,NVPTX,2284,"NVVMReflect::NVVMReflect(unsigned int Sm) : FunctionPass(ID), SmVersion(Sm) {"
LLVM,NVPTX,2285,NVVMReflectPass::NVVMReflectPass(<NUM_LIT>)
LLVM,NVPTX,2286,NVVMReflectPass::NVVMReflectPass(<NUM_LIT>)
LLVM,NVPTX,2287,
LLVM,NVPTX,2288,ReflectVal = VarMap[ReflectArg];
LLVM,NVPTX,2289,ReflectVal = VarMap[ReflectArg];
LLVM,NVPTX,2290,
LLVM,NVPTX,2291,"Call->replaceAllUsesWith(ConstantInt::get(Call->getType(), ReflectVal));"
LLVM,NVPTX,2292,
LLVM,NVPTX,2293,initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
LLVM,NVPTX,2294,assert(ReflectArg.size() > 0 && <STR_LIT>);
LLVM,NVPTX,2295,ToRemove.push_back(Call);
LLVM,NVPTX,2296,
LLVM,NVPTX,2297,initializeNVVMReflectPass(PassRegistry::getPassRegistry());
LLVM,NVPTX,2298,if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(Operand)) {
LLVM,NVPTX,2299,VarMap[NameValPair[1]] = Val;
LLVM,NVPTX,2300,"Reflect -> replaceAllUsesWith(ConstantInt::get(Reflect->getType(), ReflectVal));"
LLVM,NVPTX,2301,
LLVM,NVPTX,2302,
LLVM,NVPTX,2303,
LLVM,NVPTX,2304,
LLVM,NVPTX,2305,if (ToRemove.size() == <NUM_LIT>) return false;
LLVM,NVPTX,2306,Here's a breakdown of the code:
LLVM,NVPTX,2307,for (; I != E; ++I) {
LLVM,NVPTX,2308,"Tys[0] = PointerType::get(I8Ty, 0);"
LLVM,NVPTX,2309,ReflectFunction = M.getFunction(NVVM_REFLECT_FUNCTION);
LLVM,NVPTX,2310,ValStream >> Val;
LLVM,NVPTX,2311,
LLVM,NVPTX,2312,"for (unsigned j = <NUM_LIT>, e = allOperands.size(); j != e; ++j) {"
LLVM,NVPTX,2313,for (unsigned j = 0; j < e; ++j) {
LLVM,NVPTX,2314,
LLVM,NVPTX,2315,"copy->setOperand(<NUM_LIT>, scalarRegs[0]);"
LLVM,NVPTX,2316,copy -> RemoveOperand(<NUM_LIT>);
LLVM,NVPTX,2317,"copies.push_back(BuildMI(F, DL, InstrInfo->get(getScalarVersion(Instr)), dest[i]).addOperand(Instr->getOperand(<NUM_LIT> + i)));"
LLVM,NVPTX,2318,
LLVM,NVPTX,2319,
LLVM,NVPTX,2320,
LLVM,NVPTX,2321,copy.addReg(src1[elem]);
LLVM,NVPTX,2322,
LLVM,NVPTX,2323,for (unsigned i = 0; i < numcopies; ++i) {
LLVM,NVPTX,2324,dest.setOpcode(<OPCODE>);
LLVM,NVPTX,2325,copy->RemoveOperand(<NUM_LIT>);
LLVM,NVPTX,2326,"for (unsigned i = <NUM_LIT>, e = otherOperands.size(); i != e; ++i) copy->addOperand(otherOperands[i]);"
LLVM,NVPTX,2327,"copy->setOperand(<NUM_LIT>, scalarRegs[0]);"
LLVM,NVPTX,2328,copy -> addOperand ( dest [ i ] ) ;
LLVM,NVPTX,2329,
LLVM,NVPTX,2330,copies.push_back(F.CloneMachineInstr(Instr));
LLVM,NVPTX,2331,copy->RemoveOperand(<NUM_LIT>);
LLVM,NVPTX,2332,"copy->addOperand(MachineOperand::CreateReg(src[which.getImm()], false));"
LLVM,NVPTX,2333,copies.push_back(copy);
LLVM,NVPTX,2334,"MachineInstr * copy = BuildMI(F, DL, InstrInfo->get(getScalarVersion(Instr)), dest[i]);"
LLVM,NVPTX,2335,"copy->addOperand(MachineOperand::CreateReg(src1[elem], false));"
LLVM,NVPTX,2336,"MachineInstr * copy = BuildMI(F, DL, InstrInfo->get(getScalarVersion(Instr)), dest[i]);"
LLVM,NVPTX,2337,
LLVM,NVPTX,2338,
LLVM,NVPTX,2339,
LLVM,NVPTX,2340,
LLVM,NVPTX,2341,return get<ISA_LIT>ElemClass ( RC ) ;
LLVM,NVPTX,2342,VectorToScalarMap[regnum] = temp;
LLVM,NVPTX,2343,return isVectorRegister(dest.getReg());
LLVM,NVPTX,2344,
LLVM,NVPTX,2345,Here are a few possibilities for what the next statement could be:
LLVM,NVPTX,2346,return get<ISA_LIT>VectorSize ( MRI -> getRegClass ( regnum ) ) ;
LLVM,NVPTX,2347,if (numDefs == <NUM_LIT>) {
LLVM,NVPTX,2348,"for (unsigned i = 0, e = deadMoves.size(); i != e; ++i) {"
LLVM,NVPTX,2349,
LLVM,NVPTX,2350,elementize(F);
LLVM,NVPTX,2351,
LLVM,NVPTX,2352,
LLVM,RISCV,0,return (Val & ~0x0000000000000000) == 0x0000000000000000;
LLVM,RISCV,1,return (Val & ~0x0000000000000000) == 0x0000000000000000;
LLVM,RISCV,2,return (Val & ~ <NUM_LIT>) == <NUM_LIT>;
LLVM,RISCV,3,
LLVM,RISCV,4,return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;
LLVM,RISCV,5,return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;
LLVM,RISCV,6,return (Val & ~ <NUM_LIT>) == <NUM_LIT>;
LLVM,RISCV,7,return (Val & ~ <NUM_LIT>) == <NUM_LIT>;
LLVM,RISCV,8,return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;
LLVM,RISCV,9,
LLVM,RISCV,10,
LLVM,RISCV,11,
LLVM,RISCV,12,
LLVM,RISCV,13,
LLVM,RISCV,14,
LLVM,RISCV,15,
LLVM,RISCV,16,
LLVM,RISCV,17,Some possible next statements could include:
LLVM,RISCV,18,Some possible next statements could include:
LLVM,RISCV,19,
LLVM,RISCV,20,
LLVM,RISCV,21,
LLVM,RISCV,22,"return create<ISA_LIT>ELFObjectWriter(OS, OSABI, Is64Bit);"
LLVM,RISCV,23,* `uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;`: This line retrieves the OS ABI (Application Binary Interface) value for the current target using the `getOSABI` method of the `MCEL
LLVM,RISCV,24,
LLVM,RISCV,25,const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override {
LLVM,RISCV,26,Here are a few possibilities for what the next statement could be:
LLVM,RISCV,27,MCInst & Res = Inst.relax(STI);
LLVM,RISCV,28,
LLVM,RISCV,29,
LLVM,RISCV,30,OW -> write32(<NUM_LIT>);
LLVM,RISCV,31,"However, based on the name of the method and the parameters it takes, it is likely that the method is intended to write a sequence of NOP (no-operation) instructions to the output file. The `Count` parameter specifies the number of NOP instructions to write, and the `OW` parameter is a pointer to a `MCObjectWriter` object that is used"
LLVM,RISCV,32,
LLVM,RISCV,33,if (Info.TargetOffset > 0) {
LLVM,RISCV,34,Infos[0
LLVM,RISCV,35,
LLVM,RISCV,36,
LLVM,RISCV,37,
LLVM,RISCV,38,return STI->getFeatureBits()[<STR_LIT>];
LLVM,RISCV,39,
LLVM,RISCV,40,
LLVM,RISCV,41,
LLVM,RISCV,42,
LLVM,RISCV,43,return Infos[Kind - FirstTargetFixupKind];
LLVM,RISCV,44,The
LLVM,RISCV,45,Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xFF);
LLVM,RISCV,46,uint8
LLVM,RISCV,47,"return new <ISA_LIT>AsmBackend(T, STI, MRI, Options);"
LLVM,RISCV,48,if ( ! AUIPCTarget . getSymA ( ) || AUIPCTarget . getSymB ( ) ) return false ;
LLVM,RISCV,49,
LLVM,RISCV,50,"Type = llvm::StringSwitch<unsigned>(Name).Case(<STR_LIT>, ELF::R_<ISA_LIT>_NONE).Case(<STR_LIT>, ELF::R_<ISA_LIT>_32).Case(<STR_LIT>, ELF::R_<ISA_LIT>_64).Default(-<NUM_LIT>);"
LLVM,RISCV,51,
LLVM,RISCV,52,assert(Layout.getAssembler().getContext().getAsmInfo()->getMinInstAlignment() == <NUM_LIT> && <STR_LIT>);
LLVM,RISCV,53,
LLVM,RISCV,54,
LLVM,RISCV,55,Res.addOperand(Inst.getOperand(<NUM_LIT>));
LLVM,RISCV,56,return STI.getFeatureBits()[<STR_LIT>] || ForceRelocs;
LLVM,RISCV,57,bool HasStdExtC = STI
LLVM,RISCV,58,"Ctx.addFixup(MCExpr::create(AF.getContents().size(), Ctx), MCExpr::create(Count, Ctx), MCFixupKind(MCFixupKind::FK_CodeAlign));"
LLVM,RISCV,59,Asm.addFixup (Fixup);
LLVM,RISCV,60,if (Count % MinNopLen != 0) return false;
LLVM,RISCV,61,if (HasStdExtC) {
LLVM,RISCV,62,if (HasStdExtC) {
LLVM,RISCV,63,
LLVM,RISCV,64,
LLVM,RISCV,65,
LLVM,RISCV,66,Size = AF.getAlignment() - MinNopLen;
LLVM,RISCV,67,
LLVM,RISCV,68,
LLVM,RISCV,69,MCInst & Res = Inst.relax(STI);
LLVM,RISCV,70,
LLVM,RISCV,71,
LLVM,RISCV,72,
LLVM,RISCV,73,
LLVM,RISCV,74,case <STR_LIT> : return <STR_LIT> ;
LLVM,RISCV,75,
LLVM,RISCV,76,case FK_Data_1: case FK_Data_2: case FK_Data_4: case FK_Data_8:
LLVM,RISCV,77,
LLVM,RISCV,78,"case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT>"
LLVM,RISCV,79,
LLVM,RISCV,80,"case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup ."
LLVM,RISCV,81,
LLVM,RISCV,82,
LLVM,RISCV,83,if (Info.Flags & MCFixupKindInfo::FKF_IsPCRel) {
LLVM,RISCV,84,"return create<ISA_LIT>ELFObjectWriter(OS, OSABI, Is64Bit);"
LLVM,RISCV,85,
LLVM,RISCV,86,
LLVM,RISCV,87,Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xFF);
LLVM,RISCV,88,Data[Offset + i] = <STR_LIT>[i % <STR_LIT>.size()];
LLVM,RISCV,89,"MCAsmBackend *backend = llvm::create<ISA_LIT>AsmBackend(T, STI, MRI, Options);"
LLVM,RISCV,90,
LLVM,RISCV,91,return Infos[Kind - FirstTargetFixupKind];
LLVM,RISCV,92,return <NUM_LIT>;
LLVM,RISCV,93,return Value;
LLVM,RISCV,94,
LLVM,RISCV,95,
LLVM,RISCV,96,
LLVM,RISCV,97,"MCAsmBackend::MCAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)"
LLVM,RISCV,98,"MCAsmBackend::MCAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, const MCTargetOptions &Options)"
LLVM,RISCV,99,return MCAsmBackend::getFixupKindInfo(Kind);
LLVM,RISCV,100,case <STR_LIT>:
LLVM,RISCV,101,
LLVM,RISCV,102,
LLVM,RISCV,103,for ( uint64_t i = Nop16Count ; i != <NUM_LIT> ; -- i ) OW -> write16 ( <NUM_LIT> ) ;
LLVM,RISCV,104,
LLVM,RISCV,105,
LLVM,RISCV,106,"Asm.getStreamer().EmitValue(NopBytes, Fixup, SMLoc());"
LLVM,RISCV,107,"Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes, FixedValue);"
LLVM,RISCV,108,
LLVM,RISCV,109,case <STR_LIT> : ShouldForce = T -> getValue ( ) -> findAssociatedFragment ( ) != Fixup . getValue ( ) -> findAssociatedFragment ( ) ; break ;
LLVM,RISCV,110,unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;
LLVM,RISCV,111,
LLVM,RISCV,112,
LLVM,RISCV,113,"case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >>"
LLVM,RISCV,114,for (unsigned i = 0; i < NumBytes; ++i) {
LLVM,RISCV,115,"return create<ISA_LIT>ELFObjectWriter(OSABI, Is64Bit);"
LLVM,RISCV,116,uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
LLVM,RISCV,117,
LLVM,RISCV,118,case <STR_LIT> :
LLVM,RISCV,119,
LLVM,RISCV,120,
LLVM,RISCV,121,return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
LLVM,RISCV,122,
LLVM,RISCV,123,if (ShouldForce) { ... }
LLVM,RISCV,124,
LLVM,RISCV,125,if ( ( Count % MinNopLen ) != <NUM_LIT> ) return false ;
LLVM,RISCV,126,Inst.addOperand(MCOperand::createImm(Expr->getValue()));
LLVM,RISCV,127,Inst.addOperand(MCOperand::createImm(Expr));
LLVM,RISCV,128,Inst.addOperand(MCOperand::createImm(N));
LLVM,RISCV,129,
LLVM,RISCV,130,assert ( N == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,131,"Op = make_unique < <ISA_LIT>Operand > ( KindImm , StartLoc , EndLoc ) ;"
LLVM,RISCV,132,return Op;
LLVM,RISCV,133,Op->Mem.Disp = Disp;
LLVM,RISCV,134,
LLVM,RISCV,135,return Op;
LLVM,RISCV,136,
LLVM,RISCV,137,return Imm;
LLVM,RISCV,138,return Reg;
LLVM,RISCV,139,
LLVM,RISCV,140,
LLVM,RISCV,141,return Value >= MinValue && Value <= MaxValue;
LLVM,RISCV,142,
LLVM,RISCV,143,return isReg(FP128Reg);
LLVM,RISCV,144,return isReg(FP32Reg) && (getRegType() == FP32Reg);
LLVM,RISCV,145,
LLVM,RISCV,146,
LLVM,RISCV,147,else {
LLVM,RISCV,148,return ( Kind == KindMem && Mem . RegKind == RegKind && ( HasIndex || ! Mem . Index ) ) ;
LLVM,RISCV,149,"return isMem(RegKind, HasIndex) && inRange(Mem.Disp, -20, 20);"
LLVM,RISCV,150,
LLVM,RISCV,151,
LLVM,RISCV,152,
LLVM,RISCV,153,return isReg(PCR64Reg);
LLVM,RISCV,154,return isReg(PCR64Reg);
LLVM,RISCV,155,
LLVM,RISCV,156,
LLVM,RISCV,157,
LLVM,RISCV,158,"return isImm( - <NUM_LIT>, <NUM_LIT> );"
LLVM,RISCV,159,"return isImm( - <NUM_LIT>, <NUM_LIT> );"
LLVM,RISCV,160,
LLVM,RISCV,161,
LLVM,RISCV,162,
LLVM,RISCV,163,
LLVM,RISCV,164,
LLVM,RISCV,165,
LLVM,RISCV,166,
LLVM,RISCV,167,"bool isImm(int min, int max) {"
LLVM,RISCV,168,
LLVM,RISCV,169,"RegisterMCAsmParser(Y, The<ISA_LIT>64Target);"
LLVM,RISCV,170,case Match_MnemonicFail:
LLVM,RISCV,171,ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ;
LLVM,RISCV,172,if (getLexer()->is(AsmToken::RParen)) {
LLVM,RISCV,173,return false;
LLVM,RISCV,174,
LLVM,RISCV,175,
LLVM,RISCV,176,
LLVM,RISCV,177,
LLVM,RISCV,178,
LLVM,RISCV,179,Here are a few possibilities:
LLVM,RISCV,180,
LLVM,RISCV,181,
LLVM,RISCV,182,"return Error(Loc, <STR_LIT>);"
LLVM,RISCV,183,
LLVM,RISCV,184,Operands.push_back(std::move(op));
LLVM,RISCV,185,RegNo = GR32Regs[Reg.Number];
LLVM,RISCV,186,llvm_unreachable(<STR_LIT>);
LLVM,RISCV,187,"MCTargetAsmParser::MCTargetAsmParser(Options, sti);"
LLVM,RISCV,188,MCAsmParserExtension::Initialize(Parser);
LLVM,RISCV,189,"StartLoc ( startLoc ) , EndLoc ( endLoc ) {"
LLVM,RISCV,190,"StartLoc ( startLoc ) , EndLoc ( endLoc ) {"
LLVM,RISCV,191,Inst.addOperand(MCOperand::createImm(SysReg.Encoding));
LLVM,RISCV,192,
LLVM,RISCV,193,Inst.addOperand(MCOperand::createImm(Imm));
LLVM,RISCV,194,
LLVM,RISCV,195,
LLVM,RISCV,196,for (unsigned i = 0; i < N; i++) {
LLVM,RISCV,197,
LLVM,RISCV,198,assert ( N == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,199,assert ( N == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,200,if (IsConstantImm) { ... }
LLVM,RISCV,201,
LLVM,RISCV,202,
LLVM,RISCV,203,return false;
LLVM,RISCV,204,
LLVM,RISCV,205,return Reg - <STR_LIT> + <STR_LIT>;
LLVM,RISCV,206,return Reg - <STR_LIT> + <STR_LIT>;
LLVM,RISCV,207,"return RI.getMatchingSuperReg(Reg, <STR_LIT>, &<ISA_LIT>MCRegisterClasses[RegClassID]);"
LLVM,RISCV,208,"Op = new Op(StartLoc, EndLoc, IsRV64);"
LLVM,RISCV,209,Op->setRegNo(RegNo);
LLVM,RISCV,210,
LLVM,RISCV,211,
LLVM,RISCV,212,Op -> EndLoc = E ;
LLVM,RISCV,213,Op->VType.Val = VTypeI;
LLVM,RISCV,214,"return <ISA_LIT>Operand :: createReg ( <STR_LIT> , llvm :: SMLoc ( ) , llvm :: SMLoc ( ) , isRV64 ( ) ) ;"
LLVM,RISCV,215,
LLVM,RISCV,216,
LLVM,RISCV,217,
LLVM,RISCV,218,
LLVM,RISCV,219,
LLVM,RISCV,220,
LLVM,RISCV,221,
LLVM,RISCV,222,
LLVM,RISCV,223,
LLVM,RISCV,224,"Out.emitRV64Inst(Inst, SecondOpcode, DestReg, SourceReg, ShAmt);"
LLVM,RISCV,225,"Out.emitExtend (DestReg, SourceReg, SignExtend, Width, IDLoc);"
LLVM,RISCV,226,if (Res) {
LLVM,RISCV,227,"emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(<NUM_LIT>)).addOperand(Inst.getOperand(<NUM_LIT>)).addOperand(Inst.getOperand(<NUM_LIT>)).addOperand(Inst.getOperand(<NUM_LIT>)));"
LLVM,RISCV,228,return RE -> evaluateAsConstant(CE);
LLVM,RISCV,229,
LLVM,RISCV,230,return EndLoc;
LLVM,RISCV,231,
LLVM,RISCV,232,
LLVM,RISCV,233,
LLVM,RISCV,234,
LLVM,RISCV,235,
LLVM,RISCV,236,
LLVM,RISCV,237,Kind = KindTy::Register;
LLVM,RISCV,238,FRM = SE.getSymbol().getName();
LLVM,RISCV,239,FRM = SE.getSymbol().getName();
LLVM,RISCV,240,
LLVM,RISCV,241,
LLVM,RISCV,242,return SysReg;
LLVM,RISCV,243,"return StringRef(SysReg.Data, SysReg.Length);"
LLVM,RISCV,244,
LLVM,RISCV,245,
LLVM,RISCV,246,return Kind;
LLVM,RISCV,247,if (IsConstantImm) {
LLVM,RISCV,248,"IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ;"
LLVM,RISCV,249,return false;
LLVM,RISCV,250,
LLVM,RISCV,251,
LLVM,RISCV,252,return false;
LLVM,RISCV,253,return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,254,Imm = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,255,
LLVM,RISCV,256,Prev = c;
LLVM,RISCV,257,if (Prev == '\0' || Prev == 'i' || Prev == 'o' || Prev == 'r' || Prev == 'w') {
LLVM,RISCV,258,StringRef Str = SVal->getSymbol()->getName();
LLVM,RISCV,259,if (SVal == nullptr) {
LLVM,RISCV,260,return isGPR( ) && IsGPRAsFPR;
LLVM,RISCV,261,if (isGPRAsFPR()) {
LLVM,RISCV,262,if (isGPR && IsGPRAsFPR) {
LLVM,RISCV,263,return isGPR( ) && IsGPRAsFPR && IsRV64;
LLVM,RISCV,264,
LLVM,RISCV,265,return isGPR() && IsGPRAsFPR && !IsRV64 && !((Reg.RegNum - <STR_LIT>) & <NUM_LIT>);
LLVM,RISCV,266,Imm = readInt64(MCExpr.getExpr());
LLVM,RISCV,267,"Next, the `VK` variable is checked to see if it is equal to the `MCExpr"
LLVM,RISCV,268,Imm = <ISA_LIT>MCExpr :: getImm ( VK ) ;
LLVM,RISCV,269,bool isMem ( ) const override { return false ; }
LLVM,RISCV,270,
LLVM,RISCV,271,return VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,272,
LLVM,RISCV,273,return false;
LLVM,RISCV,274,"return getSTI().hasFeature(""<STR_LIT>"");"
LLVM,RISCV,275,"return getSTI().hasFeature(""<STR_LIT>"");"
LLVM,RISCV,276,"return IsConstantImm && ( Imm != <NUM_LIT> ) && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;"
LLVM,RISCV,277,if (IsConstantImm) {
LLVM,RISCV,278,return IsConstantImm;
LLVM,RISCV,279,
LLVM,RISCV,280,
LLVM,RISCV,281,
LLVM,RISCV,282,return (getImm() & 0x1F) == 0;
LLVM,RISCV,283,
LLVM,RISCV,284,return (getImm() & 0x1F) == 0x1F;
LLVM,RISCV,285,VK = MCExpr::VK_<ISA_LIT>_None;
LLVM,RISCV,286,
LLVM,RISCV,287,
LLVM,RISCV,288,
LLVM,RISCV,289,
LLVM,RISCV,290,bool Token::isToken() const {
LLVM,RISCV,291,"return new Token(Kind.getKind(), Kind.getToken());"
LLVM,RISCV,292,return false;
LLVM,RISCV,293,if (IsConstantImm) { ... }
LLVM,RISCV,294,
LLVM,RISCV,295,
LLVM,RISCV,296,return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExp
LLVM,RISCV,297,return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExp
LLVM,RISCV,298,"IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) ;"
LLVM,RISCV,299,if (IsConstantImm) {
LLVM,RISCV,300,
LLVM,RISCV,301,return false;
LLVM,RISCV,302,if (IsConstantImm) {
LLVM,RISCV,303,
LLVM,RISCV,304,Imm = getImm ( ) ;
LLVM,RISCV,305,"return IsConstantImm && isShiftedUInt < <NUM_LIT>, <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;"
LLVM,RISCV,306,
LLVM,RISCV,307,
LLVM,RISCV,308,
LLVM,RISCV,309,
LLVM,RISCV,310,return (isRV64( ) && isUInt<NUM_LIT>(Imm)) || isUInt<NUM_LIT>(Imm);
LLVM,RISCV,311,return false;
LLVM,RISCV,312,return (isRV64( ) && isUInt<NUM_LIT>(Imm)) || isUInt<NUM_LIT>(Imm);
LLVM,RISCV,313,if (Imm != VK_<ISA_LIT>_None) {
LLVM,RISCV,314,return (isRV64() && isUInt<NUM_LIT>(Imm)) || isUInt<NUM_LIT>(Imm);
LLVM,RISCV,315,return (isRV64() && isUInt<NUM_LIT>(Imm)) || isUInt<NUM_LIT>(Imm);
LLVM,RISCV,316,"return Kind == KindTy :: Register && Reg . RegNum == ""r0"" ;"
LLVM,RISCV,317,
LLVM,RISCV,318,
LLVM,RISCV,319,
LLVM,RISCV,320,
LLVM,RISCV,321,return false;
LLVM,RISCV,322,Here is an example of what the next statement might look like:
LLVM,RISCV,323,if ( RegNo == <STR_LIT> ) RegNo = MatchRegisterAltName ( Name ) ;
LLVM,RISCV,324,const MCExpr * V = Sym -> getVariableValue ( false ) ;
LLVM,RISCV,325,return MatchOperand_NoMatch;
LLVM,RISCV,326,Twine Msg = <STR_LIT> <STR_LIT> ;
LLVM,RISCV,327,"Operands.push_back(<ISA_LIT>Operand::createSysReg(SysReg->Name, S, SysReg->Encoding, isRV64()));"
LLVM,RISCV,328,if (IDVal == <STR_LIT>)
LLVM,RISCV,329,"getTargetStreamer()->emitAttribute(Tag, IntegerValue);"
LLVM,RISCV,330,unsigned Opcode;
LLVM,RISCV,331,getTargetStreamer().emitDirectiveOptionPush();
LLVM,RISCV,332,return MatchOperand_NoMatch;
LLVM,RISCV,333,
LLVM,RISCV,334,return parseOperandWithModifier(Operands);
LLVM,RISCV,335,getParser().Lex()
LLVM,RISCV,336,"Operands.push_back(<ISA_LIT>Operand::createReg(RegNo, S, E, isRV64()));"
LLVM,RISCV,337,"Operands.push_back(<ISA_LIT>Operand::createToken(<STR_LIT>, getLoc(), isRV64()));"
LLVM,RISCV,338,"Operands.push_back(<ISA_LIT>Operand::createToken(<STR_LIT>, getLoc(), isRV64()));"
LLVM,RISCV,339,return false;
LLVM,RISCV,340,
LLVM,RISCV,341,"Operands.push_back(<ISA_LIT>Operand::createImm(Res, S, E, isRV64()));"
LLVM,RISCV,342,"Operands.push_back(<ISA_LIT>Operand::createToken(<STR_LIT>, getLoc(), isRV64()));"
LLVM,RISCV,343,getParser()->Lex();
LLVM,RISCV,344,if (getLexer().isNot(AsmToken::LParen)) {
LLVM,RISCV,345,ParserOptions = ParserOptionsStack.pop_back_val();
LLVM,RISCV,346,FeatureBitStack.pop_back_val()
LLVM,RISCV,347,
LLVM,RISCV,348,"If `Kind` is equal to `KindTy::Immediate`, then the code will execute the statement `OS << *getImm();`. If `Kind` is equal to `KindTy::Register`, then the code will execute the statement `OS << <STR_LIT> << RegName(getReg()) << <STR"
LLVM,RISCV,349,Feature
LLVM,RISCV,350,FeatureBitStack.push_back(FeatureBit(FeatureBitStack.size()));
LLVM,RISCV,351,if (ABIName.endswith(<STR_LIT>) && !getSTI().getFeatureBits()[<STR_LIT>]) { errs() << <STR_LIT> <STR_LIT> <STR_LIT>; } else if (ABIName.endswith(<STR_LIT>) && !getSTI().getFeatureBits()[<STR_LIT>]) { errs() << <STR_LIT> <STR_LIT> <STR_LIT>; } <ST
LLVM,RISCV,352,MCSubtargetInfo & STI = copySTI ( ) ;
LLVM,RISCV,353,"OperandMatchResultTy <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo ,"
LLVM,RISCV,354,getParser().Lex();
LLVM,RISCV,355,if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) {
LLVM,RISCV,356,if ( IsRegVR && ( Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8 ) ) {
LLVM,RISCV,357,
LLVM,RISCV,358,
LLVM,RISCV,359,MCOperand Symbol = Inst.getOperand(SymbolOpIdx);
LLVM,RISCV,360,
LLVM,RISCV,361,"emitToStreamer(Out, MCInstBuilder(Opcode).addOperand(Inst.getOperand(<NUM_LIT>)).addOperand(Inst.getOperand(<NUM_LIT>)).addOperand(Inst.getOperand(<NUM_LIT>)).addOperand(Inst.getOperand(<NUM_LIT>)));"
LLVM,RISCV,362,"Operands.push_back(ISA_LITOperand::createSysReg(SysReg->Name, S, Imm, isRV64()));"
LLVM,RISCV,363,return parseDirectiveOption();
LLVM,RISCV,364,
LLVM,RISCV,365,unsigned
LLVM,RISCV,366,Op.Reg.RegNum = convertFPR64ToFPR16(Reg);
LLVM,RISCV,367,Inst.addOperand(MCOperand::createExpr(Expr));
LLVM,RISCV,368,if (IsConstant) {
LLVM,RISCV,369,
LLVM,RISCV,370,
LLVM,RISCV,371,"emitToStreamer(Out, MCInstBuilder(<STR_LIT>).addReg(DestReg).addReg(DestReg).addImm(ShiftAmount));"
LLVM,RISCV,372,int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Value ) ;
LLVM,RISCV,373,Ret = true;
LLVM,RISCV,374,
LLVM,RISCV,375,
LLVM,RISCV,376,return false;
LLVM,RISCV,377,
LLVM,RISCV,378,```
LLVM,RISCV,379,"return IsConstantImm && ( Imm != <NUM_LIT> ) && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;"
LLVM,RISCV,380,return IsValid && (VK == MCExpr::VK_None || VK == MCExpr::VK_LO || VK == MCExpr::VK_PCREL_LO);
LLVM,RISCV,381,IsValid = isInt < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,382,
LLVM,RISCV,383,
LLVM,RISCV,384,"return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;"
LLVM,RISCV,385,
LLVM,RISCV,386,
LLVM,RISCV,387,"IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,388,"IsValid = <ISA_LIT>AsmParser::classifySymbolRef(getImm(), VK, Imm);"
LLVM,RISCV,389,return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,390,return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,391,
LLVM,RISCV,392,
LLVM,RISCV,393,```
LLVM,RISCV,394,```
LLVM,RISCV,395,
LLVM,RISCV,396,"return IsConstantImm && isShiftedUInt < <NUM_LIT>, <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;"
LLVM,RISCV,397,
LLVM,RISCV,398,return isUInt < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,399,getTargetStreamer().emitDirectiveOptionNoRVC();
LLVM,RISCV,400,Res = getParser ( ) . ParseExpr ( getLexer ( ) ) ;
LLVM,RISCV,401,if (getLexer().isNot(AsmToken::EndOfStatement)) {
LLVM,RISCV,402,return false;
LLVM,RISCV,403,return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ;
LLVM,RISCV,404,
LLVM,RISCV,405,"emitToStreamer(Out, Inst);"
LLVM,RISCV,406,
LLVM,RISCV,407,case Register:
LLVM,RISCV,408,
LLVM,RISCV,409,
LLVM,RISCV,410,StartLoc = Reg.StartLoc;
LLVM,RISCV,411,assert(Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT>);
LLVM,RISCV,412,"emitToStreamer(Out, MCInstBuilder(<STR_LIT>).addOperand(TmpReg).addExpr(RefToLinkTmpLabel));"
LLVM,RISCV,413,"emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel));"
LLVM,RISCV,414,
LLVM,RISCV,415,"Out . EmitSymbolRef ( Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) , IDLoc , DestReg ) ;"
LLVM,RISCV,416,"emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addImm ( Inst . Imm ) ) ;"
LLVM,RISCV,417,
LLVM,RISCV,418,"return StringRef ( SysReg . Data , SysReg . Length ) ;"
LLVM,RISCV,419,return SysReg;
LLVM,RISCV,420,"IsValid = AsmParser::classifySymbolRef(getImm(), VK, Imm);"
LLVM,RISCV,421,return false;
LLVM,RISCV,422,
LLVM,RISCV,423,
LLVM,RISCV,424,
LLVM,RISCV,425,return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA
LLVM,RISCV,426,return IsConstantImm;
LLVM,RISCV,427,
LLVM,RISCV,428,return false;
LLVM,RISCV,429,return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_
LLVM,RISCV,430,
LLVM,RISCV,431,
LLVM,RISCV,432,RegNo = MatchRegisterAltName(Name);
LLVM,RISCV,433,"Operands.push_back(<ISA_LIT>Operand::createSysReg(Identifier, S, SysReg->Encoding, isRV64()));"
LLVM,RISCV,434,"Operands.push_back(<ISA_LIT>Operand::createReg(RegNo, S, E, isRV64()));"
LLVM,RISCV,435,OS << <STR_LIT> << getToken() << <STR_LIT>;
LLVM,RISCV,436,OS << <STR_LIT> << getToken() << <STR_LIT>;
LLVM,RISCV,437,
LLVM,RISCV,438,"Parser.addAliasForDirective(<STR_LIT>, <STR_LIT>);"
LLVM,RISCV,439,"Parser.addAliasForDirective(<STR_LIT>, <STR_LIT>);"
LLVM,RISCV,440,Reg = o.Reg;
LLVM,RISCV,441,
LLVM,RISCV,442,return MatchOperand_NoMatch;
LLVM,RISCV,443,if (IsRegFPR64 || IsRegFPR64C) return Match_InvalidOperand;
LLVM,RISCV,444,"emitToStreamer(Out, MCInstBuilder(SecondOpcode).addOperand(DestReg).addOperand(TmpReg).addExpr(RefToLinkTmpLabel));"
LLVM,RISCV,445,"emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( RefToLinkTmpLabel ) ) ;"
LLVM,RISCV,446,Here are a few possibilities:
LLVM,RISCV,447,ISA_LIT`NumInstrsCompressed++
LLVM,RISCV,448,"return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,449,
LLVM,RISCV,450,
LLVM,RISCV,451,if (IsConstantImm) {
LLVM,RISCV,452,return false;
LLVM,RISCV,453,if (VK == MCExpr::VK_RVC_Imm) return true;
LLVM,RISCV,454,"IsValid = AsmParser::classifySymbolRef(getImm(), VK, Imm);"
LLVM,RISCV,455,return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI ) ;
LLVM,RISCV,456,case Match_InvalidSImm6NonZero :
LLVM,RISCV,457,RegNo = MatchRegisterName(Name);
LLVM,RISCV,458,if ( RegNo == <NUM_LIT> ) RegNo = MatchRegisterAltName ( Name ) ;
LLVM,RISCV,459,case AsmToken::Identifier:
LLVM,RISCV,460,"Based on the pattern of the code, it is likely that"
LLVM,RISCV,461,
LLVM,RISCV,462,
LLVM,RISCV,463,return true;
LLVM,RISCV,464,```
LLVM,RISCV,465,"IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,466,
LLVM,RISCV,467,return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO );
LLVM,RISCV,468,"return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;"
LLVM,RISCV,469,
LLVM,RISCV,470,Here are a few possibilities:
LLVM,RISCV,471,
LLVM,RISCV,472,Here are a few possibilities:
LLVM,RISCV,473,```
LLVM,RISCV,474,case VK_Integer:
LLVM,RISCV,475,
LLVM,RISCV,476,if (IsConstantImm && (Imm & 0x100) == 0) {
LLVM,RISCV,477,"return generateImmOutOfRangeError(Operands, ErrorInfo, -((1 << 10) - 1), (1 << 10) - 1, ""Invalid SImm10Lsb0000"");"
LLVM,RISCV,478,getParser().eatToEndOfStatement();
LLVM,RISCV,479,getLexer().Lex();
LLVM,RISCV,480,
LLVM,RISCV,481,
LLVM,RISCV,482,setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
LLVM,RISCV,483,"emitToStreamer(Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(Inst.Imm));"
LLVM,RISCV,484,"emitToStreamer(Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(Inst.Imm));"
LLVM,RISCV,485,"emitToStreamer ( Out , MCInstBuilder ( Inst . Opc ) . addReg ( DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ) ;"
LLVM,RISCV,486,Opcode = MCBinaryExpr::BINOP_ADD;
LLVM,RISCV,487,if (getLexer().isNot(AsmToken::EndOfStatement)) {
LLVM,RISCV,488,
LLVM,RISCV,489,Inst.addOperand(MCOperand::createImm(N));
LLVM,RISCV,490,return Op;
LLVM,RISCV,491,Op->IsRV64 = IsRV64;
LLVM,RISCV,492,SrcReg = DestReg;
LLVM,RISCV,493,
LLVM,RISCV,494,
LLVM,RISCV,495,
LLVM,RISCV,496,
LLVM,RISCV,497,
LLVM,RISCV,498,"return generateImmOutOfRangeError ( Operands , ErrorInfo , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> <STR_LIT> ) ;"
LLVM,RISCV,499,if (getLexer()->isNot(AsmToken::RParen)) {
LLVM,RISCV,500,getParser().Lex();
LLVM,RISCV,501,"Operands.push_back(<ISA_LIT>Operand::createImm(Res, S, E, isRV64()));"
LLVM,RISCV,502,
LLVM,RISCV,503,"Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ;"
LLVM,RISCV,504,"Operands.push_back(<ISA_LIT>Operand::createImm(Res, S, E, isRV64()));"
LLVM,RISCV,505,"if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;"
LLVM,RISCV,506,case AsmToken::Percent:`
LLVM,RISCV,507,"Operands.push_back(<ISA_LIT>Operand::createReg(RegNo, S, E, isRV64()));"
LLVM,RISCV,508,
LLVM,RISCV,509,StringRef Name = getLexer().getTok().getIdentifier();
LLVM,RISCV,510,"Operands.push_back(<ISA_LIT>Operand::createReg(RegNo, S, E, isRV64()));"
LLVM,RISCV,511,"Operands.push_back(<ISA_LIT>Operand::createVType(VTypeI, S, isRV64()));"
LLVM,RISCV,512,
LLVM,RISCV,513,* `auto Op = make_
LLVM,RISCV,514,
LLVM,RISCV,515,return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,516,Here are a few possibilities:
LLVM,RISCV,517,return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;
LLVM,RISCV,518,IsValid = isInt < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,519,
LLVM,RISCV,520,
LLVM,RISCV,521,"However, based on the names of the functions and the context of the code, it is likely that the next statement will be a conditional statement that checks the value of the `IsValid` variable, which is set to the result of the `classifySymbolRef` function if the `IsConstantImm` variable"
LLVM,RISCV,522,
LLVM,RISCV,523,return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,524,if (IsConstantImm) {
LLVM,RISCV,525,"case Match_InvalidUImm5: return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;"
LLVM,RISCV,526,Identifier = getParser().parseIdentifier();
LLVM,RISCV,527,getParser().Lex();
LLVM,RISCV,528,"return Error(Loc, <STR_LIT>);"
LLVM,RISCV,529,getParser().Lex();
LLVM,RISCV,530,if (getLexer().isNot(AsmToken::RParen)) {
LLVM,RISCV,531,
LLVM,RISCV,532,"const MCExpr * ModExpr = <ISA_LIT>MCExpr :: create ( SubExpr , VK , getContext ( ) ) ;"
LLVM,RISCV,533,if (SubExpr->getKind() != MCExpr::SymbolRef) {
LLVM,RISCV,534,"Operands.push_back(<ISA_LIT>Operand::createReg(RegNo, S, E));"
LLVM,RISCV,535,
LLVM,RISCV,536,
LLVM,RISCV,537,Kind = o.Kind;
LLVM,RISCV,538,"case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ;"
LLVM,RISCV,539,return IsValid && ( ( IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) ;
LLVM,RISCV,540,IsValid = isInt < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,541,VK = MCExpr::getVariantKind ();
LLVM,RISCV,542,return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,543,```
LLVM,RISCV,544,
LLVM,RISCV,545,"IsValid = <ISA_LIT>AsmParser::classifySymbolRef(getImm(), VK, Imm);"
LLVM,RISCV,546,return false;
LLVM,RISCV,547,return false;
LLVM,RISCV,548,case Match_InvalidSImm12Lsb0 :
LLVM,RISCV,549,return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,550,return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,551,return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO );
LLVM,RISCV,552,return IsValid && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ) ;
LLVM,RISCV,553,
LLVM,RISCV,554,getParser().Lex();
LLVM,RISCV,555,getParser().eatToEndOfStatement();
LLVM,RISCV,556,
LLVM,RISCV,557,
LLVM,RISCV,558,"emitToStreamer(Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(Inst.Imm));"
LLVM,RISCV,559,"emitLoadStoreSymbol ( Inst , <STR_LIT> , IDLoc , Out , true ) ;"
LLVM,RISCV,560,
LLVM,RISCV,561,
LLVM,RISCV,562,
LLVM,RISCV,563,if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getNumOperands ( ) == <NUM_LIT> ) ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ;
LLVM,RISCV,564,
LLVM,RISCV,565,Inst.addOperand(MCOperand.createImm(VType
LLVM,RISCV,566,Inst.addOperand(MCOperand.createImm(VType
LLVM,RISCV,567,Op -> VType . Encoding = ( SewLog2 << <NUM_LIT> ) | Flmul ;
LLVM,RISCV,568,
LLVM,RISCV,569,
LLVM,RISCV,570,
LLVM,RISCV,571,
LLVM,RISCV,572,
LLVM,RISCV,573,
LLVM,RISCV,574,Here is an example of
LLVM,RISCV,575,TailAgnostic = false;
LLVM,RISCV,576,"Based on these observations, it is likely that the next statement will be a check for another error condition, such as"
LLVM,RISCV,577,if ( ( TargetFlags & <STR_LIT> ) && ( Inst . getNumOperands ( ) == <NUM_LIT> ) ) CheckReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ;
LLVM,RISCV,578,Op.Reg.RegNum = convertFPR64ToFPR32(Reg);
LLVM,RISCV,579,assert ( N == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,580,assert ( N == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,581,
LLVM,RISCV,582,Op -> SpecialCapReg . Data = Str . data ( ) ;
LLVM,RISCV,583,
LLVM,RISCV,584,
LLVM,RISCV,585,
LLVM,RISCV,586,
LLVM,RISCV,587,
LLVM,RISCV,588,"emitAuipccInstPair(DestReg, DestReg, Symbol, <ISA_LIT>MCExpr::VK_<ISA_LIT>_PCREL_LO, <STR_LIT>, IDLoc, Out);"
LLVM,RISCV,589,"emitAuipccInstPair(DestReg, DestReg, Symbol, MCExpr::VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI, <STR_LIT>, IDLoc, Out);"
LLVM,RISCV,590,
LLVM,RISCV,591,"Out.emitRRI (Inst.getOpcode (), DestReg, 0, IDLoc);"
LLVM,RISCV,592,"emitAuipccInstPair ( DestReg , TmpReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI , SecondOpcode , IDLoc , Out ) ;"
LLVM,RISCV,593,
LLVM,RISCV,594,"return AsmParser::classifySymbolRef(getImm(), VK) && VK == MCExpr::VK_CCALL;"
LLVM,RISCV,595,return is
LLVM,RISCV,596,return getSTI().getFeatureBits(<STR_LIT>);
LLVM,RISCV,597,"However, based on the syntax and the context of the code, it is likely that the next statement will be a conditional statement that checks whether the `Kind` variable is equal to the `KindTy::Register` value, and if so, it will check whether the `Reg"
LLVM,RISCV,598,return false;
LLVM,RISCV,599,
LLVM,RISCV,600,
LLVM,RISCV,601,
LLVM,RISCV,602,
LLVM,RISCV,603,
LLVM,RISCV,604,return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,605,
LLVM,RISCV,606,
LLVM,RISCV,607,"IsValid = AsmParser::classifySymbolRef(getImm(), VK);"
LLVM,RISCV,608,return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI || VK == <ISA_LIT>MCExp
LLVM,RISCV,609,
LLVM,RISCV,610,if (IsConstantImm) {
LLVM,RISCV,611,
LLVM,RISCV,612,"Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ;"
LLVM,RISCV,613,getTargetStreamer().emitDirectiveOptionRVC( );
LLVM,RISCV,614,getTargetStreamer().emitDirectiveOptionNoPIC();
LLVM,RISCV,615,
LLVM,RISCV,616,case AsmToken::Identifier: {
LLVM,RISCV,617,if (SpecialCapReg) {
LLVM,RISCV,618,
LLVM,RISCV,619,
LLVM,RISCV,620,
LLVM,RISCV,621,case <STR_LIT>:
LLVM,RISCV,622,return isUInt < <NUM_LIT> > ( Imm ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ) ;
LLVM,RISCV,623,"IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,624,"emitLoadImm(Reg, Imm, Out);"
LLVM,RISCV,625,"emitToStreamer(Out, MCInstBuilder(<STR_LIT>).addReg(Reg).addReg(<STR_LIT>).addExpr(Op1.getExpr()));"
LLVM,RISCV,626,
LLVM,RISCV,627,assert ( N == <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,628,
LLVM,RISCV,629,Op->Vtypei.Sew = static_cast<VSEW>(sew.logBase2());
LLVM,RISCV,630,
LLVM,RISCV,631,case <STR_LIT> : return <STR_LIT> ;
LLVM,RISCV,632,
LLVM,RISCV,633,
LLVM,RISCV,634,
LLVM,RISCV,635,return false;
LLVM,RISCV,636,return Kind == KindTy::VectorRegister;
LLVM,RISCV,637,
LLVM,RISCV,638,if (Result == MatchOperand_Success) return false;
LLVM,RISCV,639,if (Result == MatchOperand_Success) return false;
LLVM,RISCV,640,RegNo = <STR_LIT>;
LLVM,RISCV,641,
LLVM,RISCV,642,StringRef Name = getLexer().getTok().getIdentifier();
LLVM,RISCV,643,"getLexer().Lex(); if (getLexer().is(AsmToken::EndOfStatement)) { Operands.push_back(<ISA_LIT>Operand::createVTypeImm(sew, lmul, ediv, S, isRV64())); return MatchOperand_Success; }`"
LLVM,RISCV,644,
LLVM,RISCV,645,"case KindTy::VTypeImm: SmallVector<char, <NUM_LIT>> VTypeBuf;"
LLVM,RISCV,646,Kind = o.Kind;
LLVM,RISCV,647,"However, based on the `switch` statement, it is likely that the next statement will be one of the following:"
LLVM,RISCV,648,Op -> Imm . Val = Val ;
LLVM,RISCV,649,"Operands.push_back(<ISA_LIT>Operand::createImm(Res, S, E));"
LLVM,RISCV,650,if (VK == <ISA_LIT>MCExpr::VK_None) {
LLVM,RISCV,651,"Operands.push_back(Operand::createToken(<STR_LIT>, getLoc()));"
LLVM,RISCV,652,RegNo = MatchRegisterAltName(Name);
LLVM,RISCV,653,"case Match_InvalidVTypeI: { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , <STR_LIT> <STR_LIT> ) ; }"
LLVM,RISCV,654,
LLVM,RISCV,655,return IsConstantImm && IsInRange && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,656,if (VK == <ISA_LIT>MCExpr::VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr::VK_<ISA_LIT>_PCREL_LO) return true;
LLVM,RISCV,657,
LLVM,RISCV,658,return RegNo == <NUM_LIT>;
LLVM,RISCV,659,
LLVM,RISCV,660,if (IsRegFPR32) { ... }
LLVM,RISCV,661,Op.Reg.RegNum = convertFPR32ToFPR64(Reg);
LLVM,RISCV,662,
LLVM,RISCV,663,"Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());"
LLVM,RISCV,664,"Operands.push_back(<ISA_LIT>Operand::createReg(RegNo, S, E, isRV64()));"
LLVM,RISCV,665,if ( HadParens ) {
LLVM,RISCV,666,Imm = getImm();
LLVM,RISCV,667,"bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);"
LLVM,RISCV,668,
LLVM,RISCV,669,"Operands.push_back(Operand::createImm(Res, S, E, isRV64()));"
LLVM,RISCV,670,
LLVM,RISCV,671,Op->VType.Lmul = static_cast<VLMUL>(Flmul);
LLVM,RISCV,672,"return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,673,return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,674,"bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;"
LLVM,RISCV,675,return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,676,
LLVM,RISCV,677,return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,678,"IsValid = isShiftedUInt<NUM_LIT, NUM_LIT>(Imm);"
LLVM,RISCV,679,Imm = getImm();
LLVM,RISCV,680,if (IsConstantImm) {
LLVM,RISCV,681,if (IsConstantImm) {
LLVM,RISCV,682,if (getLexer().isNot(AsmToken::LParen)) {
LLVM,RISCV,683,if (getSTI().getFeatureBits()[<STR_LIT>]) {
LLVM,RISCV,684,
LLVM,RISCV,685,
LLVM,RISCV,686,
LLVM,RISCV,687,
LLVM,RISCV,688,if (IsConstantImm) { ... }
LLVM,RISCV,689,getParser().Lex();
LLVM,RISCV,690,
LLVM,RISCV,691,
LLVM,RISCV,692,
LLVM,RISCV,693,
LLVM,RISCV,694,
LLVM,RISCV,695,Op->setSew(Sew);
LLVM,RISCV,696,
LLVM,RISCV,697,
LLVM,RISCV,698,
LLVM,RISCV,699,if (Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT> && Lmul != <NUM_LIT>) return MatchOperand_NoMatch;
LLVM,RISCV,700,if ( TargetFlags == <STR_LIT> ) {
LLVM,RISCV,701,if ( TargetFlags == <STR_LIT> ) {
LLVM,RISCV,702,return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,703,
LLVM,RISCV,704,return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,705,return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,706,
LLVM,RISCV,707,if (getSTI().getFeatureBits()[<STR_LIT>]) {
LLVM,RISCV,708,Inst.addOperand(MCOperand::createExpr(Expr));
LLVM,RISCV,709,case 'i': Imm |= <STR_LIT>;
LLVM,RISCV,710,
LLVM,RISCV,711,Kind = RE->getKind();
LLVM,RISCV,712,
LLVM,RISCV,713,Op->Reg =
LLVM,RISCV,714,return std::move(Op);
LLVM,RISCV,715,
LLVM,RISCV,716,"emitToStreamer(Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(Inst.Imm));"
LLVM,RISCV,717,
LLVM,RISCV,718,"S.EmitInstruction((Res ? CInst : Inst), getSTI());"
LLVM,RISCV,719,Here are a few possibilities:
LLVM,RISCV,720,
LLVM,RISCV,721,
LLVM,RISCV,722,"return StringRef(SysReg.Data, SysReg.Length);"
LLVM,RISCV,723,
LLVM,RISCV,724,"IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,725,return false;
LLVM,RISCV,726,return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,727,return IsConstantImm && ( Imm != <NUM_LIT> ) && ( isUInt < <NUM_LIT> > ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;
LLVM,RISCV,728,
LLVM,RISCV,729,return true;
LLVM,RISCV,730,return IsConstantImm && IsInRange && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,731,bool Instruction::isReg() const {
LLVM,RISCV,732,
LLVM,RISCV,733,return false;
LLVM,RISCV,734,return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,735,
LLVM,RISCV,736,return IsConstantImm && isInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None;
LLVM,RISCV,737,
LLVM,RISCV,738,
LLVM,RISCV,739,Imm = getImm ( ) ;
LLVM,RISCV,740,
LLVM,RISCV,741,"IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;"
LLVM,RISCV,742,
LLVM,RISCV,743,"return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,744,"return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;"
LLVM,RISCV,745,
LLVM,RISCV,746,
LLVM,RISCV,747,return isUInt < <NUM_LIT> > ( Imm ) ;
LLVM,RISCV,748,return (isRV64( ) && isUInt < <NUM_LIT> > (Imm)) || isUInt < <NUM_LIT> > (Imm);
LLVM,RISCV,749,Here is an example of what the next statement might look like:
LLVM,RISCV,750,"Operands.push_back(<ISA_LIT>Operand::createImm(Res, S, E, isRV64()));"
LLVM,RISCV,751,"Operands.push_back(<ISA_LIT>Operand::createImm(Res, S, E, isRV64()));"
LLVM,RISCV,752,Some possible next statements could include:
LLVM,RISCV,753,
LLVM,RISCV,754,"if (Option == ""rvc"") {"
LLVM,RISCV,755,return MatchOperand_NoMatch;
LLVM,RISCV,756,
LLVM,RISCV,757,"const MCExpr * ModExpr = MCExpr::create(SubExpr, VK, getContext());"
LLVM,RISCV,758,"Operands.push_back(<ISA_LIT>Operand::createToken(<STR_LIT>, FirstS, isRV64()));"
LLVM,RISCV,759,return true;
LLVM,RISCV,760,
LLVM,RISCV,761,
LLVM,RISCV,762,"emitToStreamer(Out, MCInstBuilder(""<STR_LIT>"").addReg(Reg).addReg(""<STR_LIT>"").addExpr(Op1.getExpr()));"
LLVM,RISCV,763,"Parser.addAliasForDirective(<STR_LIT>, <STR_LIT>);"
LLVM,RISCV,764,"this->init(STI, Parser, MII, Options);"
LLVM,RISCV,765,
LLVM,RISCV,766,if ( ( IsRegFPR32 && Kind == MCK_FPR64 ) || ( IsRegFPR32C && Kind == MCK_FPR64C ) ) { Op . Reg . RegNum = convertFPR32ToFPR64 ( Reg ) ; return Match_Success ; }
LLVM,RISCV,767,OutStreamer->EmitLabel(Stubs[i].first);
LLVM,RISCV,768,Some possible next statements could include:
LLVM,RISCV,769,
LLVM,RISCV,770,"OutStreamer->EmitValue(Expr, Size);"
LLVM,RISCV,771,return MCSymbolRefExpr::VK_NTPOFF;
LLVM,RISCV,772,RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( The<ISA_LIT>Target ) ;
LLVM,RISCV,773,RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B ( The<
LLVM,RISCV,774,return false;
LLVM,RISCV,775,OS << '%' << InstPrinter :: getRegisterName ( MI -> getOperand ( opNum ) . getReg ( ) ) ;
LLVM,RISCV,776,
LLVM,RISCV,777,O << <STR_LIT> ;
LLVM,RISCV,778,
LLVM,RISCV,779,Subtarget->setInstrItinerary(MF.getInstrItinerary());
LLVM,RISCV,780,
LLVM,RISCV,781,OutStreamer->EmitInstruction(TmpInst);
LLVM,RISCV,782,Res = Res + 1;
LLVM,RISCV,783,
LLVM,RISCV,784,
LLVM,RISCV,785,
LLVM,RISCV,786,"emitPseudoExpansionLowering(*OutStreamer, MI);"
LLVM,RISCV,787,"AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);"
LLVM,RISCV,788,
LLVM,RISCV,789,RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Z ( getThe<ISA_LIT>128Target ( ) ) ;
LLVM,RISCV,790,RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ;
LLVM,RISCV,791,MO.getReg()
LLVM,RISCV,792,
LLVM,RISCV,793,case MachineOperand::MO_Memory:`
LLVM,RISCV,794,case MachineOperand :: MO_Register : OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ;
LLVM,RISCV,795,RTS.emitTargetAttributes(*STI);
LLVM,RISCV,796,
LLVM,RISCV,797,
LLVM,RISCV,798,O << <STR_LIT> ; break ;
LLVM,RISCV,799,OS << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ; return false ;
LLVM,RISCV,800,
LLVM,RISCV,801,
LLVM,RISCV,802,RTS.emitDirectiveOptionPop();
LLVM,RISCV,803,RTS.setTargetStreamer(OutStreamer);
LLVM,RISCV,804,RTS.emitDirectiveOptionNoRVC();
LLVM,RISCV,805,RTS.EmitBasicBlockStart(MBB);
LLVM,RISCV,806,
LLVM,RISCV,807,STI = TM.getMCSubtargetInfo();
LLVM,RISCV,808,STI = TM.getMCSubtargetInfo();
LLVM,RISCV,809,return false;
LLVM,RISCV,810,bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF )
LLVM,RISCV,811,case MachineOperand::MO_Immediate:`
LLVM,RISCV,812,
LLVM,RISCV,813,RTS.emitTargetAttributes(*MCSTI);
LLVM,RISCV,814,RTS.emitTargetAttributes(*MCSTI);
LLVM,RISCV,815,RTS.emitEndOfAsmFile(M);
LLVM,RISCV,816,RTS.setTargetStreamer(OutStreamer);
LLVM,RISCV,817,
LLVM,RISCV,818,RTS.setTargetABI(STI->getTargetABI());
LLVM,RISCV,819,TmpInst.setOpcode(MI->getOpcode());
LLVM,RISCV,820,TmpInst.setOpcode(MI->getOpcode());
LLVM,RISCV,821,if (Res) {
LLVM,RISCV,822,Some possible next statements could include:
LLVM,RISCV,823,"return ""getPassName"";"
LLVM,RISCV,824,RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ;
LLVM,RISCV,825,case MachineOperand::MO_GlobalAddress:`
LLVM,RISCV,826,"case MachineOperand :: MO_BlockAddress : { MCSymbol * Sym = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Sym -> print ( OS , MAI ) ; return false ; }"
LLVM,RISCV,827,MCSTI = new MCSubtargetInfo(TM.getMCSubtargetInfo());
LLVM,RISCV,828,MCSTI = new MCSubtargetInfo(TM.getMCSubtargetInfo());
LLVM,RISCV,829,
LLVM,RISCV,830,
LLVM,RISCV,831,if ( TargetABI != ABI_Unknown ) return TargetABI ;
LLVM,RISCV,832,if (TargetABI != ABI_Unknown) return TargetABI;
LLVM,RISCV,833,
LLVM,RISCV,834,
LLVM,RISCV,835,
LLVM,RISCV,836,unsigned VLMULBits = static_cast < unsigned > ( VLMUL ) ;
LLVM,RISCV,837,"However, based on the name of the function and the parameters it takes, it is likely that the function is responsible for encoding a vector type based on the input parameters. The `VLMUL` parameter is likely a multiplier for the vector length, and the `SEW` parameter is likely a shift amount for the vector element width. The `TailAgnost"
LLVM,RISCV,838,"return isCheriPureCapABI(TargetABI) ? ""CheriPureCap"" : ""Cheri"";"
LLVM,RISCV,839,
LLVM,RISCV,840,
LLVM,RISCV,841,"TargetABI = StringSwitch < ABI > ( ABIName ) . Case ( <STR_LIT> , ABI_ILP32 ) . Case ( <STR_LIT> , ABI_ILP32F ) . Case ( <STR_LIT> , ABI_ILP32D ) . Case ( <STR_LIT> , ABI_ILP32E ) . Case ( <STR_LIT> , ABI_IL32PC64 ) . Case ( <ST"
LLVM,RISCV,842,return (TSFlags & IsRVVWiden
LLVM,RISCV,843,
LLVM,RISCV,844,OS << LMul;
LLVM,RISCV,845,return (TSFlags & UsesMaskPolicyMask) != 0;
LLVM,RISCV,846,report_fatal_error(<STR_LIT>);
LLVM,RISCV,847,return static_cast<STR_LIT>(Fractional ? NUM_LIT - LmulLog2 : LmulLog2);
LLVM,RISCV,848,OS << <STR_LIT>;
LLVM,RISCV,849,OS << <STR_LIT> << LMul;
LLVM,RISCV,850,errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ;
LLVM,RISCV,851,unsigned VTypeI = ( ( VLMULBits & <NUM_LIT> ) << <NUM_LIT> ) | ( VSEWBits << <NUM_LIT> ) | ( VLMULBits & <NUM_LIT> );
LLVM,RISCV,852,return static_cast < int8_t > ( MergeOpIndex ) ;
LLVM,RISCV,853,
LLVM,RISCV,854,return static_cast<int8_t>(SEWIndex);
LLVM,RISCV,855,
LLVM,RISCV,856,
LLVM,RISCV,857,unsigned VLMUL = ( VType & <NUM_LIT> ) | ( ( VType & <NUM_LIT> ) >> <NUM_LIT> ) ;
LLVM,RISCV,858,unsigned VLMUL = ( VType & <NUM_LIT> ) | ( ( VType & <NUM_LIT> ) >> <NUM_LIT> ) ;
LLVM,RISCV,859,
LLVM,RISCV,860,unsigned VSEW = ( VType >> <NUM_LIT> ) & <NUM_LIT> ;
LLVM,RISCV,861,return HasDummyMask;
LLVM,RISCV,862,
LLVM,RISCV,863,Offset = <NUM_LIT>;
LLVM,RISCV,864,
LLVM,RISCV,865,return Desc.getNumOperands() - Offset;
LLVM,RISCV,866,return (TSFlags & UsesMaskPolicyMask) != 0;
LLVM,RISCV,867,
LLVM,RISCV,868,
LLVM,RISCV,869,
LLVM,RISCV,870,
LLVM,RISCV,871,return VTypeI;
LLVM,RISCV,872,
LLVM,RISCV,873,Based on the name of the
LLVM,RISCV,874,return static_cast < <ISA_LIT>VSEW > ( VSEW ) ;
LLVM,RISCV,875,errs() << <STR_LIT> << ABIName << <STR_LIT>;
LLVM,RISCV,876,errs() << <STR_LIT> <STR_LIT> <STR_LIT>;
LLVM,RISCV,877,
LLVM,RISCV,878,
LLVM,RISCV,879,FeatureVector.push_back(std::string(<STR_LIT>) + Feature.Key);
LLVM,RISCV,880,FeatureVector.push_back(std::string(<STR_LIT>) + Feature.Key);
LLVM,RISCV,881,if (IsRV32E) { ... }
LLVM,RISCV,882,VTypeI |= <NUM_LIT>;
LLVM,RISCV,883,unsigned VTypeI = (VSEWBits << <NUM_LIT>) | (VLMULBits & <NUM_LIT>);
LLVM,RISCV,884,FeatureVector.push_back(std::string(<STR_LIT>) + Feature.Key);
LLVM,RISCV,885,if (isTailAgnostic(VType)) OS << <STR_LIT>;
LLVM,RISCV,886,"OS << ""LMul"" << LMul;"
LLVM,RISCV,887,OS << <STR_LIT> << LMul;
LLVM,RISCV,888,errs() << <STR_LIT>;
LLVM,RISCV,889,TargetABI = ABI_Unknown;
LLVM,RISCV,890,
LLVM,RISCV,891,return TSFlags & ForceTailAgnosticMask;
LLVM,RISCV,892,
LLVM,RISCV,893,
LLVM,RISCV,894,return ( TSFlags & InstFormatMask ) >> InstFormatShift ;
LLVM,RISCV,895,return ( TSFlags & InstFormatMask ) >> InstFormatShift;
LLVM,RISCV,896,
LLVM,RISCV,897,return decodeVSEW(VSEW);
LLVM,RISCV,898,"return static_cast<std::string>(VLMUL) + ""some string"";"
LLVM,RISCV,899,
LLVM,RISCV,900,if (TSFlags & HasDummyMaskOpMask) {
LLVM,RISCV,901,return (TSFlags & HasDummyMaskOpMask) != 0;
LLVM,RISCV,902,return (TSFlags & HasMergeOpMask) != 0;
LLVM,RISCV,903,return TSFlags & HasSEWOpMask;
LLVM,RISCV,904,
LLVM,RISCV,905,return (TSFlags & HasVLOpMask) != 0;
LLVM,RISCV,906,return TSFlags & HasVLOpMask;
LLVM,RISCV,907,return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
LLVM,RISCV,908,
LLVM,RISCV,909,
LLVM,RISCV,910,
LLVM,RISCV,911,
LLVM,RISCV,912,return isPowerOf2_32(SEW) && SEW >= <NUM_LIT> && SEW <= <NUM_LIT>;
LLVM,RISCV,913,
LLVM,RISCV,914,Here are some possible next statements:
LLVM,RISCV,915,R
LLVM,RISCV,916,StringSwitch < RoundingMode > ( Str )
LLVM,RISCV,917,
LLVM,RISCV,918,"However, based on the names of the classes and parameters, it is likely that the `validate` function is checking the validity of a triple (i.e., a set of three values) and a feature bitset (i.e., a set of bits that represent the presence or absence of certain"
LLVM,RISCV,919,
LLVM,RISCV,920,MBBStartOffset += TII->GetInstSizeInBytes(I);
LLVM,RISCV,921,
LLVM,RISCV,922,"return ""getPassName"";"
LLVM,RISCV,923,BSel ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>BSelPass ( * PassRegistry :: getPassRegistry ( ) ) ;
LLVM,RISCV,924,
LLVM,RISCV,925,EverMadeChange |= MadeChange;
LLVM,RISCV,926,
LLVM,RISCV,927,
LLVM,RISCV,928,
LLVM,RISCV,929,CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {
LLVM,RISCV,930,CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {
LLVM,RISCV,931,PrevVSETVLI = nullptr;
LLVM,RISCV,932,Changed = true;
LLVM,RISCV,933,PrevVSETVLI = &MI;
LLVM,RISCV,934,MachineFunctionPass::getAnalysisUsage(AU);
LLVM,RISCV,935,MachineFunctionPass::getAnalysisUsage(AU);
LLVM,RISCV,936,return <ISA_LIT>_CLEANUP_VSETVLI_NAME;
LLVM,RISCV,937,return <ISA_LIT>_CLEANUP_VSETVLI_NAME;
LLVM,RISCV,938,return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: IsSSA ) ;
LLVM,RISCV,939,
LLVM,RISCV,940,Register AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;
LLVM,RISCV,941,"* `initialize<ISA_LIT>CleanupVSETVLIPass`: This is a function call to the `initialize` function, which is a member function of the `PassRegistry` class. The `<ISA_LIT>` template parameter is used to specify the type of the `ISA"
LLVM,RISCV,942,PrevVSETVLI = &MI;
LLVM,RISCV,943,if ( ! ST . hasStdExtV ( ) ) return false ;
LLVM,RISCV,944,
LLVM,RISCV,945,
LLVM,RISCV,946,return cc64_get_representable_length(Length);
LLVM,RISCV,947,return Align ( cc128_get_required_alignment ( Size ) ) ;
LLVM,RISCV,948,return Align ( cc128_get_required_alignment ( Size ) ) ;
LLVM,RISCV,949,"return static_cast < TailPaddingAmount > ( llvm :: alignTo ( Size , cc64_get_required_alignment ( Size ) ) - Size ) ;"
LLVM,RISCV,950,ID.AddInteger(Modifier) + 1;
LLVM,RISCV,951,if (Constants[I].isMachineConstantPoolEntry() && (Constants[I].getAlignment() & AlignMask) == <NUM_LIT>) {
LLVM,RISCV,952,if (Constants[I].isMachineConstantPoolEntry() && (Constants[I].getAlignment() & AlignMask) == <NUM_LIT>) {
LLVM,RISCV,953,
LLVM,RISCV,954,
LLVM,RISCV,955,
LLVM,RISCV,956,
LLVM,RISCV,957,GV = gv;
LLVM,RISCV,958,<ISA_LIT>ConstantPoolValue ::= <ISA_LIT>ConstantPoolValue <ISA_LIT>ConstantPoolValue
LLVM,RISCV,959,
LLVM,RISCV,960,AU.setPreservesAll();
LLVM,RISCV,961,
LLVM,RISCV,962,BB = Next;
LLVM,RISCV,963,Here are a few possibilities:
LLVM,RISCV,964,Here are a few possibilities:
LLVM,RISCV,965,
LLVM,RISCV,966,return DecodeStatus::Fail;
LLVM,RISCV,967,Reg = Reg + 1;
LLVM,RISCV,968,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,969,
LLVM,RISCV,970,Inst.setOpcode(ARM64_REG_FPR64 + RegNo);
LLVM,RISCV,971,Here is an example of what the next statement
LLVM,RISCV,972,
LLVM,RISCV,973,
LLVM,RISCV,974,Register Reg = <STR_LIT> + RegNo;
LLVM,RISCV,975,Register Reg = <STR_LIT> + RegNo;
LLVM,RISCV,976,
LLVM,RISCV,977,"DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ;"
LLVM,RISCV,978,Inst.addOperand(Inst.getOperand(<NUM_LIT>));
LLVM,RISCV,979,"DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ;"
LLVM,RISCV,980,
LLVM,RISCV,981,
LLVM,RISCV,982,return MCDisassembler :: Success;
LLVM,RISCV,983,return Result;
LLVM,RISCV,984,"return new MCDisassembler<ISA_LIT>(T, STI, Ctx);"
LLVM,RISCV,985,Reg = RegNo + Reg;
LLVM,RISCV,986,Size = <NUM_LIT>;
LLVM,RISCV,987,"TargetRegistry::RegisterMCDisassembler(getThe<ISA_LIT>128Target(), create<ISA_LIT>Disassembler);"
LLVM,RISCV,988,Here is a possible next statement
LLVM,RISCV,989,"MCDisassembler::MCDisassembler(STI, Ctx)"
LLVM,RISCV,990,"MCDisassembler::MCDisassembler(STI, Ctx)"
LLVM,RISCV,991,"DecodeGPCRRegisterClass(Inst, <NUM_LIT>, Address, Decoder);"
LLVM,RISCV,992,"DecodeGPCRRegisterClass(Inst, <NUM_LIT>, Address, Decoder);"
LLVM,RISCV,993,
LLVM,RISCV,994,return MCDisassembler::Fail;
LLVM,RISCV,995,MCRegister Reg = <STR_LIT> + RegNo ;
LLVM,RISCV,996,
LLVM,RISCV,997,
LLVM,RISCV,998,
LLVM,RISCV,999,Inst.setOpcode(ARM64_REG_FPR64 + RegNo);
LLVM,RISCV,1000,"However, based on the name of the function and the parameters it takes, it is likely that the function is responsible for decoding a register class for a general-purpose register (GPR) in a computer's instruction set architecture (ISA). The `RegNo`"
LLVM,RISCV,1001,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1002,
LLVM,RISCV,1003,MCRegister Reg = <STR_LIT> + RegNo ;
LLVM,RISCV,1004,MCRegister Reg = <STR_LIT> + RegNo;
LLVM,RISCV,1005,Inst.addOperand(MCOperand::CreateReg(Reg));
LLVM,RISCV,1006,bool IsRV32E = FeatureBits[<STR_LIT>];
LLVM,RISCV,1007,Reg = <STR_LIT>;
LLVM,RISCV,1008,Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;
LLVM,RISCV,1009,
LLVM,RISCV,1010,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1011,Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;
LLVM,RISCV,1012,
LLVM,RISCV,1013,Here is a possible next statement:
LLVM,RISCV,1014,MCRegister Reg = <STR_LIT> + RegNo ;
LLVM,RISCV,1015,LLVM_DEBUG(dbgs() << <STR_LIT>);
LLVM,RISCV,1016,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1017,
LLVM,RISCV,1018,
LLVM,RISCV,1019,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1020,
LLVM,RISCV,1021,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1022,Inst.addOperand(MCOperand::createReg(SignExtend64<N>(Imm)));
LLVM,RISCV,1023,
LLVM,RISCV,1024,Inst.addOperand(MCOperand::createImm(Imm));
LLVM,RISCV,1025,
LLVM,RISCV,1026,"For example, if the value of `RegNo` is 0, the next statement might be:"
LLVM,RISCV,1027,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1028,Here is an example of what the next statement
LLVM,RISCV,1029,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1030,
LLVM,RISCV,1031,"return decodeSImmOperand < N > ( Inst , Imm , Address , Decoder ) ;"
LLVM,RISCV,1032,
LLVM,RISCV,1033,"MCRegister Reg = MCRegister::create(RegNo, <STR_LIT>);"
LLVM,RISCV,1034,
LLVM,RISCV,1035,"Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address, this, STI);"
LLVM,RISCV,1036,if (STI.getFeatureBits()[<STR_LIT>] && !STI.getFeatureBits()[<STR_LIT>]) {
LLVM,RISCV,1037,"Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);"
LLVM,RISCV,1038,
LLVM,RISCV,1039,"return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;"
LLVM,RISCV,1040,
LLVM,RISCV,1041,
LLVM,RISCV,1042,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1043,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1044,return MCDisassembler::Fail;
LLVM,RISCV,1045,"Inst.setRegister(RegNo, FPR64DecoderTable[RegNo]);"
LLVM,RISCV,1046,
LLVM,RISCV,1047,"However, based on the name of the function and the parameters it takes, it is likely that the function is responsible for decoding a register class for a General Purpose Register (GPR) in a computer architecture. The `MCInst` parameter is likely an instance of a class that represents a machine instruction, and the `RegNo` parameter is likely an integer that represents the register number. The"
LLVM,RISCV,1048,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1049,"Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);"
LLVM,RISCV,1050,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1051,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1052,"DecodeGPRRegisterClass(Inst, <NUM_LIT>, Address, Decoder);"
LLVM,RISCV,1053,
LLVM,RISCV,1054,
LLVM,RISCV,1055,return MCDisassembler :: Fail ;
LLVM,RISCV,1056,
LLVM,RISCV,1057,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1058,
LLVM,RISCV,1059,return MCDisassembler :: Fail ;
LLVM,RISCV,1060,Inst.addOperand(MCOperand::createImm(Imm));
LLVM,RISCV,1061,
LLVM,RISCV,1062,"Inst.setReg(RegNo, Address);"
LLVM,RISCV,1063,return MCDisassembler :: Fail ;
LLVM,RISCV,1064,
LLVM,RISCV,1065,
LLVM,RISCV,1066,
LLVM,RISCV,1067,
LLVM,RISCV,1068,Inst.setRegister(RegNo);
LLVM,RISCV,1069,MCRegister Reg = <STR_LIT> + RegNo;
LLVM,RISCV,1070,
LLVM,RISCV,1071,Inst.addOperand(Inst.getOperand(<NUM_LIT>));
LLVM,RISCV,1072,Inst.addOperand(MCOperand::createReg(Rd));
LLVM,RISCV,1073,return MCDisassembler::Success;
LLVM,RISCV,1074,"uint64_t SImm6 = fieldFromInstruction(Insn, <NUM_LIT>, <NUM_LIT>) << <NUM_LIT> | fieldFromInstruction(Insn, <NUM_LIT>, <NUM_LIT>);"
LLVM,RISCV,1075,"return decodeSImmOperand < N > ( Inst , Imm , Address , Decoder ) ;"
LLVM,RISCV,1076,
LLVM,RISCV,1077,
LLVM,RISCV,1078,
LLVM,RISCV,1079,
LLVM,RISCV,1080,
LLVM,RISCV,1081,Inst.setOpcode(ARM64_INS_MOV);`
LLVM,RISCV,1082,Inst.addOperand(MCOperand::createImm(Imm));
LLVM,RISCV,1083,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1084,
LLVM,RISCV,1085,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1086,Here is a possible next statement:
LLVM,RISCV,1087,
LLVM,RISCV,1088,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1089,"DecodeGPRRegisterClass(Inst, <NUM_LIT>, Address, Decoder);"
LLVM,RISCV,1090,"return new MCDisassembler<ISA_LIT>(T, STI, Ctx);"
LLVM,RISCV,1091,"MCDisassembler *disassembler = new MCDisassembler(STI, Ctx);"
LLVM,RISCV,1092,Assuming that `SignExtend64`
LLVM,RISCV,1093,Inst.addOperand(MCOperand::createImm(Imm));
LLVM,RISCV,1094,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1095,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1096,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1097,"Inst.setOperand(0, MCOperand::createReg(RegNo));"
LLVM,RISCV,1098,return MCDisassembler :: Fail;
LLVM,RISCV,1099,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1100,Inst.setFRM(Imm);
LLVM,RISCV,1101,
LLVM,RISCV,1102,Reg = GPRDecoderTable[RegNo + <NUM_LIT>];
LLVM,RISCV,1103,
LLVM,RISCV,1104,
LLVM,RISCV,1105,return MCDisassembler::Fail;
LLVM,RISCV,1106,
LLVM,RISCV,1107,Inst.addOperand(MCOperand::createImm(Reg));
LLVM,RISCV,1108,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,RISCV,1109,
LLVM,RISCV,1110,
LLVM,RISCV,1111,
LLVM,RISCV,1112,
LLVM,RISCV,1113,Size = <NUM_LIT>;
LLVM,RISCV,1114,
LLVM,RISCV,1115,* `ISA_LIT` is a macro that expands to the name of the instruction set architecture (ISA) being targeted.
LLVM,RISCV,1116,* `ISA_LIT` is a macro that expands to the name of the instruction set architecture (ISA) being targeted.
LLVM,RISCV,1117,
LLVM,RISCV,1118,"MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_<ISA_L"
LLVM,RISCV,1119,"MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_<ISA_L"
LLVM,RISCV,1120,~ELFObjectWriter() {
LLVM,RISCV,1121,~ELFObjectWriter() {
LLVM,RISCV,1122,case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI20 ;
LLVM,RISCV,1123,case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_ADD ;
LLVM,RISCV,1124,
LLVM,RISCV,1125,case <STR_LIT> : return ELF :: R_<ISA_LIT>_JALR ;
LLVM,RISCV,1126,"MCObjectWriter *llvm::create<ISA_LIT>ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool Is64Bit) {"
LLVM,RISCV,1127,
LLVM,RISCV,1128,"MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_<ISA_L"
LLVM,RISCV,1129,"MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_<ISA_L"
LLVM,RISCV,1130,
LLVM,RISCV,1131,
LLVM,RISCV,1132,case <STR_LIT> : return ELF :: R_<ISA_LIT>_TPREL_LO12_S ;
LLVM,RISCV,1133,
LLVM,RISCV,1134,case FK_Data_4: return ELF::R_<ISA_LIT>_32;
LLVM,RISCV,1135,case FK_Data_1:
LLVM,RISCV,1136,case FK_Data_8 : return ELF :: R_<ISA_LIT>_64 ;
LLVM,RISCV,1137,
LLVM,RISCV,1138,
LLVM,RISCV,1139,
LLVM,RISCV,1140,writer->write(elf_object);
LLVM,RISCV,1141,
LLVM,RISCV,1142,Result += item.StringValue.size() + <NUM_LIT>;
LLVM,RISCV,1143,return S;
LLVM,RISCV,1144,"setAttributeItem(Attribute, Value, false)"
LLVM,RISCV,1145,
LLVM,RISCV,1146,
LLVM,RISCV,1147,
LLVM,RISCV,1148,
LLVM,RISCV,1149,emitDirectiveOptionNoRVC(this);
LLVM,RISCV,1150,emitDirectiveOptionNoRVC(this);
LLVM,RISCV,1151,
LLVM,RISCV,1152,
LLVM,RISCV,1153,Some possible next statements could include:
LLVM,RISCV,1154,Some possible next statements could include:
LLVM,RISCV,1155,Here are a few possibilities for what the next statement could be:
LLVM,RISCV,1156,Here are a few possibilities for what the next statement could be:
LLVM,RISCV,1157,
LLVM,RISCV,1158,
LLVM,RISCV,1159,
LLVM,RISCV,1160,
LLVM,RISCV,1161,"DF->getFixups()->push_back(MCFixup::create(DF->getContents()->size(), A, static_cast<MCFixupKind>(Sub), Loc));"
LLVM,RISCV,1162,"DF->getFixups()->push_back(MCFixup::create(DF->getContents()->size(), C, static_cast<MCFixupKind>(Add), Loc));"
LLVM,RISCV,1163,case <STR_LIT> : EFlags |= ELF :: EF_<ISA_LIT>_FLOAT_ABI_SINGLE ; break ;
LLVM,RISCV,1164,
LLVM,RISCV,1165,Streamer.emitInt8(<NUM_LIT>);
LLVM,RISCV,1166,"return std::make_pair(""hello"", ""world"");"
LLVM,RISCV,1167,
LLVM,RISCV,1168,"RHS = MCBinaryExpr::create(MCBinaryExpr::Add, MCSymbolRefExpr::create(&B, C), MCConstantExpr::create(E.getConstant(), C), C);"
LLVM,RISCV,1169,
LLVM,RISCV,1170,MCELFStreamer::reset();`
LLVM,RISCV,1171,this.someProperty = someValue;
LLVM,RISCV,1172,MCAsmBackend *MAB = new MCAsmBackend(C);
LLVM,RISCV,1173,MCAsmBackend *MAB = new MCAsmBackend(C);
LLVM,RISCV,1174,
LLVM,RISCV,1175,
LLVM,RISCV,1176,EFlags |= ELF::EF_<ISA_LIT>_RVC;
LLVM,RISCV,1177,
LLVM,RISCV,1178,DF->addFixup (CapFixup);
LLVM,RISCV,1179,assert ( CapSize == ( getContext ( ) . getTargetTriple ( ) . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ;
LLVM,RISCV,1180,
LLVM,RISCV,1181,
LLVM,RISCV,1182,Some possible next statements could include:
LLVM,RISCV,1183,Some possible next statements could include:
LLVM,RISCV,1184,MCA.setELFHeaderEFlags(EFlags);
LLVM,RISCV,1185,return nullptr;
LLVM,RISCV,1186,Item->Type = AttributeType::Text;
LLVM,RISCV,1187,Item->Type = AttributeType::Text;
LLVM,RISCV,1188,Item -> Type = AttributeType :: NumericAndText ;
LLVM,RISCV,1189,"BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ; break ;"
LLVM,RISCV,1190,
LLVM,RISCV,1191,
LLVM,RISCV,1192,auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
LLVM,RISCV,1193,"BuildMI(LoopTailMBB, DL, TII->get(getSCForRMWCap(PtrIsCap, Ordering, CLen)), ScratchReg)"
LLVM,RISCV,1194,
LLVM,RISCV,1195,"if (Width == <NUM_LIT>) return getLRForRMW32(PtrIsCap, Ordering);"
LLVM,RISCV,1196,case AtomicOrdering :: Release :
LLVM,RISCV,1197,return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1198,return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1199,return PtrIsCap ? <STR_LIT> : <STR_LIT>;
LLVM,RISCV,1200,return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1201,
LLVM,RISCV,1202,"llvm_unreachable(""Unreachable code executed"");"
LLVM,RISCV,1203,
LLVM,RISCV,1204,case AtomicOrdering :: AcquireRelease : return <STR_LIT> ;
LLVM,RISCV,1205,case AtomicOrdering :: AcqRel : return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1206,case AtomicOrdering :: AcqRel : return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1207,case AtomicOrdering :: Relaxed : return PtrIsCap ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,1208,return CLen == <NUM_LIT> ? ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) : ( PtrIsCap ? <STR_LIT> : <STR_LIT> ) ;
LLVM,RISCV,1209,"BuildMI(LoopMBB, DL, TII->get(<STR_LIT>), ScratchReg).addReg(DestReg).addReg(IncrReg);"
LLVM,RISCV,1210,
LLVM,RISCV,1211,
LLVM,RISCV,1212,
LLVM,RISCV,1213,"In the first branch, the code generates a machine instruction that reads"
LLVM,RISCV,1214,
LLVM,RISCV,1215,"BuildMI(LoopHeadMBB, DL, TII->get(<STR_LIT>), Scratch1Reg).addReg(DestReg).addImm(<NUM_LIT>);"
LLVM,RISCV,1216,MBBI = NMBBI;
LLVM,RISCV,1217,"case <STR_LIT> : return expandAtomicCmpXchg ( MBB , MBBI , false , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,1218,
LLVM,RISCV,1219,"However, based on the names of the functions being called, it appears that the code is attempting to perform a read-modify-write (RMW) operation on a memory location, and the `Width` variable is being used to determine the size of the memory location being accessed. The `getLRForRMW32` and `getLRForRMW64`"
LLVM,RISCV,1220,return <STR_LIT>;
LLVM,RISCV,1221,
LLVM,RISCV,1222,"llvm_unreachable(""<STR_LIT>"");"
LLVM,RISCV,1223,"return ""MyPass"";"
LLVM,RISCV,1224,
LLVM,RISCV,1225,return <STR_LIT>;
LLVM,RISCV,1226,case AtomicOrdering :: AcqRel : return <STR_LIT> ;
LLVM,RISCV,1227,
LLVM,RISCV,1228,
LLVM,RISCV,1229,
LLVM,RISCV,1230,
LLVM,RISCV,1231,
LLVM,RISCV,1232,return new ExpandCoreVHwlpPseudoPass();
LLVM,RISCV,1233,return new ExpandCoreVHwlpPseudoPass();
LLVM,RISCV,1234,
LLVM,RISCV,1235,"BuildMI( * Preheader, HwlpSetup, DL, TII -> get( <STR_LIT> ) ) . addImm( LoopNum ) . addImm( count ) . addSym( LastInstrSymbol );"
LLVM,RISCV,1236,Here are some possible next statements:
LLVM,RISCV,1237,Here are some possible next statements:
LLVM,RISCV,1238,return Changed;
LLVM,RISCV,1239,
LLVM,RISCV,1240,
LLVM,RISCV,1241,
LLVM,RISCV,1242,"NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end());"
LLVM,RISCV,1243,
LLVM,RISCV,1244,"return expandAuipccInstPair(MBB, MBBI, NextMBBI, <STR_LIT>, SecondOpcode);"
LLVM,RISCV,1245,"return expandAuipccInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,1246,
LLVM,RISCV,1247,
LLVM,RISCV,1248,SecondOpcode = STI.is64Bit() ? <STR_LIT> : <STR_LIT>;
LLVM,RISCV,1249,
LLVM,RISCV,1250,
LLVM,RISCV,1251,unsigned DestReg = MI.getOperand(0).getReg();
LLVM,RISCV,1252,
LLVM,RISCV,1253,
LLVM,RISCV,1254,
LLVM,RISCV,1255,
LLVM,RISCV,1256,
LLVM,RISCV,1257,
LLVM,RISCV,1258,
LLVM,RISCV,1259,
LLVM,RISCV,1260,const MCInstrDesc & Desc = TII -> get ( Opcode ) ;
LLVM,RISCV,1261,Register SrcReg = MBBI->getOperand(<NUM_LIT>).getReg();
LLVM,RISCV,1262,"BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg).addReg(AddrReg).addReg(ScratchReg);"
LLVM,RISCV,1263,
LLVM,RISCV,1264,
LLVM,RISCV,1265,
LLVM,RISCV,1266,"BuildMI(MBB, MBBI, DL, Desc).addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)).add(MBBI->getOperand(<NUM_LIT>)).add(MBBI->getOperand(<NUM_LIT>));"
LLVM,RISCV,1267,
LLVM,RISCV,1268,"NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end());"
LLVM,RISCV,1269,
LLVM,RISCV,1270,
LLVM,RISCV,1271,"BuildMI(MBB, MBBI, DL, TII->get(Opcode), TRI->getSubReg(DestReg, SubRegIdx + I)).addReg(Base).addMemOperand(*(MBBI->memoperands_begin()));"
LLVM,RISCV,1272,"BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(TRI->getSubReg(SrcReg, SubRegIdx + I)).addReg(Base).addMemOperand(*(MBBI->memoperands_begin()));"
LLVM,RISCV,1273,"BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(TRI->getSubReg(SrcReg, SubRegIdx + I)).addReg(Base).addMemOperand(*(MBBI->memoperands_begin()));"
LLVM,RISCV,1274,
LLVM,RISCV,1275,
LLVM,RISCV,1276,
LLVM,RISCV,1277,
LLVM,RISCV,1278,"BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg).addReg(AddrReg);"
LLVM,RISCV,1279,
LLVM,RISCV,1280,"However, based on the syntax and the fact that the code is using the `BuildMI` function, it appears that the code is attempting to generate machine code instructions for a specific architecture. The `BuildMI` function is likely a function that generates a machine code"
LLVM,RISCV,1281,
LLVM,RISCV,1282,"Based on the function signature, it appears that the function takes the following arguments:"
LLVM,RISCV,1283,
LLVM,RISCV,1284,
LLVM,RISCV,1285,"case AtomicRMWInst::Sub: BuildMI(LoopMBB, DL, TII->get(<STR_LIT>), ScratchReg) .addReg(DestReg) .addReg(IncrReg); break;"
LLVM,RISCV,1286,"insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, ScratchReg);"
LLVM,RISCV,1287,
LLVM,RISCV,1288,
LLVM,RISCV,1289,"case <STR_LIT> : return expandAtomicBinOp ( MBB , MBBI , AtomicRMWInst :: Xchg , true , <NUM_LIT> , NextMBBI ) ;"
LLVM,RISCV,1290,"return expandLoadLocalAddress(MBB, MBBI, NextMBBI);"
LLVM,RISCV,1291,template <typename ISA_LIT>
LLVM,RISCV,1292,return new ExpandPseudoPass<ISA_LIT>();
LLVM,RISCV,1293,
LLVM,RISCV,1294,SecondOpcode = STI.is64Bit() ? <STR_LIT> : <STR_LIT>;
LLVM,RISCV,1295,SecondOpcode = STI.is64Bit() ? <STR_LIT> : <STR_LIT>;
LLVM,RISCV,1296,
LLVM,RISCV,1297,"return expandAuipcInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,1298,
LLVM,RISCV,1299,
LLVM,RISCV,1300,return Modified;
LLVM,RISCV,1301,
LLVM,RISCV,1302,
LLVM,RISCV,1303,
LLVM,RISCV,1304,
LLVM,RISCV,1305,
LLVM,RISCV,1306,"return ""MyPass"";"
LLVM,RISCV,1307,Some possible next statements could include:
LLVM,RISCV,1308,
LLVM,RISCV,1309,SavedRegs.set(FP);
LLVM,RISCV,1310,
LLVM,RISCV,1311,
LLVM,RISCV,1312,"BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);"
LLVM,RISCV,1313,const TargetRegisterClass * RC = & <STR_LIT> ;
LLVM,RISCV,1314,return MF.getTarget().Options.DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
LLVM,RISCV,1315,return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI -> hasVarSizedObjects ( ) ;
LLVM,RISCV,1316,return isInt < <NUM_LIT> > ( MFI -> getMaxCallFrameSize ( ) + getStackAlignment ( ) ) && ! MFI -> hasVarSizedObjects ( ) ;
LLVM,RISCV,1317,"TargetFrameLowering::TargetFrameLowering(TargetFrameLowering::StackGrowsDown, <NUM_LIT>, <NUM_LIT>)"
LLVM,RISCV,1318,"TargetFrameLowering::TargetFrameLowering(TargetFrameLowering::StackGrowsDown, <NUM_LIT>, <NUM_LIT>)"
LLVM,RISCV,1319,
LLVM,RISCV,1320,"BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg).addReg(SrcReg).addReg(ScratchReg, RegState::Kill).setMIFlag(Flag);"
LLVM,RISCV,1321,
LLVM,RISCV,1322,
LLVM,RISCV,1323,uint64_t StackSize = Offset;
LLVM,RISCV,1324,const auto * RVFI = MF->getInfo<ISA_LIT>MachineFunctionInfo>();
LLVM,RISCV,1325,SavedRegs.set(Regs[i]);
LLVM,RISCV,1326,"static const MCPhysReg CSRegs[] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR"
LLVM,RISCV,1327,MFI->setStackSize(FrameSize);
LLVM,RISCV,1328,if (Amount != <NUM_LIT>) {
LLVM,RISCV,1329,if ( RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ) {
LLVM,RISCV,1330,"adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset, MachineInstr::FrameDestroy);"
LLVM,RISCV,1331,"BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlag(MachineInstr::FrameSetup);"
LLVM,RISCV,1332,Register SCSPReg = <STR_LIT> ( ) ;
LLVM,RISCV,1333,
LLVM,RISCV,1334,CSI.size() > <NUM_LIT>
LLVM,RISCV,1335,return <NUM_LIT>;
LLVM,RISCV,1336,return STI.getFPReg();
LLVM,RISCV,1337,"Offset += StackOffset::get(ScalarLocalVarSize, RVFI->getRVVStackSize());"
LLVM,RISCV,1338,
LLVM,RISCV,1339,
LLVM,RISCV,1340,return SpillLibCalls[CSI.size()];
LLVM,RISCV,1341,return STI.getSPReg();
LLVM,RISCV,1342,return STI.getSPReg();
LLVM,RISCV,1343,
LLVM,RISCV,1344,"However, based on the name of the method and the context in which it is being called, it is likely that the next statement will be a call to the `getStackIDForScalableVectors` method, which will return the stack ID for scalable vectors. The returned stack ID will then be used to retrieve the stack frame for the current function, which will be stored in the `"
LLVM,RISCV,1345,"alignTo(MFI.getStackSize() + RVFI->getRVVPadding(), getStackAlign());"
LLVM,RISCV,1346,return ( MFI . hasVarSizedObjects ( ) || ( ! hasReservedCallFrame ( MF ) && ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) != <NUM_LIT> ) ) ) && TRI -> hasStackRealignment ( MF ) ;
LLVM,RISCV,1347,
LLVM,RISCV,1348,
LLVM,RISCV,1349,return MF.getTarget().Options.DisableFramePointerElim(MF) || RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
LLVM,RISCV,1350,return MF.hasReservedCallFrame();
LLVM,RISCV,1351,return false;
LLVM,RISCV,1352,"For example, the next statement could be a call to the `hasVInstructions` method of the `Subtarget` object, which would return a boolean value indicating whether the subtarget has any V"
LLVM,RISCV,1353,"For example, the next statement could be a call to the `hasVInstructions` method of the `Subtarget` object, which would return a boolean value indicating whether the subtarget has any V"
LLVM,RISCV,1354,"return any_of(MF, [&TII](const MachineBasicBlock &MBB) { return any_of(MBB, [&TII](const MachineInstr &MI) { return TII.isRVVSpill(MI, true); }); });"
LLVM,RISCV,1355,"return any_of(MF, [&TII](const MachineBasicBlock &MBB) { return any_of(MBB, [&TII](const MachineInstr &MI) { return TII.isRVVSpill(MI, true); }); });"
LLVM,RISCV,1356,
LLVM,RISCV,1357,Size = Info.getSize();`
LLVM,RISCV,1358,"TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);"
LLVM,RISCV,1359,
LLVM,RISCV,1360,"BuildMI(MBB, MBBI, DL, TII->get(<STR_LIT>), DestReg).addReg(SrcReg).addImm(Val).setMIFlag(Flag);"
LLVM,RISCV,1361,
LLVM,RISCV,1362,
LLVM,RISCV,1363,for (unsigned i = 0; i < CSRegs.size(); ++i) {
LLVM,RISCV,1364,MFI->setStackSize(FrameSize);
LLVM,RISCV,1365,"FrameSize = alignTo(FrameSize, StackAlign);"
LLVM,RISCV,1366,"adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);"
LLVM,RISCV,1367,return MBB.erase(MI);
LLVM,RISCV,1368,
LLVM,RISCV,1369,for (const CalleeSavedInfo &CSI : CSI) {
LLVM,RISCV,1370,"adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);"
LLVM,RISCV,1371,
LLVM,RISCV,1372,
LLVM,RISCV,1373,
LLVM,RISCV,1374,RC = &RegInfo->getRegClassForKind(TargetRegisterKind::RIP);
LLVM,RISCV,1375,
LLVM,RISCV,1376,"TargetFrameLowering(StackGrowsDown, Align(NUM_LIT), NUM_LIT)"
LLVM,RISCV,1377,"TargetFrameLowering(StackGrowsDown, Align(NUM_LIT), NUM_LIT)"
LLVM,RISCV,1378,"Offset = alignTo(Offset + ObjectSize, <NUM_LIT>);"
LLVM,RISCV,1379,"Offset = alignTo(Offset + ObjectSize, <NUM_LIT>);"
LLVM,RISCV,1380,MFI.setStackSize(FrameSize);
LLVM,RISCV,1381,
LLVM,RISCV,1382,uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
LLVM,RISCV,1383,if ( hasFP ( MF ) ) {
LLVM,RISCV,1384,RS->addScavengingFrameIndex(RegScavFI);
LLVM,RISCV,1385,RVFI->setCalleeSavedStackSize(Size);
LLVM,RISCV,1386,return true;
LLVM,RISCV,1387,return true;
LLVM,RISCV,1388,return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(MF);
LLVM,RISCV,1389,
LLVM,RISCV,1390,return true;
LLVM,RISCV,1391,return false;
LLVM,RISCV,1392,
LLVM,RISCV,1393,
LLVM,RISCV,1394,this->setTargetSubtarget(&STI);
LLVM,RISCV,1395,this->setTargetSubtarget(&STI);
LLVM,RISCV,1396,"BuildMI(MBB, MI, DL, TII.get(<STR_LIT>), <STR_LIT>).addExternalSymbol(SpillLibCall, <STR_LIT>).setMIFlag(MachineInstr::FrameSetup);"
LLVM,RISCV,1397,uint64_t StackBase = MFI.getStackBase();
LLVM,RISCV,1398,"uint64_t FrameSize = alignTo(MFI.getStackSize(), StackAlign);"
LLVM,RISCV,1399,uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
LLVM,RISCV,1400,
LLVM,RISCV,1401,MFI.setMaxCallFrameSize(MaxCallSize);
LLVM,RISCV,1402,"adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset, MachineInstr::FrameDestroy);"
LLVM,RISCV,1403,if ( FirstSPAdjustAmount ) StackSize = FirstSPAdjustAmount ;
LLVM,RISCV,1404,"BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);"
LLVM,RISCV,1405,
LLVM,RISCV,1406,StackAlign = getStackAlignment(); if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) {
LLVM,RISCV,1407,
LLVM,RISCV,1408,FrameReg = <STR_LIT> ;
LLVM,RISCV,1409,return false;
LLVM,RISCV,1410,RS.scavengeRegisters(*TmpMBB);
LLVM,RISCV,1411,return true;
LLVM,RISCV,1412,
LLVM,RISCV,1413,const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ;
LLVM,RISCV,1414,const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ;
LLVM,RISCV,1415,
LLVM,RISCV,1416,
LLVM,RISCV,1417,Offset += RVFI->getVarArgsSaveSize();
LLVM,RISCV,1418,
LLVM,RISCV,1419,"FrameSize = alignTo(FrameSize, TRI->getSpillAlignment(<STR_LIT>));"
LLVM,RISCV,1420,FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
LLVM,RISCV,1421,Offset += MFI.getStackSize();
LLVM,RISCV,1422,
LLVM,RISCV,1423,
LLVM,RISCV,1424,return ( ( MFI . hasVarSizedObjects ( ) || RVFI -> hasSpillVRs ( ) ) && TRI -> needsStackRealignment ( MF ) ) ;
LLVM,RISCV,1425,
LLVM,RISCV,1426,
LLVM,RISCV,1427,"BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg).addReg(SPReg).addReg(FactorRegister, RegState::Kill).setMIFlag(Flag);"
LLVM,RISCV,1428,SavedRegs.set(CSRegs[i]);
LLVM,RISCV,1429,if ( ! hasReservedCallFrame ( MF ) ) { ... }
LLVM,RISCV,1430,if (FirstSPAdjustAmount != 0) {
LLVM,RISCV,1431,
LLVM,RISCV,1432,return <STR_LIT>;
LLVM,RISCV,1433,Size += MFI.getObjectSize(FrameIdx);
LLVM,RISCV,1434,"NewMI->copyImplicitOps(*MF, *MI);`"
LLVM,RISCV,1435,const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;
LLVM,RISCV,1436,return <NUM_LIT> - StackAlign;
LLVM,RISCV,1437,uint64_t StackOffset = StackSize - StackAlign;
LLVM,RISCV,1438,
LLVM,RISCV,1439,FrameReg = RI->getFrameRegister(MF);
LLVM,RISCV,1440,uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ;
LLVM,RISCV,1441,"if ( hasBP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , BPReg ) . addReg ( SPReg ) . addImm ( <NUM_LIT> ) ; }"
LLVM,RISCV,1442,"unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -MFI.getStackSize()));"
LLVM,RISCV,1443,Some possible next statements could include:
LLVM,RISCV,1444,Some possible next statements could include:
LLVM,RISCV,1445,
LLVM,RISCV,1446,
LLVM,RISCV,1447,return true;
LLVM,RISCV,1448,"BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);"
LLVM,RISCV,1449,
LLVM,RISCV,1450,
LLVM,RISCV,1451,
LLVM,RISCV,1452,
LLVM,RISCV,1453,uint64_t RVVStackSize = RVFI->getRVVStackSize();
LLVM,RISCV,1454,uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
LLVM,RISCV,1455,if ( hasFP ( MF ) ) {
LLVM,RISCV,1456,
LLVM,RISCV,1457,Size += RegInfo->getSpillSize(*RC);
LLVM,RISCV,1458,SavedRegs.set(<STR_LIT>);`
LLVM,RISCV,1459,SavedRegs = SavedRegs + determineCalleeSaves(MF
LLVM,RISCV,1460,assert(hasFP(MF) && <STR_LIT>);
LLVM,RISCV,1461,if ( hasFP ( MF ) ) {
LLVM,RISCV,1462,
LLVM,RISCV,1463,report_fatal_error(<STR_LIT>)
LLVM,RISCV,1464,SavedRegs.set(<STR_LIT>);`
LLVM,RISCV,1465,SavedRegs.set(MF.getFrameInfo().getCalleeSavedRegs());
LLVM,RISCV,1466,
LLVM,RISCV,1467,uint64_t StackAlign = RI->needsStackRealignment(MF) ? MFI.getMaxAlignment() : getStackAlignment();
LLVM,RISCV,1468,LastFrameDestroy->eraseFromParent();
LLVM,RISCV,1469,"adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);"
LLVM,RISCV,1470,FrameReg = <STR_LIT>;
LLVM,RISCV,1471,"Offset += StackOffset::get(alignTo(MFI->getStackSize() - RVFI->getCalleeSavedStackSize(), <NUM_LIT>), RVFI->getRVVStackSize());"
LLVM,RISCV,1472,
LLVM,RISCV,1473,"adjustReg(MBB, MBBI, DL, FPReg, SPReg, StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);"
LLVM,RISCV,1474,for (const auto &Entry : CSI) {
LLVM,RISCV,1475,return MBB.erase(I);
LLVM,RISCV,1476,for (const auto &Entry : CSI) {
LLVM,RISCV,1477,"unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(nullptr, RI->getDwarfRegNum(SPReg, true), -FPOffset));"
LLVM,RISCV,1478,"BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex);"
LLVM,RISCV,1479,"BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION), SPReg).addCFIIndex(CFIIndex);"
LLVM,RISCV,1480,FrameReg = RI->getFrameRegister(MF);
LLVM,RISCV,1481,"unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));"
LLVM,RISCV,1482,"MRI->getDwarfFrameInfo(MF, MBB, MBBI, DL, CSI, StackSize, RVFI->getVarArgsSaveSize());"
LLVM,RISCV,1483,
LLVM,RISCV,1484,
LLVM,RISCV,1485,Subtarget.getStdExtV()
LLVM,RISCV,1486,
LLVM,RISCV,1487,return MFI.hasBP();
LLVM,RISCV,1488,
LLVM,RISCV,1489,RI->needsStackRealignment(MF);
LLVM,RISCV,1490,"adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);"
LLVM,RISCV,1491,
LLVM,RISCV,1492,SavedRegs.set(<STR_LIT>);`
LLVM,RISCV,1493,FrameSize += (MaxStackAlign.value() - StackAlign.value());
LLVM,RISCV,1494,return MBB.erase(MI);
LLVM,RISCV,1495,uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
LLVM,RISCV,1496,if ( RI->needsStackRealignment(MF) || MFI.hasVarSizedObjects() ) {
LLVM,RISCV,1497,if ( hasFP ( MF ) ) {
LLVM,RISCV,1498,Register SCSPReg = <STR_LIT> ( ) ;
LLVM,RISCV,1499,Register SCSPReg = <STR_LIT> ( ) ;
LLVM,RISCV,1500,
LLVM,RISCV,1501,return <NUM_LIT> - getStackAlign().value();`
LLVM,RISCV,1502,
LLVM,RISCV,1503,
LLVM,RISCV,1504,NonLibcallCSI.reserve(CSI.size());
LLVM,RISCV,1505,return NonLibcallCSI;
LLVM,RISCV,1506,TRI = STI.getRegisterInfo();
LLVM,RISCV,1507,return MFI.hasBP();
LLVM,RISCV,1508,return RegInfo->hasFP(MFI.getFP());
LLVM,RISCV,1509,return MF.getTarget().Options.DisableFramePointerElim(MF) || RegInfo->needsStackRealignment(MF) || MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
LLVM,RISCV,1510,return MF.hasReservedCallFrame();
LLVM,RISCV,1511,
LLVM,RISCV,1512,
LLVM,RISCV,1513,
LLVM,RISCV,1514,"TargetFrameLowering(StackGrowsDown, <NUM_LIT>, <NUM_LIT>)"
LLVM,RISCV,1515,"TargetFrameLowering(StackGrowsDown, <NUM_LIT>, <NUM_LIT>)"
LLVM,RISCV,1516,"BuildMI(MBB, MI, DL, TII.get(<STR_LIT>), <STR_LIT>).addExternalSymbol(SpillLibCall, <STR_LIT>).setMIFlag(MachineInstr::FrameSetup);"
LLVM,RISCV,1517,for (auto &CS : NonLibcallCSI) {
LLVM,RISCV,1518,Value * Stride;
LLVM,RISCV,1519,Builder.SetInsertPoint(GEP->getSourceElementType());
LLVM,RISCV,1520,
LLVM,RISCV,1521,
LLVM,RISCV,1522,"for (auto *II : Gathers) Changed |= tryCreateStridedLoadStore(II, II->getType(), II->getArgOperand(<NUM_LIT>), II->getArgOperand(<NUM_LIT>));"
LLVM,RISCV,1523,
LLVM,RISCV,1524,return new GatherScatterLoweringPass<ISA_LIT>();
LLVM,RISCV,1525,AU.addRequired<TargetPassConfig>();
LLVM,RISCV,1526,
LLVM,RISCV,1527,
LLVM,RISCV,1528,
LLVM,RISCV,1529,"Value * Stride = ConstantInt::get(StartVal->getType(), StrideVal);"
LLVM,RISCV,1530,if (Step->getType()->isIntegerTy() && Step->getType()->getIntegerBitWidth() == 32) {
LLVM,RISCV,1531,Value * Splat = getSplatValue(BO->getOperand(OtherIndex));
LLVM,RISCV,1532,
LLVM,RISCV,1533,
LLVM,RISCV,1534,
LLVM,RISCV,1535,bool <ISA_LIT>GatherScatterLowering :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; auto & TPC = getAnalysis < TargetPassConfig > ( ) ; auto & TM = TPC . getTM < <ISA_LIT>TargetMachine > ( ) ; ST = & TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; if ( ! ST -> hasVInstructions ( ) || ! ST -
LLVM,RISCV,1536,Call -> takeName ( II ) ;
LLVM,RISCV,1537,Call->setOnlyReadsMemory(true);
LLVM,RISCV,1538,if (InstrInfo.hasAVLReg() && InstrInfo.AVLReg == <STR_LIT>) {
LLVM,RISCV,1539,assert ( isValid ( ) && <STR_LIT> ) ;
LLVM,RISCV,1540,DefMI->getVRegDef(Require->getAVLReg());
LLVM,RISCV,1541,
LLVM,RISCV,1542,
LLVM,RISCV,1543,
LLVM,RISCV,1544,CurInfo = <STR_LIT> ( ) ;
LLVM,RISCV,1545,return false;
LLVM,RISCV,1546,if (InReg.isVirtual()) return true;
LLVM,RISCV,1547,if (DefInfo.hasSameAVL(PBBInfo.Exit) || !DefInfo.hasSameVTYPE(PBBInfo.Exit)) return true;
LLVM,RISCV,1548,InstrInfo.setAVLReg(VLOp.getReg());
LLVM,RISCV,1549,if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(<STR_LIT>) || MI.modifiesRegister(<STR_LIT>)) { BBInfo.Change = <STR_LIT>(); }
LLVM,RISCV,1550,
LLVM,RISCV,1551,if (InstrInfo.MaskRegOp && hasSameVLMAX(InstrInfo) && TailAgnostic == InstrInfo.TailAgnostic && MaskAgnostic == InstrInfo.MaskAgnostic) return true;
LLVM,RISCV,1552,
LLVM,RISCV,1553,return getAVLReg() == <STR_LIT>;
LLVM,RISCV,1554,
LLVM,RISCV,1555,return (this->getSEW() == Other.getSEW());
LLVM,RISCV,1556,return getAVLImm() == <NUM_LIT>;
LLVM,RISCV,1557,return false;
LLVM,RISCV,1558,
LLVM,RISCV,1559,return MI.getOpcode() == <STR_LIT> || MI.getOpcode() == <STR_LIT> || MI.getOpcode() == <STR_LIT>;
LLVM,RISCV,1560,
LLVM,RISCV,1561,if (PHI->getOperand(PHIOp)->getReg() == AVLReg) {
LLVM,RISCV,1562,if (InReg.isVirtual()) return true;
LLVM,RISCV,1563,for (const MachineBasicBlock &MBB : MF) {
LLVM,RISCV,1564,
LLVM,RISCV,1565,
LLVM,RISCV,1566,PrevVSETVLIMI = nullptr;
LLVM,RISCV,1567,return false;
LLVM,RISCV,1568,return false;
LLVM,RISCV,1569,if ( HasPolicy ) {
LLVM,RISCV,1570,unsigned Log2SEW = MI.getOperand(NumOperands - <NUM_LIT>).getImm();
LLVM,RISCV,1571,const MachineOperand &VLOp = MI.getOperand(NumOperands - <NUM_LIT>);
LLVM,RISCV,1572,return hasSameAVL(InstrInfo);
LLVM,RISCV,1573,return false;
LLVM,RISCV,1574,return true;
LLVM,RISCV,1575,
LLVM,RISCV,1576,
LLVM,RISCV,1577,InInfo.setUnknown();
LLVM,RISCV,1578,const MachineOperand & VLOp = MI . getOperand ( getVLOpNum ( MI ) ) ;
LLVM,RISCV,1579,const MachineOperand & VLOp = MI . getOperand ( getVLOpNum ( MI ) ) ;
LLVM,RISCV,1580,HadVectorOp = true;
LLVM,RISCV,1581,
LLVM,RISCV,1582,if (PrevMI) {
LLVM,RISCV,1583,"CurInfo = computeInfoForInstr(MI, TSFlags, MRI);"
LLVM,RISCV,1584,BlockInfo[UnavailablePred->getNumber()].Exit = AvailableInfo;
LLVM,RISCV,1585,
LLVM,RISCV,1586,dbgs() << <STR_LIT>;
LLVM,RISCV,1587,dbgs() << <STR_LIT>;
LLVM,RISCV,1588,
LLVM,RISCV,1589,
LLVM,RISCV,1590,
LLVM,RISCV,1591,
LLVM,RISCV,1592,
LLVM,RISCV,1593,return <STR_LIT> ( MI . getDesc ( ) ) ;
LLVM,RISCV,1594,
LLVM,RISCV,1595,return false;
LLVM,RISCV,1596,return ST.hasAVLImm();
LLVM,RISCV,1597,"BuildMI(MBB, InsertPt, DL, TII->get(<STR_LIT>)).addReg(<STR_LIT>, RegState::Define | RegState::Dead).addReg(<STR_LIT>, RegState::Kill).addImm(Info.encodeVTYPE()).addReg(<STR_LIT>, RegState::Implicit);"
LLVM,RISCV,1598,if (Require.StoreOp && VLMul == Require.VLMul && SEW == Require.SEW) return true;
LLVM,RISCV,1599,return false;
LLVM,RISCV,1600,"For example, the"
LLVM,RISCV,1601,if (MI.getOpcode() == <STR_LIT>) return true;
LLVM,RISCV,1602,"return !canSkipVSETVLIForLoadStore(MI, Require, CurInfo);"
LLVM,RISCV,1603,return false;
LLVM,RISCV,1604,OS << <STR_LIT> << ( unsigned ) AVLReg;
LLVM,RISCV,1605,BlockInfo.clear();
LLVM,RISCV,1606,"InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, false);"
LLVM,RISCV,1607,
LLVM,RISCV,1608,BBInfo.Change = getInfoForVSETVLI(MI);
LLVM,RISCV,1609,CurInfo = <STR_LIT> ( ) ;
LLVM,RISCV,1610,"return encodeVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);"
LLVM,RISCV,1611,"return encodeVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);"
LLVM,RISCV,1612,
LLVM,RISCV,1613,return (getVTYPE() == Other.getVTYPE());
LLVM,RISCV,1614,DestReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ;
LLVM,RISCV,1615,return *this;
LLVM,RISCV,1616,return <STR_LIT> ( ) ;
LLVM,RISCV,1617,return getAVLImm() == Other.getAVLImm();
LLVM,RISCV,1618,return false;
LLVM,RISCV,1619,"However, based on the name of the function and the parameters it takes, it is likely that the function is setting the value of a variable or property based on the input parameters. The `assert` statement is used to check that the function is being called with valid input parameters, and the `<STR_LIT>` parameter is likely"
LLVM,RISCV,1620,
LLVM,RISCV,1621,
LLVM,RISCV,1622,HadVectorOp = true;
LLVM,RISCV,1623,"BuildMI(MBB, MI, DL, TII->get(""<STR_LIT>""))"
LLVM,RISCV,1624,"BuildMI(MBB, MI, DL, TII->get(<STR_LIT>)).addReg(<STR_LIT>, RegState::Define | RegState::Dead).addReg(<STR_LIT>, RegState::Kill).addImm(Info.encodeVTYPE()).addReg(<STR_LIT>, RegState::Implicit);"
LLVM,RISCV,1625,VSETVLIInfo DefInfo = getInfoForVSETVLI( *DefMI );
LLVM,RISCV,1626,
LLVM,RISCV,1627,MachineInstr * DefMI = MRI->getVRegDef(InReg);
LLVM,RISCV,1628,"InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, false, MaskRegOp);"
LLVM,RISCV,1629,LMul = Fractional ? ( <NUM_LIT> / LMul ) : ( LMul * <NUM_LIT> ) ;
LLVM,RISCV,1630,
LLVM,RISCV,1631,
LLVM,RISCV,1632,BBInfo.Pred = InInfo.intersect(BlockInfo[P->getNumber()].Exit);
LLVM,RISCV,1633,const MachineOperand &VLMul = MI.getOperand(NumOperands - 1);
LLVM,RISCV,1634,BBInfo.Change.isValid()
LLVM,RISCV,1635,BBInfo.Change = <STR_LIT> ( ) ;
LLVM,RISCV,1636,return new InsertVSETVLIPass<ISA_LIT>();
LLVM,RISCV,1637,
LLVM,RISCV,1638,MI = MRI->getVRegDef(MI->getOperand(<NUM_LIT>).getReg());
LLVM,RISCV,1639,Some possible next statements could include:
LLVM,RISCV,1640,
LLVM,RISCV,1641,MI . getOperand ( <NUM_LIT> ) . setIsDead ( false ) ;
LLVM,RISCV,1642,return AVLImm;
LLVM,RISCV,1643,return AVLImm;
LLVM,RISCV,1644,
LLVM,RISCV,1645,NewInfo.setAVLReg(AVLReg);
LLVM,RISCV,1646,NewInfo.setVTYPE(MI.getOperand(<NUM_LIT>).getImm());
LLVM,RISCV,1647,
LLVM,RISCV,1648,
LLVM,RISCV,1649,
LLVM,RISCV,1650,
LLVM,RISCV,1651,Info.setUnknown(); return Info;
LLVM,RISCV,1652,return State == AVLIsImm;
LLVM,RISCV,1653,return State == AVLIsImm;
LLVM,RISCV,1654,return State == AVLIsReg;
LLVM,RISCV,1655,return false;
LLVM,RISCV,1656,return getAVLReg() == Other.getAVLReg();
LLVM,RISCV,1657,
LLVM,RISCV,1658,return getSEWLMULRatio() == Other.getSEWLMULRatio();
LLVM,RISCV,1659,
LLVM,RISCV,1660,return SEWLMULRatioOnly;
LLVM,RISCV,1661,"BuildMI(MBB, MI, DL, TII->get(<STR_LIT>)).addReg(<STR_LIT>, RegState::Define | RegState::Dead).addReg(<STR_LIT>, RegState::Kill).addImm(Info.encodeVTYPE()).addReg(<STR_LIT>, RegState::Implicit);"
LLVM,RISCV,1662,return *this;
LLVM,RISCV,1663,return true;
LLVM,RISCV,1664,
LLVM,RISCV,1665,
LLVM,RISCV,1666,
LLVM,RISCV,1667,
LLVM,RISCV,1668,return Other;
LLVM,RISCV,1669,return Other;
LLVM,RISCV,1670,
LLVM,RISCV,1671,if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVTYPE(CurInfo)) { return false; }
LLVM,RISCV,1672,if (PHI->getNumOperands() > 0) {
LLVM,RISCV,1673,InsertVSETVLIPass::runOnFunction(Function &F) {
LLVM,RISCV,1674,void initialize<ISA_LIT>InsertVSETVLIPass(PassRegistry &Registry) {
LLVM,RISCV,1675,
LLVM,RISCV,1676,AVLImm = Imm;
LLVM,RISCV,1677,AVLReg = Reg ;
LLVM,RISCV,1678,
LLVM,RISCV,1679,
LLVM,RISCV,1680,
LLVM,RISCV,1681,
LLVM,RISCV,1682,
LLVM,RISCV,1683,
LLVM,RISCV,1684,O << '(' << getRegisterName(Base) << ')' ;
LLVM,RISCV,1685,"O << ""bdaddr("" << MI->getOperand(OpNum).getReg() << "")"";"
LLVM,RISCV,1686,
LLVM,RISCV,1687,if (MI->getOperand(opNum)->isImm()) { OS << <STR_LIT>; }
LLVM,RISCV,1688,OS << MI -> getOperand ( opNum ) . getImm ( ) ;
LLVM,RISCV,1689,"printOperand(MI, OpNum, O);"
LLVM,RISCV,1690,
LLVM,RISCV,1691,
LLVM,RISCV,1692,"printInstruction(MI, O);"
LLVM,RISCV,1693,"printInstruction(MI, O);"
LLVM,RISCV,1694,
LLVM,RISCV,1695,OS << getRegisterName ( MI -> getOperand ( opNum ) . getReg ( ) ) ;
LLVM,RISCV,1696,
LLVM,RISCV,1697,
LLVM,RISCV,1698,
LLVM,RISCV,1699,
LLVM,RISCV,1700,O << Value;
LLVM,RISCV,1701,O << Value;
LLVM,RISCV,1702,O << Value;
LLVM,RISCV,1703,O << Value;
LLVM,RISCV,1704,
LLVM,RISCV,1705,O << Value;
LLVM,RISCV,1706,Value = MI->getOperand(OpNum)->getImm();
LLVM,RISCV,1707,
LLVM,RISCV,1708,Value = MI->getOperand(OpNum)->getImm();
LLVM,RISCV,1709,O << <STR_LIT>;
LLVM,RISCV,1710,
LLVM,RISCV,1711,
LLVM,RISCV,1712,O << 'i';
LLVM,RISCV,1713,if (MO.isMem()) { ... }
LLVM,RISCV,1714,
LLVM,RISCV,1715,
LLVM,RISCV,1716,O << <STR_LIT> << Sew << <STR_LIT> << Lmul;
LLVM,RISCV,1717,"if (NoAliases || !printAliasInstr(NewMI, STI, O)) printInstruction(NewMI, STI, O);"
LLVM,RISCV,1718,O << <STR_LIT> << Lmul;
LLVM,RISCV,1719,"O << ""c"" << Imm;"
LLVM,RISCV,1720,O << SpecialCapReg -> Name;
LLVM,RISCV,1721,NoAliases = true;
LLVM,RISCV,1722,
LLVM,RISCV,1723,
LLVM,RISCV,1724,"printInstruction(NewMI, Address, STI, O);"
LLVM,RISCV,1725,"Res = DecompressInstruction(NewMI, &UncompressedMI);"
LLVM,RISCV,1726,"printRegName ( O , MO . getReg ( ) ) ;"
LLVM,RISCV,1727,O << Imm;
LLVM,RISCV,1728,
LLVM,RISCV,1729,
LLVM,RISCV,1730,case <STR_LIT> :
LLVM,RISCV,1731,"O << "" "";"
LLVM,RISCV,1732,O << <STR_LIT> << Ediv;
LLVM,RISCV,1733,"However, based on the names of the variables and the operations being performed, it is likely that the next statement of the code will be a calculation involving the values of these variables. For example, it could be a statement that sets the value of `Sew` to the result of a bitwise AND operation between `Imm` and a constant"
LLVM,RISCV,1734,
LLVM,RISCV,1735,
LLVM,RISCV,1736,
LLVM,RISCV,1737,"If `MC.isReg()` returns `false`, then the next statement will be executed if `MC.isIm"
LLVM,RISCV,1738,O << getRegisterName(MC.getReg());
LLVM,RISCV,1739,
LLVM,RISCV,1740,
LLVM,RISCV,1741,
LLVM,RISCV,1742,
LLVM,RISCV,1743,O << formatHex ( Value ) ;
LLVM,RISCV,1744,O << formatHex ( Value ) ;
LLVM,RISCV,1745,
LLVM,RISCV,1746,O << 'o' ;
LLVM,RISCV,1747,O << 'r' ;
LLVM,RISCV,1748,if (Res) {
LLVM,RISCV,1749,
LLVM,RISCV,1750,
LLVM,RISCV,1751,
LLVM,RISCV,1752,
LLVM,RISCV,1753,
LLVM,RISCV,1754,O << SysReg->Name;
LLVM,RISCV,1755,
LLVM,RISCV,1756,
LLVM,RISCV,1757,FRMArg = MI->getOperand(OpNo)->getImm();
LLVM,RISCV,1758,"Res = uncompressInst(UncompressedMI, *MI, MRI, STI);"
LLVM,RISCV,1759,NewMI = const_cast < MCInst * > ( & UncompressedMI ) ;
LLVM,RISCV,1760,"printImm ( O , MO . getImm ( ) ) ;"
LLVM,RISCV,1761,
LLVM,RISCV,1762,"InstPrinter::InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {"
LLVM,RISCV,1763,"InstPrinter::InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {"
LLVM,RISCV,1764,MMO->setOffset(Offset);
LLVM,RISCV,1765,"However, based on the naming conventions and the context of the code, it is likely that the next statement will be a call to the `addMemOperand` method of the `MachineInstrBuilder` class, passing in the `MachineMemOperand` object created by the previous line"
LLVM,RISCV,1766,return MIB.addImm(Offset).addFrameIndex(FI).addMemOperand(MMO);
LLVM,RISCV,1767,unsigned Reg;
LLVM,RISCV,1768,unsigned Reg;
LLVM,RISCV,1769,FBB = TBB;
LLVM,RISCV,1770,
LLVM,RISCV,1771,case ARM::t2MOVr:
LLVM,RISCV,1772,
LLVM,RISCV,1773,return ( STI . isRV64 ( ) || STI . isRV32 ( ) ) ? <NUM_LIT> : <NUM_LIT> ;
LLVM,RISCV,1774,return ( STI . isRV64 ( ) || STI . isRV32 ( ) ) ? <NUM_LIT> : <NUM_LIT> ;
LLVM,RISCV,1775,
LLVM,RISCV,1776,
LLVM,RISCV,1777,count++;
LLVM,RISCV,1778,
LLVM,RISCV,1779,
LLVM,RISCV,1780,Target = &MI->getOperand(<NUM_LIT>);
LLVM,RISCV,1781,
LLVM,RISCV,1782,"return isSimpleMove(MI, FrameIndex, <STR_LIT>);"
LLVM,RISCV,1783,FrameIndex = MI->getOperand(<NUM_LIT>).getIndex();
LLVM,RISCV,1784,
LLVM,RISCV,1785,
LLVM,RISCV,1786,
LLVM,RISCV,1787,
LLVM,RISCV,1788,I = Target->getNext();
LLVM,RISCV,1789,
LLVM,RISCV,1790,RI = new RI(sti);
LLVM,RISCV,1791,
LLVM,RISCV,1792,if ( NumTerminators > <NUM_LIT> ) return true ;
LLVM,RISCV,1793,int HighWidth = ( HighOffset == OffsetA ) ? WidthA : WidthB;
LLVM,RISCV,1794,if (LowOffset == HighOffset) {
LLVM,RISCV,1795,
LLVM,RISCV,1796,
LLVM,RISCV,1797,
LLVM,RISCV,1798,
LLVM,RISCV,1799,"if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMul)) {"
LLVM,RISCV,1800,"return std::make_pair(TF & Mask, TF & ~Mask);"
LLVM,RISCV,1801,Here's a breakdown of the code:
LLVM,RISCV,1802,
LLVM,RISCV,1803,
LLVM,RISCV,1804,
LLVM,RISCV,1805,Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ;
LLVM,RISCV,1806,const MachineOperand * BaseReg = nullptr;
LLVM,RISCV,1807,return MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;
LLVM,RISCV,1808,return MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;
LLVM,RISCV,1809,
LLVM,RISCV,1810,"llvm::erase_if(RepeatedSequenceLocs, CannotInsertCall);"
LLVM,RISCV,1811,
LLVM,RISCV,1812,return TargetFlags;
LLVM,RISCV,1813,using namespace II;
LLVM,RISCV,1814,
LLVM,RISCV,1815,
LLVM,RISCV,1816,
LLVM,RISCV,1817,RS->enterBasicBlockEnd(MBB);
LLVM,RISCV,1818,
LLVM,RISCV,1819,case <STR_LIT> :
LLVM,RISCV,1820,
LLVM,RISCV,1821,"case <STR_LIT> :     return isIntN(<NUM_LIT>, BrOffset);"
LLVM,RISCV,1822,
LLVM,RISCV,1823,"return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ;"
LLVM,RISCV,1824,case <STR_LIT> : if (MI.getOperand(<NUM_LIT>).isReg() && MI.getOperand(<NUM_LIT>).isImm() && MI.getOperand(<NUM_LIT>).getImm() == <NUM_L
LLVM,RISCV,1825,return false;
LLVM,RISCV,1826,if (F.hasLinkOnceODRLinkage()) return false;
LLVM,RISCV,1827,FrameIndex = MI.getOperand(<NUM_LIT>).getIndex();
LLVM,RISCV,1828,
LLVM,RISCV,1829,"return !CheckFIs || any_of(MI.operands(), [](const MachineOperand &MO) { return MO.isFI(); });"
LLVM,RISCV,1830,if (Opcode == <ISA_LIT>InstrInfo :: getRVVSpillOpcode ()) return true;
LLVM,RISCV,1831,
LLVM,RISCV,1832,
LLVM,RISCV,1833,FrameIndex = MI.getOperand(<NUM_LIT>).getIndex();
LLVM,RISCV,1834,
LLVM,RISCV,1835,"MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MemoryLocation :: UnknownSize , MFI . getObjectAlign ( FI ) ) ;"
LLVM,RISCV,1836,
LLVM,RISCV,1837,
LLVM,RISCV,1838,for ( <STR_LIT> & Inst : Seq ) {
LLVM,RISCV,1839,
LLVM,RISCV,1840,I = I->getNextNode();
LLVM,RISCV,1841,I = MBB.end();
LLVM,RISCV,1842,
LLVM,RISCV,1843,
LLVM,RISCV,1844,
LLVM,RISCV,1845,
LLVM,RISCV,1846,Ok = isUInt < <NUM_LIT> > ( Imm ) ; break ;
LLVM,RISCV,1847,case <STR_LIT> : Ok = isInt < <NUM_LIT> > ( Imm ) ; break ;
LLVM,RISCV,1848,
LLVM,RISCV,1849,
LLVM,RISCV,1850,"for (auto &C : RepeatedSequenceLocs) C.setCallInfo(MachineOutlinerDefault, CallOverhead);"
LLVM,RISCV,1851,if (MI.isInlineAsm()) return outliner::InstrType::Illegal;
LLVM,RISCV,1852,"MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;"
LLVM,RISCV,1853,* BytesAdded += getInstSizeInBytes(MI);
LLVM,RISCV,1854,ScratchReg = MRI.createVirtualRegister(&<STR_LIT>);
LLVM,RISCV,1855,return true;
LLVM,RISCV,1856,FrameIndex = MI.getOperand(<NUM_LIT>).getIndex();
LLVM,RISCV,1857,if (MI.getOperand(<NUM_LIT>).isFI() && MI.getOperand(<NUM_LIT>).isImm() && MI.getOperand(<NUM_LIT>).getImm() == <NUM_LIT>) {
LLVM,RISCV,1858,"BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(<NUM_LIT>);"
LLVM,RISCV,1859,
LLVM,RISCV,1860,MRI.createVirtualRegister(&<STR_LIT>);
LLVM,RISCV,1861,Result = DstReg;
LLVM,RISCV,1862,
LLVM,RISCV,1863,
LLVM,RISCV,1864,unsigned NewOpc;
LLVM,RISCV,1865,
LLVM,RISCV,1866,
LLVM,RISCV,1867,ErrInfo = <STR_LIT>;
LLVM,RISCV,1868,if ( !Ok ) { ErrInfo = <STR_LIT> ; return false ; }
LLVM,RISCV,1869,
LLVM,RISCV,1870,
LLVM,RISCV,1871,MIB.copyImplicitOps(MI);
LLVM,RISCV,1872,
LLVM,RISCV,1873,"MBB.insert(new IndirectBranchInst(DestBB, RestoreBB, DL, BrOffset, RS));"
LLVM,RISCV,1874,if ( MBBI -> getNumDefs ( ) ) {
LLVM,RISCV,1875,ScratchReg = MRI.createVirtualRegister(&<STR_LIT>);
LLVM,RISCV,1876,
LLVM,RISCV,1877,
LLVM,RISCV,1878,"BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(<NUM_LIT>);"
LLVM,RISCV,1879,
LLVM,RISCV,1880,
LLVM,RISCV,1881,
LLVM,RISCV,1882,
LLVM,RISCV,1883,"return getInlineAsmLength(MI.getOperand(<NUM_LIT>).getSymbolName(), *TM.getMCAsmInfo());"
LLVM,RISCV,1884,
LLVM,RISCV,1885,
LLVM,RISCV,1886,DL = I->getDebugLoc();
LLVM,RISCV,1887,
LLVM,RISCV,1888,MachineBasicBlock * MBB = I->getParent();
LLVM,RISCV,1889,
LLVM,RISCV,1890,return DstReg > SrcReg && ( DstReg - SrcReg ) < NumRegs;
LLVM,RISCV,1891,return DstReg > SrcReg && ( DstReg - SrcReg ) < NumRegs;
LLVM,RISCV,1892,"return TargetInstrInfo :: commuteInstructionImpl ( WorkingMI , false , OpIdx1 , OpIdx2 ) ;"
LLVM,RISCV,1893,"BuildMI(MBB, II, DL, TII->get(<STR_LIT>), ScaledRegister).addReg(VL).addImm(ShiftAmount);"
LLVM,RISCV,1894,
LLVM,RISCV,1895,"case CASE_VFMA_OPCODE_LMULS_MF4 ( FMADD , VV ) :"
LLVM,RISCV,1896,"SlotIndex Idx = LIS->ReplaceMachineInstrInMaps(MI, *MIB);"
LLVM,RISCV,1897,return get(Opcode).getSize();
LLVM,RISCV,1898,"MBB.insertBranchInstruction(MBB.getTerminator(), DestBB, RestoreBB, DL, BrOffset, RS);"
LLVM,RISCV,1899,"It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(<STR_LIT>), <STR_LIT>).addGlobalAddress(M.getNamedValue(MF.getName()), <NUM_LIT>, <STR_LIT>));"
LLVM,RISCV,1900,"It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(<STR_LIT>), <STR_LIT>).addGlobalAddress(M.getNamedValue(MF.getName()), <NUM_LIT>, <STR_LIT>));"
LLVM,RISCV,1901,
LLVM,RISCV,1902,
LLVM,RISCV,1903,
LLVM,RISCV,1904,"BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg).addReg(SrcReg, RegState::Kill).addReg(SrcReg, RegState::Kill).setMIFlag(Flag);"
LLVM,RISCV,1905,if (UseVMV_V_I) {
LLVM,RISCV,1906,unsigned Log2SEW = MI.getOperand(OpIdx).getImm();
LLVM,RISCV,1907,return outliner::InstrType::Illegal;
LLVM,RISCV,1908,return outliner::InstrType::Illegal;
LLVM,RISCV,1909,
LLVM,RISCV,1910,
LLVM,RISCV,1911,"BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg).addImm(Inst.Imm).setMIFlag(Flag);"
LLVM,RISCV,1912,"BuildMI(MBB, MBBI, DL, get(Inst.Opc), DstReg).addReg(SrcReg, RegState::Kill).addReg(SrcReg, RegState::Kill).setMIFlag(Flag);"
LLVM,RISCV,1913,
LLVM,RISCV,1914,
LLVM,RISCV,1915,
LLVM,RISCV,1916,Opc = <STR_LIT>;
LLVM,RISCV,1917,
LLVM,RISCV,1918,
LLVM,RISCV,1919,
LLVM,RISCV,1920,
LLVM,RISCV,1921,"MachineInstr & MI = * BuildMI (&MBB, DL, get(PseudoOpcode)).addMBB(TBB);"
LLVM,RISCV,1922,PseudoOpcode = <STR_LIT>;
LLVM,RISCV,1923,
LLVM,RISCV,1924,
LLVM,RISCV,1925,case <STR_LIT>:     return MI.getOperand(<NUM_LIT>).isReg() && MI.getOperand(<NUM_LIT>).getReg() == MI.getOperand(<NUM_LIT>).getReg();
LLVM,RISCV,1926,
LLVM,RISCV,1927,
LLVM,RISCV,1928,return true;
LLVM,RISCV,1929,
LLVM,RISCV,1930,MI.getOperand(<NUM_LIT>).getImm()
LLVM,RISCV,1931,Opcode = <STR_LIT> ;
LLVM,RISCV,1932,STI = STI.getTargetAB
LLVM,RISCV,1933,STI = STI.getTargetAB
LLVM,RISCV,1934,"MachineMemOperand *MMO = MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, MFI.getObjectSize(FI), MFI.getObjectAlign(FI));"
LLVM,RISCV,1935,
LLVM,RISCV,1936,
LLVM,RISCV,1937,return false;
LLVM,RISCV,1938,if ( NumTerminators > <NUM_LIT> ) return true ;
LLVM,RISCV,1939,
LLVM,RISCV,1940,Cond[<NUM_LIT>].setImm(getOppositeBranchOpcode(Cond[<NUM_LIT>].getImm()));
LLVM,RISCV,1941,
LLVM,RISCV,1942,
LLVM,RISCV,1943,I->removeFromParent();
LLVM,RISCV,1944,Opc = <STR_LIT>;
LLVM,RISCV,1945,
LLVM,RISCV,1946,return get(Opcode).getSize();
LLVM,RISCV,1947,FrameIndex = MI.getOperand(<NUM_LIT>).getIndex();
LLVM,RISCV,1948,
LLVM,RISCV,1949,return <NUM_LIT>;
LLVM,RISCV,1950,return MI.getOperand(<NUM_LIT>).getReg();
LLVM,RISCV,1951,
LLVM,RISCV,1952,"BuildMI(MBB, I, DL, get(<STR_LIT>), DstReg).addFrameIndex(FI).addImm(<NUM_LIT>);"
LLVM,RISCV,1953,
LLVM,RISCV,1954,DL = I->getDebugLoc();
LLVM,RISCV,1955,
LLVM,RISCV,1956,case TargetOpcode::INLINEASM_BR: {
LLVM,RISCV,1957,"return getInlineAsmLength(MI.getOperand(<NUM_LIT>).getSymbolName(), *TM.getMCAsmInfo());"
LLVM,RISCV,1958,
LLVM,RISCV,1959,Register N = MRI.createVirtualRegister(&<STR_LIT>);
LLVM,RISCV,1960,"BuildMI(MBB, II, DL, TII->get(<STR_LIT>), N).addReg(<STR_LIT>).addImm(NumOfVReg);"
LLVM,RISCV,1961,return true;
LLVM,RISCV,1962,Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ;
LLVM,RISCV,1963,
LLVM,RISCV,1964,
LLVM,RISCV,1965,"BuildMI(MBB, MBBI, DL, get(<STR_LIT>), DstReg)"
LLVM,RISCV,1966,
LLVM,RISCV,1967,"BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(<NUM_LIT>);"
LLVM,RISCV,1968,Opcode = <STR_LIT>;
LLVM,RISCV,1969,
LLVM,RISCV,1970,else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;
LLVM,RISCV,1971,"BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result).addReg(SrcReg, RegState::Kill).addImm(Inst.Imm).setMIFlag(Flag);"
LLVM,RISCV,1972,
LLVM,RISCV,1973,case TargetOpcode::INLINEASM:
LLVM,RISCV,1974,* The code is part of a switch statement that is handling different opcodes in a machine instruction.
LLVM,RISCV,1975,"return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ;"
LLVM,RISCV,1976,"return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ;"
LLVM,RISCV,1977,FBB = <NUM_LIT>;
LLVM,RISCV,1978,Cond.push_back(MachineOperand::CreateImm(ThisCond[<NUM_LIT>].getImm()));
LLVM,RISCV,1979,"1. `else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ;`: This line checks if the `DestReg` and `SrcReg` registers are contained in the `STR_LIT` string. If"
LLVM,RISCV,1980,
LLVM,RISCV,1981,
LLVM,RISCV,1982,count++;
LLVM,RISCV,1983,
LLVM,RISCV,1984,
LLVM,RISCV,1985,
LLVM,RISCV,1986,
LLVM,RISCV,1987,FrameIndex = MI.getOperand(<NUM_LIT>).getIndex();
LLVM,RISCV,1988,if (MI.isStoreToStackSlot())
LLVM,RISCV,1989,
LLVM,RISCV,1990,"case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ;"
LLVM,RISCV,1991,Cond[<NUM_LIT>].setImm(getOppositeBranchOpcode(Cond[<NUM_LIT>].getImm()));
LLVM,RISCV,1992,
LLVM,RISCV,1993,"BuildMI(MBB, MBBI, DL, get(<STR_LIT>), DstReg).addImm(Hi20).setMIFlag(Flag);"
LLVM,RISCV,1994,TBB = ThisTarget->getMBB();
LLVM,RISCV,1995,
LLVM,RISCV,1996,
LLVM,RISCV,1997,"InstrInfo::InstrInfo(const Subtarget &Subtarget) : GenInstrInfo(<STR_LIT>, <STR_LIT>), Subtarget(Subtarget) {"
LLVM,RISCV,1998,"InstrInfo::InstrInfo(const Subtarget &Subtarget) : GenInstrInfo(<STR_LIT>, <STR_LIT>), Subtarget(Subtarget) {"
LLVM,RISCV,1999,
LLVM,RISCV,2000,
LLVM,RISCV,2001,case TargetOpcode :: INLINEASM :
LLVM,RISCV,2002,Here is a breakdown of the code
LLVM,RISCV,2003,"BuildMI(MBB, MBBI, DL, get(<STR_LIT>), DstReg)"
LLVM,RISCV,2004,
LLVM,RISCV,2005,
LLVM,RISCV,2006,"MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ;"
LLVM,RISCV,2007,
LLVM,RISCV,2008,return <NUM_LIT>;
LLVM,RISCV,2009,return MI.getOperand(<NUM_LIT>).getReg();
LLVM,RISCV,2010,MI.getOperand(<NUM_LIT>).getImm()
LLVM,RISCV,2011,
LLVM,RISCV,2012,"BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(<NUM_LIT>);"
LLVM,RISCV,2013,"BuildMI(MBB, MBBI, DL, get(<STR_LIT>), DstReg).addImm(Hi20).setMIFlag(Flag);"
LLVM,RISCV,2014,Target = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ;
LLVM,RISCV,2015,Cond.push_back(MachineOperand::CreateIm
LLVM,RISCV,2016,I = MBB.end()
LLVM,RISCV,2017,* BytesRemoved += getInstSizeInBytes( *I );
LLVM,RISCV,2018,Cond[<NUM_LIT>].setImm(getOppositeBranchOpcode(Cond[<NUM_LIT>].getImm()));
LLVM,RISCV,2019,
LLVM,RISCV,2020,
LLVM,RISCV,2021,
LLVM,RISCV,2022,
LLVM,RISCV,2023,Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LI
LLVM,RISCV,2024,TII = *STI.getInstrInfo();
LLVM,RISCV,2025,TII = *STI.getInstrInfo();
LLVM,RISCV,2026,InstructionSelector * selector = create<ISA_L
LLVM,RISCV,2027,
LLVM,RISCV,2028,"return ""John Doe"";"
LLVM,RISCV,2029,return DEBUG_TYPE;
LLVM,RISCV,2030,TII = *STI.getInstrInfo();
LLVM,RISCV,2031,TII = *STI.getInstrInfo();
LLVM,RISCV,2032,
LLVM,RISCV,2033,
LLVM,RISCV,2034,
LLVM,RISCV,2035,errs() << <STR_LIT>;
LLVM,RISCV,2036,unsigned Op1Code = Op1 -> getOpcode ( ) ;
LLVM,RISCV,2037,AM.Offset = TestOffset;
LLVM,RISCV,2038,"Offset = CurDAG->getTargetFrameIndex(FrameIndex, VT);"
LLVM,RISCV,2039,"return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(<NUM_LIT>));"
LLVM,RISCV,2040,"However, based on the syntax and structure of the code, it appears that the next statement will likely be a call to the `getTargetConstant` method of the `CurDAG` object, passing in the `Imm` and `SDLoc` objects as arguments, along with the result of the `getValue"
LLVM,RISCV,2041,
LLVM,RISCV,2042,Here is a breakdown of the code
LLVM,RISCV,2043,
LLVM,RISCV,2044,Based on the syntax
LLVM,RISCV,2045,
LLVM,RISCV,2046,
LLVM,RISCV,2047,Lowering = Subtarget->getTargetLowering();
LLVM,RISCV,2048,Lowering = Subtarget->getTargetLowering();
LLVM,RISCV,2049,return ret;
LLVM,RISCV,2050,DAG *dag = new DAG(MF);
LLVM,RISCV,2051,ResNode = SelectCode(Node);
LLVM,RISCV,2052,OutOps.push_back(Offset);
LLVM,RISCV,2053,if (isInt<NUM_LIT>(CN->getSExtValue())) {
LLVM,RISCV,2054,
LLVM,RISCV,2055,
LLVM,RISCV,2056,return true;
LLVM,RISCV,2057,Base = selectRegAddr(Addr);
LLVM,RISCV,2058,"SDValue Result = CurDAG->getNode(Opcode, DL, VT, Lower, Upper);"
LLVM,RISCV,2059,"SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), <STR_LIT>, XLenVT);"
LLVM,RISCV,2060,"ReplaceNode(Node, CurDAG->getMachineNode(<STR_LIT>, DL, VT, TFI, Imm));"
LLVM,RISCV,2061,return false;
LLVM,RISCV,2062,
LLVM,RISCV,2063,
LLVM,RISCV,2064,
LLVM,RISCV,2065,
LLVM,RISCV,2066,"LLVM_DEBUG(dbgs() << ""Found a load with a constant offset: "");"
LLVM,RISCV,2067,
LLVM,RISCV,2068,default :
LLVM,RISCV,2069,
LLVM,RISCV,2070,
LLVM,RISCV,2071,"Assuming that the `SDNode` class has a method called `getUsers()` that returns a list of all the users of the node, and that the `WUsers` class is a subclass of `SD"
LLVM,RISCV,2072,
LLVM,RISCV,2073,
LLVM,RISCV,2074,
LLVM,RISCV,2075,"SrcReg = SDValue ( Result , <NUM_LIT> ) ;"
LLVM,RISCV,2076,
LLVM,RISCV,2077,ShAmt = N.getOperand(<NUM_LIT>);
LLVM,RISCV,2078,"VL = CurDAG->getTargetConstant(<STR_LIT>, SDLoc(N), N->getValueType(<NUM_LIT>));"
LLVM,RISCV,2079,
LLVM,RISCV,2080,"const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ;"
LLVM,RISCV,2081,"Based on the context and patterns in the code, it is likely that the next statement will"
LLVM,RISCV,2082,return false;
LLVM,RISCV,2083,"SplatVal = DAG.getTargetConstant(SplatImm, SDLoc(N), XLenVT);"
LLVM,RISCV,2084,"SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), Subtarget->getXLenVT());"
LLVM,RISCV,2085,"SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), Subtarget->getXLenVT());"
LLVM,RISCV,2086,"CurDAG->setNodeMemRefs(Store, {MemOp->getMemOperand()});"
LLVM,RISCV,2087,Operands
LLVM,RISCV,2088,
LLVM,RISCV,2089,"Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);"
LLVM,RISCV,2090,
LLVM,RISCV,2091,
LLVM,RISCV,2092,"CurDAG->setNodeMemRefs(Load, {MemOp->getMemOperand()});"
LLVM,RISCV,2093,
LLVM,RISCV,2094,
LLVM,RISCV,2095,"MachineSDNode * Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(<NUM_LIT>), Operands);"
LLVM,RISCV,2096,IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ;
LLVM,RISCV,2097,
LLVM,RISCV,2098,if (IsTA) { uint64_t TSFlags = TII->get(I->UnmaskedPseudo).TSFlags; }
LLVM,RISCV,2099,
LLVM,RISCV,2100,return true;
LLVM,RISCV,2101,"return llvm::all_of(Values, [](SDValue V) { return V->isUndef(); });"
LLVM,RISCV,2102,
LLVM,RISCV,2103,"MachineSDNode * Load = CurDAG->getMachineNode(P->Pseudo, DL, <STR_LIT>, <STR_LIT>, <STR_LIT>, Operands);"
LLVM,RISCV,2104,
LLVM,RISCV,2105,
LLVM,RISCV,2106,
LLVM,RISCV,2107,assert(isa<ConstantSDNode>(N->getOperand(<NUM_LIT>)));
LLVM,RISCV,2108,"Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);"
LLVM,RISCV,2109,"Result = CurDAG->getNode(SrcReg, SDImm);"
LLVM,RISCV,2110,
LLVM,RISCV,2111,
LLVM,RISCV,2112,"const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , false , true , ScalarSize , static_cast < unsigned > ( LMUL ) ) ;"
LLVM,RISCV,2113,
LLVM,RISCV,2114,
LLVM,RISCV,2115,
LLVM,RISCV,2116,"CurDAG->setNodeMemRefs(Store, {MemOp->getMemOperand()});"
LLVM,RISCV,2117,
LLVM,RISCV,2118,
LLVM,RISCV,2119,Val = N;
LLVM,RISCV,2120,Val = N;
LLVM,RISCV,2121,"LLVM_DEBUG(dbgs() << ""New base: "");"
LLVM,RISCV,2122,LLVM_DEBUG(dbgs() << <STR_LIT>);
LLVM,RISCV,2123,return false;
LLVM,RISCV,2124,
LLVM,RISCV,2125,"case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; }"
LLVM,RISCV,2126,case <STR_LIT> :
LLVM,RISCV,2127,"Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);"
LLVM,RISCV,2128,"Result = CurDAG->getMachineNode(Inst.Opc, DL, XLenVT, SrcReg, SDImm);"
LLVM,RISCV,2129,case <STR_LIT> : {
LLVM,RISCV,2130,RS1 = Shl.getOperand(<NUM_LIT>);
LLVM,RISCV,2131,RS1 = Shl.getOperand(<NUM_LIT>);
LLVM,RISCV,2132,return true;
LLVM,RISCV,2133,
LLVM,RISCV,2134,
LLVM,RISCV,2135,
LLVM,RISCV,2136,"SrcReg = SDValue(Result, <NUM_LIT>);"
LLVM,RISCV,2137,
LLVM,RISCV,2138,return true;
LLVM,RISCV,2139,if (N.getOpcode() == <STR_LIT> && Subtarget->getXLenVT() == <STR_LIT> && cast<VTSDNode>(N.getOperand(<NUM_LIT>))->getVT() == <STR_LIT>) {
LLVM,RISCV,2140,if ( isa < ConstantSDNode > ( Srl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Shl . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNod
LLVM,RISCV,2141,Here are a few possibilities:
LLVM,RISCV,2142,RS1 = Srl . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2143,if (auto *GA = dyn_cast<GlobalAddressSDNode>(ImmOperand)) {
LLVM,RISCV,2144,doPeepholeLoadStoreOffset();
LLVM,RISCV,2145,Some possible next statements could include:
LLVM,RISCV,2146,
LLVM,RISCV,2147,
LLVM,RISCV,2148,"Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT());"
LLVM,RISCV,2149,
LLVM,RISCV,2150,"Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), Subtarget->getXLenVT());"
LLVM,RISCV,2151,Base = Addr;
LLVM,RISCV,2152,
LLVM,RISCV,2153,
LLVM,RISCV,2154,case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ;
LLVM,RISCV,2155,return true;
LLVM,RISCV,2156,
LLVM,RISCV,2157,
LLVM,RISCV,2158,"case <STR_LIT> : Alternatively, it's possible that the next statement could be the default label, which would be indicated by the keyword ""default"""
LLVM,RISCV,2159,"return createM4Tuple ( CurDAG , Regs , NF ) ;"
LLVM,RISCV,2160,"LLVM_DEBUG(dbgs() << ""New base: ""); LLVM_DEBUG(Base->dump(CurDAG)); LLVM_DEBUG(dbgs() << ""New offset: ""); LLVM_DEBUG(N->dump(CurDAG));"
LLVM,RISCV,2161,
LLVM,RISCV,2162,
LLVM,RISCV,2163,return <STR_LIT> + Index ;
LLVM,RISCV,2164,Shl = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2165,uint32_t VC2 = Srl.getConstantOperandVal(<NUM_LIT>);
LLVM,RISCV,2166,assert(isa<ConstantSDNode>(N->getOperand(<NUM_LIT>)));
LLVM,RISCV,2167,
LLVM,RISCV,2168,
LLVM,RISCV,2169,"SDValue Mask = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);"
LLVM,RISCV,2170,
LLVM,RISCV,2171,"SDValue SuperReg = SDValue(Load, <NUM_LIT>);"
LLVM,RISCV,2172,
LLVM,RISCV,2173,
LLVM,RISCV,2174,
LLVM,RISCV,2175,
LLVM,RISCV,2176,SplatVal = N.getOperand(0);
LLVM,RISCV,2177,"SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits());"
LLVM,RISCV,2178,if (SplatImm != <constant value>)
LLVM,RISCV,2179,if (SplatImm != <constant value>)
LLVM,RISCV,2180,
LLVM,RISCV,2181,Operands.push_back(Node->getOperand(<NUM_LIT> + NF));
LLVM,RISCV,2182,Operands.push_back(SEW);
LLVM,RISCV,2183,
LLVM,RISCV,2184,"SDValue Store = CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(<NUM_LIT>), Operands);"
LLVM,RISCV,2185,"Store->setOperand(<NUM_LIT> + NF, Node->getOperand(<NUM_LIT> + NF));"
LLVM,RISCV,2186,
LLVM,RISCV,2187,"Next, the function switches on the machine opcode of the `User` node, which is obtained by calling the `getMachineOpcode()` method"
LLVM,RISCV,2188,"for (auto UI = Node->use_begin(), UE = Node->use_end(); UI != UE; ++UI) {"
LLVM,RISCV,2189,"ImmOperand = CurDAG->getTargetConstant(Const->getSExtValue(), SDLoc(ImmOperand), ImmOperand.getValueType());"
LLVM,RISCV,2190,"SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), <STR_LIT>, XLenVT);"
LLVM,RISCV,2191,
LLVM,RISCV,2192,"LLVM_DEBUG(dbgs() << ""Found a floating-point constant: "" << F64Val.getMachineOpcode());"
LLVM,RISCV,2193,
LLVM,RISCV,2194,doPeepholeLoadStoreADDI();
LLVM,RISCV,2195,"SDValue Imm = CurDAG->getTargetConstant(<NUM_LIT>, DL, XLenVT);"
LLVM,RISCV,2196,EVT VT = Node->getValueType(<NUM_LIT>);
LLVM,RISCV,2197,case <STR_LIT> : if ( Bits < <NUM_LIT> ) return false ; break ;
LLVM,RISCV,2198,
LLVM,RISCV,2199,return VL;
LLVM,RISCV,2200,"ReplaceNode(Node, CurDAG->getMachineNode(<STR_LIT>, DL, VT, TFI, Imm));"
LLVM,RISCV,2201,"ReplaceNode(Node, CurDAG->getMachineNode(<STR_LIT>, DL, VT, TFI, Imm));"
LLVM,RISCV,2202,VL = N;
LLVM,RISCV,2203,VL = N;
LLVM,RISCV,2204,if (Vec1->getOpcode() == <STR_LIT>) {
LLVM,RISCV,2205,
LLVM,RISCV,2206,1. `Dest = SRC1 + SRC2;`
LLVM,RISCV,2207,"SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);"
LLVM,RISCV,2208,
LLVM,RISCV,2209,
LLVM,RISCV,2210,if (VT == XLenVT && ConstNode->isNullValue()) {
LLVM,RISCV,2211,case <STR_LIT>:
LLVM,RISCV,2212,
LLVM,RISCV,2213,assert(isa<ConstantSDNode>(N->getOperand(<NUM_LIT>)));
LLVM,RISCV,2214,case <STR_LIT> : { LoadSDNode * Load = cast < LoadSDNode > ( Node ) ; if ( Load -> getAddressingMode ( ) != <STR_LIT> ) break ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Base = Node -> getOperand ( <NUM_LIT> ) ; SDValue Offset = Node -> getOperand ( <NUM_LIT> ) ; bool simm12 = false ; bool signExtend = Loa
LLVM,RISCV,2215,
LLVM,RISCV,2216,RS1 = Shl.getOperand(<NUM_LIT>);
LLVM,RISCV,2217,
LLVM,RISCV,2218,
LLVM,RISCV,2219,"DAGToDAGISel::DAGToDAGISel(TargetMachine &TargetMachine, CodeGenOpt::Level OptLevel) : SelectionDAGISel(TargetMachine, OptLevel) {"
LLVM,RISCV,2220,"DAGToDAGISel::DAGToDAGISel(TargetMachine &TargetMachine, CodeGenOpt::Level OptLevel) : SelectionDAGISel(TargetMachine, OptLevel) {"
LLVM,RISCV,2221,"case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm ="
LLVM,RISCV,2222,Operands.push_back(Chain);
LLVM,RISCV,2223,"static const unsigned RegClassIDs[] = { ""str_lit"", ""str_lit"", ""str_lit"", ""str_lit"", ""str_lit"", ""str_lit"", ""str_lit"" };"
LLVM,RISCV,2224,The
LLVM,RISCV,2225,
LLVM,RISCV,2226,"return createTupleImpl(CurDAG, Regs, RegClassIDs[NF - <NUM_LIT>], <STR_LIT>);"
LLVM,RISCV,2227,
LLVM,RISCV,2228,
LLVM,RISCV,2229,
LLVM,RISCV,2230,
LLVM,RISCV,2231,
LLVM,RISCV,2232,
LLVM,RISCV,2233,"ReplaceUses(N, N0.getNode());"
LLVM,RISCV,2234,
LLVM,RISCV,2235,
LLVM,RISCV,2236,
LLVM,RISCV,2237,
LLVM,RISCV,2238,
LLVM,RISCV,2239,
LLVM,RISCV,2240,Some possible next statements could be:
LLVM,RISCV,2241,Base = FIN->getBasePtr();
LLVM,RISCV,2242,
LLVM,RISCV,2243,"SrcReg = SDValue(Result, <NUM_LIT>);"
LLVM,RISCV,2244,
LLVM,RISCV,2245,"C->setOperand(0, ConstantInt::get(C->getContext(), 0));"
LLVM,RISCV,2246,Val = N;
LLVM,RISCV,2247,if (AndMask.getBitWidth() == ShiftWidth) {
LLVM,RISCV,2248,
LLVM,RISCV,2249,"MachineSDNode * Load = CurDAG->getMachineNode(P->Pseudo, DL, <STR_LIT>, <STR_LIT>, Operands);"
LLVM,RISCV,2250,"MachineSDNode * Load = CurDAG->getMachineNode(P->Pseudo, DL, <STR_LIT>, <STR_LIT>, Operands);"
LLVM,RISCV,2251,
LLVM,RISCV,2252,
LLVM,RISCV,2253,SplatVal = N . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2254,B
LLVM,RISCV,2255,"return selectVSplatSimmHelper(N, SplatVal, *CurDAG, *Subtarget, [](int64_t Imm) { return isInt<NUM_LIT>(Imm); });"
LLVM,RISCV,2256,
LLVM,RISCV,2257,
LLVM,RISCV,2258,return Imm != <NUM_LIT> && ( ( isInt < <NUM_LIT> > ( Imm ) && Imm != - <NUM_LIT> ) || Imm == <NUM_LIT> ) ; }
LLVM,RISCV,2259,
LLVM,RISCV,2260,MVT EltVT = N.getSimpleValueType().getVectorElementType();
LLVM,RISCV,2261,"SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits());"
LLVM,RISCV,2262,if (SplatImm == 0) return false;
LLVM,RISCV,2263,
LLVM,RISCV,2264,
LLVM,RISCV,2265,
LLVM,RISCV,2266,return VT;
LLVM,RISCV,2267,
LLVM,RISCV,2268,
LLVM,RISCV,2269,"RVLocs.resize(Outs.size(), CCValAssign());"
LLVM,RISCV,2270,"CCState CCInfo(CallConv, IsVar"
LLVM,RISCV,2271,
LLVM,RISCV,2272,"Value = DAG.getNode(<STR_LIT>, DL, VA.getLocVT(), Value, DAG.getValueType(VA.getValVT()));"
LLVM,RISCV,2273,"case CCValAssign::ZExt: return DAG.getNode(<STR_LIT>, DL, VA.getLocVT(), Value);"
LLVM,RISCV,2274,"MachineInstrBuilder jumpMI = BuildMI( *BB, MI, DL, TII->get(jump), RA );"
LLVM,RISCV,2275,
LLVM,RISCV,2276,
LLVM,RISCV,2277,
LLVM,RISCV,2278,case 'U' : case 'V' : case 'W' : case 'X' : case 'Y' : case 'Z' : return C_Other;
LLVM,RISCV,2279,return <STR_LIT>;
LLVM,RISCV,2280,return <STR_LIT>;
LLVM,RISCV,2281,
LLVM,RISCV,2282,"if (Subtarget.isRV64()) return std::make_pair(<NUM_LIT>, &<STR_LIT>);"
LLVM,RISCV,2283,
LLVM,RISCV,2284,
LLVM,RISCV,2285,
LLVM,RISCV,2286,"TargetLoweringObjectFileELF::Initialize(Ctx, TM);"
LLVM,RISCV,2287,"bool TargetLowering::isFPImmLegal(const APFloat& Imm, EVT VT) const {"
LLVM,RISCV,2288,return false;
LLVM,RISCV,2289,"Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), Op.getValueType()));"
LLVM,RISCV,2290,Here's a
LLVM,RISCV,2291,Here are a few possibilities:
LLVM,RISCV,2292,return Result;
LLVM,RISCV,2293,return Result;
LLVM,RISCV,2294,"unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);"
LLVM,RISCV,2295,
LLVM,RISCV,2296,"return getAddrPIC(Op, DAG);"
LLVM,RISCV,2297,
LLVM,RISCV,2298,
LLVM,RISCV,2299,
LLVM,RISCV,2300,
LLVM,RISCV,2301,
LLVM,RISCV,2302,
LLVM,RISCV,2303,
LLVM,RISCV,2304,
LLVM,RISCV,2305,
LLVM,RISCV,2306,
LLVM,RISCV,2307,unsigned sp = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,2308,MF.getInfo<ISA_LIT>FunctionInfo>()->setManipulatesSP(true);
LLVM,RISCV,2309,"return DAG . getCopyFromReg ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , sp , Op . getValueType ( ) ) ;"
LLVM,RISCV,2310,
LLVM,RISCV,2311,Here are a few possibilities:
LLVM,RISCV,2312,"However, based on the syntax and the names of the variables, it appears that the next statement is likely to be a call to the `getFrameIndex` method of the `FuncInfo` object, passing in the result of the `getVarArgsFrameIndex` method as an argument. The `"
LLVM,RISCV,2313,ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ;
LLVM,RISCV,2314,
LLVM,RISCV,2315,MVT ArgVT = Outs[i].VT;
LLVM,RISCV,2316,
LLVM,RISCV,2317,
LLVM,RISCV,2318,
LLVM,RISCV,2319,int Offset = - ( XLenInBytes * <NUM_LIT> );
LLVM,RISCV,2320,"FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FrameReg, VT);"
LLVM,RISCV,2321,
LLVM,RISCV,2322,
LLVM,RISCV,2323,"case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ;"
LLVM,RISCV,2324,
LLVM,RISCV,2325,"unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));"
LLVM,RISCV,2326,"Val = DAG.getNode(<STR_LIT>, DL, LocVT, Val);"
LLVM,RISCV,2327,"Val = DAG.getNode(<STR_LIT>, DL, LocVT, Val);"
LLVM,RISCV,2328,"setOperationAction(<STR_LIT>, <STR_LIT>, Legal);"
LLVM,RISCV,2329,
LLVM,RISCV,2330,"Val = RegInfo.createVirtualRegister(LocVT, ValVT);"
LLVM,RISCV,2331,ArgTy = FType->getParamType(Ins[i].getOrigArgIndex());
LLVM,RISCV,2332,
LLVM,RISCV,2333,
LLVM,RISCV,2334,
LLVM,RISCV,2335,if (LocVT == <STR_LIT> || LocVT == <STR_LIT>) {
LLVM,RISCV,2336,if (LocVT == <STR_LIT> || LocVT == <STR_LIT>) {
LLVM,RISCV,2337,
LLVM,RISCV,2338,
LLVM,RISCV,2339,
LLVM,RISCV,2340,Some possible next statements could be:
LLVM,RISCV,2341,Some possible next statements could be:
LLVM,RISCV,2342,
LLVM,RISCV,2343,"However, based on the structure of the code, it appears that the next statement will be one of the following:"
LLVM,RISCV,2344,"BuildMI(TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(), TII.get(<STR_LIT>), SelectMBBI->getOperand(<NUM_LIT>).getReg())"
LLVM,RISCV,2345,SelectDebugValues . push_back ( & * SequenceMBBI ) ;
LLVM,RISCV,2346,
LLVM,RISCV,2347,case 'A' :
LLVM,RISCV,2348,
LLVM,RISCV,2349,Here are a few possibilities for what the next statement could be:
LLVM,RISCV,2350,
LLVM,RISCV,2351,
LLVM,RISCV,2352,
LLVM,RISCV,2353,
LLVM,RISCV,2354,Info.memVT = <STR_LIT> (PtrTy->getElementType());
LLVM,RISCV,2355,return ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtD ( ) ) ;
LLVM,RISCV,2356,
LLVM,RISCV,2357,
LLVM,RISCV,2358,"MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true)"
LLVM,RISCV,2359,"Addr = getStaticTLSAddr(N, DAG, true);"
LLVM,RISCV,2360,"RetOps.push_back(DAG.getRegister(RegHi, <STR_LIT>));"
LLVM,RISCV,2361,RetOpc = <STR_LIT>;
LLVM,RISCV,2362,
LLVM,RISCV,2363,"Val = DAG.getNode(FIN, PtrVT);"
LLVM,RISCV,2364,RC = & <STR_LIT>;
LLVM,RISCV,2365,"After that, it is creating a copy of the value of the"
LLVM,RISCV,2366,
LLVM,RISCV,2367,F.getContext().diagnose(DiagnosticInfoUnsupported{...});
LLVM,RISCV,2368,"State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));"
LLVM,RISCV,2369,
LLVM,RISCV,2370,
LLVM,RISCV,2371,InVals.push_back(ArgValue);
LLVM,RISCV,2372,
LLVM,RISCV,2373,
LLVM,RISCV,2374,
LLVM,RISCV,2375,
LLVM,RISCV,2376,
LLVM,RISCV,2377,
LLVM,RISCV,2378,
LLVM,RISCV,2379,
LLVM,RISCV,2380,
LLVM,RISCV,2381,if (VT == <STR_LIT> && !Subtarget.hasStdExtF()) return false;
LLVM,RISCV,2382,
LLVM,RISCV,2383,
LLVM,RISCV,2384,"SDValue NewOp0 = DAG.getNode(<STR_LIT>, DL, <STR_LIT>, Op0);"
LLVM,RISCV,2385,"Results.push_back(DAG.getNode(<STR_LIT>, DL, <STR_LIT>, FPConv));"
LLVM,RISCV,2386,if (IsCallerStructRet || IsCalleeStructRet) return false;
LLVM,RISCV,2387,"const uint32_t * CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);"
LLVM,RISCV,2388,"return DAG.getNode(<STR_LIT>, DL, Ty, Addr, DAG.getConstant(Offset, DL, XLenVT));"
LLVM,RISCV,2389,"setOperationAction(<STR_LIT>, XLenVT, Custom);"
LLVM,RISCV,2390,"if (ValVT == <STR_LIT> && !UseGPRForF32) Reg = State.AllocateReg(ArgFPR32s, ArgFPR64s);"
LLVM,RISCV,2391,
LLVM,RISCV,2392,SelectMBBI = Next;
LLVM,RISCV,2393,"int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ;"
LLVM,RISCV,2394,
LLVM,RISCV,2395,
LLVM,RISCV,2396,
LLVM,RISCV,2397,
LLVM,RISCV,2398,unsigned VReg = RegInfo . createVirtualRegister ( RC ) ;
LLVM,RISCV,2399,State.addLoc(It);
LLVM,RISCV,2400,unsigned Reg = State . AllocateReg ( ArgGPRs ) ;
LLVM,RISCV,2401,
LLVM,RISCV,2402,
LLVM,RISCV,2403,
LLVM,RISCV,2404,SDValue Glue;
LLVM,RISCV,2405,"InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo()));"
LLVM,RISCV,2406,
LLVM,RISCV,2407,Flag = DAG.getMachineFunction()->getReturn().getReturnValue();`
LLVM,RISCV,2408,"setOperationAction(<STR_LIT>, <STR_LIT>, Expand)"
LLVM,RISCV,2409,
LLVM,RISCV,2410,for (unsigned i = 0; i < NumArgs; ++i) {
LLVM,RISCV,2411,
LLVM,RISCV,2412,
LLVM,RISCV,2413,"for (unsigned i = <NUM_LIT>, e = Outs.size(); i != e; ++i) {"
LLVM,RISCV,2414,
LLVM,RISCV,2415,if ( ValVT . isScalarInteger ( ) && ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) ) {
LLVM,RISCV,2416,switch (CC) {
LLVM,RISCV,2417,"return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ;"
LLVM,RISCV,2418,"return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ;"
LLVM,RISCV,2419,"return EVT::getVectorVT(Context, <STR_LIT>, VT.getVectorElementCount());"
LLVM,RISCV,2420,
LLVM,RISCV,2421,
LLVM,RISCV,2422,"Next, the function checks if"
LLVM,RISCV,2423,if (ScalarTy->isIntegerTy(<NUM_LIT>)) return Subtarget.hasVInstructionsI64();
LLVM,RISCV,2424,
LLVM,RISCV,2425,"SDValue Bitcast = DAG . getBitcast ( IntVT , FloatVal ) ;"
LLVM,RISCV,2426,
LLVM,RISCV,2427,
LLVM,RISCV,2428,
LLVM,RISCV,2429,
LLVM,RISCV,2430,
LLVM,RISCV,2431,if (VT.isScalarInteger() && VT != XLenVT) {
LLVM,RISCV,2432,Ops.push_back(&Op->getOperandUse(<NUM_LIT>));
LLVM,RISCV,2433,
LLVM,RISCV,2434,if (LMul > Subtarget.getMaxVLForFixedLengthVectors()) return false;
LLVM,RISCV,2435,if (EltVT.getSizeInBits() > Subtarget.getMaxELENForFixedLengthVectors()) return false;
LLVM,RISCV,2436,
LLVM,RISCV,2437,
LLVM,RISCV,2438,FirstMaskArgument = preAssignMask(Ins);
LLVM,RISCV,2439,
LLVM,RISCV,2440,
LLVM,RISCV,2441,FirstMaskArgument = preAssignMask(Outs);
LLVM,RISCV,2442,"CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);"
LLVM,RISCV,2443,"State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;"
LLVM,RISCV,2444,"State.addLoc(CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));"
LLVM,RISCV,2445,if (LocVT == <STR_LIT>)
LLVM,RISCV,2446,"State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));"
LLVM,RISCV,2447,if (LocVT == <STR_LIT>) {
LLVM,RISCV,2448,SDLoc DL(N);
LLVM,RISCV,2449,
LLVM,RISCV,2450,Op1 = Op1 . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2451,Op0 = Op0.getOperand(<NUM_LIT>);
LLVM,RISCV,2452,
LLVM,RISCV,2453,Value *LHSVal = LHS->getOperand(0);
LLVM,RISCV,2454,NonConstantVal = FalseVal;
LLVM,RISCV,2455,
LLVM,RISCV,2456,"SDValue Result = combineSelectAndUse(N, N0"
LLVM,RISCV,2457,
LLVM,RISCV,2458,
LLVM,RISCV,2459,
LLVM,RISCV,2460,return Subtarget . getXLen ( ) - Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) + <NUM_LIT> ;
LLVM,RISCV,2461,assert(VT.isFixedLengthVector() && <STR_LIT>);
LLVM,RISCV,2462,case CCValAssign :: BCvt:
LLVM,RISCV,2463,
LLVM,RISCV,2464,bool convertSelectOfConstantsToMath ( EVT VT ) const override {
LLVM,RISCV,2465,
LLVM,RISCV,2466,assert(VT.isScalableVector() && <STR_LIT>);
LLVM,RISCV,2467,"Val = convertToBCvtVector(LocVT, Val, DAG, Subtarget);"
LLVM,RISCV,2468,
LLVM,RISCV,2469,"SDValue NewRes = DAG.getNode(WOpcode, DL, <STR_LIT>, NewOp"
LLVM,RISCV,2470,
LLVM,RISCV,2471,"SDValue NewWOp = DAG.getNode(N->getOpcode(), DL, <STR_LIT"
LLVM,RISCV,2472,if (Subtarget.hasStdExtM() && VT.getSizeInBits() >= Subtarget.getXLen()) return false;
LLVM,RISCV,2473,if (Subtarget.hasStdExtZba() && !Imm.isSignedIntN(NUM_LIT) && ((Imm - NUM_LIT).isPowerOf2() || (Imm - NUM_LIT).isPowerOf2() || (Imm - NUM_LIT).isPowerOf2())) return true;
LLVM,RISCV,2474,SubRegIdx = 0;
LLVM,RISCV,2475,
LLVM,RISCV,2476,
LLVM,RISCV,2477,
LLVM,RISCV,2478,"* `Type * Tys [ ] = { AlignedAddr -> getType ( ) } ;` declares an array of `Type` objects, where each element is the result of calling the `getType"
LLVM,RISCV,2479,"Value * MaskedCmpXchg = Builder.CreateCall(MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});"
LLVM,RISCV,2480,
LLVM,RISCV,2481,LoopMBB->addSuccessor(DoneMBB);
LLVM,RISCV,2482,HeadMBB->addSuccessor(IfFalseMBB);
LLVM,RISCV,2483,
LLVM,RISCV,2484,
LLVM,RISCV,2485,
LLVM,RISCV,2486,
LLVM,RISCV,2487,"return DAG . getMergeValues ( { DAG . getBitcast ( VT , L ) , L . getValue ( <NUM_LIT> ) } , DL ) ;"
LLVM,RISCV,2488,
LLVM,RISCV,2489,"StoredVal = DAG.getBitcast(NewVT, StoredVal);"
LLVM,RISCV,2490,
LLVM,RISCV,2491,return TargetLowering :: getConstraintType ( Constraint ) ;
LLVM,RISCV,2492,
LLVM,RISCV,2493,"return getDefaultVLOps(VecVT, VecVT, DL, DAG, Subtarget);"
LLVM,RISCV,2494,MVT XLenVT = Subtarget . getXLenVT ( ) ;
LLVM,RISCV,2495,CLI = TargetLowering::CallLoweringInfo(DAG);
LLVM,RISCV,2496,"However, based on the names of the methods and the types of the variables, it is likely that the next statement will be a call to a method that creates a new node in the directed acyclic graph (DAG) representing the program. The `getTargetGlobalAddress` method is likely to return a pointer to a global variable"
LLVM,RISCV,2497,
LLVM,RISCV,2498,"However, based on the name of the method and the parameters it takes, it is likely that the next statement will be a return statement that returns a register number or a pointer to a register that is used to store the exception pointer. The `ISA_LIT` constant is likely to be a constant that represents the instruction set architecture (ISA)"
LLVM,RISCV,2499,"However, based on the name of the method and the parameters it takes, it is likely that the method is responsible for retrieving a register that is used to store the exception selector for the personality function specified by the `PersonalityFn` parameter. The `Constant` class is likely used to represent a constant value that is used as an argument to the `"
LLVM,RISCV,2500,
LLVM,RISCV,2501,
LLVM,RISCV,2502,
LLVM,RISCV,2503,
LLVM,RISCV,2504,case <NUM_LIT> : return <STR_LIT> :: LMUL_8;
LLVM,RISCV,2505,assert ( VT . getVectorElementType ( ) . getSizeInBits ( ) <= <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,2506,switch (CC) {
LLVM,RISCV,2507,
LLVM,RISCV,2508,
LLVM,RISCV,2509,return <STR_LIT>;
LLVM,RISCV,2510,Reg = MatchRegisterName(RegName);
LLVM,RISCV,2511,
LLVM,RISCV,2512,"return getRegisterTypeForCallingConv(Context, CC, VT);"
LLVM,RISCV,2513,return <STR_LIT>;
LLVM,RISCV,2514,"Mask = DAG.getMaskForRVV(VT, ContainerVT, DL, Subtarget);"
LLVM,RISCV,2515,
LLVM,RISCV,2516,"return getPointerTy(DL, VT.getVectorElementType());"
LLVM,RISCV,2517,Here are a few possible next statements:
LLVM,RISCV,2518,
LLVM,RISCV,2519,
LLVM,RISCV,2520,
LLVM,RISCV,2521,Info.opc = <STR_LIT>;
LLVM,RISCV,2522,
LLVM,RISCV,2523,return ( VT == <STR_LIT> && Subtarget . hasStdExtZfh ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) ) || ( VT == <STR_LIT> && Subtarget . hasStdExtD ( ) ) ;
LLVM,RISCV,2524,
LLVM,RISCV,2525,
LLVM,RISCV,2526,Some possible next statements could include:
LLVM,RISCV,2527,
LLVM,RISCV,2528,return true;
LLVM,RISCV,2529,if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
LLVM,RISCV,2530,"const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ;"
LLVM,RISCV,2531,
LLVM,RISCV,2532,return false;
LLVM,RISCV,2533,
LLVM,RISCV,2534,if (C1.isSignedIntN(<NUM_LIT>) && !(C1 * C2).isSignedIntN(<NUM_LIT>)) return false;
LLVM,RISCV,2535,
LLVM,RISCV,2536,return false;
LLVM,RISCV,2537,if ( SeqStepNum && SeqStepDenom ) {
LLVM,RISCV,2538,"Val = DAG.getNode(<STR_LIT>, DL, <STR_LIT>, Val, DAG.getConstant(<NUM_LIT>, DL, Subtarget.getXLenVT()));"
LLVM,RISCV,2539,
LLVM,RISCV,2540,"SDValue NegX = DAG.getNode(<STR_LIT>, DL, ContainerVT, SplatZero, X, Mask, VL);"
LLVM,RISCV,2541,BlockAddress * BA = N->getBlockAddress();
LLVM,RISCV,2542,BlockAddress * BA = N->getBlockAddress();
LLVM,RISCV,2543,ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
LLVM,RISCV,2544,"SDValue SlidedownAmt = DAG.getConstant(RemIdx, DL, XLenVT);"
LLVM,RISCV,2545,"Vec = DAG.getNode(<STR_LIT>, DL, WideVT, Vec);"
LLVM,RISCV,2546,
LLVM,RISCV,2547,"SDValue Op2 = convertToScalableVector(ContainerVT, Op.getOperand(<NUM_LIT>), DAG, Subtarget);"
LLVM,RISCV,2548,"Mag = convertToScalableVector(ContainerVT, Mag, DAG, Subtarget);"
LLVM,RISCV,2549,return Result;
LLVM,RISCV,2550,
LLVM,RISCV,2551,
LLVM,RISCV,2552,"SDValue Op1 = convertToScalableVector(ContainerVT, Op.getOperand(<NUM_"
LLVM,RISCV,2553,
LLVM,RISCV,2554,case ISD::SHL: Opc = ISD::SHL_RVV; break;
LLVM,RISCV,2555,
LLVM,RISCV,2556,"SDValue NewValue = convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);"
LLVM,RISCV,2557,"InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo()));"
LLVM,RISCV,2558,"SDValue ScalarSplat = DAG.getSplatVector(M1VT, DL, ScalarVal);"
LLVM,RISCV,2559,
LLVM,RISCV,2560,
LLVM,RISCV,2561,
LLVM,RISCV,2562,{
LLVM,RISCV,2563,"return DAG.getNode(<STR_LIT>, DL, Ty, Addr, DAG.getConstant(Offset, DL, XLenVT));"
LLVM,RISCV,2564,"Vec = DAG.getNode(Opc, DL, ContainerVT, Vec, Val, VL);"
LLVM,RISCV,2565,
LLVM,RISCV,2566,
LLVM,RISCV,2567,
LLVM,RISCV,2568,
LLVM,RISCV,2569,
LLVM,RISCV,2570,
LLVM,RISCV,2571,"Ops.push_back(DAG.getTargetConstant(IntID, DL, XLenVT));"
LLVM,RISCV,2572,
LLVM,RISCV,2573,"assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() && ""Vector element count mismatch"");"
LLVM,RISCV,2574,"Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);"
LLVM,RISCV,2575,Ops.push_back(VL);
LLVM,RISCV,2576,
LLVM,RISCV,2577,
LLVM,RISCV,2578,MFI.setReturnAddressIsTaken(true);
LLVM,RISCV,2579,"return DAG . getNode ( <STR_LIT> , DL , VT , Scalar , VL ) ;"
LLVM,RISCV,2580,"if (TrueVal - FalseVal == 0) return DAG.getNode(<STR_LIT>, DL, Op.getValueType(), CondV, FalseV);"
LLVM,RISCV,2581,
LLVM,RISCV,2582,
LLVM,RISCV,2583,"RMValue = DAG.getNode(<STR_LIT>, DL, XLenVT, Shifted, DAG.getConstant(<NUM_LIT>, DL, XLenVT));"
LLVM,RISCV,2584,"Hi = DAG.getNode(<STR_LIT>, DL, VT, CC, HiTrue, Zero);"
LLVM,RISCV,2585,
LLVM,RISCV,2586,SDValue Lo = Op . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2587,"SDValue Parts[2] = {Lo, Hi};"
LLVM,RISCV,2588,"However, based on the names of the variables and the functions being called, it is likely that the next statement will be related to the creation of a vector mask or a vector of values. The `getDefaultVLOps` function is likely to return a pair of values, with the first value being a mask and the"
LLVM,RISCV,2589,"return DAG . getNode ( <STR_LIT> , DL , VecVT , Lo , Hi , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ;"
LLVM,RISCV,2590,
LLVM,RISCV,2591,"SDValue ScalableRes = DAG.getNode(NewOpc, DL, ContainerVT, Ops);"
LLVM,RISCV,2592,
LLVM,RISCV,2593,
LLVM,RISCV,2594,MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
LLVM,RISCV,2595,"return DAG.getNode(<STR_LIT>, DL, VT, VL);"
LLVM,RISCV,2596,"SDValue VL = getDefaultScalableVLOps(VT, DL, DAG, Subtarget).second;"
LLVM,RISCV,2597,"SDValue SplatZero = DAG.getConstant(<NUM_LIT>, DL, Subtarget.getXLenVT());"
LLVM,RISCV,2598,"SDValue Trunc = DAG . getNode ( <STR_LIT> , DL , VecVT , Src , SplatOne ) ;"
LLVM,RISCV,2599,
LLVM,RISCV,2600,
LLVM,RISCV,2601,MVT ContainerVT = getContainerForFixedLengthVector(VT);
LLVM,RISCV,2602,MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
LLVM,RISCV,2603,
LLVM,RISCV,2604,if (Src.getOpcode() == <STR_LIT> && isa<ConstantSDNode>(Src.getOperand(<NUM_LIT>))) {
LLVM,RISCV,2605,if (ShAmt >= Width || !isPowerOf2_64(ShAmt)) return None;
LLVM,RISCV,2606,
LLVM,RISCV,2607,
LLVM,RISCV,2608,return isTailCall();
LLVM,RISCV,2609,
LLVM,RISCV,2610,
LLVM,RISCV,2611,
LLVM,RISCV,2612,
LLVM,RISCV,2613,
LLVM,RISCV,2614,if (SetCCs.empty()) return SDValue();`
LLVM,RISCV,2615,return GREV;
LLVM,RISCV,2616,
LLVM,RISCV,2617,SDValue N0 = N -> getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2618,
LLVM,RISCV,2619,return N->getValue() ^ DAG->getValue();
LLVM,RISCV,2620,return ArgIdx.index();
LLVM,RISCV,2621,ArgIdx.index()
LLVM,RISCV,2622,
LLVM,RISCV,2623,return false;
LLVM,RISCV,2624,return false;
LLVM,RISCV,2625,
LLVM,RISCV,2626,
LLVM,RISCV,2627,return IsSigned;
LLVM,RISCV,2628,
LLVM,RISCV,2629,
LLVM,RISCV,2630,"return DAG.getNode(<STR_LIT>, DL, VT, Lo, Hi, VL);"
LLVM,RISCV,2631,
LLVM,RISCV,2632,
LLVM,RISCV,2633,unsigned Count = ValueVTBitSize / PartEltVT.getSizeInBits();
LLVM,RISCV,2634,return IsLegalMask(NewMask);
LLVM,RISCV,2635,NewMask = NewMask.shl(MinSignedBits);
LLVM,RISCV,2636,"SDValue New2 = DAG.getNode(<STR_LIT>, DL, VT, New1, DAG.getConstant(C0, DL, VT));"
LLVM,RISCV,2637,"SDValue NA0 = DAG.getNode(<STR_LIT>, DL, VT, NL, DAG.getConstant(Diff, DL, VT));"
LLVM,RISCV,2638,"CC = <STR_LIT> ( CC ) ; std :: swap ( LHS , RHS ) ;"
LLVM,RISCV,2639,"Hi = DAG.getLoad(<STR_LIT>, DL, Chain, FIN, MachinePointerInfo::getFixedStack(MF, FI));"
LLVM,RISCV,2640,
LLVM,RISCV,2641,Here are a few possibilities:
LLVM,RISCV,2642,return VT.isVector() && VT.getVectorElementType().isInteger() && VT.getVectorElementType().getIntegerBitWidth() == 32;
LLVM,RISCV,2643,
LLVM,RISCV,2644,for (auto Reg : Regs) {
LLVM,RISCV,2645,for (auto Reg : Regs) {
LLVM,RISCV,2646,
LLVM,RISCV,2647,Created.push_back(Cmp.getNode());
LLVM,RISCV,2648,"SDValue Result = DAG.getNode(ISD::ANY_EXTEND, DL, NarrowVT, Op1);"
LLVM,RISCV,2649,
LLVM,RISCV,2650,
LLVM,RISCV,2651,
LLVM,RISCV,2652,SDValue NewRes = D
LLVM,RISCV,2653,
LLVM,RISCV,2654,
LLVM,RISCV,2655,return JumpTableEncoding::Relative;
LLVM,RISCV,2656,
LLVM,RISCV,2657,"In the `default` case, the code calls the `llvm_unreachable` function, which is a"
LLVM,RISCV,2658,Info.opc = <STR_LIT>;
LLVM,RISCV,2659,return SDValue ( II ) ;
LLVM,RISCV,2660,
LLVM,RISCV,2661,if (VT == <STR_LIT> && !Subtarget.hasStdExtZfh()) return false;
LLVM,RISCV,2662,if (VT == <STR_LIT> && !Subtarget.hasStdExtZfh()) return false;
LLVM,RISCV,2663,if (Srcs[0] < 0 || Srcs[1] < 0 || Srcs[0] == Srcs[1]) return false;
LLVM,RISCV,2664,return LD->getMemoryVT() == VT2;
LLVM,RISCV,2665,
LLVM,RISCV,2666,"return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , Ctx ) ;"
LLVM,RISCV,2667,"return MCSymbolRefExpr::create(MBB->getSymbol(), Ctx);"
LLVM,RISCV,2668,
LLVM,RISCV,2669,"SDValue ScalarSplat = lowerScalarSplat(ScalarVal, DAG.getConstant(<NUM_LIT>, DL, XLenVT), M1VT, DL, DAG, Subtarget);"
LLVM,RISCV,2670,MVT M1VT = getLMUL1VT(VectorVal.getSimpleValueType());
LLVM,RISCV,2671,return FpToInt;
LLVM,RISCV,2672,
LLVM,RISCV,2673,
LLVM,RISCV,2674,"SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT);"
LLVM,RISCV,2675,
LLVM,RISCV,2676,
LLVM,RISCV,2677,"Val = DAG.getNode(MaskOpc, DL, ContainerVT, Op1, Op2, VL);"
LLVM,RISCV,2678,"Index = DAG . getNode ( <STR_LIT> , DL , IndexVT , Index , TrueMask , VL ) ;"
LLVM,RISCV,2679,
LLVM,RISCV,2680,Ops.push_back(VL);
LLVM,RISCV,2681,"return DAG.getNode(<STR_LIT>, DL, VT, Scalar, VL);"
LLVM,RISCV,2682,"SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags());"
LLVM,RISCV,2683,
LLVM,RISCV,2684,
LLVM,RISCV,2685,"SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , ResVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;"
LLVM,RISCV,2686,
LLVM,RISCV,2687,
LLVM,RISCV,2688,return Shift;
LLVM,RISCV,2689,
LLVM,RISCV,2690,"SDValue Result = DAG.getNode(Opc, DL, DstVT, FpToInt, ZeroInt);"
LLVM,RISCV,2691,
LLVM,RISCV,2692,
LLVM,RISCV,2693,return false;
LLVM,RISCV,2694,
LLVM,RISCV,2695,ValueEltVT = ValueVT.getVectorElementType();
LLVM,RISCV,2696,"Op0 = DAG.getNode(ExtOpc, DL, NarrowVT, Op0, Mask, VL);"
LLVM,RISCV,2697,Op0 = Op0.getOperand(<NUM_LIT>);
LLVM,RISCV,2698,if (Addend != SeqAddend) return None;
LLVM,RISCV,2699,"return Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});"
LLVM,RISCV,2700,case AtomicRMWInst :: Min : return <STR_LIT> ;
LLVM,RISCV,2701,case AtomicRMWInst :: UMin : return <STR_LIT> ;
LLVM,RISCV,2702,
LLVM,RISCV,2703,
LLVM,RISCV,2704,if (Size == 32) {
LLVM,RISCV,2705,
LLVM,RISCV,2706,
LLVM,RISCV,2707,
LLVM,RISCV,2708,case <STR_LIT> :
LLVM,RISCV,2709,
LLVM,RISCV,2710,case <STR_LIT> :
LLVM,RISCV,2711,"setOperationAction(<STR_LIT>, XLenVT, Custom)"
LLVM,RISCV,2712,
LLVM,RISCV,2713,
LLVM,RISCV,2714,"Value * Result = Builder.CreateCall(Intrinsic::masked_atomic_cmpxchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});"
LLVM,RISCV,2715,"return DCI.CombineTo(N, Op0.getOperand(<NUM_LIT>), Op0.getOperand(<NUM_LIT>));"
LLVM,RISCV,2716,"setOperationAction(<STR_LIT>, XLenVT, Expand);"
LLVM,RISCV,2717,"State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, VA1.getLocVT(), CCValAssign::Full));"
LLVM,RISCV,2718,if (LocVT == <STR_LIT>) {
LLVM,RISCV,2719,"State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));"
LLVM,RISCV,2720,
LLVM,RISCV,2721,return VLOperand != <NUM_LIT> ;
LLVM,RISCV,2722,
LLVM,RISCV,2723,LocVT = XLenVT;
LLVM,RISCV,2724,if ( ArgFlags . isSplit ( ) || ! PendingLocs . empty ( ) ) {
LLVM,RISCV,2725,
LLVM,RISCV,2726,"setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;"
LLVM,RISCV,2727,Info.opc = <STR_LIT>;
LLVM,RISCV,2728,
LLVM,RISCV,2729,
LLVM,RISCV,2730,"SDValue Vec = DAG.getBitcast(I32VT, Op.getOperand(NumOps - OpOffset));"
LLVM,RISCV,2731,"SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , Ops , MGN -> getMemoryVT ( ) , MGN -> getMemOperand ( ) ) ;"
LLVM,RISCV,2732,"VL = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), ContainerVT, Index);"
LLVM,RISCV,2733,"VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT);"
LLVM,RISCV,2734,"VL = DAG.getRegister(<STR_LIT>, XLenVT);"
LLVM,RISCV,2735,Ops.push_back(VL);
LLVM,RISCV,2736,
LLVM,RISCV,2737,SDValue Lo = Op.getOperand(0);
LLVM,RISCV,2738,"Vec = DAG.getNode(BaseOpc, DL, VecEVT, Lo, Hi);"
LLVM,RISCV,2739,
LLVM,RISCV,2740,
LLVM,RISCV,2741,* Fast = true;
LLVM,RISCV,2742,if (Opcode == <STR_LIT> && !N->getFlags().hasAllowReassociation()) return SDValue();
LLVM,RISCV,2743,if (Opcode == <STR_LIT> && N->getFlags().hasNoSignedZeros() && isNullFPConstant(V)) return true;
LLVM,RISCV,2744,
LLVM,RISCV,2745,
LLVM,RISCV,2746,"TailMBB->splice(TailMBB->end(), HeadMBB, std::next(LastSelectPseudo->getIterator()), HeadMBB->end());"
LLVM,RISCV,2747,"SDValue mask = getAllOnesMask(VecVT, VL, D"
LLVM,RISCV,2748,unsigned NumElts = (VT.getVectorNumElements() * <STR_LIT>) / MinVLen;
LLVM,RISCV,2749,enum MVT {
LLVM,RISCV,2750,"SDValue Mask = getAllOnesMask(ContainerVT, VL, DL, DAG);"
LLVM,RISCV,2751,
LLVM,RISCV,2752,assert(EC > 0);
LLVM,RISCV,2753,"int Srcs[2] = { -1, -1 };"
LLVM,RISCV,2754,return false;
LLVM,RISCV,2755,
LLVM,RISCV,2756,ContainerVT = getContainerForFixedLengthVector(VecVT);
LLVM,RISCV,2757,"SDValue Result = DAG.getNode(ISD::SELECT, DL, ContainerVT, Cmp, Op1, Op2);"
LLVM,RISCV,2758,
LLVM,RISCV,2759,GV = N
LLVM,RISCV,2760,
LLVM,RISCV,2761,"SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ;"
LLVM,RISCV,2762,
LLVM,RISCV,2763,
LLVM,RISCV,2764,MVT MaskVT = getMaskTypeFor(ContainerVT);
LLVM,RISCV,2765,"SmallVector<SDValue, <NUM_LIT>> Ops { Chain, DAG.getTargetConstant(IntID, DL, XLenVT) };"
LLVM,RISCV,2766,"Index = DAG.getNode(<STR_LIT>, DL, IndexVT, Index, TrueMask, VL);"
LLVM,RISCV,2767,if (IsUnmasked) {
LLVM,RISCV,2768,"Src = DAG.getNode(ConvOpc, DL, ContainerVT, Src, Mask, VL);"
LLVM,RISCV,2769,"Vec = DAG.getNode(<STR_LIT>, DL, I32VT, Passthru, Vec, ScalarHi, I32Mask, I32VL);"
LLVM,RISCV,2770,"SDValue SplatOne = DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ;"
LLVM,RISCV,2771,Result = Src;
LLVM,RISCV,2772,SrcEltVT = <STR_LIT> ( SrcEltVT . getSizeInBits ( ) / <NUM_LIT> ) ;
LLVM,RISCV,2773,"SDValue UpOffset = DAG.getNode(<STR_LIT>, DL, XLenVT, VLMax, DownOffset);"
LLVM,RISCV,2774,
LLVM,RISCV,2775,"SDValue Result = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Src , Splat , ZeroSplat , VL ) ;"
LLVM,RISCV,2776,"Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget));"
LLVM,RISCV,2777,MVT ContainerVT = getContainerForFixedLengthVector(VT);
LLVM,RISCV,2778,"Result = DAG.getNode(<STR_LIT>, DL, ContainerVT, Op1, Op2, VL);"
LLVM,RISCV,2779,
LLVM,RISCV,2780,
LLVM,RISCV,2781,
LLVM,RISCV,2782,"if ( SDValue V = combineBinOpToReduce ( N , DAG ) ) return V ;"
LLVM,RISCV,2783,return GORC;
LLVM,RISCV,2784,
LLVM,RISCV,2785,if (XC && OldShiftOpcode == <STR_LIT> && XC->isOne()) return false;
LLVM,RISCV,2786,return false;
LLVM,RISCV,2787,return Subtarget . is64Bit ( ) && CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ;
LLVM,RISCV,2788,case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ; break ;
LLVM,RISCV,2789,Explanation:
LLVM,RISCV,2790,
LLVM,RISCV,2791,LLVM_DEBUG(dbgs() << <STR_LIT> << i << <STR_LIT> << EVT(ArgVT).getEVTString() << '\n');
LLVM,RISCV,2792,
LLVM,RISCV,2793,if (ValVT == <STR_LIT> && !UseGPRForF16_F32) Reg = State.AllocateReg(ArgFPR16s);
LLVM,RISCV,2794,if (LocVT == <STR_LIT> || LocVT == <STR_LIT>) {
LLVM,RISCV,2795,NonConstantVal = TrueVal;
LLVM,RISCV,2796,return Result;
LLVM,RISCV,2797,"SDValue Result = combineSelectCCAndUse(N, N0, N1, DAG, AllOnes);"
LLVM,RISCV,2798,"Known = KnownBits::urem(Known.trunc(<NUM_LIT>), Known2.trunc(<NUM_LIT>));"
LLVM,RISCV,2799,case <STR_LIT> :
LLVM,RISCV,2800,if (Subtarget.hasStdExtM() && VT.getSizeInBits() >= Subtarget.getXLen()) return false;
LLVM,RISCV,2801,return false;
LLVM,RISCV,2802,switch (Constraint.getType()) {
LLVM,RISCV,2803,
LLVM,RISCV,2804,
LLVM,RISCV,2805,"int C1Cost = getCost(C1Int, Ty.getSizeInBits(), Subtarget.is64Bit());"
LLVM,RISCV,2806,"SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget);"
LLVM,RISCV,2807,"SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL, Subtarget.getXLenVT());"
LLVM,RISCV,2808,VT = <STR_LIT>;
LLVM,RISCV,2809,VaArgOffset = CCInfo.getNextStackOffset();
LLVM,RISCV,2810,
LLVM,RISCV,2811,"VL = MVT(ContainerVT, IndexVT, DAG, Subtarget);"
LLVM,RISCV,2812,
LLVM,RISCV,2813,"StepVec = DAG.getNode(<STR_LIT>, DL, VT, Mask, VL);"
LLVM,RISCV,2814,"StepVec = DAG.getNode(<STR_LIT>, DL, VT, StepVec, StepVal);"
LLVM,RISCV,2815,"SDValue Gather = DAG . getNode ( GatherOpc , DL , ContainerVT , V1 , LHSIndices , TrueMask , VL ) ;"
LLVM,RISCV,2816,"Ops.push_back(DAG.getZExtOrTrunc(V, DL, XLenVT));"
LLVM,RISCV,2817,
LLVM,RISCV,2818,
LLVM,RISCV,2819,
LLVM,RISCV,2820,"if (auto GREV = combineORToGREV(SDValue(N, <NUM_LIT>), DAG, Subtarget)) return GREV;"
LLVM,RISCV,2821,"return SDValue(N, <NUM_LIT>);"
LLVM,RISCV,2822,
LLVM,RISCV,2823,
LLVM,RISCV,2824,"LMul = divideCeil(VT.getSizeInBits(), MinVLen);"
LLVM,RISCV,2825,case <STR_LIT> :
LLVM,RISCV,2826,if (Step != SeqStep) return None;
LLVM,RISCV,2827,"if ( SeqStep ) { int64_t Addend = SignExtend64 ( Val - ( Idx * ( uint64_t ) * SeqStep ) , EltSizeInBits ) ; if ( ! SeqAddend ) SeqAddend = Addend ; else if ( SeqAddend != Addend ) return Non"
LLVM,RISCV,2828,"SDValue Result = translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);"
LLVM,RISCV,2829,"SDValue Gather = DAG.getNode(GatherOpc, DL, ContainerVT, V1, DAG.getConstant(Lane, DL, XLenVT), TrueMask, VL);"
LLVM,RISCV,2830,
LLVM,RISCV,2831,
LLVM,RISCV,2832,
LLVM,RISCV,2833,return false;
LLVM,RISCV,2834,
LLVM,RISCV,2835,"Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ;"
LLVM,RISCV,2836,VL = Op . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2837,"Result = DAG.getNode(ISD::VEC_TRUNC, DL, ContainerVT, Result, Mask, VL);"
LLVM,RISCV,2838,"SDValue Result = DAG.getNode(ISD::VEC_SPLAT, DL, ContainerVT, Src, Splat, ZeroSplat, VL);"
LLVM,RISCV,2839,
LLVM,RISCV,2840,MVT VT = Op . getSimpleValueType ( ) ;
LLVM,RISCV,2841,"MIB.addImm(<ISA_LIT>VType::encodeVTYPE(Multiplier, ElementWidth, true, false));"
LLVM,RISCV,2842,LLVM_DEBUG ( dbg
LLVM,RISCV,2843,
LLVM,RISCV,2844,if (VT.isVector() && VT.getVectorNumElements() > 1) {
LLVM,RISCV,2845,Outs[i].VT = VT;
LLVM,RISCV,2846,Reg = State.AllocateReg(ArgGPRs);
LLVM,RISCV,2847,CombinedShAmt = ShAmt1 | ShAmt2;
LLVM,RISCV,2848,
LLVM,RISCV,2849,"Val = DAG.getNode(<STR_LIT>, DL, <STR_LIT>, Val);"
LLVM,RISCV,2850,if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
LLVM,RISCV,2851,"case <STR_LIT> : assert ( ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; return emitReadCycleWidePseudo ( MI , BB ) ;"
LLVM,RISCV,2852,
LLVM,RISCV,2853,
LLVM,RISCV,2854,
LLVM,RISCV,2855,OutChains.push_back(Chain);
LLVM,RISCV,2856,
LLVM,RISCV,2857,"case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ;"
LLVM,RISCV,2858,"case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ;"
LLVM,RISCV,2859,
LLVM,RISCV,2860,RetOps[0] = Chain;
LLVM,RISCV,2861,"SDValue Result = DAG.getNode(<STR_LIT>, DL, Op.getValueType(), Ops);"
LLVM,RISCV,2862,if (Src.getOpcode() == <STR_LIT> && isa<ConstantSDNode>(Src.getOperand(<NUM_LIT>))) {
LLVM,RISCV,2863,"case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; APInt LHSMask = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> )"
LLVM,RISCV,2864,
LLVM,RISCV,2865,FirstMaskArgument = I;
LLVM,RISCV,2866,Here are a few possibilities for the next statement:
LLVM,RISCV,2867,
LLVM,RISCV,2868,WOpc = Op1.getOpcode();
LLVM,RISCV,2869,unsigned ShAmt2 = Src.getConstantOperandVal(<NUM_LIT>);
LLVM,RISCV,2870,CombinedShAmt = ShAmt1 + ShAmt2;
LLVM,RISCV,2871,Op0 = Op0 . getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,2872,if ( BitWidth < <NUM_LIT> || ShAmt1 != ( BitWidth / <NUM_LIT> ) || ShAmt2 != ( BitWidth - <NUM_LIT> ) ) return SDValue ( ) ;
LLVM,RISCV,2873,uint64_t Mask = GREVMasks[Stage];
LLVM,RISCV,2874,Res = ( ( x & Mask ) << Shift ) | ( ( x >> Shift ) & Mask ) ;
LLVM,RISCV,2875,
LLVM,RISCV,2876,"SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, <STR_LIT>);"
LLVM,RISCV,2877,
LLVM,RISCV,2878,"SDValue MNLo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrLo ) , <NUM_LIT> ) ;"
LLVM,RISCV,2879,case <STR_LIT> :
LLVM,RISCV,2880,if (X & Y != 0) {
LLVM,RISCV,2881,if (C && C->getAPIntValue().ule(<NUM_LIT>)) {
LLVM,RISCV,2882,int MaskSrc = M < Size ? <NUM_LIT> : <NUM_LIT>;
LLVM,RISCV,2883,assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ;
LLVM,RISCV,2884,
LLVM,RISCV,2885,
LLVM,RISCV,2886,"return ( isElementRotate ( LoSrc , HiSrc , M ) > <NUM_LIT> ) || isInterleaveShuffle ( M , SVT , SwapSources , Subtarget ) ;"
LLVM,RISCV,2887,"SDValue SplatZero = DAG.getNode(<STR_LIT>, DL, ContainerVT, DAG.getUNDEF(ContainerVT), DAG.getConstant(<NUM_LIT>, DL, Subtarget.getXLenVT()));"
LLVM,RISCV,2888,
LLVM,RISCV,2889,
LLVM,RISCV,2890,"SDValue NewValue = convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);"
LLVM,RISCV,2891,"SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, DAG.getUNDEF(M1VT), VectorVal, ScalarSplat, Mask, VL);"
LLVM,RISCV,2892,MVT M1VT = getLMUL1VT(VectorVal.getSimpleValueType());
LLVM,RISCV,2893,
LLVM,RISCV,2894,
LLVM,RISCV,2895,
LLVM,RISCV,2896,
LLVM,RISCV,2897,"SDValue One = DAG.getConstant(1, DL, XLenVT);"
LLVM,RISCV,2898,if ( VT . isFloatingPoint ( ) ) {
LLVM,RISCV,2899,
LLVM,RISCV,2900,
LLVM,RISCV,2901,"SDValue ShiftRightOp = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, VT, Lo, Shamt);"
LLVM,RISCV,2902,int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ;
LLVM,RISCV,2903,"return DAG.getNode(<STR_LIT>, DL, VecVT, DAG.getUNDEF(VecVT), Lo, DAG.getRegister(<STR_LIT>, <STR_LIT>));"
LLVM,RISCV,2904,"StepVec = DAG . getNode ( <STR_LIT> , DL , VT , StepVec , StepVal ) ;"
LLVM,RISCV,2905,"StepVec = DAG.getNode(<STR_LIT>, DL, VT, StepVec, StepVal);"
LLVM,RISCV,2906,"SDValue Vec = convertToScalableVector(ContainerVT, Vec, DAG, Subtarget);"
LLVM,RISCV,2907,
LLVM,RISCV,2908,
LLVM,RISCV,2909,"SDValue Mask = DAG.getNode(ISD::SETCC, DL, MaskVT, Trunc, SplatZero, getCondCodeForSetCC(CondCode::SETLT));"
LLVM,RISCV,2910,"SDValue Trunc = DAG.getNode(<STR_LIT>, DL, ContainerVT, Src, SplatOne, Mask, VL);"
LLVM,RISCV,2911,
LLVM,RISCV,2912,
LLVM,RISCV,2913,"UpOffset = DAG.getConstant(ImmValue, DL, XLenVT);"
LLVM,RISCV,2914,MVT InterimFVT = DstVT;
LLVM,RISCV,2915,"SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , StartSplat , Vec , StartSplat , Mask , VL ) ;"
LLVM,RISCV,2916,ContainerVT = VT . getFixedLengthVectorElementType ( ) ;
LLVM,RISCV,2917,
LLVM,RISCV,2918,"SDValue Result = DAG.getNode(ISD::BITREVERSE, SDLoc(N), Src);"
LLVM,RISCV,2919,SDValue Src = N->getOperand(<NUM_LIT>);`
LLVM,RISCV,2920,if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit() && Src.getOpcode() == <STR_LIT> && Src.hasOneUse() && VT == <STR_LIT> && cast<VTSDNode>(N->getOperand(<NUM_LIT>))->getVT() == <STR_LIT> && DAG.ComputeNumSignBits(Src.getOperand(<NUM_LIT>)) > <NU
LLVM,RISCV,2921,
LLVM,RISCV,2922,Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ;
LLVM,RISCV,2923,
LLVM,RISCV,2924,
LLVM,RISCV,2925,
LLVM,RISCV,2926,"Reg = State.AllocateReg(ArgFPR16s, ArgFPR64s);"
LLVM,RISCV,2927,"Val = DAG.getNode(<STR_LIT>, DL, VA.getValVT(), Val);"
LLVM,RISCV,2928,
LLVM,RISCV,2929,case CCValAssign::Full: break;
LLVM,RISCV,2930,"Val = DAG.getNode(<STR_LIT>, DL, <STR_LIT>, Val);"
LLVM,RISCV,2931,MI . getOperand ( <NUM_LIT> ) . setReg (
LLVM,RISCV,2932,
LLVM,RISCV,2933,case <STR_LIT>:
LLVM,RISCV,2934,"MachineInstr * LoInstr = MF.createPseudoReg(LoReg, MI.getType());"
LLVM,RISCV,2935,
LLVM,RISCV,2936,if (isNullConstant(Idx)) return Op;
LLVM,RISCV,2937,"SDValue Result = DAG.getNode(<STR_LIT>, DL, EltVT, Slidedown);"
LLVM,RISCV,2938,Operands.push_back(Promote);
LLVM,RISCV,2939,
LLVM,RISCV,2940,
LLVM,RISCV,2941,case <STR_LIT>:
LLVM,RISCV,2942,case <STR_LIT> :
LLVM,RISCV,2943,ExtType = MVT::i32;
LLVM,RISCV,2944,
LLVM,RISCV,2945,"State.addLoc(CCValAssign::getReg(ValNo2, ValVT2, Reg, LocVT2, CCValAssign::Full));"
LLVM,RISCV,2946,if (LocVT == <STR_LIT> || LocVT == <STR_LIT>) {
LLVM,RISCV,2947,
LLVM,RISCV,2948,"return emitSelectPseudo ( MI , BB ) ;"
LLVM,RISCV,2949,
LLVM,RISCV,2950,"Value * MaskedCmpXchg = Builder.CreateCall(MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});"
LLVM,RISCV,2951,"Incr = Builder.CreateSExt(Incr, Builder.getInt64Ty());"
LLVM,RISCV,2952,"Result = Builder . CreateCall ( LrwOpScwLoop , { AlignedAddr , Incr , Mask , SextShamt , Ordering } ) ;"
LLVM,RISCV,2953,
LLVM,RISCV,2954,Args.push_back(Load);
LLVM,RISCV,2955,return <STR_LIT> ( Subtarget . getTargetABI ( ) ) ? <NUM_LIT> : <NUM_LIT> ;
LLVM,RISCV,2956,
LLVM,RISCV,2957,
LLVM,RISCV,2958,if (Op.isAligned(CapAlign)) {
LLVM,RISCV,2959,"EVT ResultType = getSetCCResultType(DL, Context, VT);"
LLVM,RISCV,2960,"SDValue MNAdd = SDValue(DAG.getMachineNode(<STR_LIT>, DL, Ty, MNHi, TPReg, AddrAdd), <NUM_LIT>);"
LLVM,RISCV,2961,return TailPaddingAmount :: None;
LLVM,RISCV,2962,
LLVM,RISCV,2963,BlockAddress * BA = N->getBlockAddress();
LLVM,RISCV,2964,"return getAddr(N, Ty, DAG, true, true);"
LLVM,RISCV,2965,"return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , LHS , RHS , TargetCC , Op . getOperand ( <NUM_LIT> ) ) ;"
LLVM,RISCV,2966,ConstantPoolSDNode * pool = N->
LLVM,RISCV,2967,unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;
LLVM,RISCV,2968,return Addr;
LLVM,RISCV,2969,
LLVM,RISCV,2970,
LLVM,RISCV,2971,
LLVM,RISCV,2972,
LLVM,RISCV,2973,
LLVM,RISCV,2974,int Off = - XLenInBytes;
LLVM,RISCV,2975,"SDValue Ops[ ] = { LHS, RHS, TargetCC, TrueV, FalseV };"
LLVM,RISCV,2976,"SDValue TargetCC = DAG . getTargetConstant ( CCVal , DL , XLenVT ) ;"
LLVM,RISCV,2977,const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;
LLVM,RISCV,2978,Ops.push_back(SetCC->getOperand(<NUM_LIT>));
LLVM,RISCV,2979,return AtomicExpansionKind :: None;
LLVM,RISCV,2980,
LLVM,RISCV,2981,if (Size < 32) return AtomicExpansionKind::CmpXChg;
LLVM,RISCV,2982,
LLVM,RISCV,2983,return false;
LLVM,RISCV,2984,
LLVM,RISCV,2985,"However, based on the name of the function and the fact that it is declared as a `const` method, it is likely that the function returns a boolean value indicating whether the `Operand` object has a splat operand. The `splat` method is typically used to create a new operand that is a copy of the original operand, but"
LLVM,RISCV,2986,
LLVM,RISCV,2987,BitVector ReservedRegs = Subtarget.getRegisterInfo().getReservedRegs(MF);
LLVM,RISCV,2988,if ( ! Value . getNode ( ) ) {
LLVM,RISCV,2989,"LLVM_DEBUG(dbgs() << ""Building vector with "" << NumElts << "" elements\n"");"
LLVM,RISCV,2990,
LLVM,RISCV,2991,
LLVM,RISCV,2992,"BuildMI(HeadMBB, DL, TII.get(Opcode)).addReg(LHS).addReg(RHS).addMBB(TailMBB);"
LLVM,RISCV,2993,
LLVM,RISCV,2994,
LLVM,RISCV,2995,
LLVM,RISCV,2996,
LLVM,RISCV,2997,
LLVM,RISCV,2998,
LLVM,RISCV,2999,
LLVM,RISCV,3000,
LLVM,RISCV,3001,
LLVM,RISCV,3002,llvm_unreachable(nullptr);
LLVM,RISCV,3003,
LLVM,RISCV,3004,
LLVM,RISCV,3005,
LLVM,RISCV,3006,
LLVM,RISCV,3007,"ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL);"
LLVM,RISCV,3008,
LLVM,RISCV,3009,
LLVM,RISCV,3010,
LLVM,RISCV,3011,"However, based on the names of the functions and the variables, it is likely that the next statement will be a call to `getMachineNode` with the same arguments as the previous call, but with a different first argument. The first argument is likely to be a different machine node,"
LLVM,RISCV,3012,
LLVM,RISCV,3013,"SDValue Result = DAG.getBlockAddress(N->getFunction(), N->getBasicBlock());"
LLVM,RISCV,3014,
LLVM,RISCV,3015,"SDValue Addr = getAddr(N, DAG);"
LLVM,RISCV,3016,
LLVM,RISCV,3017,
LLVM,RISCV,3018,if (UseMI && UseMI->isImplicitDef()) TailAgnostic = true;
LLVM,RISCV,3019,MI = MRI.getVRegDef(MI->getOperand(<NUM_LIT>).getReg());
LLVM,RISCV,3020,
LLVM,RISCV,3021,
LLVM,RISCV,3022,"return DAG.getNode(<STR_LIT>, DL, VecVT, Lo);"
LLVM,RISCV,3023,"Gather = DAG . getNode ( GatherOpc , DL , ContainerVT , V1 , LHSIndices , TrueMask , VL ) ;"
LLVM,RISCV,3024,
LLVM,RISCV,3025,
LLVM,RISCV,3026,int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( );
LLVM,RISCV,3027,if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) {
LLVM,RISCV,3028,"SDValue NewOp = DAG.getNode(<STR_LIT>, DL, <STR_LIT>, NewOp0);"
LLVM,RISCV,3029,"SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ;"
LLVM,RISCV,3030,
LLVM,RISCV,3031,
LLVM,RISCV,3032,"setOperationAction(<STR_LIT>, <STR_LIT>, Expand);"
LLVM,RISCV,3033,
LLVM,RISCV,3034,
LLVM,RISCV,3035,Base = LS -> getBasePtr ( ) ;
LLVM,RISCV,3036,
LLVM,RISCV,3037,
LLVM,RISCV,3038,It
LLVM,RISCV,3039,
LLVM,RISCV,3040,"SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , XLenVT ) ;"
LLVM,RISCV,3041,
LLVM,RISCV,3042,Mask = MLoad->getMask(); PassThru = MLoad->getPassThru();
LLVM,RISCV,3043,
LLVM,RISCV,3044,
LLVM,RISCV,3045,
LLVM,RISCV,3046,Instruction * Op = dyn_cast <Instruction> (OpIdx.value().get());
LLVM,RISCV,3047,Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ;
LLVM,RISCV,3048,if (Subtarget.hasStdExtF() && VT == <STR_LIT>)
LLVM,RISCV,3049,
LLVM,RISCV,3050,
LLVM,RISCV,3051,
LLVM,RISCV,3052,Results.push_back(Res.getValue(I));
LLVM,RISCV,3053,Results.push_back(Res);
LLVM,RISCV,3054,
LLVM,RISCV,3055,
LLVM,RISCV,3056,"SDValue finalResult = DAG . getNode ( <STR_LIT> , DL , RegTy , rawResult , mask ) ;"
LLVM,RISCV,3057,EVT Ty = Op.getValueType(pos);
LLVM,RISCV,3058,
LLVM,RISCV,3059,case <STR_LIT>:
LLVM,RISCV,3060,"setOperationAction(<STR_LIT>, XLenVT, Custom);"
LLVM,RISCV,3061,"setOperationAction(<STR_LIT>, <STR_LIT>, Custom);"
LLVM,RISCV,3062,"setOperationAction(<STR_LIT>, <STR_LIT>, Custom)"
LLVM,RISCV,3063,
LLVM,RISCV,3064,"Results.push_back(customLegalizeToWOp(N, DAG));"
LLVM,RISCV,3065,"MIB.addReg(DestReg, RegState::Define | RegState::Dead).addReg(MI.getOperand(VLIndex).getReg());"
LLVM,RISCV,3066,TailAgnostic = false;
LLVM,RISCV,3067,Known . resetAll ( ) ;
LLVM,RISCV,3068,Known = Known . sext ( BitWidth ) ;
LLVM,RISCV,3069,return Subtarget.getXLen() - Op.getOperand(<NUM_LIT>).getScalarValueSizeInBits() + <NUM_LIT>;
LLVM,RISCV,3070,
LLVM,RISCV,3071,
LLVM,RISCV,3072,
LLVM,RISCV,3073,return SDValue ( ) ;
LLVM,RISCV,3074,
LLVM,RISCV,3075,
LLVM,RISCV,3076,"return DAG.getNode(ISD::SPLAT_VECTOR, DL, VecVT, SplatVal, Zero);"
LLVM,RISCV,3077,"SplatZero = DAG.getSplatVector(VecVT, DL, SplatZero);"
LLVM,RISCV,3078,"SDValue Result = DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatOne, SplatZero);"
LLVM,RISCV,3079,if (NewMask == Mask) return true;
LLVM,RISCV,3080,"SDValue NewRHS = DAG.getNode(<STR_LIT>, DL, RHS.getValueType(), RHS, DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), <NUM_LIT>)));"
LLVM,RISCV,3081,
LLVM,RISCV,3082,Offset = Op -> getOperand ( <NUM_LIT> ) ;
LLVM,RISCV,3083,
LLVM,RISCV,3084,In the code
LLVM,RISCV,3085,
LLVM,RISCV,3086,"MachineInstrBuilder pbclrMI = BuildMI( *BB, MI, DL, TII->get(opcode) );"
LLVM,RISCV,3087,pbclrMI.addOperand(MI.getOperand(<NUM_LIT>));
LLVM,RISCV,3088,"However, based on the variable names and the context of the code, it appears that the code is generating a machine code instruction that performs a bitwise operation on two operands. The instruction is being generated using a library or framework that provides a set of functions for generating machine code instructions, and the specific instruction being generated is determined by the value of the `"
LLVM,RISCV,3089,
LLVM,RISCV,3090,
LLVM,RISCV,3091,paddrnMI . addOperand ( MI . getOperand ( reg1 ) ) ;
LLVM,RISCV,3092,
LLVM,RISCV,3093,
LLVM,RISCV,3094,"However, based on the names of the variables and the operations performed by the `OPCODE` macro, it is likely that the next statement will be a call to the `OPCODE` macro with the `SMIN` or `UMIN` operation, followed by a call to the `"
LLVM,RISCV,3095,
LLVM,RISCV,3096,case AtomicOrdering :: NotAtomic :
LLVM,RISCV,3097,unsigned pred = PI | PO | PR | PW ;
LLVM,RISCV,3098,OutChains.push_back(Store);
LLVM,RISCV,3099,"Glue = DAG.getNode(ISA_LIT, DL, RetOps, Chain);"
LLVM,RISCV,3100,return SDValue ( ) ;
LLVM,RISCV,3101,
LLVM,RISCV,3102,"Prefix = StringRef(B, I - B);"
LLVM,RISCV,3103,
LLVM,RISCV,3104,if ( Prefix == <STR_LIT> ) {
LLVM,RISCV,3105,
LLVM,RISCV,3106,
LLVM,RISCV,3107,return TargetLowering::getConstraintType(Constraint);
LLVM,RISCV,3108,"return lowerSETVL(Op, DAG);"
LLVM,RISCV,3109,
LLVM,RISCV,3110,
LLVM,RISCV,3111,
LLVM,RISCV,3112,
LLVM,RISCV,3113,"return DAG . getNode ( <STR_LIT> , DL , VT , SplatVal ) ;"
LLVM,RISCV,3114,"return DAG . getNode ( <STR_LIT> , DL , VT , SplatVal ) ;"
LLVM,RISCV,3115,"MIB.addReg(DestReg, RegState::Define | RegState::Dead).addReg(MI.getOperand(VLIndex).getReg());"
LLVM,RISCV,3116,
LLVM,RISCV,3117,case <STR_LIT> :
LLVM,RISCV,3118,
LLVM,RISCV,3119,return VT.changeVectorElementTypeToInteger();
LLVM,RISCV,3120,return getPointerTy(DL);
LLVM,RISCV,3121,
LLVM,RISCV,3122,unsigned ExtOpc = isa < ConstantSDNode > ( ScalarOp ) ? <STR_LIT> : <STR_LIT> ;
LLVM,RISCV,3123,
LLVM,RISCV,3124,"case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ;"
LLVM,RISCV,3125,"Hi = DAG.getNode(<STR_LIT>, DL, VecVT, Hi, ThirtyTwoV);"
LLVM,RISCV,3126,
LLVM,RISCV,3127,return ArgIdx.index();
LLVM,RISCV,3128,MVT ArgVT = ArgIdx.value().VT;
LLVM,RISCV,3129,
LLVM,RISCV,3130,
LLVM,RISCV,3131,
LLVM,RISCV,3132,Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ;
LLVM,RISCV,3133,
LLVM,RISCV,3134,"However, based on the names of the methods and the context of the code, it is likely that the next statement will be a call to the `getNode` method, passing in the values of `DL`, `VA.getValVT()`, and `Value` as arguments. The `getNode` method is likely to return a"
LLVM,RISCV,3135,"Value = DAG.getNode(<STR_LIT>, DL, VA.getLocVT(), Value, DAG.getValueType(VA.getValVT()));"
LLVM,RISCV,3136,
LLVM,RISCV,3137,
LLVM,RISCV,3138,
LLVM,RISCV,3139,"SDValue NewVASTART = DAG.getVASTART(Chain, Addr, PtrVT, FuncInfo);"
LLVM,RISCV,3140,
LLVM,RISCV,3141,
LLVM,RISCV,3142,unsigned Reg = State . AllocateReg ( ArgGPRs ) ;
LLVM,RISCV,3143,"State.addLoc(CCValAssign::getMem(ValNo2, ValVT2, State.AllocateStack(XLenInBytes, XLenInBytes), LocVT2, CCValAssign::Full));"
LLVM,RISCV,3144,break;
LLVM,RISCV,3145,
LLVM,RISCV,3146,"Val = DAG.getNode(<STR_LIT>, DL, LocVT, Val);"
LLVM,RISCV,3147,
LLVM,RISCV,3148,"Result = Builder.CreateCall(MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});"
LLVM,RISCV,3149,Type * Tys[ ] = { AlignedAddr -> getType ( ) } ;
LLVM,RISCV,3150,"Result = Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, SextShamt, Ordering});"
LLVM,RISCV,3151,
LLVM,RISCV,3152,return Builder.CreateFence(AtomicOrdering::Acquire);
LLVM,RISCV,3153,return Builder.CreateFence(AtomicOrdering::Acquire);
LLVM,RISCV,3154,case AtomicRMWInst::Xchg:
LLVM,RISCV,3155,llvm_unreachable(<STR_LIT>);
LLVM,RISCV,3156,"return std::make_pair(<NUM_LIT>, &<STR_LIT>);"
LLVM,RISCV,3157,"return std::make_pair(<NUM_LIT>, &<STR_LIT>);"
LLVM,RISCV,3158,return VT.changeVectorElementTypeToInteger();
LLVM,RISCV,3159,"return DL.getTypeSizeInBits(VT) > DL.getTypeSizeInBits(EVT::getSetCCResultType(DL, LLVMContext, VT));"
LLVM,RISCV,3160,return <STR_LIT>;
LLVM,RISCV,3161,
LLVM,RISCV,3162,
LLVM,RISCV,3163,if (IsCallerStructRet && IsCalleeStructRet) return false;
LLVM,RISCV,3164,
LLVM,RISCV,3165,
LLVM,RISCV,3166,return Subtarget.is64Bit() && SrcVT == <STR_LIT> && DstVT == <STR_LIT>;
LLVM,RISCV,3167,Here are a few possibilities for the next statement:
LLVM,RISCV,3168,return (SrcBits == <NUM_LIT> && DestBits == <NUM_LIT>);
LLVM,RISCV,3169,case Instruction::SDiv:
LLVM,RISCV,3170,
LLVM,RISCV,3171,return false;
LLVM,RISCV,3172,"SDValue MNLo = SDValue(DAG.getMachineNode(<STR_LIT>, DL, Ty, BALo), <NUM_LIT>);"
LLVM,RISCV,3173,InVals.push_back(ArgValue);
LLVM,RISCV,3174,"InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo()));"
LLVM,RISCV,3175,"FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());"
LLVM,RISCV,3176,```
LLVM,RISCV,3177,"SDValue MNLo = SDValue(DAG.getMachineNode(<STR_LIT>, DL, Ty, MNHi, GALo), <NUM_LIT>);"
LLVM,RISCV,3178,
LLVM,RISCV,3179,
LLVM,RISCV,3180,"SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);"
LLVM,RISCV,3181,"unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));"
LLVM,RISCV,3182,"SDValue Result = DAG.getNode(ISD::SETCC, DL, VTs, LHS, RHS, TargetCC);"
LLVM,RISCV,3183,"return DAG.getStore(Op.getOperand(<NUM_LIT>), DL, FI, Op.getOperand(<NUM_LIT>), MachinePointerInfo(SV));"
LLVM,RISCV,3184,FuncInfo->setVAStart(Op.getOperand(0));
LLVM,RISCV,3185,
LLVM,RISCV,3186,
LLVM,RISCV,3187,
LLVM,RISCV,3188,return true;
LLVM,RISCV,3189,return AtomicExpansionKind::MaskedIntrinsic;
LLVM,RISCV,3190,Here are a few possible next statements:
LLVM,RISCV,3191,
LLVM,RISCV,3192,"Hi = DAG.getCopyFromReg(Chain, DL, LoVReg, <STR_LIT>);"
LLVM,RISCV,3193,
LLVM,RISCV,3194,
LLVM,RISCV,3195,
LLVM,RISCV,3196,getLegacyLegalizerInfo().computeTables().getLeg
LLVM,RISCV,3197,* `ISA_LIT` is a macro that expands to a string literal containing the name of the instruction set architecture (ISA) being targeted.
LLVM,RISCV,3198,return CalleeSavedStackSize;
LLVM,RISCV,3199,
LLVM,RISCV,3200,return RVVPadding;
LLVM,RISCV,3201,
LLVM,RISCV,3202,"However, based on the name of the method and the return type, it is likely that the method returns the size of a stack or queue that is used to store return values. The `const` keyword at the end of the method signature suggests that the method does not modify the state of the object, and that it is a ""pure"" function that only depends"
LLVM,RISCV,3203,"mapping(IO, MFI);"
LLVM,RISCV,3204,CalleeSavedStackSize = Size;
LLVM,RISCV,3205,"However, based on the name of the function and the parameter, it is likely that the function is setting the stack alignment for the RVV (RISC-V Vector Extension) to the value specified by the `StackAlign` parameter. The `Align` class is likely used to represent the alignment of the stack"
LLVM,RISCV,3206,
LLVM,RISCV,3207,
LLVM,RISCV,3208,return MF.getSubtarget<ISA_LIT>Subtarget>().enableSaveRestore() && VarArgsSaveSize == NUM_LIT && !MF.getFrameInfo().hasTailCall();
LLVM,RISCV,3209,
LLVM,RISCV,3210,"EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(), RC->getAlignment(), false);"
LLVM,RISCV,3211,
LLVM,RISCV,3212,return LibCallStackSize;
LLVM,RISCV,3213,return LibCallStackSize;
LLVM,RISCV,3214,return moveFrameIndex;
LLVM,RISCV,3215,return CallsEhReturn && ( FI == EhDataRegFI [ <NUM_LIT> ] || FI == EhDataRegFI [ <NUM_LIT> ] ) ;
LLVM,RISCV,3216,
LLVM,RISCV,3217,
LLVM,RISCV,3218,Some possible next statements could be:
LLVM,RISCV,3219,MachineFunctionInfo(MF);
LLVM,RISCV,3220,MachineFunctionInfo(MF);
LLVM,RISCV,3221,LibCallStackSize = Size;
LLVM,RISCV,3222,
LLVM,RISCV,3223,
LLVM,RISCV,3224,
LLVM,RISCV,3225,
LLVM,RISCV,3226,
LLVM,RISCV,3227,
LLVM,RISCV,3228,return VarArgsFirstGPR + 1;
LLVM,RISCV,3229,
LLVM,RISCV,3230,
LLVM,RISCV,3231,
LLVM,RISCV,3232,SavedGPRFrameSize = 0;
LLVM,RISCV,3233,SavedGPRFrameSize = 0;
LLVM,RISCV,3234,
LLVM,RISCV,3235,
LLVM,RISCV,3236,"However, based on the name of the function and the types of the parameters, it is likely that the function is used to set the formal argument information for a function or method, and the `Size` parameter is used to specify the size of the formal argument list, while the `HasByval` parameter is used to indicate whether the function has a by-value parameter"
LLVM,RISCV,3237,HighSavedGPR = Reg;
LLVM,RISCV,3238,
LLVM,RISCV,3239,
LLVM,RISCV,3240,RegSaveFrameIndex = FI;
LLVM,RISCV,3241,
LLVM,RISCV,3242,
LLVM,RISCV,3243,
LLVM,RISCV,3244,VarArgsFirstFPR = FPR ;
LLVM,RISCV,3245,
LLVM,RISCV,3246,
LLVM,RISCV,3247,
LLVM,RISCV,3248,
LLVM,RISCV,3249,
LLVM,RISCV,3250,
LLVM,RISCV,3251,VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;
LLVM,RISCV,3252,MachineFunction(MF);
LLVM,RISCV,3253,MachineFunction(MF);
LLVM,RISCV,3254,VarArgsFrameIndex = Index ;
LLVM,RISCV,3255,return VarArgsSaveSize;
LLVM,RISCV,3256,
LLVM,RISCV,3257,RCToScavenge = & <STR_LIT>;
LLVM,RISCV,3258,
LLVM,RISCV,3259,
LLVM,RISCV,3260,return new <ISA_LIT>MakeCompressibleOpt ( ) ;
LLVM,RISCV,3261,"However, based on the name of the function and the parameters it takes, it is likely that the function is used to calculate a base address adjustment for compression. The `Offset` parameter is likely to be the offset of the data to be compressed, and the `Opcode` parameter is likely to be the opcode"
LLVM,RISCV,3262,"However, based on the name of the function and the parameters it takes, it is likely that the function is used to calculate a base address adjustment for compression. The `Offset` parameter is likely to be the offset of the data to be compressed, and the `Opcode` parameter is likely to be the opcode"
LLVM,RISCV,3263,
LLVM,RISCV,3264,if (isCompressibleStore(MI)) {
LLVM,RISCV,3265,"if ( ! MOImm . isImm ( ) ) return RegImmPair ( <STR_LIT> , <NUM_LIT> ) ;"
LLVM,RISCV,3266,
LLVM,RISCV,3267,
LLVM,RISCV,3268,
LLVM,RISCV,3269,"However, based on the names of the methods and the types of the variables, it is likely that the next statement will be a call to a method on the `STI` object, such as `STI.getOpcode()` or `STI.getSubtarget()`. The `STI` object is a reference to a subtarget, and the `get"
LLVM,RISCV,3270,return Opcode == <STR_LIT> || ( ! STI . is64Bit ( ) && Opcode == <STR_LIT> ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;
LLVM,RISCV,3271,
LLVM,RISCV,3272,Some possible next statements could include:
LLVM,RISCV,3273,
LLVM,RISCV,3274,MOImm.setImm(NewOffset);
LLVM,RISCV,3275,
LLVM,RISCV,3276,
LLVM,RISCV,3277,"Res.push_back(Inst(<STR_LIT>, Lo12));"
LLVM,RISCV,3278,"Res.push_back(Inst(<STR_LIT>, ShiftAmount));"
LLVM,RISCV,3279,"TmpSeq.push_back(<STR_LIT> (<STR_LIT>, <NUM_LIT>));"
LLVM,RISCV,3280,
LLVM,RISCV,3281,"Res.push_back(<STR_LIT> (<STR_LIT>, ShiftAmount));"
LLVM,RISCV,3282,
LLVM,RISCV,3283,Res.push_back(Lo12);
LLVM,RISCV,3284,
LLVM,RISCV,3285,
LLVM,RISCV,3286,Res = TmpSeq;
LLVM,RISCV,3287,"Res.push_back(<STR_LIT>(<STR_LIT>, Hi20));"
LLVM,RISCV,3288,Compressed = false;
LLVM,RISCV,3289,
LLVM,RISCV,3290,"Res.push_back(Inst(<STR_LIT>, ShiftAmount));"
LLVM,RISCV,3291,
LLVM,RISCV,3292,MatSeq.push_back(Chunk);
LLVM,RISCV,3293,return <NUM_LIT> - UpperTrailingOnes;
LLVM,RISCV,3294,unsigned UpperTrailingOnes = countTrailingOnes ( Hi_32 ( Val ) ) ;
LLVM,RISCV,3295,if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) {
LLVM,RISCV,3296,if (isUInt<NUM_LIT>(Hi52) && !isInt<NUM_LIT>(Hi52) && ActiveFeatures[STR_LIT]) {
LLVM,RISCV,3297,Cost += <NUM_LIT>;
LLVM,RISCV,3298,
LLVM,RISCV,3299,"TmpSeq.push_back(<STR_LIT>(Opc, Bit + <NUM_LIT>));"
LLVM,RISCV,3300,int64_t Lo12 = SignExtend64 < <NUM_LIT> > ( Val ) ;
LLVM,RISCV,3301,if ( Res . size ( ) > <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) {
LLVM,RISCV,3302,if (isUInt < <NUM_LIT> > (Val) && !isInt < <NUM_LIT> > (Val) && ActiveFeatures[<STR_LIT>]) {
LLVM,RISCV,3303,case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Compressed = isInt < <NUM_LIT> > ( Instr . Imm
LLVM,RISCV,3304,Div = <NUM_LIT>;
LLVM,RISCV,3305,"Res.push_back(<STR_LIT>(<STR_LIT>, Lo12));"
LLVM,RISCV,3306,
LLVM,RISCV,3307,"Cost += getInstSeqCost(MatSeq, HasRVC);"
LLVM,RISCV,3308,"Cost += getInstSeqCost(MatSeq, HasRVC);"
LLVM,RISCV,3309,if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind);
LLVM,RISCV,3310,Res.setOpcode(Opcode);
LLVM,RISCV,3311,"MCAsmBackend * backend = llvm::create<ISA_LIT>MCAsmBackend(T, MRI, TT, CPU);"
LLVM,RISCV,3312,"const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT"
LLVM,RISCV,3313,
LLVM,RISCV,3314,return (int16_t)Value != (int64_t)Value;
LLVM,RISCV,3315,Res.setOpcode(Opcode);
LLVM,RISCV,3316,OSABI = osABI;
LLVM,RISCV,3317,OSABI = osABI;
LLVM,RISCV,3318,OW->write8(0);
LLVM,RISCV,3319,
LLVM,RISCV,3320,"return MCAsmInfo :: getExprForFDESymbol ( Sym , Encoding , Streamer ) ;"
LLVM,RISCV,3321,
LLVM,RISCV,3322,One possible next statement could be: ExceptionsType = ExceptionHandling :: DwarfCFI ; Another possible next statement could be:
LLVM,RISCV,3323,
LLVM,RISCV,3324,
LLVM,RISCV,3325,CalleeSaveStackSlotSize = TT.isArch64Bit() ? <NUM_LIT> : <NUM_LIT>;
LLVM,RISCV,3326,
LLVM,RISCV,3327,Here are a few possible next statements:
LLVM,RISCV,3328,
LLVM,RISCV,3329,MCAsmInfo::MCAsmInfo(const Triple &TT) : MCAsmInfo(TT) {}
LLVM,RISCV,3330,CalleeSaveStackSlotSize = TT.isArch64Bit() ? <NUM_LIT> : <NUM_LIT>;
LLVM,RISCV,3331,Data64bitsDirective = <STR_LIT> ;
LLVM,RISCV,3332,
LLVM,RISCV,3333,"Fixups.push_back(MCFixup::create(<NUM_LIT>, Expr, MCFixupKind(FixupKind), MI.getLoc()));"
LLVM,RISCV,3334,"Fixups.push_back(MCFixup::create(<NUM_LIT>, Expr, MCFixupKind(FixupKind), MI.getLoc()));"
LLVM,RISCV,3335,"case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); <STR_LIT> :: write < uint16_t > (O"
LLVM,RISCV,3336,
LLVM,RISCV,3337,MCNumEmitted += <NUM_LIT>;
LLVM,RISCV,3338,
LLVM,RISCV,3339,
LLVM,RISCV,3340,
LLVM,RISCV,3341,
LLVM,RISCV,3342,"<STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;"
LLVM,RISCV,3343,switch (Size) {
LLVM,RISCV,3344,
LLVM,RISCV,3345,
LLVM,RISCV,3346,"return new MCCodeEmitter(Ctx, MCII);"
LLVM,RISCV,3347,
LLVM,RISCV,3348,"uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);"
LLVM,RISCV,3349,
LLVM,RISCV,3350,if (DestReg.isReg() && SrcReg.isReg() && TPReg.isReg()) {
LLVM,RISCV,3351,"<STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;"
LLVM,RISCV,3352,TmpInst = MCInstBuilder(<STR_LIT>)
LLVM,RISCV,3353,
LLVM,RISCV,3354,
LLVM,RISCV,3355,MCNumEmitted++;
LLVM,RISCV,3356,OS.write(Bits);
LLVM,RISCV,3357,"Based on the patterns we see in the code, it is likely that the next statement will be"
LLVM,RISCV,3358,
LLVM,RISCV,3359,
LLVM,RISCV,3360,++MCNumEmitted;
LLVM,RISCV,3361,
LLVM,RISCV,3362,
LLVM,RISCV,3363,case <NUM_LIT> : {
LLVM,RISCV,3364,
LLVM,RISCV,3365,
LLVM,RISCV,3366,case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ;
LLVM,RISCV,3367,"Fixups.push_back(MCFixup::create(<NUM_LIT>, Expr, MCFixupKind(FixupKind), MI.getLoc()));"
LLVM,RISCV,3368,
LLVM,RISCV,3369,"<STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;"
LLVM,RISCV,3370,TmpInst = MCInstBuilder(<STR_LIT>) .addReg(<STR_LIT>) .addReg(Ra) .addImm(<NUM_LIT>);
LLVM,RISCV,3371,"Fixups.push_back(MCFixup::create(<NUM_LIT>, Expr, MCFixupKind(FixupKind), MI.getLoc()));"
LLVM,RISCV,3372,"Fixups.push_back(MCFixup::create(<NUM_LIT>, Dummy, MCFixupKind(<STR_LIT>), MI.getLoc()));"
LLVM,RISCV,3373,"Fixups.push_back(MCFixup::create(<NUM_LIT>, Expr, MCFixupKind(FixupKind), MI.getLoc()));"
LLVM,RISCV,3374,"return new MCCodeEmitter<ISA_LIT>(MCII, MRI, Ctx);"
LLVM,RISCV,3375,"return new MCCodeEmitter<ISA_LIT>(MCII, MRI, Ctx);"
LLVM,RISCV,3376,ShiftValue = (ShiftValue << I) & (Size - 1);
LLVM,RISCV,3377,return MO . getImm ( ) << <NUM_LIT> ;
LLVM,RISCV,3378,
LLVM,RISCV,3379,Some possible next statements could include:
LLVM,RISCV,3380,return MO.getImm() << <NUM_LIT>;
LLVM,RISCV,3381,Here are some possible next statements:
LLVM,RISCV,3382,return static_cast < unsigned > ( MO . getImm ( ) ) ;
LLVM,RISCV,3383,if (MO.isImm()) return MO.getImm();
LLVM,RISCV,3384,
LLVM,RISCV,3385,
LLVM,RISCV,3386,if (MO.isImm()) {
LLVM,RISCV,3387,return Expr->evaluateAsConstant();`
LLVM,RISCV,3388,return Expr->evaluateAsConstant();`
LLVM,RISCV,3389,
LLVM,RISCV,3390,
LLVM,RISCV,3391,
LLVM,RISCV,3392,
LLVM,RISCV,3393,switch (Size) {
LLVM,RISCV,3394,TmpInst = MCInstBuilder(<STR_LIT>) .addReg(<STR_LIT>) .addReg(Ra) .addImm(<NUM_LIT>);
LLVM,RISCV,3395,
LLVM,RISCV,3396,"Fixups.push_back(MCFixup::create(<NUM_LIT>, Expr, MCFixupKind(FixupKind), MI.getLoc()));"
LLVM,RISCV,3397,
LLVM,RISCV,3398,
LLVM,RISCV,3399,"return new <ISA_LIT>MCCodeEmitter(Ctx, MCII);"
LLVM,RISCV,3400,
LLVM,RISCV,3401,"<STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;"
LLVM,RISCV,3402,Here is the next statement
LLVM,RISCV,3403,
LLVM,RISCV,3404,
LLVM,RISCV,3405,
LLVM,RISCV,3406,
LLVM,RISCV,3407,
LLVM,RISCV,3408,
LLVM,RISCV,3409,"However, based on the name of the class and the method being overridden, it is likely that the next statement will be related to emitting machine code for a specific instruction set architecture (ISA). The `MCCodeEmitter` class is likely to be a part of a code generation framework that generates machine code for a specific ISA, and the `emit` method is likely to be responsible for em"
LLVM,RISCV,3410,"However, based on the name of the class and the method being overridden, it is likely that the next statement will be related to emitting machine code for a specific instruction set architecture (ISA). The `MCCodeEmitter` class is likely to be a part of a code generation framework that generates machine code for a specific ISA, and the `emit` method is likely to be responsible for em"
LLVM,RISCV,3411,"return new MCExpr(Expr, Kind, Ctx);"
LLVM,RISCV,3412,return Res;
LLVM,RISCV,3413,
LLVM,RISCV,3414,"Res = MCValue::get(Target.getSymA(), nullptr, Target.getConstant() + (Fixup->getOffset() - AUIPCOffset));"
LLVM,RISCV,3415,const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSRE -> findAssociatedFragment ( ) ) ;
LLVM,RISCV,3416,return nullptr;
LLVM,RISCV,3417,"return StringSwitch<MCExpr::VariantKind>(name).Case(<STR_LIT>, VK_<ISA_LIT>_LO).Case(<STR_LIT>, VK_<ISA_LIT>_HI).Case(<STR_LIT>, VK_<ISA_LIT>_PCREL_LO).Case(<STR_LIT>, VK_<ISA_LIT>_PCREL_HI).Default(VK_<ISA_"
LLVM,RISCV,3418,
LLVM,RISCV,3419,
LLVM,RISCV,3420,
LLVM,RISCV,3421,
LLVM,RISCV,3422,
LLVM,RISCV,3423,if (Value.isPCRelative()) return false;
LLVM,RISCV,3424,Res = evaluateAsInt64(Value.getConstant());
LLVM,RISCV,3425,
LLVM,RISCV,3426,return true;
LLVM,RISCV,3427,
LLVM,RISCV,3428,case MCExpr :: Unary :
LLVM,RISCV,3429,
LLVM,RISCV,3430,Offset = <NUM_LIT>;
LLVM,RISCV,3431,
LLVM,RISCV,3432,OS << ')';
LLVM,RISCV,3433,
LLVM,RISCV,3434,Res = evaluateAsInt64(Value.getConstant());
LLVM,RISCV,3435,
LLVM,RISCV,3436,Offset = <NUM_LIT>;
LLVM,RISCV,3437,
LLVM,RISCV,3438,
LLVM,RISCV,3439,
LLVM,RISCV,3440,if (Kind == VK_<ISA_LIT>_CALL_PLT) OS << <STR_LIT>;
LLVM,RISCV,3441,Res = evaluateAsInt64(Value.getConstant());
LLVM,RISCV,3442,
LLVM,RISCV,3443,return false;
LLVM,RISCV,3444,switch ( ( unsigned ) F . getKind ( ) ) {
LLVM,RISCV,3445,
LLVM,RISCV,3446,
LLVM,RISCV,3447,case VK_<ISA_LIT>_PCREL_HI :
LLVM,RISCV,3448,return false;
LLVM,RISCV,3449,
LLVM,RISCV,3450,Offset = <NUM_LIT>;
LLVM,RISCV,3451,Kind = Kind;
LLVM,RISCV,3452,Kind = Kind;
LLVM,RISCV,3453,
LLVM,RISCV,3454,
LLVM,RISCV,3455,"return new (Ctx) MCExpr(Kind, Expr);"
LLVM,RISCV,3456,
LLVM,RISCV,3457,case MCExpr::SymbolRef:
LLVM,RISCV,3458,case VK_<ISA_LIT>_LO12 : return <STR_LIT> ;
LLVM,RISCV,3459,case VK_<ISA_LIT>_TPREL_HI20 : return <STR_LIT> ;
LLVM,RISCV,3460,
LLVM,RISCV,3461,Here are a few possibilities:
LLVM,RISCV,3462,
LLVM,RISCV,3463,case VK_<ISA_LIT>_LO :
LLVM,RISCV,3464,"Res = MCValue::get(Target.getSymA(), nullptr, Target.getConstant() + (Fixup->getOffset() - AUIPCOffset));"
LLVM,RISCV,3465,if (AUIPCOffset + Target.getSymA()->getSymbol().getOffset() > 0x80000000) return false;
LLVM,RISCV,3466,Offset = AUIPCSymbol -> getOffset ( ) ;
LLVM,RISCV,3467,
LLVM,RISCV,3468,if (AUIPCSymbol->getKind() != MCSymbolRefExpr::VK_None) return false;
LLVM,RISCV,3469,Res = evaluateAsInt64(Value.getConstant());
LLVM,RISCV,3470,
LLVM,RISCV,3471,Res = MCValue();
LLVM,RISCV,3472,"Res = getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup);"
LLVM,RISCV,3473,return getSubExpr().findAssociatedFragment().getAssociatedValue();
LLVM,RISCV,3474,return getSubExpr().findAssociatedFragment().getAssociatedValue();
LLVM,RISCV,3475,
LLVM,RISCV,3476,
LLVM,RISCV,3477,
LLVM,RISCV,3478,
LLVM,RISCV,3479,
LLVM,RISCV,3480,
LLVM,RISCV,3481,"return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;"
LLVM,RISCV,3482,
LLVM,RISCV,3483,return <STR_LIT>;
LLVM,RISCV,3484,this->Expr = Expr;
LLVM,RISCV,3485,this->Expr = Expr;
LLVM,RISCV,3486,return (Flags & VariantKindMask) >> VariantKindShift;
LLVM,RISCV,3487,OutMI.setOpcode(Opcode);
LLVM,RISCV,3488,
LLVM,RISCV,3489,
LLVM,RISCV,3490,"Expr = MCBinaryExpr::createAdd(Expr, OffsetExpr, Ctx);"
LLVM,RISCV,3491,"MCInstLower::MCInstLower(MCContext &ctx, AsmPrinter &asmprinter) : Ctx(ctx), AsmPrinter(asmprinter) {"
LLVM,RISCV,3492,"MCInstLower::MCInstLower(MCContext &ctx, AsmPrinter &asmprinter) : Ctx(ctx), AsmPrinter(asmprinter) {"
LLVM,RISCV,3493,OutMI.emit(OutMI);
LLVM,RISCV,3494,
LLVM,RISCV,3495,
LLVM,RISCV,3496,report_fatal_error(<STR_LIT>);
LLVM,RISCV,3497,
LLVM,RISCV,3498,OutMI.addOperand(MCOp);
LLVM,RISCV,3499,OutMI.setOpcode(<STR_LIT>);
LLVM,RISCV,3500,
LLVM,RISCV,3501,MCOp = MCOperand::createReg(MO->getReg());
LLVM,RISCV,3502,
LLVM,RISCV,3503,Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO;
LLVM,RISCV,3504,
LLVM,RISCV,3505,
LLVM,RISCV,3506,return MCOperand::createExpr(ME);
LLVM,RISCV,3507,"const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ;"
LLVM,RISCV,3508,return MCOperand::createExpr(ME);
LLVM,RISCV,3509,
LLVM,RISCV,3510,
LLVM,RISCV,3511,"Expr = MCBinaryExpr::createAdd(Expr, OffsetExpr, Ctx);"
LLVM,RISCV,3512,
LLVM,RISCV,3513,
LLVM,RISCV,3514,MCOp.setReg(Reg);
LLVM,RISCV,3515,
LLVM,RISCV,3516,
LLVM,RISCV,3517,MCOp = MCOperand(some_value);
LLVM,RISCV,3518,case MachineOperand::
LLVM,RISCV,3519,"case MachineOperand::MO_ExternalSymbol: MCOp = lowerSymbolOperand(MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP); break;"
LLVM,RISCV,3520,"However, based on the names of the methods and the context in which they are being called, it is likely that the next statement will be a call to a method on the `MCSubtargetInfo` object returned by `getSubtargetInfo`. The `MCSubtargetInfo` class is part of the LLVM project and is used to represent"
LLVM,RISCV,3521,
LLVM,RISCV,3522,llvm_unreachable(<STR_LIT>);
LLVM,RISCV,3523,case MCSymbolRefExpr::VK_GOT: llvm_unreachable(<STR_LIT>);
LLVM,RISCV,3524,
LLVM,RISCV,3525,
LLVM,RISCV,3526,
LLVM,RISCV,3527,
LLVM,RISCV,3528,case MCSymbolRefExpr :: VK_GOT :
LLVM,RISCV,3529,case FK_Data_4: return ELF::R_<ISA_LIT>_TLS_TPREL32;
LLVM,RISCV,3530,
LLVM,RISCV,3531,this->setRelocationModel(RelocationModel::Static);
LLVM,RISCV,3532,this->setRelocationModel(RelocationModel::Static);
LLVM,RISCV,3533,
LLVM,RISCV,3534,
LLVM,RISCV,3535,MAI->addInitialFrameState(Inst);
LLVM,RISCV,3536,MAI->addInitialFrameState(Inst);
LLVM,RISCV,3537,"X -> initMCCodeGenInfo(RM, CM, OL);"
LLVM,RISCV,3538,"X -> initMCCodeGenInfo(RM, CM, OL);"
LLVM,RISCV,3539,"return new <ISA_LIT>MCInstPrinter(TT, SyntaxVariant, MAI, MII, MRI);"
LLVM,RISCV,3540,return X;
LLVM,RISCV,3541,
LLVM,RISCV,3542,
LLVM,RISCV,3543,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,RISCV,3544,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,RISCV,3545,
LLVM,RISCV,3546,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,RISCV,3547,Here are some possible next statements:
LLVM,RISCV,3548,"TargetRegistry::RegisterMCAsmInfo(*T, create<ISA_LIT>MCAsmInfo);"
LLVM,RISCV,3549,
LLVM,RISCV,3550,"return new MCTargetStreamer<ISA_LIT>(S, STI, TT);"
LLVM,RISCV,3551,
LLVM,RISCV,3552,MAI->addInitialFrameState(Inst);
LLVM,RISCV,3553,"return new <ISA_LIT>MCAsmInfo(MRI, TT);"
LLVM,RISCV,3554,"* `MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;`: This line creates a new instance of the `MCAsmInfo` class, passing in the `TT` object as a parameter. The `new` operator is used to allocate memory for the new object on the heap. The `MAI` variable is then assigned the address of"
LLVM,RISCV,3555,MCRegisterInfo * X = create<ISA_LIT>MCRegisterInfo ( TT );
LLVM,RISCV,3556,MCRegisterInfo * X = create<ISA_LIT>MCRegisterInfo ( TT );
LLVM,RISCV,3557,TargetRegistry::Register
LLVM,RISCV,3558,"TargetRegistry::RegisterMCCodeEmitter(*T, create<ISA_LIT>MCCodeEmitter);"
LLVM,RISCV,3559,if (CPUName.empty()) {
LLVM,RISCV,3560,std::string CPUName(CPU);
LLVM,RISCV,3561,
LLVM,RISCV,3562,CPU = TT.isArch64Bit() ? <STR_LIT> : <STR_LIT>;
LLVM,RISCV,3563,"MAI->setDwarfRegNum(<STR_LIT>, true);"
LLVM,RISCV,3564,return MAI;
LLVM,RISCV,3565,#include <llvm/MC/MCStreamer.h>
LLVM,RISCV,3566,ISA_LIT streamer = create<
LLVM,RISCV,3567,MAI->setInitialFrameState(Options);
LLVM,RISCV,3568,"MAI->initialize(MRI, TT, Options);"
LLVM,RISCV,3569,
LLVM,RISCV,3570,"MCObjectFileInfo * MOFI = new MCObjectFileInfo(Ctx, PIC, LargeCodeModel);"
LLVM,RISCV,3571,CPU = TT.isArch64Bit() ? <STR_LIT> : <STR_
LLVM,RISCV,3572,"return new MCSubtargetInfo(TT, CPU, FS);"
LLVM,RISCV,3573,
LLVM,RISCV,3574,Target = Addr + Imm;
LLVM,RISCV,3575,
LLVM,RISCV,3576,
LLVM,RISCV,3577,
LLVM,RISCV,3578,
LLVM,RISCV,3579,"TargetRegistry::RegisterMCRegisterInfo( *T, create<ISA_LIT"
LLVM,RISCV,3580,MAI->addInitialFrameState(Inst);
LLVM,RISCV,3581,RAReg = <STR_LIT> ;
LLVM,RISCV,3582,"TargetRegistry::RegisterMCAsmInfo(*T, create<ISA_LIT>MCAsmInfo);"
LLVM,RISCV,3583,"TargetRegistry::RegisterMCCodeEmitter(*T, create<ISA_LIT>MCCodeEmitter);"
LLVM,RISCV,3584,
LLVM,RISCV,3585,
LLVM,RISCV,3586,TargetRegistry::RegisterMCCodeEmitter(The<ISA
LLVM,RISCV,3587,"MAI->setDwarfRegNum(Reg, true);"
LLVM,RISCV,3588,
LLVM,RISCV,3589,
LLVM,RISCV,3590,"TargetRegistry::RegisterMCCodeEmitter(*T, create<ISA_LIT>MCCodeEmitter);"
LLVM,RISCV,3591,"TargetAsmStreamer* streamer = new TargetAsmStreamer(S, OS);"
LLVM,RISCV,3592,"TargetAsmStreamer* streamer = new TargetAsmStreamer(S, OS);"
LLVM,RISCV,3593,return new <ISA_LIT>MCAsmInfo ( TT ) ;
LLVM,RISCV,3594,
LLVM,RISCV,3595,"return new <ISA_LIT>TargetELFStreamer(S, STI);"
LLVM,RISCV,3596,"return new <ISA_LIT>TargetELFStreamer(S, STI);"
LLVM,RISCV,3597,"TargetRegistry::RegisterMCCodeEmitter(*T, create<ISA_LIT>MCCodeEmitter);"
LLVM,RISCV,3598,
LLVM,RISCV,3599,if (Tail.getOperand(<NUM_LIT>).isFI()) return false;
LLVM,RISCV,3600,
LLVM,RISCV,3601,LoADDI = MRI->use_begin(HiLuiDestReg)->getParent();
LLVM,RISCV,3602,LoADDI = &HiLUI;
LLVM,RISCV,3603,ImmOp.setOffset(Offset);
LLVM,RISCV,3604,if (Tail.getOperand(<NUM_LIT>).isFI()) return false;
LLVM,RISCV,3605,
LLVM,RISCV,3606,HiLUI->getOpcode() == LLVM::Instruction::Load
LLVM,RISCV,3607,for (auto *MI : DeadInstrs) MI->eraseFromParent();
LLVM,RISCV,3608,Here
LLVM,RISCV,3609,LoADDI.getOperand(0).setOffset(Offset);
LLVM,RISCV,3610,Offset = SignExtend64 < <NUM_LIT> > ( OffsetTail . getOperand ( <NUM_LIT> ) . getImm ( ) << <NUM_LIT> ) ;
LLVM,RISCV,3611,Offset = SignExtend64 < <NUM_LIT> > ( OffsetTail . getOperand ( <NUM_LIT> ) . getImm ( ) << <NUM_LIT> ) ;
LLVM,RISCV,3612,
LLVM,RISCV,3613,"case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; foldOffset ( HiLUI , LoADDI , Tail , Offset ) ; return true ; } break ;"
LLVM,RISCV,3614,if (Tail.getOperand(<NUM_LIT>).isFI()) return false;
LLVM,RISCV,3615,
LLVM,RISCV,3616,
LLVM,RISCV,3617,case <STR_LIT> : { int64_t Offset = Tail . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Tail ) ; fold
LLVM,RISCV,3618,ImmOp.setOffset(Offset);
LLVM,RISCV,3619,
LLVM,RISCV,3620,DeadInstrs.insert(&Tail);
LLVM,RISCV,3621,
LLVM,RISCV,3622,"return ""MyPass"";"
LLVM,RISCV,3623,int64_t OffHi = AddiImmOp . getImm ( ) ;
LLVM,RISCV,3624,return false;
LLVM,RISCV,3625,return false;
LLVM,RISCV,3626,"MadeChange |= detectAndFoldOffset(HiLUI, *LoADDI);"
LLVM,RISCV,3627,LLVM_DEBUG(dbgs() << <STR_LIT> << MadeChange << <STR_LIT>);
LLVM,RISCV,3628,
LLVM,RISCV,3629,"return ""MyPass"";"
LLVM,RISCV,3630,"return <STR_LIT> . contains ( Reg1 , Reg2 ) || <STR_LIT> . contains ( Reg1 , Reg2 ) ;"
LLVM,RISCV,3631,"return <STR_LIT> . contains ( Reg1 , Reg2 ) || <STR_LIT> . contains ( Reg1 , Reg2 ) ;"
LLVM,RISCV,3632,Some possible next statements could include:
LLVM,RISCV,3633,Some possible next statements could include:
LLVM,RISCV,3634,
LLVM,RISCV,3635,
LLVM,RISCV,3636,return new PulpHWLoopsPass<ISA_LIT>();
LLVM,RISCV,3637,LoopSetup = &MI;
LLVM,RISCV,3638,Here are a few possibilities for what the next statement could be:
LLVM,RISCV,3639,
LLVM,RISCV,3640,
LLVM,RISCV,3641,"BuildMI( *Preheader, Setup, Setup->getDebugLoc(), TII->get( <STR_LIT> ) ) .addImm( LoopNum ) .addReg( count ) .addSym( LastInstrSymbol );"
LLVM,RISCV,3642,Some possible next statements could include:
LLVM,RISCV,3643,Some possible next statements could include:
LLVM,RISCV,3644,
LLVM,RISCV,3645,return new RedundantCopyEliminationPass<ISA_LIT>();
LLVM,RISCV,3646,return new RedundantCopyElimination().eliminateRedundantCopies();
LLVM,RISCV,3647,
LLVM,RISCV,3648,
LLVM,RISCV,3649,
LLVM,RISCV,3650,return true;
LLVM,RISCV,3651,
LLVM,RISCV,3652,"if ( MI -> modifiesRegister ( TargetReg , TRI ) ) break ;"
LLVM,RISCV,3653,Some possible next statements could include:
LLVM,RISCV,3654,return Changed;
LLVM,RISCV,3655,TargetRegisterInfo TRI();
LLVM,RISCV,3656,TargetRegisterInfo TRI();
LLVM,RISCV,3657,m_tri = TRI;
LLVM,RISCV,3658,m_tri = TRI;
LLVM,RISCV,3659,return &MF.getRegClass(Kind);
LLVM,RISCV,3660,return &MF.getRegClass(Kind);
LLVM,RISCV,3661,
LLVM,RISCV,3662,Offset = <NUM_LIT>;
LLVM,RISCV,3663,
LLVM,RISCV,3664,return CSR_Interrupt_SaveList;
LLVM,RISCV,3665,return CSR_Interrupt_RegMask;
LLVM,RISCV,3666,
LLVM,RISCV,3667,return Reserved;
LLVM,RISCV,3668,return Reserved;
LLVM,RISCV,3669,Offset = <NUM_LIT>;
LLVM,RISCV,3670,
LLVM,RISCV,3671,
LLVM,RISCV,3672,return RC;
LLVM,RISCV,3673,
LLVM,RISCV,3674,Ops.push_back(dwarf::DW_OP_plus);
LLVM,RISCV,3675,return MF.getSubtarget<ISA_LIT>Subtarget>().hasStdExtC() ? NUM_LIT : NUM_LIT;
LLVM,RISCV,3676,return MF.getSubtarget<ISA_LIT>Subtarget>().hasStdExtC() ? NUM_LIT : NUM_LIT;
LLVM,RISCV,3677,
LLVM,RISCV,3678,
LLVM,RISCV,3679,FrameIdx = FII->second;
LLVM,RISCV,3680,"Reserved.set(Reg, true);"
LLVM,RISCV,3681,
LLVM,RISCV,3682,
LLVM,RISCV,3683,return Reserved;
LLVM,RISCV,3684,
LLVM,RISCV,3685,
LLVM,RISCV,3686,"markSuperRegs(Reserved, <STR_LIT>)"
LLVM,RISCV,3687,"BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), VL) .addReg(FrameReg, getKillRegState(FrameRegIsKill)) .addReg(ScalableFactorRegister, RegState::Kill);"
LLVM,RISCV,3688,"MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, FrameRegIsKill);"
LLVM,RISCV,3689,return CSR_ILP32_LP64_SaveList;
LLVM,RISCV,3690,return CSR_ILP32D_LP64D_RegMask;
LLVM,RISCV,3691,return TFI -> getFPReg ( ) ;
LLVM,RISCV,3692,
LLVM,RISCV,3693,
LLVM,RISCV,3694,
LLVM,RISCV,3695,return FrameIdx;
LLVM,RISCV,3696,
LLVM,RISCV,3697,Offset = <NUM_LIT>;
LLVM,RISCV,3698,"TII->movImm(MBB, II, DL, ScratchReg, Offset);"
LLVM,RISCV,3699,
LLVM,RISCV,3700,FrameIdx = FII->second;
LLVM,RISCV,3701,"TII->movImm(MBB, II, DL, ScratchReg, Offset);"
LLVM,RISCV,3702,"BuildMI(MBB, II, DL, TII->get(<STR_LIT>), ScratchReg).addReg(FrameReg).addReg(ScratchReg, RegState::Kill);"
LLVM,RISCV,3703,
LLVM,RISCV,3704,return TFI->hasFP(MF) ? <STR_LIT> : <STR_LIT>;
LLVM,RISCV,3705,checkAllSuperRegsMarked(Reserved);
LLVM,RISCV,3706,return FII->second;
LLVM,RISCV,3707,
LLVM,RISCV,3708,Here are a few possibilities for what the next statement could be:
LLVM,RISCV,3709,
LLVM,RISCV,3710,
LLVM,RISCV,3711,"TII->movImm(MBB, II, DL, FrameReg, Offset);"
LLVM,RISCV,3712,
LLVM,RISCV,3713,
LLVM,RISCV,3714,return CSR_ILP32F_LP64F_RegMask;
LLVM,RISCV,3715,
LLVM,RISCV,3716,"MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);"
LLVM,RISCV,3717,
LLVM,RISCV,3718,
LLVM,RISCV,3719,"markSuperRegs(Reserved, <STR_LIT>)"
LLVM,RISCV,3720,
LLVM,RISCV,3721,return CSR_Interrupt_RegMask;
LLVM,RISCV,3722,if ( ! MI . isDebugValue ( ) && ! isInt < <NUM_LIT> > ( Offset ) ) {
LLVM,RISCV,3723,IsKill = (FrameReg == <STR_LIT>);
LLVM,RISCV,3724,int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
LLVM,RISCV,3725,return CSR_RV64_SaveList;
LLVM,RISCV,3726,return CSR_RV64D_SaveList;
LLVM,RISCV,3727,else if ( Subtarget . hasD ( ) ) return CSR_RV32D_RegMask ;
LLVM,RISCV,3728,return TFI->hasFP(MF) ? (Subtarget.isRV64() ? <STR_LIT> : <STR_LIT>) : (Subtarget.isRV64() ? <STR_LIT> : <STR_LIT>);
LLVM,RISCV,3729,
LLVM,RISCV,3730,
LLVM,RISCV,3731,"<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( STI ) {"
LLVM,RISCV,3732,"<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( STI ) {"
LLVM,RISCV,3733,"However, based on the name of the function and the parameters it takes, it is likely that the next statement will be a call to a method of the `TargetRegisterClass` class that returns a pointer to a register class. The `getPointerRegClass` method is likely to be a method that returns a pointer to the register class that is used for pointers of the specified"
LLVM,RISCV,3734,"However, based on the names of the functions and the context of the code, it is likely that the next statement will be a call to the `checkAllSuperRegsMarked` function, which will check whether all of the super registers have been marked. If all of the super registers have been marked, the"
LLVM,RISCV,3735,Here is a possible sequence of statements:
LLVM,RISCV,3736,
LLVM,RISCV,3737,"TII->movImm32(MBB, II, DL, ScratchReg, Offset);"
LLVM,RISCV,3738,
LLVM,RISCV,3739,
LLVM,RISCV,3740,return CSR_XLEN_F64_Interrupt_RegMask;
LLVM,RISCV,3741,return CSR_Interrupt_RegMask;
LLVM,RISCV,3742,
LLVM,RISCV,3743,
LLVM,RISCV,3744,
LLVM,RISCV,3745,
LLVM,RISCV,3746,
LLVM,RISCV,3747,
LLVM,RISCV,3748,
LLVM,RISCV,3749,
LLVM,RISCV,3750,
LLVM,RISCV,3751,firstEffectiveVSETVLI = &(*instr);
LLVM,RISCV,3752,if (firstEffectiveVSETVLI == nullptr) firstEffectiveVSETVLI = &(*instr);
LLVM,RISCV,3753,
LLVM,RISCV,3754,
LLVM,RISCV,3755,FunctionPass * create<ISA_LIT>RemoveRedundancyVSETVLPass ( ) {
LLVM,RISCV,3756,
LLVM,RISCV,3757,
LLVM,RISCV,3758,
LLVM,RISCV,3759,if (order) {
LLVM,RISCV,3760,
LLVM,RISCV,3761,
LLVM,RISCV,3762,redundancyVSETVLI.clear();
LLVM,RISCV,3763,
LLVM,RISCV,3764,Some possible next statements could include:
LLVM,RISCV,3765,pos += 1;
LLVM,RISCV,3766,return new RI5CYIRPass();
LLVM,RISCV,3767,return new <ISA_LIT>RI5CYIR ( ) ;
LLVM,RISCV,3768,
LLVM,RISCV,3769,
LLVM,RISCV,3770,if (setcc_inner.getOperand(<NUM_LIT>).getOpcode() == <STR_LIT>) {
LLVM,RISCV,3771,type = t;
LLVM,RISCV,3772,type = t;
LLVM,RISCV,3773,
LLVM,RISCV,3774,
LLVM,RISCV,3775,"errs() << ""Transforming bit manipulation in function "" << F.getName().str() << ""..."";"
LLVM,RISCV,3776,limit_l = immediate / 2;
LLVM,RISCV,3777,
LLVM,RISCV,3778,* `dag = NULL;`
LLVM,RISCV,3779,
LLVM,RISCV,3780,Args.push_back(Entry);
LLVM,RISCV,3781,
LLVM,RISCV,3782,"return callFunction(DAG, dl, Chain, memFnName, Dst, Src, Size);"
LLVM,RISCV,3783,if (DstAS == <NUM_LIT>) {
LLVM,RISCV,3784,const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( SelectionDAG & DAG ) { return reinterpret_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) ;
LLVM,RISCV,3785,
LLVM,RISCV,3786,~ <ISA_LIT>SelectionDAGInfo ( ) {
LLVM,RISCV,3787,~ <ISA_LIT>SelectionDAGInfo ( ) {
LLVM,RISCV,3788,const MachineInstr *UserOp = &MI;
LLVM,RISCV,3789,
LLVM,RISCV,3790,
LLVM,RISCV,3791,if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; }
LLVM,RISCV,3792,if ( !MI->getOperand(I).isReg() ) return false;
LLVM,RISCV,3793,case <STR_LIT> : {
LLVM,RISCV,3794,case <STR_LIT> : return MI.getOperand(<NUM_LIT>).getImm() >= <NUM_LIT>;
LLVM,RISCV,3795,
LLVM,RISCV,3796,
LLVM,RISCV,3797,
LLVM,RISCV,3798,"return ""MyPass"";"
LLVM,RISCV,3799,
LLVM,RISCV,3800,if ( MI -> getOpcode ( ) == <STR_LIT> ) { E = MI -> getNumOperands ( ) ; D = <NUM_LIT> ; }
LLVM,RISCV,3801,
LLVM,RISCV,3802,Here are a few possibilities for what the next statement could be:
LLVM,RISCV,3803,initialize<ISA_LIT>SExtWRemovalPass(PassRegistry::getPassRegistry());
LLVM,RISCV,3804,"MRI.replaceRegWith(DstReg, SrcReg);"
LLVM,RISCV,3805,
LLVM,RISCV,3806,
LLVM,RISCV,3807,
LLVM,RISCV,3808,
LLVM,RISCV,3809,"However, based on the name of the function and the return type, it is likely that the function returns a pointer to a `RegisterInfo` object that represents a register in the ISA. The `const` keyword in the function signature suggests that the function does not modify the state of the object it is called on, and the `getRegisterInfo` name suggests that the function is"
LLVM,RISCV,3810,
LLVM,RISCV,3811,
LLVM,RISCV,3812,
LLVM,RISCV,3813,"return bindsLocally(GV, RM);"
LLVM,RISCV,3814,return TargetTriple.isOSBinFormatELF();
LLVM,RISCV,3815,return TargetTriple.isOSBinFormatELF();
LLVM,RISCV,3816,"InstrInfo = RISCVInstrInfo(initializeSubtargetDependencies(CPU, FS));"
LLVM,RISCV,3817,"InstrInfo = RISCVInstrInfo(initializeSubtargetDependencies(CPU, FS));"
LLVM,RISCV,3818,return UseSoftFloat;
LLVM,RISCV,3819,
LLVM,RISCV,3820,
LLVM,RISCV,3821,
LLVM,RISCV,3822,
LLVM,RISCV,3823,
LLVM,RISCV,3824,return EnableUnalignedScalarMem;
LLVM,RISCV,3825,
LLVM,RISCV,3826,return hasVInstructionsI64() ? <NUM_LIT> : <NUM_LIT>;
LLVM,RISCV,3827,
LLVM,RISCV,3828,
LLVM,RISCV,3829,
LLVM,RISCV,3830,return <NUM_LIT> ;
LLVM,RISCV,3831,return maxVLen;
LLVM,RISCV,3832,
LLVM,RISCV,3833,
LLVM,RISCV,3834,
LLVM,RISCV,3835,
LLVM,RISCV,3836,TSInfo->someMethod();
LLVM,RISCV,3837,TSInfo->someMethod();
LLVM,RISCV,3838,* `const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override`: This is a member function that returns a pointer to a `TargetLowering` object. The `const` keyword indicates that the function does not modify the object it is called on. The `<ISA_LIT>` template parameter is a placeholder for
LLVM,RISCV,3839,* `const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override`: This is a member function that returns a pointer to a `TargetLowering` object. The `const` keyword indicates that the function does not modify the object it is called on. The `<ISA_LIT>` template parameter is a placeholder for
LLVM,RISCV,3840,return XLen;
LLVM,RISCV,3841,
LLVM,RISCV,3842,
LLVM,RISCV,3843,return HasStdExtA;
LLVM,RISCV,3844,
LLVM,RISCV,3845,
LLVM,RISCV,3846,
LLVM,RISCV,3847,
LLVM,RISCV,3848,
LLVM,RISCV,3849,
LLVM,RISCV,3850,
LLVM,RISCV,3851,
LLVM,RISCV,3852,return HasStdExtZbb;
LLVM,RISCV,3853,
LLVM,RISCV,3854,
LLVM,RISCV,3855,
LLVM,RISCV,3856,
LLVM,RISCV,3857,
LLVM,RISCV,3858,
LLVM,RISCV,3859,return HasStdExtZbkx;
LLVM,RISCV,3860,
LLVM,RISCV,3861,"For example, the next statement might be a conditional statement that checks the return"
LLVM,RISCV,3862,return HasStdExtZbm;
LLVM,RISCV,3863,
LLVM,RISCV,3864,
LLVM,RISCV,3865,return HasStdExtZbr;
LLVM,RISCV,3866,bool hasStdExt
LLVM,RISCV,3867,
LLVM,RISCV,3868,
LLVM,RISCV,3869,
LLVM,RISCV,3870,return HasStdExtZfh;
LLVM,RISCV,3871,
LLVM,RISCV,3872,return HasStdExtZfhmin;
LLVM,RISCV,3873,
LLVM,RISCV,3874,
LLVM,RISCV,3875,
LLVM,RISCV,3876,
LLVM,RISCV,3877,
LLVM,RISCV,3878,
LLVM,RISCV,3879,
LLVM,RISCV,3880,
LLVM,RISCV,3881,
LLVM,RISCV,3882,
LLVM,RISCV,3883,
LLVM,RISCV,3884,
LLVM,RISCV,3885,
LLVM,RISCV,3886,
LLVM,RISCV,3887,
LLVM,RISCV,3888,
LLVM,RISCV,3889,
LLVM,RISCV,3890,return HasStdExtZve32f && HasStdExtF;
LLVM,RISCV,3891,return HasStdExtZve64d && HasStdExtD;
LLVM,RISCV,3892,
LLVM,RISCV,3893,
LLVM,RISCV,3894,
LLVM,RISCV,3895,return HasRV64;
LLVM,RISCV,3896,
LLVM,RISCV,3897,
LLVM,RISCV,3898,
LLVM,RISCV,3899,
LLVM,RISCV,3900,Based on the structure of the code and the naming conventions
LLVM,RISCV,3901,return PowerOf2Floor(Max);
LLVM,RISCV,3902,
LLVM,RISCV,3903,
LLVM,RISCV,3904,
LLVM,RISCV,3905,
LLVM,RISCV,3906,bool Is64Bit = TT.isArch64Bit();
LLVM,RISCV,3907,XLenVT = <STR_LIT>;
LLVM,RISCV,3908,
LLVM,RISCV,3909,return !<ISA_LIT>DisableUsingConstantPoolForLargeInts;
LLVM,RISCV,3910,
LLVM,RISCV,3911,
LLVM,RISCV,3912,if ( RVVVectorBitsMax < ( int ) ZvlLen ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ;
LLVM,RISCV,3913,
LLVM,RISCV,3914,unsigned Max = RVVVectorBitsMax;
LLVM,RISCV,3915,return getMaxLMULForFixedLengthVectorsImpl();
LLVM,RISCV,3916,hasStdExtV ( ) && <STR_LIT>;
LLVM,RISCV,3917,"ParseSubtargetFeatures(CPUName, FS);"
LLVM,RISCV,3918,Here is an example of what the initialization of the `Instr
LLVM,RISCV,3919,Here is an example of what the initialization of the `Instr
LLVM,RISCV,3920,"ParseSubtargetFeatures(CPUName, FS);"
LLVM,RISCV,3921,"ParseSubtargetFeatures(CPUName, FS);"
LLVM,RISCV,3922,Here are a few possibilities for what the next statement could be:
LLVM,RISCV,3923,
LLVM,RISCV,3924,
LLVM,RISCV,3925,"ParseSubtargetFeatures(CPUName, FS);"
LLVM,RISCV,3926,unsigned ELEN = hasVInstructionsI64() ? <NUM_LIT> : <NUM_LIT>;
LLVM,RISCV,3927,
LLVM,RISCV,3928,
LLVM,RISCV,3929,
LLVM,RISCV,3930,
LLVM,RISCV,3931,
LLVM,RISCV,3932,
LLVM,RISCV,3933,Here are a few possible next statements that could be executed:
LLVM,RISCV,3934,
LLVM,RISCV,3935,
LLVM,RISCV,3936,
LLVM,RISCV,3937,
LLVM,RISCV,3938,Here are a few possible next statements that could be executed:
LLVM,RISCV,3939,InstSelector->selectInstructions();
LLVM,RISCV,3940,"return is64Bit() ? ""64-bit"" : ""32-bit"";"
LLVM,RISCV,3941,"return is64Bit() ? ""64-bit"" : ""32-bit"";"
LLVM,RISCV,3942,"ParseSubtargetFeatures(CPUName, TuneCPUName, FS);"
LLVM,RISCV,3943,
LLVM,RISCV,3944,
LLVM,RISCV,3945,InstrInfo( *this );
LLVM,RISCV,3946,InstrInfo( *this );
LLVM,RISCV,3947,assert(hasVInstructions() && <STR_LIT>);
LLVM,RISCV,3948,"return PowerOf2Floor(std::max<unsigned>(std::min<unsigned>(RVVVectorELENMax, <NUM_LIT>), <NUM_LIT>));"
LLVM,RISCV,3949,
LLVM,RISCV,3950,
LLVM,RISCV,3951,
LLVM,RISCV,3952,
LLVM,RISCV,3953,
LLVM,RISCV,3954,return HasStdExtV || HasStdExtZve32x;
LLVM,RISCV,3955,
LLVM,RISCV,3956,return HasStdExtV || (HasStdExtZve32f && HasStdExtF);
LLVM,RISCV,3957,return HasStdExtV || (HasStdExtZve32f && HasStdExtF);
LLVM,RISCV,3958,return HasStdExtV || ( HasStdExtZve64d && HasStdExtD ) ;
LLVM,RISCV,3959,
LLVM,RISCV,3960,return HasStdExtV || HasStdExtZve64x;
LLVM,RISCV,3961,
LLVM,RISCV,3962,Here are some possible next statements:
LLVM,RISCV,3963,
LLVM,RISCV,3964,return HasExtXCoreVMac;
LLVM,RISCV,3965,return HasExtXCoreVMem;
LLVM,RISCV,3966,
LLVM,RISCV,3967,
LLVM,RISCV,3968,return HasStdExtV && hasStdExtZfh ( ) ;
LLVM,RISCV,3969,
LLVM,RISCV,3970,return HasStdExtV && hasStdExtD();
LLVM,RISCV,3971,
LLVM,RISCV,3972,
LLVM,RISCV,3973,
LLVM,RISCV,3974,RegBankInfo.reset(RBI);
LLVM,RISCV,3975,
LLVM,RISCV,3976,"Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);"
LLVM,RISCV,3977,
LLVM,RISCV,3978,
LLVM,RISCV,3979,
LLVM,RISCV,3980,
LLVM,RISCV,3981,
LLVM,RISCV,3982,
LLVM,RISCV,3983,
LLVM,RISCV,3984,return RVV
LLVM,RISCV,3985,"return PowerOf2Floor(std::max<unsigned>(std::min<unsigned>(RVVVectorELENMax, <NUM_LIT>), <NUM_LIT>));"
LLVM,RISCV,3986,return hasStdExtV ( ) ? MaxInterleaveFactor : <NUM_LIT> ;
LLVM,RISCV,3987,hasStdExtV ( ) && <STR_LIT>;
LLVM,RISCV,3988,"unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);"
LLVM,RISCV,3989,unsigned Min = RVVVectorBitsMin;
LLVM,RISCV,3990,
LLVM,RISCV,3991,
LLVM,RISCV,3992,"ParseSubtargetFeatures ( CPU , TuneCPU , FS ) ;"
LLVM,RISCV,3993,TuneCPU = CPU;
LLVM,RISCV,3994,InstSelector->selectInstructions();
LLVM,RISCV,3995,
LLVM,RISCV,3996,
LLVM,RISCV,3997,
LLVM,RISCV,3998,
LLVM,RISCV,3999,
LLVM,RISCV,4000,
LLVM,RISCV,4001,return The<ISA_LIT>32Target;
LLVM,RISCV,4002,
LLVM,RISCV,4003,RegisterTarget<Tri
LLVM,RISCV,4004,"LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;"
LLVM,RISCV,4005,LLVMInitialize<
LLVM,RISCV,4006,Ret += <STR_LIT>;
LLVM,RISCV,4007,
LLVM,RISCV,4008,
LLVM,RISCV,4009,RegisterTargetMachine<ISA_LIT>TargetMachine> C(The<ISA_LIT>Target);
LLVM,RISCV,4010,
LLVM,RISCV,4011,
LLVM,RISCV,4012,"TargetPassConfig(TM, PM);"
LLVM,RISCV,4013,"TargetPassConfig(TM, PM);"
LLVM,RISCV,4014,TLOF = make_unique<TargetObjectFile>();
LLVM,RISCV,4015,
LLVM,RISCV,4016,return new yaml::<ISA_LIT>MachineFunctionInfo(*MFI);
LLVM,RISCV,4017,
LLVM,RISCV,4018,return TargetTransformInfo <ISA_LIT>TargetMachine::getTargetTransformInfo(F);
LLVM,RISCV,4019,return getTargetTriple().isArch64Bit();
LLVM,RISCV,4020,PFS.MF.getInfo<ISA_LIT>MachineFunctionInfo>(YamlMFI).initializeBaseYamlFields();
LLVM,RISCV,4021,return <STR_LIT>;
LLVM,RISCV,4022,
LLVM,RISCV,4023,TargetPassConfig *config = TargetMachine::createPassConfig
LLVM,RISCV,4024,"return new TargetPassConfig( *this, PM );"
LLVM,RISCV,4025,return *CM;
LLVM,RISCV,4026,"In other words, if the condition `CM` is true, the code will return the value of `*CM`, and if the condition is false, the code will continue executing the next statement after the `if` block"
LLVM,RISCV,4027,
LLVM,RISCV,4028,"LLVMTargetMachine::LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), getEffectiveCodeModel(CM), OL)"
LLVM,RISCV,4029,TLOF = make_unique<ELFTargetObjectFile>();
LLVM,RISCV,4030,TLOF = make_unique<ELFTargetObjectFile>();
LLVM,RISCV,4031,
LLVM,RISCV,4032,return <STR_LIT>;
LLVM,RISCV,4033,TLOF = make_unique<TargetLoweringObjectFileELF>();
LLVM,RISCV,4034,TLOF = make_unique<TargetLoweringObjectFileELF>();
LLVM,RISCV,4035,return false;
LLVM,RISCV,4036,
LLVM,RISCV,4037,TM -> getOptLevel ( ) != CodeGenOpt :: None
LLVM,RISCV,4038,addPass(create<ISA_LIT>MergeBaseOffsetOptPass());
LLVM,RISCV,4039,LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) {
LLVM,RISCV,4040,initializeGlobalISel( * PR ) ;
LLVM,RISCV,4041,return true;
LLVM,RISCV,4042,return <STR_LIT> ;
LLVM,RISCV,4043,return <STR_LIT>;
LLVM,RISCV,4044,
LLVM,RISCV,4045,TLOF = std::make_unique<ELFTargetObjectFile>();
LLVM,RISCV,4046,initialize<ISA_LIT>CleanupVSETVLIPass ( * PR ) ;
LLVM,RISCV,4047,
LLVM,RISCV,4048,addPass(create<ISA_LIT>GatherScatterLoweringPass());
LLVM,RISCV,4049,return false;
LLVM,RISCV,4050,
LLVM,RISCV,4051,return false;
LLVM,RISCV,4052,
LLVM,RISCV,4053,
LLVM,RISCV,4054,TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableRedundantCopyElimination
LLVM,RISCV,4055,addPass ( create<ISA_LIT>ExpandAtomicPseudoPass ( ) ) ;
LLVM,RISCV,4056,addPass ( create<ISA_LIT>ExpandAtomicPseudoPass ( ) ) ;
LLVM,RISCV,4057,addPass(create<ISA_LIT>MergeBaseOffsetOptPass());
LLVM,RISCV,4058,addPass(create<ISA_LIT>MergeBaseOffsetOptPass());
LLVM,RISCV,4059,
LLVM,RISCV,4060,
LLVM,RISCV,4061,return true;
LLVM,RISCV,4062,
LLVM,RISCV,4063,return <STR_LIT>;
LLVM,RISCV,4064,return <STR_LIT>;
LLVM,RISCV,4065,I = SubtargetMap[Key];
LLVM,RISCV,4066,I = SubtargetMap[Key];
LLVM,RISCV,4067,return SrcAS == DstAS;
LLVM,RISCV,4068,return SrcAS == DstAS;
LLVM,RISCV,4069,initialize<ISA_LIT>PassName ( * PR ) ;
LLVM,RISCV,4070,addPass ( create<ISA_LIT>MakeCompressibleOptPass ( ) ) ;
LLVM,RISCV,4071,"A pre-emit pass is a pass that is executed before the emitter pass, which is responsible for generating the final output of the compiler. Pre-emit passes are typically used to perform tasks such as code optimization, dead code"
LLVM,RISCV,4072,
LLVM,RISCV,4073,RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( getThe<ISA_LIT>64Target ( ) ) ;
LLVM,RISCV,4074,TLOF = std::make_unique<ISA_LIT::ELFTargetObjectFile>();
LLVM,RISCV,4075,addPass(create<ISA_LIT>RemoveRedundancyVSETVLPass());
LLVM,RISCV,4076,addPass(create<ISA_LIT>RemoveRedundancyVSETVLPass());
LLVM,RISCV,4077,I = SubtargetMap[Key];
LLVM,RISCV,4078,initializeGlobalISel(PR);
LLVM,RISCV,4079,TargetPassConfig::addIRPasses(createCheriBoundAllocasPass());
LLVM,RISCV,4080,TargetPassConfig::addIRPasses(createCheriBoundAllocasPass());
LLVM,RISCV,4081,StringRef PurecapOptions = <STR_LIT>;
LLVM,RISCV,4082,return (<STR_LIT> + CapTypes + IntegerTypes + <STR_LIT> + PurecapOptions).str();
LLVM,RISCV,4083,return SrcAS == DstAS;
LLVM,RISCV,4084,TLOF = std::make_unique<ELFTargetObjectFile>();
LLVM,RISCV,4085,
LLVM,RISCV,4086,initialize<ISA_LIT>LowerVSETVLIPass ( * PR ) ;
LLVM,RISCV,4087,
LLVM,RISCV,4088,
LLVM,RISCV,4089,addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ;
LLVM,RISCV,4090,return false;
LLVM,RISCV,4091,
LLVM,RISCV,4092,addPass ( create<ISA_LIT>MergeBaseOffsetOptPass ( ) ) ;
LLVM,RISCV,4093,addPass(create<ISA_LIT>MergeBaseOffsetOptPass());
LLVM,RISCV,4094,TLOF = make_unique<ISA_LIT>ELFTargetObjectFile>();
LLVM,RISCV,4095,TLOF = make_unique<ISA_LIT>ELFTargetObjectFile>();
LLVM,RISCV,4096,I = SubtargetMap[Key];
LLVM,RISCV,4097,auto PR = PassRegistry::getPassRegistry();
LLVM,RISCV,4098,initializeGlobalISel(PR);
LLVM,RISCV,4099,addPass(create<ISA_LIT>PulpHWLoopsPass());
LLVM,RISCV,4100,
LLVM,RISCV,4101,TargetPassConfig::addISelPrepare();`
LLVM,RISCV,4102,addPass(createPromoteMemoryToRegisterPass());
LLVM,RISCV,4103,TargetPassConfig :: addPass ( create<ISA_LIT>OptimizeVSETVLUsesPass ( ) ) ;
LLVM,RISCV,4104,
LLVM,RISCV,4105,return RM.getValue();
LLVM,RISCV,4106,"this->TargetMachine::TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL);"
LLVM,RISCV,4107,"this->TargetMachine::TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL);"
LLVM,RISCV,4108,initAsmInfo();
LLVM,RISCV,4109,TLOF = make_unique<TargetObjectFile>();
LLVM,RISCV,4110,
LLVM,RISCV,4111,addPass ( create<ISA_LIT>ISelDag ( get
LLVM,RISCV,4112,addPass(createAtomicExpandPass());
LLVM,RISCV,4113,
LLVM,RISCV,4114,addPass(&BranchRelaxationPassID);
LLVM,RISCV,4115,addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ;
LLVM,RISCV,4116,
LLVM,RISCV,4117,return <STR_LIT>;
LLVM,RISCV,4118,"return new <ISA_LIT>PassConfig ( * this , PM ) ;"
LLVM,RISCV,4119,"return new <ISA_LIT>PassConfig ( * this , PM ) ;"
LLVM,RISCV,4120,PR->initialize<ISA_LIT>ExpandPseudoPass();
LLVM,RISCV,4121,RegisterTargetMachine<ISA_LIT>TargetMachine> X(getThe<ISA_LIT>32Target());
LLVM,RISCV,4122,"TargetPassConfig(TM,"
LLVM,RISCV,4123,"TargetPassConfig(TM,"
LLVM,RISCV,4124,TLOF = make_unique < <ISA_LIT>ELFTargetObjectFile > ( );
LLVM,RISCV,4125,TLOF = make_unique < <ISA_LIT>ELFTargetObjectFile > ( );
LLVM,RISCV,4126,
LLVM,RISCV,4127,
LLVM,RISCV,4128,
LLVM,RISCV,4129,
LLVM,RISCV,4130,if (Ty->isSized()) return false;
LLVM,RISCV,4131,return Size > <NUM_LIT> && Size <= SSThreshold;
LLVM,RISCV,4132,"if (Kind.isData() && isGlobalInSmallSection(GO, TM)) {"
LLVM,RISCV,4133,return RTM.getAlignmentForPreciseBounds(Size);
LLVM,RISCV,4134,"MCSection *section = getSectionForConstant(DL, Kind, C, Align);"
LLVM,RISCV,4135,"return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Align);"
LLVM,RISCV,4136,
LLVM,RISCV,4137,
LLVM,RISCV,4138,OS << <STR_LIT> << Attribute << <STR_LIT> << Twine ( Value ) << <STR_LIT>;
LLVM,RISCV,4139,OS << </STR_LIT> << Attribute << <STR_LIT> << Twine ( Value ) << </STR_LIT> ;
LLVM,RISCV,4140,OS << <STR_LIT> ;
LLVM,RISCV,4141,
LLVM,RISCV,4142,OS << <STR_LIT> ;
LLVM,RISCV,4143,OS << <STR_LIT> ;
LLVM,RISCV,4144,OS << <STR_LIT> ;
LLVM,RISCV,4145,
LLVM,RISCV,4146,OS << <STR_LIT> ;
LLVM,RISCV,4147,OS << <STR_LIT> ;
LLVM,RISCV,4148,OS << <STR_LIT> ;
LLVM,RISCV,4149,OS << <STR_LIT> .rvc;
LLVM,RISCV,4150,
LLVM,RISCV,4151,
LLVM,RISCV,4152,"emitAttribute(<STR_LIT>, <STR_LIT>);"
LLVM,RISCV,4153,OS << <STR_LIT> << Attribute << <STR_LIT> << String << <STR_LIT>;
LLVM,RISCV,4154,finishAttributeSection();
LLVM,RISCV,4155,
LLVM,RISCV,4156,
LLVM,RISCV,4157,
LLVM,RISCV,4158,
LLVM,RISCV,4159,
LLVM,RISCV,4160,OS.SetStreamer(S);
LLVM,RISCV,4161,OS.SetStreamer(S);
LLVM,RISCV,4162,Here is an example of what the next statement might look like: ```
LLVM,RISCV,4163,Here is an example of what the next statement might look like: ```
LLVM,RISCV,4164,assert(ABI != <STR_LIT> && <STR_LIT>);
LLVM,RISCV,4165,"OS << <STR_LIT> << ""CapMode"";"
LLVM,RISCV,4166,OS << <STR_LIT> ;
LLVM,RISCV,4167,
LLVM,RISCV,4168,"if (STI.hasFeature(""<STR_LIT>"")) Arch += ""<STR_LIT>"";"
LLVM,RISCV,4169,if (STI.hasFeature(<STR_LIT>)) Arch += <STR_LIT>;
LLVM,RISCV,4170,"emitAttribute(<STR_LIT>, <STR_LIT>);"
LLVM,RISCV,4171,"emitTextAttribute(<STR_LIT>, ISAInfo->toString());"
LLVM,RISCV,4172,"auto ParseResult = llvm::<STR_LIT>(XLen, FeatureVector);"
LLVM,RISCV,4173,
LLVM,RISCV,4174,"if (STI.hasFeature(""<STR_LIT>"")) Arch += ""<STR_L"
LLVM,RISCV,4175,
LLVM,RISCV,4176,
LLVM,RISCV,4177,
LLVM,RISCV,4178,"BaseCost = std::max(BaseCost, LT.first);"
LLVM,RISCV,4179,
LLVM,RISCV,4180,return Cost + (LT.first - <NUM_LIT>);
LLVM,RISCV,4181,
LLVM,RISCV,4182,"return getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);"
LLVM,RISCV,4183,
LLVM,RISCV,4184,return MaxVectorSizeInBits / <STR_LIT>;
LLVM,RISCV,4185,BaseCost = BaseCost + LT.first * VL;
LLVM,RISCV,4186,return TypeSize :: getScalable ( ST -> hasStdExtV ( ) ? <STR_LIT> : <NUM_LIT> ) ;
LLVM,RISCV,4187,
LLVM,RISCV,4188,unsigned <ISA_LIT>TTIImpl :: getRegUsage
LLVM,RISCV,4189,return LT.first * <NUM_LIT>;
LLVM,RISCV,4190,"return BaseT::getShuffleCost(Kind, Tp, Mask, Index, SubTp);"
LLVM,RISCV,4191,
LLVM,RISCV,4192,"Cost += TLI->getSpliceCost(DL, Tp, Index);"
LLVM,RISCV,4193,"LLVM_DEBUG(dbgs() << ""Cost: "" << Cost << "" Partial: "" << UP.Partial << ""\n"");"
LLVM,RISCV,4194,
LLVM,RISCV,4195,"return isLegalMaskedGatherScatter(DataType, Alignment);"
LLVM,RISCV,4196,return isLegalElementTypeForRVV(DataType->getScalarType());
LLVM,RISCV,4197,
LLVM,RISCV,4198,
LLVM,RISCV,4199,if (Alignment < DL.getTypeStoreSize(DataType->getScalarType()).getFixedSize()) return false;
LLVM,RISCV,4200,return false;
LLVM,RISCV,4201,
LLVM,RISCV,4202,"However, based on the name of the function and the parameters, it is likely that the function is checking whether a masked store operation is legal for the given data type and alignment. A masked store operation is a type of store operation that stores a value to memory while simultaneously masking out certain bits of the value, typically to avoid storing certain values"
LLVM,RISCV,4203,case RecurKind::Mul: case RecurKind::FMul: case RecurKind::UDiv: case RecurKind::SDiv: case RecurKind::FDiv: case RecurKind::URem: case RecurKind::SRem: case RecurKind::FRem:
LLVM,RISCV,4204,"In C++, a vector is a dynamic array that can grow or shrink in size as elements are added or removed. A scalable vector is a vector that can grow or shrink in size in a way that is proportional to the size of the vector. For example, if a vector has a capacity of"
LLVM,RISCV,4205,"In C++, a vector is a dynamic array that can grow or shrink in size as elements are added or removed. A scalable vector is a vector that can grow or shrink in size in a way that is proportional to the size of the vector. For example, if a vector has a capacity of"
LLVM,RISCV,4206,return TTI::TCC_Free;
LLVM,RISCV,4207,
LLVM,RISCV,4208,"if (isLegalMaskedLoadStore(DataType, Alignment)) { ... }"
LLVM,RISCV,4209,if (Alignment < DL.getTypeStoreSize(DataType->getScalarType()).getFixedSize()) return false;
LLVM,RISCV,4210,return TTI::TCC_Free;
LLVM,RISCV,4211,
LLVM,RISCV,4212,
LLVM,RISCV,4213,
LLVM,RISCV,4214,return false;
LLVM,RISCV,4215,return false;
LLVM,RISCV,4216,
LLVM,RISCV,4217,return false;
LLVM,RISCV,4218,
LLVM,RISCV,4219,return false;
LLVM,RISCV,4220,
LLVM,RISCV,4221,"In C++, a vector is a dynamic array that can grow or shrink in size as elements are added or removed. A scalable vector is a vector that can grow or shrink in size in a way that is proportional to the size of the vector. For example, if a vector has a capacity of"
LLVM,RISCV,4222,
LLVM,RISCV,4223,return ST -> hasStdExtV ( ) ? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ;
LLVM,RISCV,4224,return false;
LLVM,RISCV,4225,return false;
LLVM,RISCV,4226,Cost += getInstructionCost(I);
LLVM,RISCV,4227,"Cost = getInstructionCost(L, SE, UP, ORE);"
LLVM,RISCV,4228,return ST -> getMinRVVVectorSizeInBits ( ) ;
LLVM,RISCV,4229,return TypeSize::getFixed(ST->getXLen());
LLVM,RISCV,4230,
LLVM,RISCV,4231,const int BitWidth = Ty->getIntegerBitWidth();
LLVM,RISCV,4232,ImmArgIdx = <NUM_LIT>;
LLVM,RISCV,4233,Takes12BitImm = true;
LLVM,RISCV,4234,return TTI::TCC_Free;
LLVM,RISCV,4235,
LLVM,RISCV,4236,if (I.isTerminator()) return false;
LLVM,RISCV,4237,
LLVM,RISCV,4238,
LLVM,RISCV,4239,"return getIntImmCost(Imm, Ty);"
LLVM,RISCV,4240,
LLVM,RISCV,4241,"return divideCeil(Size, ST->getMinRVVVectorSizeInBits());"
LLVM,RISCV,4242,Here are a few possibilities:
LLVM,RISCV,4243,"Cost += getUserCost(&I, Operands, TargetTransformInfo::TCK_SizeAndLatency);"
LLVM,RISCV,4244,"return getRVVArithmeticReductionCost(Opcode, VTy, FMF, CostKind);"
LLVM,RISCV,4245,
LLVM,RISCV,4246,case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( std :: abs ( PowDiff ) <= <NUM_LIT> ) return <NUM_LIT> ; if ( Src -> isIntOrIntVectorTy ( ) ) return <NUM_LIT> ; return std :: abs ( PowDiff ) ; }
LLVM,RISCV,4247,
LLVM,RISCV,4248,
LLVM,RISCV,4249,return TypeSize :: getFixed ( ST -> hasStdExtV ( ) ? ST -> getMinRVVVectorSizeInBits ( ) : <NUM_LIT> ) ;
LLVM,RISCV,4250,case TargetTransformInfo :: RGK_FixedWidthVector :
LLVM,RISCV,4251,return false;
LLVM,RISCV,4252,return false;
LLVM,RISCV,4253,
LLVM,RISCV,4254,
LLVM,RISCV,4255,if ( Instruction :: isCommutative ( Opcode ) || Idx == ImmArgIdx ) {
LLVM,RISCV,4256,return false;
LLVM,RISCV,4257,
LLVM,RISCV,4258,if (Alignment < DL.getTypeStoreSize(DataType->getScalarType()).getFixedSize()) return false;
LLVM,RISCV,4259,
LLVM,RISCV,4260,return false;
LLVM,RISCV,4261,if (Opcode == Instruction::Gather || Opcode == Instruction::Scatter) {
LLVM,RISCV,4262,unsigned NumLoads = VTy -> getNumElements ( ) ;
LLVM,RISCV,4263,
LLVM,RISCV,4264,return TTI::TCC_Free;
LLVM,RISCV,4265,return BaseT::getMaxVScale();
LLVM,RISCV,4266,assert(isPowerOf2_32(TyWidth) && <STR_LIT>);
LLVM,RISCV,4267,
LLVM,RISCV,4268,
LLVM,RISCV,4269,
LLVM,RISCV,4270,
LLVM,RISCV,4271,
LLVM,RISCV,4272,
LLVM,RISCV,4273,
LLVM,ARC,0,
LLVM,ARC,1,
LLVM,ARC,2,"MCInstPrinter . printInst ( TmpInst , O ) ;"
LLVM,ARC,3,
LLVM,ARC,4,
LLVM,ARC,5,MF.ensureAlignment(Align(<NUM_LIT>));
LLVM,ARC,6,"MCInstLowering(OutContext, *this);"
LLVM,ARC,7,"MCInstLowering(OutContext, *this);"
LLVM,ARC,8,"MCInstPrinter::emitInstruction(MI, O);"
LLVM,ARC,9,
LLVM,ARC,10,"return ""MyPass"";"
LLVM,ARC,11,
LLVM,ARC,12,MF.ensureAlignment(Align(<NUM_LIT>));
LLVM,ARC,13,
LLVM,ARC,14,"BuildMI(MI->getParent(), MI, MI->getDebugLoc(), TII->get(getBRccForPseudo(MI))).addMBB(MI->getOperand(<NUM_LIT>).getMBB()).addReg(MI->getOperand(<NUM_LIT>).getReg()).add(MI->getOperand(<NUM_LIT>)).addImm(getCCForBRcc(MI->getOperand(<NUM_"
LLVM,ARC,15,
LLVM,ARC,16,
LLVM,ARC,17,MaxSize += Size;
LLVM,ARC,18,"BranchToPCList.push_back(std::make_pair(&MI, PC));"
LLVM,ARC,19,return PassRegistry::getPassRegistry()->getPass<ISA_LIT>BranchFinalizePass()
LLVM,ARC,20,return new <ISA_LIT>BranchFinalize();
LLVM,ARC,21,
LLVM,ARC,22,
LLVM,ARC,23,
LLVM,ARC,24,
LLVM,ARC,25,MI -> eraseFromParent ( ) ;
LLVM,ARC,26,"However, based on the syntax and structure of the code, it appears that the next statement after the first `BuildMI` call is likely to be another `BuildMI` call, possibly with a different set of parameters. The second `BuildMI` call is also likely to be followed by a call to the `addReg` method, and then a call to"
LLVM,ARC,27,Here is a possible next
LLVM,ARC,28,Branches.push_back(&MI);
LLVM,ARC,29,
LLVM,ARC,30,"DecodeSymbolicOperandOff(Inst, Address, SignExtend32<B>(InsnS), Decoder);"
LLVM,ARC,31,
LLVM,ARC,32,
LLVM,ARC,33,"return DecodeGPR32RegisterClass ( Inst , RegNo , Address , Decoder ) ;"
LLVM,ARC,34,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,ARC,35,LLVM_DEBUG(dbgs() << <STR_LIT>);
LLVM,ARC,36,Inst.addOperand(MCOperand::createReg(DstA));
LLVM,ARC,37,"DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder);"
LLVM,ARC,38,
LLVM,ARC,39,Inst.addOperand(MCOperand::createReg(R));
LLVM,ARC,40,Inst . addOperand ( MCOperand :: createReg ( RegNum ) ) ;
LLVM,ARC,41,Inst.addOperand(MCOperand::createReg(RegNum));
LLVM,ARC,42,"static_assert ( B > <NUM_LIT> , <STR_LIT> ) ;"
LLVM,ARC,43,
LLVM,ARC,44,"return (nullptr != Disassembler && Disassembler->tryAddingSymbolicOperand(Inst, Value, Address, true, <NUM_LIT>, atLeast));"
LLVM,ARC,45,
LLVM,ARC,46,
LLVM,ARC,47,
LLVM,ARC,48,if (Success == Result) { LLVM_DEBUG(dbgs() << <STR_LIT>); return Result; }
LLVM,ARC,49,"LLVM_DEBUG(dbgs() << ""Decoding instruction at address "" << Address << "" with size "" << Size << "" and opcode "" << Instr.getOpcode() << ""\n"");"
LLVM,ARC,50,LLVMInitialize<ISA_LIT>Disassembler();
LLVM,ARC,51,Inst.addOperand(MCOperand::createReg(DstB));
LLVM,ARC,52,Inst.addOperand(MCOperand::createImm(U6Field));
LLVM,ARC,53,"return Decoder.decodeRegister(Inst, Address, Value);"
LLVM,ARC,54,Inst.addOperand(MCOperand::createImm(Result));
LLVM,ARC,55,"Field U7 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;"
LLVM,ARC,56,
LLVM,ARC,57,
LLVM,ARC,58,
LLVM,ARC,59,static const uint64_t AtLeast = <NUM_LIT>;
LLVM,ARC,60,
LLVM,ARC,61,
LLVM,ARC,62,
LLVM,ARC,63,
LLVM,ARC,64,
LLVM,ARC,65,Inst.addOperand(MCOperand::createReg(Reg));
LLVM,ARC,66,return MCDisassembler :: Fail;
LLVM,ARC,67,
LLVM,ARC,68,
LLVM,ARC,69,
LLVM,ARC,70,
LLVM,ARC,71,return MCDisassembler::Success;
LLVM,ARC,72,SrcC = decodeCField(Insn);
LLVM,ARC,73,Inst.addOperand(MCOperand::createImm(LImm));
LLVM,ARC,74,Insn64 = (Bytes[<NUM_LIT>] & <NUM_LIT>) >> <NUM_LIT>;
LLVM,ARC,75,if (Result == MCDisassembler::Success) {
LLVM,ARC,76,Inst.addOperand(MCOperand::createReg(DstA));
LLVM,ARC,77,"DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder);"
LLVM,ARC,78,"Field::DecodeMoveHRegInstruction(Inst, Insn, Address, Decoder);"
LLVM,ARC,79,
LLVM,ARC,80,"if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn48 ; if ( ! readInstruction48 ( Bytes , Address , Size , Insn48 ) ) return Fail ; Result = decodeInstruction ( DecoderTable48 , Instr , Insn48 , Address , this , STI ) ; if ( Success == Result ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Result ; } DEBUG ( dbgs ( ) << <ST"
LLVM,ARC,81,"MCDisassembler::MCDisassembler(STI, Ctx)"
LLVM,ARC,82,"MCDisassembler::MCDisassembler(STI, Ctx)"
LLVM,ARC,83,"return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo ( ) ) ;"
LLVM,ARC,84,
LLVM,ARC,85,
LLVM,ARC,86,return Insn & 0
LLVM,ARC,87,
LLVM,ARC,88,Inst.addOperand(MCOperand::createReg(DstB));
LLVM,ARC,89,Inst.addOperand(MCOperand::createImm(InsnS < max ? static_cast<int>(InsnS) : -<NUM_LIT>));
LLVM,ARC,90,const unsigned max = ( <NUM_LIT> << B ) - <NUM_LIT> ;
LLVM,ARC,91,
LLVM,ARC,92,
LLVM,ARC,93,"LLVM_DEBUG(dbgs() << ""Register number is out of range"");"
LLVM,ARC,94,
LLVM,ARC,95,Inst.addOperand(MCOperand::createImm((uint32_t)(Insn >> <NUM_LIT>)));
LLVM,ARC,96,
LLVM,ARC,97,Inst.addOperand(MCOperand::createImm(Value));
LLVM,ARC,98,Inst.addOperand(MCOperand::createImm(SignExtend32<B>(maskTrailingOnes<decltype(InsnS)>(B) & InsnS)));
LLVM,ARC,99,
LLVM,ARC,100,Inst.addOperand(MCOperand::createImm(U6));
LLVM,ARC,101,
LLVM,ARC,102,Inst.addOperand(MCOperand::createImm(LImm));
LLVM,ARC,103,"return (nullptr != Decoder && Decoder->tryAddingSymbolicOperand(Inst, Value, Address, true, <NUM_LIT>, AtLeast));"
LLVM,ARC,104,uint64_t NextAddress = Address + Offset;
LLVM,ARC,105,Inst.addOperand(MCOperand::createImm(Offset));
LLVM,ARC,106,"if ( !readInstruction32(Bytes, Address, Size, Insn32) ) { return Fail; }"
LLVM,ARC,107,Here are a few possibilities:
LLVM,ARC,108,
LLVM,ARC,109,
LLVM,ARC,110,Size = 48;
LLVM,ARC,111,
LLVM,ARC,112,
LLVM,ARC,113,
LLVM,ARC,114,
LLVM,ARC,115,
LLVM,ARC,116,MBBI = NMBBI;
LLVM,ARC,117,Some possible next statements could include:
LLVM,ARC,118,Some possible next statements could include:
LLVM,ARC,119,
LLVM,ARC,120,
LLVM,ARC,121,
LLVM,ARC,122,
LLVM,ARC,123,
LLVM,ARC,124,
LLVM,ARC,125,
LLVM,ARC,126,
LLVM,ARC,127,if (Amt != <NUM_LIT>) {
LLVM,ARC,128,
LLVM,ARC,129,"BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(""<STR_LIT>"")) .addExternalSymbol(load_funclet_name[Last - <STR_LIT>]) .addReg(<STR_LIT>, RegState::Implicit | RegState::Kill);"
LLVM,ARC,130,"CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));"
LLVM,ARC,131,"RegInfo->eliminateFrameIndex(MF, RS, MF.getFrameInfo());"
LLVM,ARC,132,return false;
LLVM,ARC,133,for (unsigned i = 0; i < Last; i++) {
LLVM,ARC,134,for (auto Reg : CSI) {
LLVM,ARC,135,
LLVM,ARC,136,"BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(<STR_LIT>), <STR_LIT>).addExternalSymbol(load_funclet_name[Last - <STR_LIT>]).addReg(<STR_LIT>, RegState::Implicit | RegState::Kill);"
LLVM,ARC,137,"LLVM_DEBUG(dbgs() << ""Creating stack frame for function "" << MF.getName() << "":\n"");"
LLVM,ARC,138,Opc = IsAdd ? <STR_LIT> : <STR_LIT> ;
LLVM,ARC,139,"BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr).addReg(StackPtr).addImm(AbsAmount);"
LLVM,ARC,140,AdjOp = Positive ? TII.getAdjustSpUpOpcode() : TII.getAdjustSpDownOpcode();
LLVM,ARC,141,return false;
LLVM,ARC,142,"BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlags(MachineInstr::FrameSetup);"
LLVM,ARC,143,"RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false);"
LLVM,ARC,144,const TargetRegisterClass * RC = & <STR_LIT> ;
LLVM,ARC,145,LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getParent ( ) -> getName ( ) << <STR_LIT> ) ;
LLVM,ARC,146,TargetFrameLowering::StackGrowsDown
LLVM,ARC,147,TargetFrameLowering::StackGrowsDown
LLVM,ARC,148,for (auto &I : CSI) {
LLVM,ARC,149,
LLVM,ARC,150,return MBB.erase(I);
LLVM,ARC,151,"BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(""<STR_LIT>"")) .addReg(""<STR_LIT>"") .addReg(""<STR_LIT>"") .addImm(StackSize - AmountAboveFunclet);"
LLVM,ARC,152,"BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(""<STR_LIT>"")).addReg(""<STR_LIT>"").addReg(""<STR_LIT>"").addImm(StackSize - AmountAboveFunclet);"
LLVM,ARC,153,AdjOp = Positive ? <STR_LIT> : <STR_LIT>;
LLVM,ARC,154,"AdjOp = TII.getAdjustmentOpcode(Amount, Positive);"
LLVM,ARC,155,DEBUG ( dbgs ( ) << <STR_LIT> << RegScavFI << <STR_LIT> ) ;
LLVM,ARC,156,if (MFI.hasStackObjects()) {
LLVM,ARC,157,return true;
LLVM,ARC,158,unsigned Last = determineLastCalleeSave(CSI);
LLVM,ARC,159,
LLVM,ARC,160,return HasFP;
LLVM,ARC,161,
LLVM,ARC,162,int ScalarAlloc = MF.getFrameInfo().getStackSize();`
LLVM,ARC,163,ST = st;
LLVM,ARC,164,ST = st;
LLVM,ARC,165,"MFI.setObjectOffset(I.getFrameIdx(), CurOffset);"
LLVM,ARC,166,"TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);"
LLVM,ARC,167,SavedRegs.set(<STR_LIT>)
LLVM,ARC,168,
LLVM,ARC,169,
LLVM,ARC,170,
LLVM,ARC,171,"BuildMI(MBB, MBBI, dl, TII->get(Opc), Reg).addReg(Reg, RegState::Kill).addImm(NumBytes);"
LLVM,ARC,172,AbsAmount = AbsAmount % <NUM_LIT>;
LLVM,ARC,173,
LLVM,ARC,174,
LLVM,ARC,175,return HasFP;
LLVM,ARC,176,return HasFP;
LLVM,ARC,177,LLVM_DEBUG(dbgs() << <STR_LIT> << MFI.getStackSize() << <STR_LIT>);
LLVM,ARC,178,LLVM_DEBUG(dbgs() << <STR_LIT> << MBB.getParent()->getName() << <STR_LIT>);
LLVM,ARC,179,"O << "" "";"
LLVM,ARC,180,return <STR_LIT>;
LLVM,ARC,181,
LLVM,ARC,182,
LLVM,ARC,183,"However, based on the syntax and the context of the code, it is likely that the next statement will be a call to the `CondCodeToString` function, passing in the result of the `getOperand` method as an argument. The `getOperand` method is called on the `MI"
LLVM,ARC,184,"printInstruction(MI, Address, O);"
LLVM,ARC,185,
LLVM,ARC,186,"printOperand(MI, OpNum, O);"
LLVM,ARC,187,
LLVM,ARC,188,case <STR_LIT> : return <STR_LIT> ;
LLVM,ARC,189,Offset = CE->evaluateAsAbsolute ( ) ;
LLVM,ARC,190,return BadConditionCode ( BRCC ) ;
LLVM,ARC,191,
LLVM,ARC,192,
LLVM,ARC,193,"InstPrinter::InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {"
LLVM,ARC,194,"InstPrinter::InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {"
LLVM,ARC,195,DEBUG ( dbgs ( ) << <STR_LIT> << cc << <STR_LIT> ) ;
LLVM,ARC,196,return <STR_LIT>;
LLVM,ARC,197,Here is an example of what
LLVM,ARC,198,Op.isImm() && <STR_LIT>
LLVM,ARC,199,OS << '+' << Offset;
LLVM,ARC,200,"printInstruction(MI, O);"
LLVM,ARC,201,"printInstruction(MI, O);"
LLVM,ARC,202,"printRegName(O, base.getReg());"
LLVM,ARC,203,O << Op.getImm();
LLVM,ARC,204,"printImmName(O, Op.getImm());"
LLVM,ARC,205,const MCOperand &Operand = MI->getOperand(OpNum);
LLVM,ARC,206,Op.isImm() && <STR_LIT>
LLVM,ARC,207,
LLVM,ARC,208,
LLVM,ARC,209,if (CantAnalyze) return false;
LLVM,ARC,210,"MachineMemOperand *MMO = MFI.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FrameIndex), MachineMemOperand::MOLoad, MFI."
LLVM,ARC,211,
LLVM,ARC,212,MMO->setOffset(MFI.getObjectOffset(FrameIndex));
LLVM,ARC,213,
LLVM,ARC,214,MMO->setAlignment(Align);
LLVM,ARC,215,
LLVM,ARC,216,
LLVM,ARC,217,
LLVM,ARC,218,
LLVM,ARC,219,return false;
LLVM,ARC,220,return true;
LLVM,ARC,221,
LLVM,ARC,222,
LLVM,ARC,223,if (Cond.empty()) {
LLVM,ARC,224,
LLVM,ARC,225,
LLVM,ARC,226,
LLVM,ARC,227,RI.init ( ST );
LLVM,ARC,228,RI.init ( ST );
LLVM,ARC,229,
LLVM,ARC,230,
LLVM,ARC,231,MIB.add(Cond[i]);
LLVM,ARC,232,"return BuildMI(MBB, MI, DL, get(<STR_LIT>), Reg).addImm(Value).getInstr();"
LLVM,ARC,233,MMO->setDebugLoc(DL);
LLVM,ARC,234,return false;
LLVM,ARC,235,"LLVM_DEBUG(dbgs() << <STR_LIT> << printReg(SrcReg, TRI) << <STR_LIT> << FrameIndex << <STR_LIT>);"
LLVM,ARC,236,
LLVM,ARC,237,
LLVM,ARC,238,MachineFrameInfo &MFI = MF
LLVM,ARC,239,"<ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , ST ( ST ) , RI ( ST ) {"
LLVM,ARC,240,"<ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , ST ( ST ) , RI ( ST ) {"
LLVM,ARC,241,MachineInstr &InstToDelete = *DI;
LLVM,ARC,242,
LLVM,ARC,243,
LLVM,ARC,244,
LLVM,ARC,245,
LLVM,ARC,246,
LLVM,ARC,247,
LLVM,ARC,248,return MI.getDesc().get
LLVM,ARC,249,return MI . getDesc ( ) . getSize ( ) ;
LLVM,ARC,250,
LLVM,ARC,251,
LLVM,ARC,252,
LLVM,ARC,253,MIB.add(Cond[i]);
LLVM,ARC,254,
LLVM,ARC,255,
LLVM,ARC,256,return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;
LLVM,ARC,257,
LLVM,ARC,258,
LLVM,ARC,259,return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT>;
LLVM,ARC,260,return Opc == <STR_LIT> ;
LLVM,ARC,261,
LLVM,ARC,262,return Op.isImm() && Op.getImm() == <NUM_LIT>;
LLVM,ARC,263,return Op.isImm() && Op.getImm() == <NUM_LIT>;
LLVM,ARC,264,
LLVM,ARC,265,"MachineInstr *Instr = new MachineInstr(dl, Reg, Value);"
LLVM,ARC,266,
LLVM,ARC,267,return false;
LLVM,ARC,268,
LLVM,ARC,269,Here is an example of what the next statement might look like:
LLVM,ARC,270,Here is an example of what the next statement might look like:
LLVM,ARC,271,
LLVM,ARC,272,"* The function is named `create<ISA_LIT>ISelDag`, where `ISA_LIT` is a placeholder for the name of the instruction set architecture (ISA) being targeted."
LLVM,ARC,273,
LLVM,ARC,274,
LLVM,ARC,275,RHSC = -RHSC;
LLVM,ARC,276,return false;
LLVM,ARC,277,
LLVM,ARC,278,
LLVM,ARC,279,"Offset = CurDAG->getTargetConstant(<NUM_LIT>, SDLoc(Addr), <STR_LIT>);"
LLVM,ARC,280,if (Base.getOpcode() == <STR_LIT>) {
LLVM,ARC,281,
LLVM,ARC,282,
LLVM,ARC,283,
LLVM,ARC,284,"Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), <STR_LIT>);"
LLVM,ARC,285,"RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ;"
LLVM,ARC,286,
LLVM,ARC,287,
LLVM,ARC,288,llvm_unreachable(<STR_LIT>)
LLVM,ARC,289,"Based on the pattern of the previous cases, it is likely that the next statement will be: case <STR_LIT>: return LowerGLOBAL_VAR (Op, DAG);"
LLVM,ARC,290,
LLVM,ARC,291,
LLVM,ARC,292,
LLVM,ARC,293,
LLVM,ARC,294,
LLVM,ARC,295,CCInfo.SetCallingConv(CallConv);
LLVM,ARC,296,return nullptr;
LLVM,ARC,297,
LLVM,ARC,298,case <STR_LIT> : return <STR_LIT> ;
LLVM,ARC,299,Some possible next statements could include:
LLVM,ARC,300,
LLVM,ARC,301,"SDValue Call = DAG.getNode(<STR_LIT>, dl, NodeTys, Ops);"
LLVM,ARC,302,
LLVM,ARC,303,
LLVM,ARC,304,MFI.setFrameAddress(ARI.getFrameAddress());
LLVM,ARC,305,"However, based on the names of the methods and the context of the code, it is likely that the next statement will be a call to the `getNode` method, passing in the `GA` value as the first argument, and the `dl` value as the second argument. The `getNode` method is likely to return a"
LLVM,ARC,306,Here are a few possibilities for what the next statement could be:
LLVM,ARC,307,"return DAG.getNode(<STR_LIT>, SDLoc(N), <STR_LIT>, GA);"
LLVM,ARC,308,"Based on the pattern of the previous cases, it is likely that the next statement will be: case <STR_LIT>: return LowerGLOBAL_VAR (Op, DAG);"
LLVM,ARC,309,int Offset = VA.getLocMemOffset();`
LLVM,ARC,310,"Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);"
LLVM,ARC,311,
LLVM,ARC,312,"SDValue SR = DAG.getNode(<STR_LIT>, dl, <STR_LIT>, LS, DAG.getConstant(<NUM_LIT> - Width, dl, <STR_LIT>));"
LLVM,ARC,313,return Op;
LLVM,ARC,314,
LLVM,ARC,315,if (CI->isTailCall()) {
LLVM,ARC,316,return false;
LLVM,ARC,317,"SDValue <ISA_LIT>TargetLowering :: PerformDAGCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { return { } ;"
LLVM,ARC,318,
LLVM,ARC,319,MF.setAlignment(<NUM_LIT>);
LLVM,ARC,320,"* `explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF )`: This is the constructor of the `FunctionInfo` class, which takes a reference to a `MachineFunction` object as its parameter. The `explicit` keyword is used to indicate that this constructor can only be called with an explicit argument list, and not through implicit conversion."
LLVM,ARC,321,"* `explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF )`: This is the constructor of the `FunctionInfo` class, which takes a reference to a `MachineFunction` object as its parameter. The `explicit` keyword is used to indicate that this constructor can only be called with an explicit argument list, and not through implicit conversion."
LLVM,ARC,322,MF.setAlignment(Align(<NUM_LIT>));
LLVM,ARC,323,
LLVM,ARC,324,
LLVM,ARC,325,
LLVM,ARC,326,return VarArgsFrameIndex;
LLVM,ARC,327,ReturnStackOffsetSet = true;
LLVM,ARC,328,
LLVM,ARC,329,
LLVM,ARC,330,
LLVM,ARC,331,
LLVM,ARC,332,
LLVM,ARC,333,Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ;
LLVM,ARC,334,AllowAtInName = true ;
LLVM,ARC,335,OutMI.addOperand(MCOp);
LLVM,ARC,336,
LLVM,ARC,337,
LLVM,ARC,338,
LLVM,ARC,339,OutMI
LLVM,ARC,340,"return LowerSymbolOperand(MO, MOTy, Offset);"
LLVM,ARC,341,return MCOperand::createReg(MO.getReg());
LLVM,ARC,342,
LLVM,ARC,343,return MAI;
LLVM,ARC,344,TargetRegistry::
LLVM,ARC,345,return X;
LLVM,ARC,346,MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;
LLVM,ARC,347,Here is an example of what the next statement might look like: ```
LLVM,ARC,348,Here is an example of what the next statement might look like: ```
LLVM,ARC,349,return MAI;
LLVM,ARC,350,MAI->addInitialFrameState(Inst);
LLVM,ARC,351,"return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;"
LLVM,ARC,352,"return new <ISA_LIT>MCInstPrinter(T, SyntaxVariant, MAI, MII, MRI);"
LLVM,ARC,353,
LLVM,ARC,354,MCRegisterInfo *
LLVM,ARC,355,"return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;"
LLVM,ARC,356,
LLVM,ARC,357,
LLVM,ARC,358,"TargetRegistry::RegisterMCAsmInfo(The<ISA_LIT>Target, create<ISA_LIT>"
LLVM,ARC,359,"Ldst.addOperand(MachineOperand::CreateReg(NewBase, true));"
LLVM,ARC,360,Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
LLVM,ARC,361,Result = Add . getNextNode ( ) ;
LLVM,ARC,362,"LLVM_DEBUG(dbgs() << ""Found a load/store instruction that can be optimized\n"");"
LLVM,ARC,363,Result = nullptr;
LLVM,ARC,364,Result = nullptr;
LLVM,ARC,365,
LLVM,ARC,366,if (MBB->empty()) {
LLVM,ARC,367,
LLVM,ARC,368,if (DUMP_AFTER()) MF.dump();
LLVM,ARC,369,
LLVM,ARC,370,
LLVM,ARC,371,LLVM_DEBUG(dbgs() << <STR_LIT> << *First << <STR_LIT> << *Last << <STR_LIT>);
LLVM,ARC,372,if ( MI -> isDebugValue ( ) ) continue ;
LLVM,ARC,373,Amount = Sign * MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;
LLVM,ARC,374,Here are a few possibilities for what the next statement could be:
LLVM,ARC,375,Here are a few possibilities for what the next statement could be:
LLVM,ARC,376,"if (isLoadStoreThatCanHandleDisplacement(AII, *MI, -NewOffset)) continue;"
LLVM,ARC,377,
LLVM,ARC,378,Result = First;
LLVM,ARC,379,for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) {
LLVM,ARC,380,if (MI->isDebugValue()) continue;
LLVM,ARC,381,
LLVM,ARC,382,Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
LLVM,ARC,383,
LLVM,ARC,384,
LLVM,ARC,385,NewOffset += MO.getImm();
LLVM,ARC,386,
LLVM,ARC,387,MachineFunctionPass
LLVM,ARC,388,MachineFunctionPass
LLVM,ARC,389,return OPTADDRMODE_DESC;
LLVM,ARC,390,In the second case
LLVM,ARC,391,"So, the next statement will likely be something like:"
LLVM,ARC,392,"For example, if the `NUM_LIT` template parameter is set to 1"
LLVM,ARC,393,"For example, if the `NUM_LIT` template parameter is set to 1"
LLVM,ARC,394,return isInt < <NUM_LIT> > ( Off );
LLVM,ARC,395,
LLVM,ARC,396,"return dominatesAllUsesOf(Ldst, R, MDT, MRI);"
LLVM,ARC,397,if (Res) {
LLVM,ARC,398,MI = std::prev(Res->getIterator());
LLVM,ARC,399,bool <ISA_LIT>OptAddrMode :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; AST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AII = AST -> getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ;
LLVM,ARC,400,for (auto &MBB : MF) Changed |= processBasicBlock(MBB);
LLVM,ARC,401,
LLVM,ARC,402,Offset = StackSize + Offset;
LLVM,ARC,403,
LLVM,ARC,404,
LLVM,ARC,405,"However, based on the name of the method and the fact that it is a member function of the `RegisterInfo` class, it is likely that the method returns a register that is used as a frame pointer in the machine function. The `MachineFunction` class is a part of the LLVM compiler infrastructure and represents a function in the machine code level. The `RegisterInfo"
LLVM,ARC,406,
LLVM,ARC,407,
LLVM,ARC,408,* `ISA_LIT` is a macro that expands to a string literal representing the name of the instruction set architecture (ISA) being targeted.
LLVM,ARC,409,* `ISA_LIT` is a macro that expands to a string literal representing the name of the instruction set architecture (ISA) being targeted.
LLVM,ARC,410,"MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);"
LLVM,ARC,411,
LLVM,ARC,412,case <STR_LIT> : assert ( ( Offset % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ;
LLVM,ARC,413,<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {
LLVM,ARC,414,<ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {
LLVM,ARC,415,
LLVM,ARC,416,
LLVM,ARC,417,
LLVM,ARC,418,
LLVM,ARC,419,
LLVM,ARC,420,Register frameRegister = MF.getFrameRegister();
LLVM,ARC,421,
LLVM,ARC,422,
LLVM,ARC,423,
LLVM,ARC,424,return true;
LLVM,ARC,425,return true;
LLVM,ARC,426,
LLVM,ARC,427,return true;
LLVM,ARC,428,InstrInfo.init(this);
LLVM,ARC,429,InstrInfo.init(this);
LLVM,ARC,430,* `Subtarget` is a class that inherits from `GenSubtargetInfo` and `FrameLowering`.
LLVM,ARC,431,* `Subtarget` is a class that inherits from `GenSubtargetInfo` and `FrameLowering`.
LLVM,ARC,432,
LLVM,ARC,433,
LLVM,ARC,434,
LLVM,ARC,435,
LLVM,ARC,436,
LLVM,ARC,437,
LLVM,ARC,438,return &InstrInfo.getRegisterInfo();
LLVM,ARC,439,return &TSInfo;
LLVM,ARC,440,
LLVM,ARC,441,
LLVM,ARC,442,return Xnorm;
LLVM,ARC,443,
LLVM,ARC,444,The<ISA_LIT>Target.setTriple(Triple::normalize(ISA_LIT));
LLVM,ARC,445,
LLVM,ARC,446,
LLVM,ARC,447,
LLVM,ARC,448,initAsmInfo();
LLVM,ARC,449,return CM.orElse(new CodeModel.Model());
LLVM,ARC,450,"In other words, if the condition `CM` is true, the code will return the value of `*CM`, and if the condition is false, the code will continue executing the next statement after the `if` block"
LLVM,ARC,451,
LLVM,ARC,452,
LLVM,ARC,453,
LLVM,ARC,454,"A pre-emit pass is a pass that is executed before the emitter pass, which is responsible for generating the final output of the compiler. Pre-emit passes are typically used to perform tasks such as code optimization, dead code"
LLVM,ARC,455,"A pre-emit pass is a pass that is executed before the emitter pass, which is responsible for generating the final output of the compiler. Pre-emit passes are typically used to perform tasks such as code optimization, dead code"
LLVM,ARC,456,"TargetPassConfig(TM,"
LLVM,ARC,457,"TargetPassConfig(TM,"
LLVM,ARC,458,initAsmInfo();
LLVM,ARC,459,
LLVM,ARC,460,"return new <ISA_LIT>PassConfig ( * this , PM ) ;"
LLVM,ARC,461,TargetLoweringObjectFile * getObjFileLowering ( ) const override {
LLVM,ARC,462,return * RM;
LLVM,ARC,463,"However, based on the name of the method and the fact that it is declared as `const`, it is likely that the method returns a pointer to a `Subtarget` object that is associated with the `Function` object passed as an argument. The `Subtarget` object may contain information about the target architecture and the specific subtarget (e.g., CPU model) that the"
LLVM,ARC,464,"However, based on the name of the method and the fact that it is declared as `const`, it is likely that the method returns a pointer to a `Subtarget` object that is associated with the `Function` object passed as an argument. The `Subtarget` object may contain information about the target architecture and the specific subtarget (e.g., CPU model) that the"
LLVM,ARC,465,
LLVM,ARC,466,
LLVM,ARC,467,
LLVM,ARC,468,BaseT::BaseT(std::move(static_cast<BaseT&>(Arg)));
LLVM,ARC,469,BaseT::BaseT(std::move(static_cast<BaseT&>(Arg)));
LLVM,ARC,470,
LLVM,ARC,471,