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README.md
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---
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# OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection
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### Introduction
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OriGen is a fine-tuned lora model designed for Verilog code generation. It is trained on top of DeepSeek Coder 7B using datasets generated from code-to-code augmentation and self-reflection.
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**Repository:** [pku-liang/OriGen](https://github.com/pku-liang/OriGen)
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### Evaluation Results
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<img src="figures/evaluation.png" alt="evaluation" width="1000"/>
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### Quick Start
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```python
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from transformers import AutoModelForCausalLM, AutoTokenizer, TextStreamer
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import torch
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from peft import PeftModel
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model_name = "deepseek-ai/deepseek-coder-7b-instruct-v1.5"
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tokenizer = AutoTokenizer.from_pretrained(model_name)
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model = AutoModelForCausalLM.from_pretrained(
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model_name,
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low_cpu_mem_usage=True,
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torch_dtype=torch.float16,
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attn_implementation="flash_attention_2",
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device_map="auto",
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)
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model = PeftModel.from_pretrained(model, model_id="henryen/OriGen")
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model.eval()
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streamer = TextStreamer(tokenizer, skip_prompt=True, skip_special_tokens=True)
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prompt = "### Instruction: Please act as a professional Verilog designer. and provide Verilog code based on the given instruction. Generate a concise Verilog module for a 8 bit full adder, don't include any unnecessary code.\n### Response: "
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inputs = tokenizer(prompt, return_tensors="pt").to("cuda")
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outputs = model.generate(
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**inputs,
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max_new_tokens=1000,
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do_sample=False,
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temperature=0,
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eos_token_id=tokenizer.eos_token_id,
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pad_token_id=tokenizer.pad_token_id,
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streamer=streamer
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)
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```
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### Paper
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**Arxiv:** https://arxiv.org/abs/2407.16237
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Please cite our paper if you use this model.
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```
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@article{2024origen,
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title={OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection},
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author={Cui, Fan and Yin, Chenyang and Zhou, Kexing and Xiao, Youwei and Sun, Guangyu and Xu, Qiang and Guo, Qipeng and Song, Demin and Lin, Dahua and Zhang, Xingcheng and others},
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journal={arXiv preprint arXiv:2407.16237},
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year={2024}
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}
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```
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figures/evaluation.png
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