nyu-dice-lab
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Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GT-7B

Text Generation

text-generation-inference

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Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GT-7B

Commit History

Upload tokenizer

dc0cfda
verified

wilyub commited on May 13

Upload Qwen2ForCausalLM

7143447
verified

wilyub commited on May 13

initial commit

eb0b2f8
verified

wilyub commited on May 13