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rtl-llm

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charleshong3  updated a model about 1 month ago
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-vhdl-gs16-batch16
charleshong3  published a model about 1 month ago
rtl-llm/qwen2.5coder-7b-origen-verilog-vhdl-vhdl-gs16-batch16
charleshong3  updated a model about 1 month ago
rtl-llm/qwen2.5coder-7b-origen-vhdl-vhdl-verilog-chisel-gs16
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Charles Hong's profile picture Huijae An's profile picture Brendan Roberts's profile picture Alex Um's profile picture Advay Ratan's profile picture

rtl-llm 's datasets 6

rtl-llm/vhdl_chisel_interleaved_fine

Updated May 9 • 2

rtl-llm/chisel-verilog-pairs

Viewer • Updated May 1 • 35.5k • 6

rtl-llm/vhdl_github_deduplicated

Viewer • Updated Mar 10 • 8.97k • 16

rtl-llm/github_vhdl_verilog

Viewer • Updated Mar 6 • 16.1k • 5

rtl-llm/vhdl_github

Viewer • Updated Feb 25 • 101k • 15

rtl-llm/PyMTL_Verilog_pairs

Viewer • Updated Dec 13, 2024 • 18.6k • 35
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