rtl-llm
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qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate-len1024

Text Generation

text-generation-inference

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qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate-len1024

Commit History

Upload Qwen2ForCausalLM

28c8d1b
verified

charleshong3 commited on 24 days ago

Upload tokenizer

aa73137
verified

charleshong3 commited on 24 days ago

initial commit

da87ad4
verified

charleshong3 commited on 24 days ago