rtl-llm
/

qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate

Commit History

initial commit

9fd43cc
verified

charleshong3 commited on 25 days ago