rtl-llm
/

qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate

Commit History

Upload Qwen2ForCausalLM

7a05376
verified

charleshong3 commited on 24 days ago

Upload tokenizer

6d7dc1b
verified

charleshong3 commited on 24 days ago

initial commit

9fd43cc
verified

charleshong3 commited on 24 days ago