rtl-llm
/

qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-32b-origen-verilog-vhdl-chisel-truncate / config.json

Commit History

Upload Qwen2ForCausalLM

7a05376
verified

charleshong3 commited on 25 days ago