rtl-llm
/

qwen2.5coder-7b-origen-verilog-vhdl-chisel-interleaved-gs16

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-7b-origen-verilog-vhdl-chisel-interleaved-gs16 / model-00004-of-00004.safetensors

Commit History

Upload Qwen2ForCausalLM

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charleshong3 commited on 24 days ago

Upload Qwen2ForCausalLM

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charleshong3 commited on 24 days ago