rtl-llm
/

qwen2.5coder-7b-origen-verilog-vhdl-vhdl-chisel

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-7b-origen-verilog-vhdl-vhdl-chisel / .gitattributes

Commit History

Upload tokenizer

7482f61
verified

charleshong3 commited on 27 days ago

initial commit

e9093c8
verified

charleshong3 commited on 27 days ago