rtl-llm
/

qwen2.5coder-7b-origen-verilog-vhdl-vhdl-gs16-batch16

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-7b-origen-verilog-vhdl-vhdl-gs16-batch16 / .gitattributes

Commit History

Upload tokenizer

6aaa756
verified

charleshong3 commited on 23 days ago

initial commit

3721976
verified

charleshong3 commited on 23 days ago