rtl-llm
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qwen2.5coder-7b-origen-verilog-vhdl-vhdl-pymtl-chisel-truncate

Text Generation

text-generation-inference

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qwen2.5coder-7b-origen-verilog-vhdl-vhdl-pymtl-chisel-truncate

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initial commit

a291fc0
verified

charleshong3 commited on 26 days ago