rtl-llm
/

qwen2.5coder-7b-origen-verilog-vhdl-vhdl-truncate-interleave-len1024

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-7b-origen-verilog-vhdl-vhdl-truncate-interleave-len1024 / generation_config.json

Commit History

Upload Qwen2ForCausalLM

10cdc4e
verified

charleshong3 commited on 25 days ago