rtl-llm
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qwen2.5coder-7b-origen-vhdl-verilog-len768

Text Generation

text-generation-inference

Model card Files Files and versions Community

qwen2.5coder-7b-origen-vhdl-verilog-len768

Commit History

Upload Qwen2ForCausalLM

05d3814
verified

charleshong3 commited on 27 days ago

Upload tokenizer

b96241d
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charleshong3 commited on 27 days ago

initial commit

946f5ce
verified

charleshong3 commited on 27 days ago