data/text/DLP3/898274

TPS659411EVM: PMIC TPS65941X

Part Number: TPS659411EVM Hi all, I am designing the J7 platform base on SOC:DRA829 and PMICA:TPS659413 and PMICB:TPS659411, we are designing the SOP products, there is something need your help: 1 What is the timing sequence between VCCA(3V3),nPWRON/ENABLE of PMICA and VOUT_LDOVINT of PMICA? since I think the input signal nPWRON/ENABLE will be behind the output signal VOUT_LDOVINT which will ensure the synchronization of PMICA and PMICB, can you provide me with the exactly number of the time sequency? 2 According tocompany reference design: J7 EVM board, only PMICA have the wakeup function from GPIO4, and PMICB will follow the standard startup sequence process(like high level input signal on nPWRON/ENABLE) , my quension is that in real SOP product is the PMICB in this design can will be wakeup from the LP_standby state?we need to meet the quiescent current requirement. thanks! Best Regards,

Hi, VCCA is the power for PMIC A and PMIC B. Once this pin is supplied, the device internal regulators will also be supplied (LDOVINT and LDOVRTC). Then, the PMIC will load the default NVM settings from memory and wait in STANDBY mode. For the devices to turn on, use the ENABLE pin of PMIC A. This will cause both PMIC devices output rails to execute the power sequence to supply the Jacinto 7 processor. The PMIC A and PMIC B devices stay in sync through their SPMI communication (connecting GPIO_5 and GPIO_6 between the two devices). For full features of the power architecture for Jacinto 7, see our user guide: <secret URL>/lit/pdf/slvubr0 Thanks, Nastasha

Nastasha, Thanks for you answer! I have look through the document, there is someting useful for me, but I still has some questions. I would like to disscuss with your for the following 3 conditions, 1 First Startup( from power off to power on) 2 Wakeup(from LP_standby mode to normal mode) 3 Power off(From normal mode to LP_standby mode) I want to know the timing relationship of EN, LDOVINT of both PMICA and PMICB as well as the data communication state duing the change of the state of EN, LDOVINT in the 3 conditions each other! The figure description is preferred. thanks! Best Regards,

Hi, We have a diagram in the datasheet that is called "Device Startup Timing". This refers to the times that it takes to startup. These values depicted in the diagram are also specified in the specs section of the datasheet. Note that these specs will tell you the time from OFF to STANDBY. OFF to ACTIVE timing depends on how and when you are enabling the transition to the active state with the ENABLE pin. LDOVINT and LDOVRTC are included in this diagram. Power off timing will depend on the power sequence executing (whether it is an immediate or sequenced power down event). These timing are depicted in the user guide I previously shared. LP_STANDBY to STANDBY will go through BIST before going into the standby state, so only that timing will need to be considered to go to standby state. STANDBY to ACTIVE state timing is dependent on the power up sequence timing shown in the user guide. Please let me know if this helps. Thanks, Nastasha

Nastasha, The Figure 5-5 solved my first question of first start up timing sequence, but I haven't see the wakeup timing sequence since in wakeup state it is something different from first startup, eg., the VCCA is always on, when the CAN wakup signal in, the system will execute the NVM first or wakeup the VINT & VRTC first? And at this time when will the Valid On Request signal be active? before NVM or after NVM? Thanks! Best Regards,

Hi, I think I understand your question. This is how you turn on the system: 1. VCCA is powered 2. CAN event turns on the PMICs (pulls ENABLE pin high or uses GPIO wakeup functionality) Please let me know if I interpreted this correctly. In this case, once VCCA is powered, LDOVINT and LDOVRTC will be immediately powered. Then, NVM will load. Then BIST will run. Then, the device will wait for the CAN event. Once the CAN event occurs, the power sequence will start immediately. If the CAN event happens earlier, the device will wait until the previous steps are done, and then begin powering up. The first steps take 5-10ms (each step is more precisely defined in the datasheet). Then the power sequence takes ~15ms. If the CAN event happens at least 5ms after power is supplied to the PMIC, then there shouldn't be any delay. The only exception is if the CAN is waking up the device from LP_STANDBY. Then, the device will go through BIST before powering up. There is a figure in the datasheet (5-38) that may also help explain these scenarios. Let me know if this helps! Thanks, Nastasha

Nastasha, Thanks for your reply. As for this scenaria- Wakeup from LP_STANDBY state, my understanding is firstly the CAN_WAKEUP signal will be asserted, then system of PMICA will go through NVM and BIST before powering up, then LDOVINT active, then PMICB Enable(at the same time the PMICA will be also enable by an external control signal), then PMICB go through NVM and BIST, then by comunication of SPMI(I2C) the two PMICs will work synchronous,is it right? Best Regards,

Nastasha, Could you help to check if my understanding is right or wrong? Thanks! Best Regards,

Hi, When waking up from LP_STANDBY, the LDOVINT of PMIC A will turn on immediately, which will also enable PMIC B (since LDOVINT of PMIC A is connected to ENABLE of PMIC B). Then, both devices will load NVM and complete BIST in parallel. Then, through SPMI communication they will start the power up sequence together. Hope this helps! thanks, Nastasha

Nastasha, Thanks! Best Regards,