sample_embedding_folder2/0540822.txt

Ticket Name: TDA2x EVM (Vayu EVM): DDR3 reset signal and VTT turn off

Query Text:
Other Parts Discussed in Thread: TDA2 Hello team, I have two questions about DDR3 reference schematic in Vayu EVM (516582G4_VAYU_EVM_03MAR_2015A.pdf). 1. In Vayu reference schematic, DDR3 reset signals (DDR1_RST, DDR2_RST) come from 1V35_DDR power, not from TDA2 DDR reset singals (AG21,R24). Is there any specific reason not to use TDA2 DDR reset signals? 2. In Vayu reference schematic, VTT regulation LOD includes TR circuit on VTT supply. It looks to discharge VTT supply when it is off. What is the specific reason to add this kinds of circuit, and is it the mendatory for VTT supply? Best regards, Lloyd

Responses:
Hello Lloyd, All this is to support Suspend-To-RAM (STR), aka Fast Suspend-Resume (FSR). During STR the DDR3 memories must of course remain powered while the SoC is entirely off (except for possibly its RTC domains), and they must NOT be in reset (otherwise the memory chips shall exit the Suspend state and loose their contents). Therefore the DDRx_RST signals are derived from the PG output of the memory subsystem power buck (if you notice, the DDR3 supply for the SoC goes through a switch that is off during suspend, but the buck stays on). The SoC reset outputs pull low while it is off and would reset the chips if they were used for this purpose. On the other hand, the memory chips must see a stable low on CKE while in suspend. Therefore we actively discharge VTT, so that no glitches occur on CKE during the power-down (upon suspend entry) and power-up (upon resume) sequences - these are possible through the termination resistors of the other C/A bus signals. If STR/FSR is not a design requirement, the active discharge circuit is not needed, and the DDR3 resets can be driven by the SoC. Hope this answers your questions. Best regards, Lubo