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| { | |
| "ticketNumber" : "1021421", | |
| "reporterName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "resolutionStatus" : "", | |
| "ticketName" : "TDA2SX: RGB Interlaced output on LCD1", | |
| "rankName" : "Intellectual", | |
| "replies" : "", | |
| "views" : "", | |
| "queryText" : "Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, SYSCONFIG Hi Expert, I'm developing a custom tda2sx board on TI-RTOS Vision SDK v03.05. I need RGB888 Interlaced output on LCD1. I tried changing the scan format in chains_common.c. The following is my setting: static Void ChainsCommon_SetDctrlConfig pVInfo->mInfo.scanFormat = SYSTEM_SF_INTERLACED; pVInfo->mInfo.standard = SYSTEM_STD_576I; pVInfo->mInfo.pixelClock = 13500U; pVInfo->mInfo.vBackPorch = 19U; pVInfo->mInfo.vSyncLen = 3U; pVInfo->mInfo.vFrontPorch = 2U; pVInfo->mInfo.hBackPorch = 138U; pVInfo->mInfo.hSyncLen = 126U; pVInfo->mInfo.hFrontPorch = 24U; pVInfo->mInfo.fps = 50U; But no matter how I change the configuration, vout clk and sync remain the same. Always the following result CLK: 27.xMHz Hsync: 32.xkHz Vsync: 50 Are my settings correct, or are there other steps? My query is related to the thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/803192/rtos-tda2p-abz-working-of-adv7393-on-tda2px Could you please give some suggestions here? Thanks in advance.", | |
| "imageList" : null, | |
| "partNumber" : "NA", | |
| "allResponseList" : [ { | |
| "contentId" : "", | |
| "userName" : "Brijesh Jadav", | |
| "rankPoints" : "400895", | |
| "rankName" : "TI__Guru****", | |
| "date" : "", | |
| "userId" : "/members/1838755", | |
| "content" : "Hi, Interlaced and pixel clock are two different things. There is a separate interface for setting up clock, please use it to change the clock. Also vsync rate can remain same, depending on timing parameter. So could you please share your exact requirement? Rgds, Brijesh", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "rankName" : "Intellectual", | |
| "date" : "", | |
| "userId" : "/members/6162313", | |
| "content" : "Hi, My requirement is below: CLK：13.5 MHz Hsync：15.625 kHz Vsync：50 I tried to change pVInfo->mInfo, but it did not affect the result. pVInfo->mInfo.width = displayWidth; // 576 pVInfo->mInfo.height = displayHeight; // 720 pVInfo->mInfo.pixelClock = 13500U; But the CLK output is always 27MHz. Please tell me how to configure the \"separate interface for setting the clock\"? Thanks in advance.", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Brijesh Jadav", | |
| "rankPoints" : "400895", | |
| "rankName" : "TI__Guru****", | |
| "date" : "", | |
| "userId" : "/members/1838755", | |
| "content" : "You could change the pixel clock using this API Bsp_platformSetVencClkSrc. Please change clock to 13.5MHz here. Rgds, Brijesh", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "rankName" : "Intellectual", | |
| "date" : "", | |
| "userId" : "/members/6162313", | |
| "content" : "Hi, According to your suggestion, the current output is as follows: CLK: 13.5 MHz Hsync: 15.625 kHz Vsync: 25 Hz How can I adjust Vsync to 50?? In addition, I will confirm with you again that the tda2 series can achieve RGB888 Interlaced output on LCD1? Thanks in advance.", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Brijesh Jadav", | |
| "rankPoints" : "400895", | |
| "rankName" : "TI__Guru****", | |
| "date" : "", | |
| "userId" : "/members/1838755", | |
| "content" : "ok, atleast clock is correct now, 13.5Mhz We need to now configure DSS to output interlaced resolution. can you please check if interlaced output is set in the config/control register for the LCD you are using? Rgds, Brijesh", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "rankName" : "Intellectual", | |
| "date" : "", | |
| "userId" : "/members/6162313", | |
| "content" : "Hi, a. Can you tell me which registers should be checked for interlaced output? b. My configuration is as follows, why do I need to check? pVInfo->mInfo.width = displayWidth; // 576 pVInfo->mInfo.height = displayHeight; // 720 pVInfo->mInfo.scanFormat = SYSTEM_SF_INTERLACED; pVInfo->mInfo.standard = SYSTEM_STD_576I; c. Please answer me, can tda2 series achieve RGB888 Interlaced output on LCD1? Thanks in advance.", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Brijesh Jadav", | |
| "rankPoints" : "400895", | |
| "rankName" : "TI__Guru****", | |
| "date" : "", | |
| "userId" : "/members/1838755", | |
| "content" : "Hi, Wu BoHan said: a. Can you tell me which registers should be checked for interlaced output? Can you check DISPC_CONFIG. OUTPUTMODE_ENABLE (bit25) for the LCD output that you are using? This must be set to 1 for interlaced output Wu BoHan said: b. My configuration is as follows, why do I need to check? pVInfo->mInfo.width = displayWidth; // 576 pVInfo->mInfo.height = displayHeight; // 720 pVInfo->mInfo.scanFormat = SYSTEM_SF_INTERLACED; pVInfo->mInfo.standard = SYSTEM_STD_576I; This looks to be correct. Wu BoHan said: c. Please answer me, can tda2 series achieve RGB888 Interlaced output on LCD1? Weil, possible, but not validated. Regards, Brijesh", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "rankName" : "Intellectual", | |
| "date" : "", | |
| "userId" : "/members/6162313", | |
| "content" : "Hi, Brijesh Jadav said: Can you check DISPC_CONFIG. OUTPUTMODE_ENABLE (bit25) for the LCD output that you are using? This must be set to 1 for interlaced output I checked DISPC_CONFIG1(0x5800 1044) and the result was 0x0040 0c04. OUTPUTMODEENABLE (bit 22) 0x1: Interlace mode selected How should I check or set the next step? thanks.", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Brijesh Jadav", | |
| "rankPoints" : "400895", | |
| "rankName" : "TI__Guru****", | |
| "date" : "", | |
| "userId" : "/members/1838755", | |
| "content" : "Hi, Can you please run gel file from pdk_xx_xx_xx_xx\\packages\\ti\\drv\\vps\\docs\\tda2xx\\TDA2xx_Dss_RegDump.gel from IPU core? and share the output. This will tell us if the register is setup correctly. Regards, Brijesh", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "rankName" : "Intellectual", | |
| "date" : "", | |
| "userId" : "/members/6162313", | |
| "content" : "Hi, The results of run gel are as follows: [IPU1-0] 29.388702 s: DSS_DISPC_REVISION = 0x51 [IPU1-0] 29.388824 s: DSS_DISPC_SYSCONFIG = 0x1 [IPU1-0] 29.388916 s: DSS_DISPC_SYSSTATUS = 0x1 [IPU1-0] 29.389068 s: DSS_DISPC_IRQSTATUS = 0x0 [IPU1-0] 29.389190 s: DSS_DISPC_IRQENABLE = 0x4662 [IPU1-0] 29.389373 s: DSS_DISPC_CONTROL1 = 0x329 [IPU1-0] 29.389556 s: DSS_DISPC_CONFIG1 = 0x400c04 [IPU1-0] 29.389800 s: DSS_DISPC_DEFAULT_COLOR0 = 0x0 [IPU1-0] 29.390197 s: DSS_DISPC_DEFAULT_COLOR1 = 0x0 [IPU1-0] 29.390319 s: DSS_DISPC_TRANS_COLOR0 = 0x0 [IPU1-0] 29.390502 s: DSS_DISPC_TRANS_COLOR1 = 0x0 [IPU1-0] 29.390624 s: DSS_DISPC_LINE_STATUS = 0x16 [IPU1-0] 29.390776 s: DSS_DISPC_LINE_NUMBER = 0x23b [IPU1-0] 29.390898 s: DSS_DISPC_TIMING_H1 = 0x4400b3e [IPU1-0] 29.391356 s: DSS_DISPC_TIMING_V1 = 0x1300202 [IPU1-0] 29.391661 s: DSS_DISPC_POL_FREQ1 = 0x7000 [IPU1-0] 29.391844 s: DSS_DISPC_DIVISOR1 = 0x10001 [IPU1-0] 29.391966 s: DSS_DISPC_GLOBAL_ALPHA = 0xffffffff [IPU1-0] 29.416610 s: DSS_DISPC_SIZE_TV = 0x0 [IPU1-0] 29.416732 s: DSS_DISPC_SIZE_LCD1 = 0x23f02cf [IPU1-0] 29.416946 s: DSS_DISPC_GFX_BA0 = 0x84d95800 [IPU1-0] 29.417190 s: DSS_DISPC_GFX_BA1 = 0x84d95da0 [IPU1-0] 29.417312 s: DSS_DISPC_GFX_POSITION = 0x0 [IPU1-0] 29.417525 s: DSS_DISPC_GFX_SIZE = 0x0 [IPU1-0] 29.417647 s: DSS_DISPC_GFX_ATTRIBUTES = 0xe0000a1 [IPU1-0] 29.417830 s: DSS_DISPC_GFX_BUF_THRESHOLD = 0x4ff04f8 [IPU1-0] 29.417952 s: DSS_DISPC_GFX_BUF_SIZE_STATUS = 0x500 [IPU1-0] 29.418349 s: DSS_DISPC_GFX_ROW_INC = 0x1 [IPU1-0] 29.418471 s: DSS_DISPC_GFX_PIXEL_INC = 0x1 [IPU1-0] 29.418593 s: DSS_DISPC_GFX_TABLE_BA = 0x0 [IPU1-0] 29.418745 s: DSS_DISPC_VID1_BA0 = 0x84c33000 [IPU1-0] 29.418867 s: DSS_DISPC_VID1_BA1 = 0x84c332d0 [IPU1-0] 29.418989 s: DSS_DISPC_VID1_POSITION = 0x0 [IPU1-0] 29.419172 s: DSS_DISPC_VID1_SIZE = 0x0 [IPU1-0] 29.419325 s: DSS_DISPC_VID1_ATTRIBUTES = 0x2008401 [IPU1-0] 29.419447 s: DSS_DISPC_VID1_BUF_THRESHOLD = 0x7ff07f8 [IPU1-0] 29.419569 s: DSS_DISPC_VID1_BUF_SIZE_STATUS = 0x800 [IPU1-0] 29.419691 s: DSS_DISPC_VID1_ROW_INC = 0x1 [IPU1-0] 29.419813 s: DSS_DISPC_VID1_PIXEL_INC = 0x1 [IPU1-0] 29.419935 s: DSS_DISPC_VID1_FIR = 0x4000400 [IPU1-0] 29.420148 s: DSS_DISPC_VID1_PICTURE_SIZE = 0x0 [IPU1-0] 29.420270 s: DSS_DISPC_VID1_CONV_COEF0 = 0x0 [IPU1-0] 29.420453 s: DSS_DISPC_VID1_CONV_COEF1 = 0x0 [IPU1-0] 29.420575 s: DSS_DISPC_VID1_CONV_COEF2 = 0x0 [IPU1-0] 29.420728 s: DSS_DISPC_VID1_CONV_COEF3 = 0x0 [IPU1-0] 29.420850 s: DSS_DISPC_VID1_CONV_COEF4 = 0x0 [IPU1-0] 29.420972 s: DSS_DISPC_VID2_POSITION = 0x0 [IPU1-0] 29.426096 s: DSS_DISPC_VID2_SIZE = 0x0 [IPU1-0] 29.426188 s: DSS_DISPC_VID2_ATTRIBUTES = 0x6008400 [IPU1-0] 29.426432 s: DSS_DISPC_VID2_BUF_THRESHOLD = 0x7ff07f8 [IPU1-0] 29.426523 s: DSS_DISPC_VID2_BUF_SIZE_STATUS = 0x800 [IPU1-0] 29.426584 s: DSS_DISPC_VID2_ROW_INC = 0x1 [IPU1-0] 29.426676 s: DSS_DISPC_VID2_PIXEL_INC = 0x1 [IPU1-0] 29.426737 s: DSS_DISPC_VID2_FIR = 0x4000400 [IPU1-0] 29.426798 s: DSS_DISPC_VID2_PICTURE_SIZE = 0x0 [IPU1-0] 29.426859 s: DSS_DISPC_VID2_CONV_COEF0 = 0x0 [IPU1-0] 29.426950 s: DSS_DISPC_VID2_CONV_COEF1 = 0x0 [IPU1-0] 29.427011 s: DSS_DISPC_VID2_CONV_COEF2 = 0x0 [IPU1-0] 29.427286 s: DSS_DISPC_VID2_CONV_COEF3 = 0x0 [IPU1-0] 29.427347 s: DSS_DISPC_VID2_CONV_COEF4 = 0x0 [IPU1-0] 29.427438 s: DSS_DISPC_DATA1_CYCLE1 = 0x0 [IPU1-0] 29.427499 s: DSS_DISPC_DATA1_CYCLE2 = 0x0 [IPU1-0] 29.427560 s: DSS_DISPC_DATA1_CYCLE3 = 0x0 [IPU1-0] 29.427621 s: DSS_DISPC_CPR1_COEF_R = 0x0 [IPU1-0] 29.427774 s: DSS_DISPC_CPR1_COEF_G = 0x0 [IPU1-0] 29.427896 s: DSS_DISPC_CPR1_COEF_B = 0x0 [IPU1-0] 29.428018 s: DSS_DISPC_GFX_PRELOAD = 0x100 [IPU1-0] 29.428597 s: DSS_DISPC_VID1_PRELOAD = 0x100 [IPU1-0] 29.428719 s: DSS_DISPC_VID2_PRELOAD = 0x100 [IPU1-0] 29.428841 s: DSS_DISPC_CONTROL2 = 0x300 [IPU1-0] 29.428963 s: DSS_DISPC_GFX_POSITION2 = 0x0 [IPU1-0] 29.429421 s: DSS_DISPC_VID1_POSITION2 = 0x0 [IPU1-0] 29.429543 s: DSS_DISPC_VID2_POSITION2 = 0x0 [IPU1-0] 29.429665 s: DSS_DISPC_VID3_POSITION2 = 0x0 [IPU1-0] 29.429878 s: DSS_DISPC_VID3_ATTRIBUTES = 0xa008400 [IPU1-0] 29.430458 s: DSS_DISPC_VID3_CONV_COEF0 = 0x0 [IPU1-0] 29.430580 s: DSS_DISPC_VID3_CONV_COEF1 = 0x0 [IPU1-0] 29.430702 s: DSS_DISPC_VID3_CONV_COEF2 = 0x0 [IPU1-0] 29.430885 s: DSS_DISPC_VID3_CONV_COEF3 = 0x0 [IPU1-0] 29.431007 s: DSS_DISPC_VID3_CONV_COEF4 = 0x0 [IPU1-0] 29.444915 s: DSS_DISPC_VID3_BUF_SIZE_STATUS = 0x800 [IPU1-0] 29.445312 s: DSS_DISPC_VID3_BUF_THRESHOLD = 0x7ff07f8 [IPU1-0] 29.445495 s: DSS_DISPC_VID3_FIR = 0x4000400 [IPU1-0] 29.445617 s: DSS_DISPC_VID3_PICTURE_SIZE = 0x0 [IPU1-0] 29.445739 s: DSS_DISPC_VID3_PIXEL_INC = 0x1 [IPU1-0] 29.445861 s: DSS_DISPC_VID3_POSITION = 0x0 [IPU1-0] 29.446013 s: DSS_DISPC_VID3_PRELOAD = 0x100 [IPU1-0] 29.446440 s: DSS_DISPC_VID3_ROW_INC = 0x1 [IPU1-0] 29.446562 s: DSS_DISPC_VID3_SIZE = 0x0 [IPU1-0] 29.446715 s: DSS_DISPC_DEFAULT_COLOR2 = 0x0 [IPU1-0] 29.446837 s: DSS_DISPC_TRANS_COLOR2 = 0x0 [IPU1-0] 29.446959 s: DSS_DISPC_CPR2_COEF_B = 0x0 [IPU1-0] 29.447355 s: DSS_DISPC_CPR2_COEF_G = 0x0 [IPU1-0] 29.447477 s: DSS_DISPC_CPR2_COEF_R = 0x0 [IPU1-0] 29.447660 s: DSS_DISPC_DATA2_CYCLE1 = 0x0 [IPU1-0] 29.447782 s: DSS_DISPC_DATA2_CYCLE2 = 0x0 [IPU1-0] 29.447935 s: DSS_DISPC_DATA2_CYCLE3 = 0x0 [IPU1-0] 29.448179 s: DSS_DISPC_SIZE_LCD2 = 0x0 [IPU1-0] 29.448301 s: DSS_DISPC_TIMING_H2 = 0x0 [IPU1-0] 29.448423 s: DSS_DISPC_TIMING_V2 = 0x0 [IPU1-0] 29.448545 s: DSS_DISPC_POL_FREQ2 = 0x0 [IPU1-0] 29.448697 s: DSS_DISPC_DIVISOR2 = 0x40001 [IPU1-0] 29.448819 s: DSS_DISPC_WB_ATTRIBUTES = 0x8000 [IPU1-0] 29.448941 s: DSS_DISPC_WB_CONV_COEF0 = 0x0 [IPU1-0] 29.464497 s: DSS_DISPC_WB_CONV_COEF1 = 0x0 [IPU1-0] 29.464588 s: DSS_DISPC_WB_CONV_COEF2 = 0x0 [IPU1-0] 29.464863 s: DSS_DISPC_WB_CONV_COEF3 = 0x0 [IPU1-0] 29.464924 s: DSS_DISPC_WB_CONV_COEF4 = 0x0 [IPU1-0] 29.464985 s: DSS_DISPC_WB_BUF_SIZE_STATUS = 0x800 [IPU1-0] 29.465107 s: DSS_DISPC_WB_BUF_THRESHOLD = 0x7ff07f8 [IPU1-0] 29.465168 s: DSS_DISPC_WB_FIR = 0x4000400 [IPU1-0] 29.465229 s: DSS_DISPC_WB_PICTURE_SIZE = 0x0 [IPU1-0] 29.465320 s: DSS_DISPC_WB_PIXEL_INC = 0x1 [IPU1-0] 29.465381 s: DSS_DISPC_WB_ROW_INC = 0x1 [IPU1-0] 29.465442 s: DSS_DISPC_WB_SIZE = 0x0 [IPU1-0] 29.465503 s: DSS_DISPC_VID1_BA_UV0 = 0x84b35a00 [IPU1-0] 29.465564 s: DSS_DISPC_VID1_BA_UV1 = 0x84b35cd0 [IPU1-0] 29.465656 s: DSS_DISPC_CONFIG2 = 0x0 [IPU1-0] 29.465717 s: DSS_DISPC_VID1_ATTRIBUTES2 = 0x0 [IPU1-0] 29.465778 s: DSS_DISPC_VID2_ATTRIBUTES2 = 0x0 [IPU1-0] 29.465869 s: DSS_DISPC_VID3_ATTRIBUTES2 = 0x0 [IPU1-0] 29.465930 s: DSS_DISPC_GAMMA_TABLE0 = 0x0 [IPU1-0] 29.465991 s: DSS_DISPC_GAMMA_TABLE2 = 0x0 [IPU1-0] 29.466296 s: DSS_DISPC_VID1_FIR2 = 0x4000400 [IPU1-0] 29.466418 s: DSS_DISPC_VID2_FIR2 = 0x4000400 [IPU1-0] 29.466540 s: DSS_DISPC_VID3_FIR2 = 0x4000400 [IPU1-0] 29.466662 s: DSS_DISPC_WB_FIR2 = 0x4000400 [IPU1-0] 29.466784 s: DSS_DISPC_GLOBAL_BUFFER = 0x246d2240 [IPU1-0] 29.466937 s: DSS_DISPC_DIVISOR = 0x10001 [IPU1-0] 29.467364 s: DSS_DISPC_WB_ATTRIBUTES2 = 0x0 [IPU1-0] 29.467516 s: DSS_DISPC_DEFAULT_COLOR3 = 0x0 [IPU1-0] 29.467638 s: DSS_DISPC_TRANS_COLOR3 = 0x0 [IPU1-0] 29.467760 s: DSS_DISPC_CPR3_COEF_B = 0x0 [IPU1-0] 29.467882 s: DSS_DISPC_CPR3_COEF_G = 0x0 [IPU1-0] 29.468004 s: DSS_DISPC_CPR3_COEF_R = 0x0 [IPU1-0] 29.468462 s: DSS_DISPC_DATA3_CYCLE1 = 0x0 [IPU1-0] 29.468584 s: DSS_DISPC_DATA3_CYCLE2 = 0x0 [IPU1-0] 29.468706 s: DSS_DISPC_DATA3_CYCLE3 = 0x0 [IPU1-0] 29.468919 s: DSS_DISPC_SIZE_LCD3 = 0x0 [IPU1-0] 29.493747 s: DSS_DISPC_DIVISOR3 = 0x40001 [IPU1-0] 29.493869 s: DSS_DISPC_POL_FREQ3 = 0x0 [IPU1-0] 29.494387 s: DSS_DISPC_TIMING_H3 = 0x0 [IPU1-0] 29.494509 s: DSS_DISPC_TIMING_V3 = 0x0 [IPU1-0] 29.494631 s: DSS_DISPC_CONTROL3 = 0x300 [IPU1-0] 29.494845 s: DSS_DISPC_CONFIG3 = 0x0 [IPU1-0] 29.494967 s: DSS_DISPC_BA0_FLIPIMMEDIATE_EN = 0x0 [IPU1-0] 29.495424 s: DSS_DISPC_DISABLE_MSTANDBY_ENHANCEMENT = 0x1 [IPU1-0] 29.495546 s: DSS_DISPC_GLOBAL_MFLAG_ATTRIBUTE = 0x6 [IPU1-0] 29.495668 s: DSS_DISPC_GFX_MFLAG_THRESHOLD = 0x0 [IPU1-0] 29.495790 s: DSS_DISPC_VID1_MFLAG_THRESHOLD = 0x0 [IPU1-0] 29.495912 s: DSS_DISPC_VID2_MFLAG_THRESHOLD = 0x0 [IPU1-0] 29.496370 s: DSS_DISPC_VID3_MFLAG_THRESHOLD = 0x0 [IPU1-0] 29.496492 s: DSS_DISPC_WB_MFLAG_THRESHOLD = 0x0 How should I check or set the next step? thanks.", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Brijesh Jadav", | |
| "rankPoints" : "400895", | |
| "rankName" : "TI__Guru****", | |
| "date" : "", | |
| "userId" : "/members/1838755", | |
| "content" : "Hi, I think the issue can be due to below register, it should be set to half of frame size. It should be set (288-1) for the field display. Can you try with this change? 9.416732 s: DSS_DISPC_SIZE_LCD1 = 0x23f02cf Regards, Brijesh", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "rankName" : "Intellectual", | |
| "date" : "", | |
| "userId" : "/members/6162313", | |
| "content" : "Hi, I directly modify the DSS_DISPC_SIZE_LCD1 register to 0x11f02c. The Vsync output is 50Hz, but it is not continuous. As shown below: a. Is there an API to modify DSS_DISPC_SIZE_LCD1? b. In addition, Vsync is not continuous, how to fix it? thanks.", | |
| "imageList" : [ "Data/input/1021421/jpg" ] | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Brijesh Jadav", | |
| "rankPoints" : "400895", | |
| "rankName" : "TI__Guru****", | |
| "date" : "", | |
| "userId" : "/members/1838755", | |
| "content" : "Hi, What do you mean by vsync is not continuous? Also can you confirm that DSS_DISPC_SIZE_LCD1 is set to 0x11d02cf? Also how about the vertical timing? We would have to make vertical timing also half. Regards, Brijesh", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "rankName" : "Intellectual", | |
| "date" : "", | |
| "userId" : "/members/6162313", | |
| "content" : "Hi, I modify the DSS_DISPC_SIZE_LCD1 register is set to 0x11d02cf. The vertical timing is shown below: Why is there no Vsync at the position marked by the green line? thanks.", | |
| "imageList" : [ "Data/input/1021421/jpg" ] | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Brijesh Jadav", | |
| "rankPoints" : "400895", | |
| "rankName" : "TI__Guru****", | |
| "date" : "", | |
| "userId" : "/members/1838755", | |
| "content" : "Hi, Did you also change the timing? I think you need to halve the virtual timing. I guess driver will set full vertical timing, so can make all timing to half in timing_v register? Regards, Brijesh", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Wu BoHan", | |
| "rankPoints" : "315", | |
| "rankName" : "Intellectual", | |
| "date" : "", | |
| "userId" : "/members/6162313", | |
| "content" : "Hi, Brijesh Jadav said: so can make all timing to half in timing_v register? The timing_v register is DISPC_TIMING_V1 (0x5800 1068)? My configuration is as follows: static Void ChainsCommon_SetDctrlConfig pVInfo->mInfo.vBackPorch = 19U; pVInfo->mInfo.vSyncLen = 3U; pVInfo->mInfo.vFrontPorch = 2U; pVInfo->mInfo.hBackPorch = 138U; pVInfo->mInfo.hSyncLen = 126U; pVInfo->mInfo.hFrontPorch = 24U; Wu BoHan said: [IPU1-0] 29.390898 s: DSS_DISPC_TIMING_H1 = 0x4400b3e [IPU1-0] 29.391356 s: DSS_DISPC_TIMING_V1 = 0x1300202 VBP[31:20]: 0x013 → 19 VFP[19:8]: 0x002 → 2 VSW[7:0]: 0x02 → 2 HBP[31:20]: 0x044 → 68 HFP[19:8]: 0x00b → 11 HSW[7:0]: 0x3e → 62 Do I need to halve the virtual timing? Is there an API to using? thanks.", | |
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| "userName" : "Brijesh Jadav", | |
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| "content" : "Hi, vsync cannot vary so much. Once the timing is provided, atleast, it will be periodic. so are you sure that you are measuring vsync? Is DSS really configured for discrete sync output? And also is the pinmux for the vsync output setup correctly? Regarding timing, for PAL resolution, there would be 312 lines per field. You are programming 286 + 19 + 2 + 3 lines, which is 310 lines.. It is slightly short, but even with this timing, you should get vsync period consistent. vsync cannot vary so much.. Regards, Brijesh", | |
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| "userName" : "Wu BoHan", | |
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| "content" : "Hi, Brijesh Jadav said: Is DSS really configured for discrete sync output? How can I check the configuration and results? thanks.", | |
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| "userName" : "Brijesh Jadav", | |
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| "content" : "Hi, Wu BoHan said: How can I check the configuration and results? I meant the pinmux, pixel clock etc. are you sure that the pinmux is correct? Can you also probe pixel clock and make sure it is correct? Regards, Brijesh", | |
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| "userName" : "Wu BoHan", | |
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| "content" : "Hi, When I tried changing the scan format in chains_common.c. The following is my setting: static Void ChainsCommon_SetDctrlConfig pVInfo->mInfo.scanFormat = SYSTEM_SF_INTERLACED; pVInfo->mInfo.standard = SYSTEM_STD_576I; Assertion occurs during execution: [IPU1-0] 5.807478 s: CAPTURE: Create in progress !!! [IPU1-0] 5.807692 s: CAPTURE: VIP1 Slice1 PortB capture mode is [ 8-bit] !!! [IPU1-0] 5.862044 s: CAPTURE: Create Done !!! [IPU1-0] 5.862441 s: DISPLAY: Create in progress !!! [IPU1-0] 5.862746 s: dispcore/src/vpscore_dss.c @ Line 1412: [IPU1-0] 5.862868 s: Format(interlaced/progressive) conversion is not supported [IPU1-0] 5.862959 s: dispdrv/src/vpsdrv_displayCore.c @ Line 304: [IPU1-0] 5.863020 s: Set DSS parameter failed [IPU1-0] 5.863081 s: Assertion @ Line: 459 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! [IPU1-0] 5.863600 s: Assertion @ Line: 459 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! Assertion points to the following: Int32 DisplayLink_drvDisplayCreate(DisplayLink_Obj *pObj) status = FVID2_control( pObj->displayHndl, IOCTL_VPS_DISP_SET_DSS_PARAMS, &pObj->dssPrms, NULL); What should I do? thanks.", | |
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| "userName" : "Brijesh Jadav", | |
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| "content" : "Hi, It looks like your output format is set to interlaced format, but input is in progressive. Could you please make sure to set both of them to interlaced? I think on TDA3x, we had support for setting up output to NTSC/PAL resolution, which are interlaced resolution. Could you please check display settings for these modes in the vision sdk and make similar changes for TDA2x? For TDA3x, on display settings, we can select output to DAC and select the resolution to NTSC/PAL. Entire usecase will then work and output on NTSC/PAL resolution. Regards, Brijesh", | |
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| } ], | |
| "tags" : [ ], | |
| "fourmType" : "processors-forum" | |
| } |