embed files

sample_embedding_folder/1000341.txt

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+Ticket Name: TDA2SX: TDA2SXBTQABCRQ1
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 1. How many watchdog timers in TDA2SXBTQABCRQ1 and where? 2. The MPU has its own watchdog timer that is different from watchdog timer in the PRCM? 3.IPU and DSP use the watchdog in the PRCM? If so, how to distinguish the error output by watchdog? 4. The following picture is from TDA2 technical reference manual chapter 18.4.6. When T is not within threshold low to threshold high, the output alert maybe do not be asserted to 1, like the blue arrow in the picture. Why? thank you!
+
+Responses:
+1. 2 watchdog timers. 1x system watchdog and 1x MPU watchdog timer. 2. yes. 3. One watchdog timer can only be used by either IPU or DSP. You can also use GP Timer as watchdog timer. 4. Alert (Temp too high) is generated first when the temp goes above the high threshold and the next alert (Temp is safe) is generated only when the temp goes below the low threshold. In between this two events is where you have to do thermal management to lower the temp to avoid thermal shutdown.
+

sample_embedding_folder/1000532.txt

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+Ticket Name: TDA2EXEVM: Communication with another SPI slave
+
+Query Text:
+Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 Hi, Can you please give some directions on how to share the TDA2 SPI Master (there are 4 SPI Modules that can be Master where each module has support for 4 Slaves (4 CS))? There is an API in Utils_mcspi.c that I am looking at as a reference. Upon boots, the Radar SDK initializes 4 SPI instances using channel 0 (CS0) to set up SPI communications with the 4 attached AWRs. My questions are as follows: 1. Why is it not necessary to call Utils_mcspiOpen() during AWR Init? 2. Why static Utils_mcspiDeviceCommObj gUtils_mcspiDeviceCommObj[UTILS_MCSPI_NUM_DEVICES]; where UTILS_MCSPI_NUM_DEVICES = 8? I thought there are 4 SPI modules only. 3. In my application where I share SPI Module0 using CS1 to communicate with my slave device, I called the Utils_mcspiOpen() specifying the deviceId = 0, mcSpiDevInstNum = 0, mcSpiChannelNum = 1. This resulted in a crash during boot. Debugged into it said the FIFO has already been in use. 4. The thought in calling Utils_mcspiOpen() was because the SPI 4 instances have already been initialized during AWRs setup. I assume I need to call Open() before calling Utils_mcspiRead()/Write(). Thank you in advance,
+
+Responses:
+Hi, Each McSPI can support up to 4 Master but only 1 Slave. 1. SPI is needed for configuration so as long as it is called before radar configuration step, it is fine. 2. UTILS_MCSPI_NUM_DEVICES is just a number to limit the total number of external devices which can be connected to SPIx, not number of SPI modules. It is just a number we picked. Each McSPI as master can connect up to 4 devices. 3. deviceId is the index of the radar devices, not mcspi instance id. If you already have one radar with CS0 on McSPI1 (mcspi instance 0), this would be deviceId =1. 4. _Init() then _open() to get handle. After that, use the handle to call read/write. Regards, Stanley
+
+Hi Stanley, Thanks for the clarifications. Got a bit further. We need a bit more clarity to get this working. 1. is mcSpiChannelNum in Utils_mcspiOpen() the same as ChipSelect? If not, don't I need to specify the CS# on the mcSpi module? 2. I now called Utils_mcspiInit(1) and then called Utils_mcspiOpen(1, 0, 1, edmaHandle) to get a valid SPI handle. This resulted in a UTILS_MCSPI: McSPI GIO Create Failed!! on the console. After it crashed. 3. So looks like we still don't completely understand the API usage. Thanks,
+
+Any Suggestions?
+
+Hi Asher, I am not sure I follow what you are trying to implement here. Are you using radar driver in SDK? If yes, radar SPI driver is implemented in ~/pdk_xx_xx_xx_xx/packages/ti/drv/vps/src/devices/radar_ar12xx/src/bspdrv_ar12xxMcspiCfgPriv.c. Only Utils_mcspiInit() is called from use case to add the McSPI instace to GIO device and configure crossbar for interrupt. The instance will be opened later by radar SPI driver in PDK. To configure radar, we use radar APIs from rl_sensor.c in ~/mmwave_dfp/ti/control/mmwavelink/src/rl_sensor.c, which has the callback hooked to radar SPI driver. We don't directly call McSPI APIs from use case since SPI protocol is implemented by radar link layer. Regards, Stanley
+
+In addition, please note that Utils_mcspiInit(UInt32 mcSpiInstNum) where mcSpiInstNum = 0 (McSPI1), 1 (McSPI2), 2...
+
+Hi Stanley, Sorry for the confusion. Let me start this over again. We would like to use (configure) one of the 4 mcSPI modules on the TDA2 to communicate with a SPI slave device. Please provide steps on how that can be done. We went thru the utils_mcspi.c in radar SDK thinking that that's the API we should be using as awr12xx configuration is using that utils API to configure AWR. We read the TDA2 datasheet and it indicated that each MCSPI module can support 4 slave. Is this not the case? I think you briefly stated that "Each McSPI can support up to 4 Master but only 1 Slave". Does that mean we cannot use SPI to talk to our external device over SPI? If this is true, then case close. SPI is not the solution. If mcSPI module can be used, then please provide instructions on how to add a SPI slave to an mcSPI module using chip select knowing that each mcSPI module is a Master to each slave AWR. Thanks, --Khai
+
+Khai Trinh said: We read the TDA2 datasheet and it indicated that each MCSPI module can support 4 slave. Is this not the case? What I meant was when McSPI is the master, it can support up to 4 slave devices with 4 CSn. So, yes, each McSPI module as master can connect to 4 slaves. Which external SPI slave device are you connecting to? Radar or something else? If it is radar, why don't you use our radar SPI driver? Regards, Stanley
+
+Another SPI slave device. Please provide step-by-step instructions on how to configure it. i have tried Uitls_mcSPI.c API. If you go back to my questions below: Thanks for the clarifications. Got a bit further. We need a bit more clarity to get this working. 1. is mcSpiChannelNum in Utils_mcspiOpen() the same as ChipSelect? If not, don't I need to specify the CS# on the mcSpi module? 2. I now called Utils_mcspiInit(1) and then called Utils_mcspiOpen(1, 0, 1, edmaHandle) to get a valid SPI handle. This resulted in a UTILS_MCSPI: McSPI GIO Create Failed!! on the console. After it crashed. 3. So looks like we still don't completely understand the API usage. Thanks, --Khai You gave some hint on i
+
+Hi Stanley, Just want to follow on this topic. Can you please advice... The current setup in the SDK is each mcSPI module is a Master on processor side with an AWR as a slave. So 4 mcSPI modules pairing with 4 AWR slaves. That part I don't have to do anything. It's all working as is. Now I need to add another SPI slave device to 1 of the 4 Master. So we need to configure a ChipSelect on the Master side. How that can be done thru the Utils_mcSPI.c API is really my question. I have tried a few things I described above without any luck. If you have an answer, please describe it here so I can try it out. For something like this, a conf call can be much more productive. Thanks,
+
+Hi, Ok. It makes more sense now. 1. You don't have to call Utils_mcspiInit(instId) again because each instance only needs to be initialized once. Since you are using one of the instances which is used by radar, it is already called in ChainsCommon_ar12xxInit(). Make sure you open SPI channel only after ChainsCommon_ar12xxInit(). 2. FIFO mode can be enabled on only one channel per McSPI instance. Utils_mcspiOpen() keeps track of it in its scope. However, Radar driver enables FIFO mode in its own open call outside of Utils_mscpiOpen(). For your use case to work, you have to disable FIFO mode in Utils_mcspiOpen(). You can change the below line in Utils_mcspiOpen() to 1 to disable FIFO mode. static UInt32 fifoEnabled[UTILS_MCSPI_NUM_MCSPI_INST] = {1U, 1U, 1U, 1U}; Please give this a try and see if it works. Regards, Stanley
+

sample_embedding_folder/1000797.txt

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+Ticket Name: TDA2HV: TI support of QEMU for TDA2 APP
+
+Query Text:
+Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hi there, 1. Does QEMU support TDA2 APP? I have been searching for some time but in QEMU says that if the TDA2 machine is not listed than is very unlikely to be supported. 2. Is there any emulator support to test app without a board? I need it for testing. The board can be damaged by a quick test. 3. Can I convert my Application Image back to ELF? In my opinion, it is converted to ELF -> Application Image(RPRC) using the following command. ``` out2rprc.exe <App_In_name(elf or coff)> <App_out_name> ``` Please let me know if it supported. Any guidance would be appreciated. Regards,
+
+Responses:
+Hi, 1. No. We don't have QEMU support on TDA2. 2. No. We don't have emulator for TDA2. 3. No. We don't have utility to covert AppImage back to multiple Elf files. Regards, Stanley
+

sample_embedding_folder/1001310.txt

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+Ticket Name: TDA2EVM5777: How to use I2C high speed mode?
+
+Query Text:
+Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2 Hi expert, We have a requirement to use I2C5 to communicate between TDA2 SOC and MCU. I checked the Source code and found the I2C API path. Would this API support high speed mode and is easy to apply on the vision sdk? If it is not applicable, is there any other sample code? C:\PROCESSOR_SDK_VISION_03_05_00_00\ti_components\drivers\pdk_01_10_01_06\packages\ti\drv\stw_lld\i2clld\src\lld_hsi2c.c
+
+Responses:
+Hi, The supported i2c bus speed is 100Khz and 400Khz for this I2C driver. It doesn't support HS mode. We don't have example i2c driver for HS mode. However, the I2C hardware on TDA2 is capable of running HS mode. Regards, Stanley
+

sample_embedding_folder/1001510.txt

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+Ticket Name: TDA2HV: CLANG and LLVM build support
+
+Query Text:
+Part Number: TDA2HV Other Parts Discussed in Thread: TDA2 Hello Does the tda processor support "clang" builds? If applying, where should I edit it?
+
+Responses:
+Hi, Not supported and no plans to add it for TDA2. Note : There is a plan to add support for TDA4 devices in next release Regards Vineet
+

sample_embedding_folder/1001590.txt

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+Ticket Name: TDA2PXEVM: Problems with the TIDL library import tool
+
+Query Text:
+Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello, I am trying to use TIDL library on TDA2PX EVM to run DNNs on EVE and DSP cores. I am using TensorFlow as a framework. I am following the user guide with the title " TI Deep learning Library on TDAx " - November 2019. The user guide states that " TIDL supports slim based tensorflow models ". Does TIDL library supports only slim based TensorFlow models ? Does it mean that I can not import models trained in TensorFlow, not TensorFlow slim? I have tried to import MobileNet V2 from TensorFlow Keras applications using the TIDL library, but I get error mesages saying that "Pad Layer is not supported by TIDL and cannot be merged into any TIDL layer". Moreover, I need to know where I can find the file "optimize_for_inference.py". Thanks, Ahmed Anwar
+
+Responses:
+Hi Ahmed, >> Does it mean that I can not import models trained in TensorFlow, not TensorFlow slim? Yes, TIDL on TDA2 can import only TensorFlow slim models. On TDA4 we support TensorFlow models also. >> but I get error mesages saying that "Pad Layer is not supported by TIDL and cannot be merged into any TIDL layer" This is because of Pad layer is not supported, refer to datasheet for all the supported layers >> I need to know where I can find the file "optimize_for_inference.py" This is available in "tensorflow/python/tools" folder Thanks, Praveen
+
+Hello Praveen, Thank you for your reply. I have a question regarding the TensorFlow slim models. In the user guide, there is an example of a Keras/TensorFlow model which can be found here. This example uses Keras from TensorFlow, not TensorFlow slim, to build a simple CNN, which can be used as an input to the TIDL import tool. Does this mean that I can use Keras from TensorFlow, not TensorFlow slim, to build a CNN and use it as an input to the TIDL import tool ? I just need to understand this point better, as most of my development is already in Keras/TensorFlow, and the example that I mentioned also uses Keras/TensorFlow. However, based on your reply, "TIDL on TDA2 can import only TensorFlow slim models". Would you please illustrate how this example uses Keras/TensorFlow if only TensorFlow slim models are supported on TDA2 ? Thanks, Ahmed Anwar
+
+Yes, We have limited layers support for Tesnsoflow in TDA2, where as most of the layers are supported with Caffe/Tensorflow slim models. Please refer to below comment in the user guide section 3.6.5. " We have developed/defined TIDL library layers based on the layer types Caffe framework. Most of our test cases (Layer level and network level) and demos are based caffe framework. With respect to Tensorflow, we have validated two pre-trained models from tensorflow github (Slim based Mobilenet V1 and Googlenet/inceptionetV1), this covers most of the CNN layers (Convolution, Max Pooling , Average pooling, Batch norm, Fully connected layer, softmax, Relu, Relu6, concate etc). " Thanks, Praveen
+

sample_embedding_folder/1002851.txt

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+Ticket Name: TDA2E: Counting an external signal edge
+
+Query Text:
+Part Number: TDA2E Other Parts Discussed in Thread: MMWCAS-DSP-EVM Hello. I need to count the rise or falling edges of an external clock signal which frequency is up to 300 kHz using the TDA2xx on the MMWCAS-DSP-EVM board (I just use the Ethernet peripheral so I can unmount lot of components if necessary). As you can imagine using an interrupt approach is not reliable at such high frequency, so, I intend to use a counter module that directly writes into a register the number of time the specific edge arrives. I took a look into "Timers" chapter inside TRM document (SPRUI29G) but it seams there is no way to increment the counter register using an external source. Could somebody provide me some guide? Which other module can I use to reach my goal? Thanks in advice, Pablo.
+
+Responses:
+Hi, You can refer to TRM Ch 28 PWM which has eCAP to capture input signal. However, you have to check if EVM has exposed any pin which is routed to eCAP. https://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/linux/Foundational_Components/Kernel/Kernel_Drivers/Display/PWM.html Regards, Stanley
+

sample_embedding_folder/1004827.txt

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+Ticket Name: TDA4VM: Linux OS memory size
+
+Query Text:
+Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hello Jacinto team, My customer is considering TDA4 for its Automotive Vision application, and they are asking me about the size that Linux OS takes on theTDA4 SoC: from previous experience with TDA2, they know Linux took ~1Gb of Flash memory. Do you know what is the memory requirement for Linux OS on TDA4 ? Best regards, Antoine
+
+Responses:
+Hi Antoine, This is the output of free command on our latest 7.3 Linux SDK. So ~1 GB with Linux. ~3GB is free out of total 4GB DDR on board. If no other questions please click verify answer. Best Regards, Keerthy
+

sample_embedding_folder/1005296.txt

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+Ticket Name: TDA2SX: how to use Image pyramid algorithm link in vision sdk for tda2
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 I want to use Image pyramid algorithm link in vision sdk for tda2, this algorithm link is supported on M4, but the comment for this algorithm link in algorithmLink.h says: "Image pyramid algorithm link. Only valid for TDA3x" typedef enum { ALGORITHM_LINK_IPU_ALG_DMA_SWMS = 0, /**< Alg to DMA based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_OBJECT_DRAW = 1, /**< Alg to draw rectangles on the image (Needed by PD) */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB = 2, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB1 = 3, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_HW_CRC = 4, /**< CRC for checking Frame Freeze Detect on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_IMG_PYRAMID = 5, /**< Image pyramid algorithm link. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_SCENE_OBSTRUCTION_DETECT = 6, /** < Alg to perform SCENE obstruction detection */ ALGORITHM_LINK_IPU_ALG_DEWARP = 7, /**< Plugin to that supports DeWarpping of images, depends on SIMCOP/TDA3x*/ ALGORITHM_LINK_IPU_ALG_RADAR_PROCESS = 8, /**< Alg to perform radar processing */ ALGORITHM_LINK_IPU_ALG_RVC_DIAGNOSTIC = 9, /**< Plugin to support Robust RVC diagnostics register only for TDA2xx */ ALGORITHM_LINK_IPU_ALG_OPENVX = 10, /**< Pluging to support OpenVX */ ALGORITHM_LINK_IPU_ALG_TIDLPREPROC = 11, /**< Alg to do TIDL Pre Process */ ALGORITHM_LINK_IPU_ALG_VPE_SWMS = 12, /**< Alg to VPE based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB2 = 13, /**< AEWB for ISS running on IPU1-0 in SRV demo. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_OPENVX_TIDL = 14, /**< Pluging to support OpenVX TIDL */ ALGORITHM_LINK_IPU_ALG_MAXNUM = 15, /**< Should be the last value of this enumeration. * Will be used by Link/driver for validating the input parameters. */ ALGORITHM_LINK_IPU_ALG_FORCE32BITS = 0x7FFFFFFF /**< This should be the last value after the max enumeration value. * This is to make sure enum size defaults to 32 bits always regardless * of compiler. */ } AlgorithmLink_IpuAlgorithmId; I don't know why this link is not valid for tda2x. If I want to use this LINK for tda2x , how to do ? thanks
+
+Responses:
+This is duplicate of below thread, so closing this thread. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1005297/tda2sx-how-to-use-image-pyramid-algorithm-link-in-vision-sdk-for-tda2 Regards, Brijesh
+

sample_embedding_folder/1005297.txt

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+Ticket Name: TDA2SX: how to use Image pyramid algorithm link in vision sdk for tda2
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 I want to use Image pyramid algorithm link in vision sdk for tda2, this algorithm link is supported on M4, but the comment for this algorithm link in algorithmLink.h says: "Image pyramid algorithm link. Only valid for TDA3x" typedef enum { ALGORITHM_LINK_IPU_ALG_DMA_SWMS = 0, /**< Alg to DMA based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_OBJECT_DRAW = 1, /**< Alg to draw rectangles on the image (Needed by PD) */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB = 2, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB1 = 3, /**< AEWB for ISS running on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_HW_CRC = 4, /**< CRC for checking Frame Freeze Detect on IPU1-0. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_IMG_PYRAMID = 5, /**< Image pyramid algorithm link. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_SCENE_OBSTRUCTION_DETECT = 6, /** < Alg to perform SCENE obstruction detection */ ALGORITHM_LINK_IPU_ALG_DEWARP = 7, /**< Plugin to that supports DeWarpping of images, depends on SIMCOP/TDA3x*/ ALGORITHM_LINK_IPU_ALG_RADAR_PROCESS = 8, /**< Alg to perform radar processing */ ALGORITHM_LINK_IPU_ALG_RVC_DIAGNOSTIC = 9, /**< Plugin to support Robust RVC diagnostics register only for TDA2xx */ ALGORITHM_LINK_IPU_ALG_OPENVX = 10, /**< Pluging to support OpenVX */ ALGORITHM_LINK_IPU_ALG_TIDLPREPROC = 11, /**< Alg to do TIDL Pre Process */ ALGORITHM_LINK_IPU_ALG_VPE_SWMS = 12, /**< Alg to VPE based SW Mosaic */ ALGORITHM_LINK_IPU_ALG_ISS_AEWB2 = 13, /**< AEWB for ISS running on IPU1-0 in SRV demo. Only valid for TDA3x */ ALGORITHM_LINK_IPU_ALG_OPENVX_TIDL = 14, /**< Pluging to support OpenVX TIDL */ ALGORITHM_LINK_IPU_ALG_MAXNUM = 15, /**< Should be the last value of this enumeration. * Will be used by Link/driver for validating the input parameters. */ ALGORITHM_LINK_IPU_ALG_FORCE32BITS = 0x7FFFFFFF /**< This should be the last value after the max enumeration value. * This is to make sure enum size defaults to 32 bits always regardless * of compiler. */ } AlgorithmLink_IpuAlgorithmId; I don't know why this link is not valid for tda2x. If I want to use this LINK for tda2x , how to do ? thanks
+
+Responses:
+Hi, It was initially implemented using resizer, which is available on TDA3x. But could you please if it internally uses VPE driver? Then it can even be enabled on TDA2x. Regards, Brijesh
+

sample_embedding_folder/1005841.txt

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+Ticket Name: TDA2PXEVM: TIDL Import Tool and Inference on the TDA2Px EVM
+
+Query Text:
+Part Number: TDA2PXEVM Hello, I am trying to run custom deep learning models on the TDA2Px EVM. As I understand, in order to run Deep Learning models on the board, TIDL library is used. The TIDL import tool generates binary files that represent the network and parameters of the model. What I also understand from this step is that the tool translates the input model from a framework like TensoFlow to a format that can be executed on DSP and EVE cores. When I tried to understand how to use the generated files for inference on the board, I found section 3.3.4 (Building the Test Application Executable through GMAKE) in the TIDL library which discusses how to load the .out files of the sample test application on the DSP and EVE cores using Code Compuser Studio (CCS). I want to understand these points: - What is the link between the TIDL import tool output binary files and building the .out files (dsp_test_dl_algo.out and dsp_test_dl_algo.out) for inference on the board ? The user guide states that for building the sample test application project I should execute the command (gmake CORE=dsp all) for DSP and (gmake CORE=eve all) for EVE. What about a different custom model ? What changes should I make and how to link the translated model by the TIDL import tool in order to build the (dsp_test_dl_algo.out and eve_test_dl_algo.out) files for my custom model? - Is there a way to run the .out files on the board without using CCS ? I want to run the models on the board using only a terminal, is it possible ? - Is there a specific OS that should be installed on an SD card for booting the board to run TIDL applications ? - I am facing some issues for setting a stable workflow for model deployment on TDA2PX EVM. I usually have custom trained deep learning models in TensorFlow and I am trying to deploy those models on the TDA2Px EVM. If there are any documentations or tutorials in addition to the provided user guides, please let me know. Thanks, Ahmed Anwar
+
+Responses:
+Hi Ahmed Anwar, 1. There is no dependency on "TIDL import tool output binary files" for building the .out files, these bin files are input which you need to specify in the infer config file. 2. Yes, you can run TIDL on the board without CCS, for that refer to TIDL OD usecase in the Vision SDK. 3. No, just follow the steps in Vision SDK user guide. 4. Refer to TIDL usecases section in the Vision SDK user guide. Overall, you can run TIDL on the board without CCS by using TIDL usecases, I would recommend to run the existing usecase as is first and once it is working then replace the "params" and "net" binary files in the SD card with your bin files and run. You can also refer to below e2e thread to import and run our pre-trained SSD model in the TIDL OD usecase. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/689617/tda2-how-to-run-ssd-based-tidl-od-use-case-in-vision-sdk-with-pre-trained-model Thanks, Praveen
+
+Hi Praveen, Thank you for your reply. I would like to understand these points: - What is the usage of the .out files (dsp_test_dl_algo.out and dsp_test_dl_algo.out) ? As I understand, I need only the network and parameters .bin files for running a model on the board using TIDL usecases.Would you please let me know what the usage of the .out files is ? Do I need them or just I need the .bin files ? - In the Vision SDK TIDL User Guide, in section 5 "Build and Run TIDL Object detect use case", these statements are present: "The TIDL Object detect use case is enabled and runs on TDA2XX SoC only." "Build the Vision SDK for TDA2XX BIOS configuration choosing the ‘MAKECONFIG?=tda2xx_evm_bios_all’ in the Rules.make." "Please refer to the ‘VisionSDK_UserGuide_TDA2xx.pdf’ for steps on building and running the Vision SDK." I am using TDA2PX, not TDA2XX. Does this mean that I can not run TIDL models and usecases on TDA2PX ? If TDA2PX supports TIDL usecases, should I follow "VisionSDK_UserGuide_TDA2xx.pdf" as stated or "VisionSDK_UserGuide_TDA2px.pdf’" ? Thanks, Ahmed Anwar
+
+Hi, >> What is the usage of the .out files (dsp_test_dl_algo.out and dsp_test_dl_algo.out) ? These .out files are required to when you connect the board to CCS and run TIDL on CCS based setup, but if you want to run TIDL without CCS then these .out files are not required. >> I am using TDA2PX, not TDA2XX. Does this mean that I can not run TIDL models and usecases on TDA2PX ? No, you can run TIDL models and usecases on TDA2PX, please refer to "VisionSDK_UserGuide_TDA2px.pdf" file. FYI, many customers were successfully able to run TIDL usecases on TDA2PX, you can search in the e2e for those threads as reference. I have shared few threads https://e2e.ti.com/support/processors-group/processors/f/processors-forum/867915/tidl_od-usecase-on-tda2px?tisearch=e2e-sitesearch&keymatch=TDA2PX# https://e2e.ti.com/support/processors-group/processors/f/processors-forum/714606/linux-tda2pxevm-issue-in-running-vision-sdk-demo-application-on-tda2px?tisearch=e2e-sitesearch&keymatch=TDA2PX# Thanks, Praveen
+
+Does That mean I Can't Run TIDL use cases on Vision SDK Linux or in other words I must use the "MAKECONFIG?=tda2Px_evm_bios_all" configration but I can't use the "MAKECONFIG?=tda2xx_evm_linux_all" configuration? Thanks, Kirollos Henry
+
+You can but you have to set OPENVX_INCLUDE=y in ~/vision_sdk/apps/configs/tda2px_evm_linux_all/cfg.mk.
+
+Thank you so much I was able to Solve that issue Best Regards, Kirollos Henry
+

sample_embedding_folder/1006960.txt

@@ -0,0 +1,28 @@
+Ticket Name: TDA2SG: TDA2 LCD2 BT656 signal
+
+Query Text:
+Part Number: TDA2SG Other Parts Discussed in Thread: TDA2 Hi Sir : TDA2 output BT.656 signal, when converted to BT.601 signal. Hsync will output all the time. If Vsync is low and Hsync is low, how do I set it?
+
+Responses:
+Hi, Do you mean, you dont want hsync to be toggling when vsync is low? If this is the case, you could treat DE signal as inverted hsync. DE will toggle only during active video portion. Regards, Brijesh
+
+Hi Brijesh : The hardware only has Hsync and Vsync and PCLK and ATA [7:0] pins, no DE output. The image had the output I wanted.
+
+Hi Pierre Hsieh, hsync will toggle during vsync, this cannot be changed. In this case, you need to use DE line. Regards, Brijesh
+
+Hi Brijesh : I cannot modify the BT656 configuration of TDA2 to output the desired signal?
+
+Hi Pierre Hsieh, Hsync is supposed to toggle even during vsync inactive period.. This behavior cannot be changed. Regards, Brijesh
+
+Hi Brijesh : BT.656 does not have a DE Line specification. How can I convert to BT.601 with DE Line?
+
+Hi Pierre Hsieh, BT656 does not even output hsync and vsync, so we cannot use hsync/vsync signals for BT656. We have to use discrete sync output mode in order to get sync signals. and when we enable discrete sync signals, we will also get DE signal. Regards, Brijesh
+
+Hi Brijesh : This TDA2 hardware configuration, Display Subsystem DPI2 output BT.656, only output Data and PCLK signal lines. Analyze Bt.656, there will still be H Active in V Blanking. TDA2 can output on BT.656, the V Blanking signal is only H Blanking?
+
+Hi Pierre Hsieh, When you say BT656, it is embedded sync output format, and in this format, DSS does not output sync signals, so there will not be any hsync or vsync signals in bt656 output. So can you check if you are configuring DSS for discrete sync output? Regards, Brijesh
+
+Hi Brijesh : BT.605 does not have Hsync and Vsync, so I converted it to BT601 using FPGA. I used FPGA to convert TDA2 output BT.656 signal into BT.601 signal. I found that VBlanking has a HActive signal for BT.601 signal.
+
+Hi Pierre Hsieh, ok, in this case, you need to change FPGA. FPGA should out hsync correctly. This is not DSS question. Regards, Brijesh
+

sample_embedding_folder/1008079.txt

@@ -0,0 +1,20 @@
+Ticket Name: TDA2SG: How can output yuv422 format in the display
+
+Query Text:
+Part Number: TDA2SG Hi ,expert: My system has three overlay in the display,like this : 1,VID1: BGRA32_8888 2.VID2: YUV420SP 3.GFX: BGRA32_8888 general, TDA2s use the rgb888 output to display, and my system is work ok,Now I want to use the yuv422( YUYV) to the display, I see the "dssm2mwb" link ,I found this link may need "sync" link and then use buftype of "SYSTEM_BUFFER_TYPE_VIDEO_FRAME_CONTAINER". I have the question as follow: 1,sync need 3 overlay framerate is same,but my system is not satisfy and overlay has different display framesrate, so i think this solution may not very well . 2,Is There other solution to yuv422 display output thanks!
+
+Responses:
+Hi, do you mean yuv422 over embedded sync output interface? Rgds, Brijesh
+
+no, I mean if i use sync link ,if one of queue has no video ,sync will no send cmd to process ,so I think this solution is not suit. Now I want to checkout the problem: 1,VID1: BGRA32_8888 ->YUYV 2.VID2: YUV420SP 3.GFX: BGRA32_8888 ->YUYV overlay like this,the display can work? 2) Is there some usecase of yuv422 output I can refer
+
+hi, #1, in this case, you would require to change sync link to support this feature. Currently it is not supported. sync link does not output if one of the input is not available. #2, do you mean to use 3 video pipelines, each with different data type? yes, display will work with this combination #3, where yuv422 do you require? Is it at the output of capture link or input to the display link? Regards, Brijesh
+
+output in the dispaly link , if i dont want to use "sync",I will do as follow: change RGBA328888 to YUYV format and it will make 3 video pipeline dataformat to 1,VID1: YUYV 2.VID2: YUV420SP 3.GFX: YUYV is the display link support "YUYV" and "YUV420sp" format output.
+
+Yes, display link supports both of these formats. Rgds, Brijesh
+
+I use capture_dsswb link ,and set vout format BT656 and DISPC_VP1_CONTROL.TDMENABLE = 0x1: TDM enabled DISPC_VP1_CONTROL. TDMPARALLELMODE = 0x0: 8-bit parallel output interface selected DISPC_VP1_CONTROL. TDMCYCLEFORMAT = 0x2: 2 cycles for 1 pixel DISPC_DATA1_CYCLE1 = 0x8 DISPC_DATA1_CYCLE2 = 0x8 DISPC_DATA1_CYCLE3 = 0x0 but my capture_dsswb has no video data,so I think writeback pipeline do not well work. how can I use writeback?
+
+Hi, these two things are different and independent. could you help me with what exactly you are trying to enable? - are the three input video pipelines enabled? - why are you enabling TDM for BT656 output? - why are you enabling dss wb path? Regards, Brijesh
+

sample_embedding_folder/1011115.txt

@@ -0,0 +1,10 @@
+Ticket Name: TDA4VM: TDA4 RTOS SDK network utilities
+
+Query Text:
+Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 Hi, In TDA4 RTOS SDK, do we have something similar as the TDA2.TDA3's network_rx, network_tx tools ? I saw that we have some ETHFW demo involving Plex media server but I just need a simple client/server example app that is able to save a file on PC over ethernet. regards, Victor
+
+Responses:
+Hi Victor, No simple utility on RTOS of the kind you are looking for. Can you spell out your requirement : Do you want to stream a file from your EVM to your PC ? or do you want to use the CPSW 9G as a switch and connect multiple devices over it ? Regards Vineet
+
+Hi Vineet, I actually implemented the tool since it didn't exist on TDA4. The ticket can be closed. Thanks. regards, Victor
+

sample_embedding_folder/1012640.txt

@@ -0,0 +1,14 @@
+Ticket Name: TDA2SX: TDA2SXBU PMIC Selection
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi Expert, Could TDA2SXBU PMIC Select TPS659039-O9039A387? If TDA2SXBU PMIC could not select TPS659039-O9039A387,do you have any suggestions? Thanks Daniel
+
+Responses:
+Hi Daniel, Sorry for the delay. Is this issue still open ? Regards Vineet
+
+Hi Vineet Issue is still open. Could you help me? Thanks Daniel
+
+Hi Daniel, Will take a look at this internally and get back. Regards Vineet
+
+Vineet, We recommend the PMIC that is implemented on the TDA2 EVM. Regards, Kyle
+

sample_embedding_folder/1013160.txt

@@ -0,0 +1,43 @@
+Ticket Name: TDA2SX: Tda2s SPI slave mode reception problem
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hello, expert Tda2s is SPI slave mode. If the master sends a 1MHz clock and sends 140 bytes every 20ms, it will get stuck after receiving several times. If it sends 32 bytes every time, it will not get stuck. If it sends 32 bytes every 10ms, it will still receive several times of data and it will get stuck. dmesg1.txt   146 root      0:00 [kworker/0:1H]
+  148 root      0:00 cat /proc/kmsg
+  149 root      0:00 ps
+root@dra7xx-evm:/app# 
+root@dra7xx-evm:/app# 
+root@dra7xx-evm:/app# 
+root@dra7xx-evm:/app# 
+root@dra7xx-evm:/app# ./spi_rev_tool_32 -D  /dev/spidev1.0  -s 1000000 -b 8
+[   36.808325] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0
+[   36.809212] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0
+[   36.810092] spidev spi1.0: setup mode 0, 8 bits/w, 1000000 Hz max --> 0
+<7>[   36.808304] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal
+<4>[   36.808325] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0
+<7>[   36.809182] spidev spi1.0: spi mode 0
+<7>[   36.809198] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal
+<4>[   36.809212] spidev spi1.0: setup mode 0, 8 bits/w, 48000000 Hz max --> 0
+<7>[   36.810065] spidev spi1.0: 8 bits per word
+<7>[   36.810079] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal
+<4>[   36.810092] spidev spi1.0: setup mode 0, 8 bits/w, 1000000 Hz max --> 0
+<7>[   36.810946] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz
+<7>[   36.810973] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal
+RX | 4D 56 00 00 10 9A 00 00  | MV...?.
+RX | 01 01 00 00 00 00 00 00  | ........
+RX | 00 00 00 00 00 00 00 00  | ........
+RX | 00 00 00 00 00 00 00 00  | ........
+RX | 00 00 00 00 00 00 00 00  | ........
+RX | 00 00 00 00 00 00 00 00  | ........
+RX | 00 00 00 00 00 00 00 00  | ........
+RX | 00 00 00 00 00 00 00 00  | ........
+<7>[   36.826262] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal
+<7>[   36.826462] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz
+<7>[   36.826487] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal
+<7>[   36.827021] spidev spi1.0: setup: speed 48000000, sample leading edge, clk normal
+<7>[   36.827126] spidev spi1.0:   xfer len 32 rx tx 8bits 0 usec 1000000Hz
+<7>[   36.827149] spidev spi1.0: setup: speed 1000000, sample leading edge, clk normal
+ I add printing when I can't receive hand data, it's stuck in SPI_ transfer_ one_ message()---->master-transfer_ one(). How to find the problem? The problem of the master side has been ruled out, and the measurement SPI CLK CS is normal.
+
+Responses:
+Hi, Our Linux SDK doesn't support SPI slave mode. It has not been validated on TDA2 EVM. Regards, Stanley
+

sample_embedding_folder/1013431.txt

@@ -0,0 +1,16 @@
+Ticket Name: TDA2PXEVM: roscore run error on my TDA2Px-EVM due to python version
+
+Query Text:
+Part Number: TDA2PXEVM Hi all, I am trying to run ROS on my TDA2Px-EVM so, I have done this clone: git clone git://arago-project.org/git/projects/oe-layersetup.git tisdk Then this configuration and build: ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-06.03.00.106-config.txt cd build . conf/setenv export TOOLCHAIN_PATH_ARMV7=$HOME/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf export TOOLCHAIN_PATH_ARMV8=$HOME/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu MACHINE=dra7xx-evm bitbake arago-base-tisdk-image This Arago project was running just fine. Then I went to the meta-ros layer and created that file in recipes-core/images: require recipes-core/images/arago-base-tisdk-image.bb export IMAGE_BASENAME = "ros-base-image" DESCRIPTION = "An image with packagegroup-ros-world installed" IMAGE_INSTALL = "packagegroup-core-boot ${CORE_IMAGE_EXTRA_INSTALL}" IMAGE_LINGUAS = " " LICENSE = "MIT" inherit core-image IMAGE_ROOTFS_SIZE = "8192" IMAGE_INSTALL += "packagegroup-ros-world" And named that file ros-base-image.bb Then I ran that build command: MACHINE=dra7xx-evm bitbake ros-base-image This build finished with no errors And I also was able to boot the board with no issues When the board Started I exported these variables: export ROS_ROOT=/opt/ros export ROS_DISTRO=indigo export ROS_PACKAGE_PATH=/opt/ros/indigo/share export PATH=$PATH:/opt/ros/indigo/bin export LD_LIBRARY_PATH=/opt/ros/indigo/lib export PYTHONPATH=/opt/ros/indigo/lib/python3.5/site-packages export ROS_MASTER_URI=http://localhost:11311 export CMAKE_PREFIX_PATH=/opt/ros/indigo touch /opt/ros/indigo/.catkin When I try to run roscore I got an error no module named xmlrpc as if it is trying to run for python2 and not python3 although the one installed is python3 I spent a couple of days trying to solve this but I am always having same error. And also I was not able to follow that guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf Because my machine is running on ubuntu 18 and this guide required ubuntu 14 host machine Thank you so much. Best regards, Kirollos Henry I have done this clone: git clone git://arago-project.org/git/projects/oe-layersetup.git tisdk Then this configuration and build: ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-06.03.00.106-config.txt cd build . conf/setenv export TOOLCHAIN_PATH_ARMV7=$HOME/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf export TOOLCHAIN_PATH_ARMV8=$HOME/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu MACHINE=dra7xx-evm bitbake arago-base-tisdk-image This Arago project was running just fine. Then I went to the meta-ros layer and created that file in recipes-core/images: require recipes-core/images/arago-base-tisdk-image.bb export IMAGE_BASENAME = "ros-base-image" DESCRIPTION = "An image with packagegroup-ros-world installed" IMAGE_INSTALL = "packagegroup-core-boot ${CORE_IMAGE_EXTRA_INSTALL}" IMAGE_LINGUAS = " " LICENSE = "MIT" inherit core-image IMAGE_ROOTFS_SIZE = "8192" IMAGE_INSTALL += "packagegroup-ros-world" And named that file ros-base-image.bb Then I ran that build command: MACHINE=dra7xx-evm bitbake ros-base-image This build finished with no errors And I also was able to boot the board with no issues When the board Started I exported these variables: export ROS_ROOT=/opt/ros export ROS_DISTRO=indigo export ROS_PACKAGE_PATH=/opt/ros/indigo/share export PATH=$PATH:/opt/ros/indigo/bin export LD_LIBRARY_PATH=/opt/ros/indigo/lib export PYTHONPATH=/opt/ros/indigo/lib/python3.5/site-packages export ROS_MASTER_URI=http://localhost:11311 export CMAKE_PREFIX_PATH=/opt/ros/indigo touch /opt/ros/indigo/.catkin When I try to run roscore I got an error no module named xmlrpc as if it is trying to run for python2 and not python3 although the one installed is python3 I spent a couple of days trying to solve this but I am always having same error. And also I was not able to follow that guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf Because my machine is running on ubuntu 18 and this guide required ubuntu 14 host machine Thank you so much. Best regards, Kirollos Henry I have done this clone: git clone git://arago-project.org/git/projects/oe-layersetup.git tisdk Then this configuration and build: ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-06.03.00.106-config.txt cd build . conf/setenv export TOOLCHAIN_PATH_ARMV7=$HOME/gcc-arm-8.3-2019.03-x86_64-arm-linux-gnueabihf export TOOLCHAIN_PATH_ARMV8=$HOME/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu MACHINE=dra7xx-evm bitbake arago-base-tisdk-image This Arago project was running just fine. Then I went to the meta-ros layer and created that file in recipes-core/images: require recipes-core/images/arago-base-tisdk-image.bb export IMAGE_BASENAME = "ros-base-image" DESCRIPTION = "An image with packagegroup-ros-world installed" IMAGE_INSTALL = "packagegroup-core-boot ${CORE_IMAGE_EXTRA_INSTALL}" IMAGE_LINGUAS = " " LICENSE = "MIT" inherit core-image IMAGE_ROOTFS_SIZE = "8192" IMAGE_INSTALL += "packagegroup-ros-world" And named that file ros-base-image.bb Then I ran that build command: MACHINE=dra7xx-evm bitbake ros-base-image This build finished with no errors And I also was able to boot the board with no issues When the board Started I exported these variables: export ROS_ROOT=/opt/ros export ROS_DISTRO=indigo export ROS_PACKAGE_PATH=/opt/ros/indigo/share export PATH=$PATH:/opt/ros/indigo/bin export LD_LIBRARY_PATH=/opt/ros/indigo/lib export PYTHONPATH=/opt/ros/indigo/lib/python3.5/site-packages export ROS_MASTER_URI=http://localhost:11311 export CMAKE_PREFIX_PATH=/opt/ros/indigo touch /opt/ros/indigo/.catkin When I try to run roscore I got an error no module named xmlrpc as if it is trying to run for python2 and not python3 although the one installed is python3 I spent a couple of days trying to solve this but I am always having same error. And also I was not able to follow that guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf Because my machine is running on ubuntu 18 and this guide required ubuntu 14 host machine Thank you so much. Best regards, Kirollos Henry
+
+Responses:
+Hi Kirollos, We will get back to you in couple of days. Thanks for your patience. Best Regards, Keerthy
+
+Kirollos, There are two main questions in your post. -1- Issue with running roscore with an updated image "ros-base-image" that you have created - the issue with xmlrpc. Unfortunately, this issue is very custom to your changes and you will have to debug this issue by yourself. Note that ROS integration is not a default on the SDK and we are quite unfamiliar with this error and will need more debug on the specific changes that you have done at your end. -2- And also I was not able to follow that guide: Sorry, what are you not able to follow in this guide? Yes, the SDK is dependent on Ubuntu 14.04 and it is recommended that you use the mentioned version to recreate the SDK successfully. Regards Karthik
+
+Hello Karthik, I want to know how much disk space is required to build yocto file system using this guide as I started building it by commenting the host check part in the script but I reached only 20% and took about 100GB of my disk space. I want to know how much disk space I have to free for this. Best regards, Kirollos Henry
+
+Hi Kirollos, 20% competion and 100GB of disk space doesn't sound quite right. But usually a single build needs about 150GB-200GB of disk space for the full build. Regards Karthik
+
+Hi Karthik, Thank you so much I was able to run roscore after some changes on the board using the steps I have previously done
+

sample_embedding_folder/1013586.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA2PXEVM: Installing ROS on TDA2PXEVM after building Yocto filesystem
+
+Query Text:
+Part Number: TDA2PXEVM Hello all, I have built Yocto filesystem on my TDA2Px using this guide: https://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/6_00_00_03/exports/wiki/Processor%20SDK%20Linux%20Automotive%20Software%20Developers%20Guide%20-%20Texas%20Instruments%20Wiki.pdf I want to know how can I add ROS layer and build Yocto again with ROS installed and have ROS running on my TDA2Px-EVM. Or in other word how can I customize a ROS layer or is there any guide for that? Thank you, Best Regards, Kirollos Henry
+
+Responses:
+Kirollos, It seems like you have made progress on the ROS image already: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1013431/tda2pxevm-roscore-run-error-on-my-tda2px-evm-due-to-python-version. There is no guide for integrating ROS with TDA2Px - most of our experiments with ROS were experimental and since both TI SDK and ROS were moving quite a bit we didn't snapshot a stable version and document the same. Lets continue discussion on the newer thread. Closing this one for now. Regards Karthik
+

sample_embedding_folder/1014661.txt

@@ -0,0 +1,10 @@
+Ticket Name: TDA2SA: Is there a Code Composer Studio(CCS) project existing to build the "VISION SDK/project" on OS (Linux/or windows) Platform ?
+
+Query Text:
+Part Number: TDA2SA Other Parts Discussed in Thread: TDA2 Hi Expert, My platform is TDA2 I want to confirm again. Is there a Code Composer Studio(CCS) project existing to build the "VISION SDK/project" on OS (Linux/or windows) Platform ? Thanks Daniel
+
+Responses:
+Hi Expert Is there any update? Thanks Daniel
+
+Hi, No, we use commend line and makefile to build Vision SDK. CCS build takes longer time than command-line build/makefile build. Regards, Stanley
+

sample_embedding_folder/1015551.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA2SX: pressure test script / software
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi At present, we are preparing to do tda2sx ddr3l pressure test,Do you have tda2 ddr3l pressure test script / software? If there is no script, what should I do for stress testing?If we want to develop stress testing software, how to raise the corresponding software requirements? Please help me give some advice. Thank you!
+
+Responses:
+Hi, There is nothing provided outside of what may exist in the SDKs. What operating system does your application use? Thanks, Kevin
+

sample_embedding_folder/1015553.txt

@@ -0,0 +1,28 @@
+Ticket Name: TDA2P-ACD: Custom calibration tool for 2D SRV
+
+Query Text:
+Part Number: TDA2P-ACD Other Parts Discussed in Thread: TDA2 Hi all, I am trying to make a custom calibration tool for 2D surround view in Python with OpenCV that would match the existing one developed in Matlab. So far, I managed to implement the same workflow and to obtain the parameters of initial perspective metrices for 4 cameras with stitched bird view as shown in the image below. As can be seen, the bird view image is decent. However, when I provide the obtained perspective matrices (scaled to match Q11.20 format that I believe is used in GeometricAlignment and Sythesis algorithms), I get the result which is not even comparable to the one shown above, i.e., everything is distorted. This indicates that matrix parameters are wrong or incorrectly interpreted. To confirm that the perspective matrix coefficients are correct I used the same values in another framework (Octave) and I get nice bird view for each camera (I provide a view for front camera below). The question is what I am doing wrong and why I do not get (at least to some extent) correct bird view on the target? Best regards, Mladen
+
+Responses:
+Just an additional note. I also tried to use perspective matrix generated by the tool for provided sample images in both Python and Octave. All I got is also distorted indicating that the TI tool does not provide the matrix coefficients expected by OpenCV warpPerspective() and Octave imperspectivewarp().
+
+Did you compare bin files from your python with the bin files from TI tool?
+
+Hi Do-Kyoung Kwon, I am not sure what bin files are you referring to. Currently, I am trying to get initial perspective matrices that would be comparable with the one obtained from TI tool. So far I found out that OpenCV and Octave functions returns forward mapped homographies, however, the SV algorithm is based on back-mapping. Therefore, I tried to use inverse matrices, but it seems that it does not work either. Now I suspect it has something with translating the image center to 0 instead of (width/2, height/2).
+
+Oh.. I now realized that you are working on SRV on TDA2. I thought you are working on SRV on TDA4.
+
+Right. It is 2D surround view running on C66.
+
+I think image center could be a reason. There might be no issue with perspective matrices give that you got the right reconstruction for the upper part of SRV. But it seems hard to say without debugging.
+
+Actually, I got the right reconstruction on all 4 views as you can see in the first image (this is an output from Python tool). The issue arises when I provide the obtained matrices to the usecase (GeometricAlignment link) or to the Surroundview.exe tool for further perspective matrices tuning. It seems that those initial matrices are not in the form expected by the current implementation. I will also check for the image centers, but anyway, thank you for your time.
+
+Great to hear that you resolve the issue.
+
+No, the issue is still unresolved. I am chasing the way to adjust the perspective matrices to match the required format.
+
+I figured this out. Image centers are just one side of the coin. Input images relative to output view orientation should be considered as well. Obviously, a rule for feature points (corners selected in reference image and input images) correspondence I used in my custom tool is different from the one in the TI tool, so I had to add some rotations to the input images (and output results) to match them. It is very specific to my case, but it would be informative if you could share somewhere in the documentation how the corners selected in the tool on reference image corresponds to the corners selected on the input images for each camera view.
+
+Great! Thanks for the suggestion, too!
+

sample_embedding_folder/1015697.txt

@@ -0,0 +1,38 @@
+Ticket Name: How to burn the sd card file to emmc Tda2ex-17 (SDK V03.08)
+
+Query Text:
+Other Parts Discussed in Thread: TDA2, SYSBIOS Dear all, I'm just a beginner As shown in the title! Currently only use sd card to boot I’m not sure about the creation process and other settings like uenv-emmc.txt May I ask which document is talking about how to burn the emmc part? I don’t know the first thing to know and what to do at the beginning Although there are many related issues But is there a detailed document for reference? The part about burning into emmc! Can anyone give me some suggestions on the above issues ===================================================================== And how to enter terminal like => root@dra7xx-evm:~# Beacuse I put sd card into board and starting My log starts directly here ------------------------------------------------ TDA2Ex SBL Boot DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed TI EVM PAD Config Completed DDR Config Completed App Image Download Begins SD Boot - file open completed successfully MPU CPU0 Image Load Completed IPU1 CPU0 Image Load Completed IPU1 CPU1 Image Load Completed IPU2 CPU0 and CPU1 Image Load Completed .....................etc -------------------------------------------------------------- I’m not sure how to get in root@dra7xx-evm:~# Which paragraph may I have missed The above are some of my questions. Please help me . VERY THANKS!!
+
+Responses:
+Dear all, Please tell me if there is something unclear Thanks!
+
+Dear all, By the way , when I was in Bulid The different settings are MAKECONFIG=tda2xx_evm_linux_all => MAKECONFIG=tda2ex_evm_bios_all
+
+Dear all, Is it because we are a custom board? Because some related settings are not done and directly with your EV setting to run, so there is no way to run to => root@dra7xx-evm:~# Is it? What can I do about those related settings? Are there other documents or suggestions?
+
+Dear all, 【Supplement】 And my VisionSDK_Linux_UserGuide.pdf did 4 .3 steps But the log does not show anything Next However I did VisionSDK_UserGuide_TDA2Ex.pdf
+Some later steps gmake -s sbl and gmake -s appimage
+Generate MLO and appimage to overwrite the original MLO (without apimage) Have Log ------------------------------------------------ TDA2Ex SBL Boot DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed etc.... --------------------------------------------- But VisionSDK_Linux_UserGuide.pdf did 4 .3 steps Why is there no system log?? Is there a problem? Because we are a custom board, what should I pay attention to and set?  
+
+If you set MAKECONFIG=tda2ex_evm_bios_all and build "gmake -s sbl", the MLO is for the baremetal bootloader for TI-RTOS (SYSBIOS). For Linux, you should set MAKECONFIG=tda2xx_evm_linux_all. However, sbl build is only for RTOS, not Linux. To build the bootloader (spl/u-boot) for Linux, you have to build from linux u-boot on Ubuntu PC. VisionSDK_Linux_UserGuide.pdf has all the steps documented. You have to follow the steps from the beginning to set up Linux build environment. Regards, Stanley
+
+Dear Stanley, Step1 !!! I did the steps above in the document (VisionSDK_Linux_UserGuide.pdf) And my MAKECONFIG is tda2ex_evm_linux_all I have done step 4.2,Then burn it into the SD card When I put it in our coustom board, """ there is no log """ =================================================================== Step2 !!! Then I did another thing I will overwrite the MLO and put in appimage built by the window => tda2ex_evm_bios_all  (These two files are completed under the window ) But there is a log out Like this ------------------------------------------------ TDA2Ex SBL Boot DPLL Configuration Completed Clock Domain Configuration Completed Module Enable Configuration Completed etc.... --------------------------------------------- ============================================================================== The key problem is!! when I was in step 1!!! Why did I complete 4.2 and put the sd card into our costom board and there is no log display???? Why did I do the second experiment but it works like this(Step2 !!!) ? Is there something wrong?? I have followed VisionSDK_Linux_UserGuide.pdf, but the 4.3 step is still unsuccessful Thanks!!!!!
+
+One possibility is that Linux u-boot SPL (MLO) got stuck since you were booting the MLO for EVM on the custom board. Do you have JTAG to connect the device and check what is going on with debugger? You can use Lauterbach JTAG with Trace32 or XDS560v2 JTAG with CCS to debug. Regards, Stanley
+
+Dear, Q1. So it may be the relationship of the custom board? Because it doesn’t match with MLO?? =============================================================== Q2.in addition ,If Q1 is right I want to ask, is it because some need to be set according to our board? Is there any direction to tell me what needs to be modified? ============================================================= I will learn about the debug method and try it out Please tell me these two answers Thanks!!
+
+Q1: Yes Q2: You have to identify what is different between your board and EVM. For example, if DDR is different, you have to update EMIF configuration or the access to DDR may not work. There are other things like Pin mux, PMIC, and etic. Regards, Stanley
+
+Thank you!!
+
+Dear Stanley, I want to check some places Please help me with these problems ================================================================ Q1 : Would like to ask how to determine if MLO has been executed? Q2: Where is the TDA uart port set? I also suspect that the port may be wrong, so I want to check Q3: Where is the MLO log printed? And where is the MLO source code ?? And where it started to run?? Q4: Where is the ROM code??, I want to know how the process of booting to MLO to display log is Q5: Is there any clear information about the boot process (part of the program)? ================================================================= If there is something wrong with the question I asked, please let me know Thank you !
+
+Dear Stanley, But the DDR of my RTOS is the same as LINUX DDR RTOS can see log but LINUX does not Just changed MLO, any other suggestions? Thanks!
+
+Dear Stanley, Can you help me this issue? Thanks!
+
+Dear Stanley, But the DDR of my RTOS is the same as LINUX DDR RTOS can see log but LINUX does not Just changed MLO, have any other suggestions? and I I opened another thread e2e.ti.com/.../3799935 Thanks!
+
+Could you download the pre-built binaries from the below link? http://software-dl.ti.com/infotainment/esd/jacinto6/processor-sdk-linux-automotive/latest/index_FDS.html boot-dra7xx-evm.tar.gz will include the MLO and u-boot. Can you try this on your board first?
+

sample_embedding_folder/1015916.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA4 capture output YUV420 format
+
+Query Text:
+Other Parts Discussed in Thread: TDA2 We use TDA4 and connect YUV422 camera. TDA2 can set capture input format YUV422 and capture output format YUV420. Can TDA4 set capture input format YUV422 and capture output format YUV420 ?
+
+Responses:
+Hi, No, VIP module in TDA2x can convert YUV422 to YUV420, but CSIRX cannot convert YUV422 to YUV420. You will require to use some other module like LDC or DSS for this conversion. Regards, Brijesh
+

sample_embedding_folder/1016368.txt

@@ -0,0 +1,20 @@
+Ticket Name: TDA2HF: About import tool sampleInData
+
+Query Text:
+Part Number: TDA2HF Hello， I have two questions about import configuration parameters: (1).does sampleInData support video input or multiple images ? (2).if sampleInData support,how to set and how to prepare the video and images? and other question about caffe-jacinto quantize test: I test the imagenet_jacintonet11v2_iter_160000.caffemodel and set quantize: true in deploy.prototxt, save the output of pool5, and then remove quantize: true only,save the output of pool5 again, the results are same."quantize: true" doesn't seem to work.So if quantize: true does work,What happens to the output? Thanks, chen poca
+
+Responses:
+Hi Chen poca, 1. You can set "numSampleInData" variable in the import config file and set "numFrames" variable in the infer config file for running multiple images. 2. You can concatenate multiple images to prepare the multiple image input The test results with and without quantize are available here in "caffe_jacinto_models\trained\image_classification\imagenet_jacintonet11v2" folder in the github (https://github.com/tidsp/caffe-jacinto-models), please refer to "run.log" in "test_quantize" and "test" folders. Thanks, Praveen
+
+hello, thank you for your replying. my reason to setting numSampleInData variable >1 is for import process not for inference.if numSampleInData>1,can I set sampleInData to multiple images?
+
+Yes
+
+so how to set multiple image to the sample InData ？using the txt file to list image path？or concatenate multiple images to one .y file？
+
+Concatenate multiple images to one .y file
+
+Sorry for the late reply and thank you for your answer.I have another question,if using multiple images to the sampleInData,would this improve the effect and generalization ability of the quantization?
+
+No
+

sample_embedding_folder/1016451.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA2PXEVM: Connect TDAPx-EVM to the internet
+
+Query Text:
+Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello all, I have TDAPx-EVM board and I was able to build Yocto file system and boot the board using the built yocto file system. I want to connect it to the internet, after connecting it to an Ethernet cable there is still no internet connection, so I want to know is anything I have to configure or what should I do to have and internet connection on my TDAPx-EVM Thank You, Best regards, Kirollos Henry
+
+Responses:
+Hi, Could you share the log from boot to linux kernel and the log from "ifconfig"? Did you change Linux kernel default config used by TDA2 SDK? Ethernet should be enabled already from the default config. Regards, Stanley
+

sample_embedding_folder/1024368.txt

@@ -0,0 +1,36 @@
+Ticket Name: TDA2SX: How to use VIP to receive 576I image?
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TVP5158, TVP5154, TDA2 Hi expert, Our company uses a custom board with SDK0305. The requirement is to receive 720*576I 4CH standard images. Q1:How can I make VIP capture receive 25 frame? If possible, Please provide suggestions for modification. Q2:I saw the 1CH TVP5158 driver in the SDK, Can I use TVP5158 driver to receive TVP5154? If possible, can I change it to 4CH? Q3:I am curious about the 25fps or 50field that Capture will receive?
+
+Responses:
+Hi, Wu YiTing said: Q1:How can I make VIP capture receive 25 frame? If possible, Please provide suggestions for modification. fps is controlled by your pixel clock, so as long as pixel clock is correct, VIP would be able to capture 25fps. Wu YiTing said: Q2:I saw the 1CH TVP5158 driver in the SDK, Can I use TVP5158 driver to receive TVP5154? If possible, can I change it to 4CH? Yes, you can, but you would require to bring it up. Wu YiTing said: Q3:I am curious about the 25fps or 50field that Capture will receive? Capture will receive individual fields and so it will also store field and give callbacks on fields capture. Application would have to merge them and create frames out of them. Regards, Brijesh
+
+fps is controlled by your pixel clock, so as long as pixel clock is correct, VIP would be able to capture 25fps. -> I measured the TVP5154 to be 27MHZ. Is this standard? In fact, we have TP2824 decoder pixcel clock output is 37.125MHZ, can VIP receive it correctly? Yes, you can, but you would require to bring it up. -> I have tried to use TVP5158 driver to receive TVP5154 images but it fails. Can you guide me to achieve it? Capture will receive individual fields and so it will also store field and give callbacks on fields capture. Application would have to merge them and create frames out of them. -> So the Capture driver will merge the fields into Frames, and then send the New data to the Capture link, right? Then I print the Capture link information and see that it should be 25fps, right?
+
+Wu YiTing said: -> I measured the TVP5154 to be 27MHZ. Is this standard? In fact, we have TP2824 decoder pixcel clock output is 37.125MHZ, can VIP receive it correctly? Yes, it should be fine, as long as HS and VS are correct. Wu YiTing said: -> So the Capture driver will merge the fields into Frames, and then send the New data to the Capture link, right? No, driver or link will not merge the fields. It has to be done in the application. Regards, Brijesh
+
+No, driver or link will not merge the fields. It has to be done in the application. -> Does TI provide an application for merging?
+
+I have tried to use TVP5158 driver to receive TVP5154 images but it fails. Do I need to modify some VIP settings in these files? I use PROCESSOR_SDK_VISION_03_05_00_00 The following are my setup steps Step1: Select usecase C:\PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\apps\src\rtos\usecases\vip_single_cam_view Step2: Make sure that Pinmux is configured correctly Step3: Select CHAINS_CAPTURE_SRC_VIDDEC_TVP5158 Step4: captureOutWidth 720, captureOutHeight 576 Step5: Chain_Create Step6: Chain_Start Step7: Initialize TVP5154 7-1// Write to all decoders 0XFE, 0X0F 7-2// write 0x00 to register 0x7F ==> initialize 5154 0X7F, 0X00 vip_single_cam_view.rar
+
+This is the result of Capture link to Display link and then through HDMI 720P. Camera -> TVP5154 -> TDA2 -> HDMI pixcel clock 27MHZ Display link only received 1fps Camera -> TP2824 -> TDA2 -> HDMI pixcel clock 74.25MHZ Display link received 50fps and image is cropped Camera to monitor The yellow sticker indicates that the image is cropped after passing through TDA2
+
+By the way TP2824 hardware: Output BT656. embedded 720*576I
+
+Hi Brijesh Could you help to update? Thanks for your kindly help Daniel
+
+Wu YiTing said: -> Does TI provide an application for merging? No, It has to be done in the application. Wu YiTing said: Do I need to modify some VIP settings in these files? No this should work fine. Just make sure to configure VIP in single channel mode, since this use case might be configuring it in multi-channel mode. Wu YiTing said: Camera -> TVP5154 -> TDA2 -> HDMI pixcel clock 27MHZ Display link only received 1fps Are you configuring VIP in embedded sync format or discrete sync? can you first check if VIP is configured correctly by looking into register? Then check if VIP is detecting size correctly. Then check for fps. fps might be low because your link might.be returning frames in time. Regards, Brijesh
+
+No, It has to be done in the application. -> I found the use case vip_single_rvc_cam_view_crcvpe VPE seems to be able to field merge this can be achieved? Are you configuring VIP in embedded sync format or discrete sync? can you first check if VIP is configured correctly by looking into register? Then check if VIP is detecting size correctly. Then check for fps. fps might be low because your link might.be returning frames in time. -> I use the default setting of TVP5158, which I think is embedded sync format, i will check the VIP size.
+
+Wu YiTing said: -> I found the use case vip_single_rvc_cam_view_crcvpe VPE seems to be able to field merge this can be achieved? Yes, VPE can be used to convert field to frames, but please note it will make 60field -> 60frames. There is a DeInterlacer module in VPE, which can convert field to frames. Now if you want just 30frames/sec, then you could drop/ignore alternate frames at the output of VPE. Regards, Brijesh
+
+How can I check if the Filed image is cropped? I think the size of the 576i field should be 720*288. There will be 50 fields per second. Can I check from the image?
+
+Yes, VPE can be used to convert field to frames, but please note it will make 60field -> 60frames. There is a DeInterlacer module in VPE, which can convert field to frames. Now if you want just 30frames/sec, then you could drop/ignore alternate frames at the output of VPE. -> Have you implemented field merge with VPE?
+
+Hi Brijesh, Please help me understand pInprms->dataFormat, pOutprms->dataFormat, my VIP input format is YUV422I, but why I have to set the following to see the correct color picture "indata formate = SYSTEM_DF_YUV422P outdata formate = SYSTEM_DF_YUV422I_YUYV"
+
+Hi Wu YiTing, Wu YiTing said: There will be 50 fields per second. Can I check from the image? You could save image and check it out. I dont see any other way. But before that, can you please check if captured image size reported by VIP is correct? Wu YiTing said: -> Have you implemented field merge with VPE? No, please refer to existing usease Wu YiTing said: Please help me understand pInprms->dataFormat, pOutprms->dataFormat, my VIP input format is YUV422I, but why I have to set the following to see the correct color picture "indata formate = SYSTEM_DF_YUV422P outdata formate = SYSTEM_DF_YUV422I_YUYV" Input data format here means the format that VIP is receiving data. Here, YUV422P means, it is receiving YUV422 data. Output data format is storage format, so data is stored as YUV422 in UYVY format. Regards, Brijesh
+

sample_embedding_folder/1024518.txt

@@ -0,0 +1,31 @@
+Ticket Name: TDA2PXEVM: Mismatch between TIDL host emulation tool and target board TDA2Px EVM File I/O use case
+
+Query Text:
+Part Number: TDA2PXEVM Hi, I used TIDL import tool to convert a TensorFlow model, then I used the host emulation tool to check the output of the model after conversion. I found that the output is acceptable after quantization. Then, I used TIDL file I/O use case to check the output on the board and compare it to the output of the host emulation tool. However, I find a great mismatch between the two outputs. The output from the target is mostly zeros, which is completely different from the host emulation tool output. I searched on the forum, but did not find a systematic way to debug the cause of this difference. I specify the following parameters in the TIDLCFG.TXT file: inputWidth=128
+inputHeight=32
+inputFile=IN.bin
+outputFile=OUT.bin
+netFileName=NET.bin
+paramFileName=PRM.bin Would you please let me know what is the cause of this issue, or how to appropriately debug it ? Thanks, Ahmed Anwar
+
+Responses:
+Hi Ahmed Anwar, In the TIDL file I/O use case, which core did you select to run TIDL? Kindly check with both the cores and isolate if this issue is specific to any core (EVE/DSP) ? Thanks, Praveen
+
+Hi Praveen, I checked both cores. The problem is the same whether I choose EVE or DSP. The output is completely different from the host emulation tool output, with the majority of zero values. Thanks, Ahmed Anwar
+
+Hi Praveen, I noticed that the output file size from the File I/O use case on TDA2PX EVM is not equal to the output file size from the host emulation tool. The output file size from the host emulation tool = 96 bytes. This size is correct and was expected, as I have 96 values in the output of my model, and if each value is represented by 1 byte, so the output file size should be 96 bytes. When I read this 96 byte file as int8, the output is reasonable, and I was expecting to find the same output with the same size on target. However, the output file size from the File I/O use case = 4.1 KB, which is not equal to the 96 byte file I get from the host emulation tool. Would you please explain how I get different file sizes from the host emulation tool and File I/O use case, given that I use the same model and input files? And if you have any idea about this mismatch problem in general, please let me know. Thanks, Ahmed Anwar
+
+Hi Ahmed Anwar, You are getting output file size of 4.1KB (which is 128x32) because FILE I/O usecase dumps output considering it as segmentation application, so it writes output data considering input dimension. If your application is not segmentation, then you may need to provide the output dimension to the usecase and dump the actual output of 96 bytes, for this you need to modify the dump code in the usecase and for this modified code please refer to last post in the below thread. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/874558/tda2-ti-vision-sdk---tidl---verifying-that-inceptionv1-works-with-tidl/3240125#3240125 Thanks, Praveen
+
+Hi Praveen, Thank you for your reply. I will try to edit the dumping code in the use case based on the post you provided. Until I modify the code, I have this question, by which I try to figure out if the correct 96 bytes are present within the 4096 bytes or not: Does the 4096 byte output (32 * 128) have the actual 96 output ? When the use case dumps 4096 values, does it dump my actual 96 values (Which are the output of the model) and dumps also other values to complete the 4096 bytes ? If this is the case, I need to understand these points: How can I get the actual 96 byte output of the 4096 bytes ? Is there an offset to start extracting the actual output from ? Are the wrongly dumped bytes (other than the correct 96 bytes) all zeros ? If not, how there values are determined, if the actual model has only 96 bytes output ? Would you please answer my question till I modify the code and test the use case after modification ? Thanks, Ahmed Anwar
+
+Hi Praveen, I changed the use case code based on the post you provided, and rebuilt the SDK. The output file size is now correct. However, the output is not correct and does not match the host emulation tool output. Most of the values are zeros, which is completely different from the host emulation tool output. Would you please help me in identifying the cause of this mismatch ? Thanks, Ahmed Anwar
+
+Hi Praveen, I also have a question regarding that the File I/O use case is used for segmentation. My application is not segmentation, does this make an issue ? I added the output height and width to the use case code as you said, but the output is not correct. Is it ok to use the File I/O use case with a model which is not used for segmentation ? Thanks, Ahmed Anwar
+
+Hi Ahemd Anwar, Could you please provide some details about your application. Also, kindly confirm that you had updated "dmaPrm.srcPitch[0]" and "dmaPrm.destPitch[0]" with outWidth as these can effect the offset in output buffer. Thanks, Praveen
+
+Hi Praveen, My application is classification. I confirm that I updated "dmaPrm.srcPitch[0]" and "dmaPrm.destPitch[0]" with outWidth. Thanks, Ahmed Anwar
+
+Hi Praveen, Is there a difference between the way of execution of the host emulation tool and the File I/O use case on target ? I need to understand this, as it is supposed to be the same, and it is supposed to get on target the same output that I get using the host emulation tool. I think that getting good results using the host emulation tool means that the conversion and quantization are done in a good way, and that I can go on with deploying the model to the board. I need to understand if there is differences between the source code that runs the host emulation tool and the File I/O use case, as they produce different results. Thanks, Ahmed Anwar
+

sample_embedding_folder/1027878.txt

@@ -0,0 +1,73 @@
+Ticket Name: TDA2HG: [Opengl] -- the cube usage in fbo
+
+Query Text:
+Part Number: TDA2HG Other Parts Discussed in Thread: TDA2 hi: I have a question about the usage of cubemap in fbo; the simple code as bellow: { glGenFramebuffers(1, &fboID); glBindFramebuffer(GL_FRAMEBUFFER,fboID); glGenTextures(1, &cubemapID); glBindTexture(GL_TEXTURE_CUBE_MAP, cubemapID); for (unsigned int i = 0; i < 6; ++i) { glTexImage2D(GL_TEXTURE_CUBE_MAP_POSITIVE_X + i, 0, GL_RGB, 256, 256, 0, GL_RGB, GL_UNSIGNED_BYTE, nullptr); } glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MIN_FILTER, GL_LINEAR); glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MAG_FILTER, GL_LINEAR); glUniform.. //update the uniform variable glViewport(0, 0, 256, 256); for (unsigned int i = 0; i < 6; ++i) { glFramebufferTexture2D(GL_FRAMEBUFFER, GL_COLOR_ATTACHMENT0, GL_TEXTURE_CUBE_MAP_POSITIVE_X + i, cubemapID, 0); if (glCheckFramebufferStatus(GL_FRAMEBUFFER) != GL_FRAMEBUFFER_COMPLETE) { printf("glCheckFramebufferStatus error!\n"); } glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT); renderCube(); } } when i test the code, it works well on windows, but when i move it to the tda2 platform, the question is comming, sometimes the effiect is black , or is white, or white and black , or other colors, it's change every time. how is this? and how to resolved it? thanks
+
+Responses:
+Hello, Can you try and see if this works:     // Setup texture for cubemap
+    glGenTextures(1, &textureCubeMap);
+    char buffer0[CUBEMAP_TEX_LEN * CUBEMAP_TEX_LEN * 6];
+
+    glBindTexture(GL_TEXTURE_CUBE_MAP, textureCubeMap);
+    memset((void *)buffer0, 0x50, CUBEMAP_TEX_LEN*CUBEMAP_TEX_LEN*6);
+    for(GLuint i = 0; i < 6; i++)
+    {
+            glTexImage2D(
+                            GL_TEXTURE_CUBE_MAP_POSITIVE_X + i,
+                            0, GL_RGBA8, CUBEMAP_TEX_LEN, CUBEMAP_TEX_LEN,
+                            0, GL_RGBA, GL_UNSIGNED_BYTE, (char *)buffer0
+                        );
+    }
+
+    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MAG_FILTER, GL_LINEAR);
+    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_MIN_FILTER, GL_LINEAR);
+    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_S, GL_CLAMP_TO_EDGE);
+    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_T, GL_CLAMP_TO_EDGE);
+    glTexParameteri(GL_TEXTURE_CUBE_MAP, GL_TEXTURE_WRAP_R, GL_CLAMP_TO_EDGE);
+
+    // Setup Framebuffer for cubemap
+    glGenFramebuffers(1, &fbCubeMap);
+    
+    
+    // Rendering part
+    GLint current_fbo;
+    glGetIntegerv(GL_FRAMEBUFFER_BINDING, &current_fbo);
+    glBindFramebuffer(GL_FRAMEBUFFER, fbCubeMap);
+    
+    // Render to cubemap
+    for (int i = 0; i < 6; i++)
+	{
+        glFramebufferTexture2D(GL_FRAMEBUFFER,
+		    GL_COLOR_ATTACHMENT0,
+		    GL_TEXTURE_CUBE_MAP_POSITIVE_X + i,
+		    textureCubeMap,
+		    0);
+	    glClear(GL_COLOR_BUFFER_BIT|GL_DEPTH_BUFFER_BIT);
+	    //.... draw/render to cube map surface
+	}
+	
+	// Bind the original frame buffer
+	glBindFramebuffer(GL_FRAMEBUFFER, current_fbo);
+	
+	// Use cubemap texture
+	glBindTexture(GL_TEXTURE_CUBE_MAP, textureCubeMap);
+
+    //... draw to the final framebuffer using cubemap
+    // In the shader code, use samplerCube to sample texture
+    // e.g:
+    // uniform samplerCube skybox;
+    // ...
+    // vec4 colorval = texture(skybox, direction);
+    
+
+    
+    
+	    
+
+
+
+    
+
+
+ If it still doesn't work, can you try and use glGetError to check for any errors? Regards Hemant
+

sample_embedding_folder/1028256.txt

@@ -0,0 +1,12 @@
+Ticket Name: TDA2PXEVM: Is Reshape/Permute layer supported on TDA2X with CaffeImportTool?
+
+Query Text:
+Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi ! When convert shufflenetv2 caffemodel to tidl bin/param using REL.TIDL.01.01.03.00, it failed. EEROR LOG: TIDL returned with error code : -1100, refer to interface header file for error code details Error at line: 1578 : in file .\.\src\tidl_tb.c, of function : test_ti_dl_ivison End of config list found ! But I check that reshape layer and permute layer work well in SSD model. So how can I make separate reshape layer and permute layer work ?
+
+Responses:
+Hi, Reshape, Permute layers are supported only in the context of SSD network. They are not supported as standalone layers. Thanks, Praveen
+
+Hi Praveen Thanks for you replay. So currently, channel shuffle can not work on TIDL(both tda2 / 4). These requirements will be supported in the futures?
+
+Hi, It can work on TDA4 TIDL but not in TDA2 TIDL, please note that both are different code bases and TDA4 can support much more netwroks and frame works compare to TIDL on TDA2 , please try with TIDL on TDA4 (https://www.ti.com/tool/download/PROCESSOR-SDK-RTOS-J721E/08.00.00.12). Thanks, Praveen
+

sample_embedding_folder/1028549.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA2PXEVM: Is there a way to build yocto but not thud on TDA2Px-EVM to build python3 Tensorflow-lite
+
+Query Text:
+Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hello all, I Have TDA2Px-EVM board and I was able to build yocto file system on using this guide: http://software-dl.ti.com/processor-sdk-linux/esd/docs/06_00_00_07/linux/Overview_Building_the_SDK.html I was also able to customize the image as i have added some layers like meta-ros, meta-scipy and I was also able to create custom layer to install and build some libraries, packages and package groups. I was installing some python packages and the changes I made to the image allowed me to install most of the needed python3 packages using pip3. I am currently facing a problem in installing tensorflow or tensorflow-lite when I added meta-tensorflow-lite layer https://github.com/NobuoTsukamoto/meta-tensorflow-lite/ and appended to my image recipe IMAGE_INSTALL += " python3-tensorflow-lite " I have got "ERROR: Layer meta-tensorflow-lite is not compatible with the core layer which only supports these series: thud" So I am currently facing a problem as processor sdk 6.x are all based on thud and this distro is not supported in the tensorflow-lite meta layer and When I tried to build a different version of processor SDK there was a toolchain error "ERROR: Failed to parse external Linaro toolchain version from: gcc version 8.3.0 " as probably the other versions of processor SDK doesn't support "dra7xx-evm". My problem shortly is there any way to build yocto file system on TDA2Px-EVM based on another yocto distro rather than thud or is there a way to build and install python3 tensorflow or tensorflow-lite on TDA2Px-EVM using the built and working yocto with this version of processor SDK. Thanks in Advance. Best regards, Kirollos Henry
+
+Responses:
+Hi Kirollos, Apologies for the delay in the response to this. Kirollos Henry said: is there any way to build yocto file system on TDA2Px-EVM based on another yocto distro rather than thud The short answer is no, thud is the last release with a completely validated offering with DRA7/TDA2. You will have to take care of the migration at your end. Kirollos Henry said: is there a way to build and install python3 tensorflow or tensorflow-lite on TDA2Px-EVM using the built and working yocto with this version of processor SDK. I dont think anyone in TI has spent time on this problem, therefore we are unable to provide you with any further instructions. Regards Karthik
+

sample_embedding_folder/1030453.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA2EG-17: Can a thread share works to dual core?
+
+Query Text:
+Part Number: TDA2EG-17 Hello this article: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/692229/linux-tda2-hao-can-i-use-2-a15 said that "You can think as a single A15 core with CPU clock/frequency doubled" for dual core. But this article: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/862271/tda2hg-why-the-a15-usage-just-50-can-not-up-to-90 said one thread can only run in one core. So it means multi-threads will be separated to dual core automatically, but one thread can't. Is it? Thanks. BR, Jeff
+
+Responses:
+Jeff, One thread can be scheduled only on one CPU. - Keerthy
+

sample_embedding_folder/1030791.txt

@@ -0,0 +1,12 @@
+Ticket Name: TDA2SX: PROCESSOR_SDK_VISION_03_05 tidl_OD usecase layer limitations ?
+
+Query Text:
+Part Number: TDA2SX Hi I tried to use tidl_model_import.out to get bin file. I used stats_tool_out.bin and trace_dump_0_512x512.y file to check test image detection result. Test image showed model can detect object. test image detection result: But I ran on tdasx, it cannot detect any object. I suspect tdasx cannot run too many layers model. The number of layersGroupId are 157 and number of parameters are 3.5M. Do tdasx have any limitations about layers or parameters count? thanks yumei
+
+Responses:
+Hi Yumei, Below are the SSD limitations listed in the TIDL datasheet : – Only Caffe-Jacinto based SSD network is validated. – Reshape, Permute layers are supported only in the context of SSD network. – “share_location” has to be true – Tested with 4 and 5 heads. – SaveOutputParameter is ignored in TIDL inference. – code_type is only tested with CENTER_SIZE. Please try the suggestions mentioned in the below thread in OD use case to get the detections in the output : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/689617/tda2-how-to-run-ssd-based-tidl-od-use-case-in-vision-sdk-with-pre-trained-model Thanks, Praveen
+
+Hi Praveen I confused about Tested with 4 and 5 heads. Did it mean about 4 and 5 anchor box result? Thanks, yumei
+
+Yes
+

sample_embedding_folder/1032151.txt

@@ -0,0 +1,12 @@
+Ticket Name: TDA2PXEVM: How can I extract two CNN output tensors on TIDL (TDA2)
+
+Query Text:
+Part Number: TDA2PXEVM Other Parts Discussed in Thread: TDA2 Hi sir! My network have two (maybe more) output layers (CxHxW) : Cx56x56 & Cx28x28. How can I get two outputs from TDIL?
+
+Responses:
+Hi IIuo, Sorry for the delay. This is not supported in TIDL on TDA2. Thanks, Praveen
+
+Hi Praveen I proposed a method to solve this problem ： using Transpose Conv and Concat. Step 1. I add a Transposed Conv layer with 4x4 kernel, stride 2 to the small size layer (for upsampling : Cx28x28 -> Cx56x56) Step 2. I fill filter manually to make Transposed Conv layer working as insert 0 between original output elements [e11 e12 -> [ e11 0 e12 0 e21 e22] 0 0 0 0 e21 0 e22 0 0 0 0 0 ] Step 3. I use Concat layer to get my output tensor : 2Cx56x56 So I can simply add stride =1 / 2 to decode different output tensor. Those works have been tested on Caffe. Hope that can help others.
+
+Thanks for sharing.
+

sample_embedding_folder/1033681.txt

@@ -0,0 +1,8 @@
+Ticket Name: CCSTUDIO: Using CCS scripting with Lauterbach debugger.
+
+Query Text:
+Part Number: CCSTUDIO Other Parts Discussed in Thread: TDA2 Hi, I have a TDA2XX-EVM on which i'm loading and running few binaries of different cores. Here i'm using Spectrum Digital XDS560V2 STM USB Emulator. Also i'm using scripts to launch ccxml, load and run binaries. But i need to use Lauterbach debugger instead of this spectrum digital debugger. But i could'nt find any example scripts with respect to Lauterbach debugger. Can anyone please tell me or send me a reference links that specifies the use of Lauterbach debugger for my TDA2XX regards, Likhith
+
+Responses:
+-0- Which TDA2 chip are you using? Does it have a single A15 or a dual-A15? I do have TRACE32 CMMs which are converted versions of GELs which I use. Typically these are shared via TI-CDDS. If you have access I could upload there. If you tell exactly which CPU you have I can see about uploading a subset here. -1- Lauterbach on their website (and in their release images) has simplified scripts which allow running code on TDA2 systems. It might be one of these is sufficient for whatever you are trying to run. https://www.lauterbach.com/scripts/hardware/arm~tda2x~vayu_evm/hardware-arm-tda2x-vayu_evm_20200205093516_all_files.zip https://www.lauterbach.com/scripts/hardware/arm~dra72x~j6_eco_evm/hardware-arm-dra72x-j6_eco_evm_20200205093452_all_files.zip https://www.lauterbach.com/scripts/hardware/arm~dra7xx/hardware-arm-dra7xx_20200205093452_all_files.zip Regards, Richard W.
+

sample_embedding_folder/1035356.txt

@@ -0,0 +1,38 @@
+Ticket Name: TDA2EXEVM: TDA2 DSP2 XDC ASSERT
+
+Query Text:
+Part Number: TDA2EXEVM Other Parts Discussed in Thread: SYSBIOS We run our algorithm on DSP2. Sometimes DSP2 will have XDC Assert message and then DSP2 will crash. How can we solve it? Log: [DSP2 ] 11173.232111 s: ### XDC ASSERT - ERROR CALLBACK START ### [DSP2 ] 11173.232141 s: [DSP2 ] 11173.232202 s: assertion failure: A_badContext: bad calling context. See GateMutex API doc for details. [DSP2 ] 11173.232233 s: [DSP2 ] 11173.232233 s: ### XDC ASSERT - ERROR CALLBACK END ###
+
+Responses:
+Have any update?
+
+Hi, Please refer to BIOS API doc for GateMutex. Or, you can find the source under ~/bios_6_46_06_00/packages/ti/sysbios/gates/GateMutex.c. You are hitting the below error where GateMutex_enter() is called in HWI or SWI context. /*
+ *  ======== GateMutex_enter ========
+ *  Returns FIRST_ENTER when it gets the gate, returns NESTED_ENTER
+ *  on nested calls.
+ *
+ *  During startup, Task_self returns NULL.  So all calls to the 
+ *  GateMutex_enter look like it is a nested call, so nothing done.
+ *  Then the leave's will do nothing either. 
+ */
+IArg GateMutex_enter(GateMutex_Object *obj)
+{
+    Semaphore_Handle sem;
+
+    /* make sure we're not calling from Hwi or Swi context */
+    Assert_isTrue(((BIOS_getThreadType() == BIOS_ThreadType_Task) ||
+                   (BIOS_getThreadType() == BIOS_ThreadType_Main)),
+                   GateMutex_A_badContext);
+
+    if (obj->owner != Task_self()) {
+        sem = GateMutex_Instance_State_sem(obj);
+        Semaphore_pend(sem, BIOS_WAIT_FOREVER);
+
+        obj->owner = Task_self();
+
+        return (FIRST_ENTER);
+    }
+
+    return (NESTED_ENTER);
+} Regards, Stanley
+

sample_embedding_folder/1037669.txt

@@ -0,0 +1,14 @@
+Ticket Name: TDA2HG: tda2 anti-aliasing
+
+Query Text:
+Part Number: TDA2HG hello: usecase: render a model, but the alias is obvious, so i need to use the anti-aliasing. when the egl chooseconfig, i add the EGL_SAMPLE_BUFFERS, 1 and EGL_SAMPLES,4 to the attribs, it works better, but not enough, so i change the EGL_SAMPLES, 8, the result is eglCreateContex failed! it seems doesn't support. do you have other methods? thanks ~
+
+Responses:
+Hello, That is correct. 8 is not supported. 4 is the max value for EGL_SAMPLES. Regards Hemant
+
+how about TDA4, the max value?
+
+Hello, TDA4VMid also supports upto 4 - but of course, you will need to keep overall performance in mind. Regards Hemant
+
+got it, thank you~
+

sample_embedding_folder/1038392.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA2SX: Memory access error when EVE read address more than 512MB DDR
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Hi expert, Customer used 512MB on TDA2 before while they increased DDR3 to 1GB recently. After modified EMIF and DMM configuration in gel file, we could access 0xB5000000 on DSP and ARM in CCS memory watch page. But on EVE, it reported error as below. Could you please suggest what we need to do to make EVE access correct? Thank you.
+
+Responses:
+Hi, You have to update the EVE MMU mapping in GEL file. The max page size per entry in EVE MMU is only 16MB. Regards, Stanley
+

sample_embedding_folder/1038421.txt

@@ -0,0 +1,28 @@
+Ticket Name: TDA2EVM5777： How to correctly connect SOC and EMMC when resetting TPS659039
+
+Query Text:
+Part Number: TDA2EVM5777 Other Parts Discussed in Thread: TDA2E, TDA2 Hello, Question 1: We measured that the SOC PORZ port was continuously pulled down, and the system was not powered on normally. We need TI experts to help analyze the cause of the failure? Figure 2 is a schematic diagram of the hardware schematic design. The RTC_PORZ, RTC_ISO, PORZ of the PMIC and the external reset IC are connected together; the PORZ reset of the PMIC passes through the A device and the RSTOUTn of the PMIC passes through the B device, combined into an AND gate circuit, and the gate output Connect the reset port of EMMC. Question 2: When the connection between PMIC PORZ and A device is disconnected, the system is powered on normally. Figure 1. The yellow line is the waveform we measured at the PORZ reset port of the PMIC, and the pink line is the waveform measured at the reset port of the EMMC. As shown by the pink line, there is a 5ms pull-up level before EMMC reset. We are worried that it will affect the startup of EMMC. Is it necessary to eliminate it through the AND gate? Model of PMIC: TPS659039 SOC model: TDA2E
+
+Responses:
+Is the block diagram trying to show customer hardware implementation or TI EVM implementation? The diagram is not correct, as the PMIC does not have PORz, RTC_PORz, RTC_ISO signals. These are signals on the processor, which is NOT identified in the diagram. Also the processor does not have reset out signal, that is on the PMIC. Certainly you can't have a reset output from the processor feeding back into the reset input of the PMIC, as that could create a loop where stuck in reset. TI's EVM correctly implements this reset structure. The PMIC reset output feeds the reset inputs of the processor. The processor's reset output (nRSTOUT) is sourced into the PMICs nWARMRESET input.
+
+Hi Robert, Robert Eschler said: Is the block diagram trying to show customer hardware implementation or TI EVM implementation? The block diagram is updated as follows，Can you confirm if there is any problem with the design? Robert Eschler said: Certainly you can't have a reset output from the processor feeding back into the reset input of the PMIC, According to the TPS659039 specification, the NRESWARM port of TPS659039 is connected to the RETOUTn of SOC，RETOUTn is the Warm reset output of SOC
+
+The block diagram still cannot be correct, as SoC does not support a reset out. Should this be from PMIC? If you compare with TI EVM, the RESET OUT of PMIC is AND-gate with reset supervisor. Why not replicate the EVM logic, as it is tested/validated? Also - BufferA does not serve any purpose, as any time SoC is reset, nRSTOUT is asserted. Only BufferB is required to reset eMMC device.
+
+Robert Eschler said: BufferA does not serve any purpose According to the TDA2 specification, Buffer A is needed. In our block diagram, buffer A and buffer B form an AND gate Robert Eschler said: The block diagram still cannot be correct, as SoC does not support a reset out. Should this be from PMIC? YES,Update as shown below
+
+Can you please clarify in the TDA2 specification where it states buffer A + buffer B (AND-gate) is required for eMMC Reset? PMIC RESET_OUT should connect directly to SoC's reset input(s). It can be AND-gate with supervisor output, but does not need to be routed through supervisor.
+
+Robert Eschler said: Can you please clarify in the TDA2 specification where it states buffer A + buffer B (AND-gate) is required for eMMC Reset? Sorry，I don’t understand what you mean. I want to eliminate the waveform measured by the RSTN reset pin of EMMC when it is powered on, as shown in the red box in the figure below： Initially ，we wanted to achieve the reset architecture as shown in the figure below and the red box truth table results, but the current reset architecture design seems to be problematic, the PORZ pin of the SOC has been pulled low, so I want to confirm whether our reset architecture design correct?
+
+Have you tried a configuration like modified image below? I don't think the issue is with the AND-gate on nRSTOUT. Also - from the waveform, it looks like the logic levels are very low and are just now turning on (with power supplies). Once the power levels and input thresholds are met, the logic starts working as expected. Maybe try an pull-down resistor (or similar) to eliminate the early pulse.
+
+If the reset pin of EMMC remains in this state after power-on, will there be any hidden dangers?
+
+The eMMC is getting a valid reset pulse (low then high), and it appears the final high is full scale (1.8V). I don't see any issue with the final reset. I'm still not clear on the smaller pulse, but again - could be from power just reaching valid logic levels.
+
+I checked the relevant design in the DEMO board, the version is： 516582H_VAYU_EVM_13NOV2015_H As shown in the figure, the DEMO board does not use the AND gate mentioned in the manual, but only uses a buffer. I want to confirm whether the design can also meet the requirements of TDA2?
+
+The AND-gate you are referring only affects the eMMC (or other peripherals), and does not affect the TDA2. The PORz circuit for the TDA2 should not include RSTOUTn, as it is reset output of TDA2.
+

sample_embedding_folder/1038804.txt

@@ -0,0 +1,12 @@
+Ticket Name: TDA2EXEVM: How to use remote service on TDA2
+
+Query Text:
+Part Number: TDA2EXEVM Other Parts Discussed in Thread: TDA2 The customer would like to get serializer and deserializer‘s register information in usecase code, but that information is on another core, so he intends to use remote service to get the information which is on another core. The customer would like to know how to use remote service function on TDA2, and could you you please offer an example? Thanks. Best Regards, Cherry Zhou
+
+Responses:
+Hi, The latest update as follows: The customer also would like to have an example about how to use remote service function based on TDA2 SDK. Thanks again! Best Regards, Cherry Zhou
+
+Hi, May I know is there any update? Thanks! Best Regards, Cherry Zhou
+
+Hi Cherry, Could you give some details about the customer system? What OS is used on A15? Which core will have the SerDes driver? Which core does need to get the register info via remote calls? Regards, Stanley
+

sample_embedding_folder/1039081.txt

@@ -0,0 +1,26 @@
+Ticket Name: TDA4VM: Create 2 framebuffers， But introduced a new problem: splash screen, the screen keeps flickering
+
+Query Text:
+Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 background: Based on TDA4, SDK7.03, QNX system, to achieve off-screen rendering problem: what I want to do is this: Create 2 framebuffers, let’s call them fb1 and fb2. Render the scene to fb2 normally. Render fb2 to fb1 with one post-processing effect. Render fb1 to the default framebuffer (we’ll call it fb0) with another post-processing effect. This method really works. But introduced a new problem: splash screen, the screen keeps flickering. After verification: changing glFinish to glReadPixels, the flickering phenomenon still exists. But the image saved by glReadPixels is normal. The specific implementation is as follows:
+
+Responses:
+Hello, Thank you for creating a new thread. I will close the other one and let us use this one. For reference: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1033627/tda4vm-off-screen-rendering-problem-0x506-gl_invalid_framebuffer_operation The fact that glReadPixels on the offscreen buffer returns normal expected image, we need to think if the display node is somehow showing the wrong buffer. Do we know if there is a timing involved? Some suggestions and questions: 1. Have you tried glReadPixels on the final FB? Does this look okay? 2. Instead of any post processing, can we do a simple glClear (of different colors) to fb0, fb1 and fb2 And can we switch colors for each to see what is ending up on the display. 3. As a separate experiment, continue with normal rendering processing but do a glClear of alternating colors on fb0 Regards Hemant
+
+OK, I will start experimenting now, and I will tell you immediately if there is a conclusion, it is expected in three hours. But this is done to verify: the two Buffers are constantly switching or?
+
+In order to better verify, compare and analyze the result data, FB1 was rendered red by me; FB2 was rendered blue by me; FB0 was finally rendered (including the content on FB1 and FB2 and other textures such as the car model drawn normally) After verification, the image results saved by FB0, FB1, and FB2 are all completely OK. [AVM] FB0 Width=1920, Height=720, Format=0x80e1 (GL_BGRA=0x80e1, GL_BGR=0x80e0), Type=0x1401... [AVM] FB1 Width=560, Height=720, Format=0x80e1 (GL_BGRA=0x80e1, GL_BGR=0x80e0), Type=0x1401... [AVM] FB2 Width=1280, Height=960, Format=0x80e1 (GL_BGRA=0x80e1, GL_BGR=0x80e0), Type=0x1401... FB0 is the default FB of external TDA4: 1920*720 format GL_BGRA (GL_BGRA_EXT), save the image OK FB1 is an FB created internally by myself: 560*720 format GL_BGRA (GL_BGRA_EXT), save the image OK FB2 is another FB created internally by myself: 1280*960 format GL_BGRA (GL_BGRA_EXT), save the image OK The specific video and the results, I will let Fredy forward it to you，Here is just a screenshot
+
+Let me add the setting parameters of Display Node. Is there a problem with these parameter settings, especially the two parameters opMode and pipeId (Can you explain what is the meaning of setting different values for these two parameters? I will also do verification at the same time, See the impact of these different values): display_params.opMode = TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE; display_params.pipeId = 2; display_params.outWidth = SV_DISPLAY_WIDTH; display_params.outHeight = SV_DISPLAY_HEIGHT; display_params.posX = 0; display_params.posY = 0; obj->disp_config = vxCreateUserDataObject(obj->context, "tivx_display_params_t", sizeof(tivx_display_params_t), &display_params); status = vxGetStatus((vx_reference)obj->disp_config); obj->displayObj.disp_node = tivxDisplayNode(obj->graph, obj->disp_config, obj->out_img); vxSetNodeTarget(obj->displayObj.disp_node, VX_TARGET_STRING, TIVX_TARGET_DISPLAY1); vxSetReferenceName((vx_reference)obj->displayObj.disp_node, "Display_node");
+
+Share the latest research information: it has a certain relationship with the screen parameter settings. Change the opMode parameter of the display node from TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE to TIVX_KERNEL_DISPLAY_BUFFER_COPY_MODE, the splash screen problem is solved, but the rendering slows down. In other words: using TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE will render faster, but the screen will flick; using TIVX_KERNEL_DISPLAY_BUFFER_COPY_MODE will not flicker, but the rendering will be slower. But this is not enough, rendering is too slow. TDA2 also uses the TIVX_KERNEL_DISPLAY_ZERO_BUFFER_COPY_MODE parameter, which renders quickly without flickering. I still feel that there is a problem, you can continue to research in this direction, and I will continue to research at the same time.
+
+Hello, Thank you for confirming that and sorry for not getting back sooner. We of course need the zero copy mode. Because the copy mode is working fine, I tend to agree that it could be the display side of things that could be out of sync. I will check this internally and get back. In the meanwhile, if there are any updates, please let us know. Regards Hemant
+
+Thanks for the reply. But how to solve this problem? Need help urgently~ Please~ Another more urgent problem is encountered: After AVM is started (GPU rendering), it may cause communication blocking between its own process and the processes of other modules. This is a newly discovered problem.
+
+Just to rule something out - can you confirm that you have a glFinish at "each" stage of the offscreen and on screen rendering. With three frame buffers, this would mean three glFinish (at least for verifying - ideally, glFinish at the very end should be fine). I am trying to replicate this behavior here on Linux and also discussing with display experts. Regards Hemant
+
+I confirm that there is glFinish in "every" phase. This problem of off-screen rendering causing splash screen is one of the problems; Another newly discovered problem is that after AVM rendering, it will affect the IPC process communication. This is also explained in another e2e post of mine. Please help and solve it. Thank you, and look forward to your prompt reply.
+
+Hello, is there any progress now? It's anxious, please. Thanks~
+

sample_embedding_folder/1040319.txt

@@ -0,0 +1,10 @@
+Ticket Name: TDA4VM: Does TDA4 ISP support RGB-IR sensor ?
+
+Query Text:
+Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 The TDA2/TDA3 vision SDK 3.8 has the demosaicing function implemented on c66x . Was wondering if the TDA4 ISP is flexible enough to avoid using the DSP for such pixel intensive task. regards, Victor
+
+Responses:
+Hi Victor, There are 2 kinds of RGB-Ir sensors 1. 2x2 CFA : This type is natively supported by TDA4 ISP. Any 2x2 CFA is supported. 2. 4x4 CFA : This requires a pre-processing step similar to what was done on TDA2P and TDA3. Regards, Mayank
+
+Thanks !
+

sample_embedding_folder/1041010.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA2P-ABZ: Does this board support Deep learning accelaration (TIDL)?
+
+Query Text:
+Part Number: TDA2P-ABZ Other Parts Discussed in Thread: TDA2 I'm trying to figure out if our boards will get any speedup from going through the TIDL conversion, on one hand https://training.ti.com/overview-ti-deep-learning-tda2-and-tda3-adas-platforms this link this claim accleration, on the other hand in the TIDL userguide , https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/07_00_00_11/exports/docs/tidl_j7_01_02_00_09/ti_dl/docs/user_guide_html/md_tidl_overview.html, it lists only TD4 as deep learning accelerated. Can anyone shed some info?
+
+Responses:
+Hi Joseph, TDA2 and TDA3 are old generation boards which can do TIDL conversion, but on these boards there is no active TIDL development and limited support. TDA4 is our new generation more capable device with active TIDL development and also supports huge variety of DL networks with different frameworks. We would suggest to evaluate TDA4 for DL acceleration. Thanks, Praveen
+

sample_embedding_folder/1042093.txt

@@ -0,0 +1,10 @@
+Ticket Name: TDA2SX: NDK Change static IP configuration
+
+Query Text:
+Part Number: TDA2SX Hi, TI Experts! We use TDA2X custom board with PROCESSOR_SDK_RADAR_03_07_00_00 and set up IP configuration in PROCESSOR_SDK_RADAR_03_07_00_00\vision_sdk\links_fw\src\rtos\bios_app_common\tda2xx\cfg\NDK_config.cfg Can we change static IP configuration in our application at runtime? Can you advice any examples? Best Regards, Dmitry
+
+Responses:
+Hi, Please refer to the below thread. https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/681655/ccs-msp432e401y-how-does-the-udpecho-sample-code-configure-static-ip Regards, Stanley
+
+Thanks a lot!
+

sample_embedding_folder/1045963.txt

@@ -0,0 +1,20 @@
+Ticket Name: TDA4VM: porting hardware surround view interface to app_srv_camera demo display unexpect
+
+Query Text:
+Part Number: TDA4VM Other Parts Discussed in Thread: TDA2 porting hardware surround view interface to app_srv_camera demo display unexpect Dear expert, I porting my surround view interface into app_srv_camera demo, add my init interface to tivxGlSrvCreate, which need 3 paramters (display, surface, context), replace render_renderFrame with my UpdataApp interface for doing surround view function, in my interface, there are create serval framebuffers use glGenFramebuffer, and when the app run, call glBindFramebuffer bind texture to each framebuffer, then glBindFramebuffer (GL_FRAMEBUFFER, 0) render all the contents to the window provided framebuffer, now on tda4vm linux sdk, because the surface is null, I don't know where the display content store and how to get it when do glBindFramebuffer (GL_FRAMEBUFFER, 0) . In tivxGlSrvProcess, I found appEglBindFramebuffer call glBindFramebuffer bind the display buffer , so I modify my UpdataApp interface , delete all glBindFramebuffer code line, after do that I can see one part of my materials dispaly on screen . my question: 1) if tda4vm can create surface for render, how to do it, I try to call eglCreatePbufferSurface to create it , but it failed 2) if can't create surface, how to modify my interface for dispaly all the materials or how to get the content buffer after render finish. sdk vision: 07_03_00_07 OS: Linux Thanks!
+
+Responses:
+Hello, In case of TI's TDA4 surround view implementation, the display is controlled using R5 and the OpenVX display node abstracts this out. Look at vision_apps/utils/opengl/src/a72/app_gl_egl_utils_linux.c. There is a function to create render surface/texture from a pre-allocated dmabuf - appEglWindowCreateIMG. This function basically takes a dmabuf fd and creates an EGL Image that can be rendered to. This is used as a frame buffer in appEglBindFrameBuffer (in the same file). You can follow the same procedure. What are you trying to do in your use case? Do you need to send your GPU rendered buffer to R5 display? You can also look at a simpler example - vision_apps/apps/basic_demos/app_linux_arm_opengl_mosaic Regards Hemant
+
+Thanks！ Yes， I need to send my GPU rendered buffer to R5 dispaly, but I don't know how to do it, I try to use glReadPixel read my gpu output to output_target_ptr, but it failed and return 0x506 error report. As you discribe I follow app_gl_egl_utils_linux.c , use the same procedure, in my own case which run on tda2 before, which need input 4 camera capture frames and load some other materials, then do surround view function and display the output render buffer.
+
+hi， expert As my described， my function interface have many materials and textures need scale/render to one surface, It's hard for me modify the process flow, so I want to create a surface with pbuffer which can pass to function interface or use a opengl interface like glReadPixel copy the output buffer to display buffer. This problem bothered me for a long time, I need you help. Thanks!
+
+Hello, glReadPixels should work - not sure why you are seeing that error. Can you please review all the arguments and make sure they are okay? But please know that glReadPixels may have a performance hit - but should certainly get you the required data. As I mentioned in my previous post, app_linux_arm_opengl_mosaic shows how to handle GPU to display. Regards Hemant
+
+Thanks for your reply! I am already reference the app_linux_arm_opengl_mosaic demo, I modified my program, replace the function code call glBindFramebuffer (GL_FRAMEBUFFER, 0) to glBindFramebuffer (GL_FRAMEBUFFER, disp_fb), then call glFramebufferTexture2D bind the texture need render to current framebuffer, but there are some errors arised， This is the log ### glCheckFramebufferStatus not completed! status 36054 GL: after eglSwapBuffers() glError (0x506) If I deleted glFramebufferTexture2D , no error log print out, but there is also no display. If I keep call glBindFramebuffer (GL_FRAMEBUFFER, 0) in my app, the glCheckFramebufferStatus also report error, is't means there is no default framebuffer ?
+
+hello: I did some test of that , when glBindFramebuffer(GL_FRAMEBUFFER, 0) glCheckFramebufferStatus return 0x8219 which GL_FRAMEBUFFER_UNDEFINED, so EGL_NO_SURFACE which means no default framebuffer, so I call glBindFramebuffer (GL_FRAMEBUFFER, fboid) and glFramebufferTexture2D , fixed some bugs of my app, glCheckFramebufferStatus return ok, and I can see some color output to my screen（but not correct）, I think this is because my default render flow not suitable the new draw flow。 I know on tda4vm QNX can create a surface with buffer, which can pass to my app, so there is't need modify the render flow. so my question is can I create a surface with a buffer on linux?
+
+resolved! please close it!
+

sample_embedding_folder/1046205.txt

@@ -0,0 +1,8 @@
+Ticket Name: TDA2SX: How to change the DDR memory size on the tda2?
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, Two DDRs are used in our own tda2 board, each of which is 2GB, with a total of 4GB. It is found that the default memory node in DTS is 1GB. After changing it to 4GB, it is found that the kernel cannot be started. How can I use all 4GB of memory?
+
+Responses:
+Hi, Can you please let me know on how you confirmed on the total of 4GB? Do you have a custom board or you are using standard TI TDA2SX EVM? The max that can be supported can be upto 4GB but I believe on the TI Board it is 2GB DDR. Can you share the links on 4GB DDR? Best Regards, Keerthy
+

sample_embedding_folder/1046305.txt

@@ -0,0 +1,61 @@
+Ticket Name: TDA2HF: Set DSS parameter failed when Display_Link was creating
+
+Query Text:
+Part Number: TDA2HF In PROCESSOR_SDK_VISION_03_08_00_00,i builded a chain: capture->vpe->display vpe params was set as below: 
+static Void chains_vipSingleCam_Enc_Dec_SgxDisplay_SetVPEPrms(
+VpeLink_CreateParams *pPrm,
+UInt32 numLvdsCh,
+UInt32 displayWidth,
+UInt32 displayHeight,
+UInt32 inputWidth,
+UInt32 inputHeight
+)
+{
+UInt16 chId;
+
+pPrm->enableOut[0] = TRUE;
+
+for(chId = 0; chId < numLvdsCh; chId++)
+{
+pPrm->chParams[chId].outParams[0].numBufsPerCh =
+VPE_LINK_NUM_BUFS_PER_CH_DEFAULT;
+
+pPrm->chParams[chId].outParams[0].width = displayWidth;
+pPrm->chParams[chId].outParams[0].height = displayHeight;
+pPrm->chParams[chId].outParams[0].dataFormat =SYSTEM_DF_RGB24_888 ;
+
+pPrm->chParams[chId].scCfg.bypass = FALSE;
+pPrm->chParams[chId].scCfg.nonLinear = FALSE;
+pPrm->chParams[chId].scCfg.stripSize = 0;
+
+pPrm->chParams[chId].scCropCfg.cropStartX = 32;
+pPrm->chParams[chId].scCropCfg.cropStartY = 24;
+pPrm->chParams[chId].scCropCfg.cropWidth = inputWidth-32;
+pPrm->chParams[chId].scCropCfg.cropHeight = inputHeight-24;
+}
+}
+ then i got assert as below: [HOST] [IPU1-0]     57.923595 s: CaptureLink_drvAllocAndQueueFrames:1553:FVID2_queue: captureVipHandle=0x9f11b880, frameList.numFrames=6, streamId=0
+ [HOST] [IPU1-0]     57.923961 s:  CAPTURE: Create Done !!!
+ [HOST] [IPU1-0]     57.924388 s:  VPE: Create in progress !!!
+ [HOST] [IPU1-0]     57.925242 s: wwlog:vpe set flag=82176,format=20
+ [HOST] [IPU1-0]     58.164765 s:  VPE: Loading Down-scaling Co-effs
+ [HOST] [IPU1-0]     58.164978 s:  VPE: Co-effs Loading ... DONE !!!
+ [HOST] [IPU1-0]     58.165222 s:  VPE: Create Done !!!
+ [HOST] [IPU1-0]     58.165649 s:  DISPLAY: Create in progress !!!
+ [HOST] [IPU1-0]     58.165954 s:    wwlog: repliEnalbe is false before set!!!!!
+ [HOST] [IPU1-0]     58.166046 s: wwlog: repliEnalbe set true
+ [HOST] [IPU1-0]     58.166107 s: wwlog: display get flag= 82176,format=20
+ [HOST] [IPU1-0]     58.166168 s: wwlog: display will create in SYSTEM_DF_RGB24_888!!!!!
+ [HOST] [IPU1-0]     58.166320 s: hal/src/vpshal_dssDispcVid.c @ Line 1023:
+ [HOST] [IPU1-0]     58.166412 s: Invalid Data format
+ [HOST] [IPU1-0]     58.166595 s: dispdrv/src/vpsdrv_displayCore.c @ Line 304:
+ [HOST] [IPU1-0]     58.166687 s: Set DSS parameter failed
+ [HOST] [IPU1-0]     58.166748 s:  Assertion @ Line: 474 in displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!! But when i use capture->vpe->sgxFmcpy(A15)->display,display_link can run normal in SYSTEM_DF_BGRA16_4444 . I want to know why dispaly_link cant be creanted in SYSTEM_DF_RGB24_888,or how to make display_link run in SYSTEM_DF_RGB24_888 .
+
+Responses:
+Hi, I think DSS does not support RGB24_888 format, ie R in lower byte, followed by G, followed by B. DSS supports BGR24_888 format, So can you try changing it to system_df_BGR24_888 format? Regards, Brijesh
+
+Thanks for your reply. Dont know why ,but display does run normal with BGR24_888,
+
+Because it is only supported in the DSS. The other RGB packed format is not supported.
+

sample_embedding_folder/1046872.txt

@@ -0,0 +1,12 @@
+Ticket Name: TDA2SX: TDA2XSBTQABCRQ1 Display output YUV422 hardware schematic review
+
+Query Text:
+Part Number: TDA2SX Other Parts Discussed in Thread: TDA2 Dear experts, Our customer want to output YUV422 but not sure whether this connection correct according to TDA2 TRM. Can you help review this?
+
+Responses:
+Hi Dong, It really depends on the output interface that they are going to use. If output interface is going to be BT656, then you could use 10bit output lines, ie D0 to D9 or 8bit output data lines D9 to D2. If output interface is going to be discrete sync (BT601, yuv22 discrete sync), then 8bit data would be on D7-D0 data lines.. Regards, Brijesh
+
+Hi Brijesh, Thanks for your reply. It's very helpful to me. They have another question is how to configure BT656 or BT601 output in the SDK code.
+
+Hi Dong, Unfortunately, EVM does not support BT656 or BT601 output interface, so SDK does not support or have any usease to demonstrate it. Regards, Brijesh
+

sample_embedding_folder/1048217.txt

@@ -0,0 +1,24 @@
+Ticket Name: PROCESSOR-SDK-TDAX: "AR12XX: FAULT: BSS CPU fault!!" seen frequently, forcing user to reboot radar
+
+Query Text:
+Part Number: PROCESSOR-SDK-TDAX Other Parts Discussed in Thread: MMWCAS-DSP-EVM, MMWCAS-RF-EVM, AWR2243, AWR1243, TDA2 Hello, I have an MMWCAS-RF-EVM mounted on MMWCAS-DSP-EVM. I'm using PROCESSOR_SDK_RADAR_ 3.08 and often times I'm seeing this error on my terminal window. [IPU1-0] 1300.877569 s: radar_ar12xx/src/bspdrv_ar12xxPriv.c @ Line 541: [IPU1-0] 1300.877691 s: AR12XX: FAULT: BSS CPU fault!! [IPU1-0] 1300.877783 s: radar_ar12xx/src/bspdrv_ar12xxPriv.c @ Line 545: [IPU1-0] 1300.877844 s: AR12XX: FAULT: ESM fault!! [IPU1-0] 1301.117214 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.117336 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.117458 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.150216 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.150369 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large [IPU1-0] 1301.150460 s: SyncLink: dropping frame due to time delta(-2084364888ms) too large I am forced to reboot the radar if I want to continue working with it. The hardware version reported by the serial terminal is ES3.0. I don't seem to have this problem happen this frequently in the ES1.0 hardware that I have. Please tell me how to isolate and fix this problem? Is there a firmware update I'm missing? Thanks Asher
+
+Responses:
+Hi, ES1.0 and ES2.0 have different version of radar firmware. During radar init, it should try to check the revision of radar and download the corresponding firmware. You can check the log to see if the ES version of radar was detected correctly. Regards, Stanley
+
+Hi Stanley, We have 2 Cascade RF boards where both boards have AWR2243 transceivers. However one board has hwMajor of 1 and the other has hwMajor 3. We believe these numbers represent ES1.0 and ES3.0. Since we have 2 AWR FW binary files for AWR1243 and AWR2243, Both cascade boards are downloaded with 2243 FW disregards whether one is an ES1.0 and the other is an ES3.0. That's how we modified the TDA2 bootup code to detect and behave. Please tell us if that assumption is correct. Now back to the BSS and ESM Faults above, we've seen this error showed up very often on the ES3.0 HW version vs the ES1.0 HW version even though both are running with same 2243 FW. So we are wondering if ES3.0 HW version has an updated FW for it to be used that fixes above errors seen? Thank you, --Khai
+
+Hi Khai, I have forwarded this question to our Radar team to comment. In Radar SDK, only AWR1243 ES1.0 and 2.0 firmware have been tested. Regards, Stanley
+
+Hi, Unfortunately, as mentioned by Stanley the Radar Processor SDK demo is not validated with AWR2243. There are some patches available in this forum provided by some forum members but they are not validated by TI We would have to open this question to the forum community for further support thank you Cesar
+
+Hi Khai, If you refer mmWave DFP 2.2.3.1 example, where same code works for both AWR2243 ES1.0 and ES1.1 based on HW version. You need to implement similar logic in your application C:\ti\mmwave_dfp_02_02_03_01\ti\example\mmWaveLink_SingleChip_Example\mmw_example.c retVal = rlDeviceGetMssVersion(deviceMap, &mssFwVer); /* For AWR2243 ES1.0 MSS ROM FW version '2.2.0.3' and ES1.1: '2.2.1.7' */ if ((mssFwVer.fwBuild == 1) && (mssFwVer.fwDebug == 7)) { gMmwaveSensorEs1_1 = AWR2243_ES1_1; } else { gMmwaveSensorEs1_1 = AWR2243_ES1_0; } Similar way you can check first the AWR1243 MSS ROM version which will have some definite value for ES1.0/2.0/3.0 Silicon samples and based on that select the matching FW version to download. Regards, Jitendra
+
+Hi Jiten, So is there a ES3.0 AWR2243 FW you can send us? In the HW detection, what parameters constitute to AWR2243 ES3.0 device? Thanks, --Khai
+
+There is no AWR2243ES 3.0, only ES 1.0 and ES 1.1 There was an AWR1243 ES3.0 Thank you Cesar
+
+Hi Jiten, Thanks for the clarification. So we have 2 FWs built into the AppImage in TDA2. One for 1243 and one for 2243 since we have both Cascade RF board in 1243 and 2243. My questions are: 1. What is the logic to detect AWR models (1243 or 2243)? 2. If it's 1243, would the same 1243 FW be compatible with all ESx version? 3. If it's 2243, would the same 2243 FW be compatible with all ES1.0 or 1.1 version? Thanks, --Khai
+
+The FW release are usually not compatible. The DFP release notes mention the ES supported. Thank you Cesar
+

sample_embedding_folder/1049699.txt

@@ -0,0 +1,8 @@
+Ticket Name: DRA756: EMMC linux driver issue
+
+Query Text:
+Part Number: DRA756 Hi. sdk: PROCESSOR_SDK_VISION_03_05_00_00 For the same software, only the SOC of the two boards is different. One uses tda2s and the other uses dra756. Tda2s can use EMMC ddr50 mode.while dra756 cannot use ddr50 mode,Dra756 can use EMMC HS mode dts: &mmc2 { status = "okay"; vmmc-supply = <&evm_3v3_sw>; bus-width = <8>; max-frequency = <192000000>; pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v","ddr50"; pinctrl-0 = <&mmc2_pins_default>; pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev11_conf>; pinctrl-3 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_rev20_conf>; pinctrl-4 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev11_conf>; pinctrl-5 = <&mmc2_pins_hs200_1_8v &mmc2_iodelay_hs200_1_8v_rev20_conf>; }; dr756 emmc ddr50 mode log: [ 1.072168] ldousb: disabling [ 1.073427] omap8250 4806a000.serial: failed to request DMA [ 1.074258] Waiting for root device PARTUUID=dda7f685-03... [ 1.163294] mmc0: host does not support reading read-only switch, assuming write-enable [ 1.168022] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 1.169218] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 1.174636] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 p8 p9 > [ 1.220299] mmc1: MAN_BKOPS_EN bit is not set [ 1.223227] mmc1: new DDR MMC card at address 0001 [ 1.224159] mmcblk1: mmc1:0001 8GUF4R 7.28 GiB [ 1.224893] mmcblk1boot0: mmc1:0001 8GUF4R partition 1 31.9 MiB [ 1.225796] mmcblk1boot1: mmc1:0001 8GUF4R partition 2 31.9 MiB [ 1.226886] omap_hsmmc 480b4000.mmc: ADMA err: ST_TFR, desc at 0xfe441008 follows the erroneous one [ 1.228069] mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00 [ 1.229261] mmcblk1: retrying using single block read [ 1.229960] mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 1.231130] blk_update_request: I/O error, dev mmcblk1, sector 0 [ 1.231951] mmcblk1: error -84 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 [ 1.233120] blk_update_request: I/O error, dev mmcblk1, sector 1 [ 1.233945] mmcblk1: error -84 transferring data, sector 2, nr 6, cmd response 0x900, card status 0x0 [ 1.235114] blk_update_request: I/O error, dev mmcblk1, sector 2 [ 1.235931] mmcblk1: error -84 transferring data, sector 3, nr 5, cmd response 0x900, card status 0x0 [ 1.237100] blk_update_request: I/O error, dev mmcblk1, sector 3 [ 1.237917] mmcblk1: error -84 transferring data, sector 4, nr 4, cmd response 0x900, card status 0x0 [ 1.239084] blk_update_request: I/O error, dev mmcblk1, sector 4 [ 1.239903] mmcblk1: error -84 transferring data, sector 5, nr 3, cmd response 0x900, card status 0x0 [ 1.241072] blk_update_request: I/O error, dev mmcblk1, sector 5 [ 1.241890] mmcblk1: error -84 transferring data, sector 6, nr 2, cmd response 0x900, card status 0x0 [ 1.243057] blk_update_request: I/O error, dev mmcblk1, sector 6 [ 1.243873] mmcblk1: error -84 transferring data, sector 7, nr 1, cmd response 0x900, card status 0x0 [ 1.245057] blk_update_request: I/O error, dev mmcblk1, sector 7 [ 1.245822] Buffer I/O error on dev mmcblk1, logical block 0, async page read [ 1.246800] omap_hsmmc 480b4000.mmc: ADMA err: ST_TFR, desc at 0xfe441008 follows the erroneous one [ 1.247980] mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00 [ 1.249170] mmcblk1: retrying using single block read [ 1.249869] mmcblk1: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0 [ 1.251036] blk_update_request: I/O error, dev mmcblk1, sector 0 [ 1.251859] mmcblk1: error -84 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 [ 1.253027] blk_update_request: I/O error, dev mmcblk1, sector 1 [ 1.253845] mmcblk1: error -84 transferring data, sector 2, nr 6, cmd response 0x900, card status 0x0 [ 1.255082] mmcblk1: error -84 transferring data, sector 3, nr 5, cmd response 0x900, card status 0x0 [ 1.256310] mmcblk1: error -84 transferring data, sector 4, nr 4, cmd response 0x900, card status 0x0 [ 1.257532] mmcblk1: error -84 transferring data, sector 5, nr 3, cmd response 0x900, card status 0x0 [ 1.258760] mmcblk1: error -84 transferring data, sector 6, nr 2, cmd response 0x900, card status 0x0 [ 1.259982] mmcblk1: error -84 transferring data, sector 7, nr 1, cmd response 0x900, card status 0x0 [ 1.261153] Buffer I/O error on dev mmcblk1, logical block 0, async page read [ 1.262070] mmcblk1: unable to read partition table [ 1.532364] EXT4-fs (mmcblk0p3): recovery complete
+
+Responses:
+Hi GJ, Is this still an open issue for you or were you able to resolve the issue yourself? regards Suman
+

sample_embedding_folder/1049857.txt

@@ -0,0 +1,10 @@
+Ticket Name: PROCESSOR-SDK-TDAX: Is there a way to program the user Programmable LEDs in TIDEP-01017?
+
+Query Text:
+Part Number: PROCESSOR-SDK-TDAX Hi, I'm using MMWCAS_DSP_EVM with Processor SDK Radar 3.08 and according to the User guide of the board, these LEDs(in Table) are user-programmable. I was wondering if I can get guidance on how to program these LEDs from the Radar SDK. I would greatly appreciate it.
+
+Responses:
+Hi, These LEDs are connected to GPIO expander output. The same GPIO expander is also configured in Bsp_boardTda2xxCascadeEnableSdAndEth() under ~\ti_components\drivers\pdk\packages\ti\drv\vps\src\boards\src\bsp_boardTda2xx.c. You can refer to that function to see how to configure the specific output of the GPIO Expander via I2C command. Regards, Stanley
+
+Hi Stanley, Thank you for the response. We were able to run this example located in ~\ti_components\drivers\pdk_01_10_04_05\packages\ti\csl\example\i2c\i2c_led_blink\main.c After modifying the slave address for the correct Port Expander (0x76 instead of 0x20), and were able to blink all those LEDs. Although we had to modify the sample code based on the datasheet(configuring the ports to become output before switching them ON/OFF).
+