sample_embedding_folder/774451.txt

Ticket Name: TDA2: Cascade Radar Host Processor Board to 20 channels

Query Text:
Part Number: TDA2 Other Parts Discussed in Thread: AWR1243 Cascade Radar Host Processor Board PROC055 with TDA2 mates with the AWR1243 PROC054 and has 4 chips with 4 channels each so 16 channels. We need to add another AWR1243 so we have 20 channels. In this case we will need to add a 5th FPGA to get the VIP frame for the TDA2. On the TDA2 ports VIP5 and VIP6 are only 16 bits wide not the 24 bits wide of VIP1, VIP2, VIP3 and VIP4. How should be proceed to enable 5 AWR1243 chips radar channels per TDA2?

Responses:
Hi Zach, We are currently using only 16 bits in the current SDK for capturing the data on the TDA to capture each of the 4 AWR1243 data. You can use the same for the 5th AWR. BTW the software which supports cascade board is available in www.ti.com/.../processor-sdk-tdax for reference. Thanks and Regards, Piyali

Hi Piyali, If we will use 16 bit mode as you indicated here, is it the MSB 16 bits for the 24 bits for the LSB 16 bits needed? Thank you, Zach

Hi Zach, Lower 16 bits (15:0). Thanks and Regards, Piyali