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TPS7A4501-SP: Stability and Power Dissipation

Part Number: TPS7A4501-SP 1) I have put 10uF capacitors at the input and output end of the LDO TPS7A4501-SP. What value of capacitor (between Vout and ADJ) is required to get better phase margin and reduced noise? 2) What is the maximum power dissipation of the device TPS7A4501-SP?

Akash, 1) There is a section in the datasheet that discusses compensation and the calculations associated with it for your particular requirements. See 9.2.2.2. 9.2.2.1 also has good information regarding the choice of capacitor. 2) There are several sections of the datasheet that are pertinent for managing thermal performance of the device. Key points. Recommended operating junction maximum temperature is 125c. So, this is the value you must design to to insure device is operating under warranted specifications. The HKU packaged device has a thermal landing that is necessary to electrically and thermally connect to the board. This improves the devices ability to dissipate heat to the board. There is a table of thermal properties for each of the 2 package types in section 7.4. Use the appropriate value depending on your package. From this table, use the information in section 11.3. to calculate the maximum junction temperature with your configuration. (Vin, Vout, Iout, case temp, ...) This will take into account the amount of power that is required to be dissipated internally due to device being a linear regulator. Additionally, there is general information on the thermal metrics and calculations in this application note. This application note is linked in the datasheet in the Thermal information table section 7.4. If this answers your question, please click "This Resolved My Issue" Regards, Wade

In datasheet section 9.2.2.2, the second pole and zero frequency is calculated using C3=470pF. But how to know the phase margin is improved using 470pF capacitor and what is the first pole frequency. Also how it reduce the output noise? How to know that 470pF will work or any other value is required?

Akash, The datasheet does not go into detail on optimization of the Cff capacitance. This application note describes equation to optimize Cff based on centering the pole an zero around the non Cff response. See With respect to quantifying the noise improvement. I do not have any data that would help quantifying Cff selection for improved noise response. An estimate of phase margin improvement can be ascertained by utilizing the WCA models and fine tuning the Cff as most appropriate for your design. The WCA model for pspice is available in the product folder. If this answers your question, please click "This Resolved My Issue" Regards, Wade