sample_embedding_folder2/0608451.txt

Ticket Name: TDA2x (ADAS) Ethernet problems

Query Text:
Other Parts Discussed in Thread: TDA2 Dear support, I am trying to get Ethernet working on a TDA2 SoC with a DP83848Q PHY. I have reuesed the Ethernet driver from the VISION_SDK_02_08_00_00; I think this driver should run on the Vayu board. On my board I got receive and transmit working with this driver, but I have noticed that there are packets lost on both directions (receice and transmit). On my board only D0 and D1 is connected for transmit and receive to the DP83848Q. The connection is direct with a 22Ohms series resistor and not with a multiplexer in between as on the Vayu board. For the TDA2 SoC I have reused the pad configuration from the SDK. I have verified the 50MHz clock for the DP83848Q and TDA2 (RMII0_MHZ_50_CLK) is fine, the reset and power supply of DP83848Q is stable. Do you have any idea what I could try or what could cause the packet loss on my setup? For testing I would like to try to set the PHY to loopback mode; How do we have to setup the GMACSW_Config structure to enable the loopback mode in PHY? Best regards, Erwin

Responses:
Hi Erwin, First, do you have all connections in place described in TRM Figure 24-178. RMII Interface Typical Application? Also, did you setup the CPSW for RMII mode? And did you check the PHY is discoverable via MDIO? Regards, Stan

Hi Stan, Yes, all the connections are there; RMII mode is setup and the PHY is discoverable. When connecting with a PC via crossed over cable the link will be established. Data transfer works in both direction, but packets are lost in both direction. Best regards, Erwin

Ok, can you post your strap pins configuration defined in PHY datasheet, 3.8 Strap Options? You said you use a crossed-over cable. Did you try with straight cable? Both should be ok, but just in case. '22-ohm termination' Where did this requirement came from? I could find 50-ohm recommendation in the datasheet. But first you may want to capture the waveforms and compare them vs. . Section 7 RMII Interface Timing Requirements. Regards, Stan