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| { | |
| "ticketNumber" : "1006560", | |
| "reporterName" : "dsafdf dsfaf", | |
| "rankPoints" : "90", | |
| "resolutionStatus" : "", | |
| "ticketName" : "TDA2EXEVM: uart2 of tda2x cant read data correctly", | |
| "rankName" : "Prodigy", | |
| "replies" : "", | |
| "views" : "", | |
| "queryText" : "Part Number: TDA2EXEVM Other Parts Discussed in Thread: DRA742, PCF8575, TLV320AIC3106, WL1835, TDA2 My question is : when my tda2x's uart2 connect to external mcu,mcu send 12 bytes per 2 sends,but tda2xx cant read data correctly from uart2. sometimes lost data,sometimes wait for a long time to get data. This is our board info: CPU : DRA752-GP ES2.0 Model: TI DRA742 Board: DRA74x EVM REV DRAM: 2 GiB NAND: 0 MiB here, we configure uart2 in dtb such as: uart2: serial@4806c000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x4806c000 0x100>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = \"uart2\"; clock-frequency = <48000000>; status = \"okay\"; dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; dma-names = \"tx\", \"rx\"; }; When we enter filesystem,we call omapconf to configure pinmux: omapconf write 0x4a0037f0 0xd0004 //rx uart2 omapconf write 0x4a0037f4 0x90004 //tx uart2 omapconf write 0x4a0037f8 0x00060103 omapconf write 0x4a0037fc 0x00060103 when i write data to /dev/ttyS1 then use oscilloscope to test,it's correct: #!/bin/bash while((1 == 1)) do echo \"haha\" > /dev/ttyS1 sleep 1 done when i use oscilloscope to test tx of mcu's uart port ,i got correct wave format!!!! This is to say,mcu send data correctly.", | |
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| "partNumber" : "NA", | |
| "allResponseList" : [ { | |
| "contentId" : "", | |
| "userName" : "Keerthy J", | |
| "rankPoints" : "132000", | |
| "rankName" : "TI__Guru***", | |
| "date" : "", | |
| "userId" : "/members/1025801", | |
| "content" : "Hi, So can you confirm from where the below is sent? dsafdf dsfaf said: while((1 == 1)) do echo \"haha\" > /dev/ttyS1 sleep 1 done Also can you paste the output of: stty -F /dev/ttyS1 -a Regards, Keerthy", | |
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| "contentId" : "", | |
| "userName" : "dsafdf dsfaf", | |
| "rankPoints" : "90", | |
| "rankName" : "Prodigy", | |
| "date" : "", | |
| "userId" : "/members/6393729", | |
| "content" : "Executed on tda2x: ========================================== while((1 == 1)) do echo \"haha\" > /dev/ttyS1 sleep 1 done ============================================ root@dra7xx-evm:~# stty -F /dev/ttyS1 -a speed 115200 baud;stty: /dev/ttyS1 line = 0; intr = ^C; quit = ^\\; erase = ^?; kill = ^U; eof = ^D; eol = <undef>; eol2 = <undef>; swtch = <undef>; start = ^Q; stop = ^S; susp = ^Z; rprnt = ^R; werase = ^W; lnext = ^V; flush = ^O; min = 1; time = 0; -parenb -parodd -cmspar cs8 hupcl -cstopb cread clocal -crtscts -ignbrk -brkint -ignpar -parmrk -inpck -istrip -inlcr -igncr icrnl ixon -ixoff -iuclc -ixany -imaxbel -iutf8 opost -olcuc -ocrnl onlcr -onocr -onlret -ofill -ofdel nl0 cr0 tab0 bs0 vt0 ff0 isig icanon iexten echo echoe echok -echonl -noflsh -xcase -tostop -echoprt echoctl echoke -flusho -extproc", | |
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| }, { | |
| "contentId" : "", | |
| "userName" : "dsafdf dsfaf", | |
| "rankPoints" : "90", | |
| "rankName" : "Prodigy", | |
| "date" : "", | |
| "userId" : "/members/6393729", | |
| "content" : "We use uart2 of tda2x for transport data,should i turn on \"raw\" property of uart2??? When i send only one character 'a' by uart1 of tda2x,i see the wave on oscilloscope: 0x61,0x0d,0x0a When i send two characters \"aa\" by uart1 of tda2x,i see the wave on oscilloscope:0x61 0x61 0x0d 0x0a, so ,when i transport data from mcu to tda2x,should i write \\n ？？？", | |
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| }, { | |
| "contentId" : "", | |
| "userName" : "dsafdf dsfaf", | |
| "rankPoints" : "90", | |
| "rankName" : "Prodigy", | |
| "date" : "", | |
| "userId" : "/members/6393729", | |
| "content" : "HELLO？？？ anyone there？？？", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Keerthy J", | |
| "rankPoints" : "132000", | |
| "rankName" : "TI__Guru***", | |
| "date" : "", | |
| "userId" : "/members/1025801", | |
| "content" : "Hello, 0x61,0x0d,0x0a --> a followed by CR(Carriage Return) & LF(Line Feed) 0x61, 0x61,0x0d,0x0a --> 'a' followed by 'a' followed by CR(Carriage Return) & LF(Line Feed) Seems like your TX is working. Have you tried the same from PC side before trying on MCU side? Best Regards, Keerthy", | |
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| }, { | |
| "contentId" : "", | |
| "userName" : "dsafdf dsfaf", | |
| "rankPoints" : "90", | |
| "rankName" : "Prodigy", | |
| "date" : "", | |
| "userId" : "/members/6393729", | |
| "content" : "Yes,i used another uart device ,one port connect to pc and recognized as /dev/ttyUSB0,another port(rx,tx,gnd) connected to uart1 of tda2x. So,i write 0xaa to /dev/ttyUSB0 on my linux pc,and read nothing on tda2x... so,what can i do now ???", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "dsafdf dsfaf", | |
| "rankPoints" : "90", | |
| "rankName" : "Prodigy", | |
| "date" : "", | |
| "userId" : "/members/6393729", | |
| "content" : "the dtb configures of uart1 and uart2 are different. serial@4806a000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x4806a000 0x100>; interrupts-extended = <0x1 0x0 0x43 0x4 0x8c 0x3e0>; ti,hwmods = \"uart1\"; clock-frequency = <0x2dc6c00>; status = \"okay\"; dmas = <0x8d 0x31 0x8d 0x32>; dma-names = \"tx\", \"rx\"; }; serial@4806c000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x4806c000 0x100>; interrupts = <0x0 0x44 0x4>; ti,hwmods = \"uart2\"; clock-frequency = <0x2dc6c00>; status = \"okay\"; dmas = <0x8d 0x33 0x8d 0x34>; dma-names = \"tx\", \"rx\"; }; and i execute cat /proc/interrupts,only uart1's interrupt was found. root@dra7xx-evm:~# cat /proc/interrupts CPU0 CPU1 17: 0 0 CBAR 32 Level gp_timer 18: 0 0 GICv2 29 Level arch_timer 19: 141230 429490 GICv2 30 Level arch_timer 22: 0 0 CBAR 4 Level l3-dbg-irq 23: 0 0 WUGEN 10 Level l3-app-irq 25: 1 0 CBAR 232 Level dra7xx-pcie-main 26: 0 0 CBAR 233 Level dra7-pcie-msi 27: 1 0 CBAR 121 Level talert 28: 0 0 CBAR 7 Level DMA 29: 4710 0 CBAR 8 Level omap-dma-engine 32: 0 0 CBAR 361 Level 43300000.edma_ccint 34: 0 0 CBAR 359 Level 43300000.edma_ccerrint 37: 0 0 CBAR 24 Level 4ae10000.gpio 38: 0 0 CBAR 25 Level 48055000.gpio 39: 0 0 CBAR 26 Level 48057000.gpio 40: 0 0 CBAR 27 Level 48059000.gpio 41: 0 0 CBAR 28 Level 4805b000.gpio 42: 0 0 CBAR 29 Level 4805d000.gpio 43: 0 0 CBAR 30 Level 48051000.gpio 44: 0 0 CBAR 116 Level 48053000.gpio 45: 1843 0 CBAR 67 Level 4806a000.serial 46: 6821 0 CBAR 68 Level 50: 496 0 CBAR 251 Level mbox_dsp1_ipc3x 54: 509 0 CBAR 255 Level mbox_ipu2_ipc3x, mbox_dsp2_ipc3x 71: 2 0 CBAR 108 Level omap_dmm_irq_handler 72: 463 0 CBAR 51 Level 48070000.i2c 73: 0 0 CBAR 56 Level 48060000.i2c 74: 0 0 CBAR 57 Level 4807a000.i2c 75: 5588 0 CBAR 78 Level mmc0 76: 0 0 CBAR 53 Level omap_hdq 77: 724 0 CBAR 81 Level mmc1 78: 52 0 CBAR 91 Level mmc2 79: 0 0 CBAR 23 Level 40d01000.mmu 80: 0 0 CBAR 145 Level 40d02000.mmu 81: 0 0 CBAR 395 Level 58882000.mmu 82: 0 0 CBAR 396 Level 55082000.mmu 83: 0 0 CBAR 61 Level 4809a000.spi 85: 0 0 CBAR 49 Level ahci[4a140000.sata] 86: 0 0 CBAR 217 Level rtc0 89: 0 0 CBAR 1 Level 48078000.elm 93: 3786 0 CBAR 335 Level 48484000.ethernet 94: 157 0 CBAR 336 Level 48484000.ethernet 97: 2 0 CBAR 16 Level SGX ISR 102: 0 0 CBAR 46 Level 4b101000.sham 103: 1 0 CBAR 47 Level 48090000.rng 104: 0 0 CBAR 146 Level 41501000.mmu 105: 0 0 CBAR 147 Level 41502000.mmu 106: 0 0 WUGEN 131 Level arm-pmu 107: 0 0 WUGEN 132 Level arm-pmu 174: 0 0 PCI-MSI 0 Edge PCIe PME, aerdrv 175: 0 0 pinctrl 992 Edge 4806a000.serial:wakeup 176: 0 0 4805d000.gpio 27 Edge 4809c000.mmc cd IPI0: 0 1 CPU wakeup interrupts IPI1: 0 0 Timer broadcast interrupts IPI2: 1885 16991 Rescheduling interrupts IPI3: 567 883 Function call interrupts IPI4: 0 0 CPU stop interrupts IPI5: 0 0 IRQ work interrupts IPI6: 0 0 completion interrupts Err: 0", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Keerthy J", | |
| "rankPoints" : "132000", | |
| "rankName" : "TI__Guru***", | |
| "date" : "", | |
| "userId" : "/members/1025801", | |
| "content" : "Can you share you dtb? I will try to reverse compile dts and check if the uart1 node is indeed present in your dts. Best Regards, Keerthy", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "dsafdf dsfaf", | |
| "rankPoints" : "90", | |
| "rankName" : "Prodigy", | |
| "date" : "", | |
| "userId" : "/members/6393729", | |
| "content" : "/dts-v1/; / { #address-cells = <0x2>; #size-cells = <0x2>; compatible = \"ti,dra7-evm\", \"ti,dra742\", \"ti,dra74\", \"ti,dra7\"; interrupt-parent = <0x1>; model = \"TI DRA742\"; chosen { stdout-path = \"/ocp/serial@4806a000\"; }; aliases { i2c0 = \"/ocp/i2c@48070000\"; i2c1 = \"/ocp/i2c@48072000\"; i2c2 = \"/ocp/i2c@48060000\"; i2c3 = \"/ocp/i2c@4807a000\"; i2c4 = \"/ocp/i2c@4807c000\"; serial0 = \"/ocp/serial@4806a000\"; serial1 = \"/ocp/serial@4806c000\"; serial2 = \"/ocp/serial@48020000\"; serial3 = \"/ocp/serial@4806e000\"; serial4 = \"/ocp/serial@48066000\"; serial5 = \"/ocp/serial@48068000\"; serial6 = \"/ocp/serial@48420000\"; serial7 = \"/ocp/serial@48422000\"; serial8 = \"/ocp/serial@48424000\"; serial9 = \"/ocp/serial@4ae2b000\"; ethernet0 = \"/ocp/ethernet@48484000/slave@48480200\"; ethernet1 = \"/ocp/ethernet@48484000/slave@48480300\"; d_can0 = \"/ocp/can@4ae3c000\"; d_can1 = \"/ocp/can@48480000\"; spi0 = \"/ocp/qspi@4b300000\"; rproc0 = \"/ocp/ipu@58820000\"; rproc1 = \"/ocp/ipu@55020000\"; rproc2 = \"/ocp/dsp@40800000\"; rproc3 = \"/ocp/dsp@41000000\"; display0 = \"/connector@1\"; sound0 = \"/sound0\"; sound1 = \"/ocp/dss@58000000/encoder@58060000\"; }; timer { compatible = \"arm,armv7-timer\"; interrupts = <0x1 0xd 0x308 0x1 0xe 0x308 0x1 0xb 0x308 0x1 0xa 0x308>; interrupt-parent = <0x2>; }; interrupt-controller@48211000 { compatible = \"arm,cortex-a15-gic\"; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0 0x48211000 0x0 0x1000 0x0 0x48212000 0x0 0x2000 0x0 0x48214000 0x0 0x2000 0x0 0x48216000 0x0 0x2000>; interrupts = <0x1 0x9 0x304>; interrupt-parent = <0x2>; phandle = <0x2>; }; interrupt-controller@48281000 { compatible = \"ti,omap5-wugen-mpu\", \"ti,omap4-wugen-mpu\"; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0 0x48281000 0x0 0x1000>; interrupt-parent = <0x2>; phandle = <0x8>; }; cpus { #address-cells = <0x1>; #size-cells = <0x0>; cpu@0 { device_type = \"cpu\"; compatible = \"arm,cortex-a15\"; reg = <0x0>; operating-points-v2 = <0x3>; clocks = <0x4>; clock-names = \"cpu\"; clock-latency = <0x493e0>; #cooling-cells = <0x2>; vbb-supply = <0x5>; vdd-supply = <0x6>; phandle = <0xfc>; }; cpu@1 { device_type = \"cpu\"; compatible = \"arm,cortex-a15\"; reg = <0x1>; operating-points-v2 = <0x3>; clocks = <0x4>; clock-names = \"cpu\"; clock-latency = <0x493e0>; #cooling-cells = <0x2>; vbb-supply = <0x5>; }; }; opp-table { compatible = \"operating-points-v2-ti-cpu\"; syscon = <0x7>; opp-shared; phandle = <0x3>; opp_nom-1000000000 { opp-hz = <0x0 0x3b9aca00>; opp-microvolt = <0x102ca0 0xcf850 0x118c30 0x102ca0 0xcf850 0x118c30>; opp-supported-hw = <0xff 0x1>; opp-suspend; }; opp_od-1176000000 { opp-hz = <0x0 0x46185600>; opp-microvolt = <0x11b340 0xd8108 0x11b340 0x11b340 0xd8108 0x11b340>; opp-supported-hw = <0xff 0x2>; }; opp_high@1500000000 { opp-hz = <0x0 0x59682f00>; opp-microvolt = <0x127690 0xe7ef0 0x1312d0 0x127690 0xe7ef0 0x1312d0>; opp-supported-hw = <0xff 0x4>; }; }; soc { compatible = \"ti,omap-infra\"; mpu { compatible = \"ti,omap5-mpu\"; ti,hwmods = \"mpu\"; }; }; ocp { compatible = \"ti,dra7-l3-noc\", \"simple-bus\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x0 0x0 0xc0000000>; ti,hwmods = \"l3_main_1\", \"l3_main_2\"; reg = <0x0 0x44000000 0x0 0x1000000 0x0 0x45000000 0x0 0x1000>; interrupts-extended = <0x1 0x0 0x4 0x4 0x8 0x0 0xa 0x4>; l4@4a000000 { compatible = \"ti,dra7-l4-cfg\", \"simple-bus\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x4a000000 0x22c000>; scm@2000 { compatible = \"ti,dra7-scm-core\", \"simple-bus\"; reg = <0x2000 0x2000>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x2000 0x2000>; scm_conf@0 { compatible = \"syscon\", \"simple-bus\"; reg = <0x0 0x1400>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x0 0x1400>; phandle = <0x9>; pbias_regulator@e00 { compatible = \"ti,pbias-dra7\", \"ti,pbias-omap\"; reg = <0xe00 0x4>; syscon = <0x9>; pbias_mmc_omap5 { regulator-name = \"pbias_mmc_omap5\"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x325aa0>; phandle = <0xad>; }; }; clocks { #address-cells = <0x1>; #size-cells = <0x0>; dss_deshdcp_clk@558 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0xa>; ti,bit-shift = <0x0>; reg = <0x558>; }; ehrpwm0_tbclk@558 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0xb>; ti,bit-shift = <0x14>; reg = <0x558>; phandle = <0xf0>; }; ehrpwm1_tbclk@558 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0xb>; ti,bit-shift = <0x15>; reg = <0x558>; phandle = <0xf1>; }; ehrpwm2_tbclk@558 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0xb>; ti,bit-shift = <0x16>; reg = <0x558>; phandle = <0xf2>; }; sys_32k_ck { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0xc 0xd 0xd 0xd>; ti,bit-shift = <0x8>; reg = <0x6c4>; phandle = <0x50>; }; }; }; pinmux@1400 { compatible = \"ti,dra7-padconf\", \"pinctrl-single\"; reg = <0x1400 0x468>; #address-cells = <0x1>; #size-cells = <0x0>; #pinctrl-cells = <0x1>; #interrupt-cells = <0x1>; interrupt-controller; pinctrl-single,register-width = <0x20>; pinctrl-single,function-mask = <0x3fffffff>; phandle = <0x8c>; mmc1_pins_default { pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>; phandle = <0xb0>; }; mmc1_pins_sdr12 { pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>; phandle = <0xb2>; }; mmc1_pins_hs { pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>; phandle = <0xb1>; }; mmc1_pins_sdr25 { pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>; phandle = <0xb3>; }; mmc1_pins_sdr50 { pinctrl-single,pins = <0x354 0x601a0 0x358 0x601a0 0x35c 0x601a0 0x360 0x601a0 0x364 0x601a0 0x368 0x601a0>; phandle = <0xb4>; }; mmc1_pins_ddr50 { pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>; phandle = <0xb5>; }; mmc1_pins_sdr104 { pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>; phandle = <0xb7>; }; mmc2_pins_default { pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>; phandle = <0xbc>; }; mmc2_pins_hs { pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>; phandle = <0xbd>; }; mmc2_pins_ddr_3_3v_rev11 { pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>; }; mmc2_pins_ddr_1_8v_rev11 { pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>; phandle = <0xbe>; }; mmc2_pins_ddr_rev20 { pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>; phandle = <0xc0>; }; mmc2_pins_hs200 { pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>; phandle = <0xc1>; }; mmc4_pins_default { pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>; phandle = <0xc6>; }; mmc4_pins_hs { pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>; phandle = <0xc9>; }; mmc3_pins_default { pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>; }; mmc3_pins_hs { pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>; }; mmc3_pins_sdr12 { pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>; }; mmc3_pins_sdr25 { pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>; }; mmc3_pins_sdr50 { pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>; }; mmc4_pins_sdr12 { pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>; phandle = <0xcc>; }; mmc4_pins_sdr25 { pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>; phandle = <0xcd>; }; dcan1_pins_default { pinctrl-single,pins = <0x3d0 0x20000 0x3d4 0x60000>; phandle = <0xea>; }; dcan1_pins_sleep { pinctrl-single,pins = <0x3d0 0x2000f 0x3d4 0x2000f>; phandle = <0xe9>; }; pinmux_mcasp8_axr2_pin { pinctrl-single,pins = <0x2fc 0x10001>; phandle = <0xe6>; }; pinmux_hdmi_i2c_pins_default { pinctrl-single,pins = <0x408 0x50000 0x40c 0x50000>; phandle = <0x10a>; }; pinmux_hdmi_i2c_pins_ddc { pinctrl-single,pins = <0x408 0x50001 0x40c 0x50001>; phandle = <0x10b>; }; }; scm_conf@1c04 { compatible = \"syscon\"; reg = <0x1c04 0x20>; #syscon-cells = <0x2>; phandle = <0x87>; }; scm_conf@1c24 { compatible = \"syscon\"; reg = <0x1c24 0x24>; phandle = <0x85>; }; dma-router@b78 { compatible = \"ti,dra7-dma-crossbar\"; reg = <0xb78 0xfc>; #dma-cells = <0x1>; dma-requests = <0xcd>; ti,dma-safe-map = <0x0>; dma-masters = <0xe>; phandle = <0x8d>; }; dma-router@c78 { compatible = \"ti,dra7-dma-crossbar\"; reg = <0xc78 0x7c>; #dma-cells = <0x2>; dma-requests = <0xcc>; ti,dma-safe-map = <0x0>; dma-masters = <0xf>; phandle = <0xdf>; }; }; cm_core_aon@5000 { compatible = \"ti,dra7-cm-core-aon\", \"simple-bus\"; #address-cells = <0x1>; #size-cells = <0x1>; reg = <0x5000 0x2000>; ranges = <0x0 0x5000 0x2000>; clocks { #address-cells = <0x1>; #size-cells = <0x0>; atl_clkin0_ck { #clock-cells = <0x0>; compatible = \"ti,dra7-atl-clock\"; clocks = <0x10 0x0 0x1a>; phandle = <0xe2>; }; atl_clkin1_ck { #clock-cells = <0x0>; compatible = \"ti,dra7-atl-clock\"; clocks = <0x10 0x0 0x1a>; phandle = <0xe3>; }; atl_clkin2_ck { #clock-cells = <0x0>; compatible = \"ti,dra7-atl-clock\"; clocks = <0x10 0x0 0x1a>; phandle = <0xe4>; }; atl_clkin3_ck { #clock-cells = <0x0>; compatible = \"ti,dra7-atl-clock\"; clocks = <0x10 0x0 0x1a>; phandle = <0xe5>; }; hdmi_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; phandle = <0x30>; }; mlb_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; phandle = <0x81>; }; mlbp_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; phandle = <0x82>; }; pciesref_acs_clk_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x5f5e100>; phandle = <0x40>; }; ref_clkin0_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; }; ref_clkin1_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; }; ref_clkin2_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; }; ref_clkin3_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; }; rmii_clk_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; }; sdvenc_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; }; secure_32k_clk_src_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x8000>; phandle = <0x6b>; }; sys_clk32_crystal_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x8000>; phandle = <0xc>; }; sys_clk32_pseudo_ck { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x11>; clock-mult = <0x1>; clock-div = <0x262>; phandle = <0xd>; }; virt_12000000_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0xb71b00>; phandle = <0x59>; }; virt_13000000_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0xc65d40>; }; virt_16800000_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x1005900>; phandle = <0x5b>; }; virt_19200000_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x124f800>; phandle = <0x5c>; }; virt_20000000_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x1312d00>; phandle = <0x5a>; }; virt_26000000_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x18cba80>; phandle = <0x5d>; }; virt_27000000_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x19bfcc0>; phandle = <0x5e>; }; virt_38400000_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x249f000>; phandle = <0x5f>; }; sys_clkin2 { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x1588800>; phandle = <0x60>; }; usb_otg_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; phandle = <0x68>; }; video1_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; phandle = <0x3a>; }; video1_m2_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; phandle = <0x2f>; }; video2_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; phandle = <0x3b>; }; video2_m2_clkin_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; phandle = <0x2e>; }; dpll_abe_ck@1e0 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-m4xen-clock\"; clocks = <0x12 0x13>; reg = <0x1e0 0x1e4 0x1ec 0x1e8>; phandle = <0x14>; }; dpll_abe_x2_ck { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-x2-clock\"; clocks = <0x14>; phandle = <0x15>; }; dpll_abe_m2x2_ck@1f0 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x15>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x1f0>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x16>; }; abe_clk@108 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x16>; ti,max-div = <0x4>; reg = <0x108>; ti,index-power-of-two; phandle = <0x62>; }; dpll_abe_m2_ck@1f0 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x14>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x1f0>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x64>; }; dpll_abe_m3x2_ck@1f4 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x15>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x1f4>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x17>; }; dpll_core_byp_mux@12c { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x17>; ti,bit-shift = <0x17>; reg = <0x12c>; phandle = <0x18>; }; dpll_core_ck@120 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-core-clock\"; clocks = <0x11 0x18>; reg = <0x120 0x124 0x12c 0x128>; phandle = <0x19>; }; dpll_core_x2_ck { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-x2-clock\"; clocks = <0x19>; phandle = <0x1a>; }; dpll_core_h12x2_ck@13c { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x1a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x13c>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x1b>; }; mpu_dpll_hs_clk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x1b>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x1c>; }; dpll_mpu_ck@160 { #clock-cells = <0x0>; compatible = \"ti,omap5-mpu-dpll-clock\"; clocks = <0x11 0x1c>; reg = <0x160 0x164 0x16c 0x168>; phandle = <0x4>; }; dpll_mpu_m2_ck@170 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x4>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x170>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x1d>; }; mpu_dclk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x1d>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x6f>; }; dsp_dpll_hs_clk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x1b>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x1e>; }; dpll_dsp_byp_mux@240 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x1e>; ti,bit-shift = <0x17>; reg = <0x240>; phandle = <0x1f>; }; dpll_dsp_ck@234 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-clock\"; clocks = <0x11 0x1f>; reg = <0x234 0x238 0x240 0x23c>; assigned-clocks = <0x20>; assigned-clock-rates = <0x23c34600>; phandle = <0x20>; }; dpll_dsp_m2_ck@244 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x20>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x244>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <0x21>; assigned-clock-rates = <0x23c34600>; phandle = <0x21>; }; iva_dpll_hs_clk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x1b>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x22>; }; dpll_iva_byp_mux@1ac { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x22>; ti,bit-shift = <0x17>; reg = <0x1ac>; phandle = <0x23>; }; dpll_iva_ck@1a0 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-clock\"; clocks = <0x11 0x23>; reg = <0x1a0 0x1a4 0x1ac 0x1a8>; assigned-clocks = <0x24>; assigned-clock-rates = <0x45707d40>; phandle = <0x24>; }; dpll_iva_m2_ck@1b0 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x24>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x1b0>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <0x25>; assigned-clock-rates = <0x17257f16>; phandle = <0x25>; }; iva_dclk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x25>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x71>; }; dpll_gpu_byp_mux@2e4 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x17>; ti,bit-shift = <0x17>; reg = <0x2e4>; phandle = <0x26>; }; dpll_gpu_ck@2d8 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-clock\"; clocks = <0x11 0x26>; reg = <0x2d8 0x2dc 0x2e4 0x2e0>; assigned-clocks = <0x27>; assigned-clock-rates = <0x4c1d7940>; phandle = <0x27>; }; dpll_gpu_m2_ck@2e8 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x27>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x2e8>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <0x28>; assigned-clock-rates = <0x195f286b>; phandle = <0x28>; }; dpll_core_m2_ck@130 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x19>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x130>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x29>; }; core_dpll_out_dclk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x29>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x73>; }; dpll_ddr_byp_mux@21c { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x17>; ti,bit-shift = <0x17>; reg = <0x21c>; phandle = <0x2a>; }; dpll_ddr_ck@210 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-clock\"; clocks = <0x11 0x2a>; reg = <0x210 0x214 0x21c 0x218>; phandle = <0x2b>; }; dpll_ddr_m2_ck@220 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x2b>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x220>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x65>; }; dpll_gmac_byp_mux@2b4 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x17>; ti,bit-shift = <0x17>; reg = <0x2b4>; phandle = <0x2c>; }; dpll_gmac_ck@2a8 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-clock\"; clocks = <0x11 0x2c>; reg = <0x2a8 0x2ac 0x2b4 0x2b0>; phandle = <0x2d>; }; dpll_gmac_m2_ck@2b8 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x2d>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x2b8>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x66>; }; video2_dclk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x2e>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x75>; }; video1_dclk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x2f>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x76>; }; hdmi_dclk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x30>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x77>; }; per_dpll_hs_clk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x17>; clock-mult = <0x1>; clock-div = <0x2>; phandle = <0x43>; }; usb_dpll_hs_clk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x17>; clock-mult = <0x1>; clock-div = <0x3>; phandle = <0x47>; }; eve_dpll_hs_clk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x1b>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x31>; }; dpll_eve_byp_mux@290 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x31>; ti,bit-shift = <0x17>; reg = <0x290>; phandle = <0x32>; }; dpll_eve_ck@284 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-clock\"; clocks = <0x11 0x32>; reg = <0x284 0x288 0x290 0x28c>; phandle = <0x33>; }; dpll_eve_m2_ck@294 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x33>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x294>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x34>; }; eve_dclk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x34>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x80>; }; dpll_core_h13x2_ck@140 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x1a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x140>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_core_h14x2_ck@144 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x1a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x144>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x51>; }; dpll_core_h22x2_ck@154 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x1a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x154>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x3d>; }; dpll_core_h23x2_ck@158 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x1a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x158>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x56>; }; dpll_core_h24x2_ck@15c { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x1a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x15c>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_ddr_x2_ck { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-x2-clock\"; clocks = <0x2b>; phandle = <0x35>; }; dpll_ddr_h11x2_ck@228 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x35>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x228>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_dsp_x2_ck { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-x2-clock\"; clocks = <0x20>; phandle = <0x36>; }; dpll_dsp_m3x2_ck@248 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x36>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x248>; ti,index-starts-at-one; ti,invert-autoidle-bit; assigned-clocks = <0x37>; assigned-clock-rates = <0x17d78400>; phandle = <0x37>; }; dpll_gmac_x2_ck { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-x2-clock\"; clocks = <0x2d>; phandle = <0x38>; }; dpll_gmac_h11x2_ck@2c0 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x38>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x2c0>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x39>; }; dpll_gmac_h12x2_ck@2c4 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x38>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x2c4>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_gmac_h13x2_ck@2c8 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x38>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x2c8>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0xd0>; }; dpll_gmac_m3x2_ck@2bc { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x38>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x2bc>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; gmii_m_clk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x39>; clock-mult = <0x1>; clock-div = <0x2>; }; hdmi_clk2_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x30>; clock-mult = <0x1>; clock-div = <0x1>; }; hdmi_div_clk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x30>; clock-mult = <0x1>; clock-div = <0x1>; }; l3_iclk_div@100 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; ti,max-div = <0x2>; ti,bit-shift = <0x4>; reg = <0x100>; clocks = <0x1b>; ti,index-power-of-two; phandle = <0xa>; }; l4_root_clk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0xa>; clock-mult = <0x1>; clock-div = <0x2>; phandle = <0xb>; }; video1_clk2_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x3a>; clock-mult = <0x1>; clock-div = <0x1>; }; video1_div_clk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x3a>; clock-mult = <0x1>; clock-div = <0x1>; }; video2_clk2_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x3b>; clock-mult = <0x1>; clock-div = <0x1>; }; video2_div_clk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x3b>; clock-mult = <0x1>; clock-div = <0x1>; }; dummy_ck { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x0>; }; }; clockdomains { }; mpu_cm@300 { compatible = \"ti,omap4-cm\"; reg = <0x300 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x300 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x4>; #clock-cells = <0x2>; }; }; dsp1_cm@400 { compatible = \"ti,omap4-cm\"; reg = <0x400 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x400 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x4>; #clock-cells = <0x2>; }; }; ipu1_cm@500 { compatible = \"ti,omap4-cm\"; reg = <0x500 0x40>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x500 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x20>; #clock-cells = <0x2>; assigned-clocks = <0x3c 0x0 0x18>; assigned-clock-parents = <0x3d>; phandle = <0x3c>; }; }; ipu_cm@540 { compatible = \"ti,omap4-cm\"; reg = <0x540 0xc0>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x540 0xc0>; clk@0 { compatible = \"ti,clkctrl\"; reg = <0x0 0x44>; #clock-cells = <0x2>; phandle = <0x8f>; }; }; dsp2_cm@600 { compatible = \"ti,omap4-cm\"; reg = <0x600 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x600 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x4>; #clock-cells = <0x2>; }; }; rtc_cm@700 { compatible = \"ti,omap4-cm\"; reg = <0x700 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x700 0x100>; clk@40 { compatible = \"ti,clkctrl\"; reg = <0x40 0x8>; #clock-cells = <0x2>; }; }; }; cm_core@8000 { compatible = \"ti,dra7-cm-core\", \"simple-bus\"; #address-cells = <0x1>; #size-cells = <0x1>; reg = <0x8000 0x3000>; ranges = <0x0 0x8000 0x3000>; clocks { #address-cells = <0x1>; #size-cells = <0x0>; dpll_pcie_ref_ck@200 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-clock\"; clocks = <0x11 0x11>; reg = <0x200 0x204 0x20c 0x208>; phandle = <0x3e>; }; dpll_pcie_ref_m2ldo_ck@210 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x3e>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x210>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x3f>; }; apll_pcie_in_clk_mux@4ae06118 { compatible = \"ti,mux-clock\"; clocks = <0x3f 0x40>; #clock-cells = <0x0>; reg = <0x21c 0x4>; ti,bit-shift = <0x7>; phandle = <0x41>; }; apll_pcie_ck@21c { #clock-cells = <0x0>; compatible = \"ti,dra7-apll-clock\"; clocks = <0x41 0x3e>; reg = <0x21c 0x220>; phandle = <0x42>; }; optfclk_pciephy_div@4a00821c { compatible = \"ti,divider-clock\"; clocks = <0x42>; #clock-cells = <0x0>; reg = <0x21c>; ti,dividers = <0x2 0x1>; ti,bit-shift = <0x8>; ti,max-div = <0x2>; phandle = <0xd3>; }; apll_pcie_clkvcoldo { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x42>; clock-mult = <0x1>; clock-div = <0x1>; }; apll_pcie_clkvcoldo_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x42>; clock-mult = <0x1>; clock-div = <0x1>; }; apll_pcie_m2_ck { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x42>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x6a>; }; dpll_per_byp_mux@14c { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x43>; ti,bit-shift = <0x17>; reg = <0x14c>; phandle = <0x44>; }; dpll_per_ck@140 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-clock\"; clocks = <0x11 0x44>; reg = <0x140 0x144 0x14c 0x148>; phandle = <0x45>; }; dpll_per_m2_ck@150 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x45>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x150>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x46>; }; func_96m_aon_dclk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x46>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x78>; }; dpll_usb_byp_mux@18c { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x47>; ti,bit-shift = <0x17>; reg = <0x18c>; phandle = <0x48>; }; dpll_usb_ck@180 { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-j-type-clock\"; clocks = <0x11 0x48>; reg = <0x180 0x184 0x18c 0x188>; phandle = <0x49>; }; dpll_usb_m2_ck@190 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x49>; ti,max-div = <0x7f>; ti,autoidle-shift = <0x8>; reg = <0x190>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x4d>; }; dpll_pcie_ref_m2_ck@210 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x3e>; ti,max-div = <0x7f>; ti,autoidle-shift = <0x8>; reg = <0x210>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x69>; }; dpll_per_x2_ck { #clock-cells = <0x0>; compatible = \"ti,omap4-dpll-x2-clock\"; clocks = <0x45>; phandle = <0x4a>; }; dpll_per_h11x2_ck@158 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x4a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x158>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x4b>; }; dpll_per_h12x2_ck@15c { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x4a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x15c>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_h13x2_ck@160 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x4a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x160>; ti,index-starts-at-one; ti,invert-autoidle-bit; }; dpll_per_h14x2_ck@164 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x4a>; ti,max-div = <0x3f>; ti,autoidle-shift = <0x8>; reg = <0x164>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x52>; }; dpll_per_m2x2_ck@150 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x4a>; ti,max-div = <0x1f>; ti,autoidle-shift = <0x8>; reg = <0x150>; ti,index-starts-at-one; ti,invert-autoidle-bit; phandle = <0x4c>; }; dpll_usb_clkdcoldo { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x49>; clock-mult = <0x1>; clock-div = <0x1>; phandle = <0x4f>; }; func_128m_clk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x4b>; clock-mult = <0x1>; clock-div = <0x2>; }; func_12m_fclk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x4c>; clock-mult = <0x1>; clock-div = <0x10>; }; func_24m_clk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x46>; clock-mult = <0x1>; clock-div = <0x4>; }; func_48m_fclk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x4c>; clock-mult = <0x1>; clock-div = <0x4>; }; func_96m_fclk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x4c>; clock-mult = <0x1>; clock-div = <0x2>; }; l3init_60m_fclk@104 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x4d>; reg = <0x104>; ti,dividers = <0x1 0x8>; }; clkout2_clk@6b0 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0x4e>; ti,bit-shift = <0x8>; reg = <0x6b0>; }; l3init_960m_gfclk@6c0 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0x4f>; ti,bit-shift = <0x8>; reg = <0x6c0>; }; usb_phy1_always_on_clk32k@640 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0x50>; ti,bit-shift = <0x8>; reg = <0x640>; phandle = <0xd5>; }; usb_phy2_always_on_clk32k@688 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0x50>; ti,bit-shift = <0x8>; reg = <0x688>; phandle = <0xd7>; }; usb_phy3_always_on_clk32k@698 { #clock-cells = <0x0>; compatible = \"ti,gate-clock\"; clocks = <0x50>; ti,bit-shift = <0x8>; reg = <0x698>; phandle = <0xd8>; }; gpu_core_gclk_mux@1220 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x51 0x52 0x28>; ti,bit-shift = <0x18>; reg = <0x1220>; assigned-clocks = <0x53>; assigned-clock-parents = <0x28>; phandle = <0x53>; }; gpu_hyd_gclk_mux@1220 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x51 0x52 0x28>; ti,bit-shift = <0x1a>; reg = <0x1220>; assigned-clocks = <0x54>; assigned-clock-parents = <0x28>; phandle = <0x54>; }; l3instr_ts_gclk_div@e50 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x55>; ti,bit-shift = <0x18>; reg = <0xe50>; ti,dividers = <0x8 0x10 0x20>; }; vip1_gclk_mux@1020 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0xa 0x56>; ti,bit-shift = <0x18>; reg = <0x1020>; }; vip2_gclk_mux@1028 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0xa 0x56>; ti,bit-shift = <0x18>; reg = <0x1028>; }; vip3_gclk_mux@1030 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0xa 0x56>; ti,bit-shift = <0x18>; reg = <0x1030>; }; }; clockdomains { coreaon_clkdm { compatible = \"ti,clockdomain\"; clocks = <0x49>; }; }; coreaon_cm@600 { compatible = \"ti,omap4-cm\"; reg = <0x600 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x600 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x1c>; #clock-cells = <0x2>; phandle = <0xd9>; }; }; l3main1_cm@700 { compatible = \"ti,omap4-cm\"; reg = <0x700 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x700 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x74>; #clock-cells = <0x2>; }; }; ipu2_cm@900 { compatible = \"ti,omap4-cm\"; reg = <0x900 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x900 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x4>; #clock-cells = <0x2>; }; }; dma_cm@a00 { compatible = \"ti,omap4-cm\"; reg = <0xa00 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0xa00 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x4>; #clock-cells = <0x2>; }; }; emif_cm@b00 { compatible = \"ti,omap4-cm\"; reg = <0xb00 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0xb00 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x4>; #clock-cells = <0x2>; }; }; atl_cm@c00 { compatible = \"ti,omap4-cm\"; reg = <0xc00 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0xc00 0x100>; clk@0 { compatible = \"ti,clkctrl\"; reg = <0x0 0x4>; #clock-cells = <0x2>; phandle = <0x10>; }; }; l4cfg_cm@d00 { compatible = \"ti,omap4-cm\"; reg = <0xd00 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0xd00 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x84>; #clock-cells = <0x2>; }; }; l3instr_cm@e00 { compatible = \"ti,omap4-cm\"; reg = <0xe00 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0xe00 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0xc>; #clock-cells = <0x2>; }; }; dss_cm@1100 { compatible = \"ti,omap4-cm\"; reg = <0x1100 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x1100 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x14>; #clock-cells = <0x2>; phandle = <0xec>; }; }; l3init_cm@1300 { compatible = \"ti,omap4-cm\"; reg = <0x1300 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x1300 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0xd4>; #clock-cells = <0x2>; phandle = <0xd2>; }; }; l4per_cm@1700 { compatible = \"ti,omap4-cm\"; reg = <0x1700 0x300>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x1700 0x300>; clk@0 { compatible = \"ti,clkctrl\"; reg = <0x0 0x20c>; #clock-cells = <0x2>; assigned-clocks = <0x57 0x168 0x18>; assigned-clock-parents = <0x58>; phandle = <0x57>; }; }; }; }; l4@4ae00000 { compatible = \"ti,dra7-l4-wkup\", \"simple-bus\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x4ae00000 0x3f000>; counter@4000 { compatible = \"ti,omap-counter32k\"; reg = <0x4000 0x40>; ti,hwmods = \"counter_32k\"; }; prm@6000 { compatible = \"ti,dra7-prm\", \"simple-bus\"; reg = <0x6000 0x3000>; interrupts = <0x0 0x6 0x4>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x6000 0x3000>; clocks { #address-cells = <0x1>; #size-cells = <0x0>; sys_clkin1@110 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; reg = <0x110>; ti,index-starts-at-one; phandle = <0x11>; }; abe_dpll_sys_clk_mux@118 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x60>; reg = <0x118>; phandle = <0x61>; }; abe_dpll_bypass_clk_mux@114 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x61 0x50>; reg = <0x114>; phandle = <0x13>; }; abe_dpll_clk_mux@10c { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x61 0x50>; reg = <0x10c>; phandle = <0x12>; }; abe_24m_fclk@11c { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x16>; reg = <0x11c>; ti,dividers = <0x8 0x10>; phandle = <0x58>; }; aess_fclk@178 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x62>; reg = <0x178>; ti,max-div = <0x2>; phandle = <0x63>; }; abe_giclk_div@174 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x63>; reg = <0x174>; ti,max-div = <0x2>; }; abe_lp_clk_div@1d8 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x16>; reg = <0x1d8>; ti,dividers = <0x10 0x20>; phandle = <0x83>; }; abe_sys_clk_div@120 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x11>; reg = <0x120>; ti,max-div = <0x2>; }; adc_gfclk_mux@1dc { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x60 0x50>; reg = <0x1dc>; }; sys_clk1_dclk_div@1c8 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x11>; ti,max-div = <0x40>; reg = <0x1c8>; ti,index-power-of-two; phandle = <0x6c>; }; sys_clk2_dclk_div@1cc { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x60>; ti,max-div = <0x40>; reg = <0x1cc>; ti,index-power-of-two; phandle = <0x6d>; }; per_abe_x1_dclk_div@1bc { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x64>; ti,max-div = <0x40>; reg = <0x1bc>; ti,index-power-of-two; phandle = <0x6e>; }; dsp_gclk_div@18c { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x21>; ti,max-div = <0x40>; reg = <0x18c>; ti,index-power-of-two; phandle = <0x70>; }; gpu_dclk@1a0 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x28>; ti,max-div = <0x40>; reg = <0x1a0>; ti,index-power-of-two; phandle = <0x72>; }; emif_phy_dclk_div@190 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x65>; ti,max-div = <0x40>; reg = <0x190>; ti,index-power-of-two; phandle = <0x74>; }; gmac_250m_dclk_div@19c { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x66>; ti,max-div = <0x40>; reg = <0x19c>; ti,index-power-of-two; phandle = <0x67>; }; gmac_main_clk { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x67>; clock-mult = <0x1>; clock-div = <0x2>; phandle = <0xe7>; }; l3init_480m_dclk_div@1ac { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x4d>; ti,max-div = <0x40>; reg = <0x1ac>; ti,index-power-of-two; phandle = <0x79>; }; usb_otg_dclk_div@184 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x68>; ti,max-div = <0x40>; reg = <0x184>; ti,index-power-of-two; phandle = <0x7a>; }; sata_dclk_div@1c0 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x11>; ti,max-div = <0x40>; reg = <0x1c0>; ti,index-power-of-two; phandle = <0x7b>; }; pcie2_dclk_div@1b8 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x69>; ti,max-div = <0x40>; reg = <0x1b8>; ti,index-power-of-two; phandle = <0x7c>; }; pcie_dclk_div@1b4 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x6a>; ti,max-div = <0x40>; reg = <0x1b4>; ti,index-power-of-two; phandle = <0x7d>; }; emu_dclk_div@194 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x11>; ti,max-div = <0x40>; reg = <0x194>; ti,index-power-of-two; phandle = <0x7e>; }; secure_32k_dclk_div@1c4 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x6b>; ti,max-div = <0x40>; reg = <0x1c4>; ti,index-power-of-two; phandle = <0x7f>; }; clkoutmux0_clk_mux@158 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>; reg = <0x158>; }; clkoutmux1_clk_mux@15c { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>; reg = <0x15c>; }; clkoutmux2_clk_mux@160 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x67 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80>; reg = <0x160>; phandle = <0x4e>; }; custefuse_sys_gfclk_div { #clock-cells = <0x0>; compatible = \"fixed-factor-clock\"; clocks = <0x11>; clock-mult = <0x1>; clock-div = <0x2>; }; eve_clk@180 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x34 0x37>; reg = <0x180>; }; hdmi_dpll_clk_mux@164 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x60>; reg = <0x164>; }; mlb_clk@134 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x81>; ti,max-div = <0x40>; reg = <0x134>; ti,index-power-of-two; }; mlbp_clk@130 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x82>; ti,max-div = <0x40>; reg = <0x130>; ti,index-power-of-two; }; per_abe_x1_gfclk2_div@138 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x64>; ti,max-div = <0x40>; reg = <0x138>; ti,index-power-of-two; }; timer_sys_clk_div@144 { #clock-cells = <0x0>; compatible = \"ti,divider-clock\"; clocks = <0x11>; reg = <0x144>; ti,max-div = <0x2>; }; video1_dpll_clk_mux@168 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x60>; reg = <0x168>; }; video2_dpll_clk_mux@16c { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x60>; reg = <0x16c>; }; wkupaon_iclk_mux@108 { #clock-cells = <0x0>; compatible = \"ti,mux-clock\"; clocks = <0x11 0x83>; reg = <0x108>; phandle = <0x55>; }; }; clockdomains { }; wkupaon_cm@1800 { compatible = \"ti,omap4-cm\"; reg = <0x1800 0x100>; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x1800 0x100>; clk@20 { compatible = \"ti,clkctrl\"; reg = <0x20 0x6c>; #clock-cells = <0x2>; phandle = <0x8e>; }; }; }; scm_conf@c000 { compatible = \"syscon\"; reg = <0xc000 0x1000>; phandle = <0x7>; }; }; axi@0 { compatible = \"simple-bus\"; #size-cells = <0x1>; #address-cells = <0x1>; ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>; pcie@51000000 { reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>; reg-names = \"rc_dbics\", \"ti_conf\", \"config\"; interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>; #address-cells = <0x3>; #size-cells = <0x2>; device_type = \"pci\"; ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>; bus-range = <0x0 0xff>; #interrupt-cells = <0x1>; num-lanes = <0x1>; linux,pci-domain = <0x0>; ti,hwmods = \"pcie1\"; phys = <0x84>; phy-names = \"pcie-phy0\"; ti,syscon-lane-sel = <0x85 0x18>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 0x86 0x1 0x0 0x0 0x0 0x2 0x86 0x2 0x0 0x0 0x0 0x3 0x86 0x3 0x0 0x0 0x0 0x4 0x86 0x4>; status = \"okay\"; compatible = \"ti,dra746-pcie-rc\", \"ti,dra7-pcie\"; interrupt-controller { interrupt-controller; #address-cells = <0x0>; #interrupt-cells = <0x1>; phandle = <0x86>; }; }; pcie_ep@51000000 { reg = <0x51000000 0x28 0x51002000 0x14c 0x51001000 0x28 0x1000 0x10000000>; reg-names = \"ep_dbics\", \"ti_conf\", \"ep_dbics2\", \"addr_space\"; interrupts = <0x0 0xe8 0x4>; num-lanes = <0x1>; num-ib-windows = <0x4>; num-ob-windows = <0x10>; ti,hwmods = \"pcie1\"; phys = <0x84>; phy-names = \"pcie-phy0\"; ti,syscon-unaligned-access = <0x87 0x14 0x1>; ti,syscon-lane-sel = <0x85 0x18>; status = \"disabled\"; compatible = \"ti,dra746-pcie-ep\", \"ti,dra7-pcie-ep\"; }; }; axi@1 { compatible = \"simple-bus\"; #size-cells = <0x1>; #address-cells = <0x1>; ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>; status = \"disabled\"; pcie@51800000 { reg = <0x51800000 0x2000 0x51802000 0x14c 0x1000 0x2000>; reg-names = \"rc_dbics\", \"ti_conf\", \"config\"; interrupts = <0x0 0x163 0x4 0x0 0x164 0x4>; #address-cells = <0x3>; #size-cells = <0x2>; device_type = \"pci\"; ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x30013000 0x13000 0x0 0xffed000>; bus-range = <0x0 0xff>; #interrupt-cells = <0x1>; num-lanes = <0x1>; linux,pci-domain = <0x1>; ti,hwmods = \"pcie2\"; phys = <0x88>; phy-names = \"pcie-phy0\"; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 0x89 0x1 0x0 0x0 0x0 0x2 0x89 0x2 0x0 0x0 0x0 0x3 0x89 0x3 0x0 0x0 0x0 0x4 0x89 0x4>; compatible = \"ti,dra746-pcie-rc\", \"ti,dra7-pcie\"; interrupt-controller { interrupt-controller; #address-cells = <0x0>; #interrupt-cells = <0x1>; phandle = <0x89>; }; }; }; ocmcram@40300000 { compatible = \"mmio-sram\"; reg = <0x40300000 0x80000>; ranges = <0x0 0x40300000 0x80000>; #address-cells = <0x1>; #size-cells = <0x1>; status = \"disabled\"; ti,no-idle; ti,no-reset-on-init; phandle = <0x103>; sram-hs@0 { compatible = \"ti,secure-ram\"; reg = <0x0 0x0>; }; }; ocmcram@40400000 { status = \"disabled\"; compatible = \"mmio-sram\"; reg = <0x40400000 0x100000>; ranges = <0x0 0x40400000 0x100000>; #address-cells = <0x1>; #size-cells = <0x1>; }; ocmcram@40500000 { status = \"disabled\"; compatible = \"mmio-sram\"; reg = <0x40500000 0x100000>; ranges = <0x0 0x40500000 0x100000>; #address-cells = <0x1>; #size-cells = <0x1>; }; bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x8 0x4a002574 0x50>; compatible = \"ti,dra752-bandgap\"; interrupts = <0x0 0x79 0x4>; #thermal-sensor-cells = <0x1>; phandle = <0xfa>; }; dsp_system@40d00000 { compatible = \"syscon\"; reg = <0x40d00000 0x100>; phandle = <0xce>; }; padconf@4844a000 { compatible = \"ti,dra7-iodelay\"; reg = <0x4844a000 0xd1c>; #address-cells = <0x1>; #size-cells = <0x0>; #pinctrl-cells = <0x2>; mmc1_iodelay_ddr_rev11_conf { pinctrl-pin-array = <0x618 0x23c 0x21c 0x620 0x5f5 0x0 0x624 0x0 0x258 0x628 0x0 0x0 0x62c 0x37 0x0 0x630 0x193 0x78 0x634 0x0 0x0 0x638 0x0 0x0 0x63c 0x17 0x3c 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x19 0x3c 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>; phandle = <0xb6>; }; mmc1_iodelay_ddr50_rev20_conf { pinctrl-pin-array = <0x618 0x434 0x14a 0x620 0x4f7 0x0 0x624 0x2d2 0x0 0x628 0x0 0x0 0x62c 0x0 0x0 0x630 0x2ef 0x0 0x634 0x0 0x0 0x638 0x14 0x0 0x63c 0x100 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x107 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>; phandle = <0xb9>; }; mmc1_iodelay_sdr104_rev11_conf { pinctrl-pin-array = <0x620 0x427 0x11 0x628 0x0 0x0 0x62c 0x17 0x0 0x634 0x0 0x0 0x638 0x0 0x0 0x640 0x0 0x0 0x644 0x2 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>; phandle = <0xb8>; }; mmc1_iodelay_sdr104_rev20_conf { pinctrl-pin-array = <0x620 0x258 0x190 0x628 0x0 0x0 0x62c 0x0 0x0 0x634 0x0 0x0 0x638 0x1e 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>; phandle = <0xba>; }; mmc2_iodelay_hs200_rev11_conf { pinctrl-pin-array = <0x190 0x26d 0x258 0x194 0x12c 0x0 0x1a8 0x2e3 0x258 0x1ac 0xf0 0x0 0x1b4 0x32c 0x258 0x1b8 0xf0 0x0 0x1c0 0x3ba 0x258 0x1c4 0x3c 0x0 0x1d0 0x53c 0x1a4 0x1d8 0x3a7 0x258 0x1dc 0x0 0x0 0x1e4 0x20d 0x258 0x1e8 0x78 0x0 0x1f0 0x2ff 0x258 0x1f4 0xe1 0x0 0x1fc 0x235 0x258 0x200 0x3c 0x0 0x364 0x3c9 0x258 0x368 0xb4 0x0>; phandle = <0xc2>; }; mmc2_iodelay_hs200_rev20_conf { pinctrl-pin-array = <0x190 0x112 0x0 0x194 0xa2 0x0 0x1a8 0x191 0x0 0x1ac 0x49 0x0 0x1b4 0x1d1 0x0 0x1b8 0x73 0x0 0x1c0 0x279 0x0 0x1c4 0x2f 0x0 0x1d0 0x3a7 0x118 0x1d8 0x26d 0x0 0x1dc 0x0 0x0 0x1e4 0xb7 0x0 0x1e8 0x0 0x0 0x1f0 0x1d3 0x0 0x1f4 0x0 0x0 0x1fc 0x106 0x0 0x200 0x2e 0x0 0x364 0x2ac 0x0 0x368 0x4c 0x0>; phandle = <0xc3>; }; mmc2_iodelay_ddr_3_3v_rev11_conf { pinctrl-pin-array = <0x18c 0x0 0x78 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x109 0x168 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x78 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x78 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x11f 0x1a4 0x1d0 0x36f 0x0 0x1d4 0x90 0xf0 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x78 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x78 0xb4 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>; }; mmc2_iodelay_ddr_1_8v_rev11_conf { pinctrl-pin-array = <0x18c 0x0 0x0 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x112 0xf0 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x3c 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x3c 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x202 0x168 0x1d0 0x36f 0x0 0x1d4 0xbb 0x78 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x3c 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x79 0x3c 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>; phandle = <0xbf>; }; mmc3_iodelay_manual1_conf { pinctrl-pin-array = <0x678 0x196 0x0 0x680 0x293 0x0 0x684 0x0 0x0 0x688 0x0 0x0 0x68c 0x0 0x0 0x690 0x82 0x0 0x694 0x0 0x0 0x698 0x0 0x0 0x69c 0xa9 0x0 0x6a0 0x0 0x0 0x6a4 0x0 0x0 0x6a8 0x0 0x0 0x6ac 0x0 0x0 0x6b0 0x0 0x0 0x6b4 0x1c9 0x0 0x6b8 0x0 0x0 0x6bc 0x0 0x0>; }; mmc4_iodelay_ds_rev11_conf { pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x60 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x246 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x187 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x231 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x24c 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>; phandle = <0xc7>; }; mmc4_iodelay_ds_rev20_conf { pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x133 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x311 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x265 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x2ab 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x343 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>; phandle = <0xc8>; }; mmc4_iodelay_sdr12_hs_sdr25_rev11_conf { pinctrl-pin-array = <0x840 0x0 0x0 0x848 0xa5b 0x0 0x84c 0x624 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x779 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x6b9 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x763 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x77f 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>; phandle = <0xca>; }; mmc4_iodelay_sdr12_hs_sdr25_rev20_conf { pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x47b 0x0 0x84c 0x72a 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x875 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x789 0x40 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x78f 0x80 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x87c 0x2c 0x898 0x0 0x0 0x89c 0x0 0x0>; phandle = <0xcb>; }; }; dma-controller@4a056000 { compatible = \"ti,omap4430-sdma\"; reg = <0x4a056000 0x1000>; interrupts = <0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4>; #dma-cells = <0x1>; dma-channels = <0x20>; dma-requests = <0x7f>; ti,hwmods = \"dma_system\"; phandle = <0xe>; }; edma@43300000 { compatible = \"ti,edma3-tpcc\"; ti,hwmods = \"tpcc\"; reg = <0x43300000 0x100000>; reg-names = \"edma3_cc\"; interrupts = <0x0 0x169 0x4 0x0 0x168 0x4 0x0 0x167 0x4>; interrupt-names = \"edma3_ccint\", \"edma3_mperr\", \"edma3_ccerrint\"; dma-requests = <0x20>; #dma-cells = <0x2>; ti,tptcs = <0x8a 0x7 0x8b 0x0>; phandle = <0xf>; }; tptc@43400000 { compatible = \"ti,edma3-tptc\"; ti,hwmods = \"tptc0\"; reg = <0x43400000 0x100000>; interrupts = <0x0 0x172 0x4>; interrupt-names = \"edma3_tcerrint\"; phandle = <0x8a>; }; tptc@43500000 { compatible = \"ti,edma3-tptc\"; ti,hwmods = \"tptc1\"; reg = <0x43500000 0x100000>; interrupts = <0x0 0x173 0x4>; interrupt-names = \"edma3_tcerrint\"; phandle = <0x8b>; }; gpio@4ae10000 { compatible = \"ti,omap4-gpio\"; reg = <0x4ae10000 0x200>; interrupts = <0x0 0x18 0x4>; ti,hwmods = \"gpio1\"; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; ti,no-idle; ti,no-reset-on-init; }; gpio@48055000 { compatible = \"ti,omap4-gpio\"; reg = <0x48055000 0x200>; interrupts = <0x0 0x19 0x4>; ti,hwmods = \"gpio2\"; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; ti,no-idle; ti,no-reset-on-init; }; gpio@48057000 { compatible = \"ti,omap4-gpio\"; reg = <0x48057000 0x200>; interrupts = <0x0 0x1a 0x4>; ti,hwmods = \"gpio3\"; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; ti,no-reset-on-init; ti,no-idle-on-init; phandle = <0xa0>; }; gpio@48059000 { compatible = \"ti,omap4-gpio\"; reg = <0x48059000 0x200>; interrupts = <0x0 0x1b 0x4>; ti,hwmods = \"gpio4\"; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; ti,no-idle; ti,no-reset-on-init; }; gpio@4805b000 { compatible = \"ti,omap4-gpio\"; reg = <0x4805b000 0x200>; interrupts = <0x0 0x1c 0x4>; ti,hwmods = \"gpio5\"; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; ti,no-reset-on-init; ti,no-idle-on-init; phandle = <0xa5>; }; gpio@4805d000 { compatible = \"ti,omap4-gpio\"; reg = <0x4805d000 0x200>; interrupts = <0x0 0x1d 0x4>; ti,hwmods = \"gpio6\"; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; ti,no-reset-on-init; ti,no-idle-on-init; ti,no-idle; phandle = <0xa7>; }; gpio@48051000 { compatible = \"ti,omap4-gpio\"; reg = <0x48051000 0x200>; interrupts = <0x0 0x1e 0x4>; ti,hwmods = \"gpio7\"; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; ti,no-reset-on-init; ti,no-idle-on-init; phandle = <0x108>; }; gpio@48053000 { compatible = \"ti,omap4-gpio\"; reg = <0x48053000 0x200>; interrupts = <0x0 0x74 0x4>; ti,hwmods = \"gpio8\"; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; #interrupt-cells = <0x2>; ti,no-reset-on-init; ti,no-idle-on-init; phandle = <0x9f>; }; serial@4806a000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x4806a000 0x100>; interrupts-extended = <0x1 0x0 0x43 0x4 0x8c 0x3e0>; ti,hwmods = \"uart1\"; clock-frequency = <0x2dc6c00>; status = \"okay\"; dmas = <0x8d 0x31 0x8d 0x32>; dma-names = \"tx\", \"rx\"; }; serial@4806c000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x4806c000 0x100>; interrupts-extended = <0x1 0x0 0x44 0x4 0x8c 0x3e0>; ti,hwmods = \"uart2\"; clock-frequency = <0x2dc6c00>; status = \"okay\"; dmas = <0x8d 0x33 0x8d 0x34>; dma-names = \"tx\", \"rx\"; }; serial@48020000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x48020000 0x100>; interrupts = <0x0 0x45 0x4>; ti,hwmods = \"uart3\"; clock-frequency = <0x2dc6c00>; status = \"okay\"; dmas = <0x8d 0x35 0x8d 0x36>; dma-names = \"tx\", \"rx\"; }; serial@4806e000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x4806e000 0x100>; interrupts = <0x0 0x41 0x4>; ti,hwmods = \"uart4\"; clock-frequency = <0x2dc6c00>; status = \"disabled\"; dmas = <0x8d 0x37 0x8d 0x38>; dma-names = \"tx\", \"rx\"; }; serial@48066000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x48066000 0x100>; interrupts = <0x0 0x64 0x4>; ti,hwmods = \"uart5\"; clock-frequency = <0x2dc6c00>; status = \"disabled\"; dmas = <0x8d 0x3f 0x8d 0x40>; dma-names = \"tx\", \"rx\"; }; serial@48068000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x48068000 0x100>; interrupts = <0x0 0x65 0x4>; ti,hwmods = \"uart6\"; clock-frequency = <0x2dc6c00>; status = \"disabled\"; dmas = <0x8d 0x4f 0x8d 0x50>; dma-names = \"tx\", \"rx\"; }; serial@48420000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x48420000 0x100>; interrupts = <0x0 0xda 0x4>; ti,hwmods = \"uart7\"; clock-frequency = <0x2dc6c00>; status = \"disabled\"; }; serial@48422000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x48422000 0x100>; interrupts = <0x0 0xdb 0x4>; ti,hwmods = \"uart8\"; clock-frequency = <0x2dc6c00>; status = \"disabled\"; }; serial@48424000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x48424000 0x100>; interrupts = <0x0 0xdc 0x4>; ti,hwmods = \"uart9\"; clock-frequency = <0x2dc6c00>; status = \"disabled\"; }; serial@4ae2b000 { compatible = \"ti,dra742-uart\", \"ti,omap4-uart\"; reg = <0x4ae2b000 0x100>; interrupts = <0x0 0xdd 0x4>; ti,hwmods = \"uart10\"; clock-frequency = <0x2dc6c00>; status = \"disabled\"; }; mailbox@4a0f4000 { compatible = \"ti,omap4-mailbox\"; reg = <0x4a0f4000 0x200>; interrupts = <0x0 0x15 0x4 0x0 0x87 0x4 0x0 0x86 0x4>; ti,hwmods = \"mailbox1\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x3>; ti,mbox-num-fifos = <0x8>; status = \"disabled\"; }; mailbox@4883a000 { compatible = \"ti,omap4-mailbox\"; reg = <0x4883a000 0x200>; interrupts = <0x0 0xed 0x4 0x0 0xee 0x4 0x0 0xef 0x4 0x0 0xf0 0x4>; ti,hwmods = \"mailbox2\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@4883c000 { compatible = \"ti,omap4-mailbox\"; reg = <0x4883c000 0x200>; interrupts = <0x0 0xf1 0x4 0x0 0xf2 0x4 0x0 0xf3 0x4 0x0 0xf4 0x4>; ti,hwmods = \"mailbox3\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@4883e000 { compatible = \"ti,omap4-mailbox\"; reg = <0x4883e000 0x200>; interrupts = <0x0 0xf5 0x4 0x0 0xf6 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4>; ti,hwmods = \"mailbox4\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@48840000 { compatible = \"ti,omap4-mailbox\"; reg = <0x48840000 0x200>; interrupts = <0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4>; ti,hwmods = \"mailbox5\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"okay\"; phandle = <0x91>; mbox_ipu1_ipc3x { ti,mbox-tx = <0x6 0x2 0x2>; ti,mbox-rx = <0x4 0x2 0x2>; status = \"okay\"; phandle = <0x92>; }; mbox_dsp1_ipc3x { ti,mbox-tx = <0x5 0x2 0x2>; ti,mbox-rx = <0x1 0x2 0x2>; status = \"okay\"; phandle = <0x9c>; }; }; mailbox@48842000 { compatible = \"ti,omap4-mailbox\"; reg = <0x48842000 0x200>; interrupts = <0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4>; ti,hwmods = \"mailbox6\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"okay\"; phandle = <0x96>; mbox_ipu2_ipc3x { ti,mbox-tx = <0x6 0x2 0x2>; ti,mbox-rx = <0x4 0x2 0x2>; status = \"okay\"; phandle = <0x97>; }; mbox_dsp2_ipc3x { ti,mbox-tx = <0x5 0x2 0x2>; ti,mbox-rx = <0x1 0x2 0x2>; status = \"okay\"; phandle = <0xf7>; }; }; mailbox@48844000 { compatible = \"ti,omap4-mailbox\"; reg = <0x48844000 0x200>; interrupts = <0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4>; ti,hwmods = \"mailbox7\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@48846000 { compatible = \"ti,omap4-mailbox\"; reg = <0x48846000 0x200>; interrupts = <0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4>; ti,hwmods = \"mailbox8\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@4885e000 { compatible = \"ti,omap4-mailbox\"; reg = <0x4885e000 0x200>; interrupts = <0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4>; ti,hwmods = \"mailbox9\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@48860000 { compatible = \"ti,omap4-mailbox\"; reg = <0x48860000 0x200>; interrupts = <0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4 0x0 0x110 0x4>; ti,hwmods = \"mailbox10\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@48862000 { compatible = \"ti,omap4-mailbox\"; reg = <0x48862000 0x200>; interrupts = <0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>; ti,hwmods = \"mailbox11\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@48864000 { compatible = \"ti,omap4-mailbox\"; reg = <0x48864000 0x200>; interrupts = <0x0 0x115 0x4 0x0 0x116 0x4 0x0 0x117 0x4 0x0 0x118 0x4>; ti,hwmods = \"mailbox12\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; mailbox@48802000 { compatible = \"ti,omap4-mailbox\"; reg = <0x48802000 0x200>; interrupts = <0x0 0x17b 0x4 0x0 0x17c 0x4 0x0 0x17d 0x4 0x0 0x17e 0x4>; ti,hwmods = \"mailbox13\"; #mbox-cells = <0x1>; ti,mbox-num-users = <0x4>; ti,mbox-num-fifos = <0xc>; status = \"disabled\"; }; timer@4ae18000 { compatible = \"ti,omap5430-timer\"; reg = <0x4ae18000 0x80>; interrupts = <0x0 0x20 0x4>; ti,hwmods = \"timer1\"; ti,timer-alwon; clock-names = \"fck\"; clocks = <0x8e 0x20 0x18>; }; timer@48032000 { compatible = \"ti,omap5430-timer\"; reg = <0x48032000 0x80>; interrupts = <0x0 0x21 0x4>; ti,hwmods = \"timer2\"; clocks = <0x57 0x38 0x18>; clock-names = \"fck\"; }; timer@48034000 { compatible = \"ti,omap5430-timer\"; reg = <0x48034000 0x80>; interrupts = <0x0 0x22 0x4>; ti,hwmods = \"timer3\"; clocks = <0x57 0x40 0x18>; clock-names = \"fck\"; }; timer@48036000 { compatible = \"ti,omap5430-timer\"; reg = <0x48036000 0x80>; interrupts = <0x0 0x23 0x4>; ti,hwmods = \"timer4\"; clocks = <0x57 0x48 0x18>; clock-names = \"fck\"; }; timer@48820000 { compatible = \"ti,omap5430-timer\"; reg = <0x48820000 0x80>; interrupts = <0x0 0x24 0x4>; ti,hwmods = \"timer5\"; clocks = <0x8f 0x18 0x18>; clock-names = \"fck\"; phandle = <0x9d>; }; timer@48822000 { compatible = \"ti,omap5430-timer\"; reg = <0x48822000 0x80>; interrupts = <0x0 0x25 0x4>; ti,hwmods = \"timer6\"; clocks = <0x8f 0x20 0x18>; clock-names = \"fck\"; phandle = <0xf8>; }; timer@48824000 { compatible = \"ti,omap5430-timer\"; reg = <0x48824000 0x80>; interrupts = <0x0 0x26 0x4>; ti,hwmods = \"timer7\"; clocks = <0x8f 0x28 0x18>; clock-names = \"fck\"; }; timer@48826000 { compatible = \"ti,omap5430-timer\"; reg = <0x48826000 0x80>; interrupts = <0x0 0x27 0x4>; ti,hwmods = \"timer8\"; clocks = <0x8f 0x30 0x18>; clock-names = \"fck\"; }; timer@4803e000 { compatible = \"ti,omap5430-timer\"; reg = <0x4803e000 0x80>; interrupts = <0x0 0x28 0x4>; ti,hwmods = \"timer9\"; clocks = <0x57 0x50 0x18>; clock-names = \"fck\"; phandle = <0x98>; }; timer@48086000 { compatible = \"ti,omap5430-timer\"; reg = <0x48086000 0x80>; interrupts = <0x0 0x29 0x4>; ti,hwmods = \"timer10\"; clocks = <0x57 0x28 0x18>; clock-names = \"fck\"; }; timer@48088000 { compatible = \"ti,omap5430-timer\"; reg = <0x48088000 0x80>; interrupts = <0x0 0x2a 0x4>; ti,hwmods = \"timer11\"; clocks = <0x57 0x30 0x18>; clock-names = \"fck\"; phandle = <0x93>; }; timer@4ae20000 { compatible = \"ti,omap5430-timer\"; reg = <0x4ae20000 0x80>; interrupts = <0x0 0x5a 0x4>; ti,hwmods = \"timer12\"; ti,timer-alwon; ti,timer-secure; clocks = <0x8e 0x28 0x18>; clock-names = \"fck\"; }; timer@48828000 { compatible = \"ti,omap5430-timer\"; reg = <0x48828000 0x80>; interrupts = <0x0 0x153 0x4>; ti,hwmods = \"timer13\"; clocks = <0x57 0xc8 0x18>; clock-names = \"fck\"; }; timer@4882a000 { compatible = \"ti,omap5430-timer\"; reg = <0x4882a000 0x80>; interrupts = <0x0 0x154 0x4>; ti,hwmods = \"timer14\"; clocks = <0x57 0xd0 0x18>; clock-names = \"fck\"; }; timer@4882c000 { compatible = \"ti,omap5430-timer\"; reg = <0x4882c000 0x80>; interrupts = <0x0 0x155 0x4>; ti,hwmods = \"timer15\"; clocks = <0x57 0xd8 0x18>; clock-names = \"fck\"; }; timer@4882e000 { compatible = \"ti,omap5430-timer\"; reg = <0x4882e000 0x80>; interrupts = <0x0 0x156 0x4>; ti,hwmods = \"timer16\"; clocks = <0x57 0x130 0x18>; clock-names = \"fck\"; }; wdt@4ae14000 { compatible = \"ti,omap3-wdt\"; reg = <0x4ae14000 0x80>; interrupts = <0x0 0x4b 0x4>; ti,hwmods = \"wd_timer2\"; status = \"disabled\"; ti,no-idle; ti,no-reset-on-init; }; spinlock@4a0f6000 { compatible = \"ti,omap4-hwspinlock\"; reg = <0x4a0f6000 0x1000>; ti,hwmods = \"spinlock\"; #hwlock-cells = <0x1>; }; dmm@4e000000 { compatible = \"ti,omap5-dmm\"; reg = <0x4e000000 0x800>; interrupts = <0x0 0x6c 0x4>; ti,hwmods = \"dmm\"; }; ipu@58820000 { compatible = \"ti,dra7-ipu\"; reg = <0x58820000 0x10000>; reg-names = \"l2ram\"; ti,hwmods = \"ipu1\"; iommus = <0x90>; ti,rproc-standby-info = <0x4a005520>; status = \"okay\"; mboxes = <0x91 0x92>; timers = <0x93>; memory-region = <0x94>; }; ipu@55020000 { compatible = \"ti,dra7-ipu\"; reg = <0x55020000 0x10000>; reg-names = \"l2ram\"; ti,hwmods = \"ipu2\"; iommus = <0x95>; ti,rproc-standby-info = <0x4a008920>; status = \"okay\"; mboxes = <0x96 0x97>; timers = <0x98 0x93>; memory-region = <0x99>; }; dsp@40800000 { compatible = \"ti,dra7-dsp\"; reg = <0x40800000 0x48000 0x40e00000 0x8000 0x40f00000 0x8000>; reg-names = \"l2ram\", \"l1pram\", \"l1dram\"; ti,hwmods = \"dsp1\"; syscon-bootreg = <0x9 0x55c>; iommus = <0x9a 0x9b>; ti,rproc-standby-info = <0x4a005420>; status = \"okay\"; mboxes = <0x91 0x9c>; timers = <0x9d>; memory-region = <0x9e>; }; i2c@48070000 { compatible = \"ti,omap4-i2c\"; reg = <0x48070000 0x100>; interrupts = <0x0 0x33 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"i2c1\"; status = \"okay\"; clock-frequency = <0x61a80>; tps659038@58 { compatible = \"ti,tps659038\"; reg = <0x58>; ti,palmas-override-powerhold; ti,system-power-controller; tps659038_pmic { compatible = \"ti,tps659038-pmic\"; regulators { smps123 { regulator-name = \"smps123\"; regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x1312d0>; regulator-always-on; regulator-boot-on; phandle = <0x6>; }; smps45 { regulator-name = \"smps45\"; regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x1312d0>; regulator-always-on; regulator-boot-on; }; smps6 { regulator-name = \"smps6\"; regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x1312d0>; regulator-always-on; regulator-boot-on; }; smps7 { regulator-name = \"smps7\"; regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x118c30>; regulator-always-on; regulator-boot-on; }; smps8 { regulator-name = \"smps8\"; regulator-min-microvolt = <0xcf850>; regulator-max-microvolt = <0x1312d0>; regulator-always-on; regulator-boot-on; }; smps9 { regulator-name = \"smps9\"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-always-on; regulator-boot-on; phandle = <0x102>; }; ldo1 { regulator-name = \"ldo1\"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; phandle = <0xaf>; }; ldo2 { regulator-name = \"ldo2\"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-always-on; regulator-boot-on; }; ldo3 { regulator-name = \"ldo3\"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-always-on; regulator-boot-on; phandle = <0xee>; }; ldo9 { regulator-name = \"ldo9\"; regulator-min-microvolt = <0x100590>; regulator-max-microvolt = <0x100590>; regulator-always-on; regulator-boot-on; regulator-allow-bypass; }; ldoln { regulator-name = \"ldoln\"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; regulator-always-on; regulator-boot-on; phandle = <0xed>; }; ldousb { regulator-name = \"ldousb\"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; regulator-boot-on; phandle = <0xd6>; }; regen2 { regulator-name = \"regen2\"; regulator-boot-on; regulator-always-on; }; sysen1 { regulator-name = \"sysen1\"; regulator-boot-on; regulator-always-on; phandle = <0x104>; }; sysen2 { regulator-name = \"sysen2\"; regulator-boot-on; regulator-always-on; phandle = <0x107>; }; }; }; }; serdes@40 { compatible = \"max96705-serdes\"; reg = <0x40>; phandle = <0xa1>; }; serdes@49 { compatible = \"max96705-serdes\"; reg = <0x49>; phandle = <0xa2>; }; serdes@4b { compatible = \"max96705-serdes\"; reg = <0x4b>; phandle = <0xa3>; }; serdes@4d { compatible = \"max96705-serdes\"; reg = <0x4d>; phandle = <0xa4>; }; serdes@4f { compatible = \"max96705-serdes\"; reg = <0x4f>; phandle = <0xa6>; }; serdes@48 { compatible = \"max96706-serdes\"; reg = <0x48>; all-des-power-gpio = <0x9f 0xe 0x0>; all-des-power-good-gpio = <0x9f 0xf 0x0>; des-power-gpio = <0xa0 0x13 0x0>; all-ser-power-gpio = <0x9f 0xc 0x0>; all-ser-power-good-gpio = <0x9f 0xd 0x0>; serializer_adapter_default = <0xa1>; serializer_adapter_link = <0xa2>; }; serdes@4a { compatible = \"max96706-serdes\"; reg = <0x4a>; all-des-power-gpio = <0x9f 0xe 0x0>; all-des-power-good-gpio = <0x9f 0xf 0x0>; des-power-gpio = <0xa0 0x19 0x0>; all-ser-power-gpio = <0x9f 0xc 0x0>; all-ser-power-good-gpio = <0x9f 0xd 0x0>; serializer_adapter_default = <0xa1>; serializer_adapter_link = <0xa3>; }; serdes@4c { compatible = \"max96706-serdes\"; reg = <0x4c>; all-des-power-gpio = <0x9f 0xe 0x0>; all-des-power-good-gpio = <0x9f 0xf 0x0>; des-power-gpio = <0x9f 0x3 0x0>; all-ser-power-gpio = <0x9f 0xc 0x0>; all-ser-power-good-gpio = <0x9f 0xd 0x0>; serializer_adapter_default = <0xa1>; serializer_adapter_link = <0xa4>; }; serdes@4e { compatible = \"max96706-serdes\"; reg = <0x4e>; all-des-power-gpio = <0x9f 0xe 0x0>; all-des-power-good-gpio = <0x9f 0xf 0x0>; des-power-gpio = <0xa5 0xd 0x0>; all-ser-power-gpio = <0x9f 0xc 0x0>; all-ser-power-good-gpio = <0x9f 0xd 0x0>; serializer_adapter_default = <0xa1>; serializer_adapter_link = <0xa6>; }; gpio@20 { compatible = \"ti,pcf8575\", \"nxp,pcf8575\"; reg = <0x20>; gpio-controller; #gpio-cells = <0x2>; interrupt-parent = <0xa7>; interrupts = <0xb 0x2>; interrupt-controller; #interrupt-cells = <0x2>; phandle = <0x101>; }; gpio@21 { compatible = \"ti,pcf8575\", \"nxp,pcf8575\"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; #gpio-cells = <0x2>; interrupt-parent = <0xa7>; interrupts = <0xb 0x2>; interrupt-controller; #interrupt-cells = <0x2>; phandle = <0xfd>; }; tlv320aic3106@19 { #sound-dai-cells = <0x0>; compatible = \"ti,tlv320aic3106\"; reg = <0x19>; adc-settle-ms = <0x28>; ai3x-micbias-vg = <0x1>; status = \"okay\"; AVDD-supply = <0xa8>; IOVDD-supply = <0xa8>; DRVDD-supply = <0xa8>; DVDD-supply = <0xa9>; phandle = <0x100>; }; }; i2c@48072000 { compatible = \"ti,omap4-i2c\"; reg = <0x48072000 0x100>; interrupts = <0x0 0x34 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"i2c2\"; status = \"disabled\"; clock-frequency = <0x61a80>; ti,no-idle; ti,no-reset-on-init; phandle = <0x10c>; gpio@26 { compatible = \"ti,pcf8575\", \"nxp,pcf8575\"; reg = <0x26>; gpio-controller; #gpio-cells = <0x2>; phandle = <0xab>; p1 { gpio-hog; gpios = <0x1 0x0>; output-low; line-name = \"vin6_sel_s0\"; }; }; ov10633@37 { compatible = \"ovti,ov10633\"; reg = <0x37>; clocks = <0xaa>; clock-names = \"xvclk\"; mux-gpios = <0xab 0x3 0x1>; port { endpoint { remote-endpoint = <0xac>; hsync-active = <0x1>; vsync-active = <0x1>; pclk-sample = <0x0>; phandle = <0xf3>; }; }; }; }; i2c@48060000 { compatible = \"ti,omap4-i2c\"; reg = <0x48060000 0x100>; interrupts = <0x0 0x38 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"i2c3\"; status = \"okay\"; clock-frequency = <0x61a80>; }; i2c@4807a000 { compatible = \"ti,omap4-i2c\"; reg = <0x4807a000 0x100>; interrupts = <0x0 0x39 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"i2c4\"; status = \"okay\"; clock-frequency = <0x61a80>; }; i2c@4807c000 { compatible = \"ti,omap4-i2c\"; reg = <0x4807c000 0x100>; interrupts = <0x0 0x37 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"i2c5\"; status = \"disabled\"; }; mmc@4809c000 { compatible = \"ti,dra7-sdhci\"; reg = <0x4809c000 0x400>; interrupts = <0x0 0x4e 0x4>; ti,hwmods = \"mmc1\"; status = \"okay\"; pbias-supply = <0xad>; max-frequency = <0xb71b000>; mmc-ddr-1_8v; mmc-ddr-3_3v; vmmc-supply = <0xae>; vqmmc-supply = <0xaf>; bus-width = <0x4>; cd-gpios = <0xa7 0x1b 0x1>; pinctrl-names = \"default\", \"hs\", \"sdr12\", \"sdr25\", \"sdr50\", \"ddr50-rev11\", \"sdr104-rev11\", \"ddr50\", \"sdr104\"; pinctrl-0 = <0xb0>; pinctrl-1 = <0xb1>; pinctrl-2 = <0xb2>; pinctrl-3 = <0xb3>; pinctrl-4 = <0xb4>; pinctrl-5 = <0xb5 0xb6>; pinctrl-6 = <0xb7 0xb8>; pinctrl-7 = <0xb5 0xb9>; pinctrl-8 = <0xb7 0xba>; }; 1w@480b2000 { compatible = \"ti,omap3-1w\"; reg = <0x480b2000 0x1000>; interrupts = <0x0 0x35 0x4>; ti,hwmods = \"hdq1w\"; }; mmc@480b4000 { compatible = \"ti,dra7-sdhci\"; reg = <0x480b4000 0x400>; interrupts = <0x0 0x51 0x4>; ti,hwmods = \"mmc2\"; status = \"okay\"; max-frequency = <0xb71b000>; sdhci-caps-mask = <0x7 0x0>; mmc-hs200-1_8v; mmc-ddr-1_8v; mmc-ddr-3_3v; vmmc-supply = <0xbb>; vqmmc-supply = <0xbb>; bus-width = <0x8>; non-removable; pinctrl-names = \"default\", \"hs\", \"ddr_1_8v-rev11\", \"ddr_1_8v\", \"hs200_1_8v-rev11\", \"hs200_1_8v\"; pinctrl-0 = <0xbc>; pinctrl-1 = <0xbd>; pinctrl-2 = <0xbe 0xbf>; pinctrl-3 = <0xc0>; pinctrl-4 = <0xc1 0xc2>; pinctrl-5 = <0xc1 0xc3>; }; mmc@480ad000 { compatible = \"ti,dra7-sdhci\"; reg = <0x480ad000 0x400>; interrupts = <0x0 0x59 0x4>; ti,hwmods = \"mmc3\"; status = \"disabled\"; max-frequency = <0x3d09000>; sdhci-caps-mask = <0x0 0x400000>; }; mmc@480d1000 { compatible = \"ti,dra7-sdhci\"; reg = <0x480d1000 0x400>; interrupts = <0x0 0x5b 0x4>; ti,hwmods = \"mmc4\"; status = \"okay\"; max-frequency = <0xb71b000>; sdhci-caps-mask = <0x0 0x400000>; bus-width = <0x4>; cap-power-off-card; keep-power-in-suspend; non-removable; #address-cells = <0x1>; #size-cells = <0x0>; vmmc-supply = <0xc4>; vqmmc-supply = <0xc5>; pinctrl-names = \"default-rev11\", \"default\", \"hs-rev11\", \"hs\", \"sdr12-rev11\", \"sdr12\", \"sdr25-rev11\", \"sdr25\"; pinctrl-0 = <0xc6 0xc7>; pinctrl-1 = <0xc6 0xc8>; pinctrl-2 = <0xc9 0xca>; pinctrl-3 = <0xc9 0xcb>; pinctrl-4 = <0xcc 0xca>; pinctrl-5 = <0xcc 0xcb>; pinctrl-6 = <0xcd 0xca>; pinctrl-7 = <0xcd 0xcb>; wifi@2 { compatible = \"ti,wl1835\"; reg = <0x2>; interrupt-parent = <0xa5>; interrupts = <0x7 0x1>; }; }; mmu@40d01000 { compatible = \"ti,dra7-dsp-iommu\"; reg = <0x40d01000 0x100>; interrupts = <0x0 0x17 0x4>; ti,hwmods = \"mmu0_dsp1\"; #iommu-cells = <0x0>; ti,syscon-mmuconfig = <0xce 0x0>; phandle = <0x9a>; }; mmu@40d02000 { compatible = \"ti,dra7-dsp-iommu\"; reg = <0x40d02000 0x100>; interrupts = <0x0 0x91 0x4>; ti,hwmods = \"mmu1_dsp1\"; #iommu-cells = <0x0>; ti,syscon-mmuconfig = <0xce 0x1>; phandle = <0x9b>; }; mmu@58882000 { compatible = \"ti,dra7-iommu\"; reg = <0x58882000 0x100>; interrupts = <0x0 0x18b 0x4>; ti,hwmods = \"mmu_ipu1\"; #iommu-cells = <0x0>; ti,iommu-bus-err-back; phandle = <0x90>; }; mmu@55082000 { compatible = \"ti,dra7-iommu\"; reg = <0x55082000 0x100>; interrupts = <0x0 0x18c 0x4>; ti,hwmods = \"mmu_ipu2\"; #iommu-cells = <0x0>; ti,iommu-bus-err-back; phandle = <0x95>; }; pruss-soc-bus@4b226004 { compatible = \"ti,am5728-pruss-soc-bus\"; reg = <0x4b226004 0x4>; ti,hwmods = \"pruss1\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges; status = \"disabled\"; pruss@4b200000 { compatible = \"ti,am5728-pruss\"; reg = <0x4b200000 0x80000>; interrupts = <0x0 0xba 0x4 0x0 0xbb 0x4 0x0 0xbc 0x4 0x0 0xbd 0x4 0x0 0xbe 0x4 0x0 0xbf 0x4 0x0 0xc0 0x4 0x0 0xc1 0x4>; interrupt-names = \"host2\", \"host3\", \"host4\", \"host5\", \"host6\", \"host7\", \"host8\", \"host9\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges; status = \"disabled\"; memories@4b200000 { reg = <0x4b200000 0x2000 0x4b202000 0x2000 0x4b210000 0x8000>; reg-names = \"dram0\", \"dram1\", \"shrdram2\"; }; cfg@4b226000 { compatible = \"syscon\"; reg = <0x4b226000 0x2000>; }; iep@4b22e000 { compatible = \"syscon\"; reg = <0x4b22e000 0x31c>; }; mii-rt@4b232000 { compatible = \"syscon\"; reg = <0x4b232000 0x58>; }; interrupt-controller@4b220000 { compatible = \"ti,am5728-pruss-intc\"; reg = <0x4b220000 0x2000>; interrupt-controller; #interrupt-cells = <0x1>; phandle = <0xcf>; }; pru@4b234000 { compatible = \"ti,am5728-pru\"; reg = <0x4b234000 0x3000 0x4b222000 0x400 0x4b222400 0x100>; reg-names = \"iram\", \"control\", \"debug\"; firmware-name = \"am57xx-pru1_0-fw\"; interrupt-parent = <0xcf>; interrupts = <0x10 0x11>; interrupt-names = \"vring\", \"kick\"; }; pru@4b238000 { compatible = \"ti,am5728-pru\"; reg = <0x4b238000 0x3000 0x4b224000 0x400 0x4b224400 0x100>; reg-names = \"iram\", \"control\", \"debug\"; firmware-name = \"am57xx-pru1_1-fw\"; interrupt-parent = <0xcf>; interrupts = <0x12 0x13>; interrupt-names = \"vring\", \"kick\"; }; mdio@4b232400 { compatible = \"ti,davinci_mdio\"; reg = <0x4b232400 0x90>; #address-cells = <0x1>; #size-cells = <0x0>; clocks = <0xd0>; clock-names = \"fck\"; bus_freq = <0xf4240>; status = \"disabled\"; }; }; }; pruss-soc-bus@4b2a6004 { compatible = \"ti,am5728-pruss-soc-bus\"; reg = <0x4b2a6004 0x4>; ti,hwmods = \"pruss2\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges; status = \"disabled\"; pruss@4b280000 { compatible = \"ti,am5728-pruss\"; reg = <0x4b280000 0x80000>; interrupts = <0x0 0xc4 0x4 0x0 0xc5 0x4 0x0 0xc6 0x4 0x0 0xc7 0x4 0x0 0xc8 0x4 0x0 0xc9 0x4 0x0 0xca 0x4 0x0 0xcb 0x4>; interrupt-names = \"host2\", \"host3\", \"host4\", \"host5\", \"host6\", \"host7\", \"host8\", \"host9\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges; status = \"disabled\"; memories@4b280000 { reg = <0x4b280000 0x2000 0x4b282000 0x2000 0x4b290000 0x8000>; reg-names = \"dram0\", \"dram1\", \"shrdram2\"; }; cfg@4b2a6000 { compatible = \"syscon\"; reg = <0x4b2a6000 0x2000>; }; iep@4b2ae000 { compatible = \"syscon\"; reg = <0x4b2ae000 0x31c>; }; mii-rt@4b2b2000 { compatible = \"syscon\"; reg = <0x4b2b2000 0x58>; }; interrupt-controller@4b2a0000 { compatible = \"ti,am5728-pruss-intc\"; reg = <0x4b2a0000 0x2000>; interrupt-controller; #interrupt-cells = <0x1>; phandle = <0xd1>; }; pru@4b2b4000 { compatible = \"ti,am5728-pru\"; reg = <0x4b2b4000 0x3000 0x4b2a2000 0x400 0x4b2a2400 0x100>; reg-names = \"iram\", \"control\", \"debug\"; firmware-name = \"am57xx-pru2_0-fw\"; interrupt-parent = <0xd1>; interrupts = <0x10 0x11>; interrupt-names = \"vring\", \"kick\"; }; pru@4b2b8000 { compatible = \"ti,am5728-pru\"; reg = <0x4b2b8000 0x3000 0x4b2a4000 0x400 0x4b2a4400 0x100>; reg-names = \"iram\", \"control\", \"debug\"; firmware-name = \"am57xx-pru2_1-fw\"; interrupt-parent = <0xd1>; interrupts = <0x12 0x13>; interrupt-names = \"vring\", \"kick\"; }; mdio@4b2b2400 { compatible = \"ti,davinci_mdio\"; reg = <0x4b2b2400 0x90>; #address-cells = <0x1>; #size-cells = <0x0>; clocks = <0xd0>; clock-names = \"fck\"; bus_freq = <0xf4240>; status = \"disabled\"; }; }; }; regulator-abb-mpu { compatible = \"ti,abb-v3\"; regulator-name = \"abb_mpu\"; #address-cells = <0x0>; #size-cells = <0x0>; clocks = <0x11>; ti,settling-time = <0x32>; ti,clock-cycles = <0x10>; reg = <0x4ae07ddc 0x4 0x4ae07de0 0x4 0x4ae06014 0x4 0x4a003b20 0xc 0x4ae0c158 0x4>; reg-names = \"setup-address\", \"control-address\", \"int-address\", \"efuse-address\", \"ldo-address\"; ti,tranxdone-status-mask = <0x80>; ti,ldovbb-override-mask = <0x400>; ti,ldovbb-vset-mask = <0x1f>; ti,abb_info = <0x102ca0 0x0 0x0 0x0 0x2000000 0x1f00000 0x11b340 0x0 0x4 0x0 0x2000000 0x1f00000 0x127690 0x0 0x8 0x0 0x2000000 0x1f00000>; phandle = <0x5>; }; regulator-abb-ivahd { compatible = \"ti,abb-v3\"; regulator-name = \"abb_ivahd\"; #address-cells = <0x0>; #size-cells = <0x0>; clocks = <0x11>; ti,settling-time = <0x32>; ti,clock-cycles = <0x10>; reg = <0x4ae07e34 0x4 0x4ae07e24 0x4 0x4ae06010 0x4 0x4a0025cc 0xc 0x4a002470 0x4>; reg-names = \"setup-address\", \"control-address\", \"int-address\", \"efuse-address\", \"ldo-address\"; ti,tranxdone-status-mask = <0x40000000>; ti,ldovbb-override-mask = <0x400>; ti,ldovbb-vset-mask = <0x1f>; ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>; }; regulator-abb-dspeve { compatible = \"ti,abb-v3\"; regulator-name = \"abb_dspeve\"; #address-cells = <0x0>; #size-cells = <0x0>; clocks = <0x11>; ti,settling-time = <0x32>; ti,clock-cycles = <0x10>; reg = <0x4ae07e30 0x4 0x4ae07e20 0x4 0x4ae06010 0x4 0x4a0025e0 0xc 0x4a00246c 0x4>; reg-names = \"setup-address\", \"control-address\", \"int-address\", \"efuse-address\", \"ldo-address\"; ti,tranxdone-status-mask = <0x20000000>; ti,ldovbb-override-mask = <0x400>; ti,ldovbb-vset-mask = <0x1f>; ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>; }; regulator-abb-gpu { compatible = \"ti,abb-v3\"; regulator-name = \"abb_gpu\"; #address-cells = <0x0>; #size-cells = <0x0>; clocks = <0x11>; ti,settling-time = <0x32>; ti,clock-cycles = <0x10>; reg = <0x4ae07de4 0x4 0x4ae07de8 0x4 0x4ae06010 0x4 0x4a003b08 0xc 0x4ae0c154 0x4>; reg-names = \"setup-address\", \"control-address\", \"int-address\", \"efuse-address\", \"ldo-address\"; ti,tranxdone-status-mask = <0x10000000>; ti,ldovbb-override-mask = <0x400>; ti,ldovbb-vset-mask = <0x1f>; ti,abb_info = <0x10a1d0 0x0 0x0 0x0 0x2000000 0x1f00000 0x127690 0x0 0x4 0x0 0x2000000 0x1f00000 0x138800 0x0 0x8 0x0 0x2000000 0x1f00000>; }; spi@48098000 { compatible = \"ti,omap4-mcspi\"; reg = <0x48098000 0x200>; interrupts = <0x0 0x3c 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"mcspi1\"; ti,spi-num-cs = <0x4>; dmas = <0x8d 0x23 0x8d 0x24 0x8d 0x25 0x8d 0x26 0x8d 0x27 0x8d 0x28 0x8d 0x29 0x8d 0x2a>; dma-names = \"tx0\", \"rx0\", \"tx1\", \"rx1\", \"tx2\", \"rx2\", \"tx3\", \"rx3\"; status = \"disabled\"; }; spi@4809a000 { compatible = \"ti,omap4-mcspi\"; reg = <0x4809a000 0x200>; interrupts = <0x0 0x3d 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"mcspi2\"; ti,spi-num-cs = <0x2>; dmas = <0x8d 0x2b 0x8d 0x2c 0x8d 0x2d 0x8d 0x2e>; dma-names = \"tx0\", \"rx0\", \"tx1\", \"rx1\"; status = \"okay\"; }; spi@480b8000 { compatible = \"ti,omap4-mcspi\"; reg = <0x480b8000 0x200>; interrupts = <0x0 0x56 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"mcspi3\"; ti,spi-num-cs = <0x2>; dmas = <0x8d 0xf 0x8d 0x10>; dma-names = \"tx0\", \"rx0\"; status = \"disabled\"; }; spi@480ba000 { compatible = \"ti,omap4-mcspi\"; reg = <0x480ba000 0x200>; interrupts = <0x0 0x2b 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"mcspi4\"; ti,spi-num-cs = <0x1>; dmas = <0x8d 0x46 0x8d 0x47>; dma-names = \"tx0\", \"rx0\"; status = \"disabled\"; }; qspi@4b300000 { compatible = \"ti,dra7xxx-qspi\"; reg = <0x4b300000 0x100 0x5c000000 0x4000000>; reg-names = \"qspi_base\", \"qspi_mmap\"; syscon-chipselects = <0x9 0x558>; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"qspi\"; clocks = <0x57 0x138 0x19>; clock-names = \"fck\"; num-cs = <0x4>; interrupts = <0x0 0x157 0x4>; status = \"okay\"; spi-max-frequency = <0x493e000>; m25p80@0 { compatible = \"s25fl256s1\"; spi-max-frequency = <0x493e000>; reg = <0x0>; spi-tx-bus-width = <0x1>; spi-rx-bus-width = <0x4>; #address-cells = <0x1>; #size-cells = <0x1>; partition@0 { label = \"QSPI.SPL\"; reg = <0x0 0x40000>; }; partition@1 { label = \"QSPI.u-boot\"; reg = <0x40000 0x100000>; }; partition@2 { label = \"QSPI.u-boot-spl-os\"; reg = <0x140000 0x80000>; }; partition@3 { label = \"QSPI.u-boot-env\"; reg = <0x1c0000 0x10000>; }; partition@4 { label = \"QSPI.u-boot-env.backup1\"; reg = <0x1d0000 0x10000>; }; partition@5 { label = \"QSPI.kernel\"; reg = <0x1e0000 0x800000>; }; partition@6 { label = \"QSPI.file-system\"; reg = <0x9e0000 0x1620000>; }; }; }; ocp2scp@4a090000 { compatible = \"ti,omap-ocp2scp\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges; reg = <0x4a090000 0x20>; ti,hwmods = \"ocp2scp3\"; phy@4a096000 { compatible = \"ti,phy-pipe3-sata\"; reg = <0x4a096000 0x80 0x4a096400 0x64 0x4a096800 0x40>; reg-names = \"phy_rx\", \"phy_tx\", \"pll_ctrl\"; syscon-phy-power = <0x9 0x374>; clocks = <0x11 0xd2 0x68 0x8>; clock-names = \"sysclk\", \"refclk\"; syscon-pllreset = <0x9 0x3fc>; #phy-cells = <0x0>; phandle = <0xd4>; }; pciephy@4a094000 { compatible = \"ti,phy-pipe3-pcie\"; reg = <0x4a094000 0x80 0x4a094400 0x64>; reg-names = \"phy_rx\", \"phy_tx\"; syscon-phy-power = <0x85 0x1c>; syscon-pcs = <0x85 0x10>; clocks = <0x3e 0x3f 0xd2 0x90 0x8 0xd2 0x90 0x9 0xd2 0x90 0xa 0xd3 0x11>; clock-names = \"dpll_ref\", \"dpll_ref_m2\", \"wkupclk\", \"refclk\", \"div-clk\", \"phy-div\", \"sysclk\"; #phy-cells = <0x0>; phandle = <0x84>; }; pciephy@4a095000 { compatible = \"ti,phy-pipe3-pcie\"; reg = <0x4a095000 0x80 0x4a095400 0x64>; reg-names = \"phy_rx\", \"phy_tx\"; syscon-phy-power = <0x85 0x20>; syscon-pcs = <0x85 0x10>; clocks = <0x3e 0x3f 0xd2 0x98 0x8 0xd2 0x98 0x9 0xd2 0x98 0xa 0xd3 0x11>; clock-names = \"dpll_ref\", \"dpll_ref_m2\", \"wkupclk\", \"refclk\", \"div-clk\", \"phy-div\", \"sysclk\"; #phy-cells = <0x0>; status = \"disabled\"; phandle = <0x88>; }; }; sata@4a141100 { compatible = \"snps,dwc-ahci\"; reg = <0x4a140000 0x1100 0x4a141100 0x7>; interrupts = <0x0 0x31 0x4>; phys = <0xd4>; phy-names = \"sata-phy\"; clocks = <0xd2 0x68 0x8>; ti,hwmods = \"sata\"; ports-implemented = <0x1>; }; rtc@48838000 { compatible = \"ti,am3352-rtc\"; reg = <0x48838000 0x100>; interrupts = <0x0 0xd9 0x4 0x0 0xd9 0x4>; ti,hwmods = \"rtcss\"; clocks = <0x50>; }; ocp2scp@4a080000 { compatible = \"ti,omap-ocp2scp\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges; reg = <0x4a080000 0x20>; ti,hwmods = \"ocp2scp1\"; phy@4a084000 { compatible = \"ti,dra7x-usb2\", \"ti,omap-usb2\"; reg = <0x4a084000 0x400>; syscon-phy-power = <0x9 0x300>; clocks = <0xd5 0xd2 0xd0 0x8>; clock-names = \"wkupclk\", \"refclk\"; #phy-cells = <0x0>; phy-supply = <0xd6>; phandle = <0xdb>; }; phy@4a085000 { compatible = \"ti,dra7x-usb2-phy2\", \"ti,omap-usb2\"; reg = <0x4a085000 0x400>; syscon-phy-power = <0x9 0xe74>; clocks = <0xd7 0xd2 0x20 0x8>; clock-names = \"wkupclk\", \"refclk\"; #phy-cells = <0x0>; phy-supply = <0xd6>; phandle = <0xde>; }; phy@4a084400 { compatible = \"ti,omap-usb3\"; reg = <0x4a084400 0x80 0x4a084800 0x64 0x4a084c00 0x40>; reg-names = \"phy_rx\", \"phy_tx\", \"pll_ctrl\"; syscon-phy-power = <0x9 0x370>; clocks = <0xd8 0x11 0xd2 0xd0 0x8>; clock-names = \"wkupclk\", \"sysclk\", \"refclk\"; #phy-cells = <0x0>; phandle = <0xdc>; }; }; target-module@4a0dd000 { compatible = \"ti,sysc-omap4-sr\", \"ti,sysc\"; ti,hwmods = \"smartreflex_core\"; reg = <0x4a0dd038 0x4>; reg-names = \"sysc\"; ti,sysc-mask = <0x4000000>; ti,sysc-sidle = <0x0 0x1 0x2 0x3>; clocks = <0xd9 0x18 0x0>; clock-names = \"fck\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x4a0dd000 0x1000>; }; target-module@4a0d9000 { compatible = \"ti,sysc-omap4-sr\", \"ti,sysc\"; ti,hwmods = \"smartreflex_mpu\"; reg = <0x4a0d9038 0x4>; reg-names = \"sysc\"; ti,sysc-mask = <0x4000000>; ti,sysc-sidle = <0x0 0x1 0x2 0x3>; clocks = <0xd9 0x8 0x0>; clock-names = \"fck\"; #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0x0 0x4a0d9000 0x1000>; }; omap_dwc3_1@48880000 { compatible = \"ti,dwc3\"; ti,hwmods = \"usb_otg_ss1\"; reg = <0x48880000 0x10000>; interrupts = <0x0 0x48 0x4>; #address-cells = <0x1>; #size-cells = <0x1>; utmi-mode = <0x2>; ranges; extcon = <0xda>; usb@48890000 { compatible = \"snps,dwc3\"; reg = <0x48890000 0x17000>; interrupts = <0x0 0x47 0x4 0x0 0x47 0x4 0x0 0x48 0x4>; interrupt-names = \"peripheral\", \"host\", \"otg\"; phys = <0xdb 0xdc>; phy-names = \"usb2-phy\", \"usb3-phy\"; maximum-speed = \"super-speed\"; dr_mode = \"otg\"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; extcon = <0xda>; }; }; omap_dwc3_2@488c0000 { compatible = \"ti,dwc3\"; ti,hwmods = \"usb_otg_ss2\"; reg = <0x488c0000 0x10000>; interrupts = <0x0 0x57 0x4>; #address-cells = <0x1>; #size-cells = <0x1>; utmi-mode = <0x2>; ranges; extcon = <0xdd>; usb@488d0000 { compatible = \"snps,dwc3\"; reg = <0x488d0000 0x17000>; interrupts = <0x0 0x49 0x4 0x0 0x49 0x4 0x0 0x57 0x4>; interrupt-names = \"peripheral\", \"host\", \"otg\"; phys = <0xde>; phy-names = \"usb2-phy\"; maximum-speed = \"high-speed\"; dr_mode = \"host\"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; snps,dis_metastability_quirk; extcon = <0xdd>; }; }; omap_dwc3_3@48900000 { compatible = \"ti,dwc3\"; ti,hwmods = \"usb_otg_ss3\"; reg = <0x48900000 0x10000>; interrupts = <0x0 0x158 0x4>; #address-cells = <0x1>; #size-cells = <0x1>; utmi-mode = <0x2>; ranges; status = \"disabled\"; usb@48910000 { compatible = \"snps,dwc3\"; reg = <0x48910000 0x17000>; interrupts = <0x0 0x58 0x4 0x0 0x58 0x4 0x0 0x158 0x4>; interrupt-names = \"peripheral\", \"host\", \"otg\"; maximum-speed = \"high-speed\"; dr_mode = \"otg\"; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; }; }; elm@48078000 { compatible = \"ti,am3352-elm\"; reg = <0x48078000 0xfc0>; interrupts = <0x0 0x1 0x4>; ti,hwmods = \"elm\"; status = \"okay\"; phandle = <0xe1>; }; gpmc@50000000 { compatible = \"ti,am3352-gpmc\"; ti,hwmods = \"gpmc\"; reg = <0x50000000 0x37c>; interrupts = <0x0 0xf 0x4>; dmas = <0xdf 0x4 0x0>; dma-names = \"rxtx\"; gpmc,num-cs = <0x8>; gpmc,num-waitpins = <0x2>; #address-cells = <0x2>; #size-cells = <0x1>; interrupt-controller; #interrupt-cells = <0x2>; gpio-controller; #gpio-cells = <0x2>; status = \"disabled\"; ranges = <0x0 0x0 0x8000000 0x1000000>; phandle = <0xe0>; nand@0,0 { compatible = \"ti,omap2-nand\"; reg = <0x0 0x0 0x4>; interrupt-parent = <0xe0>; interrupts = <0x0 0x0 0x1 0x0>; rb-gpios = <0xe0 0x0 0x0>; ti,nand-xfer-type = \"prefetch-dma\"; ti,nand-ecc-opt = \"bch8\"; ti,elm-id = <0xe1>; nand-bus-width = <0x10>; gpmc,device-width = <0x2>; gpmc,sync-clk-ps = <0x0>; gpmc,cs-on-ns = <0x0>; gpmc,cs-rd-off-ns = <0x50>; gpmc,cs-wr-off-ns = <0x50>; gpmc,adv-on-ns = <0x0>; gpmc,adv-rd-off-ns = <0x3c>; gpmc,adv-wr-off-ns = <0x3c>; gpmc,we-on-ns = <0xa>; gpmc,we-off-ns = <0x32>; gpmc,oe-on-ns = <0x4>; gpmc,oe-off-ns = <0x28>; gpmc,access-ns = <0x28>; gpmc,wr-access-ns = <0x50>; gpmc,rd-cycle-ns = <0x50>; gpmc,wr-cycle-ns = <0x50>; gpmc,bus-turnaround-ns = <0x0>; gpmc,cycle2cycle-delay-ns = <0x0>; gpmc,clk-activation-ns = <0x0>; gpmc,wr-data-mux-bus-ns = <0x0>; #address-cells = <0x1>; #size-cells = <0x1>; partition@0 { label = \"NAND.SPL\"; reg = <0x0 0x20000>; }; partition@1 { label = \"NAND.SPL.backup1\"; reg = <0x20000 0x20000>; }; partition@2 { label = \"NAND.SPL.backup2\"; reg = <0x40000 0x20000>; }; partition@3 { label = \"NAND.SPL.backup3\"; reg = <0x60000 0x20000>; }; partition@4 { label = \"NAND.u-boot-spl-os\"; reg = <0x80000 0x40000>; }; partition@5 { label = \"NAND.u-boot\"; reg = <0xc0000 0x100000>; }; partition@6 { label = \"NAND.u-boot-env\"; reg = <0x1c0000 0x20000>; }; partition@7 { label = \"NAND.u-boot-env.backup1\"; reg = <0x1e0000 0x20000>; }; partition@8 { label = \"NAND.kernel\"; reg = <0x200000 0x800000>; }; partition@9 { label = \"NAND.file-system\"; reg = <0xa00000 0xf600000>; }; }; }; atl@4843c000 { compatible = \"ti,dra7-atl\"; reg = <0x4843c000 0x3ff>; ti,hwmods = \"atl\"; ti,provided-clocks = <0xe2 0xe3 0xe4 0xe5>; clocks = <0x10 0x0 0x1a>; clock-names = \"fck\"; status = \"disabled\"; assigned-clocks = <0x61 0x10 0x0 0x1a 0x14 0x16 0xe4>; assigned-clock-parents = <0x60 0x64>; assigned-clock-rates = <0x0 0x0 0xac44000 0x15888000 0x562200>; atl2 { bws = <0x3>; aws = <0x4>; }; }; mcasp@48460000 { compatible = \"ti,dra7-mcasp-audio\"; ti,hwmods = \"mcasp1\"; reg = <0x48460000 0x2000 0x45800000 0x1000>; reg-names = \"mpu\", \"dat\"; interrupts = <0x0 0x68 0x4 0x0 0x67 0x4>; interrupt-names = \"tx\", \"rx\"; dmas = <0xdf 0x81 0x1 0xdf 0x80 0x1>; dma-names = \"tx\", \"rx\"; clocks = <0x8f 0x10 0x16 0x8f 0x10 0x18 0x8f 0x10 0x1c>; clock-names = \"fck\", \"ahclkx\", \"ahclkr\"; status = \"disabled\"; }; mcasp@48464000 { compatible = \"ti,dra7-mcasp-audio\"; ti,hwmods = \"mcasp2\"; reg = <0x48464000 0x2000 0x45c00000 0x1000>; reg-names = \"mpu\", \"dat\"; interrupts = <0x0 0x95 0x4 0x0 0x94 0x4>; interrupt-names = \"tx\", \"rx\"; dmas = <0xdf 0x83 0x1 0xdf 0x82 0x1>; dma-names = \"tx\", \"rx\"; clocks = <0x57 0x160 0x16 0x57 0x160 0x18 0x57 0x160 0x1c>; clock-names = \"fck\", \"ahclkx\", \"ahclkr\"; status = \"disabled\"; }; mcasp@48468000 { compatible = \"ti,dra7-mcasp-audio\"; ti,hwmods = \"mcasp3\"; reg = <0x48468000 0x2000 0x46000000 0x1000>; reg-names = \"mpu\", \"dat\"; interrupts = <0x0 0x97 0x4 0x0 0x96 0x4>; interrupt-names = \"tx\", \"rx\"; dmas = <0xdf 0x85 0x1 0xdf 0x84 0x1>; dma-names = \"tx\", \"rx\"; clocks = <0x57 0x168 0x16 0x57 0x168 0x18>; clock-names = \"fck\", \"ahclkx\"; status = \"disabled\"; #sound-dai-cells = <0x0>; assigned-clocks = <0x57 0x168 0x18>; assigned-clock-parents = <0xe4>; op-mode = <0x0>; tdm-slots = <0x2>; serial-dir = <0x1 0x2 0x0 0x0>; tx-num-evt = <0x20>; rx-num-evt = <0x20>; phandle = <0xff>; }; mcasp@4846c000 { compatible = \"ti,dra7-mcasp-audio\"; ti,hwmods = \"mcasp4\"; reg = <0x4846c000 0x2000 0x48436000 0x1000>; reg-names = \"mpu\", \"dat\"; interrupts = <0x0 0x99 0x4 0x0 0x98 0x4>; interrupt-names = \"tx\", \"rx\"; dmas = <0xdf 0x87 0x1 0xdf 0x86 0x1>; dma-names = \"tx\", \"rx\"; clocks = <0x57 0x198 0x16 0x57 0x198 0x18>; clock-names = \"fck\", \"ahclkx\"; status = \"disabled\"; }; mcasp@48470000 { compatible = \"ti,dra7-mcasp-audio\"; ti,hwmods = \"mcasp5\"; reg = <0x48470000 0x2000 0x4843a000 0x1000>; reg-names = \"mpu\", \"dat\"; interrupts = <0x0 0x9b 0x4 0x0 0x9a 0x4>; interrupt-names = \"tx\", \"rx\"; dmas = <0xdf 0x89 0x1 0xdf 0x88 0x1>; dma-names = \"tx\", \"rx\"; clocks = <0x57 0x178 0x16 0x57 0x178 0x18>; clock-names = \"fck\", \"ahclkx\"; status = \"disabled\"; }; mcasp@48474000 { compatible = \"ti,dra7-mcasp-audio\"; ti,hwmods = \"mcasp6\"; reg = <0x48474000 0x2000 0x4844c000 0x1000>; reg-names = \"mpu\", \"dat\"; interrupts = <0x0 0x9d 0x4 0x0 0x9c 0x4>; interrupt-names = \"tx\", \"rx\"; dmas = <0xdf 0x8b 0x1 0xdf 0x8a 0x1>; dma-names = \"tx\", \"rx\"; clocks = <0x57 0x204 0x16 0x57 0x204 0x18>; clock-names = \"fck\", \"ahclkx\"; status = \"disabled\"; }; mcasp@48478000 { compatible = \"ti,dra7-mcasp-audio\"; ti,hwmods = \"mcasp7\"; reg = <0x48478000 0x2000 0x48450000 0x1000>; reg-names = \"mpu\", \"dat\"; interrupts = <0x0 0x9f 0x4 0x0 0x9e 0x4>; interrupt-names = \"tx\", \"rx\"; dmas = <0xdf 0x8d 0x1 0xdf 0x8c 0x1>; dma-names = \"tx\", \"rx\"; clocks = <0x57 0x208 0x16 0x57 0x208 0x18>; clock-names = \"fck\", \"ahclkx\"; status = \"disabled\"; }; mcasp@4847c000 { compatible = \"ti,dra7-mcasp-audio\"; ti,hwmods = \"mcasp8\"; reg = <0x4847c000 0x2000 0x48454000 0x1000>; reg-names = \"mpu\", \"dat\"; interrupts = <0x0 0xa1 0x4 0x0 0xa0 0x4>; interrupt-names = \"tx\", \"rx\"; dmas = <0xdf 0x8f 0x1 0xdf 0x8e 0x1>; dma-names = \"tx\", \"rx\"; clocks = <0x57 0x190 0x16 0x57 0x190 0x18>; clock-names = \"fck\", \"ahclkx\"; status = \"okay\"; pinctrl-names = \"default\"; pinctrl-0 = <0xe6>; gpio-controller; #gpio-cells = <0x2>; phandle = <0x10d>; }; crossbar@4a002a48 { compatible = \"ti,irq-crossbar\"; reg = <0x4a002a48 0x130>; interrupt-controller; interrupt-parent = <0x8>; #interrupt-cells = <0x3>; ti,max-irqs = <0xa0>; ti,max-crossbar-sources = <0x190>; ti,reg-size = <0x2>; ti,irqs-reserved = <0x0 0x1 0x2 0x3 0x5 0x6 0x83 0x84>; ti,irqs-skip = <0xa 0x85 0x8b 0x8c>; ti,irqs-safe-map = <0x0>; phandle = <0x1>; }; ethernet@48484000 { compatible = \"ti,dra7-cpsw\", \"ti,cpsw\"; ti,hwmods = \"gmac\"; clocks = <0xe7 0xd2 0xb0 0x19>; clock-names = \"fck\", \"cpts\"; cpdma_channels = <0x8>; ale_entries = <0x400>; bd_ram_size = <0x2000>; mac_control = <0x20>; slaves = <0x2>; active_slave = <0x0>; cpts_clock_mult = <0x784cfe14>; cpts_clock_shift = <0x1d>; reg = <0x48484000 0x1000 0x48485200 0x2e00>; #address-cells = <0x1>; #size-cells = <0x1>; ti,no-idle; interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>; ranges; syscon = <0x9>; status = \"okay\"; mdio@48485000 { compatible = \"ti,cpsw-mdio\", \"ti,davinci_mdio\"; #address-cells = <0x1>; #size-cells = <0x0>; ti,hwmods = \"davinci_mdio\"; bus_freq = <0xf4240>; reg = <0x48485000 0x100>; phandle = <0xe8>; }; slave@48480200 { mac-address = [00 00 00 00 00 00]; phy_id = <0xe8 0x2>; phy-mode = \"rgmii\"; dual_emac_res_vlan = <0x1>; fixed-link { speed = <0x3e8>; full-duplex; }; }; slave@48480300 { mac-address = [00 00 00 00 00 00]; phy_id = <0xe8 0x3>; phy-mode = \"rgmii\"; dual_emac_res_vlan = <0x2>; fixed-link { speed = <0x64>; full-duplex; }; }; cpsw-phy-sel@4a002554 { compatible = \"ti,dra7xx-cpsw-phy-sel\"; reg = <0x4a002554 0x4>; reg-names = \"gmii-sel\"; }; }; can@4ae3c000 { compatible = \"ti,dra7-d_can\"; ti,hwmods = \"dcan1\"; reg = <0x4ae3c000 0x2000>; syscon-raminit = <0x9 0x558 0x0>; interrupts = <0x0 0xde 0x4>; clocks = <0x8e 0x68 0x18>; status = \"okay\"; pinctrl-names = \"default\", \"sleep\", \"active\"; pinctrl-0 = <0xe9>; pinctrl-1 = <0xe9>; pinctrl-2 = <0xea>; }; can@48480000 { compatible = \"ti,dra7-d_can\"; ti,hwmods = \"dcan2\"; reg = <0x48480000 0x2000>; syscon-raminit = <0x9 0x558 0x1>; interrupts = <0x0 0xe1 0x4>; clocks = <0x11>; status = \"disabled\"; }; gpu@56000000 { compatible = \"ti,dra7-sgx544\", \"img,sgx544\"; reg = <0x56000000 0x10000>; reg-names = \"gpu_ocp_base\"; interrupts = <0x0 0x10 0x4>; ti,hwmods = \"gpu\"; clocks = <0xa 0x53 0x54>; clock-names = \"iclk\", \"fclk1\", \"fclk2\"; status = \"ok\"; memory-region = <0xeb>; }; bb2d@59000000 { compatible = \"ti,dra7-bb2d\"; reg = <0x59000000 0x700>; interrupts = <0x0 0x78 0x4>; ti,hwmods = \"bb2d\"; clocks = <0xec 0x10 0x0>; clock-names = \"fck\"; status = \"okay\"; }; dss@58000000 { compatible = \"ti,dra7-dss\"; status = \"disabled\"; ti,hwmods = \"dss_core\"; syscon-pll-ctrl = <0x9 0x538>; #address-cells = <0x1>; #size-cells = <0x1>; ranges; reg = <0x58000000 0x80 0x58004054 0x4 0x58004300 0x20 0x58009054 0x4 0x58009300 0x20>; reg-names = \"dss\", \"pll1_clkctrl\", \"pll1\", \"pll2_clkctrl\", \"pll2\"; clocks = <0xec 0x0 0x8 0xec 0x0 0xc 0xec 0x0 0xd>; clock-names = \"fck\", \"video1_clk\", \"video2_clk\"; vdda_video-supply = <0xed>; ti,no-idle; ti,no-reset-on-init; dispc@58001000 { compatible = \"ti,dra7-dispc\"; reg = <0x58001000 0x1000>; interrupts = <0x0 0x14 0x4>; ti,hwmods = \"dss_dispc\"; clocks = <0xec 0x0 0x8>; clock-names = \"fck\"; syscon-pol = <0x9 0x534>; status = \"disabled\"; ti,no-idle; ti,no-reset-on-init; }; encoder@58060000 { compatible = \"ti,dra7-hdmi\"; reg = <0x58040000 0x200 0x58040200 0x80 0x58040300 0x80 0x58060000 0x19000>; reg-names = \"wp\", \"pll\", \"phy\", \"core\"; interrupts = <0x0 0x60 0x4>; status = \"disabled\"; ti,hwmods = \"dss_hdmi\"; clocks = <0xec 0x0 0x9 0xec 0x0 0xa>; clock-names = \"fck\", \"sys_clk\"; dmas = <0x8d 0x4c>; dma-names = \"audio_tx\"; vdda-supply = <0xee>; ti,no-idle; ti,no-reset-on-init; port { endpoint { remote-endpoint = <0xef>; phandle = <0x10e>; }; }; }; }; vdrm@0 { compatible = \"ti,dra7-vdrm\"; crtc@0 { compatible = \"ti,dra7-vdrm-crtc\"; x-res = <0x780>; y-res = <0x438>; refresh = <0x3c>; supported-formats = <0x34325258>; }; }; epwmss@4843e000 { compatible = \"ti,dra746-pwmss\", \"ti,am33xx-pwmss\"; reg = <0x4843e000 0x30>; ti,hwmods = \"epwmss0\"; #address-cells = <0x1>; #size-cells = <0x1>; status = \"disabled\"; ranges; pwm@4843e200 { compatible = \"ti,dra746-ehrpwm\", \"ti,am3352-ehrpwm\"; #pwm-cells = <0x3>; reg = <0x4843e200 0x80>; clocks = <0xf0 0xb>; clock-names = \"tbclk\", \"fck\"; status = \"disabled\"; }; ecap@4843e100 { compatible = \"ti,dra746-ecap\", \"ti,am3352-ecap\"; #pwm-cells = <0x3>; reg = <0x4843e100 0x80>; clocks = <0xb>; clock-names = \"fck\"; status = \"disabled\"; }; }; epwmss@48440000 { compatible = \"ti,dra746-pwmss\", \"ti,am33xx-pwmss\"; reg = <0x48440000 0x30>; ti,hwmods = \"epwmss1\"; #address-cells = <0x1>; #size-cells = <0x1>; status = \"disabled\"; ranges; pwm@48440200 { compatible = \"ti,dra746-ehrpwm\", \"ti,am3352-ehrpwm\"; #pwm-cells = <0x3>; reg = <0x48440200 0x80>; clocks = <0xf1 0xb>; clock-names = \"tbclk\", \"fck\"; status = \"disabled\"; }; ecap@48440100 { compatible = \"ti,dra746-ecap\", \"ti,am3352-ecap\"; #pwm-cells = <0x3>; reg = <0x48440100 0x80>; clocks = <0xb>; clock-names = \"fck\"; status = \"disabled\"; }; }; epwmss@48442000 { compatible = \"ti,dra746-pwmss\", \"ti,am33xx-pwmss\"; reg = <0x48442000 0x30>; ti,hwmods = \"epwmss2\"; #address-cells = <0x1>; #size-cells = <0x1>; status = \"disabled\"; ranges; pwm@48442200 { compatible = \"ti,dra746-ehrpwm\", \"ti,am3352-ehrpwm\"; #pwm-cells = <0x3>; reg = <0x48442200 0x80>; clocks = <0xf2 0xb>; clock-names = \"tbclk\", \"fck\"; status = \"disabled\"; }; ecap@48442100 { compatible = \"ti,dra746-ecap\", \"ti,am3352-ecap\"; #pwm-cells = <0x3>; reg = <0x48442100 0x80>; clocks = <0xb>; clock-names = \"fck\"; status = \"disabled\"; }; }; aes@4b500000 { compatible = \"ti,omap4-aes\"; ti,hwmods = \"aes1\"; reg = <0x4b500000 0xa0>; interrupts = <0x0 0x50 0x4>; dmas = <0xdf 0x6f 0x0 0xdf 0x6e 0x0>; dma-names = \"tx\", \"rx\"; clocks = <0xa>; clock-names = \"fck\"; }; aes@4b700000 { compatible = \"ti,omap4-aes\"; ti,hwmods = \"aes2\"; reg = <0x4b700000 0xa0>; interrupts = <0x0 0x3b 0x4>; dmas = <0xdf 0x72 0x0 0xdf 0x71 0x0>; dma-names = \"tx\", \"rx\"; clocks = <0xa>; clock-names = \"fck\"; }; des@480a5000 { compatible = \"ti,omap4-des\"; ti,hwmods = \"des\"; reg = <0x480a5000 0xa0>; interrupts = <0x0 0x4d 0x4>; dmas = <0x8d 0x75 0x8d 0x74>; dma-names = \"tx\", \"rx\"; clocks = <0xa>; clock-names = \"fck\"; }; sham@53100000 { compatible = \"ti,omap5-sham\"; ti,hwmods = \"sham\"; reg = <0x4b101000 0x300>; interrupts = <0x0 0x2e 0x4>; dmas = <0xdf 0x77 0x0>; dma-names = \"rx\"; clocks = <0xa>; clock-names = \"fck\"; }; rng@48090000 { compatible = \"ti,omap4-rng\"; ti,hwmods = \"rng\"; reg = <0x48090000 0x2000>; interrupts = <0x0 0x2f 0x4>; clocks = <0xa>; clock-names = \"fck\"; }; opp-supply@4a003b20 { compatible = \"ti,omap5-opp-supply\"; reg = <0x4a003b20 0xc>; ti,efuse-settings = <0x102ca0 0x0 0x11b340 0x4 0x127690 0x8>; ti,absolute-max-voltage-uv = <0x16e360>; }; vpe { compatible = \"ti,vpe\"; ti,hwmods = \"vpe\"; clocks = <0x56>; clock-names = \"fck\"; reg = <0x489d0000 0x120 0x489d0700 0x80 0x489d5700 0x18 0x489dd000 0x400>; reg-names = \"vpe_top\", \"sc\", \"csc\", \"vpdma\"; interrupts = <0x0 0x162 0x4>; #address-cells = <0x1>; #size-cells = <0x0>; status = \"disabled\"; ti,no-idle; ti,no-reset-on-init; }; vip@0x48970000 { compatible = \"ti,vip1\"; reg = <0x48970000 0x114 0x48975500 0xd8 0x48975700 0x18 0x48975800 0x80 0x48975a00 0xd8 0x48975c00 0x18 0x48975d00 0x80 0x4897d000 0x400>; reg-names = \"vip\", \"parser0\", \"csc0\", \"sc0\", \"parser1\", \"csc1\", \"sc1\", \"vpdma\"; ti,hwmods = \"vip1\"; interrupts = <0x0 0x15f 0x4 0x0 0x188 0x4>; syscon-pol = <0x9 0x534>; #address-cells = <0x1>; #size-cells = <0x0>; status = \"disabled\"; ti,no-idle; ti,no-reset-on-init; ports { #address-cells = <0x1>; #size-cells = <0x0>; port@0 { reg = <0x0>; endpoint@0 { slave-mode; remote-endpoint = <0xf3>; phandle = <0xac>; }; }; port@1 { reg = <0x1>; }; port@2 { reg = <0x2>; }; port@3 { reg = <0x3>; }; }; }; dsp_system@41500000 { compatible = \"syscon\"; reg = <0x41500000 0x100>; phandle = <0xf4>; }; omap_dwc3_4@48940000 { compatible = \"ti,dwc3\"; ti,hwmods = \"usb_otg_ss4\"; reg = <0x48940000 0x10000>; interrupts = <0x0 0x15a 0x4>; #address-cells = <0x1>; #size-cells = <0x1>; utmi-mode = <0x2>; ranges; status = \"disabled\"; usb@48950000 { compatible = \"snps,dwc3\"; reg = <0x48950000 0x17000>; interrupts = <0x0 0x159 0x4 0x0 0x159 0x4 0x0 0x15a 0x4>; interrupt-names = \"peripheral\", \"host\", \"otg\"; maximum-speed = \"high-speed\"; dr_mode = \"otg\"; }; }; mmu@41501000 { compatible = \"ti,dra7-dsp-iommu\"; reg = <0x41501000 0x100>; interrupts = <0x0 0x92 0x4>; ti,hwmods = \"mmu0_dsp2\"; #iommu-cells = <0x0>; ti,syscon-mmuconfig = <0xf4 0x0>; phandle = <0xf5>; }; mmu@41502000 { compatible = \"ti,dra7-dsp-iommu\"; reg = <0x41502000 0x100>; interrupts = <0x0 0x93 0x4>; ti,hwmods = \"mmu1_dsp2\"; #iommu-cells = <0x0>; ti,syscon-mmuconfig = <0xf4 0x1>; phandle = <0xf6>; }; dsp@41000000 { compatible = \"ti,dra7-dsp\"; reg = <0x41000000 0x48000 0x41600000 0x8000 0x41700000 0x8000>; reg-names = \"l2ram\", \"l1pram\", \"l1dram\"; ti,hwmods = \"dsp2\"; syscon-bootreg = <0x9 0x560>; iommus = <0xf5 0xf6>; ti,rproc-standby-info = <0x4a005620>; status = \"okay\"; mboxes = <0x96 0xf7>; timers = <0xf8>; memory-region = <0xf9>; }; vip@0x48990000 { compatible = \"ti,vip2\"; reg = <0x48990000 0x114 0x48995500 0xd8 0x48995700 0x18 0x48995800 0x80 0x48995a00 0xd8 0x48995c00 0x18 0x48995d00 0x80 0x4899d000 0x400>; reg-names = \"vip\", \"parser0\", \"csc0\", \"sc0\", \"parser1\", \"csc1\", \"sc1\", \"vpdma\"; ti,hwmods = \"vip2\"; interrupts = <0x0 0x160 0x4 0x0 0x189 0x4>; syscon-pol = <0x9 0x534>; #address-cells = <0x1>; #size-cells = <0x0>; status = \"disabled\"; ti,no-idle; ti,no-reset-on-init; ports { #address-cells = <0x1>; #size-cells = <0x0>; port@0 { reg = <0x0>; }; port@1 { reg = <0x1>; }; port@2 { reg = <0x2>; }; port@3 { reg = <0x3>; }; }; }; vip@0x489b0000 { compatible = \"ti,vip3\"; reg = <0x489b0000 0x114 0x489b5500 0xd8 0x489b5700 0x18 0x489b5800 0x80 0x489b5a00 0xd8 0x489b5c00 0x18 0x489b5d00 0x80 0x489bd000 0x400>; reg-names = \"vip\", \"parser0\", \"csc0\", \"sc0\", \"parser1\", \"csc1\", \"sc1\", \"vpdma\"; ti,hwmods = \"vip3\"; interrupts = <0x0 0x161 0x4 0x0 0x18a 0x4>; syscon-pol = <0x9 0x534>; #address-cells = <0x1>; #size-cells = <0x0>; status = \"disabled\"; ti,no-idle; ti,no-reset-on-init; ports { #address-cells = <0x1>; #size-cells = <0x0>; port@0 { reg = <0x0>; }; port@1 { reg = <0x1>; }; }; }; }; thermal-zones { cpu_thermal { polling-delay-passive = <0xfa>; polling-delay = <0x1f4>; thermal-sensors = <0xfa 0x0>; coefficients = <0x0 0x7d0>; trips { cpu_alert { temperature = <0x186a0>; hysteresis = <0x7d0>; type = \"passive\"; phandle = <0xfb>; }; cpu_crit { temperature = <0x1d4c0>; hysteresis = <0x7d0>; type = \"critical\"; }; }; cooling-maps { map0 { trip = <0xfb>; cooling-device = <0xfc 0xffffffff 0xffffffff>; }; }; }; gpu_thermal { polling-delay-passive = <0xfa>; polling-delay = <0x1f4>; thermal-sensors = <0xfa 0x1>; coefficients = <0x0 0x7d0>; trips { gpu_crit { temperature = <0x1d4c0>; hysteresis = <0x7d0>; type = \"critical\"; }; }; }; core_thermal { polling-delay-passive = <0xfa>; polling-delay = <0x1f4>; thermal-sensors = <0xfa 0x2>; coefficients = <0x0 0x7d0>; trips { core_crit { temperature = <0x1d4c0>; hysteresis = <0x7d0>; type = \"critical\"; }; }; }; dspeve_thermal { polling-delay-passive = <0xfa>; polling-delay = <0x1f4>; thermal-sensors = <0xfa 0x3>; coefficients = <0x0 0x7d0>; trips { dspeve_crit { temperature = <0x1d4c0>; hysteresis = <0x7d0>; type = \"critical\"; }; }; }; iva_thermal { polling-delay-passive = <0xfa>; polling-delay = <0x1f4>; thermal-sensors = <0xfa 0x4>; coefficients = <0x0 0x7d0>; trips { iva_crit { temperature = <0x1d4c0>; hysteresis = <0x7d0>; type = \"critical\"; }; }; }; }; pmu { compatible = \"arm,cortex-a15-pmu\"; interrupt-parent = <0x8>; interrupts = <0x0 0x83 0x4 0x0 0x84 0x4>; }; extcon_usb1 { compatible = \"linux,extcon-usb-gpio\"; id-gpio = <0xfd 0x1 0x0>; phandle = <0xda>; }; extcon_usb2 { compatible = \"linux,extcon-usb-gpio\"; id-gpio = <0xfd 0x2 0x0>; phandle = <0xdd>; }; sound0 { compatible = \"simple-audio-card\"; simple-audio-card,name = \"DRA7xx-EVM\"; simple-audio-card,widgets = \"Headphone\", \"Headphone Jack\", \"Line\", \"Line Out\", \"Microphone\", \"Mic Jack\", \"Line\", \"Line In\"; simple-audio-card,routing = \"Headphone Jack\", \"HPLOUT\", \"Headphone Jack\", \"HPROUT\", \"Line Out\", \"LLOUT\", \"Line Out\", \"RLOUT\", \"MIC3L\", \"Mic Jack\", \"MIC3R\", \"Mic Jack\", \"Mic Jack\", \"Mic Bias\", \"LINE1L\", \"Line In\", \"LINE1R\", \"Line In\"; simple-audio-card,format = \"dsp_b\"; simple-audio-card,bitclock-master = <0xfe>; simple-audio-card,frame-master = <0xfe>; simple-audio-card,bitclock-inversion; simple-audio-card,cpu { sound-dai = <0xff>; system-clock-frequency = <0x562200>; phandle = <0xfe>; }; simple-audio-card,codec { sound-dai = <0x100>; clocks = <0xe4>; }; }; leds { compatible = \"gpio-leds\"; led0 { label = \"dra7:usr1\"; gpios = <0x101 0x4 0x1>; default-state = \"off\"; }; led1 { label = \"dra7:usr2\"; gpios = <0x101 0x5 0x1>; default-state = \"off\"; }; led2 { label = \"dra7:usr3\"; gpios = <0x101 0x6 0x1>; default-state = \"off\"; }; led3 { label = \"dra7:usr4\"; gpios = <0x101 0x7 0x1>; default-state = \"off\"; }; }; gpio_keys { compatible = \"gpio-keys\"; #address-cells = <0x1>; #size-cells = <0x0>; autorepeat; USER1 { label = \"btnUser1\"; linux,code = <0x100>; gpios = <0x101 0x2 0x1>; }; USER2 { label = \"btnUser2\"; linux,code = <0x101>; gpios = <0x101 0x3 0x1>; }; }; clk_ov10633_fixed { #clock-cells = <0x0>; compatible = \"fixed-clock\"; clock-frequency = <0x16e3600>; phandle = <0xaa>; }; memory@0 { device_type = \"memory\"; reg = <0x0 0x80000000 0x0 0x80000000>; }; fixedregulator-evm_12v0 { compatible = \"regulator-fixed\"; regulator-name = \"evm_12v0\"; regulator-min-microvolt = <0xb71b00>; regulator-max-microvolt = <0xb71b00>; regulator-always-on; regulator-boot-on; phandle = <0x105>; }; fixedregulator-evm_1v8 { compatible = \"regulator-fixed\"; regulator-name = \"evm_1v8\"; vin-supply = <0x102>; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; phandle = <0xbb>; }; reserved-memory { #address-cells = <0x2>; #size-cells = <0x2>; ranges; ipu2-memory@95800000 { compatible = \"shared-dma-pool\"; reg = <0x0 0x9e000000 0x0 0x2000000>; reusable; status = \"okay\"; phandle = <0x99>; }; dsp1-memory@99000000 { compatible = \"shared-dma-pool\"; reg = <0x0 0xa1000000 0x0 0x2000000>; reusable; status = \"okay\"; phandle = <0x9e>; }; ipu1-memory@9d000000 { compatible = \"shared-dma-pool\"; reg = <0x0 0x9e000000 0x0 0x2000000>; reusable; status = \"disabled\"; phandle = <0x94>; }; dsp2-memory@9f000000 { compatible = \"shared-dma-pool\"; reg = <0x0 0xa3000000 0x0 0x2000000>; reusable; status = \"okay\"; phandle = <0xf9>; }; gpu-memory@c0000000 { compatible = \"shared-dma-pool\"; reg = <0x0 0xb0000000 0x0 0x4000000>; reusable; status = \"okay\"; phandle = <0xeb>; }; cmem@40300000 { compatible = \"shared-dma-pool\"; reg = <0x0 0x40300000 0x0 0x300000>; sram = <0x103>; no-map; status = \"okay\"; }; cmem@A9000000 { compatible = \"shared-dma-pool\"; reg = <0x0 0xa9000000 0x0 0x2000000>; no-map; status = \"okay\"; }; vsdk_sr1_mem@84000000 { compatible = \"shared-dma-pool\"; reg = <0x0 0x84000000 0x0 0x1a000000>; status = \"okay\"; }; vsdk_sr0_mem@A0000000 { compatible = \"shared-dma-pool\"; reg = <0x0 0xa0000000 0x0 0x1000000>; status = \"okay\"; }; vsdk_eve_mem@A5000000 { compatible = \"shared-dma-pool\"; reg = <0x0 0xa5000000 0x0 0x4000000>; status = \"okay\"; }; }; fixedregulator-sd { compatible = \"regulator-fixed\"; regulator-name = \"evm_3v3_sd\"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; enable-active-high; phandle = <0xae>; }; fixedregulator-evm_3v3_sw { compatible = \"regulator-fixed\"; regulator-name = \"evm_3v3_sw\"; vin-supply = <0x104>; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; phandle = <0xa8>; }; fixedregulator-aic_dvdd { compatible = \"regulator-fixed\"; regulator-name = \"aic_dvdd\"; vin-supply = <0xa8>; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; phandle = <0xa9>; }; fixedregulator-evm3v3 { compatible = \"regulator-fixed\"; regulator-name = \"evm_3v3\"; regulator-min-microvolt = <0x325aa0>; regulator-max-microvolt = <0x325aa0>; vin-supply = <0x105>; regulator-always-on; regulator-boot-on; }; fixedregulator-evm_5v0 { compatible = \"regulator-fixed\"; regulator-name = \"evm_5v0\"; regulator-min-microvolt = <0x4c4b40>; regulator-max-microvolt = <0x4c4b40>; vin-supply = <0x105>; regulator-always-on; regulator-boot-on; phandle = <0x106>; }; fixedregulator-evm_3v6 { compatible = \"regulator-fixed\"; regulator-name = \"evm_3v6\"; regulator-min-microvolt = <0x36ee80>; regulator-max-microvolt = <0x36ee80>; vin-supply = <0x106>; regulator-always-on; regulator-boot-on; phandle = <0xc4>; }; fixedregulator-mmcwl { compatible = \"regulator-fixed\"; regulator-name = \"vmmcwl_fixed\"; regulator-min-microvolt = <0x1b7740>; regulator-max-microvolt = <0x1b7740>; gpio = <0xa5 0x8 0x0>; startup-delay-us = <0x11170>; enable-active-high; phandle = <0xc5>; }; fixedregulator-vtt { compatible = \"regulator-fixed\"; regulator-name = \"vtt_fixed\"; regulator-min-microvolt = <0x149970>; regulator-max-microvolt = <0x149970>; regulator-always-on; regulator-boot-on; enable-active-high; vin-supply = <0x107>; gpio = <0x108 0xb 0x0>; }; connector@1 { compatible = \"hdmi-connector\"; label = \"hdmi\"; type = [61 00]; status = \"disabled\"; ti,no-idle; ti,no-reset-on-init; port { endpoint { remote-endpoint = <0x109>; phandle = <0x10f>; }; }; }; encoder@1 { compatible = \"ti,dra7evm-tpd12s015\"; pinctrl-names = \"i2c\", \"ddc\"; pinctrl-0 = <0x10a>; pinctrl-1 = <0x10b>; ddc-i2c-bus = <0x10c>; gpios = <0xab 0x4 0x0 0xab 0x5 0x0 0x108 0xc 0x0 0x10d 0x2 0x0>; ports { #address-cells = <0x1>; #size-cells = <0x0>; port@0 { reg = <0x0>; endpoint@0 { remote-endpoint = <0x10e>; phandle = <0xef>; }; }; port@1 { reg = <0x1>; endpoint@0 { remote-endpoint = <0x10f>; phandle = <0x109>; }; }; }; }; gpio_uart@1 { compatible = \"ti,dra7evm-gpio-uart\"; triger_uart_gpio = <0xa5 0xa 0x0>; interrupt-parent = <0xa5>; interrupts = <0xa 0x4>; }; };", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Keerthy J", | |
| "rankPoints" : "132000", | |
| "rankName" : "TI__Guru***", | |
| "date" : "", | |
| "userId" : "/members/1025801", | |
| "content" : "Hi, So TDA2 --> PC communication is working. The opposite is PC ---> TDA2 is not working. Can you check on the scope if anything is coming up on the RX line? - Keerthy", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "dsafdf dsfaf", | |
| "rankPoints" : "90", | |
| "rankName" : "Prodigy", | |
| "date" : "", | |
| "userId" : "/members/6393729", | |
| "content" : "of course data is transfering to RX line of uart2 of tda2x. So, can you have a try, use pc--->tda2x, can you read data from pc by uart2 ?????", | |
| "imageList" : null | |
| }, { | |
| "contentId" : "", | |
| "userName" : "Keerthy J", | |
| "rankPoints" : "132000", | |
| "rankName" : "TI__Guru***", | |
| "date" : "", | |
| "userId" : "/members/1025801", | |
| "content" : "Hello, dsafdf dsfaf said: is : when my tda2x's uart2 connect to external mcu,mcu send 12 bytes per 2 sends,but tda2xx cant read data correctly from uart2. sometimes lost data,sometimes wait for a long time to get data So i am not able to understand where is the problem. dsafdf dsfaf said: of course data is transfering to RX line of uart2 of tda2x Above is describing issues with RX right? - Keerthy", | |
| "imageList" : null | |
| } ], | |
| "tags" : [ ], | |
| "fourmType" : "processors-forum" | |
| } |