Ticket Name: TDA2SA: HDMI output to 1280x320 resolution LCD panel

Query Text:
Part Number: TDA2SA Other Parts Discussed in Thread: TDA2, TFP410, TFP401 Hi, I use my tda2xx custom board running vsdk3.07. Refer to the thread https://e2e.ti.com/support/processors-group/processors/f/processors-forum/726664/rtos-dra71-how-to-config-the-hdmi-resolution-1920-720 I have tested my HDMI output to 1920x720 panel, it display well. Now, I get a 1280x320 hdmi panel and want to use on my tda2 board. The panel module component is TFP401AP+LVDS83B+LCD, so i use hdmi cable connect it. After set the related clock,hsync,vsync, the panel display nothing but flickering. I afraid the parameters is wrong, I also validate the panel on the D3 tda3 rvp platform. On tda3 hdmi output, it can display. I know tda2 use the inside HDMI module and tda3 rvp use TFP410 output. Could you help me where might be wrong on tda2 board ? Thanks. Terry

Responses:
Hi Terry, Can you please make sure that timing parameter, sync polarity and pixel clock are matching as per the LCD's requirement? Yes, TDA2x has internal HDMI and since this is custom resolution, there isn't much change required.. If you don't start VENC, do you see anything on the LCD? Regards, Brijesh

Hi Brijesh, The settings are follow the LCD doc, I will check the signal later. Can you figure out where I can disable VENC if I use rtos or linux ? Terry

Hi Terry, VENC will be enabled on calling DISPLAYCTRL_LINK_CMD_SET_CONFIG control command in vision_sdk/apps/src/rtos/usecases/common/chains_common.c file. Regards, Brijesh

Hi Brijesh, 1. When I check the timing on TFP401, there is no hsync output, but pixel clock and vsync have. here is my setting in rtos:     else if(displayType == CHAINS_DISPLAY_TYPE_HDMI_1280x320)
    {
            pPrm->deviceId = DISPLAYCTRL_LINK_USE_HDMI;
            pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_HDMI;
            pVInfo->outputPort = SYSTEM_DCTRL_DSS_HDMI_OUTPUT;
            pVInfo->vencOutputInfo.vsPolarity       =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
            pVInfo->vencOutputInfo.hsPolarity       =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

            /* Below are of dont care for EVM LCD */
            pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
            pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

            pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
            pVInfo->vencOutputInfo.dvoFormat        =
                                        SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
            pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;

            pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
            pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;

            /* Configure overlay params */
            ovlyPrms->vencId                        = SYSTEM_DCTRL_DSS_VENC_HDMI;

            pVInfo->mInfo.standard     =  SYSTEM_STD_CUSTOM;
            pVInfo->mInfo.width      =  1280;
            pVInfo->mInfo.height     =  320;
            pVInfo->mInfo.scanFormat    =  SYSTEM_SF_PROGRESSIVE;
            pVInfo->mInfo.fps       =  60U;
            pVInfo->mInfo.pixelClock                =   31000U;
            pVInfo->mInfo.hFrontPorch               =   72U;
            pVInfo->mInfo.hBackPorch                =   87U;
            pVInfo->mInfo.hSyncLen                  =   1U;
            pVInfo->mInfo.vBackPorch                =   22U;
            pVInfo->mInfo.vFrontPorch               =   15U;
            pVInfo->mInfo.vSyncLen                  =   1U;
            pVInfo->vencDivisorInfo.divisorLCD  =  1;
            pVInfo->vencDivisorInfo.divisorPCD  =  1;
    } 2. if I disable DISPLAYCTRL_LINK_CMD_SET_CONFIG in chains_common.c like this, // status = System_linkControl(gChains_commonObj.displayCtrlLinkId, // DISPLAYCTRL_LINK_CMD_SET_CONFIG, // &gChains_commonObj.dctrlCfgPrms, // sizeof(DisplayCtrlLink_ConfigParams), // TRUE); // UTILS_assert(status == SYSTEM_LINK_STATUS_SOK); program will stop. [IPU1-0] 82.322454 s: dispcore/src/vpscore_dss.c @ Line 476: [IPU1-0] 82.322576 s: Display Controller registration failed for dss core instance 0 [IPU1-0] 82.322729 s: dispdrv/src/vpsdrv_displayCore.c @ Line 411: [IPU1-0] 82.322820 s: Dss core open failed!! [IPU1-0] 82.322881 s: dispdrv/src/vpsdrv_displayApi.c @ Line 348: [IPU1-0] 82.322973 s: Core open failed!! [IPU1-0] 82.323034 s: Assertion @ Line: 386 in displayLink_drv.c: pObj->displayHndl != NULL : failed !!! [IPU1-0] 82.323491 s: Assertion @ Line: 386 in displayLink_drv.c: pObj->displayHndl != NULL : failed !!! Regards, Terry

Hi Terry, Can you please update latest status on this thread? Please note HSync and VSync will only be enabled if VENC is running, ie calling DISPLAYCTRL_LINK_CMD_SET_CONFIG ioctl.. If we dont call this ioctl, we will not see HSync and Vsync toggling. Also we should not run the usecase in this case, because if VENC is not running, we cannot start the video pipeline.. Regards, Brijesh