Ticket Name: TDA2SX: Deserializer pattern generation Query Text: Part Number: TDA2SX Other Parts Discussed in Thread: TDA2, ALP, USB2ANY, DS90UB954-Q1 Hi all, We are working on tda2sx processor with our custom board. We have IMX390 sensor for road camera ADAS application. PFA block diagram of camera path and modules connected to SOC. We are facing an issue with road camera IMX390 , when we run road camera usecase we are receiving blue frames only. Please find the below consolidated information about the issue. 1) We were working with our earlier hardware prototype (B1) where this issue of all blue frames was seen at times, but it could be recovered from that state by ISP reset -> out of reset 2) In our current hardware Prototype (B2) this issue of blue frames is seen most of the times, and it is not recoverable by ISP reset -> out of reset sequence. The ISP is seen to be in Active State, with frame counts increasing almost ~30 FPS. 3) At the times when this blue frames issue is not seen, no frames are received at the output of ISP, and ISP is seen to be in fail-safe state. ISP reset -> out of reset sequence results in one of these two issue behaviours (No frames / Blue Frames) 4) While analysing this issue by comparing the hardware Schematics of B1 and B2 we realised that there was a change in Voltage level Shifter in ISP's I2C0 Path which was not being configured for proper usage, hence we updated our software to configure the same. 5) After all the software changes the behavior still remains to be the same. Usecase results in either blue frames issue or no frames issue [Point (2) and (3)]. 6) An experiments was done by connecting the Camera module (that contains IMX390 Sensor and UB953 Serializer) of B2 hardware to Main Module (that contains UB954 Deser, GW5200 ISP, and TDA2 Host) of B1 Hardware, and the behaviour was same as that of B1 [ i.e Blue frames issue seen but recovered with ISP reset -> Out of Reset Sequence]. Hence concluding that the cause of this issue is not in the camera module (i.e IMX390 Sensor and UB953 Serializer). 7) Another experiment was done by connecting the Camera module (that contains IMX390 Sensor and UB953 Serializer) of B1 hardware to Main Module (that contains UB954 Deser, GW5200 ISP, and TDA2 Host) of B2 Hardware, and the behaviour was same as that of B2 [ i.e Blue frames issue not recovered with ISP reset -> Out of Reset Sequence]. Thus supporting the conclusion from Point (6). 8) Full Rom data was read from ISP by reset to failsafe state and read binaries, and the data read from the ISP was identical with the ROM image written onto SNOR. Thus concluding that there is no issue w.r.t. SNOR flash memory. From Above experiments (6), (7) and (8) we have concluded that the modules IMX390 Sensor, UB953 Serializer and SNOR Flash have proper connections and configurations, and not causing the issue. Thus we are now suspecting the issue to be caused by the remaining modules (or their configurations/connections) in the Camera path viz, UB954 Deserializer, GW5200 ISP and TDA2 Host Processor. So, we have enabled the pattern generation for DESER to know whether there is any issue with DESER configuration. After enabling the DESER pattern generation we are not seeing any pattern on HDMI DISPLAY. only GREEN screen is observed.This experiment was done on both B1 and B2 prototypes, on both boards we observed only green screen. Below are the register settings what we did for DESER pattern gen. {0x58,0x40},//Enable the i2c pass through {0x20,0x30}, // disable video fwd {0x1F,0x02}, // csi operating speed {0x33,0x01}, // CSI0 enable {0xB0,0x00}, // Indirect Pattern Gen Registers {0xB1,0x01}, // PGEN_CTL {0xB2,0x01}, {0xB1,0x02}, // PGEN_CFG {0xB2,0x33}, {0xB1,0x03}, // PGEN_CSI_DI {0xB2,0x24}, {0xB1,0x04}, // PGEN_LINE_SIZE1 {0xB2,0x0F}, {0xB1,0x05}, // PGEN_LINE_SIZE0 {0xB2,0x00}, {0xB1,0x06}, // PGEN_BAR_SIZE1 {0xB2,0x01}, {0xB1,0x07}, // PGEN_BAR_SIZE0 {0xB2,0xE0}, {0xB1,0x08}, // PGEN_ACT_LPF1 {0xB2,0x02}, {0xB1,0x09}, // PGEN_ACT_LPF0 {0xB2,0xD0}, {0xB1,0x0A}, // PGEN_TOT_LPF1 {0xB2,0x04}, {0xB1,0x0B}, // PGEN_TOT_LPF0 {0xB2,0x1A}, {0xB1,0x0C}, // PGEN_LINE_PD1 {0xB2,0x0C}, {0xB1,0x0D}, // PGEN_LINE_PD0 {0xB2,0x67}, {0xB1,0x0E}, // PGEN_VBP {0xB2,0x21}, {0xB1,0x0F}, // PGEN_VFP {0xB2,0x0A}, Please let me know the above register settings are proper for DESER pattern generation. If above pattern GEN is correct, please tell me why we are receiving only green screen even after enabling the pattern gen. Please help us to solve this issue. This is a big blocker to us now. Thanks and Regards, A.Kavya Harini. Responses: This question is related to deserializer pattern generation. I will reassign it to FPD Link BU. Hello Alapati, Please provide all the detailed timing information for the video which you are trying to generate through PATGEN so we can review against your script. Another option is that 954 has a GUI to easily generate a PATGEN register configuration for you based on your video inputs. You can download the ALP GUI here (plus the profile updater which needs to be run), and then connect to the 954 in your system by using an I2C to use bridge - either Aardvark or USB2ANY. https://www.ti.com/tool/ALP Best Regards, Casey Hi Casey, 1. Our default Deserializer register settings are as follows: {0x4c, 0x01}, {0x33, 0x01}, // OnSemi (4-lane) 4Lane, non-continuous Clock {0x34, 0x41}, // csi-clk0 enable and periodic csi skew calibration. {0x20, 0x20}, // fwd ctl {0x21, 0x04}, // basic synchronous fwding {0x42, 0x71}, {FPD3_95X_DES_SER_ID,(BSPUTILS_SER_ID_ADDR_IMX390 << 1)}, {FPD3_95X_DES_SER_AL, (BSPUTILS_SER_ALIAS_ADDR_IMX390 << 1)}, {FPD3_95X_DES_SLAVE_ID0, (BSPUTILS_IMX390_ID_I2C_ADDR <<1)}, {FPD3_95X_DES_SLAVE_AL0, (BSPUTILS_IMX390_ALIAS_I2C_ADDR<<1)}, {0x6e, 0x88}, {0x58, 0x5E}, {0x6d, 0x40}, // STP cable for FPD {0xd5, 0xf0}, {0x25, 0x31}, {0x26, 0x01}, MIPI CSI-2 we are using 4 lanes 2. For Pattern generation we tried the below register settings {0x58,0x40}, {0x20,0x30}, // disable video fwd {0x1F,0x02}, // csi operating speed {0x33,0x01}, // CSI0 enable {0xB0,0x00}, // Indirect Pattern Gen Registers {0xB1,0x01}, // PGEN_CTL {0xB2,0x01}, {0xB1,0x02}, // PGEN_CFG {0xB2,0x33}, {0xB1,0x03}, // PGEN_CSI_DI {0xB2,0x24}, {0xB1,0x04}, // PGEN_LINE_SIZE1 {0xB2,0x0F}, {0xB1,0x05}, // PGEN_LINE_SIZE0 {0xB2,0x00}, {0xB1,0x06}, // PGEN_BAR_SIZE1 {0xB2,0x01}, {0xB1,0x07}, // PGEN_BAR_SIZE0 {0xB2,0xE0}, {0xB1,0x08}, // PGEN_ACT_LPF1 {0xB2,0x02}, {0xB1,0x09}, // PGEN_ACT_LPF0 {0xB2,0xD0}, {0xB1,0x0A}, // PGEN_TOT_LPF1 {0xB2,0x04}, {0xB1,0x0B}, // PGEN_TOT_LPF0 {0xB2,0x1A}, {0xB1,0x0C}, // PGEN_LINE_PD1 {0xB2,0x0C}, {0xB1,0x0D}, // PGEN_LINE_PD0 {0xB2,0x67}, {0xB1,0x0E}, // PGEN_VBP {0xB2,0x21}, {0xB1,0x0F}, // PGEN_VFP {0xB2,0x0A}, we are not receiving frames with the shared pattern generation code.We suspect that the ISP is not processing the frames because deserializer is generating the pattern generation. so, the Image sensor is not reachable over I2C bus. Hence we need this below configuration.. 1) Serializer and Sensor Accessible through the FPD link with appropriate I2C addresses. 2) Deserializer to be ignoring the frames received from Sensor. 3) The Deserializer to be producing pattern generation frames in MIPI output. Thanks & Regards, A.Kavya Harini. Hello Alapati, Ok, but the question I asked was what are the specific video parameters which you are trying to configure the pattern generator for? Please provide the video timing your ISP is expecting, otherwise we can not review your PATGEN code against the expected configuration for your application. Best Regards, Casey Hi Casey, Sorry for the inconvenience Below are the details of video parameters. hActive: 1920 vActive: 1080 fps : 30 bitdepth : 20 Interface : 4 Lane Mipi Is this data sufficient ? This is the information we have as of now. Please let me know if you want any other details. Thanks & Regards, A.Kavya Harini Hi Casey, We tried the below register configuration for our requirement [1920x1080 RAW20 @ 30FPS over 4 lane MIPI at 800 MBPS] {0x20,0x30}, // disable video fwd {0x1F,0x02}, // csi operating speed {0x33,0x01}, // CSI0 enable {0xB0,0x00}, // Indirect Pattern Gen Registers {0xB1,0x01}, // PGEN_CTL {0xB2,0x01}, {0xB1,0x02}, // PGEN_CFG {0xB2,0x33}, {0xB1,0x03}, // PGEN_CSI_DI {0xB2,0x2F}, // RAW20 {0xB1,0x04}, // PGEN_LINE_SIZE1 {0xB2,0x12}, {0xB1,0x05}, // PGEN_LINE_SIZE0 {0xB2,0xC0}, // 1920 pixels of 20 bits each = 1920 * 20 /8 {0xB1,0x06}, // PGEN_BAR_SIZE1 {0xB2,0x02}, {0xB1,0x07}, // PGEN_BAR_SIZE0 {0xB2,0x58}, // Dividing Line size into 8 parts. {0xB1,0x08}, // PGEN_ACT_LPF1 {0xB2,0x04}, {0xB1,0x09}, // PGEN_ACT_LPF0 {0xB2,0x38}, // 1080 Active lines per frame {0xB1,0x0A}, // PGEN_TOT_LPF1 {0xB2,0x04}, {0xB1,0x0B}, // PGEN_TOT_LPF0 {0xB2,0x65}, // 1125 Total lines per frame {0xB1,0x0C}, // PGEN_LINE_PD1 {0xB2,0x0B}, {0xB1,0x0D}, // PGEN_LINE_PD0 {0xB2,0x92}, // 29.62 us assuming 30FPS with 1125 total lines per frame {0xB1,0x0E}, // PGEN_VBP {0xB2,0x24}, // Back Porch = 36 lines {0xB1,0x0F}, // PGEN_VFP {0xB2,0x09}, // Front porch = 9 lines {0xB1,0x10}, // PGEN_COLOR0 {0xB2,0xFF}, {0xB1,0x11}, // PGEN_COLOR1 {0xB2,0x00}, {0xB1,0x12}, // PGEN_COLOR2 {0xB2,0xEE}, {0xB1,0x13}, // PGEN_COLOR3 {0xB2,0x11}, {0xB1,0x14}, // PGEN_COLOR4 {0xB2,0xDD}, {0xB1,0x15}, // PGEN_COLOR5 {0xB2,0x22}, {0xB1,0x16}, // PGEN_COLOR6 {0xB2,0xCC}, {0xB1,0x17}, // PGEN_COLOR7 {0xB2,0x33} And we received 3 frames at the SoC. However the frames appear to be corrupted/incorrect. Attached the frame captures. Can you please check the above configuration settings and correct if anything is wrong. Frame_captures.zip PS: The BackPorch and Front Porch are set taking the ISP -> Host parallel video settings as reference. Please let us know if anything needs to be changed. Thanks & Regards, A.Kavya Harini. Hello Alapati, Your PATGEN config has an invalid vertical total since it does not include any lines for vertical sync. The vertical total is VACTIVE + VFP + VSYNC + VBP Right now you have VACTIVE = 1080 VFP = 9 VBP = 36 VTOTAL = 1125 Which means there are no lines left for the VSYNC. What is the expected VSYNC width for the video in your pipeline? Best Regards, Casey Hi Casey, Thanks for your inputs, we did not contain the information about front porch. We had the information as VTotal=1125, VActive=1080, VBackPorch=36, and VSync=5 Hence we had tried the experiment with VFP=9, VFP=5, and VFP=4, and got the same behaviour in all 3 cases. Thanks & Regards, A.Kavya Harini. Hello Alapati, You have all the info needed to extract VFP from the above. (Vtotal - VBP - Vsync - Vactive) = VFP = 4 lines Can you try the following? Register Data Name 0x01 0x01 PGEN_CTL 0x02 0xB5 PGEN_CFG 0x03 0x2F PGEN_CSI_DI 0x04 0x12 PGEN_LINE_SIZE1 0x05 0xC0 PGEN_LINE_SIZE0 0x06 0x02 PGEN_BAR_SIZE1 0x07 0x58 PGEN_BAR_SIZE0 0x08 0x04 PGEN_ACT_LPF1 0x09 0x38 PGEN_ACT_LPF0 0x0A 0x04 PGEN_TOT_LPF1 0x0B 0x69 PGEN_TOT_LPF0 0x0C 0x0B PGEN_LINE_PD1 0x0D 0x88 PGEN_LINE_PD0 0x0E 0x24 PGEN_VBP 0x0F 0x09 PGEN_VFP 0x10 0xAA PGEN_COLOR0 0x11 0x33 PGEN_COLOR1 0x12 0xF0 PGEN_COLOR2 0x13 0x7F PGEN_COLOR3 0x14 0x55 PGEN_COLOR4 0x15 0xCC PGEN_COLOR5 0x16 0x0F PGEN_COLOR6 0x17 0x80 PGEN_COLOR7 0x18 0x00 PGEN_COLOR8 0x19 0x00 PGEN_COLOR9 0x1A 0x00 PGEN_COLOR10 0x1B 0x00 PGEN_COLOR11 0x1C 0x00 PGEN_COLOR12 0x1D 0x00 PGEN_COLOR13 0x1E 0x00 PGEN_COLOR14 Best Regards, Casey Hi Casey, Thanks for the reply, We tried the register settings suggested by you. Still we are receiving 3 frames which I have posted in my last mail. The issue is same. Please let us know how to proceed further. Thanks and Regards, A.Kavya Harini. Hi Casey, One update, After setting the total line size for 2200 pixels instead of 1920 (account for horizontal front and back porch) we are able to get the pattern generation output.But it is always seen as grey scale image. Thanks & Regards, A.Kavya Harini Hello Alapati, I don't understand your last comment. There is no total horizontal line size setting in the pattern generator. Only total vertical since the CSI-2 transmitter does not send discrete horizontal sync timing. Please post again your most updated code and I will take a look Best Regards, Casey Hi Casey, We are able to generate and view the video frames with pattern generation with the below configuration: {0xB1,0x01},{0xB2, 0x01}, //PGEN_CTL {0xB1,0x02},{0xB2, 0xB5}, //PGEN_CFG {0xB1,0x03},{0xB2, 0x2F}, //PGEN_CSI_DI {0xB1,0x04},{0xB2, 0x15}, //PGEN_LINE_SIZE1 /* HTotal = 2200 pixels; Line size = 2200 * 20 bits per pixel / 8 */ {0xB1,0x05},{0xB2, 0x7C}, //PGEN_LINE_SIZE0 {0xB1,0x06},{0xB2, 0x02}, //PGEN_BAR_SIZE1 {0xB1,0x07},{0xB2, 0x58}, //PGEN_BAR_SIZE0 {0xB1,0x08},{0xB2, 0x04}, //PGEN_ACT_LPF1 /* Active lines per frame = 1080 */ {0xB1,0x09},{0xB2, 0x38}, //PGEN_ACT_LPF0 {0xB1,0x0A},{0xB2, 0x04}, //PGEN_TOT_LPF1 /* Total lines per frame = 1130 */ {0xB1,0x0B},{0xB2, 0x6A}, //PGEN_TOT_LPF0 {0xB1,0x0C},{0xB2, 0x0B}, //PGEN_LINE_PD1 {0xB1,0x0D},{0xB2, 0x88}, //PGEN_LINE_PD0 {0xB1,0x0E},{0xB2, 0x24}, //PGEN_VBP /* Back Porch = 36 lines */ {0xB1,0x0F},{0xB2, 0x09}, //PGEN_VFP /* Front porch = 9 lines */ Main change that worked seemed to be with respect to PGEN_LINE_SIZE as we were considering only the HActive size instead of HTotal. Please find the received frame attached. The frames received however are all greyscale, can you provide any inputs to obtain colour frames in RAW20 mode by setting the PGEN_COLOR registers? Thanks & Regards, A.Kavya Harini Hello Alapati, This configuration doesn't make sense. The PGEN_LINE_SIZE is not controlling the Htotal. It is controlling Hactive so it should be set based on 1920 active pixels. RAW20 CSI-2 uses a 5 bytes per 2 pixels format, so the PGEN_LINE_SIZE should be 1920*(5/2) = 4800dec = 0x12C0 I suspect that this in combination with the way the data is being received and processed is giving you these strange results. Somehow your frame height is showing 1090 instead of 1080. Next, for color bars, I would suggest using the color bar pattern setting instead of fixed color pattern (0x02[7] = 0) Please try the following settings: Register Data Name 0x01 0x01 PGEN_CTL 0x02 0x35 PGEN_CFG 0x03 0x2F PGEN_CSI_DI 0x04 0x12 PGEN_LINE_SIZE1 0x05 0xC0 PGEN_LINE_SIZE0 0x06 0x02 PGEN_BAR_SIZE1 0x07 0x58 PGEN_BAR_SIZE0 0x08 0x04 PGEN_ACT_LPF1 0x09 0x38 PGEN_ACT_LPF0 0x0A 0x04 PGEN_TOT_LPF1 0x0B 0x6A PGEN_TOT_LPF0 0x0C 0x0B PGEN_LINE_PD1 0x0D 0x86 PGEN_LINE_PD0 0x0E 0x24 PGEN_VBP 0x0F 0x09 PGEN_VFP 0x10 0xAA PGEN_COLOR0 0x11 0x33 PGEN_COLOR1 0x12 0xF0 PGEN_COLOR2 0x13 0x7F PGEN_COLOR3 0x14 0x55 PGEN_COLOR4 0x15 0xCC PGEN_COLOR5 0x16 0x0F PGEN_COLOR6 0x17 0x80 PGEN_COLOR7 0x18 0x00 PGEN_COLOR8 0x19 0x00 PGEN_COLOR9 0x1A 0x00 PGEN_COLOR10 0x1B 0x00 PGEN_COLOR11 0x1C 0x00 PGEN_COLOR12 0x1D 0x00 PGEN_COLOR13 0x1E 0x00 PGEN_COLOR14 The colors can be adjusted by changing the PGEN_COLOR_x registers above. Please note you can iterate on these configurations easily using the Analog LaunchPad GUI software in demo mode. There is a PATGEN configuration tab which can generate all these registers. I would recommend downloading that here so you can give it a try - make sure to download and run the profile updater tool: https://www.ti.com/tool/ALP Best Regards, Casey Hi Casey, Even for the above set of configurations in your previous mail, we are seeing only 3 frames. Thanks for the reference to the ALP tool, we are able to use that and generate the register configuration. However, we need one clarity about the PGEN_LINE_SIZE Registers. If the Line size is supposed to be taken based on hActive pixels, where can the parameters hSyncWidth, hBackPorch, hFrontPorch, hTotal be configured. Because in our case the ISP does expect horizontal Back and front porching. Here are the parameters hActive + hSyncWidth + hBackPorch + hFrontPorch = hTotal 1920 + 44 + 148 + 88 = 2200 Please let us know if any other configuration can be done to account for these parameters. We assume that if sufficient bytes of data corresponding to hTotal is not received per line, then ISP might have some undefined behaviour. That was the reason why we tried to populate the PGEN_LINE_SIZE by taking pixels per line as hTotal instead of hActive. Please confirm/correct our understanding. Thanks and Regards, A.Kavya Harini Hello Alapati, DS90UB954-Q1 does not convey discrete DPI timing for horizontal parameters. This is optional in the CSI-2 standard and it is not implemented in our CSI-2 pattern generator (nor most CSI-2 solutions on the market). So basically the 954 will send the active line pixels at a fixed rate (in this case you have configured 800Mbps/lane), and then will transition to LP11 to wait until the next active line start. During horizontal blanking it does not send HSS/HSE packets to define DPI timing for HFP/HSYNC/HBP. The time between end of active line and start of next active line is not determined based on pixels. It is based on the line time, number of lines, and the transmitter output rate. So if you configure 1.6Gbps/lane, then each line will be sent twice as fast and then the transmitter will sit in LP11 for double the time waiting for the next active line. If you configure the transmitter for 2200 in PGEN_LINE_SIZE, but only capture a 1920 pixel image, then part of the pixels are going to be cut off since the transmitter is actually sending a 2200 active pixel line Best Regards, Casey