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sum limits_ x 1 99 frac 1 x x 1 __________________ | Summation | 180 |
Let P sum_ substack 1 le i le 2k i odd i and Q sum_ substack 1 le i le 2k i even i where k is a positive integer Then P Q k P Q k P Q P Q 2k | Summation | 180 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Choose the correct alternatives more than one may be correct and write the corresponding letters only Advantage of synchronous sequential circuits over asynchronous ones is faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above | Synchronous Asynchronous Circuits | 181 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Consider the circuit given below with initial state Q_0 1 Q_1 Q_2 0 The state of the circuit is given by the value 4Q_2 2Q_1 Q_0 Which one of the following is correct state sequence of the circuit 1 3 4 6 7 5 2 1 2 5 3 7 6 4 1 2 7 3 5 6 4 1 6 5 7 2 3 4 | Synchronous Circuit | 182 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
Design a synchronous counter to go through the following states 1 4 2 3 1 4 2 3 1 4 dots | Synchronous Counter | 183 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
System calls are usually invoked by using a software interrupt polling an indirect jump a privileged instruction | System Calls | 184 |
Consider the following set of equations x 2y 5 4x 8y 12 3x 6y 3z 15 This set has unique solution has no solution has finite number of solutions has infinite number of solutions | System Of Equations | 185 |
What values of x y and z satisfy the following system of linear equations begin bmatrix 1 amp 2 amp 3 1 amp 3 amp 4 2 amp 2 amp 3 end bmatrix begin bmatrix x y z end bmatrix begin bmatrix 6 8 12 end bmatrix x 6 y 3 z 2 x 12 y 3 z 4 x 6 y 6 z 4 x 12 y 3 z 0 | System Of Equations | 185 |
If the following system has non trivial solution u00a0 px qy rz 0 qx ry pz 0 rx py qz 0 then which one of the following options is TRUE u00a0 p q r 0 ext or p q r p q r 0 ext or p q r p q r 0 ext or p q r p q r 0 ext or p q r | System Of Equations | 185 |
Consider the following system of linear equations left begin array ccc 2 amp 1 amp 4 4 amp 3 amp 12 1 amp 2 amp 8 end array right left begin array ccc x y z end array right left begin array ccc alpha 5 7 end array right Notice that the second and the third columns of the coefficient matrix are linearly dependent For how many values of alpha does this system of equations have infinitely many solutions 0 1 2 3 | System Of Equations | 185 |
The three way handshake for TCP connection establishment is shown below Which of the following statements are TRUE S1 Loss of SYN ACK from the server will not establish a connection S2 Loss of ACK from the client cannot establish the connection S3 The server moves LISTEN u2192 SYN_RCVD u2192 SYN_SENT u2192 ESTABLISHED in the state machine on no packet loss S4 The server moves LISTEN u2192 SYN_RCVD u2192 ESTABLISHED in the state machine on no packet loss S 2 and S 3 only S 1 and S 4 only S 1 and S 3 only S 2 and S 4 only | Tcp | 186 |
Consider the following statements TCP connections are full duplex TCP has no option for selective acknowledgement TCP connections are message streams Only I is correct Only I and III are correct Only II and III are correct All of I II and III are correct | Tcp | 186 |
Assume that the bandwidth for a TCP connection is 1048560 bits sec Let alpha be the value of RTT in milliseconds rounded off to the nearest integer after which the TCP window scale option is needed Let beta be the maximum possible window size with window scale option Then the values of alpha and beta are 63 milliseconds 65535 imes 2 14 63 milliseconds 65535 imes 2 16 500 milliseconds 65535 imes 2 14 500 milliseconds 65535 imes 2 16 | Tcp | 186 |
Consider the following statements about the timeout value used in TCP The timeout value is set to the RTT Round Trip Time measured during TCP connection establishment for the entire duration of the connection Appropriate RTT estimation algorithm is used to set the timeout value of a TCP connection Timeout value is set to twice the propagation delay from the sender to the receiver Which of the following choices hold i is false but ii and iii are true i and iii are false but ii is title i and ii are false but iii is true i ii and iii are false | Tcp | 186 |
Consider a TCP client and a TCP server running on two different machines After completing data transfer the TCP client calls close to terminate the connection and a FIN segment is sent to the TCP server Server side TCP responds by sending an ACK which is received by the client side TCP As per the TCP connection state diagram RFC 793 in which state does the client side TCP connection wait for the FIN from the server side TCP LAST ACK TIME WAIT FIN WAIT 1 FIN WAIT 2 | Tcp | 186 |
Assume that the bandwidth for a TCP connection is 1048560 bits sec Let alpha be the value of RTT in milliseconds rounded off to the nearest integer after which the TCP window scale option is needed Let beta be the maximum possible window size with window scale option Then the values of alpha and beta are 63 milliseconds 65535 imes 2 14 63 milliseconds 65535 imes 2 16 500 milliseconds 65535 imes 2 14 500 milliseconds 65535 imes 2 16 | Tcp | 186 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
After Rajendra Chola returned from his voyage to Indonesia he ________ to visit the temple in Thanjavur was wishing is wishing wished had wished | Tenses | 187 |
Threads of a process share global variables but not heap heap but not global variables neither global variables nor heap both heap and global variables | Threads | 188 |
A thread is usually defined as a light weight process because an Operating System OS maintains smaller data structure for a thread than for a process In relation to this which of the following statement is correct OS maintains only scheduling and accounting information for each thread OS maintains only CPU registers for each thread OS does not maintain virtual memory state for each thread OS does not maintain a separate stack for each thread | Threads | 188 |
A thread is usually defined as a light weight process because an Operating System OS maintains smaller data structure for a thread than for a process In relation to this which of the following statement is correct OS maintains only scheduling and accounting information for each thread OS maintains only CPU registers for each thread OS does not maintain virtual memory state for each thread OS does not maintain a separate stack for each thread | Threads | 188 |
Consider the following statements with respect to user level threads and kernel supported threads context switch is faster with kernel supported threads for user level threads a system call can block the entire process Kernel supported threads can be scheduled independently User level threads are transparent to the kernel Which of the above statements are true II III and IV only II and III only I and III only I and II only | Threads | 188 |
Consider the following statements with respect to user level threads and kernel supported threads context switch is faster with kernel supported threads for user level threads a system call can block the entire process Kernel supported threads can be scheduled independently User level threads are transparent to the kernel Which of the above statements are true II III and IV only II and III only I and III only I and II only | Threads | 188 |
Consider the following statements with respect to user level threads and kernel supported threads context switch is faster with kernel supported threads for user level threads a system call can block the entire process Kernel supported threads can be scheduled independently User level threads are transparent to the kernel Which of the above statements are true II III and IV only II and III only I and III only I and II only | Threads | 188 |
Consider the following statements with respect to user level threads and kernel supported threads context switch is faster with kernel supported threads for user level threads a system call can block the entire process Kernel supported threads can be scheduled independently User level threads are transparent to the kernel Which of the above statements are true II III and IV only II and III only I and III only I and II only | Threads | 188 |
Consider the following statements about user level threads and kernel level threads Which one of the following statements is FALSE Context switch time is longer for kernel level threads than for user level threads User level threads do not need any hardware support Related kernel level threads can be scheduled on different processors in a multi processor system Blocking one kernel level thread blocks all related threads | Threads | 188 |
A thread is usually defined as a light weight process because an Operating System OS maintains smaller data structure for a thread than for a process In relation to this which of the following statement is correct OS maintains only scheduling and accounting information for each thread OS maintains only CPU registers for each thread OS does not maintain virtual memory state for each thread OS does not maintain a separate stack for each thread | Threads | 188 |
A thread is usually defined as a light weight process because an Operating System OS maintains smaller data structure for a thread than for a process In relation to this which of the following statement is correct OS maintains only scheduling and accounting information for each thread OS maintains only CPU registers for each thread OS does not maintain virtual memory state for each thread OS does not maintain a separate stack for each thread | Threads | 188 |
Consider the following statements with respect to user level threads and kernel supported threads context switch is faster with kernel supported threads for user level threads a system call can block the entire process Kernel supported threads can be scheduled independently User level threads are transparent to the kernel Which of the above statements are true II III and IV only II and III only I and III only I and II only | Threads | 188 |
In a database system unique timestamps are assigned to each transaction using Lamport s logical clock Let TS T_ 1 and TS T_ 2 be the timestamps of transactions T_ 1 and T_ 2 respectively Besides T_ 1 holds a lock on the resource R and T_ 2 has requested a conflicting lock on the same resource R The following algorithm is used to prevent deadlocks in the database system assuming that a killed transaction is restarted with the same timestamp if TS T_ 2 lt TS T_ 1 then T_ 1 is killed else T_ 2 waits Assume any transaction that is not killed terminates eventually Which of the following is TRUE about the database system that uses the above algorithm to prevent deadlocks The database system is both deadlock free and starvation free The database system is deadlock free but not starvation free The database system is starvation free but not deadlock free The database system is neither deadlock free nor starvation free | Timestamp Ordering | 189 |
In a database system unique timestamps are assigned to each transaction using Lamport s logical clock Let TS T_ 1 and TS T_ 2 be the timestamps of transactions T_ 1 and T_ 2 respectively Besides T_ 1 holds a lock on the resource R and T_ 2 has requested a conflicting lock on the same resource R The following algorithm is used to prevent deadlocks in the database system assuming that a killed transaction is restarted with the same timestamp if TS T_ 2 lt TS T_ 1 then T_ 1 is killed else T_ 2 waits Assume any transaction that is not killed terminates eventually Which of the following is TRUE about the database system that uses the above algorithm to prevent deadlocks The database system is both deadlock free and starvation free The database system is deadlock free but not starvation free The database system is starvation free but not deadlock free The database system is neither deadlock free nor starvation free | Timestamp Ordering | 189 |
In a database system unique timestamps are assigned to each transaction using Lamport s logical clock Let TS T_ 1 and TS T_ 2 be the timestamps of transactions T_ 1 and T_ 2 respectively Besides T_ 1 holds a lock on the resource R and T_ 2 has requested a conflicting lock on the same resource R The following algorithm is used to prevent deadlocks in the database system assuming that a killed transaction is restarted with the same timestamp if TS T_ 2 lt TS T_ 1 then T_ 1 is killed else T_ 2 waits Assume any transaction that is not killed terminates eventually Which of the following is TRUE about the database system that uses the above algorithm to prevent deadlocks The database system is both deadlock free and starvation free The database system is deadlock free but not starvation free The database system is starvation free but not deadlock free The database system is neither deadlock free nor starvation free | Timestamp Ordering | 189 |
In a database system unique timestamps are assigned to each transaction using Lamport s logical clock Let TS T_ 1 and TS T_ 2 be the timestamps of transactions T_ 1 and T_ 2 respectively Besides T_ 1 holds a lock on the resource R and T_ 2 has requested a conflicting lock on the same resource R The following algorithm is used to prevent deadlocks in the database system assuming that a killed transaction is restarted with the same timestamp if TS T_ 2 lt TS T_ 1 then T_ 1 is killed else T_ 2 waits Assume any transaction that is not killed terminates eventually Which of the following is TRUE about the database system that uses the above algorithm to prevent deadlocks The database system is both deadlock free and starvation free The database system is deadlock free but not starvation free The database system is starvation free but not deadlock free The database system is neither deadlock free nor starvation free | Timestamp Ordering | 189 |
In a database system unique timestamps are assigned to each transaction using Lamport s logical clock Let TS T_ 1 and TS T_ 2 be the timestamps of transactions T_ 1 and T_ 2 respectively Besides T_ 1 holds a lock on the resource R and T_ 2 has requested a conflicting lock on the same resource R The following algorithm is used to prevent deadlocks in the database system assuming that a killed transaction is restarted with the same timestamp if TS T_ 2 lt TS T_ 1 then T_ 1 is killed else T_ 2 waits Assume any transaction that is not killed terminates eventually Which of the following is TRUE about the database system that uses the above algorithm to prevent deadlocks The database system is both deadlock free and starvation free The database system is deadlock free but not starvation free The database system is starvation free but not deadlock free The database system is neither deadlock free nor starvation free | Timestamp Ordering | 189 |
In a database system unique timestamps are assigned to each transaction using Lamport s logical clock Let TS T_ 1 and TS T_ 2 be the timestamps of transactions T_ 1 and T_ 2 respectively Besides T_ 1 holds a lock on the resource R and T_ 2 has requested a conflicting lock on the same resource R The following algorithm is used to prevent deadlocks in the database system assuming that a killed transaction is restarted with the same timestamp if TS T_ 2 lt TS T_ 1 then T_ 1 is killed else T_ 2 waits Assume any transaction that is not killed terminates eventually Which of the following is TRUE about the database system that uses the above algorithm to prevent deadlocks The database system is both deadlock free and starvation free The database system is deadlock free but not starvation free The database system is starvation free but not deadlock free The database system is neither deadlock free nor starvation free | Timestamp Ordering | 189 |
In a database system unique timestamps are assigned to each transaction using Lamport s logical clock Let TS T_ 1 and TS T_ 2 be the timestamps of transactions T_ 1 and T_ 2 respectively Besides T_ 1 holds a lock on the resource R and T_ 2 has requested a conflicting lock on the same resource R The following algorithm is used to prevent deadlocks in the database system assuming that a killed transaction is restarted with the same timestamp if TS T_ 2 lt TS T_ 1 then T_ 1 is killed else T_ 2 waits Assume any transaction that is not killed terminates eventually Which of the following is TRUE about the database system that uses the above algorithm to prevent deadlocks The database system is both deadlock free and starvation free The database system is deadlock free but not starvation free The database system is starvation free but not deadlock free The database system is neither deadlock free nor starvation free | Timestamp Ordering | 189 |
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