repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
AleChir/Digital_Filter_VHDL | Digital_Filter/regn_std_logic.vhd | 1 | 664 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY regn_std_logic IS
GENERIC ( N : integer:=8);
PORT ( R: IN std_logic_vector(N-1 DOWNTO 0);
Clock, Resetn, enable : IN STD_LOGIC;
Q: OUT std_logic_vector(N-1 DOWNTO 0));
END regn_std_logic;
Architecture Behavior OF regn_std_logic IS
BEGIN
PROCESS (Clock, Resetn)
BEGIN
IF (Resetn = '0') THEN
Q <= (OTHERS => '0');
ELSIF (Clock'EVENT AND Clock = '1') THEN
IF(enable='1') then
Q <= R;
end IF;
END IF;
END PROCESS;
END Behavior; | gpl-3.0 | ddb26d2f92dff8145bfad6c2831a0662 | 0.52259 | 3.648352 | false | false | false | false |
imr/Mandelbrot-VHDL | src/Math.vhd | 1 | 2,046 | -- Ian Roth
-- ECE 8455
-- pipelined Mandelbrot Set, final project
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
USE work.fixed_pkg.all;
ENTITY Math IS
PORT(
clk, rst :IN STD_LOGIC;
x_const, y_const :IN STD_LOGIC_VECTOR(35 downto 0);
result :OUT STD_LOGIC_VECTOR(15 downto 0)
);
END ENTITY Math;
ARCHITECTURE Behavior of Math IS
TYPE fixed_array IS ARRAY(23 downto 0) OF sfixed(3 downto -32);
TYPE unsigned_array IS ARRAY(23 downto 0) OF UNSIGNED(15 downto 0);
SIGNAL x_array, y_array, x_const_array, y_const_array :fixed_array;
SIGNAL result_array :unsigned_array;
SIGNAL done_array :STD_LOGIC_VECTOR(23 downto 0);
CONSTANT fixed_zero :sfixed(3 downto -32) := X"000000000";
COMPONENT Mandelbrot
PORT(
x_const, y_const :IN sfixed(3 downto -32);
x_in, y_in :IN sfixed(3 downto -32);
iteration_in :IN unsigned(15 downto 0);
done_in, clk, rst :IN STD_LOGIC;
x_const_out, y_const_out :OUT sfixed(3 downto -32);
x_out, y_out :OUT sfixed(3 downto -32);
iteration_out :OUT unsigned(15 downto 0);
done_out :OUT STD_LOGIC
);
END COMPONENT;
BEGIN
result <= STD_LOGIC_VECTOR(result_array(23));
stage0: Mandelbrot PORT MAP(x_const => to_sfixed(x_const, 3, -32), y_const => to_sfixed(y_const, 3, -32),
x_in => fixed_zero, y_in => fixed_zero, iteration_in => X"0000",
done_in => '0', clk => clk, rst => rst, x_const_out => x_const_array(0),
y_const_out => y_const_array(0), x_out => x_array(0),
y_out => y_array(0), iteration_out => result_array(0), done_out => done_array(0));
gen_math:
FOR i IN 1 TO 23 GENERATE
stageX: Mandelbrot PORT MAP(x_const => x_const_array(i-1), y_const => y_const_array(i-1),
x_in => x_array(i-1), y_in => y_array(i-1), iteration_in => result_array(i-1),
done_in => done_array(i-1), clk => clk, rst => rst, x_const_out => x_const_array(i),
y_const_out => y_const_array(i), x_out => x_array(i),
y_out => y_array(i), iteration_out => result_array(i), done_out => done_array(i));
END GENERATE gen_math;
END Behavior; | bsd-3-clause | b44575a00bd896aff05d35cfb40ca144 | 0.659335 | 2.606369 | false | false | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/Divider_2x16.vhd | 1 | 1,444 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Divider_2x16 is
Port (
input_A, input_B : in STD_LOGIC_VECTOR (15 downto 0);
outputLow, outputHigh : out STD_LOGIC_VECTOR (15 downto 0);
carryOut : out STD_LOGIC);
end Divider_2x16;
architecture skeleton of Divider_2x16 is
begin
process(input_A, input_B)
variable inte, rest, howMuch : std_logic_vector (15 downto 0);
variable carry: std_logic;
function shiter (number : std_logic_vector(15 downto 0)) return std_logic_vector is
variable TMP : std_logic_vector(15 downto 0);
begin
for i in 14 downto 0 loop
TMP(i + 1) := number(i);
end loop;
TMP(0) := '0';
return TMP;
end shiter;
begin
carry:='0';
if(input_B = "0000000000000000") then
outputHigh <= "0000000000000000";
outputLow <= "0000000000000000";
howMuch := "0000000000000001";
else
rest := "0000000000000000";
inte := "0000000000000000";
for i in 15 downto 0 loop
rest := shiter(rest);
rest(0) := input_A(i);
if(rest >= input_B) then
rest := rest - input_B;
inte(i) := '1';
end if;
end loop;
outputHigh <= rest;
outputLow <= inte;
end if;
carryOut <= '0';
end process;
end skeleton;
| gpl-3.0 | f851e7c90307ce8be9fad29084cad8c1 | 0.583795 | 3.230425 | false | false | false | false |
terpstra/opa | opa_pbus.vhd | 1 | 9,044 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_pbus is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
p_cyc_o : out std_logic;
p_stb_o : out std_logic;
p_we_o : out std_logic;
p_stall_i : in std_logic;
p_ack_i : in std_logic;
p_err_i : in std_logic;
p_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
p_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
p_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
p_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- L1d requests action
l1d_stall_o : out std_logic; -- stall has an async dep on addr
l1d_req_i : in std_logic;
l1d_we_i : in std_logic;
l1d_addr_i : in std_logic_vector(f_opa_adr_wide(g_config) -1 downto 0);
l1d_sel_i : in std_logic_vector(f_opa_reg_wide(g_config)/8-1 downto 0);
l1d_dat_i : in std_logic_vector(f_opa_reg_wide(g_config) -1 downto 0);
l1d_pop_i : in std_logic;
l1d_full_o : out std_logic;
l1d_err_o : out std_logic;
l1d_dat_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end opa_pbus;
architecture rtl of opa_pbus is
constant c_page_size : natural := f_opa_page_size(g_isa);
constant c_adr_wide : natural := f_opa_adr_wide(g_config);
constant c_reg_wide : natural := f_opa_reg_wide(g_config);
constant c_sel_wide : natural := c_reg_wide/8;
constant c_fifo_wide : natural := c_adr_wide + c_sel_wide + c_reg_wide;
constant c_fifo_deep : natural := 4;
constant c_device_align : natural := f_opa_log2(c_page_size);
signal s_stall : std_logic; -- We can accept the op on l1d_addr_i
signal s_push : std_logic; -- L1d delivers req into FIFO (and possibly reg)
signal s_exist : std_logic; -- There exists data to be sent
signal s_full : std_logic; -- full regs were not drained by pbus
signal s_pop : std_logic; -- regs have accepted data from L1d or FIFO
signal s_fin : std_logic; -- pbus completed IO
signal s_widx : unsigned(c_fifo_deep-1 downto 0);
signal s_ridx : unsigned(c_fifo_deep-1 downto 0);
signal s_fidx : unsigned(c_fifo_deep-1 downto 0);
signal s_fifo_in : std_logic_vector(c_fifo_wide-1 downto 0);
signal s_fifo_out: std_logic_vector(c_fifo_wide-1 downto 0);
signal r_widx : unsigned(c_fifo_deep-1 downto 0) := (others => '0');
signal r_ridx : unsigned(c_fifo_deep-1 downto 0) := (others => '0');
signal r_fidx : unsigned(c_fifo_deep-1 downto 0) := (others => '0');
signal r_stall : std_logic := '0';
signal r_cyc : std_logic := '0';
signal r_stb : std_logic := '0';
-- This cannot go into FIFO because we must tap it twice
signal r_we_q : std_logic_vector(2**c_fifo_deep-1 downto 0);
signal r_we : std_logic;
signal r_adr : std_logic_vector(c_adr_wide -1 downto 0);
signal r_sel : std_logic_vector(c_reg_wide/8-1 downto 0);
signal r_dat : std_logic_vector(c_reg_wide -1 downto 0);
signal r_lock : std_logic := '0'; -- !!! set somewhere in a CSR or so
signal r_full : std_logic := '0';
signal r_err : std_logic;
signal r_que : std_logic_vector(c_reg_wide-1 downto 0);
begin
check : process(clk_i) is
begin
if rising_edge(clk_i) then
assert (f_opa_safe(l1d_req_i) = '1') report "pbus: l1d_req_i has a metavalue" severity failure;
assert (f_opa_safe(l1d_pop_i) = '1') report "pbus: l1d_req_i has a metavalue" severity failure;
-- Internal state
assert (f_opa_safe(r_full) = '1') report "pbus: r_full has a metavalue" severity failure;
assert (f_opa_safe(r_ridx) = '1') report "pbus: r_ridx has a metavalue" severity failure;
assert (f_opa_safe(r_widx) = '1') report "pbus: r_widx has a metavalue" severity failure;
assert (f_opa_safe(r_fidx) = '1') report "pbus: r_fidx has a metavalue" severity failure;
end if;
end process;
-- We accept requests into the same wishbone cycle if they are within the same device
-- OR the user has explicitly requested the cycle line stay up (r_lock).
s_stall <=
r_stall or not
(r_lock or not r_cyc or f_opa_eq(r_adr(r_adr'high downto c_device_align), l1d_addr_i(r_adr'high downto c_device_align)));
s_push <= l1d_req_i and not s_stall;
s_full <= r_stb and p_stall_i;
s_exist <= not f_opa_eq(r_widx, r_ridx) or s_push;
s_pop <= not s_full and s_exist;
s_fin <= r_cyc and (p_ack_i or p_err_i);
l1d_stall_o <= s_stall;
p_cyc_o <= r_cyc;
p_stb_o <= r_stb;
p_we_o <= r_we;
p_sel_o <= r_sel;
p_data_o <= r_dat;
p_addr_o(p_addr_o'high downto r_adr'high) <= (others => r_adr(r_adr'high));
p_addr_o(r_adr'high-1 downto 0) <= std_logic_vector(r_adr(r_adr'high-1 downto 0));
-- !!! Consider setting g_regin=false and r_addr_i to r_ridx; ie: async read memory
fifo_out : opa_dpram
generic map(
g_width => c_fifo_wide,
g_size => 2**c_fifo_deep,
g_equal => OPA_NEW,
g_regin => true,
g_regout => false)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
r_addr_i => std_logic_vector(s_ridx),
r_data_o => s_fifo_out,
w_en_i => '1',
w_addr_i => std_logic_vector(r_widx),
w_data_i => s_fifo_in);
s_widx <= r_widx + ("" & s_push);
s_ridx <= r_ridx + ("" & s_pop);
s_fidx <= r_fidx + ("" & s_fin);
s_fifo_in <= l1d_addr_i & l1d_sel_i & l1d_dat_i;
main : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_ridx <= (others => '0');
r_widx <= (others => '0');
r_fidx <= (others => '0');
r_stall <= '0';
r_cyc <= '0';
r_stb <= '0';
elsif rising_edge(clk_i) then
r_ridx <= s_ridx;
r_widx <= s_widx;
r_fidx <= s_fidx;
r_stall <= not f_opa_lt(r_widx - r_fidx, 2**c_fifo_deep-2);
r_cyc <= not f_opa_eq(s_widx, s_fidx) or r_lock;
r_stb <= s_exist or s_full;
end if;
end process;
we : process(clk_i) is
begin
if rising_edge(clk_i) then
r_we_q(to_integer(unsigned(r_widx))) <= l1d_we_i;
end if;
end process;
pbus : process(clk_i) is
begin
if rising_edge(clk_i) then
if s_pop = '1' then
if r_ridx = r_widx then
r_we <= l1d_we_i;
r_adr <= l1d_addr_i;
r_sel <= l1d_sel_i;
r_dat <= l1d_dat_i;
else
r_we <= r_we_q(to_integer(unsigned(r_ridx)));
r_adr <= s_fifo_out(s_fifo_out'high downto s_fifo_out'high-c_adr_wide+1);
r_sel <= s_fifo_out(c_reg_wide/8*9-1 downto c_reg_wide);
r_dat <= s_fifo_out(c_reg_wide-1 downto 0);
end if;
end if;
end if;
end process;
-- !!! add a FIFO just like the above once we have prefetch => high throughput loads
l1d_full_o <= r_full;
l1d_err_o <= r_err;
l1d_dat_o <= r_que;
qmain : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_full <= '0';
elsif rising_edge(clk_i) then
r_full <= (r_full and not l1d_pop_i) or (s_fin and not r_we_q(to_integer(unsigned(r_fidx))));
end if;
end process;
qbus : process(clk_i) is
begin
if rising_edge(clk_i) then
if r_full = '0' then
r_que <= p_data_i;
r_err <= p_err_i;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | f5c1a2ab85c0f4f11c685031c9132da8 | 0.600066 | 2.783626 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/tb_wrapper_complex_abs.vhd | 1 | 3,209 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 12:35:04
-- Design Name:
-- Module Name: tb_wrapper_complex_abs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_wrapper_complex_abs is
end tb_wrapper_complex_abs;
architecture Behavioral of tb_wrapper_complex_abs is
component wrapper_complex_abs is
Generic ( complex_width : natural := 32 );
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
complex_value : in STD_LOGIC_VECTOR (complex_width-1 downto 0);
complex_value_out :out STD_LOGIC_VECTOR(complex_width-1 downto 0);
abs_value : out STD_LOGIC_VECTOR (complex_width-1 downto 0);
valid_out : out STD_LOGIC;
valid_in : in STD_LOGIC;
ready_out : out STD_LOGIC;
ready_in : in STD_LOGIC);
end component wrapper_complex_abs;
--Constants
constant clock_period : time := 10 ns;
constant complex_width : natural := 32;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '1';
signal complex_value : std_logic_vector(complex_width-1 downto 0) := (others => '0');
signal valid_in : std_logic := '0';
signal ready_in : std_logic := '0';
--Outputs
signal abs_value : std_logic_vector(complex_width-1 downto 0);
signal valid_out: std_logic := '0';
signal ready_out : std_logic := '0';
signal complex_value_out : STD_LOGIC_VECTOR(complex_width-1 downto 0);
begin
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
uut : wrapper_complex_abs
port map(
clock => clock,
reset_n => reset_n,
complex_value => complex_value,
complex_value_out => complex_value_out,
abs_value => abs_value,
valid_out => valid_out,
valid_in => valid_in,
ready_out => ready_out,
ready_in => ready_in);
stim_proc: process
begin
reset_n <= '0';
wait for 100 ns;
reset_n <='1';
complex_value <= x"00010001";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 50;
ready_in <= '1';
valid_in <= '0';
wait for clock_period;
complex_value <= x"00020002";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 50;
ready_in <= '1';
valid_in <= '0';
wait for clock_period;
complex_value <= x"00030003";
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 50;
ready_in <= '1';
valid_in <= '0';
wait;
end process;
end Behavioral;
| gpl-2.0 | 9ee791fa76cd73610e2eb5d7b86bc45b | 0.588345 | 3.569522 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/moltiplicatore_booth/parte_controllo.vhd | 1 | 3,464 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:36:01 11/23/2015
-- Design Name:
-- Module Name: parte_controllo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity parte_controllo is
generic ( n : natural := 4;
m : natural := 4);
Port ( clock : in STD_LOGIC;
reset_n_all : in STD_LOGIC;
q0 : in STD_LOGIC;
q_1 : in STD_LOGIC;
enable : in STD_LOGIC;
conteggio : in STD_LOGIC;
load_a : out STD_LOGIC;
load_m : out STD_LOGIC;
load_q : out STD_LOGIC;
reset_n : out STD_LOGIC;
shift : out STD_LOGIC;
sub : out STD_LOGIC;
count_en : out STD_LOGIC;
done : out STD_LOGIC);
end parte_controllo;
architecture Behavioral of parte_controllo is
type state is (reset, init, scan, add, subtract, rshift, output, load);
signal current_state, next_state : state := reset;
begin
registro_stato : process(clock, reset_n_all)
begin
if(reset_n_all = '0') then
current_state <= reset;
elsif(clock = '1' and clock'event) then
current_state <= next_state;
end if;
end process;
f_stato_prossimo : process(current_state, reset_n_all, q0, q_1, enable, conteggio)
begin
case current_state is
when reset =>
if(enable = '1') then
next_state <= init;
else
next_state <= reset;
end if;
when init =>
next_state <= scan;
when scan =>
if(conteggio = '0') then
if(q0 = q_1) then
next_state <= rshift;
elsif(q0 = '0') then
next_state <= add;
elsif(q0 = '1') then
next_state <= subtract;
end if;
else
next_state <= output;
end if;
when add =>
next_state <= load;
when subtract =>
next_state <= load;
when rshift =>
next_state <= scan;
when output =>
next_state <= output;
when load =>
-- Stato fittizio incluso per far commutare l'uscita sh_out in maniera corretta
-- non so xkè ma questa si aggiorna un ciclo di clock dopo l'op di add o sub
next_state <= rshift;
end case;
end process;
f_uscita : process(current_state) --MOORE
begin
load_a <= '0';
load_m <= '0';
load_q <= '0';
reset_n <= '1';
shift <= '0';
sub <= '0';
count_en <= '0';
done <= '0';
case current_state is
when reset =>
reset_n <= '0';
when init =>
load_m <= '1';
load_q <= '1';
when scan =>
when add =>
load_a <= '1';
when subtract =>
load_a <= '1';
sub <= '1';
when rshift =>
shift <= '1';
count_en <= '1';
when output =>
done <= '1';
when load =>
end case;
end process;
end Behavioral;
| gpl-2.0 | ea0213a865492a16c59f20d0c0277f0f | 0.524401 | 3.368677 | false | false | false | false |
terpstra/opa | opa_prefixsum.vhd | 1 | 14,751 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_prefixsum is
generic(
g_target : t_opa_target;
g_width : natural;
g_count : natural);
port(
bits_i : in std_logic_vector(g_width-1 downto 0);
count_o : out t_opa_matrix(g_count-1 downto 0, g_width-1 downto 0);
total_o : out std_logic_vector(g_width-1 downto 0));
end opa_prefixsum;
architecture rtl of opa_prefixsum is
constant c_width : natural := g_width;
constant c_lut_wide : natural := g_target.lut_width;
constant c_num_lut : natural := 2**c_lut_wide;
constant c_max_wide : natural := 3; -- If you increase this, duplicate code below
constant c_max_units : natural := 2**c_max_wide-1;
-- Thank VHDL's restriction on flexible array sub-types for this duplication:
type t_lut_romb is array(c_num_lut-1 downto 0) of std_logic_vector(c_max_wide-1 downto 0);
type t_lut_romu is array(c_num_lut-1 downto 0) of std_logic_vector(c_max_units downto 0);
function f_matrix_to_romb(x : t_opa_matrix) return t_lut_romb is
variable result : t_lut_romb := (others => (others => '0'));
begin
for i in x'range(1) loop
for j in x'range(2) loop
result(i)(j) := x(i,j);
end loop;
end loop;
return result;
end f_matrix_to_romb;
function f_matrix_to_romu(x : t_opa_matrix) return t_lut_romu is
variable result : t_lut_romu;
begin
for i in x'range(1) loop
for j in x'range(2) loop
result(i)(j) := x(i,j);
end loop;
end loop;
return result;
end f_matrix_to_romu;
-- Directly decode the final result to 1-hot
function f_decode_table(num_unit : natural; table : t_lut_romb) return t_opa_matrix is
variable result : t_opa_matrix(c_num_lut-1 downto 0, c_max_units downto 0) := (others => (others => '0'));
variable row : unsigned(c_max_wide-1 downto 0);
begin
for i in result'range(1) loop
row := unsigned(table(i));
for b in 0 to num_unit-1 loop
result(i, b) := f_opa_bit(row = to_unsigned(b, row'length));
end loop;
result(i, num_unit) := f_opa_lt(row, num_unit);
end loop;
return result;
end f_decode_table;
---------------------------------------------------------------------------------------
-- Count the # of ones, saturated up to the specified bits
function f_compress_table(bits : natural) return t_opa_matrix is
variable result : t_opa_matrix(c_num_lut-1 downto 0, c_max_wide-1 downto 0) := (others => (others => '0'));
variable input : unsigned(c_lut_wide-1 downto 0);
variable count : unsigned(bits-1 downto 0);
constant ones : unsigned(bits-1 downto 0) := (others => '1');
begin
for i in result'range(1) loop
input := to_unsigned(i, input'length);
count := (others => '0');
for j in input'range loop
if count /= ones and input(j) = '1' then
count := count + 1;
end if;
end loop;
for b in 0 to bits-1 loop
result(i,b) := count(b);
end loop;
end loop;
return result;
end f_compress_table;
constant c_compress_rom3 : t_lut_romb := f_matrix_to_romb(f_compress_table(3));
constant c_compress_rom2 : t_lut_romb := f_matrix_to_romb(f_compress_table(2));
constant c_compress_rom1 : t_lut_romb := f_matrix_to_romb(f_compress_table(1));
constant c_compress_decode_rom7 : t_lut_romu := f_matrix_to_romu(f_decode_table(7, c_compress_rom3));
constant c_compress_decode_rom6 : t_lut_romu := f_matrix_to_romu(f_decode_table(6, c_compress_rom3));
constant c_compress_decode_rom5 : t_lut_romu := f_matrix_to_romu(f_decode_table(5, c_compress_rom3));
constant c_compress_decode_rom4 : t_lut_romu := f_matrix_to_romu(f_decode_table(4, c_compress_rom3));
constant c_compress_decode_rom3 : t_lut_romu := f_matrix_to_romu(f_decode_table(3, c_compress_rom2));
constant c_compress_decode_rom2 : t_lut_romu := f_matrix_to_romu(f_decode_table(2, c_compress_rom2));
constant c_compress_decode_rom1 : t_lut_romu := f_matrix_to_romu(f_decode_table(1, c_compress_rom1));
function f_compress(bits : natural; x : std_logic_vector) return std_logic_vector is
constant bad : std_logic_vector(c_max_wide-1 downto 0) := (others => 'X');
begin
if f_opa_safe(x) = '1' then
assert (bits >= 1 and bits <= c_max_wide) report "unsupported bit width" severity failure;
if bits = 3 then return c_compress_rom3(to_integer(unsigned(x))); end if;
if bits = 2 then return c_compress_rom2(to_integer(unsigned(x))); end if;
if bits = 1 then return c_compress_rom1(to_integer(unsigned(x))); end if;
end if;
return bad;
end f_compress;
function f_compress_decode(num_unit : natural; x : std_logic_vector) return std_logic_vector is
constant bad : std_logic_vector(c_max_units downto 0) := (others => 'X');
begin
if f_opa_safe(x) = '1' then
assert (num_unit >= 1 and num_unit <= c_max_units) report "unsupported unit count" severity failure;
if num_unit = 7 then return c_compress_decode_rom7(to_integer(unsigned(x))); end if;
if num_unit = 6 then return c_compress_decode_rom6(to_integer(unsigned(x))); end if;
if num_unit = 5 then return c_compress_decode_rom5(to_integer(unsigned(x))); end if;
if num_unit = 4 then return c_compress_decode_rom4(to_integer(unsigned(x))); end if;
if num_unit = 3 then return c_compress_decode_rom3(to_integer(unsigned(x))); end if;
if num_unit = 2 then return c_compress_decode_rom2(to_integer(unsigned(x))); end if;
if num_unit = 1 then return c_compress_decode_rom1(to_integer(unsigned(x))); end if;
end if;
return bad;
end f_compress_decode;
---------------------------------------------------------------------------------------
-- Combine subproblem sums
function f_combine_table(bits : natural) return t_opa_matrix is
constant c_parts : natural := c_lut_wide/bits;
variable result : t_opa_matrix(c_num_lut-1 downto 0, c_max_wide-1 downto 0) := (others => (others => '0'));
variable shf : integer;
variable sum : integer;
variable bin : unsigned(bits-1 downto 0);
begin
for i in result'range(1) loop
-- Determine the sum of the fields
sum := 0;
shf := i;
for j in 0 to c_parts-1 loop
sum := sum + (shf mod 2**bits);
shf := shf / 2**bits;
end loop;
-- Saturate the arithmetic and convert to unsigned
if sum >= 2**bits then sum := 2**bits-1; end if;
bin := to_unsigned(sum, bits);
-- Split result into LUT tables
for b in 0 to bits-1 loop
result(i,b) := bin(b);
end loop;
end loop;
return result;
end f_combine_table;
constant c_combine_rom3 : t_lut_romb := f_matrix_to_romb(f_combine_table(3));
constant c_combine_rom2 : t_lut_romb := f_matrix_to_romb(f_combine_table(2));
constant c_combine_rom1 : t_lut_romb := f_matrix_to_romb(f_combine_table(1));
constant c_combine_decode_rom7 : t_lut_romu := f_matrix_to_romu(f_decode_table(7, c_combine_rom3));
constant c_combine_decode_rom6 : t_lut_romu := f_matrix_to_romu(f_decode_table(6, c_combine_rom3));
constant c_combine_decode_rom5 : t_lut_romu := f_matrix_to_romu(f_decode_table(5, c_combine_rom3));
constant c_combine_decode_rom4 : t_lut_romu := f_matrix_to_romu(f_decode_table(4, c_combine_rom3));
constant c_combine_decode_rom3 : t_lut_romu := f_matrix_to_romu(f_decode_table(3, c_combine_rom2));
constant c_combine_decode_rom2 : t_lut_romu := f_matrix_to_romu(f_decode_table(2, c_combine_rom2));
constant c_combine_decode_rom1 : t_lut_romu := f_matrix_to_romu(f_decode_table(1, c_combine_rom1));
function f_combine(bits : natural; x : std_logic_vector) return std_logic_vector is
constant bad : std_logic_vector(c_max_wide-1 downto 0) := (others => 'X');
begin
if f_opa_safe(x) = '1' then
assert (bits >= 1 and bits <= c_max_wide) report "unsupported bit width" severity failure;
if bits = 3 then return c_combine_rom3(to_integer(unsigned(x))); end if;
if bits = 2 then return c_combine_rom2(to_integer(unsigned(x))); end if;
if bits = 1 then return c_combine_rom1(to_integer(unsigned(x))); end if;
end if;
return bad;
end f_combine;
function f_combine_decode(num_unit : natural; x : std_logic_vector) return std_logic_vector is
constant bad : std_logic_vector(c_max_units downto 0) := (others => 'X');
begin
if f_opa_safe(x) = '1' then
assert (num_unit >= 1 and num_unit <= c_max_units) report "unsupported unit count" severity failure;
if num_unit = 7 then return c_combine_decode_rom7(to_integer(unsigned(x))); end if;
if num_unit = 6 then return c_combine_decode_rom6(to_integer(unsigned(x))); end if;
if num_unit = 5 then return c_combine_decode_rom5(to_integer(unsigned(x))); end if;
if num_unit = 4 then return c_combine_decode_rom4(to_integer(unsigned(x))); end if;
if num_unit = 3 then return c_combine_decode_rom3(to_integer(unsigned(x))); end if;
if num_unit = 2 then return c_combine_decode_rom2(to_integer(unsigned(x))); end if;
if num_unit = 1 then return c_combine_decode_rom1(to_integer(unsigned(x))); end if;
end if;
return bad;
end f_combine_decode;
---------------------------------------------------------------------------------------
function f_satadd_step(num_unit : natural; step : natural; x : t_opa_matrix) return t_opa_matrix is
constant c_bits : natural := f_opa_log2(num_unit+1);
constant c_parts : natural := c_lut_wide/c_bits;
variable chunk : std_logic_vector(c_lut_wide-1 downto 0);
variable row : std_logic_vector(c_max_wide-1 downto 0);
variable unit : std_logic_vector(c_max_units downto 0);
variable recurse : t_opa_matrix(x'range(1), c_max_wide-1 downto 0) := (others => (others => '0'));
variable result : t_opa_matrix(x'range(1), c_max_units downto 0) := (others => (others => '0'));
begin
assert (step < x'length(1)) report "incorrect invocation" severity failure;
for i in x'range(1) loop
chunk := (others => '0');
for j in 0 to c_parts-1 loop
if i - j*step >= x'low(1) then
for b in 0 to c_bits-1 loop
chunk(j*c_bits+b) := x(i-j*step,b);
end loop;
end if;
end loop;
row := f_combine(c_bits, chunk);
unit := f_combine_decode(num_unit, chunk);
for b in row'range loop
recurse(i, b) := row(b);
end loop;
for b in unit'range loop
result(i, b) := unit(b);
end loop;
end loop;
if c_parts*step >= x'length(1) then
return result;
else
return f_satadd_step(num_unit, c_parts*step, recurse);
end if;
end f_satadd_step;
function f_satadd(num_unit : natural; x : std_logic_vector) return t_opa_matrix is
constant c_bits : natural := f_opa_log2(num_unit+1);
variable chunk : std_logic_vector(c_lut_wide-1 downto 0);
variable row : std_logic_vector(c_max_wide-1 downto 0);
variable unit : std_logic_vector(c_max_units downto 0);
variable recurse : t_opa_matrix(x'range(1), c_max_wide-1 downto 0) := (others => (others => '0'));
variable result : t_opa_matrix(x'range(1), c_max_units downto 0) := (others => (others => '0'));
begin
for i in x'range(1) loop
chunk := (others => '0');
for j in 0 to c_lut_wide-1 loop
if i-j >= x'low then
chunk(j) := x(i-j);
end if;
end loop;
row := f_compress(c_bits, chunk);
unit := f_compress_decode(num_unit, chunk);
for b in row'range loop
recurse(i, b) := row(b);
end loop;
for b in unit'range loop
result(i, b) := unit(b);
end loop;
end loop;
if c_lut_wide >= x'length(1) then
return result;
else
return f_satadd_step(num_unit, c_lut_wide, recurse);
end if;
end f_satadd;
function f_shift(x : t_opa_matrix) return t_opa_matrix is
variable result : t_opa_matrix(x'range(1), x'range(2));
begin
for i in x'range(1) loop
for j in x'range(2) loop
if i = x'low(1) then
result(i,j) := f_opa_bit(j = 0 or j = g_count);
else
result(i,j) := x(i-1,j);
end if;
end loop;
end loop;
return result;
end f_shift;
---------------------------------------------------------------------------------------
signal s_bits : std_logic_vector(bits_i'range);
signal s_sum : t_opa_matrix(bits_i'range, c_max_units downto 0);
begin
check_width :
assert (g_count <= c_max_units)
report "More units of a single type than supported"
severity failure;
-- Stop synthesis tools from breaking the circuit I built
-- The issue critical path was carefully hand-crafted
pending : for i in bits_i'range generate
lcell : opa_lcell
port map(
a_i => bits_i(i),
b_o => s_bits(i));
end generate;
s_sum <= f_shift(f_satadd(g_count, s_bits));
bits : for b in bits_i'range generate
total_o(b) <= s_sum(b, g_count);
count : for u in count_o'range(1) generate
count_o(u,b) <= s_sum(b,u);
end generate;
end generate;
end rtl;
| gpl-3.0 | 3b402a9df4009dfdf585dd2fbef7a24a | 0.620433 | 3.15125 | false | false | false | false |
freecores/grain | src/VHDL/test_synth/hw3_grain128.vhd | 1 | 840 | --
-- synthesis test 3:
-- * with clock enable
-- * fast
--
--
-- Altera EP2C-8, Quartus 8.0: 286 LEs,0 bits mem, fmax = 295 MHz (320 requested)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw3_grain128 is
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw3_grain128 is
begin
top: entity work.grain128
generic map (
DEBUG => false,
FAST => true
)
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 | b909440ec19bead2a5d6c8331c210814 | 0.619048 | 2.463343 | false | false | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/Demultiplexer_4x1.vhd | 1 | 1,759 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Demultiplexer_4x1 is
Port ( Selector : in STD_LOGIC_VECTOR(3 downto 0);
input: in STD_LOGIC;
output_A, output_B, output_C, output_D, output_E, output_F, output_G, output_H : out STD_LOGIC;
output_I, output_J, output_K, output_L, output_M, output_N, output_O, output_P : out STD_LOGIC);
end Demultiplexer_4x1;
architecture skeleton of Demultiplexer_4x1 is
begin
with Selector select
output_A <= input when "0000",
'0' when others;
with Selector select
output_B <= input when "0001",
'0' when others;
with Selector select
output_C <= input when "0010",
'0' when others;
with Selector select
output_D <= input when "0011",
'0' when others;
with Selector select
output_E <= input when "0100",
'0' when others;
with Selector select
output_F <= input when "0101",
'0' when others;
with Selector select
output_G <= input when "0110",
'0' when others;
with Selector select
output_H <= input when "0111",
'0' when others;
with Selector select
output_I <= input when "1000",
'0' when others;
with Selector select
output_J <= input when "1001",
'0' when others;
with Selector select
output_K <= input when "1010",
'0' when others;
with Selector select
output_L <= input when "1011",
'0' when others;
with Selector select
output_M <= input when "1100",
'0' when others;
with Selector select
output_N <= input when "1101",
'0' when others;
with Selector select
output_O <= input when "1110",
'0' when others;
with Selector select
output_P <= input when "1111",
'0' when others;
end skeleton; | gpl-3.0 | fd6dee68540c11894c423583f8c36d73 | 0.625924 | 3.129893 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/complex_abs.vhd | 1 | 5,472 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:14:52 06/26/2017
-- Design Name:
-- Module Name: complex_abs - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--! @file complex_abs.vhd
--! @author Antonio Riccio, Andrea Scognamiglio, Stefano Sorrentino
--! @brief Blocco che calcola il modulo di un numero complesso
--! @example tb_complex_abs.vhd
--! @anchor complex_abs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--! @brief Componente che calcola il modulo di un numero complesso
--! @details Il valore complesso deve essere fornito nel seguente modo:
--! - prima metà: parte immaginaria
--! - seconda metà: parte reale
--!
--! @note Il componente non applica la formula completa per il calcolo del modulo
--! ma trascura l'operazione di radice quadrata perchè non necessaria ai fini
--! dell'applicazione che utilizzerà questo componente.
entity complex_abs is
Generic ( complex_width : natural := 32 ); --! Parallelismo in bit del numero complesso (inteso come somma di parte reale e immaginaria)
Port ( clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
enable : in STD_LOGIC; --! Segnale di abilitazione
complex_value : in STD_LOGIC_VECTOR (complex_width-1 downto 0); --! Numero complesso di cui calcolare il modulo
abs_value : out STD_LOGIC_VECTOR (complex_width-1 downto 0); --! Modulo del numero complesso
done : out STD_LOGIC); --! Segnale di terminazione delle operazioni
end complex_abs;
--! @brief Architettura del componente descritta nel dominio strutturale
--! @details L'archittettura fa riuso di componenti utilizzati per altri progetti
architecture Structural of complex_abs is
--! Moltiplicatore di Booth
component moltiplicatore_booth
generic (
n : natural := 4;
m : natural := 4
);
port (
A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (m-1 downto 0);
enable : in STD_LOGIC;
reset_n : in STD_LOGIC;
clock : in STD_LOGIC;
done : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (n+m-1 downto 0)
);
end component moltiplicatore_booth;
--! Addzionatore ripple carry
component ripple_carry_adder
generic (
n : natural := 4
);
port (
A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
c_in : in STD_LOGIC;
c_out : out STD_LOGIC;
ovfl : out STD_LOGIC;
S : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end component ripple_carry_adder;
--! Automa a stati per controllare i segnali dei moltiplicatori
component parte_controllo_complex_abs
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
enable : in STD_LOGIC;
done_mul : in STD_LOGIC;
reset_n_all : out STD_LOGIC;
enable_mul : out STD_LOGIC;
done : out STD_LOGIC
);
end component parte_controllo_complex_abs;
signal en_mul_sig, done_real_sig, done_imag_sig, done_mul_sig, reset_n_all_sig : std_logic;
--! Prodotto della parte reale con se stessa (equivalente al quadrato della parte reale)
signal power_real_sig : std_logic_vector(complex_width-1 downto 0);
--! Prodotto della parte immaginaria con se stessa (equivalente al quadrato della parte immaginaria)
signal power_imag_sig : std_logic_vector(complex_width-1 downto 0);
--! Risultato della somma dei quadrati
signal res_add_sig : std_logic_vector(complex_width-1 downto 0);
begin
done_mul_sig <= done_real_sig and done_imag_sig;
--! Effettua il quadrato della parte reale
multiplier_real : moltiplicatore_booth
generic map (
n => (complex_width)/2,
m => (complex_width)/2
)
port map (
A => complex_value((complex_width/2)-1 downto 0),
B => complex_value((complex_width/2)-1 downto 0),
enable => en_mul_sig,
reset_n => reset_n_all_sig,
clock => clock,
done => done_real_sig,
P => power_real_sig
);
--! Effettua il quadrato della parte immaginaria
multiplier_imag : moltiplicatore_booth
generic map (
n => (complex_width)/2,
m => (complex_width)/2
)
port map (
A => complex_value(complex_width-1 downto complex_width/2),
B => complex_value(complex_width-1 downto complex_width/2),
enable => en_mul_sig,
reset_n => reset_n_all_sig,
clock => clock,
done => done_imag_sig,
P => power_imag_sig
);
--! Somma i quadrati di parte reale ed immaginaria
mul_results_add : ripple_carry_adder
generic map (
n => complex_width
)
port map (
A => power_real_sig,
B => power_imag_sig,
c_in => '0',
c_out => open,
ovfl => open,
S => abs_value
);
--! Controlla i segnali di controllo dei moltiplicatori
control_unit : parte_controllo_complex_abs
port map (
clock => clock,
reset_n => reset_n,
enable => enable,
done_mul => done_mul_sig,
reset_n_all => reset_n_all_sig,
enable_mul => en_mul_sig,
done => done
);
end Structural;
| gpl-2.0 | d0334596c0d31ecf29f3ec01e346b2d5 | 0.65417 | 3.22977 | false | false | false | false |
AleChir/Digital_Filter_VHDL | Digital_Filter/control_unit.vhd | 1 | 4,094 | library ieee;
use ieee.std_logic_1164.all;
entity control_unit is
port ( module: out std_logic;
cntrl: out std_logic;
enable_sum: out std_logic;
enable_shift: out std_logic;
clock: in std_logic;
rst_shift: out std_logic;
cs_a,cs_b,wr_rd_a,wr_rd_b: out std_logic;
finished: out std_logic;
rst_count: out std_logic;
up_count: out std_logic;
start: in std_logic;
rst_sum: out std_logic;
mux1_sel: out std_logic_vector(2 downto 0);
reset: in std_logic;
exceed: in std_logic );
end control_unit;
architecture Behaviour of control_unit is
type states is (idle,write_a,reset_for_sums,read_a,sample_shift,op_0,op_1,op_2,op_3,op_4,sample_sum,write_b,done);
signal present_state:states;
begin
process(clock,reset)
begin
if (reset='0') then
present_state<=idle;
elsif(clock'event and clock='1') then
case present_state is
when idle=>
if (start='1') then
present_state<=write_a;
else
present_state<=idle;
end if;
when write_a=>
if(exceed='1') then
present_state<=reset_for_sums;
else
present_state<=write_a;
end if;
when reset_for_sums=>
present_state<=read_a;
when read_a=>
present_state <= sample_shift;
when sample_shift =>
present_state<=op_0;
when op_0=>
present_state <= op_1;
when op_1 =>
present_state <= op_2;
when op_2 =>
present_state <= op_3;
when op_3 =>
present_state <= op_4;
when op_4 =>
present_state <= sample_sum;
when sample_sum =>
present_state <= write_b;
when write_b =>
if(exceed = '0') then
present_state <= read_a;
else
present_state <= done;
end if;
when done =>
if (start = '1') then
present_state <= done;
else
present_state <= idle;
end if;
when others =>
present_state<=idle;
end case;
end if;
end process;
process (present_state)
begin
module <= '0';
cntrl <= '0';
enable_shift <= '0';
cs_a <= '0';
cs_b <= '0';
wr_rd_a <= '0';
wr_rd_b <= '0';
finished <= '0';
up_count <= '0';
mux1_sel <= "000";
rst_sum <= '1';
rst_shift <= '1';
rst_count <= '1';
enable_sum <= '1';
case present_state is
when idle =>
rst_count <= '0';
when write_a =>
cs_a <= '1';
wr_rd_a <= '1';
up_count <= '1';
when reset_for_sums =>
rst_shift <= '0';
rst_count <= '0';
when read_a =>
cs_a <= '1';
wr_rd_a <= '0';
when sample_shift =>
cs_a <= '1';
wr_rd_a <= '0';
enable_shift <= '1';
rst_sum <= '0';
when op_0 =>
mux1_sel <= "000";
cntrl <= '1';
when op_1 =>
mux1_sel <= "001";
cntrl <= '1';
when op_2 =>
mux1_sel <= "010";
when op_3 =>
mux1_sel <= "011";
when op_4 =>
mux1_sel <= "100";
module <= '1';
when sample_sum =>
enable_sum <= '0';
when write_b =>
cs_b <= '1';
wr_rd_b <= '1';
up_count <= '1';
enable_sum <= '0';
when done =>
finished <= '1';
when others =>
end case;
end process;
end Behaviour;
| gpl-3.0 | c44b680f939c559eaa7f332512a67700 | 0.407181 | 3.873226 | false | false | false | false |
imr/Mandelbrot-VHDL | src/Memory_Control.vhd | 1 | 1,869 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY Memory_Control IS
PORT(
clk, rst, R_out, R_start,WE :IN STD_LOGIC;
data_in :IN STD_LOGIC_VECTOR(15 downto 0);
data_mem :INOUT STD_LOGIC_VECTOR(15 downto 0);
VGA_R, VGA_G, VGA_B :OUT STD_LOGIC_VECTOR(7 downto 0);
addr_out :OUT STD_LOGIC_VECTOR(19 downto 0);
WE_out :OUT STD_LOGIC
);
END Memory_Control;
ARCHITECTURE Behavior OF Memory_Control IS
CONSTANT iterations :STD_LOGIC_VECTOR(15 downto 0) := X"0018";
SIGNAL do :STD_LOGIC_VECTOR(15 downto 0);
SIGNAL addr_read :UNSIGNED(19 downto 0);
SIGNAL addr_write :UNSIGNED(19 downto 0);
BEGIN
data_mem <= "ZZZZZZZZZZZZZZZZ" WHEN WE = '0' ELSE data_in;
addr_out <= STD_LOGIC_VECTOR(addr_read) WHEN WE = '0' ELSE STD_LOGIC_VECTOR(addr_write);
PROCESS (clk, rst, R_start)
BEGIN
IF (clk'EVENT and clk = '1') THEN
IF (rst = '1') THEN
addr_read <= X"00000";
addr_write <= X"00000";
WE_out <= '1';
ELSE
IF WE = '1' THEN -- write out to memory, does not look at read
WE_out <= '0';
IF (addr_write > X"BFFFF") THEN
addr_write <= X"00000";
ELSE
addr_write <= addr_write + 1;
END IF;
ELSIF (R_out = '1') THEN -- read out from memory, if needed
WE_out <= '1';
do <= data_mem;
addr_read <= addr_read + 1;
IF (data_mem = iterations) THEN -- blank pixel if in set
VGA_R <= X"00";
VGA_G <= X"00";
VGA_B <= X"00";
ELSE -- display iterations away from set in form of pixel color
VGA_R <= do(15) & do(12) & do(9) & do(6) & do(3) & do(0) & "11";
VGA_G <= do(13) & do(10) & do(7) & do(4) & do(1) & "111";
VGA_B <= do(14) & do(11) & do(8) & do(5) & do(2) & "111";
END IF;
END IF;
IF (R_start = '1') THEN
addr_read <= X"00000";
END IF;
END IF;
END IF;
END PROCESS;
END Behavior; | bsd-3-clause | 6000965d2b877d19457addf6e7d2f727 | 0.58534 | 2.639831 | false | false | false | false |
freecores/grain | src/VHDL/grain.vhd | 1 | 3,628 | --
-- Grain
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain is
generic (
DEBUG : boolean := false; -- output debug information
FAST : boolean := false -- attempt manual register balancing
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of grain is
type state_t is (IDLE, INIT_KEYIV, INIT_RUN);
signal state : state_t;
signal cnt : unsigned(7 downto 0) := (others => '0');
signal cnt79, cnt63, cnt239 : std_logic := '0';
signal inject_input, set_injected_iv , allow_output : std_logic;
signal add_output : std_logic;
signal output_bit, output_bit_d, allow_output_d : std_logic;
begin
KEYSTREAM_O <= output_bit_d;
KEYSTREAM_VALID_O <= allow_output_d;
slow_design: if FAST = false generate
begin
functions0: entity work.grain_datapath_slow
generic map ( DEBUG => DEBUG )
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INJECT_INPUT_I => inject_input,
PAD_IV_I => set_injected_iv,
ADD_OUTPUT_I => add_output,
H_O => output_bit
);
end generate;
fast_design: if FAST = true generate
begin
functions1: entity work.grain_datapath_fast
generic map ( DEBUG => DEBUG )
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INJECT_INPUT_I => inject_input,
PAD_IV_I => set_injected_iv,
ADD_OUTPUT_I => add_output,
H_O => output_bit
);
end generate;
-- output registers:
-- (in case the "user" forgets this is at
-- his end and kills my fmax)
--
output_reg: process(CLK_I, ARESET_I)
begin
if ARESET_I = '1' then
output_bit_d <= '0';
allow_output_d <= '0';
elsif rising_edge(CLK_I) then
if CLKEN_I = '1' then
output_bit_d <= output_bit;
allow_output_d <= allow_output;
end if;
end if;
end process;
-- the counter:
cnt_proc: process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
if state = IDLE then
cnt <= b"0000_0001";
else
cnt <= cnt + 1;
end if;
if cnt = 79 then
cnt79 <= '1';
else
cnt79 <= '0';
end if;
if cnt = 63 then
cnt63 <= '1';
else
cnt63 <= '0';
end if;
if cnt = 239 then
cnt239 <= '1';
else
cnt239 <= '0';
end if;
end if;
end if;
end process;
-- the controller fsm:
ctrl_proc: process(CLK_I, ARESET_I)
begin
if ARESET_I = '1' then
state <= IDLE;
inject_input <= '0';
set_injected_iv <= '0';
add_output <= '0';
allow_output <= '0';
elsif rising_edge(CLK_I) then
if CLKEN_I = '1' then
case state is
when IDLE =>
if INIT_I = '1' then
state <= INIT_KEYIV;
inject_input <= '1';
set_injected_iv <= '0';
allow_output <= '0';
end if;
when INIT_KEYIV =>
if cnt63 = '1' then
set_injected_iv <= '1';
end if;
if cnt79 = '1' then
state <= INIT_RUN;
inject_input <= '0';
add_output <= '1';
end if;
when INIT_RUN =>
if cnt239 = '1' then
state <= IDLE;
add_output <= '0';
allow_output <= '1';
end if;
when others => state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
| lgpl-3.0 | d74a28eb8ad5a62b00b20f15d94ea3cf | 0.547685 | 2.763138 | false | false | false | false |
freecores/grain | src/VHDL/test_synth/hw3_grain.vhd | 1 | 835 | --
-- synthesis test 3:
-- * with clock enable
-- * fast
--
--
-- Altera EP2C-8, Quartus 8.0: 195 LEs, 0 memory bits, fmax = 319 MHz (320 requested)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw3_grain is
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw3_grain is
begin
top: entity work.grain
generic map (
DEBUG => false,
FAST => true
)
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 | 20a530051924f34c6defed4062b6e4dc | 0.615569 | 2.470414 | false | false | false | false |
jfdelnero/CPLD_USBHxCFloppyEmulator | rtl/vhdl/Latch4.vhd | 1 | 6,900 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------H----H--X----X-----CCCCC----22222----0000-----0000------11----------
----------H----H----X-X-----C--------------2---0----0---0----0--1--1-----------
---------HHHHHH-----X------C----------22222---0----0---0----0-----1------------
--------H----H----X--X----C----------2-------0----0---0----0-----1-------------
-------H----H---X-----X---CCCCC-----222222----0000-----0000----1111------------
-------------------------------------------------------------------------------
----------------------------------------- http://jeanfrancoisdelnero.free.fr --
--===========================================================================--
-- HxCFloppyEmu
-- Floppy drive emulator Project
--
-- http://jeanfrancoisdelnero.free.fr
-- HxC2001 - 2006 - 2008
--
-- Design units :
--
-- File name : Latch4.vhd
--
-- Purpose : 4-bits Register
--
--
-- Dependencies : IEEE.Std_Logic_1164
--
--============================================================================-
-- --
-- Copyright (C) 2006, 2007, 2008 Jean-François DEL NERO --
-- --
-- This file is part of HxCFloppyEmulator. --
-- --
-- HxCFloppyEmulator may be used and distributed without restriction provided--
-- that this copyright statement is not removed from the file and that any --
-- derivative work contains the original copyright notice and the associated --
-- disclaimer. --
-- --
-- HxCFloppyEmulator is free software; you can redistribute it --
-- and/or modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 2 --
-- of the License, or (at your option) any later version. --
-- --
-- HxCFloppyEmulator is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. --
-- See the GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with HxCFloppyEmulator; if not, write to the Free Software --
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA--
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 Jean-François DEL NERO 23 march 2008 Major update:
--
-- MFM/FM output generator (HeadShifter) rewritten.
-- It can now do any bitrate between
-- 63kbit/s and 1Mbit/s with a 62.5ns step.
-- The emulator can now handle bitrate-protected floppies ;-)
--
-- The SRAM is now used like a ring buffer (1 buffer of 8KB).
--
-- The master state machine run now at 16Mhz
-- to allow fast opcode execution / mfm loading.
--
-- "Validate Track" opcode removed (same functionnality in "SENDTRACKCODE opcode".
-- "SETINDEX" opcode modified:
-- "SENDTRACKCODE" added (2 byte : 0x3 <track number>)
-- "SETBITRATE" opcode added (2 bytes: 0xD <period value>)
-- "NOP" opcode added (2 bytes : 0x7 XX)
-- "Disk Changed" and "Ready" signals
-- are now software driven
--
-- Track position register is now 8 bits.
--
-- SRAM_CS_not is now driven (for the SRAM standby mode)
--
-- 0.5 Jean-François DEL NERO 19 November 2006 Jumper-free drive select added
-- jeanfrancoisdelnero < > free.fr
-- 0.4 Jean-François DEL NERO 11 November 2006 500kbits/s support added
-- 2*1Ko and 2*2Ko buffer size available
-- Write protect signal added
-- Shugart and IBM PC mode available
-- 0.2 Jean-François DEL NERO 16 September 2006 MFM Pulse Generator rewritten
-- 0.1 Jean-François DEL NERO 25 June 2006 First public version
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- package Latch4
-------------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------------------------
ENTITY Latch4 IS
port (
D: in std_logic_vector(3 DOWNTO 0); -- Data in
Q: out std_logic_vector(3 DOWNTO 0);-- Data out
wr: in std_logic; --Store command
clock: in std_logic; --Store command
reset_not: in std_logic
);
end Latch4;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
ARCHITECTURE arch of Latch4 is
begin
latch4 : process(clock,wr,reset_not)
begin
if(reset_not='0')
then
Q<="0000";
else
if(clock='1' and clock'event)
then
if(wr='1')
then
Q<=D;
end if;
end if;
end if;
end process;
end arch; | gpl-3.0 | ccd0925e8581c12b00b564ff29432ed9 | 0.354928 | 5.118694 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/RBCP_Sender.vhd | 1 | 2,549 | --------------------------------------------------------------------------------
--! @file RBCP_Sender.vhd
--! @brief convert RBCP signal to SRAM read signal
--! @author Takehiro Shiozaki
--! @date 2013-11-05
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RBCP_Sender is
generic(
G_ADDR : std_logic_vector(31 downto 0);
G_LEN : integer;
G_ADDR_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- RBCP interface
RBCP_ACT : in std_logic;
RBCP_ADDR : in std_logic_vector(31 downto 0);
RBCP_RE : in std_logic;
RBCP_RD : out std_logic_vector(7 downto 0);
RBCP_ACK : out std_logic;
-- SRAM interface
ADDR : out std_logic_vector(G_ADDR_WIDTH - 1 downto 0);
RD : in std_logic_vector(7 downto 0)
);
end RBCP_Sender;
architecture RTL of RBCP_Sender is
signal ReadEnable : std_logic;
signal DelayedReadEnable : std_logic_vector(1 downto 0);
signal DelayedRd : std_logic_vector(7 downto 0);
signal DelayedAddr : std_logic_vector(G_ADDR_WIDTH - 1 downto 0);
begin
ReadEnable <= '1' when(RBCP_ACT = '1' and RBCP_RE = '1' and
G_ADDR <= RBCP_ADDR and
RBCP_ADDR <= G_ADDR + G_LEN - 1) else
'0';
process(CLK, RESET)
begin
if(RESET = '1') then
DelayedReadEnable <= (others => '0');
elsif(CLK'event and CLK = '1') then
DelayedReadEnable(0) <= ReadEnable;
DelayedReadEnable(1) <= DelayedReadEnable(0);
end if;
end process;
process(CLK, RESET)
begin
if(RESET = '1') then
DelayedRd <= (others => '0');
elsif(CLK'event and CLK = '1') then
DelayedRd <= RD;
end if;
end process;
RBCP_RD <= DelayedRd;
process(CLK, RESET)
begin
if(RESET = '1') then
RBCP_ACK <= '0';
elsif(CLK'event and CLK = '1') then
RBCP_ACK <= DelayedReadEnable(1);
end if;
end process;
process(CLK, RESET)
begin
if(RESET = '1') then
DelayedAddr <= (others => '0');
elsif(CLK'event and CLK = '1') then
DelayedAddr <= conv_std_logic_vector(conv_integer(RBCP_ADDR - G_ADDR), G_ADDR_WIDTH);
end if;
end process;
ADDR <= DelayedAddr;
end RTL;
| mit | 89fa2a8141948de45811c251f8b91bac | 0.516281 | 3.615603 | false | false | false | false |
AleChir/Digital_Filter_VHDL | Digital_Filter/b82to1MUX.vhd | 1 | 493 | library ieee;
use ieee.std_logic_1164.all;
entity b82to1MUX is
port( in0,in1: in std_logic_vector(7 downto 0);
m: out std_logic_vector(7 downto 0);
sel: in std_logic);
end b82to1MUX;
architecture behavior of b82to1MUX is
begin
process(sel, in0, in1)
begin
case sel is
when '0' => m<=in0;
when '1' => m<=in1;
when others=> m<=(others=> 'Z');
end case;
end process;
end behavior; | gpl-3.0 | 17e48c3b53351151d130c36c3053ff3b | 0.541582 | 3.222222 | false | false | false | false |
Xion345/fpga-projects | library/uart/uart_dma.vhd | 1 | 5,619 | -- Direct Memory Access for UART
-- 8 bit words - Configurable number of address bytes
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity uart_dma is
generic(
RAM_READ_TICKS: integer := 1; -- Number of clocks ticks to wait to get data from memory
ADDR_BYTES: integer := 1 -- Total adress bytes: 7 + ADDR_BYTES, so 15 bits by default
);
port(
clk, reset: in std_logic;
-- UART
rx_done_tick: in std_logic;
tx_done_tick: in std_logic;
data_rx: in std_logic_vector(7 downto 0); -- UART Received byte
data_tx: out std_logic_vector(7 downto 0); -- UART byte to transmit
tx_start_tick: out std_logic; -- Tick to start UART transmission
-- Synchronous RAM
data_ram_rd: in std_logic_vector(7 downto 0); -- RAM read byte
data_ram_wr: out std_logic_vector(7 downto 0); -- RAM byte to write
addr: out std_logic_vector(ADDR_BYTES*8 + 6 downto 0); -- RAM address (15 bits)
wr: out std_logic -- RAM read/write switch
);
-- Number of bits necessary to represent integer value
function int_width(value: integer) return integer is
begin
return integer(floor(log2(real(value))));
end function;
end uart_dma;
architecture uart_dma_arch of uart_dma is
type state_type is (idle, addr_recv, send_start, send, recv, write_mem, read_mem);
signal state_reg, state_next: state_type; -- State register
signal cmd_reg, cmd_next: std_logic; -- Command register (0 - read, 1 - write)
constant ADDR_OTHER_MSB: integer := (ADDR_BYTES * 8) - 1; -- MSB for "other" address bits
constant ADDR_MSB: integer := (ADDR_OTHER_MSB + 7); -- MSB for total address bits
signal addr_reg, addr_next: std_logic_vector(ADDR_MSB downto 0); -- Memory address register
signal addr_msb_reg, addr_msb_next:
unsigned(int_width(ADDR_OTHER_MSB) downto 0); -- Most significant bit position in addr_reg for next received byte
signal data_reg, data_next: std_logic_vector(7 downto 0); -- Received data
signal ticks_reg, ticks_next:
unsigned(int_width(RAM_READ_TICKS) downto 0); -- Clock cycles counter for memory accesses
begin
-- State and data regisuter
process(clk, reset)
begin
if reset = '1' then
state_reg <= idle;
cmd_reg <= '0';
addr_msb_reg <= (others => '0');
addr_reg <= (others => '0');
data_reg <= (others => '0');
ticks_reg <= (others => '0');
elsif rising_edge(clk) then
state_reg <= state_next;
cmd_reg <= cmd_next;
addr_msb_reg <= addr_msb_next;
addr_reg <= addr_next;
data_reg <= data_next;
ticks_reg <= ticks_next;
end if;
end process;
-- Next state logic and data path
process(clk, state_reg, rx_done_tick, tx_done_tick,
state_reg, cmd_reg, addr_msb_reg, addr_reg, data_reg, ticks_reg,
data_rx, data_ram_rd)
begin
-- Default values
state_next <= state_reg;
cmd_next <= cmd_reg;
addr_msb_next <= addr_msb_reg;
addr_next <= addr_reg;
data_next <= data_reg;
ticks_next <= ticks_reg;
tx_start_tick <= '0';
wr <= '0';
case state_reg is
-- Idle, waiting for a command
-- When byte received:
-- data_rx[7] (MSB): 1 -> write to memory, 0 -> read from memory (Command)
-- data_rx[6..0]: 7 address most significant bits
when idle =>
if rx_done_tick = '1' then -- We got a byte from UART
state_next <= addr_recv;
cmd_next <= data_rx(7);
addr_msb_next <= to_unsigned(ADDR_OTHER_MSB, addr_msb_reg'length);
addr_next(ADDR_MSB downto ADDR_MSB-6) <= data_rx(6 downto 0);
end if;
-- Receive others address byte
when addr_recv =>
if rx_done_tick = '1' then
addr_next(to_integer(addr_msb_reg) downto to_integer(addr_msb_reg - 7)) <= data_rx;
if addr_msb_reg = to_unsigned(7, addr_msb_reg'length) then -- Last address byte ?
if cmd_reg = '0' then -- Move to send_start state
state_next <= read_mem;
ticks_next <= (others => '0');
else
state_next <= recv;
end if;
else
addr_msb_next <= addr_msb_reg - 8;
end if;
end if;
-- Read byte (to register)
when read_mem =>
if ticks_reg = RAM_READ_TICKS then
data_next <= data_ram_rd;
state_next <= send_start;
else
ticks_next <= ticks_reg + 1;
end if;
-- Send read byte
when send_start =>
tx_start_tick <= '1';
state_next <= send;
when send =>
if tx_done_tick = '1' then
state_next <= idle;
end if;
-- Receive byte (to register)
when recv =>
if rx_done_tick = '1' then
data_next <= data_rx;
state_next <= write_mem;
end if;
-- Write received byte (register to memory)
when write_mem =>
wr <= '1';
state_next <= idle;
end case;
end process;
-- Output logic
-- UART
data_tx <= data_reg;
-- Memory
addr <= addr_reg;
data_ram_wr <= data_reg;
end uart_dma_arch;
| mit | 8a6a8181b5a7d5a1d689841cbfa85212 | 0.541022 | 3.778749 | false | false | false | false |
terpstra/opa | opa_lm32_pkg.vhd | 1 | 35,828 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
-- LM32 ISA properties
package opa_lm32_pkg is
constant c_opa_lm32 : t_opa_isa_info := (
big_endian => true,
num_arch => 32,
imm_wide => 32,
op_wide => 32,
page_size => 4096);
function f_opa_accept_lm32(config : t_opa_config) return std_logic;
function f_opa_decode_lm32(config : t_opa_config; x : std_logic_vector) return t_opa_op;
end package;
package body opa_lm32_pkg is
constant c_arch_wide : natural := f_opa_log2(c_opa_lm32.num_arch);
function f_arch_eq(x, y : std_logic_vector) return std_logic is
begin
return f_opa_and(not (x(c_arch_wide-1 downto 0) xor y));
end f_arch_eq;
-- Registers with special meaning
constant c_lm32_ra : std_logic_vector(4 downto 0) := "11101"; -- ra=29
constant c_lm32_ea : std_logic_vector(4 downto 0) := "11110"; -- ea=30
constant c_lm32_ba : std_logic_vector(4 downto 0) := "11111"; -- ba=31
function f_parse_rtype (x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archa(c_arch_wide-1 downto 0) := x(25 downto 21);
result.archx(c_arch_wide-1 downto 0) := x(15 downto 11);
result.getb := '0';
result.geta := '1';
result.setx := '1';
result.bad := f_opa_or(x(20 downto 16)) or f_opa_or(x(10 downto 0));
result.jump := '0';
result.take := '0';
result.force := '0';
result.order := '0';
return result;
end f_parse_rtype;
function f_parse_rrtype (x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archb(c_arch_wide-1 downto 0) := x(20 downto 16);
result.archa(c_arch_wide-1 downto 0) := x(25 downto 21);
result.archx(c_arch_wide-1 downto 0) := x(15 downto 11);
result.getb := '1';
result.geta := '1';
result.setx := '1';
result.bad := f_opa_or(x(10 downto 0));
result.jump := '0';
result.take := '0';
result.force := '0';
result.order := '0';
return result;
end f_parse_rrtype;
function f_parse_sttype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archb(c_arch_wide-1 downto 0) := x(20 downto 16);
result.archa(c_arch_wide-1 downto 0) := x(25 downto 21);
result.getb := '1';
result.geta := '1';
result.setx := '0';
result.bad := '0';
result.jump := '0';
result.take := '0';
result.force := '0';
result.order := '1';
result.imm := (others => x(15));
result.imm(14 downto 0) := x(14 downto 0);
return result;
end f_parse_sttype;
function f_parse_ritype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archa(c_arch_wide-1 downto 0) := x(25 downto 21);
result.archx(c_arch_wide-1 downto 0) := x(20 downto 16);
result.getb := '0'; -- immediate
result.geta := '1';
result.setx := '1';
result.jump := '0';
result.take := '0';
result.force := '0';
result.order := '0';
-- parsing of immediate done in si(gned), lo(w), hi(gh), in(dex)
return result;
end f_parse_ritype;
function f_parse_sitype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := f_parse_ritype(x);
begin
result.bad := '0';
result.imm := (others => x(15));
result.imm(14 downto 0) := x(14 downto 0);
return result;
end f_parse_sitype;
function f_parse_lotype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := f_parse_ritype(x);
begin
result.bad := '0';
result.imm := (others => '0');
result.imm(15 downto 0) := x(15 downto 0);
return result;
end f_parse_lotype;
function f_parse_hitype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := f_parse_ritype(x);
begin
result.bad := '0';
result.imm := (others => '0');
result.imm(31 downto 16) := x(15 downto 0);
return result;
end f_parse_hitype;
function f_parse_intype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := f_parse_ritype(x);
begin
result.bad := f_opa_or(x(15 downto 5));
result.imm := (others => '-');
result.imm(4 downto 0) := x(4 downto 0);
return result;
end f_parse_intype;
function f_parse_bitype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archb(c_arch_wide-1 downto 0) := x(20 downto 16);
result.archa(c_arch_wide-1 downto 0) := x(25 downto 21);
result.getb := '1';
result.geta := '1';
result.setx := '0';
result.bad := '0';
result.jump := '1';
result.take := x(15); -- static prediction: negative = taken
result.force := '0';
result.pop := '0';
result.push := '0';
result.order := '0';
result.imm := (others => x(15));
result.imm(16 downto 2) := x(14 downto 0);
result.imm( 1 downto 0) := (others => '0');
result.immb := result.imm;
return result;
end f_parse_bitype;
function f_parse_jitype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.getb := '0';
result.geta := '0';
result.bad := '0';
result.jump := '1';
result.take := '1';
result.force := '1';
result.order := '0';
-- NOTE: caller must assign setx and push+pop
result.imm := (others => x(25));
result.imm(26 downto 2) := x(24 downto 0);
result.imm( 1 downto 0) := (others => '0');
result.immb := result.imm;
return result;
end f_parse_jitype;
function f_parse_jrtype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archa(c_arch_wide-1 downto 0) := x(25 downto 21);
result.getb := '0';
result.geta := '1';
result.bad := f_opa_or(x(20 downto 0));
result.jump := '1';
result.take := '0'; -- no point following branch to nowhere
result.force := '0';
result.order := '0';
-- NOTE: caller must assign setx and push+pop
result.imm := (others => '0'); -- necessary as it is added to PC/reg
-- immb can stay as don't care, because we can't statically predict anyway
return result;
end f_parse_jrtype;
------------------------------------------------------------------------------------------
function f_decode_b(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_jrtype(x);
variable ret : std_logic;
begin
-- !!! mess around with CSRs on eret/bret
ret := f_arch_eq(op.archa, c_lm32_ra) or
f_arch_eq(op.archa, c_lm32_ea) or
f_arch_eq(op.archa, c_lm32_ba);
op.setx := '0';
op.take := ret; -- only follow indirect branches that are returns
op.pop := ret;
op.push := '0';
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '-';
op.arg.fmode := c_opa_fast_jump;
op.fast := '1';
return op;
end f_decode_b;
function f_decode_bi(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_jitype(x);
begin
op.setx := '0';
op.pop := '0';
op.push := '0';
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '-';
op.arg.fmode := c_opa_fast_jump;
op.fast := '1';
return op;
end f_decode_bi;
function f_decode_call(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_jrtype(x);
begin
op.archx(c_arch_wide-1 downto 0) := c_lm32_ra;
op.setx := '1';
op.pop := '0';
op.push := '1';
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '-';
op.arg.fmode := c_opa_fast_jump;
op.fast := '1';
return op;
end f_decode_call;
function f_decode_calli(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_jitype(x);
begin
op.archx(c_arch_wide-1 downto 0) := c_lm32_ra;
op.setx := '1';
op.pop := '0';
op.push := '1';
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '-';
op.arg.fmode := c_opa_fast_jump;
op.fast := '1';
return op;
end f_decode_calli;
------------------------------------------------------------------------------------------
function f_decode_add(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addl;
op.fast := '1';
return op;
end f_decode_add;
function f_decode_sub(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '-';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addl;
op.fast := '1';
return op;
end f_decode_sub;
function f_decode_addi(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addl;
op.fast := '1';
return op;
end f_decode_addi;
------------------------------------------------------------------------------------------
function f_decode_and(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.lut := "1000"; -- X = A and B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_and;
function f_decode_andhi(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_hitype(x);
op.arg.lut := "1000"; -- X = A and B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_andhi;
function f_decode_andi(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_lotype(x);
op.arg.lut := "1000"; -- X = A and B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_andi;
function f_decode_or(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.lut := "1110"; -- X = A or B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_or;
function f_decode_ori(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_lotype(x);
op.arg.lut := "1110"; -- X = A or B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_ori;
function f_decode_orhi(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_hitype(x);
op.arg.lut := "1110"; -- X = A or B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_orhi;
function f_decode_nor(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.lut := "0001"; -- X = A nor B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_nor;
function f_decode_nori(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_lotype(x);
op.arg.lut := "0001"; -- X = A nor B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_nori;
function f_decode_xor(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.lut := "0110"; -- X = A xor B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_xor;
function f_decode_xori(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_lotype(x);
op.arg.lut := "0110"; -- X = A xor B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_xori;
function f_decode_xnor(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.fmode := c_opa_fast_lut;
op.arg.lut := "1001"; -- X = A xnor B
op.fast := '1';
return op;
end f_decode_xnor;
function f_decode_xnori(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_lotype(x);
op.arg.lut := "1001"; -- X = A xnor B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_xnori;
------------------------------------------------------------------------------------------
function f_decode_be(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_bitype(x);
op.arg.adder.eq := '1';
op.arg.adder.nota := '1';
op.arg.adder.notb := '0';
op.arg.adder.cin := '1';
op.arg.adder.sign := '0';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_be;
function f_decode_cmpe(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.adder.eq := '1';
op.arg.adder.nota := '1';
op.arg.adder.notb := '0';
op.arg.adder.cin := '1';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpe;
function f_decode_cmpei(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.adder.eq := '1';
op.arg.adder.nota := '1';
op.arg.adder.notb := '0';
op.arg.adder.cin := '1';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpei;
function f_decode_bne(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_bitype(x);
op.arg.adder.eq := '1';
op.arg.adder.nota := '0';
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bne;
function f_decode_cmpne(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.adder.eq := '1';
op.arg.adder.nota := '0';
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpne;
function f_decode_cmpnei(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.adder.eq := '1';
op.arg.adder.nota := '0';
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpnei;
function f_decode_bg(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_bitype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>b)=(a-b-1>=0)=overflow(a-b-1)=overflow(a+!b)
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '1';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bg;
function f_decode_cmpg(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>b)=(a-b-1>=0)=overflow(a-b-1)=overflow(a+!b)
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '1';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpg;
function f_decode_cmpgi(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>b)=(a-b-1>=0)=overflow(a-b-1)=overflow(a+!b)
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '1';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpgi;
function f_decode_bgu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_bitype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>b)=(a-b-1>=0)=overflow(a-b-1)=overflow(a+!b)
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bgu;
function f_decode_cmpgu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>b)=(a-b-1>=0)=overflow(a-b-1)=overflow(a+!b)
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpgu;
function f_decode_cmpgui(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_lotype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>b)=(a-b-1>=0)=overflow(a-b-1)=overflow(a+!b)
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpgui;
function f_decode_bge(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_bitype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>=b)=(a-b>=0)=overflow(a-b)=overflow(a+!b+1)
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '1';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bge;
function f_decode_cmpge(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>=b)=(a-b>=0)=overflow(a-b)=overflow(a+!b+1)
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '1';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpge;
function f_decode_cmpgei(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>=b)=(a-b>=0)=overflow(a-b)=overflow(a+!b+1)
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '1';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpgei;
function f_decode_bgeu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_bitype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>=b)=(a-b>=0)=overflow(a-b)=overflow(a+!b+1)
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '0';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bgeu;
function f_decode_cmpgeu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>=b)=(a-b>=0)=overflow(a-b)=overflow(a+!b+1)
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpgeu;
function f_decode_cmpgeui(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_lotype(x);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>=b)=(a-b>=0)=overflow(a-b)=overflow(a+!b+1)
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_cmpgeui;
------------------------------------------------------------------------------------------
function f_decode_mul(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.mul.sexta := '-';
op.arg.mul.sextb := '-';
op.arg.mul.high := '0';
op.arg.mul.divide := '0';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_mul;
function f_decode_muli(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.mul.sexta := '-';
op.arg.mul.sextb := '-';
op.arg.mul.high := '0';
op.arg.mul.divide := '0';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_muli;
function f_decode_mulh(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.mul.sexta := '0';
op.arg.mul.sextb := '0';
op.arg.mul.high := '1';
op.arg.mul.divide := '0';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_mulh;
function f_decode_mulhi(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.mul.sexta := '0';
op.arg.mul.sextb := '0';
op.arg.mul.high := '1';
op.arg.mul.divide := '0';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_mulhi;
function f_decode_div(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.mul.sexta := '1';
op.arg.mul.sextb := '1';
op.arg.mul.high := '0';
op.arg.mul.divide := '1';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_div;
function f_decode_divu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.mul.sexta := '0';
op.arg.mul.sextb := '0';
op.arg.mul.high := '0';
op.arg.mul.divide := '1';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_divu;
function f_decode_mod(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.mul.sexta := '1';
op.arg.mul.sextb := '1';
op.arg.mul.high := '1';
op.arg.mul.divide := '1';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_mod;
function f_decode_modu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.mul.sexta := '0';
op.arg.mul.sextb := '0';
op.arg.mul.high := '1';
op.arg.mul.divide := '1';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_modu;
------------------------------------------------------------------------------------------
function f_decode_lb(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.ldst.store := '0';
op.arg.ldst.sext := '1';
op.arg.ldst.size := c_opa_ldst_byte;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lb;
function f_decode_lbu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.ldst.store := '0';
op.arg.ldst.sext := '0';
op.arg.ldst.size := c_opa_ldst_byte;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lbu;
function f_decode_lh(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.ldst.store := '0';
op.arg.ldst.sext := '1';
op.arg.ldst.size := c_opa_ldst_half;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lh;
function f_decode_lhu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.ldst.store := '0';
op.arg.ldst.sext := '0';
op.arg.ldst.size := c_opa_ldst_half;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lhu;
function f_decode_lw(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sitype(x);
op.arg.ldst.store := '0';
op.arg.ldst.sext := '1';
op.arg.ldst.size := c_opa_ldst_word;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lw;
function f_decode_sb(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sttype(x);
op.arg.ldst.store := '1';
op.arg.ldst.sext := '-';
op.arg.ldst.size := c_opa_ldst_byte;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_sb;
function f_decode_sh(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sttype(x);
op.arg.ldst.store := '1';
op.arg.ldst.sext := '-';
op.arg.ldst.size := c_opa_ldst_half;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_sh;
function f_decode_sw(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_sttype(x);
op.arg.ldst.store := '1';
op.arg.ldst.sext := '-';
op.arg.ldst.size := c_opa_ldst_word;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_sw;
------------------------------------------------------------------------------------------
function f_decode_sl(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.shift.right := '0';
op.arg.shift.sext := '0';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_sl;
function f_decode_sli(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_intype(x);
op.arg.shift.right := '0';
op.arg.shift.sext := '0';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_sli;
function f_decode_sr(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.shift.right := '1';
op.arg.shift.sext := '1';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_sr;
function f_decode_sri(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_intype(x);
op.arg.shift.right := '1';
op.arg.shift.sext := '1';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_sri;
function f_decode_sru(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rrtype(x);
op.arg.shift.right := '1';
op.arg.shift.sext := '0';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_sru;
function f_decode_srui(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_intype(x);
op.arg.shift.right := '1';
op.arg.shift.sext := '0';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_srui;
------------------------------------------------------------------------------------------
function f_decode_sextb(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rtype(x);
op.arg.sext.size := c_opa_ldst_byte;
op.arg.smode := c_opa_slow_sext;
op.fast := '0';
return op;
end f_decode_sextb;
function f_decode_sexth(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op;
begin
op := f_parse_rtype(x);
op.arg.sext.size := c_opa_ldst_half;
op.arg.smode := c_opa_slow_sext;
op.fast := '0';
return op;
end f_decode_sexth;
------------------------------------------------------------------------------------------
function f_opa_accept_lm32(config : t_opa_config) return std_logic is
begin
assert (config.reg_width = 32) report "LM32 requires 32-bit registers" severity failure;
assert (config.ieee_fp = false) report "LM32 does not support IEEE floating point" severity failure;
return '1';
end f_opa_accept_lm32;
function f_opa_decode_lm32(config : t_opa_config; x : std_logic_vector) return t_opa_op is
constant c_opcode : std_logic_vector(5 downto 0) := x(31 downto 26);
begin
case c_opcode is
when "101101" => return f_decode_add(x);
when "001101" => return f_decode_addi(x);
when "101000" => return f_decode_and(x);
when "011000" => return f_decode_andhi(x);
when "001000" => return f_decode_andi(x);
when "110000" => return f_decode_b(x); -- ret(b ra), bret(b ba), eret(b ea)
when "010001" => return f_decode_be(x);
when "010010" => return f_decode_bg(x);
when "010011" => return f_decode_bge(x);
when "010100" => return f_decode_bgeu(x);
when "010101" => return f_decode_bgu(x);
when "111000" => return f_decode_bi(x);
when "010111" => return f_decode_bne(x);
when "110110" => return f_decode_call(x);
when "111110" => return f_decode_calli(x);
when "111001" => return f_decode_cmpe(x);
when "011001" => return f_decode_cmpei(x);
when "111010" => return f_decode_cmpg(x);
when "011010" => return f_decode_cmpgi(x);
when "111011" => return f_decode_cmpge(x);
when "011011" => return f_decode_cmpgei(x);
when "111100" => return f_decode_cmpgeu(x);
when "011100" => return f_decode_cmpgeui(x);
when "111101" => return f_decode_cmpgu(x);
when "011101" => return f_decode_cmpgui(x);
when "111111" => return f_decode_cmpne(x);
when "011111" => return f_decode_cmpnei(x);
when "100111" => return f_decode_div(x);
when "100011" => return f_decode_divu(x);
when "000100" => return f_decode_lb(x);
when "010000" => return f_decode_lbu(x);
when "000111" => return f_decode_lh(x);
when "001011" => return f_decode_lhu(x);
when "001010" => return f_decode_lw(x);
when "110101" => return f_decode_mod(x);
when "110001" => return f_decode_modu(x);
when "100010" => return f_decode_mul(x);
when "000010" => return f_decode_muli(x);
when "101010" => return f_decode_mulh(x); -- An OPA extension
when "110011" => return f_decode_mulhi(x); -- An OPA extension
when "100001" => return f_decode_nor(x);
when "000001" => return f_decode_nori(x);
when "101110" => return f_decode_or(x);
when "001110" => return f_decode_ori(x);
when "011110" => return f_decode_orhi(x);
when "101011" => return c_opa_op_bad; -- !!! raise: break, scall
when "100100" => return c_opa_op_bad; -- !!! rcsr
when "001100" => return f_decode_sb(x);
when "101100" => return f_decode_sextb(x);
when "110111" => return f_decode_sexth(x);
when "000011" => return f_decode_sh(x);
when "101111" => return f_decode_sl(x);
when "001111" => return f_decode_sli(x);
when "100101" => return f_decode_sr(x);
when "000101" => return f_decode_sri(x);
when "100000" => return f_decode_sru(x);
when "000000" => return f_decode_srui(x);
when "110010" => return f_decode_sub(x);
when "010110" => return f_decode_sw(x);
when "110100" => return c_opa_op_bad; -- !!! wcsr
when "101001" => return f_decode_xnor(x);
when "001001" => return f_decode_xnori(x);
when "100110" => return f_decode_xor(x);
when "000110" => return f_decode_xori(x);
when others => return c_opa_op_bad;
end case;
end f_opa_decode_lm32;
end opa_lm32_pkg;
| gpl-3.0 | 6fbd1068a5a5cfd7766ca14c01647e2d | 0.540415 | 2.812245 | false | false | false | false |
Xion345/fpga-projects | library/uart/uart_tx.vhd | 1 | 3,776 | -- UART Transmitter
-- 20/07/2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tx is
port(
clk, reset: in std_logic; -- Clock and reset
baud16_tick: in std_logic; -- 16x oversampled baud tick
data_in: in std_logic_vector(7 downto 0); -- Data byte to send
tx_start: in std_logic; -- Start transmission tick
tx: out std_logic; -- UART TX (Send) pin
tx_done_tick: out std_logic
);
end uart_tx;
architecture uart_tx_arch of uart_tx is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type; -- State register
signal data_reg, data_next: std_logic_vector(7 downto 0); -- Data (shift) register
signal sent_reg, sent_next: unsigned(2 downto 0); -- Count sent bits
signal ticks_reg, ticks_next: unsigned(3 downto 0); -- Ticks count (oversampling)
signal tx_reg, tx_next: std_logic; -- TX pin register
begin
-- State and data registers
process(clk, reset)
begin
if reset = '1' then
state_reg <= idle;
ticks_reg <= (others => '0');
sent_reg <= (others => '0');
data_reg <= (others => '0');
tx_reg <= '1'; -- Keep TX high for idle state (it is held low to start transmission)
elsif rising_edge(clk) then
state_reg <= state_next;
data_reg <= data_next;
sent_reg <= sent_next;
ticks_reg <= ticks_next;
tx_reg <= tx_next;
end if;
end process;
-- Next state logic and data path
process(state_reg, data_reg, sent_reg, ticks_reg, tx_reg, baud16_tick, tx_start, data_in)
begin
state_next <= state_reg;
data_next <= data_reg;
sent_next <= sent_reg;
ticks_next <= ticks_reg;
tx_next <= tx_reg;
tx_done_tick <= '0';
case state_reg is
--
when idle =>
if tx_start = '1' then
state_next <= start;
ticks_next <= (others => '0');
data_next <= data_in;
end if;
--
when start =>
if baud16_tick = '1' then
if ticks_reg = 15 then -- Move to data state
state_next <= data;
ticks_next <= (others => '0');
sent_next <= (others => '0');
else
tx_next <= '0';
ticks_next <= ticks_reg + 1;
end if;
end if;
--
when data =>
if baud16_tick = '1' then
if ticks_reg = 15 then -- Move to next bit
ticks_next <= (others => '0');
data_next <= '0' & data_reg(7 downto 1);
if sent_reg = 7 then -- Last byte ?
state_next <= stop;
else
sent_next <= sent_reg + 1;
end if;
else
tx_next <= data_reg(0);
ticks_next <= ticks_reg + 1;
end if;
end if;
--
when stop =>
if baud16_tick = '1' then
if ticks_reg = 15 then
state_next <= idle;
tx_done_tick <= '1';
else
tx_next <= '1'; -- I FOUND YOU BASTARD BUG !
ticks_next <= ticks_reg + 1;
end if;
end if;
end case;
end process;
-- Output logic
tx <= tx_reg;
end uart_tx_arch;
| mit | c6f80d79cada27df298baa683d6598a8 | 0.44571 | 4.163175 | false | false | false | false |
Xion345/fpga-projects | library/vga/vga_sync.vhd | 1 | 3,222 | -- VGA Synchronisation Circuit
-- 640x480 60Hz - Adjust clock divisor to generate a 25 Mhz pixel tick
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_sync is
generic(
CLOCK_DIVISOR: integer := 4;
--
SCREEN_WIDTH: integer := 640;
SCREEN_HEIGHT: integer := 480;
--
TOTAL_WIDTH: integer := 800;
TOTAL_HEIGHT: integer := 525;
--
HSYNC_START: integer := 656;
HSYNC_STOP: integer := 752;
HSYNC_POLARITY: std_logic := '0'; -- 0 negative polarity, 1 positive polarity
--
VSYNC_START: integer := 490;
VSYNC_STOP: integer := 492;
VSYNC_POLARITY: std_logic := '0' -- 0 negative polarity, 1 positive polarity
);
port(
clk, reset: in std_logic;
hsync, vsync: out std_logic;
pixel_tick: out std_logic;
x, y: out std_logic_vector(9 downto 0);
video_on: out std_logic
);
end vga_sync;
architecture arch of vga_sync is
constant CLOCK_DIVISOR_WIDTH: integer := 2;
signal pixel_tick_internal: std_logic;
-- Sync. counters
signal vcount_reg, vcount_next: unsigned(9 downto 0);
signal hcount_reg, hcount_next: unsigned(9 downto 0);
-- Output buffer
signal vsync_reg, vsync_next: std_logic;
signal hsync_reg, hsync_next: std_logic;
begin
-- Generate Pixel Tick
vga_clock: entity work.counter_mod_m
generic map(N => CLOCK_DIVISOR_WIDTH, M => CLOCK_DIVISOR)
port map(clk => clk, reset => reset, max_tick => pixel_tick_internal);
-- State registers
process(clk, reset)
begin
if reset='1' then
vcount_reg <= (others => '0');
hcount_reg <= (others => '0');
vsync_reg <= '0';
hsync_reg <= '0';
elsif rising_edge(clk) then
vcount_reg <= vcount_next;
hcount_reg <= hcount_next;
vsync_reg <= vsync_next;
hsync_reg <= hsync_next;
end if;
end process;
-- Increment hcount/vcount
process(hcount_reg, vcount_reg, pixel_tick_internal)
begin
hcount_next <= hcount_reg;
vcount_next <= vcount_reg;
if pixel_tick_internal = '1' then
if hcount_reg = TOTAL_WIDTH-1 then
hcount_next <= (others => '0');
if vcount_reg = TOTAL_HEIGHT-1 then
vcount_next <= (others => '0');
else
vcount_next <= vcount_reg + 1;
end if;
else
hcount_next <= hcount_reg + 1;
end if;
end if;
end process;
-- Hsync/Vsync
hsync_next <= HSYNC_POLARITY when hcount_reg >= HSYNC_START and hcount_reg < HSYNC_STOP-1 else
not HSYNC_POLARITY;
vsync_next <= VSYNC_POLARITY when vcount_reg >= VSYNC_START and vcount_reg < VSYNC_STOP-1 else
not VSYNC_POLARITY;
-- Output
pixel_tick <= pixel_tick_internal;
hsync <= hsync_reg;
vsync <= vsync_reg;
x <= std_logic_vector(hcount_reg);
y <= std_logic_vector(vcount_reg);
video_on <= '1' when hcount_reg < SCREEN_WIDTH and vcount_reg < SCREEN_HEIGHT else '0';
end arch; | mit | 40e81f217f097f06fbbbc7b6cea1771c | 0.563935 | 3.881928 | false | false | false | false |
AleChir/Digital_Filter_VHDL | Testbench/filter_with_file_write.vhd | 1 | 3,695 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity filter_with_file_write is
port( data_ext: in std_logic_vector( 7 downto 0);
clock, start, rst: in std_logic;
mem_b_out: out std_logic_vector( 7 downto 0);
done: out std_logic);
end filter_with_file_write;
architecture behavior of filter_with_file_write is
component datapath
port( x: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0);
clock: in std_logic;
rst_shift, enable_shift: in std_logic;
rst_sum, enable_sum: in std_logic;
rst_count, enable_count: in std_logic;
count_out: out std_logic_vector(9 downto 0);
module, cntrl: in std_logic;
mux1_sel: in std_logic_vector(2 downto 0);
terminal_count: out std_logic);
end component;
component control_unit
port ( module: out std_logic;
cntrl: out std_logic;
enable_sum: out std_logic;
enable_shift: out std_logic;
clock: in std_logic;
rst_shift: out std_logic;
cs_a,cs_b,wr_rd_a,wr_rd_b: out std_logic;
finished: out std_logic;
rst_count: out std_logic;
up_count: out std_logic;
start: in std_logic;
rst_sum: out std_logic;
mux1_sel: out std_logic_vector(2 downto 0);
reset: in std_logic;
exceed: in std_logic);
end component;
component ram_1024X8
port( data_in: in std_logic_vector(7 downto 0);
address: in integer range 1023 downto 0;
cs: in std_logic;
clk: in std_logic;
wr_rd_n: in std_logic;
data_out: out std_logic_vector (7 downto 0));
end component;
signal mem_a_out, mem_b_in: std_logic_vector (7 downto 0);
signal rst_shift, enable_shift: std_logic;
signal rst_sum, enable_sum: std_logic;
signal rst_count, enable_count: std_logic;
signal count_out: std_logic_vector(9 downto 0);
signal module, cntrl: std_logic;
signal mux1_sel: std_logic_vector(2 downto 0);
signal cs_a,cs_b,wr_rd_a,wr_rd_b: std_logic;
signal exceed:std_logic;
signal add: integer:=0;
begin
datapath: datapath port map(mem_a_out, mem_b_in, clock, rst_shift, enable_shift,
rst_sum, enable_sum, rst_count,enable_count,
count_out, module, cntrl, mux1_sel, exceed);
cu: control_unit port map(module,cntrl,enable_sum, enable_shift, clock, rst_shift,
cs_a, cs_b, wr_rd_a, wr_rd_b, done,rst_count,enable_count,
start, rst_sum, mux1_sel, rst, exceed);
add<= to_integer(unsigned(count_out));
ram_a: ram_1024x8 port map(data_ext,add, cs_a, clock, wr_rd_a, mem_a_out);
ram_b: ram_1024x8 port map(mem_b_in,add, cs_b, clock, wr_rd_b, mem_b_out);
process (clock)
file ofile: TEXT is out "data_in_b";
variable buf:line;
variable datab: integer;
begin
if(clock'event and clock='1') then
if (cs_b = '1' and wr_rd_b = '0') then
datab := to_integer(signed(mem_b_in));
write(buf,datab);
writeline(ofile,buf);
end if;
end if;
end process;
end architecture;
| gpl-3.0 | bc4eef75b934a302f49433df69d5ebee | 0.526658 | 3.552885 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/SynchEdgeDetector.vhd | 1 | 1,291 | --------------------------------------------------------------------------------
--! @file SynchEdgeDetector.vhd
--! @brief Synchronize async signal and detect positive edge
--! @author Takehiro Shiozaki
--! @date 2013-11-11
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity SynchEdgeDetector is
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end SynchEdgeDetector;
architecture RTL of SynchEdgeDetector is
component Synchronizer
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end component;
signal SynchronizedDin : std_logic;
signal DelayedDin : std_logic;
begin
Synchronizer_0: Synchronizer
port map(
CLK => CLK,
RESET => RESET,
DIN => DIN,
DOUT => SynchronizedDin
);
process(CLK, RESET)
begin
if(RESET = '1') then
DelayedDin <= '0';
elsif(CLK'event and CLK = '1') then
DelayedDin <= SynchronizedDin;
end if;
end process;
DOUT <= (not DelayedDin) and SynchronizedDin;
end RTL;
| mit | 01192f499862505854fad466d8a38c21 | 0.505035 | 4.482639 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_CRC7_Generator.vhd | 2 | 1,754 | ---------------------------------------------------------------------------------------
-- This generates the necessary 7-CRC for Command and Response
-- Implementation: serial input/parallel output
--
-- When input stream ends, the crcout output is the CRC checksum for the input stream.
--
-- NOTES/REVISIONS:
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC7_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC7_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(6 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(6);
shift_register(1) <= shift_register(0);
shift_register(2) <= shift_register(1);
shift_register(3) <= shift_register(2) XOR i_datain XOR shift_register(6);
shift_register(4) <= shift_register(3);
shift_register(5) <= shift_register(4);
shift_register(6) <= shift_register(5);
else -- shift CRC out (no more calculation now)
shift_register(0) <= '0';
shift_register(6 downto 1) <= shift_register(5 downto 0);
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(6);
o_crcout <= shift_register;
end rtl;
| mit | d0eeea6a7a63f90753688167b4ee4cf5 | 0.583808 | 3.149013 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/PulseExtender.vhd | 1 | 1,277 | --------------------------------------------------------------------------------
--! @file PulseExtender.vhd
--! @brief Expand width of pulse
--! @author Takehiro Shiozaki
--! @date 2013-10-28
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity PulseExtender is
generic(
G_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end PulseExtender;
architecture RTL of PulseExtender is
signal Dff : std_logic_vector(G_WIDTH - 1 downto 0);
constant C_ALL_ZERO : std_logic_vector(G_WIDTH - 1 downto 0) := (others => '0');
begin
process(CLK, RESET)
begin
if(RESET = '1') then
Dff <= (others => '0');
elsif(CLK'event and CLK = '1') then
Dff <= Dff(Dff'high - 1 downto 0) & DIN;
end if;
end process;
process(CLK, RESET)
begin
if(RESET = '1') then
DOUT <= '0';
elsif(CLK'event and CLK = '1') then
if(Dff /= C_ALL_ZERO) then
DOUT <= '1';
else
DOUT <= '0';
end if;
end if;
end process;
end RTL;
| mit | d5aa56b7fdc958febaf24321b3615333 | 0.450274 | 3.858006 | false | false | false | false |
freecores/grain | src/VHDL/test_sim/tb_grain128.vhd | 1 | 3,573 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_grain128 is
generic (
DEBUG : boolean := false;
FAST : boolean := false
);
end entity;
architecture test of tb_grain128 is
-- some testvectors:
constant GRAIN_KEY1 : unsigned(127 downto 0) := (others => '0');
constant GRAIN_IV1 : unsigned( 95 downto 0) := (others => '0');
constant GRAIN_KS1 : unsigned(127 downto 0) := x"0fd9deefeb6fad437bf43fce35849cfe";
constant GRAIN_KEY2 : unsigned(127 downto 0) := x"0123456789abcdef123456789abcdef0";
constant GRAIN_IV2 : unsigned( 95 downto 0) := x"0123456789abcdef12345678";
constant GRAIN_KS2 : unsigned(127 downto 0) := x"db032aff3788498b57cb894fffb6bb96";
-- DUT signal
signal clk, clken, areset : std_logic;
signal key_in, iv_in : std_logic;
signal key : unsigned(127 downto 0);
signal iv : unsigned(95 downto 0);
signal init, keystream, keystream_valid : std_logic;
-- monitor the output:
signal key_memory : unsigned(127 downto 0);
signal key_count : integer;
begin
-- the one and only, the DUT
DUT: entity work.grain128
generic map (
DEBUG => DEBUG,
FAST => FAST
)
port map (
CLK_I => clk,
CLKEN_I => clken,
ARESET_I => areset,
KEY_I => key_in,
IV_I => iv_in,
INIT_I => init,
KEYSTREAM_O => keystream,
KEYSTREAM_VALID_O => keystream_valid
);
-- clock generator:
clkgen_proc: process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
-- dummy clock enable: every fourth cycle
clken_proc: process
begin
clken <= '0';
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk);
clken <= '1';
wait until rising_edge(clk);
end process;
-- output monitor:
mon_proc: process(clk, areset)
begin
if areset = '1' then
key_memory <= (others => 'X');
key_count <= 0;
elsif rising_edge(clk) then
if clken = '1' then
if keystream_valid = '1' then
key_count <= key_count + 1;
key_memory <= key_memory(key_memory'high-1 downto 0) & keystream;
else
key_memory <= (others => 'X');
key_count <= 0;
end if;
end if;
end if;
end process;
-- this process will do all the testing
tester_proc: process
-- reset everything
procedure do_reset is
begin
key_in <= 'X';
iv_in <= 'X';
init <= '0';
areset <= '1';
wait for 100 ns;
areset <= '0';
end procedure;
-- initialize grain with key and IV
procedure do_init is
begin
wait until rising_edge(clk) and clken = '1';
init <= '1';
wait until rising_edge(clk) and clken = '1';
init <= '0';
for i in key'range loop
key_in <= key(key'high);
iv_in <= iv(iv'high);
key <= key rol 1;
iv <= iv rol 1;
wait until rising_edge(clk) and clken = '1';
end loop;
end procedure;
begin
-- 1. start with a reset:
do_reset;
-- 2. inject key and IV
key <= GRAIN_KEY1;
iv <= GRAIN_IV1;
do_init;
-- 3. verify output:
wait on clk until key_count = 128;
assert key_memory = GRAIN_KS1
report "incorrect output with IV = 0 and KEY = 0"
severity failure;
-- 4. try the other testvector
-- do_reset;
key <= GRAIN_KEY2;
iv <= GRAIN_IV2;
do_init;
wait on clk until key_count = 128;
assert
key_memory = GRAIN_KS2
report "incorrect output with IV = 0123.. and KEY = 0123.."
severity failure;
-- done:
report "ALL DONE" severity failure;
wait;
end process;
end test;
-- asim tb_grain128 ; wave /DUT/* ; run 100 us
| lgpl-3.0 | bddb2d0c9194203badf0ece0623a8129 | 0.616849 | 2.940741 | false | false | false | false |
freecores/grain | src/VHDL/grain_datapath_slow.vhd | 1 | 2,405 |
--
-- Grain datapath, slow and small implementation
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain_datapath_slow is
generic (
DEBUG : boolean := false -- output debug information
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INJECT_INPUT_I : in std_logic;
PAD_IV_I : in std_logic;
ADD_OUTPUT_I : in std_logic;
H_O : out std_logic
);
end entity;
architecture behav of grain_datapath_slow is
signal lfsr, nfsr : unsigned(0 to 79);
signal func_h, func_g, func_f : std_logic;
begin
-- outputs:
H_O <= func_h;
func_h <=
nfsr(1) xor nfsr(2) xor nfsr(4) xor nfsr(10) xor nfsr(31) xor nfsr(43) xor nfsr(56) xor
lfsr(25) xor nfsr(63) xor
(lfsr(3) and lfsr(64)) xor
(lfsr(46) and lfsr(64)) xor
(lfsr(64) and nfsr(63)) xor
(lfsr(3) and lfsr(25) and lfsr(46)) xor
(lfsr(3) and lfsr(46) and lfsr(64)) xor
(lfsr(3) and lfsr(46) and nfsr(63)) xor
(lfsr(25) and lfsr(46) and nfsr(63)) xor
(lfsr(46) and lfsr(64)and nfsr(63));
func_g <=
lfsr(0) xor
nfsr(62) xor nfsr(60) xor nfsr(52) xor nfsr(45) xor nfsr(37) xor nfsr(33) xor nfsr(28) xor nfsr(21) xor nfsr(14) xor nfsr(9) xor nfsr(0) xor
(nfsr(63) and nfsr(60)) xor
(nfsr(37) and nfsr(33)) xor
(nfsr(15) and nfsr(9)) xor
(nfsr(60) and nfsr(52) and nfsr(45)) xor
(nfsr(33) and nfsr(28) and nfsr(21)) xor
(nfsr(63) and nfsr(45) and nfsr(28) and nfsr(9)) xor
(nfsr(60) and nfsr(52) and nfsr(37) and nfsr(33)) xor
(nfsr(63) and nfsr(60) and nfsr(21) and nfsr(15)) xor
(nfsr(63) and nfsr(60) and nfsr(52) and nfsr(45) and nfsr(37)) xor
(nfsr(33) and nfsr(28) and nfsr(21) and nfsr(15) and nfsr(9)) xor
(nfsr(52) and nfsr(45) and nfsr(37) and nfsr(33) and nfsr(28) and nfsr(21));
func_f <=
lfsr(62) xor lfsr(51) xor lfsr(38) xor lfsr(23) xor lfsr(13) xor lfsr(0);
-- the shift registers:
sr_proc : process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
lfsr <= lfsr sll 1;
nfsr <= nfsr sll 1;
if INJECT_INPUT_I = '1' then
lfsr(79) <= IV_I or PAD_IV_I;
nfsr(79) <= KEY_I;
else
lfsr(79) <= func_f xor (ADD_OUTPUT_I and func_h);
nfsr(79) <= func_g xor (ADD_OUTPUT_I and func_h);
end if;
end if;
end if;
end process;
end behav;
| lgpl-3.0 | 7b25d78d8ddcdfed9a36c247f4e8e2e3 | 0.6079 | 2.360157 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_max.vhd | 1 | 6,352 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:21:55 07/01/2017
-- Design Name:
-- Module Name: complex_max - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--! @file complex_max.vhd
--! @author Antonio Riccio, Andrea Scognamiglio, Stefano Sorrentino
--! @brief Entità top-level
--! @example tb_complex_max.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--! @brief Componente top-level
--! @details Il componente calcola il modulo per ogni campione prima di determinare il massimo
entity complex_max is
Generic ( sample_width : natural := 32; --! Parallelismo in bit del del campione
s : natural := 5; --! Numero di satelliti
d : natural := 4; --! Numero di intervalli doppler
c : natural := 5 ); --! Numero di campioni per intervallo doppler
Port ( clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
valid_in : in STD_LOGIC; --! Indica che il dato sulla linea di ingresso è valido
ready_in : in STD_LOGIC; --! Indica che il componente a valle è pronto ad accettare valori in ingresso
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Valore complesso del campione associato al modulo
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Valore complesso del massimo
max : out STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Modulo del campione massimo
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0); --! Posizione del massimo nell'intervallo doppler
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0); --! Intervallo di frequenze doppler al quale appartiene il massimo
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0); --! Satellite associato al massimo
valid_out : out STD_LOGIC; --! Indica che il dato sulla linea di uscita è valido
ready_out : out STD_LOGIC); --! Indica che questo componente è pronto ad accettare valori in ingresso
end complex_max;
--! @brief Architettura top-level descritta nel dominio strutturale
--! @details L'architettura fa uso dei componenti @ref compute_max e @ref complex_abs
--! racchiusi nei rispettivi wrapper.
--! @see wrapper_complex_abs, wrapper_compute_max
architecture Structural of complex_max is
--! @brief Blocco che calcola il modulo del campione in ingresso
--! @see complex_abs
component wrapper_complex_abs is
generic (
complex_width : natural := 32
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
complex_value : in STD_LOGIC_VECTOR(complex_width-1 downto 0);
complex_value_out : out STD_LOGIC_VECTOR(complex_width-1 downto 0);
abs_value : out STD_LOGIC_VECTOR(complex_width-1 downto 0);
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC
);
end component wrapper_complex_abs;
--! @brief Blocco che calcola il massimo modulo tra tutti i campioni
--! @see compute_max
component wrapper_compute_max is
generic (
sample_width : natural := 32;
s : natural := 2;
d : natural := 2;
c : natural := 3
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
sample_abs : in STD_LOGIC_VECTOR(sample_width-1 downto 0);
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC
);
end component wrapper_compute_max;
signal abs_value_sig : std_logic_vector(sample_width-1 downto 0);
signal valid_out_abs : std_logic;
signal ready_in_abs : std_logic;
signal complex_value_sig : std_logic_vector(sample_width-1 downto 0);
begin
--! Istanza del componente @ref wrapper_complex_abs
wrapper_complex_abs_inst : wrapper_complex_abs
Generic map ( complex_width => sample_width )
Port map ( clock => clock,
reset_n => reset_n,
complex_value => sample,
complex_value_out => complex_value_sig,
abs_value => abs_value_sig,
valid_out => valid_out_abs,
valid_in => valid_in,
ready_out => ready_out,
ready_in => ready_in_abs);
--! Istanza del componente @ref wrapper_compute_max
wrapper_compute_max_inst : wrapper_compute_max
Generic map ( sample_width => sample_width,
s => s,
d => d,
c => c )
Port map ( clock => clock,
reset_n => reset_n,
ready_in => ready_in,
sample_abs => abs_value_sig,
sample => complex_value_sig,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
max => max,
sample_max => sample_max,
valid_in => valid_out_abs,
ready_out => ready_in_abs,
valid_out => valid_out);
end Structural;
| gpl-2.0 | 7ec4b593777324f8d3438822a4892f28 | 0.603435 | 3.563728 | false | false | false | false |
terpstra/opa | syn/uart.vhd | 1 | 5,972 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity uart is
generic(
g_wide : natural := 8;
g_deep : natural := 10);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
stb_i : in std_logic;
stall_o : out std_logic;
dat_i : in std_logic_vector(g_wide-1 downto 0);
stb_o : out std_logic;
stall_i : in std_logic;
dat_o : out std_logic_vector(g_wide-1 downto 0));
end uart;
architecture rtl of uart is
-- Virtual JTAG pins
signal s_tck : std_logic;
signal s_tdi : std_logic;
signal s_tdo : std_logic;
signal s_virtual_state_cdr : std_logic;
signal s_virtual_state_sdr : std_logic;
signal s_virtual_state_udr : std_logic;
-- SYS to JTAG
signal s_s2j_full : std_logic;
signal s_s2j_push : std_logic;
signal s_s2j_empty : std_logic;
signal s_s2j_pop : std_logic;
signal s_s2j_dat : std_logic_vector(g_wide-1 downto 0);
-- JTAG to SYS
signal s_j2s_full : std_logic;
signal s_j2s_push : std_logic;
signal s_j2s_empty : std_logic;
signal s_j2s_pop : std_logic;
signal s_j2s_dat : std_logic_vector(g_wide-1 downto 0);
-- JTAG shift register
signal r_jtag_valid : std_logic;
signal r_jtag_dat : std_logic_vector(g_wide-1 downto 0);
begin
stall_o <= s_s2j_full;
s_s2j_push <= stb_i and not s_s2j_full;
s_s2j_pop <= s_virtual_state_cdr and not s_s2j_empty;
s2j : dcfifo
generic map(
lpm_width => g_wide,
lpm_widthu => g_deep,
lpm_numwords => 2**g_deep,
lpm_showahead => "ON",
overflow_checking => "OFF",
underflow_checking=> "OFF",
rdsync_delaypipe => 4,
wrsync_delaypipe => 4)
port map(
aclr => "not"(rst_n_i),
wrclk => clk_i,
data => dat_i,
wrreq => s_s2j_push,
wrfull => s_s2j_full,
rdclk => s_tck,
q => s_s2j_dat,
rdreq => s_s2j_pop,
rdempty => s_s2j_empty);
-- !!! no flow control on input from JTAG; we drop on overflow
s_j2s_push <= r_jtag_valid and s_virtual_state_udr and not s_j2s_full;
stb_o <= not s_j2s_empty;
dat_o <= s_j2s_dat;
s_j2s_pop <= not stall_i and not s_j2s_empty;
j2s : dcfifo
generic map(
lpm_width => g_wide,
lpm_widthu => g_deep,
lpm_numwords => 2**g_deep,
lpm_showahead => "ON",
overflow_checking => "OFF",
underflow_checking=> "OFF",
rdsync_delaypipe => 4,
wrsync_delaypipe => 4)
port map(
aclr => "not"(rst_n_i),
wrclk => s_tck,
data => r_jtag_dat,
wrreq => s_j2s_push,
wrfull => s_j2s_full,
rdclk => clk_i,
q => s_j2s_dat,
rdreq => s_j2s_pop,
rdempty => s_j2s_empty);
vjtag : sld_virtual_jtag
generic map(
sld_instance_index => 98,
sld_ir_width => 1)
port map(
ir_in => open,
ir_out => "0",
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => s_tck,
tdi => s_tdi,
tdo => s_tdo,
tms => open,
virtual_state_cdr => s_virtual_state_cdr,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => s_virtual_state_sdr,
virtual_state_udr => s_virtual_state_udr,
virtual_state_uir => open);
jtag : process(s_tck) is
begin
if rising_edge(s_tck) then
if s_virtual_state_cdr = '1' then
r_jtag_valid <= not s_s2j_empty;
r_jtag_dat <= s_s2j_dat;
end if;
if s_virtual_state_sdr = '1' then
r_jtag_valid <= s_tdi;
r_jtag_dat <= r_jtag_valid & r_jtag_dat(r_jtag_dat'high downto r_jtag_dat'low+1);
end if;
end if;
end process;
s_tdo <= r_jtag_dat(r_jtag_dat'low);
end rtl;
| gpl-3.0 | dc436847a585d94837334b4b2a3822fd | 0.569324 | 3.158117 | false | false | false | false |
imr/Mandelbrot-VHDL | src/float_pkg_c.vhdl | 3 | 298,243 | -- --------------------------------------------------------------------
-- "float_pkg" package contains functions for floating point math.
-- Please see the documentation for the floating point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
-- use ieee_proposed.float_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers. Please
-- note the "%%%" comments. These are where we diverge from the
-- VHDL-200X LRM.
--
-- --------------------------------------------------------------------
-- Version : $Revision: 2.0 $
-- Date : $Date: 2009/01/27 20:45:30 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
package float_pkg is
-- generic (
-- Defaults for sizing routines, when you do a "to_float" this will be
-- the default size. Example float32 would be 8 and 23 (8 downto -23)
constant float_exponent_width : NATURAL := 8;
constant float_fraction_width : NATURAL := 23;
-- Rounding algorithm, "round_nearest" is default, other valid values
-- are "round_zero" (truncation), "round_inf" (round up), and
-- "round_neginf" (round down)
constant float_round_style : round_type := round_nearest;
-- Denormal numbers (very small numbers near zero) true or false
constant float_denormalize : BOOLEAN := true;
-- Turns on NAN processing (invalid numbers and overflow) true of false
constant float_check_error : BOOLEAN := true;
-- Guard bits are added to the bottom of every operation for rounding.
-- any natural number (including 0) are valid.
constant float_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- Note that the size of the vector is not defined here, but in
-- the package which calls this one.
type UNRESOLVED_float is array (INTEGER range <>) of STD_ULOGIC; -- main type
subtype U_float is UNRESOLVED_float;
subtype float is UNRESOLVED_float;
-----------------------------------------------------------------------------
-- Use the float type to define your own floating point numbers.
-- There must be a negative index or the packages will error out.
-- Minimum supported is "subtype float7 is float (3 downto -3);"
-- "subtype float16 is float (6 downto -9);" is probably the smallest
-- practical one to use.
-----------------------------------------------------------------------------
-- IEEE 754 single precision
subtype UNRESOLVED_float32 is UNRESOLVED_float (8 downto -23);
alias U_float32 is UNRESOLVED_float32;
subtype float32 is float (8 downto -23);
-----------------------------------------------------------------------------
-- IEEE-754 single precision floating point. This is a "float"
-- in C, and a FLOAT in Fortran. The exponent is 8 bits wide, and
-- the fraction is 23 bits wide. This format can hold roughly 7 decimal
-- digits. Infinity is 2**127 = 1.7E38 in this number system.
-- The bit representation is as follows:
-- 1 09876543 21098765432109876543210
-- 8 76543210 12345678901234567890123
-- 0 00000000 00000000000000000000000
-- 8 7 0 -1 -23
-- +/- exp. fraction
-----------------------------------------------------------------------------
-- IEEE 754 double precision
subtype UNRESOLVED_float64 is UNRESOLVED_float (11 downto -52);
alias U_float64 is UNRESOLVED_float64;
subtype float64 is float (11 downto -52);
-----------------------------------------------------------------------------
-- IEEE-754 double precision floating point. This is a "double float"
-- in C, and a FLOAT*8 in Fortran. The exponent is 11 bits wide, and
-- the fraction is 52 bits wide. This format can hold roughly 15 decimal
-- digits. Infinity is 2**2047 in this number system.
-- The bit representation is as follows:
-- 3 21098765432 1098765432109876543210987654321098765432109876543210
-- 1 09876543210 1234567890123456789012345678901234567890123456789012
-- S EEEEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
-- 11 10 0 -1 -52
-- +/- exponent fraction
-----------------------------------------------------------------------------
-- IEEE 854 & C extended precision
subtype UNRESOLVED_float128 is UNRESOLVED_float (15 downto -112);
alias U_float128 is UNRESOLVED_float128;
subtype float128 is float (15 downto -112);
-----------------------------------------------------------------------------
-- The 128 bit floating point number is "long double" in C (on
-- some systems this is a 70 bit floating point number) and FLOAT*32
-- in Fortran. The exponent is 15 bits wide and the fraction is 112
-- bits wide. This number can handle approximately 33 decimal digits.
-- Infinity is 2**32,767 in this number system.
-----------------------------------------------------------------------------
-- purpose: Checks for a valid floating point number
type valid_fpstate is (nan, -- Signaling NaN (C FP_NAN)
quiet_nan, -- Quiet NaN (C FP_NAN)
neg_inf, -- Negative infinity (C FP_INFINITE)
neg_normal, -- negative normalized nonzero
neg_denormal, -- negative denormalized (FP_SUBNORMAL)
neg_zero, -- -0 (C FP_ZERO)
pos_zero, -- +0 (C FP_ZERO)
pos_denormal, -- Positive denormalized (FP_SUBNORMAL)
pos_normal, -- positive normalized nonzero
pos_inf, -- positive infinity
isx); -- at least one input is unknown
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers.
constant fphdlsynth_or_real : BOOLEAN; -- deferred constant
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate;
-- Arithmetic functions, these operators do not require parameters.
function "abs" (arg : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Basic parameter list
-- round_style - Selects the rounding algorithm to use
-- guard - extra bits added to the end if the operation to add precision
-- check_error - When "false" turns off NAN and overflow checks
-- denormalize - When "false" turns off denormal number processing
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- reciprocal
function reciprocal (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Square root (all 754 based implementations need this)
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN;
-----------------------------------------------------------------------------
-- compare functions
-- =, /=, >=, <=, <, >, maximum, minimum
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ne ( -- not equal /=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN;
-- Need to overload the default versions of these
function "=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN;
function ">" (l, r : UNRESOLVED_float) return BOOLEAN;
function "<" (l, r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_float) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_float) return BOOLEAN;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC)
return INTEGER;
function maximum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- conversion functions
-- Converts one floating point number into another.
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function resize (
arg : UNRESOLVED_float; -- Floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128;
-- Converts an fp into an SLV (needed for synthesis)
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_float return STD_LOGIC_VECTOR];
-- Converts an fp into an std_ulogic_vector (sulv)
function to_sulv (arg : UNRESOLVED_float) return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_float return STD_ULOGIC_VECTOR];
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
-- Integer to float
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float;
-- sulv to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float;
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed;
-- float to real
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL;
-- float to integer
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL;
-- Maps metalogical values
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float;
function Is_X (arg : UNRESOLVED_float) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float;
-- These two procedures were copied out of the body because they proved
-- very useful for vendor specific algorithm development
-- Break_number converts a floating point number into it's parts
-- Exponent is biased by -1
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- a number between 1.0 and 2.0
expon : out SIGNED; -- NOTE: Add 1 to get the real exponent!
sign : out STD_ULOGIC);
-- Normalize takes a fraction and and exponent and converts them into
-- a floating point number. Does the shifting and the rounding.
-- Exponent is assumed to be biased by -1
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- Exponent is assumed to be biased by -1
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float;
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
-- overloaded compare functions
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN;
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN;
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC;
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC;
-- minimum and maximum overloads
function maximum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float;
function maximum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float;
function maximum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function minimum (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float;
function maximum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
function minimum (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_float) return UNRESOLVED_float;
function "and" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "or" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nand" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "nor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
function "xnor" (l, r : UNRESOLVED_float) return UNRESOLVED_float;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "and" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "or" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nand" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "nor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_float)
return UNRESOLVED_float;
function "xnor" (l : UNRESOLVED_float; r : STD_ULOGIC)
return UNRESOLVED_float;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC;
-- Note: "sla", "sra", "sll", "slr", "rol" and "ror" not implemented.
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (x, y : UNRESOLVED_float) return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float;
-- returns the unbiased exponent of x
function Logb (x : UNRESOLVED_float) return INTEGER;
function Logb (x : UNRESOLVED_float) return SIGNED;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float;
-- Returns TRUE if X is unordered with Y.
function Unordered (x, y : UNRESOLVED_float) return BOOLEAN;
function Finite (x : UNRESOLVED_float) return BOOLEAN;
function Isnan (x : UNRESOLVED_float) return BOOLEAN;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float;
-- ===========================================================================
-- string and textio Functions
-- ===========================================================================
-- rtl_synthesis off
-- pragma synthesis_off
-- writes S:EEEE:FFFFFFFF
procedure WRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Reads SEEEEFFFFFFFF, "." and ":" are ignored
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias BREAD is READ [LINE, UNRESOLVED_float, BOOLEAN];
alias BREAD is READ [LINE, UNRESOLVED_float];
alias BWRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_FLOAT];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_float, SIDE, WIDTH];
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Octal read with padding, no separators used
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_FLOAT];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- Hex write with padding, no separators
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0); -- width of field
-- Hex read with padding, no separators used
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float);
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_FLOAT];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_FLOAT, SIDE, WIDTH];
-- returns "S:EEEE:FFFFFFFF"
function to_string (value : UNRESOLVED_float) return STRING;
alias TO_BSTRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_FLOAT return STRING];
-- Returns a HEX string, with padding
function to_hstring (value : UNRESOLVED_float) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_FLOAT return STRING];
-- Returns and octal string, with padding
function to_ostring (value : UNRESOLVED_float) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_FLOAT return STRING];
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, NATURAL, NATURAL
return UNRESOLVED_float];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_bstring is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
alias from_binary_string is from_string [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_float
return UNRESOLVED_float];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL;
end package float_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT float_pkg package
-- This version is optimized for Synthesis, and not for simulation.
-- Note that there are functional differences between the synthesis and
-- simulation packages bodies. The Synthesis version is preferred.
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 2.0 $
-- Date : $Date: 2009/01/27 20:45:30 $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
-------------------------------------------------------------------------------
package body float_pkg is
-- Author David Bishop ([email protected])
-----------------------------------------------------------------------------
-- type declarations
-----------------------------------------------------------------------------
-- This deferred constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fphdlsynth_or_real : BOOLEAN := true; -- deferred constant
-- types of boundary conditions
type boundary_type is (normal, infinity, zero, denormal);
-- null range array constant
constant NAFP : UNRESOLVED_float (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- %%% Replicated functions
-- These functions are replicated so that we don't need to reference the new
-- 2006 package std.standard, std_logic_1164 and numeric_std.
function maximum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : INTEGER) -- inputs
return INTEGER is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
function or_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
function or_reduce (arg : STD_LOGIC_VECTOR)
return STD_ULOGIC is
begin
return or_reduce (STD_ULOGIC_VECTOR (arg));
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function and_reduce (arg : UNSIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function and_reduce (arg : SIGNED)
return STD_ULOGIC is
begin
return and_reduce (STD_ULOGIC_VECTOR (arg));
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
function find_leftmost (ARG : UNSIGNED; Y : STD_ULOGIC)
return INTEGER is
begin
for INDEX in ARG'range loop
if ARG(INDEX) = Y then
return INDEX;
end if;
end loop;
return -1;
end function find_leftmost;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return \?=\ (ufixed(l), ufixed(r));
end function \?=\;
function Is_X (s : UNSIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X (s : SIGNED) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking
function mine (L, R : INTEGER)
return INTEGER is
begin -- function minimum
if (L = INTEGER'low or R = INTEGER'low) then
report float_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- Generates the base number for the exponent normalization offset.
function gen_expon_base (
constant exponent_width : NATURAL)
return SIGNED is
variable result : SIGNED (exponent_width-1 downto 0);
begin
result := (others => '1');
result (exponent_width-1) := '0';
return result;
end function gen_expon_base;
-- Integer version of the "log2" command (contributed by Peter Ashenden)
function log2 (A : NATURAL) return NATURAL is
variable quotient : NATURAL;
variable result : NATURAL := 0;
begin
quotient := A / 2;
while quotient > 0 loop
quotient := quotient / 2;
result := result + 1;
end loop;
return result;
end function log2;
-- Function similar to the ILOGB function in MATH_REAL
function log2 (A : REAL) return INTEGER is
variable Y : REAL;
variable N : INTEGER := 0;
begin
if (A = 1.0 or A = 0.0) then
return 0;
end if;
Y := A;
if(A > 1.0) then
while Y >= 2.0 loop
Y := Y / 2.0;
N := N + 1;
end loop;
return N;
end if;
-- O < Y < 1
while Y < 1.0 loop
Y := Y * 2.0;
N := N - 1;
end loop;
return N;
end function log2;
-- purpose: Test the boundary conditions of a Real number
procedure test_boundary (
arg : in REAL; -- Input, converted to real
constant fraction_width : in NATURAL; -- length of FP output fraction
constant exponent_width : in NATURAL; -- length of FP exponent
constant denormalize : in BOOLEAN := true; -- Use IEEE extended FP
variable btype : out boundary_type;
variable log2i : out INTEGER
) is
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
constant exp_min : SIGNED (12 downto 0) :=
-(resize(expon_base, 13)) + 1; -- Minimum normal exponent
constant exp_ext_min : SIGNED (12 downto 0) :=
exp_min - fraction_width; -- Minimum for denormal exponent
variable log2arg : INTEGER; -- log2 of argument
begin -- function test_boundary
-- Check to see if the exponent is big enough
-- Note that the argument is always an absolute value at this point.
log2arg := log2(arg);
if arg = 0.0 then
btype := zero;
elsif exponent_width > 11 then -- Exponent for Real is 11 (64 bit)
btype := normal;
else
if log2arg < to_integer(exp_min) then
if denormalize then
if log2arg < to_integer(exp_ext_min) then
btype := zero;
else
btype := denormal;
end if;
else
if log2arg < to_integer(exp_min)-1 then
btype := zero;
else
btype := normal; -- Can still represent this number
end if;
end if;
elsif exponent_width < 11 then
if log2arg > to_integer(expon_base)+1 then
btype := infinity;
else
btype := normal;
end if;
else
btype := normal;
end if;
end if;
log2i := log2arg;
end procedure test_boundary;
-- purpose: Rounds depending on the state of the "round_style"
-- Logic taken from
-- "What Every Computer Scientist Should Know About Floating Point Arithmetic"
-- by David Goldberg (1991)
function check_round (
fract_in : STD_ULOGIC; -- input fraction
sign : STD_ULOGIC; -- sign bit
remainder : UNSIGNED; -- remainder to round from
sticky : STD_ULOGIC := '0'; -- Sticky bit
constant round_style : round_type) -- rounding type
return BOOLEAN is
variable result : BOOLEAN;
variable or_reduced : STD_ULOGIC;
begin -- function check_round
result := false;
if (remainder'length > 0) then -- if remainder in a null array
or_reduced := or_reduce (remainder & sticky);
rounding_case : case round_style is
when round_nearest => -- Round Nearest, default mode
if remainder(remainder'high) = '1' then -- round
if (remainder'length > 1) then
if ((or_reduce (remainder(remainder'high-1
downto remainder'low)) = '1'
or sticky = '1')
or fract_in = '1') then
-- Make the bottom bit zero if possible if we are at 1/2
result := true;
end if;
else
result := (fract_in = '1' or sticky = '1');
end if;
end if;
when round_inf => -- round up if positive, else truncate.
if or_reduced = '1' and sign = '0' then
result := true;
end if;
when round_neginf => -- round down if negative, else truncate.
if or_reduced = '1' and sign = '1' then
result := true;
end if;
when round_zero => -- round toward 0 Truncate
null;
end case rounding_case;
end if;
return result;
end function check_round;
-- purpose: Rounds depending on the state of the "round_style"
-- unsigned version
procedure fp_round (
fract_in : in UNSIGNED; -- input fraction
expon_in : in SIGNED; -- input exponent
fract_out : out UNSIGNED; -- output fraction
expon_out : out SIGNED) is -- output exponent
begin -- procedure fp_round
if and_reduce (fract_in) = '1' then -- Fraction is all "1"
expon_out := expon_in + 1;
fract_out := to_unsigned(0, fract_out'high+1);
else
expon_out := expon_in;
fract_out := fract_in + 1;
end if;
end procedure fp_round;
-- This version of break_number doesn't call "classfp"
procedure break_number ( -- internal version
arg : in UNRESOLVED_float;
fptyp : in valid_fpstate;
denormalize : in BOOLEAN := true;
fract : out UNSIGNED;
expon : out SIGNED) is
constant fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable exp : SIGNED (expon'range);
begin
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
breakcase : case fptyp is
when pos_zero | neg_zero =>
fract (fraction_width) := '0';
exp := -expon_base;
when pos_denormal | neg_denormal =>
if denormalize then
exp := -expon_base;
fract (fraction_width) := '0';
else
exp := -expon_base - 1;
fract (fraction_width) := '1';
end if;
when pos_normal | neg_normal | pos_inf | neg_inf =>
fract (fraction_width) := '1';
exp := SIGNED(arg(exponent_width-1 downto 0));
exp (exponent_width-1) := not exp(exponent_width-1);
when others =>
assert NO_WARNING
report float_pkg'instance_name
& "BREAK_NUMBER: " &
"Meta state detected in fp_break_number process"
severity warning;
-- complete the case, if a NAN goes in, a NAN comes out.
exp := (others => '1');
fract (fraction_width) := '1';
end case breakcase;
expon := exp;
end procedure break_number;
-- purpose: floating point to UNSIGNED
-- Used by to_integer, to_unsigned, and to_signed functions
procedure float_to_unsigned (
arg : in UNRESOLVED_float; -- floating point input
variable sign : out STD_ULOGIC; -- sign of output
variable frac : out UNSIGNED; -- unsigned biased output
constant denormalize : in BOOLEAN; -- turn on denormalization
constant bias : in NATURAL; -- bias for fixed point
constant round_style : in round_type) is -- rounding method
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable fract : UNSIGNED (frac'range); -- internal version of frac
variable isign : STD_ULOGIC; -- internal version of sign
variable exp : INTEGER; -- Exponent
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
-- Base to divide fraction by
variable frac_shift : UNSIGNED (frac'high+3 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable remainder : UNSIGNED (2 downto 0);
variable round : STD_ULOGIC; -- round BIT
begin
isign := to_x01(arg(arg'high));
-- exponent /= '0', normal floating point
expon := to_01(SIGNED(arg (exponent_width-1 downto 0)), 'X');
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (expon);
-- Figure out the fraction
fract := (others => '0'); -- fill with zero
fract (fract'high) := '1'; -- Add the "1.0".
shift := (fract'high-1) - exp;
if fraction_width > fract'high then -- Can only use size-2 bits
fract (fract'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-fract'high)));
else -- can use all bits
fract (fract'high-1 downto fract'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := fract & "000";
if shift < 0 then -- Overflow
fract := (others => '1');
else
frac_shift := shift_right (frac_shift, shift);
fract := frac_shift (frac_shift'high downto 3);
remainder := frac_shift (2 downto 0);
-- round (round_zero will bypass this and truncate)
case round_style is
when round_nearest =>
round := remainder(2) and
(fract (0) or (or_reduce (remainder (1 downto 0))));
when round_inf =>
round := remainder(2) and not isign;
when round_neginf =>
round := remainder(2) and isign;
when others =>
round := '0';
end case;
if round = '1' then
fract := fract + 1;
end if;
end if;
frac := fract;
sign := isign;
end procedure float_to_unsigned;
-- purpose: returns a part of a vector, this function is here because
-- or (fractr (to_integer(shiftx) downto 0));
-- can't be synthesized in some synthesis tools.
function smallfract (
arg : UNSIGNED;
shift : NATURAL)
return STD_ULOGIC is
variable orx : STD_ULOGIC;
begin
orx := arg(shift);
for i in arg'range loop
if i < shift then
orx := arg(i) or orx;
end if;
end loop;
return orx;
end function smallfract;
---------------------------------------------------------------------------
-- Visible functions
---------------------------------------------------------------------------
-- purpose: converts the negative index to a positive one
-- negative indices are illegal in 1164 and 1076.3
function to_sulv (
arg : UNRESOLVED_float) -- fp vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin -- function to_std_ulogic_vector
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
-- Converts an fp into an SLV
function to_slv (arg : UNRESOLVED_float) return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector (to_sulv (arg));
end function to_slv;
-- purpose: normalizes a floating point number
-- This version assumes an "unsigned" input with
function normalize (
fract : UNSIGNED; -- fraction, unnormalized
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign BIT
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable sfract : UNSIGNED (fract'high downto 0); -- shifted fraction
variable rfract : UNSIGNED (fraction_width-1 downto 0); -- fraction
variable exp : SIGNED (exponent_width+1 downto 0); -- exponent
variable rexp : SIGNED (exponent_width+1 downto 0); -- result exponent
variable rexpon : UNSIGNED (exponent_width-1 downto 0); -- exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width); -- result
variable shiftr : INTEGER; -- shift amount
variable stickyx : STD_ULOGIC; -- version of sticky
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round, zerores, infres : BOOLEAN;
begin -- function normalize
zerores := false;
infres := false;
round := false;
shiftr := find_leftmost (to_01(fract), '1') -- Find the first "1"
- fraction_width - nguard; -- subtract the length we want
exp := resize (expon, exp'length) + shiftr;
if (or_reduce (fract) = '0') then -- Zero
zerores := true;
elsif ((exp <= -resize(expon_base, exp'length)-1) and denormalize)
or ((exp < -resize(expon_base, exp'length)-1) and not denormalize) then
if (exp >= -resize(expon_base, exp'length)-fraction_width-1)
and denormalize then
exp := -resize(expon_base, exp'length)-1;
shiftr := -to_integer (expon + expon_base); -- new shift
else -- return zero
zerores := true;
end if;
elsif (exp > expon_base-1) then -- infinity
infres := true;
end if;
if zerores then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif infres then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
sfract := fract srl shiftr; -- shift
if shiftr > 0 then
-- stickyx := sticky or (or_reduce(fract (shiftr-1 downto 0)));
stickyx := sticky or smallfract (fract, shiftr-1);
else
stickyx := sticky;
end if;
if nguard > 0 then
round := check_round (
fract_in => sfract (nguard),
sign => sign,
remainder => sfract(nguard-1 downto 0),
sticky => stickyx,
round_style => round_style);
end if;
if round then
fp_round(fract_in => sfract (fraction_width-1+nguard downto nguard),
expon_in => exp(rexp'range),
fract_out => rfract,
expon_out => rexp);
else
rfract := sfract (fraction_width-1+nguard downto nguard);
rexp := exp(rexp'range);
end if;
-- result
rexpon := UNSIGNED (rexp(exponent_width-1 downto 0));
rexpon (exponent_width-1) := not rexpon(exponent_width-1);
result (rexpon'range) := UNRESOLVED_float(rexpon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
result (exponent_width) := sign; -- sign BIT
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
constant exponent_width : NATURAL := float_exponent_width; -- size of output exponent
constant fraction_width : NATURAL := float_fraction_width; -- size of output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- purpose: normalizes a floating point number
-- This version assumes a "ufixed" input with a "size_res" input
function normalize (
fract : ufixed; -- unsigned fixed point
expon : SIGNED; -- exponent, normalized by -1
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
constant fraction_width : NATURAL := -size_res'low;
constant exponent_width : NATURAL := size_res'high;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arguns : UNSIGNED (fract'high + fraction_width + nguard
downto 0) := (others => '0');
begin -- function normalize
arguns (arguns'high downto maximum (arguns'high-fract'length+1, 0)) :=
UNSIGNED (to_slv (fract));
result := normalize (fract => arguns,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
return result;
end function normalize;
-- Regular "normalize" function with a "size_res" input.
function normalize (
fract : UNSIGNED; -- unsigned
expon : SIGNED; -- exponent - 1, normalized
sign : STD_ULOGIC; -- sign bit
sticky : STD_ULOGIC := '0'; -- Sticky bit (rounding)
size_res : UNRESOLVED_float; -- used for sizing only
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant nguard : NATURAL := float_guard_bits) -- guard bits
return UNRESOLVED_float is
begin
return normalize (fract => fract,
expon => expon,
sign => sign,
sticky => sticky,
fraction_width => -size_res'low,
exponent_width => size_res'high,
round_style => round_style,
denormalize => denormalize,
nguard => nguard);
end function normalize;
-- Returns the class which X falls into
function Classfp (
x : UNRESOLVED_float; -- floating point input
check_error : BOOLEAN := float_check_error) -- check for errors
return valid_fpstate is
constant fraction_width : INTEGER := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : INTEGER := x'high; -- length of FP output exponent
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- classfp
if (arg'length < 1 or fraction_width < 3 or exponent_width < 3
or x'left < x'right) then
report float_pkg'instance_name
& "CLASSFP: " &
"Floating point number detected with a bad range"
severity error;
return isx;
end if;
-- Check for "X".
arg := to_01 (x, 'X');
if (arg(0) = 'X') then
return isx; -- If there is an X in the number
-- Special cases, check for illegal number
elsif check_error and
(and_reduce (STD_ULOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '1') then -- Exponent is all "1".
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
/= '0' then -- Fraction must be all "0" or this is not a number.
if (arg(-1) = '1') then -- From "W. Khan - IEEE standard
return nan; -- 754 binary FP Signaling nan (Not a number)
else
return quiet_nan;
end if;
-- Check for infinity
elsif arg(exponent_width) = '0' then
return pos_inf; -- Positive infinity
else
return neg_inf; -- Negative infinity
end if;
-- check for "0"
elsif or_reduce (STD_LOGIC_VECTOR (arg (exponent_width-1 downto 0)))
= '0' then -- Exponent is all "0"
if or_reduce (to_slv (arg (-1 downto -fraction_width)))
= '0' then -- Fraction is all "0"
if arg(exponent_width) = '0' then
return pos_zero; -- Zero
else
return neg_zero;
end if;
else
if arg(exponent_width) = '0' then
return pos_denormal; -- Denormal number (ieee extended fp)
else
return neg_denormal;
end if;
end if;
else
if arg(exponent_width) = '0' then
return pos_normal; -- Normal FP number
else
return neg_normal;
end if;
end if;
end function Classfp;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out UNSIGNED;
expon : out SIGNED;
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => fract,
expon => expon);
end procedure break_number;
procedure break_number (
arg : in UNRESOLVED_float;
denormalize : in BOOLEAN := float_denormalize;
check_error : in BOOLEAN := float_check_error;
fract : out ufixed; -- 1 downto -fraction_width
expon : out SIGNED; -- exponent_width-1 downto 0
sign : out STD_ULOGIC) is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
variable fptyp : valid_fpstate;
variable ufract : UNSIGNED (fraction_width downto 0); -- unsigned fraction
begin
fptyp := Classfp (arg, check_error);
sign := to_x01(arg(arg'high));
break_number (
arg => arg,
fptyp => fptyp,
denormalize => denormalize,
fract => ufract,
expon => expon);
fract (0 downto -fraction_width) := ufixed (ufract);
end procedure break_number;
-- Arithmetic functions
function "abs" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := '0'; -- set the sign bit to positive
return result;
else
return NAFP;
end if;
end function "abs";
-- IEEE 754 "negative" function
function "-" (
arg : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range); -- result
begin
if (arg'length > 0) then
result := to_01 (arg, 'X');
result (arg'high) := not result (arg'high); -- invert sign bit
return result;
else
return NAFP;
end if;
end function "-";
-- Addition, adds two floating point numbers
function add (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant addguard : NATURAL := guard; -- add one guard bit
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width+1+addguard downto 0); -- fractions
variable fractc, fracts : UNSIGNED (fractl'range); -- constant and shifted variables
variable urfract, ulfract : UNSIGNED (fraction_width downto 0);
variable ufract : UNSIGNED (fraction_width+1+addguard downto 0);
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable shiftx : SIGNED (exponent_width downto 0); -- shift fractions
variable sign : STD_ULOGIC; -- sign of the output
variable leftright : BOOLEAN; -- left or right used
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- addition
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf and rfptype = neg_inf)
or (lfptype = neg_inf and rfptype = pos_inf) then
-- Return quiet NAN, IEEE754-1985-7.1,2
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_inf or rfptype = neg_inf) then -- x - inf = -inf
fpresult := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = neg_zero and rfptype = neg_zero) then -- -0 + -0 = -0
fpresult := neg_zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl := (others => '0');
fractl (fraction_width+addguard downto addguard) := ulfract;
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr := (others => '0');
fractr (fraction_width+addguard downto addguard) := urfract;
shiftx := (exponl(exponent_width-1) & exponl) - exponr;
if shiftx < -fractl'high then
rexpon := exponr(exponent_width-1) & exponr;
fractc := fractr;
fracts := (others => '0'); -- add zero
leftright := false;
sticky := or_reduce (fractl);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (fractl, to_integer(shiftx));
fractc := fractr;
rexpon := exponr(exponent_width-1) & exponr;
leftright := false;
-- sticky := or_reduce (fractl (to_integer(shiftx) downto 0));
sticky := smallfract (fractl, to_integer(shiftx));
elsif shiftx = 0 then
rexpon := exponl(exponent_width-1) & exponl;
sticky := '0';
if fractr > fractl then
fractc := fractr;
fracts := fractl;
leftright := false;
else
fractc := fractl;
fracts := fractr;
leftright := true;
end if;
elsif shiftx > fractr'high then
rexpon := exponl(exponent_width-1) & exponl;
fracts := (others => '0'); -- add zero
fractc := fractl;
leftright := true;
sticky := or_reduce (fractr);
elsif shiftx > 0 then
fracts := shift_right (fractr, to_integer(shiftx));
fractc := fractl;
rexpon := exponl(exponent_width-1) & exponl;
leftright := true;
-- sticky := or_reduce (fractr (to_integer(shiftx) downto 0));
sticky := smallfract (fractr, to_integer(shiftx));
end if;
-- add
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if l(l'high) = r(r'high) then
ufract := fractc + fracts;
sign := l(l'high);
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
sign := l(l'high);
else
sign := r(r'high);
end if;
end if;
if or_reduce (ufract) = '0' then
sign := '0'; -- IEEE 854, 6.3, paragraph 2.
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon,
sign => sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => addguard);
end if;
return fpresult;
end function add;
-- Subtraction, Calls "add".
function subtract (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable negr : UNRESOLVED_float (r'range); -- negative version of r
begin
negr := -r;
return add (l => l,
r => negr,
round_style => round_style,
guard => guard,
check_error => check_error,
denormalize => denormalize);
end function subtract;
-- Floating point multiply
function multiply (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant multguard : NATURAL := guard; -- guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+multguard downto 0); -- result fraction
variable shifty : INTEGER; -- denormal shift
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif ((lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan)) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf) then -- x * inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
fpresult (exponent_width) := fp_sign;
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
rfract := fractl * fractr; -- Multiply the fraction
sfract := rfract (rfract'high downto
rfract'high - (fraction_width+1+multguard));
sticky := or_reduce (rfract (rfract'high-(fraction_width+1+multguard)
downto 0));
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => multguard);
end if;
return fpresult;
end function multiply;
function short_divide (
lx, rx : UNSIGNED)
return UNSIGNED is
-- This is a special divider for the floating point routines.
-- For a true unsigned divider, "stages" needs to = lx'high
constant stages : INTEGER := lx'high - rx'high; -- number of stages
variable partial : UNSIGNED (lx'range);
variable q : UNSIGNED (stages downto 0);
variable partial_argl : SIGNED (rx'high + 2 downto 0);
variable partial_arg : SIGNED (rx'high + 2 downto 0);
begin
partial := lx;
for i in stages downto 0 loop
partial_argl := resize ("0" & SIGNED (partial(lx'high downto i)),
partial_argl'length);
partial_arg := partial_argl - SIGNED ("0" & rx);
if (partial_arg (partial_arg'high) = '1') then -- negative
q(i) := '0';
else
q(i) := '1';
partial (lx'high+i-stages downto lx'high+i-stages-rx'high) :=
UNSIGNED (partial_arg(rx'range));
end if;
end loop;
-- to make the output look like that of the unsigned IEEE divide.
return resize (q, lx'length);
end function short_divide;
-- 1/X function. Needed for algorithm development.
function reciprocal (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
constant divguard : NATURAL := guard; -- guard bits
function onedivy (
arg : UNSIGNED)
return UNSIGNED is
variable q : UNSIGNED((2*arg'high)+1 downto 0);
variable one : UNSIGNED (q'range);
begin
one := (others => '0');
one(one'high) := '1';
q := short_divide (one, arg); -- Unsigned divide
return resize (q, arg'length+1);
end function onedivy;
variable fptype : valid_fpstate;
variable expon : SIGNED (exponent_width-1 downto 0); -- exponents
variable denorm_offset : NATURAL range 0 to 2;
variable fract : UNSIGNED (fraction_width downto 0);
variable fractg : UNSIGNED (fraction_width+divguard downto 0);
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- reciprocal
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- 1/inf, return 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_zero | pos_zero => -- 1/0
report float_pkg'instance_name
& "RECIPROCAL: Floating Point divide by zero"
severity error;
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
if (fptype = pos_denormal or fptype = neg_denormal)
and ((arg (-1) or arg(-2)) /= '1') then
-- 1/denormal = infinity, with the exception of 2**-expon_base
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fpresult (exponent_width) := to_x01 (arg (exponent_width));
else
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => fract,
expon => expon);
fractg := (others => '0');
if (fptype = pos_denormal or fptype = neg_denormal) then
-- The reciprocal of a denormal number is typically zero,
-- except for two special cases which are trapped here.
if (to_x01(arg (-1)) = '1') then
fractg (fractg'high downto divguard+1) :=
fract (fract'high-1 downto 0); -- Shift to not denormal
denorm_offset := 1; -- add 1 to exponent compensate
else -- arg(-2) = '1'
fractg (fractg'high downto divguard+2) :=
fract (fract'high-2 downto 0); -- Shift to not denormal
denorm_offset := 2; -- add 2 to exponent compensate
end if;
else
fractg (fractg'high downto divguard) := fract;
denorm_offset := 0;
end if;
expon := - expon - 3 + denorm_offset;
sfract := onedivy (fractg);
-- normalize
fpresult := normalize (fract => sfract,
expon => expon,
sign => arg(exponent_width),
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end if;
end case classcase;
return fpresult;
end function reciprocal;
-- floating point division
function divide (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractl : UNSIGNED ((2*(fraction_width+divguard)+1) downto 0); -- left
variable fractr : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractl'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+1+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width+1 downto 0); -- result exponent
variable fp_sign, sticky : STD_ULOGIC; -- sign of result
variable shifty, shiftx : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divide
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf -- inf / inf
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero -- 0 / 0
or lfptype = quiet_nan or lfptype = nan then
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDE: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult(exponent_width) := fp_sign;
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
-- Compute the exponent
rexpon := resize (exponl, rexpon'length) - exponr - 2;
if (rfptype = pos_denormal or rfptype = neg_denormal) then
-- Do the shifting here not after. That way we have a smaller
-- shifter, and need a smaller divider, because the top
-- bit in the divisor will always be a "1".
shifty := fraction_width - find_leftmost(urfract, '1');
urfract := shift_left (urfract, shifty);
rexpon := rexpon + shifty;
end if;
fractr := (others => '0');
fractr (fraction_width+divguard downto divguard) := urfract;
if (lfptype = pos_denormal or lfptype = neg_denormal) then
shiftx := fraction_width - find_leftmost(ulfract, '1');
ulfract := shift_left (ulfract, shiftx);
rexpon := rexpon - shiftx;
end if;
fractl := (others => '0');
fractl (fractl'high downto fractl'high-fraction_width) := ulfract;
-- divide
rfract := short_divide (fractl, fractr); -- unsigned divide
sfract := rfract (sfract'range); -- lower bits
sticky := '1';
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
end case classcase2;
end case classcase;
return fpresult;
end function divide;
-- division by a power of 2
function dividebyp2 (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable exponl, exponr : SIGNED(exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED(exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- divisionbyp2
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
classcase : case rfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf =>
if lfptype = pos_inf or lfptype = neg_inf then -- inf / inf
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- x / inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when pos_zero | neg_zero =>
if lfptype = pos_zero or lfptype = neg_zero then -- 0 / 0
-- Return quiet NAN, IEEE754-1985-7.1,4
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
report float_pkg'instance_name
& "DIVIDEBYP2: Floating Point divide by zero"
severity error;
-- Infinity, define in 754-1985-7.2
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (fpresult'high) := fp_sign; -- sign
end if;
when others =>
classcase2 : case lfptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf | neg_inf => -- inf / x = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when pos_zero | neg_zero => -- 0 / X = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
fp_sign := l(l'high) xor r(r'high); -- sign
fpresult (exponent_width) := fp_sign; -- sign
when others =>
fp_sign := l(l'high) xor r(r'high); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
-- right side
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
assert (or_reduce (urfract (fraction_width-1 downto 0)) = '0')
report float_pkg'instance_name
& "DIVIDEBYP2: "
& "Dividebyp2 called with a non power of two divisor"
severity error;
rexpon := (exponl(exponl'high)&exponl)
- (exponr(exponr'high)&exponr) - 1;
-- normalize
fpresult := normalize (fract => ulfract,
expon => rexpon,
sign => fp_sign,
sticky => '1',
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase2;
end case classcase;
return fpresult;
end function dividebyp2;
-- Multiply accumulate result = l*r + c
function mac (
l, r, c : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL :=
-mine (mine(l'low, r'low), c'low); -- length of FP output fraction
constant exponent_width : NATURAL :=
maximum (maximum(l'high, r'high), c'high); -- length of FP output exponent
variable lfptype, rfptype, cfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable fractl, fractr : UNSIGNED (fraction_width downto 0); -- fractions
variable fractx : UNSIGNED (fraction_width+guard downto 0);
variable fractc, fracts : UNSIGNED (fraction_width+1+guard downto 0);
variable rfract : UNSIGNED ((2*(fraction_width))+1 downto 0); -- result fraction
variable sfract, ufract : UNSIGNED (fraction_width+1+guard downto 0); -- result fraction
variable exponl, exponr, exponc : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon, rexpon2 : SIGNED (exponent_width+1 downto 0); -- result exponent
variable shifty : INTEGER; -- denormal shift
variable shiftx : SIGNED (rexpon'range); -- shift fractions
variable fp_sign : STD_ULOGIC; -- sign of result
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
variable cresize : UNRESOLVED_float (exponent_width downto -fraction_width - guard);
variable leftright : BOOLEAN; -- left or right used
variable sticky : STD_ULOGIC; -- Holds precision for rounding
begin -- multiply
if (fraction_width = 0 or l'length < 7 or r'length < 7 or c'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
cfptype := classfp (c, check_error);
end if;
if (lfptype = isx or rfptype = isx or cfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
cfptype = nan or cfptype = quiet_nan) then
-- Return quiet NAN, IEEE754-1985-7.1,1
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (((lfptype = pos_inf or lfptype = neg_inf) and
(rfptype = pos_zero or rfptype = neg_zero)) or
((rfptype = pos_inf or rfptype = neg_inf) and
(lfptype = pos_zero or lfptype = neg_zero))) then -- 0 * inf
-- Return quiet NAN, IEEE754-1985-7.1,3
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (lfptype = pos_inf or rfptype = pos_inf
or lfptype = neg_inf or rfptype = neg_inf -- x * inf = inf
or cfptype = neg_inf or cfptype = pos_inf) then -- x + inf = inf
fpresult := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
-- figure out the sign
fpresult (exponent_width) := l(l'high) xor r(r'high);
else
fp_sign := l(l'high) xor r(r'high); -- figure out the sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
cresize := resize (arg => to_x01(c),
exponent_width => exponent_width,
fraction_width => -cresize'low,
denormalize_in => denormalize,
denormalize => denormalize);
cfptype := classfp (cresize, false); -- errors already checked
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => fractl,
expon => exponl);
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => fractr,
expon => exponr);
break_number (
arg => cresize,
fptyp => cfptype,
denormalize => denormalize,
fract => fractx,
expon => exponc);
if (rfptype = pos_denormal or rfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractr, '1');
fractr := shift_left (fractr, shifty);
elsif (lfptype = pos_denormal or lfptype = neg_denormal) then
shifty := fraction_width - find_leftmost(fractl, '1');
fractl := shift_left (fractl, shifty);
else
shifty := 0;
-- Note that a denormal number * a denormal number is always zero.
end if;
-- multiply
rfract := fractl * fractr; -- Multiply the fraction
-- add the exponents
rexpon := resize (exponl, rexpon'length) + exponr - shifty + 1;
shiftx := rexpon - exponc;
if shiftx < -fractl'high then
rexpon2 := resize (exponc, rexpon2'length);
fractc := "0" & fractx;
fracts := (others => '0');
sticky := or_reduce (rfract);
elsif shiftx < 0 then
shiftx := - shiftx;
fracts := shift_right (rfract (rfract'high downto rfract'high
- fracts'length+1),
to_integer(shiftx));
fractc := "0" & fractx;
rexpon2 := resize (exponc, rexpon2'length);
leftright := false;
sticky := or_reduce (rfract (to_integer(shiftx)+rfract'high
- fracts'length downto 0));
elsif shiftx = 0 then
rexpon2 := resize (exponc, rexpon2'length);
sticky := or_reduce (rfract (rfract'high - fractc'length downto 0));
if rfract (rfract'high downto rfract'high - fractc'length+1) > fractx
then
fractc := "0" & fractx;
fracts := rfract (rfract'high downto rfract'high
- fracts'length+1);
leftright := false;
else
fractc := rfract (rfract'high downto rfract'high
- fractc'length+1);
fracts := "0" & fractx;
leftright := true;
end if;
elsif shiftx > fractx'high then
rexpon2 := rexpon;
fracts := (others => '0');
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx & rfract (rfract'high - fractc'length
downto 0));
else -- fractx'high > shiftx > 0
rexpon2 := rexpon;
fracts := "0" & shift_right (fractx, to_integer (shiftx));
fractc := rfract (rfract'high downto rfract'high - fractc'length+1);
leftright := true;
sticky := or_reduce (fractx (to_integer (shiftx) downto 0)
& rfract (rfract'high - fractc'length downto 0));
end if;
fracts (0) := fracts (0) or sticky; -- Or the sticky bit into the LSB
if fp_sign = to_X01(c(c'high)) then
ufract := fractc + fracts;
fp_sign := fp_sign;
else -- signs are different
ufract := fractc - fracts; -- always positive result
if leftright then -- Figure out which sign to use
fp_sign := fp_sign;
else
fp_sign := c(c'high);
end if;
end if;
-- normalize
fpresult := normalize (fract => ufract,
expon => rexpon2,
sign => fp_sign,
sticky => sticky,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end if;
return fpresult;
end function mac;
-- "rem" function
function remainder (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
constant divguard : NATURAL := guard; -- division guard bits
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable ulfract, urfract : UNSIGNED (fraction_width downto 0);
variable fractr, fractl : UNSIGNED (fraction_width+divguard downto 0); -- right
variable rfract : UNSIGNED (fractr'range); -- result fraction
variable sfract : UNSIGNED (fraction_width+divguard downto 0); -- result fraction
variable exponl, exponr : SIGNED (exponent_width-1 downto 0); -- exponents
variable rexpon : SIGNED (exponent_width downto 0); -- result exponent
variable fp_sign : STD_ULOGIC; -- sign of result
variable shifty : INTEGER; -- denormal number shift
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (abs(l) < abs(r)) then
fpresult := l;
else
fp_sign := to_X01(l(l'high)); -- sign
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
lfptype := classfp (lresize, false); -- errors already checked
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rfptype := classfp (rresize, false); -- errors already checked
fractl := (others => '0');
break_number (
arg => lresize,
fptyp => lfptype,
denormalize => denormalize,
fract => ulfract,
expon => exponl);
fractl (fraction_width+divguard downto divguard) := ulfract;
-- right side
fractr := (others => '0');
break_number (
arg => rresize,
fptyp => rfptype,
denormalize => denormalize,
fract => urfract,
expon => exponr);
fractr (fraction_width+divguard downto divguard) := urfract;
rexpon := (exponr(exponr'high)&exponr);
shifty := to_integer(exponl - rexpon);
if (shifty > 0) then
fractr := shift_right (fractr, shifty);
rexpon := rexpon + shifty;
end if;
if (fractr /= 0) then
-- rem
rfract := fractl rem fractr; -- unsigned rem
sfract := rfract (sfract'range); -- lower bits
-- normalize
fpresult := normalize (fract => sfract,
expon => rexpon,
sign => fp_sign,
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => divguard);
else
-- If we shift "fractr" so far that it becomes zero, return zero.
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
end if;
return fpresult;
end function remainder;
-- "mod" function
function modulo (
l, r : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant guard : NATURAL := float_guard_bits; -- number of guard bits
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := - mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable fpresult : UNRESOLVED_float (exponent_width downto -fraction_width);
variable remres : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- remainder
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
lfptype := isx;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = isx or rfptype = isx) then
fpresult := (others => 'X');
elsif (lfptype = nan or lfptype = quiet_nan)
or (rfptype = nan or rfptype = quiet_nan)
-- Return quiet NAN, IEEE754-1985-7.1,1
or (lfptype = pos_inf or lfptype = neg_inf) -- inf rem x
-- Return quiet NAN, IEEE754-1985-7.1,5
or (rfptype = pos_zero or rfptype = neg_zero) then -- x rem 0
-- Return quiet NAN, IEEE754-1985-7.1,5
fpresult := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (rfptype = pos_inf or rfptype = neg_inf) then -- x rem inf = 0
fpresult := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
remres := remainder (l => abs(l),
r => abs(r),
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
-- MOD is the same as REM, but you do something different with
-- negative values
if (is_negative (l)) then
remres := - remres;
end if;
if (is_negative (l) = is_negative (r) or remres = 0) then
fpresult := remres;
else
fpresult := add (l => remres,
r => r,
round_style => round_style,
guard => guard,
check_error => false,
denormalize => denormalize);
end if;
end if;
return fpresult;
end function modulo;
-- Square root of a floating point number. Done using Newton's Iteration.
function sqrt (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style;
constant guard : NATURAL := float_guard_bits;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := guard-arg'low; -- length of FP output fraction
constant exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable sign : STD_ULOGIC;
variable fpresult : float (arg'range);
variable fptype : valid_fpstate;
variable iexpon : SIGNED(exponent_width-1 downto 0); -- exponents
variable expon : SIGNED(exponent_width downto 0); -- exponents
variable ufact : ufixed (0 downto arg'low);
variable fact : ufixed (2 downto -fraction_width); -- fraction
variable resb : ufixed (fact'high+1 downto fact'low);
begin -- square root
fptype := Classfp (arg, check_error);
classcase : case fptype is
when isx =>
fpresult := (others => 'X');
when nan | quiet_nan |
-- Return quiet NAN, IEEE754-1985-7.1,1
neg_normal | neg_denormal | neg_inf => -- sqrt (neg)
-- Return quiet NAN, IEEE754-1985-7.1.6
fpresult := qnanfp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_inf => -- Sqrt (inf), return infinity
fpresult := pos_inffp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when pos_zero => -- return 0
fpresult := zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when neg_zero => -- IEEE754-1985-6.3 return -0
fpresult := neg_zerofp (fraction_width => fraction_width-guard,
exponent_width => exponent_width);
when others =>
break_number (arg => arg,
denormalize => denormalize,
check_error => false,
fract => ufact,
expon => iexpon,
sign => sign);
expon := resize (iexpon+1, expon'length); -- get exponent
fact := resize (ufact, fact'high, fact'low);
if (expon(0) = '1') then
fact := fact sla 1; -- * 2.0
end if;
expon := shift_right (expon, 1); -- exponent/2
-- Newton's iteration - root := (1 + arg) / 2
resb := (fact + 1) sra 1;
for j in 0 to fraction_width/4 loop
-- root := (root + (arg/root))/2
resb := resize (arg => (resb + (fact/resb)) sra 1,
left_index => resb'high,
right_index => resb'low,
round_style => fixed_truncate,
overflow_style => fixed_wrap);
end loop;
fpresult := normalize (fract => resb,
expon => expon-1,
sign => '0',
exponent_width => arg'high,
fraction_width => -arg'low,
round_style => round_style,
denormalize => denormalize,
nguard => guard);
end case classcase;
return fpresult;
end function sqrt;
function Is_Negative (arg : UNRESOLVED_float) return BOOLEAN is
-- Technically -0 should return "false", but I'm leaving that case out.
begin
return (to_x01(arg(arg'high)) = '1');
end function Is_Negative;
-- compare functions
-- =, /=, >=, <=, <, >
function eq ( -- equal =
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : BOOLEAN;
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- equal
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return false;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := true;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
is_equal := (to_slv(lresize) = to_slv(rresize));
end if;
if (check_error) then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_equal and not is_unordered;
end function eq;
function lt ( -- less than <
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_less_than, is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_less_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (fractl < fractr);
else
is_less_than := (fractl > fractr); -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_less_than := (expl < expr);
else
is_less_than := (expl > expr); -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = neg_zero and rfptype = pos_zero) then
is_less_than := false; -- -0 < 0 returns false.
else
is_less_than := (to_x01(l(l'high)) > to_x01(r(r'high)));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_less_than and not is_unordered;
end function lt;
function gt ( -- greater than >
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable expl, expr : UNSIGNED (exponent_width-1 downto 0);
variable fractl, fractr : UNSIGNED (fraction_width-1 downto 0);
variable is_greater_than : BOOLEAN;
variable is_unordered : BOOLEAN;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- greater_than
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
is_greater_than := false;
else
lresize := resize (arg => to_x01(l),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
rresize := resize (arg => to_x01(r),
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => denormalize,
denormalize => denormalize);
if to_x01(l(l'high)) = to_x01(r(r'high)) then -- sign bits
expl := UNSIGNED(lresize(exponent_width-1 downto 0));
expr := UNSIGNED(rresize(exponent_width-1 downto 0));
if expl = expr then
fractl := UNSIGNED (to_slv(lresize(-1 downto -fraction_width)));
fractr := UNSIGNED (to_slv(rresize(-1 downto -fraction_width)));
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := fractl > fractr;
else
is_greater_than := fractl < fractr; -- negative
end if;
else
if to_x01(l(l'high)) = '0' then -- positive number
is_greater_than := expl > expr;
else
is_greater_than := expl < expr; -- negative
end if;
end if;
else
lfptype := classfp (l, check_error);
rfptype := classfp (r, check_error);
if (lfptype = pos_zero and rfptype = neg_zero) then
is_greater_than := false; -- 0 > -0 returns false.
else
is_greater_than := to_x01(l(l'high)) < to_x01(r(r'high));
end if;
end if;
end if;
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return is_greater_than and not is_unordered;
end function gt;
-- purpose: /= function
function ne ( -- not equal /=
l, r : UNRESOLVED_float;
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_equal, is_unordered : BOOLEAN;
begin
is_equal := eq (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not (is_equal and not is_unordered);
end function ne;
function le ( -- less than or equal to <=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_greater_than, is_unordered : BOOLEAN;
begin
is_greater_than := gt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_greater_than and not is_unordered;
end function le;
function ge ( -- greater than or equal to >=
l, r : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error;
constant denormalize : BOOLEAN := float_denormalize)
return BOOLEAN is
variable is_less_than, is_unordered : BOOLEAN;
begin
is_less_than := lt (l => l,
r => r,
check_error => false,
denormalize => denormalize);
if check_error then
is_unordered := Unordered (x => l,
y => r);
else
is_unordered := false;
end if;
return not is_less_than and not is_unordered;
end function ge;
function \?=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return is_equal and not is_unordered;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lfptype, rfptype : valid_fpstate;
variable is_equal, is_unordered : STD_ULOGIC;
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- ?/=
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
lfptype := classfp (l, float_check_error);
rfptype := classfp (r, float_check_error);
end if;
if (lfptype = neg_zero or lfptype = pos_zero) and
(rfptype = neg_zero or rfptype = pos_zero) then
is_equal := '1';
else
lresize := resize (arg => l,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
rresize := resize (arg => r,
exponent_width => exponent_width,
fraction_width => fraction_width,
denormalize_in => float_denormalize,
denormalize => float_denormalize);
is_equal := \?=\ (to_sulv(lresize), to_sulv(rresize));
end if;
if (float_check_error) then
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan) then
is_unordered := '1';
else
is_unordered := '0';
end if;
else
is_unordered := '0';
end if;
return not (is_equal and not is_unordered);
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?>="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<"": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_float) return STD_ULOGIC is
constant fraction_width : NATURAL := -mine(l'low, r'low);
variable founddash : BOOLEAN := false;
begin
if (fraction_width = 0 or l'length < 7 or r'length < 7) then
return 'X';
else
for i in L'range loop
if L(i) = '-' then
founddash := true;
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
founddash := true;
end if;
end loop;
if founddash then
report float_pkg'instance_name
& " ""?<="": '-' found in compare string"
severity error;
return 'X';
elsif is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
function std_match (L, R : UNRESOLVED_float) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
report float_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function find_rightmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_float; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
-- These override the defaults for the compare operators.
function "=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return eq(l, r);
end function "=";
function "/=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ne(l, r);
end function "/=";
function ">=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return ge(l, r);
end function ">=";
function "<=" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return le(l, r);
end function "<=";
function ">" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return gt(l, r);
end function ">";
function "<" (l, r : UNRESOLVED_float) return BOOLEAN is
begin
return lt(l, r);
end function "<";
-- purpose: maximum of two numbers (overrides default)
function maximum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (
L, R : UNRESOLVED_float)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(l'low, r'low); -- length of FP output fraction
constant exponent_width : NATURAL := maximum(l'high, r'high); -- length of FP output exponent
variable lresize, rresize : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if ((L'length < 1) or (R'length < 1)) then return NAFP;
end if;
lresize := resize (l, exponent_width, fraction_width);
rresize := resize (r, exponent_width, fraction_width);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
-----------------------------------------------------------------------------
-- conversion functions
-----------------------------------------------------------------------------
-- Converts a floating point number of one format into another format
function resize (
arg : UNRESOLVED_float; -- Floating point input
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant in_fraction_width : NATURAL := -arg'low; -- length of FP output fraction
constant in_exponent_width : NATURAL := arg'high; -- length of FP output exponent
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
-- result value
variable fptype : valid_fpstate;
variable expon_in : SIGNED (in_exponent_width-1 downto 0);
variable fract_in : UNSIGNED (in_fraction_width downto 0);
variable round : BOOLEAN;
variable expon_out : SIGNED (exponent_width-1 downto 0); -- output fract
variable fract_out : UNSIGNED (fraction_width downto 0); -- output fract
variable passguard : NATURAL;
begin
fptype := classfp(arg, check_error);
if ((fptype = pos_denormal or fptype = neg_denormal) and denormalize_in
and (in_exponent_width < exponent_width
or in_fraction_width < fraction_width))
or in_exponent_width > exponent_width
or in_fraction_width > fraction_width then
-- size reduction
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_inf =>
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when neg_inf =>
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
when pos_zero | neg_zero =>
result := zerofp (fraction_width => fraction_width, -- hate -0
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize_in,
fract => fract_in,
expon => expon_in);
if fraction_width > in_fraction_width and denormalize_in then
-- You only get here if you have a denormal input
fract_out := (others => '0'); -- pad with zeros
fract_out (fraction_width downto
fraction_width - in_fraction_width) := fract_in;
result := normalize (
fract => fract_out,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
else
result := normalize (
fract => fract_in,
expon => expon_in,
sign => arg(arg'high),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => in_fraction_width - fraction_width);
end if;
end case classcase;
else -- size increase or the same size
if exponent_width > in_exponent_width then
expon_in := SIGNED(arg (in_exponent_width-1 downto 0));
if fptype = pos_zero or fptype = neg_zero then
result (exponent_width-1 downto 0) := (others => '0');
elsif expon_in = -1 then -- inf or nan (shorts out check_error)
result (exponent_width-1 downto 0) := (others => '1');
else
-- invert top BIT
expon_in(expon_in'high) := not expon_in(expon_in'high);
expon_out := resize (expon_in, expon_out'length); -- signed expand
-- Flip it back.
expon_out(expon_out'high) := not expon_out(expon_out'high);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon_out);
end if;
result (exponent_width) := arg (in_exponent_width); -- sign
else -- exponent_width = in_exponent_width
result (exponent_width downto 0) := arg (in_exponent_width downto 0);
end if;
if fraction_width > in_fraction_width then
result (-1 downto -fraction_width) := (others => '0'); -- zeros
result (-1 downto -in_fraction_width) :=
arg (-1 downto -in_fraction_width);
else -- fraction_width = in_fraciton_width
result (-1 downto -fraction_width) :=
arg (-1 downto -in_fraction_width);
end if;
end if;
return result;
end function resize;
function resize (
arg : UNRESOLVED_float; -- floating point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
return result;
end if;
end function resize;
function to_float32 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float32 is
begin
return resize (arg => arg,
exponent_width => float32'high,
fraction_width => -float32'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float32;
function to_float64 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float64 is
begin
return resize (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float64;
function to_float128 (
arg : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error;
constant denormalize_in : BOOLEAN := float_denormalize; -- Use IEEE extended FP
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float128 is
begin
return resize (arg => arg,
exponent_width => float128'high,
fraction_width => -float128'low,
round_style => round_style,
check_error => check_error,
denormalize_in => denormalize_in,
denormalize => denormalize);
end function to_float128;
-- to_float (Real)
-- typically not Synthesizable unless the input is a constant.
function to_float (
arg : REAL;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_real : REAL; -- Real version of argument
variable validfp : boundary_type; -- Check for valid results
variable exp : INTEGER; -- Integer version of exponent
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable frac : REAL; -- Real version of fraction
constant roundfrac : REAL := 2.0 ** (-2 - fract'high); -- used for rounding
variable round : BOOLEAN; -- to round or not to round
begin
result := (others => '0');
arg_real := arg;
if arg_real < 0.0 then
result (exponent_width) := '1';
arg_real := - arg_real; -- Make it positive.
else
result (exponent_width) := '0';
end if;
test_boundary (arg => arg_real,
fraction_width => fraction_width,
exponent_width => exponent_width,
denormalize => denormalize,
btype => validfp,
log2i => exp);
if validfp = zero then
return result; -- Result initialized to "0".
elsif validfp = infinity then
result (exponent_width - 1 downto 0) := (others => '1'); -- Exponent all "1"
-- return infinity.
return result;
else
if validfp = denormal then -- Exponent will default to "0".
expon := (others => '0');
frac := arg_real * (2.0 ** (to_integer(expon_base)-1));
else -- Number less than 1. "normal" number
expon := UNSIGNED (to_signed (exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
frac := (arg_real / 2.0 ** exp) - 1.0; -- Number less than 1.
end if;
for i in 0 to fract'high loop
if frac >= 2.0 ** (-1 - i) then
fract (fract'high - i) := '1';
frac := frac - 2.0 ** (-1 - i);
else
fract (fract'high - i) := '0';
end if;
end loop;
round := false;
case round_style is
when round_nearest =>
if frac > roundfrac or ((frac = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if frac /= 0.0 and result(exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if frac /= 0.0 and result(exponent_width) = '1' then
round := true;
end if;
when others =>
null; -- don't round
end case;
if (round) then
if and_reduce (fract) = '1' then -- fraction is all "1"
expon := expon + 1;
fract := (others => '0');
else
fract := fract + 1;
end if;
end if;
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
return result;
end if;
end function to_float;
-- to_float (Integer)
function to_float (
arg : INTEGER;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : NATURAL; -- Natural version of argument
variable expon : SIGNED (exponent_width-1 downto 0);
variable exptmp : SIGNED (exponent_width-1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract : UNSIGNED (fraction_width-1 downto 0) := (others => '0');
variable fracttmp : UNSIGNED (fraction_width-1 downto 0);
variable round : BOOLEAN;
variable shift : NATURAL;
variable shiftr : NATURAL;
variable roundfrac : NATURAL; -- used in rounding
begin
if arg < 0 then
result (exponent_width) := '1';
arg_int := -arg; -- Make it positive.
else
result (exponent_width) := '0';
arg_int := arg;
end if;
if arg_int = 0 then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- If the number is larger than we can represent in this number system
-- we need to return infinity.
shift := log2(arg_int);
if shift > to_integer(expon_base) then
-- worry about infinity
if result (exponent_width) = '0' then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
-- return negative infinity.
result := neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
end if;
else -- Normal number (can't be denormal)
-- Compute Exponent
expon := to_signed (shift-1, expon'length); -- positive fraction.
-- Compute Fraction
arg_int := arg_int - 2**shift; -- Subtract off the 1.0
shiftr := shift;
for I in fract'high downto maximum (fract'high - shift + 1, 0) loop
shiftr := shiftr - 1;
if (arg_int >= 2**shiftr) then
arg_int := arg_int - 2**shiftr;
fract(I) := '1';
else
fract(I) := '0';
end if;
end loop;
-- Rounding routine
round := false;
if arg_int > 0 then
roundfrac := 2**(shiftr-1);
case round_style is
when round_nearest =>
if arg_int > roundfrac or
((arg_int = roundfrac) and fract(0) = '1') then
round := true;
end if;
when round_inf =>
if arg_int /= 0 and result (exponent_width) = '0' then
round := true;
end if;
when round_neginf =>
if arg_int /= 0 and result (exponent_width) = '1' then
round := true;
end if;
when others =>
null;
end case;
end if;
if round then
fp_round(fract_in => fract,
expon_in => expon,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
expon := exptmp;
end if;
-- Put the number together and return
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
end if;
return result;
end function to_float;
-- to_float (unsigned)
function to_float (
arg : UNSIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable sarg : SIGNED (ARG_LEFT+1 downto 0); -- signed version of arg
begin
if arg'length < 1 then
return NAFP;
end if;
sarg (XARG'range) := SIGNED (XARG);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style);
return result;
end function to_float;
-- to_float (signed)
function to_float (
arg : SIGNED;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable arg_int : UNSIGNED(xarg'range); -- Real version of argument
variable argb2 : UNSIGNED(xarg'high/2 downto 0); -- log2 of input
variable rexp : SIGNED (exponent_width - 1 downto 0);
variable exp : SIGNED (exponent_width - 1 downto 0);
-- signed version of exp.
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable round : BOOLEAN;
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable rfract : UNSIGNED (fraction_width-1 downto 0);
variable sign : STD_ULOGIC; -- sign bit
begin
if arg'length < 1 then
return NAFP;
end if;
if Is_X (xarg) then
result := (others => 'X');
elsif (xarg = 0) then
result := zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else -- Normal number (can't be denormal)
sign := to_X01(xarg (xarg'high));
arg_int := UNSIGNED(abs (to_01(xarg)));
-- Compute Exponent
argb2 := to_unsigned(find_leftmost(arg_int, '1'), argb2'length); -- Log2
if argb2 > UNSIGNED(expon_base) then
result := pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
result (exponent_width) := sign;
else
exp := SIGNED(resize(argb2, exp'length));
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract (0),
sign => sign,
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if round then
fp_round(fract_in => fract,
expon_in => exp,
fract_out => rfract,
expon_out => rexp);
else
rfract := fract;
rexp := exp;
end if;
else
rexp := exp;
rfract := (others => '0');
rfract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
result (exponent_width) := sign;
expon := UNSIGNED (rexp-1);
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(rfract);
end if;
end if;
return result;
end function to_float;
-- std_logic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
variable fpvar : UNRESOLVED_float (exponent_width downto -fraction_width);
begin
if arg'length < 1 then
return NAFP;
end if;
fpvar := UNRESOLVED_float(arg);
return fpvar;
end function to_float;
-- purpose: converts a ufixed to a floating point
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
constant exponent_width : NATURAL := float_exponent_width; -- width of exponent
constant fraction_width : NATURAL := float_fraction_width; -- width of fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable sarg : sfixed (arg'high+1 downto arg'low); -- Signed version of arg
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
begin -- function to_float
if (arg'length < 1) then
return NAFP;
end if;
sarg (arg'range) := sfixed (arg);
sarg (sarg'high) := '0';
result := to_float (arg => sarg,
exponent_width => exponent_width,
fraction_width => fraction_width,
round_style => round_style,
denormalize => denormalize);
return result;
end function to_float;
function to_float (
arg : UNRESOLVED_sfixed; -- signed fixed point
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width; -- length of FP output fraction
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
constant integer_width : INTEGER := arg'high;
constant in_fraction_width : INTEGER := arg'low;
variable xresult : sfixed (integer_width downto in_fraction_width);
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable arg_int : UNSIGNED(integer_width - in_fraction_width
downto 0); -- unsigned version of argument
variable argx : SIGNED (integer_width - in_fraction_width downto 0);
variable exp, exptmp : SIGNED (exponent_width downto 0);
variable expon : UNSIGNED (exponent_width - 1 downto 0);
-- Unsigned version of exp.
constant expon_base : SIGNED (exponent_width-1 downto 0) :=
gen_expon_base(exponent_width); -- exponent offset
variable fract, fracttmp : UNSIGNED (fraction_width-1 downto 0) :=
(others => '0');
variable round : BOOLEAN := false;
begin
if (arg'length < 1) then
return NAFP;
end if;
xresult := to_01(arg, 'X');
argx := SIGNED(to_slv(xresult));
if (Is_X (arg)) then
result := (others => 'X');
elsif (argx = 0) then
result := (others => '0');
else
result := (others => '0'); -- zero out the result
if argx(argx'left) = '1' then -- toss the sign bit
result (exponent_width) := '1'; -- Negative number
arg_int := UNSIGNED(to_x01(not STD_LOGIC_VECTOR (argx))) + 1; -- Make it positive with two's complement
else
result (exponent_width) := '0';
arg_int := UNSIGNED(to_x01(STD_LOGIC_VECTOR (argx))); -- new line: direct conversion to unsigned
end if;
-- Compute Exponent
exp := to_signed(find_leftmost(arg_int, '1'), exp'length); -- Log2
if exp + in_fraction_width > expon_base then -- return infinity
result (-1 downto -fraction_width) := (others => '0');
result (exponent_width -1 downto 0) := (others => '1');
return result;
elsif (denormalize and
(exp + in_fraction_width <= -resize(expon_base, exp'length))) then
exp := -resize(expon_base, exp'length);
-- shift by a constant
arg_int := shift_left (arg_int,
(arg_int'high + to_integer(expon_base)
+ in_fraction_width - 1));
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => arg_int(arg_int'high-fraction_width),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => arg_int (arg_int'high-1 downto
(arg_int'high-fraction_width)),
expon_in => exp,
fract_out => fract,
expon_out => exptmp);
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
else
arg_int := shift_left (arg_int, arg_int'high-to_integer(exp));
exp := exp + in_fraction_width;
if (arg_int'high > fraction_width) then
fract := arg_int (arg_int'high-1 downto (arg_int'high-fraction_width));
round := check_round (
fract_in => fract(0),
sign => result(result'high),
remainder => arg_int((arg_int'high-fraction_width-1)
downto 0),
round_style => round_style);
if (round) then
fp_round (fract_in => fract,
expon_in => exp,
fract_out => fracttmp,
expon_out => exptmp);
fract := fracttmp;
exp := exptmp;
end if;
else
fract (fraction_width-1 downto fraction_width-1-(arg_int'high-1)) :=
arg_int (arg_int'high-1 downto 0);
end if;
end if;
expon := UNSIGNED (resize(exp-1, exponent_width));
expon(exponent_width-1) := not expon(exponent_width-1);
result (exponent_width-1 downto 0) := UNRESOLVED_float(expon);
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
end if;
return result;
end function to_float;
-- size_res functions
-- Integer to float
function to_float (
arg : INTEGER;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- real to float
function to_float (
arg : REAL;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding option
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- unsigned to float
function to_float (
arg : UNSIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- signed to float
function to_float (
arg : SIGNED;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style) -- rounding
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style);
return result;
end if;
end function to_float;
-- std_ulogic_vector to float
function to_float (
arg : STD_ULOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low);
return result;
end if;
end function to_float;
-- unsigned fixed point to float
function to_float (
arg : UNRESOLVED_ufixed; -- unsigned fixed point input
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- use ieee extensions
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- signed fixed point to float
function to_float (
arg : UNRESOLVED_sfixed;
size_res : UNRESOLVED_float;
constant round_style : round_type := float_round_style; -- rounding
constant denormalize : BOOLEAN := float_denormalize) -- rounding option
return UNRESOLVED_float is
variable result : UNRESOLVED_float (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_float (arg => arg,
exponent_width => size_res'high,
fraction_width => -size_res'low,
round_style => round_style,
denormalize => denormalize);
return result;
end if;
end function to_float;
-- to_integer (float)
function to_integer (
arg : UNRESOLVED_float; -- floating point input
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return INTEGER is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (-arg'low downto 0); -- Fraction
variable fract : UNSIGNED (1-arg'low downto 0); -- Fraction
variable expon : SIGNED (arg'high-1 downto 0);
variable isign : STD_ULOGIC; -- internal version of sign
variable round : STD_ULOGIC; -- is rounding needed?
variable result : INTEGER;
variable base : INTEGER; -- Integer exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan | pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := 0; -- return 0
when pos_inf =>
result := INTEGER'high;
when neg_inf =>
result := INTEGER'low;
when others =>
break_number (
arg => arg,
fptyp => validfp,
denormalize => false,
fract => frac,
expon => expon);
fract (fract'high) := '0'; -- Add extra bit for 0.6 case
fract (fract'high-1 downto 0) := frac;
isign := to_x01 (arg (arg'high));
base := to_integer (expon) + 1;
if base < -1 then
result := 0;
elsif base >= frac'high then
result := to_integer (fract) * 2**(base - frac'high);
else -- We need to round
if base = -1 then -- trap for 0.6 case.
result := 0;
else
result := to_integer (fract (frac'high downto frac'high-base));
end if;
-- rounding routine
case round_style is
when round_nearest =>
if frac'high - base > 1 then
round := fract (frac'high - base - 1) and
(fract (frac'high - base)
or (or_reduce (fract (frac'high - base - 2 downto 0))));
else
round := fract (frac'high - base - 1) and
fract (frac'high - base);
end if;
when round_inf =>
round := fract(frac'high - base - 1) and not isign;
when round_neginf =>
round := fract(frac'high - base - 1) and isign;
when others =>
round := '0';
end case;
if round = '1' then
result := result + 1;
end if;
end if;
if isign = '1' then
result := - result;
end if;
end case classcase;
return result;
end function to_integer;
-- to_unsigned (float)
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable sign : STD_ULOGIC; -- not used
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | pos_denormal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1');
when others =>
float_to_unsigned (
arg => arg,
frac => frac,
sign => sign,
denormalize => false,
bias => 0,
round_style => round_style);
end case classcase;
return (frac);
end function to_unsigned;
-- to_signed (float)
function to_signed (
arg : UNRESOLVED_float; -- floating point input
constant size : NATURAL; -- length of output
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable sign : STD_ULOGIC; -- true if negative
variable validfp : valid_fpstate; -- Valid FP state
variable frac : UNSIGNED (size-1 downto 0); -- Fraction
variable result : SIGNED (size-1 downto 0);
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero | pos_denormal | neg_denormal =>
result := (others => '0'); -- return 0
when pos_inf =>
result := (others => '1');
result (result'high) := '0';
when neg_inf =>
result := (others => '0');
result (result'high) := '1';
when others =>
float_to_unsigned (
arg => arg,
sign => sign,
frac => frac,
denormalize => false,
bias => 0,
round_style => round_style);
result (size-1) := '0';
result (size-2 downto 0) := SIGNED(frac (size-2 downto 0));
if sign = '1' then
-- Because the most negative signed number is 1 less than the most
-- positive signed number, we need this code.
if frac(frac'high) = '1' then -- return most negative number
result := (others => '0');
result (result'high) := '1';
else
result := -result;
end if;
else
if frac(frac'high) = '1' then -- return most positive number
result := (others => '1');
result (result'high) := '0';
end if;
end if;
end case classcase;
return result;
end function to_signed;
-- purpose: Converts a float to ufixed
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-1 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-1 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable result_big : UNRESOLVED_ufixed (left_index downto right_index-3);
variable result : UNRESOLVED_ufixed (left_index downto right_index); -- result
begin -- function to_ufixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
frac := (others => 'X');
when pos_zero | neg_inf | neg_zero | neg_normal | neg_denormal =>
frac := (others => '0'); -- return 0
when pos_inf =>
frac := (others => '1'); -- always saturate
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
-- Figure out the fraction
if (validfp = pos_denormal) and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Remove the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
end case classcase;
result_big := to_ufixed (
arg => STD_ULOGIC_VECTOR(frac),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- purpose: Converts a float to sfixed
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
constant left_index : INTEGER; -- integer part
constant right_index : INTEGER; -- fraction part
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
constant size : INTEGER := left_index - right_index + 4; -- unsigned size
variable expon_base : INTEGER; -- exponent offset
variable validfp : valid_fpstate; -- Valid FP state
variable exp : INTEGER; -- Exponent
variable sign : BOOLEAN; -- true if negative
variable expon : UNSIGNED (exponent_width-1 downto 0); -- Vectorized exponent
-- Base to divide fraction by
variable frac : UNSIGNED (size-2 downto 0) := (others => '0'); -- Fraction
variable frac_shift : UNSIGNED (size-2 downto 0); -- Fraction shifted
variable shift : INTEGER;
variable rsigned : SIGNED (size-1 downto 0); -- signed version of result
variable result_big : UNRESOLVED_sfixed (left_index downto right_index-3);
variable result : UNRESOLVED_sfixed (left_index downto right_index)
:= (others => '0'); -- result
begin -- function to_sfixed
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | nan | quiet_nan =>
result := (others => 'X');
when pos_zero | neg_zero =>
result := (others => '0'); -- return 0
when neg_inf =>
result (left_index) := '1'; -- return smallest negative number
when pos_inf =>
result := (others => '1'); -- return largest number
result (left_index) := '0';
when others =>
expon_base := 2**(exponent_width-1) -1; -- exponent offset
if arg(exponent_width) = '0' then
sign := false;
else
sign := true;
end if;
-- Figure out the fraction
if (validfp = pos_denormal or validfp = neg_denormal)
and denormalize then
exp := -expon_base +1;
frac (frac'high) := '0'; -- Add the "1.0".
else
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
frac (frac'high) := '1'; -- Add the "1.0".
end if;
shift := (frac'high - 3 + right_index) - exp;
if fraction_width > frac'high then -- Can only use size-2 bits
frac (frac'high-1 downto 0) := UNSIGNED (to_slv (arg(-1 downto
-frac'high)));
else -- can use all bits
frac (frac'high-1 downto frac'high-fraction_width) :=
UNSIGNED (to_slv (arg(-1 downto -fraction_width)));
end if;
frac_shift := frac srl shift;
if shift < 0 then -- Overflow
frac := (others => '1');
else
frac := frac_shift;
end if;
if not sign then
rsigned := SIGNED("0" & frac);
else
rsigned := -(SIGNED("0" & frac));
end if;
result_big := to_sfixed (
arg => STD_LOGIC_VECTOR(rsigned),
left_index => left_index,
right_index => (right_index-3));
result := resize (arg => result_big,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
end case classcase;
return result;
end function to_sfixed;
-- size_res versions
-- float to unsigned
function to_unsigned (
arg : UNRESOLVED_float; -- floating point input
size_res : UNSIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return UNSIGNED is
variable result : UNSIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_unsigned (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_unsigned;
-- float to signed
function to_signed (
arg : UNRESOLVED_float; -- floating point input
size_res : SIGNED;
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error) -- check for errors
return SIGNED is
variable result : SIGNED (size_res'range);
begin
if (SIZE_RES'length = 0) then
return result;
else
result := to_signed (
arg => arg,
size => size_res'length,
round_style => round_style,
check_error => check_error);
return result;
end if;
end function to_signed;
-- purpose: Converts a float to unsigned fixed point
function to_ufixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_ufixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_ufixed;
-- float to signed fixed point
function to_sfixed (
arg : UNRESOLVED_float; -- fp input
size_res : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style; -- saturate
constant round_style : fixed_round_style_type := fixed_round_style; -- rounding
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (
arg => arg,
left_index => size_res'high,
right_index => size_res'low,
overflow_style => overflow_style,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
return result;
end if;
end function to_sfixed;
-- to_real (float)
-- typically not Synthesizable unless the input is a constant.
function to_real (
arg : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return REAL is
constant fraction_width : INTEGER := -mine(arg'low, arg'low); -- length of FP output fraction
constant exponent_width : INTEGER := arg'high; -- length of FP output exponent
variable sign : REAL; -- Sign, + or - 1
variable exp : INTEGER; -- Exponent
variable expon_base : INTEGER; -- exponent offset
variable frac : REAL := 0.0; -- Fraction
variable validfp : valid_fpstate; -- Valid FP state
variable expon : UNSIGNED (exponent_width - 1 downto 0)
:= (others => '1'); -- Vectorized exponent
begin
validfp := classfp (arg, check_error);
classcase : case validfp is
when isx | pos_zero | neg_zero | nan | quiet_nan =>
return 0.0;
when neg_inf =>
return REAL'low; -- Negative infinity.
when pos_inf =>
return REAL'high; -- Positive infinity
when others =>
expon_base := 2**(exponent_width-1) -1;
if to_X01(arg(exponent_width)) = '0' then
sign := 1.0;
else
sign := -1.0;
end if;
-- Figure out the fraction
for i in 0 to fraction_width-1 loop
if to_X01(arg (-1 - i)) = '1' then
frac := frac + (2.0 **(-1 - i));
end if;
end loop; -- i
if validfp = pos_normal or validfp = neg_normal or not denormalize then
-- exponent /= '0', normal floating point
expon := UNSIGNED(arg (exponent_width-1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
exp := to_integer (SIGNED(expon)) +1;
sign := sign * (2.0 ** exp) * (1.0 + frac);
else -- exponent = '0', IEEE extended floating point
exp := 1 - expon_base;
sign := sign * (2.0 ** exp) * frac;
end if;
return sign;
end case classcase;
end function to_real;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_ULOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_sulv (result);
end function realtobits;
function bitstoreal (arg : STD_ULOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
-- purpose: Removes meta-logical values from FP string
function to_01 (
arg : UNRESOLVED_float; -- floating point input
XMAP : STD_LOGIC := '0')
return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin -- function to_01
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_01: null detected, returning NULL"
severity warning;
return NAFP;
end if;
result := UNRESOLVED_float (STD_LOGIC_VECTOR(to_01(UNSIGNED(to_slv(arg)), XMAP)));
return result;
end function to_01;
function Is_X
(arg : UNRESOLVED_float)
return BOOLEAN is
begin
return Is_X (to_slv(arg));
end function Is_X;
function to_X01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01(to_slv(arg)));
return result;
end if;
end function to_X01;
function to_X01Z (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_X01Z: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_X01Z(to_slv(arg)));
return result;
end if;
end function to_X01Z;
function to_UX01 (arg : UNRESOLVED_float) return UNRESOLVED_float is
variable result : UNRESOLVED_float (arg'range);
begin
if (arg'length < 1) then
assert NO_WARNING
report float_pkg'instance_name
& "TO_UX01: null detected, returning NULL"
severity warning;
return NAFP;
else
result := UNRESOLVED_float (to_UX01(to_slv(arg)));
return result;
end if;
end function to_UX01;
-- These allows the base math functions to use the default values
-- of their parameters. Thus they do full IEEE floating point.
function "+" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return add (l, r);
end function "+";
function "-" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return subtract (l, r);
end function "-";
function "*" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return multiply (l, r);
end function "*";
function "/" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return divide (l, r);
end function "/";
function "rem" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return remainder (l, r);
end function "rem";
function "mod" (l, r : UNRESOLVED_float) return UNRESOLVED_float is
begin
return modulo (l, r);
end function "mod";
-- overloaded versions
function "+" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "+" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return add (l, r_float);
end function "+";
function "+" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return add (l_float, r);
end function "+";
function "-" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "-" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return subtract (l, r_float);
end function "-";
function "-" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return subtract (l_float, r);
end function "-";
function "*" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "*" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return multiply (l, r_float);
end function "*";
function "*" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return multiply (l_float, r);
end function "*";
function "/" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "/" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return divide (l, r_float);
end function "/";
function "/" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return divide (l_float, r);
end function "/";
function "rem" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "rem" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return remainder (l, r_float);
end function "rem";
function "rem" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return remainder (l_float, r);
end function "rem";
function "mod" (l : UNRESOLVED_float; r : REAL) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : REAL; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "mod" (l : UNRESOLVED_float; r : INTEGER) return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return modulo (l, r_float);
end function "mod";
function "mod" (l : INTEGER; r : UNRESOLVED_float) return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return modulo (l_float, r);
end function "mod";
function "=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : REAL) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : REAL; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
function "=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return eq (l, r_float);
end function "=";
function "/=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ne (l, r_float);
end function "/=";
function ">=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return ge (l, r_float);
end function ">=";
function "<=" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return le (l, r_float);
end function "<=";
function ">" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return gt (l, r_float);
end function ">";
function "<" (l : UNRESOLVED_float; r : INTEGER) return BOOLEAN is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return lt (l, r_float);
end function "<";
function "=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return eq (l_float, r);
end function "=";
function "/=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ne (l_float, r);
end function "/=";
function ">=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return ge (l_float, r);
end function ">=";
function "<=" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return le (l_float, r);
end function "<=";
function ">" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return gt (l_float, r);
end function ">";
function "<" (l : INTEGER; r : UNRESOLVED_float) return BOOLEAN is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float(l, r'high, -r'low);
return lt (l_float, r);
end function "<";
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : REAL) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- real and float
function \?=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : REAL; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- ?= overloads
function \?=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?=\ (l, r_float);
end function \?=\;
function \?/=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?/=\ (l, r_float);
end function \?/=\;
function \?>\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>\ (l, r_float);
end function \?>\;
function \?>=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?>=\ (l, r_float);
end function \?>=\;
function \?<\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<\ (l, r_float);
end function \?<\;
function \?<=\ (l : UNRESOLVED_float; r : INTEGER) return STD_ULOGIC is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return \?<=\ (l, r_float);
end function \?<=\;
-- integer and float
function \?=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?=\ (l_float, r);
end function \?=\;
function \?/=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?/=\ (l_float, r);
end function \?/=\;
function \?>\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>\ (l_float, r);
end function \?>\;
function \?>=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?>=\ (l_float, r);
end function \?>=\;
function \?<\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<\ (l_float, r);
end function \?<\;
function \?<=\ (l : INTEGER; r : UNRESOLVED_float) return STD_ULOGIC is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return \?<=\ (l_float, r);
end function \?<=\;
-- minimum and maximum overloads
function minimum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : REAL)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : REAL; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
function minimum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return minimum (l, r_float);
end function minimum;
function maximum (l : UNRESOLVED_float; r : INTEGER)
return UNRESOLVED_float is
variable r_float : UNRESOLVED_float (l'range);
begin
r_float := to_float (r, l'high, -l'low);
return maximum (l, r_float);
end function maximum;
function minimum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return minimum (l_float, r);
end function minimum;
function maximum (l : INTEGER; r : UNRESOLVED_float)
return UNRESOLVED_float is
variable l_float : UNRESOLVED_float (r'range);
begin
l_float := to_float (l, r'high, -r'low);
return maximum (l_float, r);
end function maximum;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_float (RESULT, L'high, -L'low);
end function "not";
function "and" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "and";
function "or" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_float) return UNRESOLVED_float is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report float_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_float (RESULT, L'high, -L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_float)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_float; R : STD_ULOGIC)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces, same as numeric_std functions
function and_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_float) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-----------------------------------------------------------------------------
-- Recommended Functions from the IEEE 754 Appendix
-----------------------------------------------------------------------------
-- returns x with the sign of y.
function Copysign (
x, y : UNRESOLVED_float) -- floating point input
return UNRESOLVED_float is
begin
return y(y'high) & x (x'high-1 downto x'low);
end function Copysign;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : INTEGER; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(y'low, y'low); -- length of FP output fraction
constant exponent_width : NATURAL := y'high; -- length of FP output exponent
variable arg, result : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width-1 downto 0); -- Vectorized exp
variable exp : SIGNED (exponent_width downto 0);
variable ufract : UNSIGNED (fraction_width downto 0);
constant expon_base : SIGNED (exponent_width-1 downto 0)
:= gen_expon_base(exponent_width); -- exponent offset
variable fptype : valid_fpstate;
begin
-- This can be done by simply adding N to the exponent.
arg := to_01 (y, 'X');
fptype := classfp(arg, check_error);
classcase : case fptype is
when isx =>
result := (others => 'X');
when nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
when others =>
break_number (
arg => arg,
fptyp => fptype,
denormalize => denormalize,
fract => ufract,
expon => expon);
exp := resize (expon, exp'length) + N;
result := normalize (
fract => ufract,
expon => exp,
sign => to_x01 (arg (arg'high)),
fraction_width => fraction_width,
exponent_width => exponent_width,
round_style => round_style,
denormalize => denormalize,
nguard => 0);
end case classcase;
return result;
end function Scalb;
-- Returns y * 2**n for integral values of N without computing 2**n
function Scalb (
y : UNRESOLVED_float; -- floating point input
N : SIGNED; -- exponent to add
constant round_style : round_type := float_round_style; -- rounding option
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize) -- Use IEEE extended FP
return UNRESOLVED_float is
variable n_int : INTEGER;
begin
n_int := to_integer(N);
return Scalb (y => y,
N => n_int,
round_style => round_style,
check_error => check_error,
denormalize => denormalize);
end function Scalb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return INTEGER is
constant fraction_width : NATURAL := -mine (x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : INTEGER; -- result
variable arg : UNRESOLVED_float (exponent_width downto -fraction_width); -- internal argument
variable expon : SIGNED (exponent_width - 1 downto 0);
variable fract : UNSIGNED (fraction_width downto 0);
constant expon_base : INTEGER := 2**(exponent_width-1) -1; -- exponent
-- offset +1
variable fptype : valid_fpstate;
begin
-- Just return the exponent.
arg := to_01 (x, 'X');
fptype := classfp(arg);
classcase : case fptype is
when isx | nan | quiet_nan =>
-- Return quiet NAN, IEEE754-1985-7.1,1
result := 0;
when pos_denormal | neg_denormal =>
fract (fraction_width) := '0';
fract (fraction_width-1 downto 0) :=
UNSIGNED (to_slv(arg(-1 downto -fraction_width)));
result := find_leftmost (fract, '1') -- Find the first "1"
- fraction_width; -- subtract the length we want
result := -expon_base + 1 + result;
when others =>
expon := SIGNED(arg (exponent_width - 1 downto 0));
expon(exponent_width-1) := not expon(exponent_width-1);
expon := expon + 1;
result := to_integer (expon);
end case classcase;
return result;
end function Logb;
-- returns the unbiased exponent of x
function Logb (
x : UNRESOLVED_float) -- floating point input
return SIGNED is
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
variable result : SIGNED (exponent_width - 1 downto 0); -- result
begin
-- Just return the exponent.
result := to_signed (Logb (x), exponent_width);
return result;
end function Logb;
-- returns the next representable neighbor of x in the direction toward y
function Nextafter (
x, y : UNRESOLVED_float; -- floating point input
constant check_error : BOOLEAN := float_check_error; -- check for errors
constant denormalize : BOOLEAN := float_denormalize)
return UNRESOLVED_float is
constant fraction_width : NATURAL := -mine(x'low, x'low); -- length of FP output fraction
constant exponent_width : NATURAL := x'high; -- length of FP output exponent
function "=" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function "="
return eq (l => l,
r => r,
check_error => false);
end function "=";
function ">" (
l, r : UNRESOLVED_float) -- inputs
return BOOLEAN is
begin -- function ">"
return gt (l => l,
r => r,
check_error => false);
end function ">";
variable fract : UNSIGNED (fraction_width-1 downto 0);
variable expon : UNSIGNED (exponent_width-1 downto 0);
variable sign : STD_ULOGIC;
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable validfpx, validfpy : valid_fpstate; -- Valid FP state
begin -- fp_Nextafter
-- If Y > X, add one to the fraction, otherwise subtract.
validfpx := classfp (x, check_error);
validfpy := classfp (y, check_error);
if validfpx = isx or validfpy = isx then
result := (others => 'X');
return result;
elsif (validfpx = nan or validfpy = nan) then
return nanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif (validfpx = quiet_nan or validfpy = quiet_nan) then
return qnanfp (fraction_width => fraction_width,
exponent_width => exponent_width);
elsif x = y then -- Return X
return x;
else
fract := UNSIGNED (to_slv (x (-1 downto -fraction_width))); -- Fraction
expon := UNSIGNED (x (exponent_width - 1 downto 0)); -- exponent
sign := x(exponent_width); -- sign bit
if (y > x) then
-- Increase the number given
if validfpx = neg_inf then
-- return most negative number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero or validfpx = neg_zero then
-- return smallest denormal number
sign := '0';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = pos_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return pos_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1;
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = pos_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = neg_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest negative denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = neg_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
else
-- Decrease the number
if validfpx = pos_inf then
-- return most positive number
expon := (others => '1');
expon (0) := '0';
fract := (others => '1');
elsif validfpx = pos_zero
or classfp (x) = neg_zero then
-- return smallest negative denormal number
sign := '1';
expon := (others => '0');
fract := (others => '0');
fract(0) := '1';
elsif validfpx = neg_normal then
if and_reduce (fract) = '1' then -- fraction is all "1".
if and_reduce (expon (exponent_width-1 downto 1)) = '1'
and expon (0) = '0' then
-- Exponent is one away from infinity.
assert NO_WARNING
report float_pkg'instance_name
& "FP_NEXTAFTER: NextAfter overflow"
severity warning;
return neg_inffp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
expon := expon + 1; -- Fraction overflow
fract := (others => '0');
end if;
else
fract := fract + 1;
end if;
elsif validfpx = neg_denormal then
if and_reduce (fract) = '1' then -- fraction is all "1".
-- return smallest possible normal number
expon := (others => '0');
expon(0) := '1';
fract := (others => '0');
else
fract := fract + 1;
end if;
elsif validfpx = pos_normal then
if or_reduce (fract) = '0' then -- fraction is all "0".
if or_reduce (expon (exponent_width-1 downto 1)) = '0' and
expon (0) = '1' then -- Smallest exponent
-- return the largest positive denormal number
expon := (others => '0');
fract := (others => '1');
else
expon := expon - 1;
fract := (others => '1');
end if;
else
fract := fract - 1;
end if;
elsif validfpx = pos_denormal then
if or_reduce (fract(fract'high downto 1)) = '0'
and fract (0) = '1' then -- Smallest possible fraction
return zerofp (fraction_width => fraction_width,
exponent_width => exponent_width);
else
fract := fract - 1;
end if;
end if;
end if;
result (-1 downto -fraction_width) := UNRESOLVED_float(fract);
result (exponent_width -1 downto 0) := UNRESOLVED_float(expon);
result (exponent_width) := sign;
return result;
end if;
end function Nextafter;
-- Returns True if X is unordered with Y.
function Unordered (
x, y : UNRESOLVED_float) -- floating point input
return BOOLEAN is
variable lfptype, rfptype : valid_fpstate;
begin
lfptype := classfp (x);
rfptype := classfp (y);
if (lfptype = nan or lfptype = quiet_nan or
rfptype = nan or rfptype = quiet_nan or
lfptype = isx or rfptype = isx) then
return true;
else
return false;
end if;
end function Unordered;
function Finite (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = pos_inf) or (fp_state = neg_inf) then
return true;
else
return false;
end if;
end function Finite;
function Isnan (
x : UNRESOLVED_float)
return BOOLEAN is
variable fp_state : valid_fpstate; -- fp state
begin
fp_state := Classfp (x);
if (fp_state = nan) or (fp_state = quiet_nan) then
return true;
else
return false;
end if;
end function Isnan;
-- Function to return constants.
function zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
constant result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
return result;
end function zerofp;
function nanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-1) := '1'; -- MSB of Fraction "1"
-- Note: From W. Khan "IEEE Standard 754 for Binary Floating Point"
-- The difference between a signaling NAN and a quiet NAN is that
-- the MSB of the Fraction is a "1" in a Signaling NAN, and is a
-- "0" in a quiet NAN.
return result;
end function nanfp;
function qnanfp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1');
-- Exponent all "1"
result (-fraction_width) := '1'; -- LSB of Fraction "1"
-- (Could have been any bit)
return result;
end function qnanfp;
function pos_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width-1 downto 0) := (others => '1'); -- Exponent all "1"
return result;
end function pos_inffp;
function neg_inffp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width downto 0) := (others => '1'); -- top bits all "1"
return result;
end function neg_inffp;
function neg_zerofp (
constant exponent_width : NATURAL := float_exponent_width; -- exponent
constant fraction_width : NATURAL := float_fraction_width) -- fraction
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width) :=
(others => '0'); -- zero
begin
result (exponent_width) := '1';
return result;
end function neg_zerofp;
-- size_res versions
function zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function zerofp;
function nanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return nanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function nanfp;
function qnanfp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return qnanfp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function qnanfp;
function pos_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return pos_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function pos_inffp;
function neg_inffp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_inffp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_inffp;
function neg_zerofp (
size_res : UNRESOLVED_float) -- variable is only use for sizing
return UNRESOLVED_float is
begin
return neg_zerofp (
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function neg_zerofp;
-- rtl_synthesis off
-- pragma synthesis_off
--%%% these functions are copied from std_logic_1164 (VHDL-200X edition)
-- Textio functions
-- purpose: writes float into a line (NOTE changed basetype)
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
-- %%% Replicated textio functions
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report float_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
-- %%% END replicated textio functions
-- purpose: Checks the punctuation in a line
procedure check_punctuation (
arg : in STRING;
colon : out BOOLEAN; -- There was a colon in the line
dot : out BOOLEAN; -- There was a dot in the line
good : out BOOLEAN; -- True if enough characters found
chars : in INTEGER) is
-- Examples. Legal inputs are "0000000", "0000.000", "0:000:000"
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable icolon, idot : BOOLEAN; -- internal
variable j : INTEGER := 0; -- charters read
begin
good := false;
icolon := false;
idot := false;
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j = chars then
exit;
elsif xarg(i) = ':' then
icolon := true;
elsif xarg(i) = '.' then
idot := true;
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
if j = chars then
good := true; -- There are enough charactes to read
end if;
colon := icolon;
if idot and icolon then
dot := false;
else
dot := idot;
end if;
end procedure check_punctuation;
-- purpose: Searches a line for a ":" and replaces it with a ".".
procedure fix_colon (
arg : inout STRING;
chars : in integer) is
alias xarg : STRING (1 to arg'length) is arg; -- make it downto range
variable j : INTEGER := 0; -- charters read
begin
for i in 1 to arg'length loop
if xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT or j > chars then
exit;
elsif xarg(i) = ':' then
xarg (i) := '.';
elsif xarg (i) /= '_' then
j := j + 1;
end if;
end loop;
end procedure fix_colon;
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_float; -- floating point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
WRITE (L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable readOk : BOOLEAN;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report float_pkg'instance_name
& "READ(float): "
& "Error end of file encountered."
severity error;
return;
elsif c = ' ' or c = CR or c = HT then -- reading done.
if (i /= value'low) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Value truncated."
severity warning;
return;
end if;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
report float_pkg'instance_name
& "READ(float): "
& "String begins with an ""_""" severity error;
return;
elsif lastu then -- "__" detected
report float_pkg'instance_name
& "READ(float): "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
if not (i = -1 or i = value'high-1) then
report float_pkg'instance_name
& "READ(float): "
& "Warning: Separator point does not match number format: '"
& c & "' encountered at location " & INTEGER'image(i) & "."
severity warning;
end if;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
report float_pkg'instance_name
& "READ(float): "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
-- Possible data: 0:0000:0000000
-- 000000000000
variable c : CHARACTER;
variable mv : UNRESOLVED_float (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
READ (l, c, readOk);
if VALUE'length > 0 then
i := value'high;
good := false;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
return;
elsif c = ' ' or c = CR or c = HT then -- reading done
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = ':' or c = '.' then -- separator, ignore
-- good := (i = -1 or i = value'high-1);
lastu := false;
elsif (char_to_MVL9plus(c) = error) then
return;
else
mv (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
READ (l, c, readOk);
end loop readloop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure OWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_ostring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure OWRITE;
procedure OREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/3)
& " valid octal characters."
severity error;
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "OREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (2 downto 1) /= "00" then
report float_pkg'instance_name & "OREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "OREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "OREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "OREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+2)/3) * 3; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/3);
if not ok then
return;
elsif dot then
OREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
OREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (2 downto 1) /= "00" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/3); -- replaces the colon with a ".".
OREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
OREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure OREAD;
procedure HWRITE (
L : inout LINE; -- access type (pointer)
VALUE : in UNRESOLVED_float; -- value to write
JUSTIFIED : in SIDE := right; -- which side to justify text
FIELD : in WIDTH := 0) is -- width of field
begin
WRITE (L => L,
VALUE => to_hstring(VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure HWRITE;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "short string encounted: " & L.all
& " needs to have " & integer'image (ne/4)
& " valid hex characters."
severity error;
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
report float_pkg'instance_name & "HREAD: "
& "End of string encountered"
severity error;
return;
elsif nybble (3 downto 1) /= "000" then
report float_pkg'instance_name & "HREAD: "
& "Illegal sign bit STRING encounted "
severity error;
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
report float_pkg'instance_name & "HREAD: "
& "error encounted reading STRING " & L.all
severity error;
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
report float_pkg'instance_name & "HREAD: "
& "Error encounted during read"
severity error;
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
report float_pkg'instance_name & "HREAD: "
& "Vector truncated."
severity error;
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNRESOLVED_float; GOOD : out BOOLEAN) is
constant ne : INTEGER := ((value'length+3)/4) * 4; -- pad
variable slv : STD_LOGIC_VECTOR (ne-1 downto 0); -- slv
variable slvu : ufixed (VALUE'range); -- Unsigned fixed point
variable c : CHARACTER;
variable ok : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable colon, dot : BOOLEAN;
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
GOOD := false;
Skip_whitespace (L);
if VALUE'length > 0 then
check_punctuation (arg => L.all,
colon => colon,
dot => dot,
good => ok,
chars => ne/4);
if not ok then
return;
elsif dot then
HREAD (L, slvu, ok); -- read it like a UFIXED number
if not ok then
return;
else
VALUE := UNRESOLVED_float (slvu);
end if;
elsif colon then
HREAD (L, nybble, ok); -- read the sign bit
if not ok then
return;
elsif nybble (3 downto 1) /= "000" then
return;
end if;
read (l, c, ok); -- read the colon
fix_colon (L.all, ne/4); -- replaces the colon with a ".".
HREAD (L, slvu (slvu'high-1 downto slvu'low), ok); -- read it like a UFIXED number
if not ok then
return;
else
slvu (slvu'high) := nybble (0);
VALUE := UNRESOLVED_float (slvu);
end if;
else
HREAD (L, slv, ok);
if not ok then
return;
end if;
if (or_reduce (slv(ne-1 downto VALUE'high-VALUE'low+1)) = '1') then
return;
end if;
VALUE := to_float (slv(VALUE'high-VALUE'low downto 0),
VALUE'high, -VALUE'low);
end if;
GOOD := true;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_float) return STRING is
variable s : STRING(1 to value'high - value'low +3);
variable sindx : INTEGER;
begin -- function write
s(1) := MVL9_to_char(STD_ULOGIC(VALUE(VALUE'high)));
s(2) := ':';
sindx := 3;
for i in VALUE'high-1 downto 0 loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
s(sindx) := ':';
sindx := sindx + 1;
for i in -1 downto VALUE'low loop
s(sindx) := MVL9_to_char(STD_ULOGIC(VALUE(i)));
sindx := sindx + 1;
end loop;
return s;
end function to_string;
function to_hstring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_hstring (slv);
end function to_hstring;
function to_ostring (value : UNRESOLVED_float) return STRING is
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
floop : for i in slv'range loop
slv(i) := to_X01Z (value(i + value'low));
end loop floop;
return to_ostring (slv);
end function to_ostring;
function from_string (
bstring : STRING; -- binary string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
READ (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_string: Bad string " & bstring
severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
OREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_ostring: Bad string " & ostring
severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant exponent_width : NATURAL := float_exponent_width;
constant fraction_width : NATURAL := float_fraction_width)
return UNRESOLVED_float is
variable result : UNRESOLVED_float (exponent_width downto -fraction_width);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
HREAD (L, result, good);
deallocate (L);
assert (good)
report float_pkg'instance_name
& "from_hstring: Bad string " & hstring
severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_string (bstring => bstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_ostring (ostring => ostring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_float) -- used for sizing only
return UNRESOLVED_float is
begin
return from_hstring (hstring => hstring,
exponent_width => size_res'high,
fraction_width => -size_res'low);
end function from_hstring;
-- rtl_synthesis on
-- pragma synthesis_on
function to_float (
arg : STD_LOGIC_VECTOR;
constant exponent_width : NATURAL := float_exponent_width; -- length of FP output exponent
constant fraction_width : NATURAL := float_fraction_width) -- length of FP output fraction
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
exponent_width => exponent_width,
fraction_width => fraction_width);
end function to_float;
function to_float (
arg : STD_LOGIC_VECTOR;
size_res : UNRESOLVED_float)
return UNRESOLVED_float is
begin
return to_float (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_float;
-- For Verilog compatability
function realtobits (arg : REAL) return STD_LOGIC_VECTOR is
variable result : float64; -- 64 bit floating point
begin
result := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_slv (result);
end function realtobits;
function bitstoreal (arg : STD_LOGIC_VECTOR) return REAL is
variable arg64 : float64; -- arg converted to float
begin
arg64 := to_float (arg => arg,
exponent_width => float64'high,
fraction_width => -float64'low);
return to_real (arg64);
end function bitstoreal;
end package body float_pkg;
| bsd-3-clause | 21a40fbb9068f0525fb8a43587337e0c | 0.555718 | 4.214496 | false | false | false | false |
terpstra/opa | opa_slow.vhd | 1 | 8,957 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_slow is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
regfile_stb_i : in std_logic;
regfile_rega_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_regb_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_arg_i : in std_logic_vector(f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_i : in std_logic_vector(f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_regx_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_stb_o : out std_logic;
l1d_we_o : out std_logic;
l1d_sext_o : out std_logic;
l1d_size_o : out std_logic_vector(1 downto 0);
l1d_addr_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_data_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_oldest_o : out std_logic; -- delivered 1 cycle after stb
l1d_retry_i : in std_logic; -- valid 1 cycle after stb_o
l1d_data_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0); -- 2 cycles
issue_oldest_i : in std_logic;
issue_retry_o : out std_logic;
issue_fault_o : out std_logic;
issue_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
issue_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
issue_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end opa_slow;
architecture rtl of opa_slow is
constant c_reg_wide : natural := f_opa_reg_wide(g_config);
constant c_adr_wide : natural := f_opa_adr_wide(g_config);
constant c_imm_wide : natural := f_opa_imm_wide(g_isa);
constant c_log_reg_wide : natural := f_opa_log2(c_reg_wide);
constant c_log_reg_bytes: natural := c_log_reg_wide - 3;
function f_pow(m : natural) return natural is begin return 8*2**m; end f_pow;
signal s_arg : t_opa_arg;
signal r_stb : std_logic := '0';
signal r_rega : std_logic_vector(c_reg_wide-1 downto 0);
signal r_regb : std_logic_vector(c_reg_wide-1 downto 0);
signal r_imm : std_logic_vector(c_imm_wide-1 downto 0);
signal r_mode1 : std_logic_vector(1 downto 0);
signal r_mode2 : std_logic_vector(1 downto 0);
signal r_mode3 : std_logic_vector(1 downto 0);
signal s_mul : t_opa_mul;
signal s_product : std_logic_vector(2*c_reg_wide-1 downto 0);
signal s_mul_out : std_logic_vector( c_reg_wide-1 downto 0);
signal r_high1 : std_logic;
signal r_high2 : std_logic;
signal r_high3 : std_logic;
signal s_ldst : t_opa_ldst;
signal r_ldst : t_opa_ldst;
signal s_shift : t_opa_shift;
signal r_shift : t_opa_shift;
signal r_sexta : std_logic_vector(2*c_reg_wide -1 downto 0);
signal r_shamt : std_logic_vector(c_log_reg_wide downto 0);
signal s_shout : std_logic_vector(2*c_reg_wide -1 downto 0);
signal r_shout : std_logic_vector(c_reg_wide -1 downto 0);
type t_reg is array(natural range <>) of std_logic_vector(c_reg_wide-1 downto 0);
signal s_sext : t_opa_sext;
signal r_sext : t_opa_sext;
signal s_sext_mux: t_reg(c_log_reg_bytes-1 downto 0);
signal s_sext_a : std_logic_vector(c_reg_wide-1 downto 0);
signal r_sext_a : std_logic_vector(c_reg_wide-1 downto 0);
signal r_sext_o : std_logic_vector(c_reg_wide-1 downto 0);
begin
issue_retry_o <= l1d_retry_i;
issue_fault_o <= '0';
issue_pc_o <= (others => '0');
issue_pcf_o <= (others => '0');
issue_pcn_o <= (others => '0');
s_arg <= f_opa_arg_from_vec(regfile_arg_i);
s_mul <= s_arg.mul;
s_ldst <= s_arg.ldst;
s_shift<= s_arg.shift;
s_sext <= s_arg.sext;
control : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_stb <= '0';
elsif rising_edge(clk_i) then
r_stb <= regfile_stb_i;
end if;
end process;
main : process(clk_i) is
begin
if rising_edge(clk_i) then
r_rega <= regfile_rega_i;
r_regb <= regfile_regb_i;
r_imm <= regfile_imm_i;
r_ldst <= s_ldst;
r_mode1 <= s_arg.smode;
r_mode2 <= r_mode1;
r_mode3 <= r_mode2;
r_high1 <= s_mul.high;
r_high2 <= r_high1;
r_high3 <= r_high2;
end if;
end process;
prim : opa_prim_mul
generic map(
g_wide => c_reg_wide,
g_regout => true,
g_regwal => false,
g_target => g_target)
port map(
clk_i => clk_i,
a_i => regfile_rega_i,
b_i => regfile_regb_i,
x_o => s_product);
with r_high3 select
s_mul_out <=
s_product( c_reg_wide-1 downto 0) when '0',
s_product(2*c_reg_wide-1 downto c_reg_wide) when '1',
(others => 'X') when others;
-- Hand over memory accesses to the L1d
l1d_stb_o <= r_stb and f_opa_eq(r_mode1, c_opa_slow_ldst);
l1d_we_o <= r_ldst.store;
l1d_sext_o <= r_ldst.sext;
l1d_size_o <= r_ldst.size;
l1d_addr_o <= std_logic_vector(signed(r_rega) + signed(r_imm));
l1d_data_o <= r_regb;
l1d_oldest_o <= issue_oldest_i;
-- Implement a shifter
shifter : process(clk_i) is
begin
if rising_edge(clk_i) then
r_shift <= s_shift;
-- sign extend the shifter
case r_shift.sext is
when '0' => r_sexta <= (others => '0');
when '1' => r_sexta <= (others => r_rega(r_rega'high));
when others => r_sexta <= (others => 'X');
end case;
r_sexta(r_rega'range) <= r_rega;
-- calculate distance
case r_shift.right is
when '1' => r_shamt <= '0' & r_regb(c_log_reg_wide-1 downto 0);
when '0' =>
case f_opa_or(r_regb(c_log_reg_wide-1 downto 0)) is
when '1' => r_shamt <= '1' & std_logic_vector(0-unsigned(r_regb(c_log_reg_wide-1 downto 0)));
when '0' => r_shamt <= (others => '0');
when others => r_shamt <= (others => 'X');
end case;
when others => r_shamt <= (others => 'X');
end case;
-- run the shifter
r_shout <= s_shout(r_shout'range);
end if;
end process;
s_shout <= f_opa_rotate_right(r_sexta, unsigned(r_shamt));
-- Implement sign extension
sextmux : for i in s_sext_mux'range generate
s_sext_mux(i)(c_reg_wide-1 downto f_pow(i)) <= (others => r_rega(f_pow(i)-1));
s_sext_mux(i)(f_pow(i)-1 downto 0) <= r_rega(f_pow(i)-1 downto 0);
end generate;
s_sext_a <= s_sext_mux(to_integer(unsigned(r_sext.size))) when f_opa_safe(r_sext.size)='1' else (others => 'X');
sext : process(clk_i) is
begin
if rising_edge(clk_i) then
r_sext <= s_sext;
r_sext_a <= s_sext_a;
r_sext_o <= r_sext_a;
end if;
end process;
-- pick the output
with r_mode3 select
regfile_regx_o <=
s_mul_out when c_opa_slow_mul,
l1d_data_i when c_opa_slow_ldst,
r_shout when c_opa_slow_shift,
r_sext_o when c_opa_slow_sext,
(others => 'X') when others;
end rtl;
| gpl-3.0 | 6cc09c8d1861cd8bef6bcc06ae67639c | 0.606453 | 2.799937 | false | true | false | false |
terpstra/opa | opa_icache.vhd | 1 | 10,473 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_icache is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
predict_stall_o : out std_logic;
predict_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_stb_o : out std_logic;
decode_stall_i : in std_logic;
decode_fault_i : in std_logic;
decode_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_dat_o : out std_logic_vector(f_opa_fetch_bits(g_isa,g_config)-1 downto 0);
i_cyc_o : out std_logic;
i_stb_o : out std_logic;
i_stall_i : in std_logic;
i_ack_i : in std_logic;
i_err_i : in std_logic;
i_addr_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto 0);
i_data_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end opa_icache;
architecture rtl of opa_icache is
constant c_big_endian: boolean := f_opa_big_endian(g_isa);
constant c_op_align : natural := f_opa_op_align(g_isa);
constant c_page_size : natural := f_opa_page_size(g_isa);
constant c_reg_wide : natural := f_opa_reg_wide(g_config);
constant c_adr_wide : natural := f_opa_adr_wide(g_config);
constant c_fetch_bits: natural := f_opa_fetch_bits(g_isa,g_config);
constant c_num_load : natural := c_fetch_bits/c_reg_wide;
constant c_reg_align : natural := f_opa_log2(c_reg_wide/8);
constant c_load_wide : natural := f_opa_log2(c_num_load);
constant c_page_wide : natural := f_opa_log2(c_page_size);
constant c_fetch_align: natural := f_opa_fetch_align(g_isa,g_config);
constant c_fetch_bytes: natural := f_opa_fetch_bytes(g_isa,g_config);
constant c_tag_wide : natural := c_adr_wide - c_page_wide;
constant c_size : natural := c_page_size/c_fetch_bytes;
constant c_fetch_adr : unsigned(c_adr_wide-1 downto 0) := to_unsigned(c_fetch_bytes, c_adr_wide);
constant c_increment : unsigned(c_adr_wide-1 downto c_op_align) := c_fetch_adr(c_adr_wide-1 downto c_op_align);
signal r_wipe : std_logic := '1';
signal r_hit : std_logic := '0';
signal s_stall : std_logic;
signal s_dstb : std_logic;
signal s_repeat: std_logic;
signal s_wen : std_logic;
signal r_wen : std_logic := '0';
signal r_icyc : std_logic := '0';
signal r_istb : std_logic := '0';
signal s_pc1 : std_logic_vector(c_adr_wide-1 downto c_op_align);
signal s_rtag : std_logic_vector(c_adr_wide-1 downto c_page_wide);
signal s_rdata : std_logic_vector(c_fetch_bits-1 downto 0);
signal r_rdata : std_logic_vector(c_fetch_bits-1 downto 0);
signal s_wdata : std_logic_vector(c_fetch_bits-1 downto 0);
signal s_rraw : std_logic_vector(c_tag_wide+c_fetch_bits-1 downto 0);
signal s_wraw : std_logic_vector(c_tag_wide+c_fetch_bits-1 downto 0);
signal r_pc1 : std_logic_vector(c_adr_wide-1 downto c_op_align) := std_logic_vector(c_increment);
signal r_pc2 : std_logic_vector(c_adr_wide-1 downto c_op_align) := (others => '0');
signal s_last_load : std_logic;
signal s_last_get : std_logic;
begin
s_pc1 <= predict_pc_i when (s_stall = '0' or decode_fault_i = '1') else r_pc1;
-- !!! increase number of ways
cache : opa_dpram
generic map(
g_width => s_rtag'length + s_rdata'length,
g_size => c_size,
g_equal => OPA_OLD,
g_regin => true,
g_regout => false)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
r_addr_i => s_pc1(c_page_wide-1 downto c_fetch_align),
r_data_o => s_rraw,
w_en_i => s_wen,
w_addr_i => r_pc2 (c_page_wide-1 downto c_fetch_align),
w_data_i => s_wraw);
s_rtag <= s_rraw(s_rraw'left downto s_rdata'length);
s_rdata <= s_rraw(s_rdata'range);
s_wraw(s_wraw'left downto s_wdata'length) <= r_pc2(s_rtag'range);
s_wraw(s_wdata'range) <= s_wdata;
-- The r_pc[12] comparison optimizes the case where we just wrote to the
-- cache, and there were two back-to-back fetches of the same address.
--
-- If s_repeat were ALWAYS 0, we would get the old data from icache and
-- conclude that there is no hit and then reload the same line again.
-- Slow, but safe. This is why the memory cannot be OPA_UNDEF.
--
-- However, in the case that the r_pc1 and r_pc2 really refer to the same
-- PHYSICAL address lines, we can use this optimization to avoid a cache
-- refill without the need for OPA_NEW.
s_repeat <= f_opa_eq(r_pc1(r_pc1'high downto c_fetch_align),
r_pc2(r_pc2'high downto c_fetch_align));
pc : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_wipe <= '1';
r_hit <= '0';
r_pc1 <= std_logic_vector(c_increment);
r_pc2 <= (others => '0');
elsif rising_edge(clk_i) then
r_pc1 <= s_pc1;
if r_wipe = '1' then
if r_wen ='1' then
r_pc2(c_page_wide-1 downto c_fetch_align) <=
std_logic_vector(unsigned(r_pc2(c_page_wide-1 downto c_fetch_align)) + 1);
r_wipe <= not f_opa_and(r_pc2(c_page_wide-1 downto c_fetch_align));
end if;
else
if s_stall = '0' then
r_hit <= f_opa_eq(r_pc1(s_rtag'range), s_rtag) or s_repeat;
r_pc2 <= r_pc1;
end if;
end if;
end if;
end process;
rdata : process(clk_i) is
begin
if rising_edge(clk_i) then
if s_stall = '0' and s_repeat = '0' then
r_rdata <= s_rdata;
end if;
if s_wen = '1' then
r_rdata <= s_wdata;
end if;
end if;
end process;
s_stall <= decode_stall_i or not s_dstb;
s_dstb <= (r_hit or r_wen) and not r_wipe;
predict_stall_o <= s_stall;
decode_stb_o <= s_dstb;
decode_pc_o <= r_pc2;
decode_pcn_o <= r_pc1;
decode_dat_o <= r_rdata;
-- When accepting data into the line, endian matters
dat1p : if c_num_load > 1 generate
data : block is
signal r_wdata : std_logic_vector(c_fetch_bits-1 downto 0);
begin
refill : process(clk_i) is
begin
if rising_edge(clk_i) then
if (r_icyc and i_ack_i) = '1' then
r_wdata <= s_wdata;
end if;
end if;
end process;
big : if c_big_endian generate
s_wdata <= r_wdata(c_fetch_bits-c_reg_wide-1 downto 0) & i_data_i;
end generate;
small : if not c_big_endian generate
s_wdata <= i_data_i & r_wdata(c_fetch_bits-1 downto c_reg_wide);
end generate;
end block;
end generate;
dat1 : if c_num_load = 1 generate
s_wdata <= i_data_i;
end generate;
-- !!! think about what to do on i_err_i
-- probably easiest is to fill cache with instructions which generate a fault
i_cyc_o <= r_icyc;
i_stb_o <= r_istb;
i_addr_o(c_adr_wide-1 downto c_fetch_align) <= r_pc2(c_adr_wide-1 downto c_fetch_align);
i_addr_o(c_reg_align-1 downto 0) <= (others => '0');
fill : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_wen <= '0';
r_icyc <= '0';
r_istb <= '0';
elsif rising_edge(clk_i) then
if s_wen = '1' then
r_wen <= '1';
elsif decode_stall_i = '0' then
r_wen <= '0';
end if;
if (not s_dstb and not r_icyc) = '1' then
r_istb <= '1';
r_icyc <= '1';
else
if (r_istb and not i_stall_i) = '1' then
r_istb <= not s_last_load;
end if;
if (r_icyc and i_ack_i) = '1' then
r_icyc <= not s_last_get;
end if;
end if;
end if;
end process;
count1 : if c_num_load = 1 generate
s_last_load <= '1';
s_last_get <= '1';
s_wen <= i_ack_i;
end generate;
count1p : if c_num_load > 1 generate
sigs : block is
signal r_load : unsigned(c_load_wide-1 downto 0) := (others => '0');
signal r_got : unsigned(c_load_wide-1 downto 0) := (others => '0');
begin
counters : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_load <= (others => '0');
r_got <= (others => '0');
elsif rising_edge(clk_i) then
if r_icyc = '0' then
r_load <= (others => '0');
r_got <= (others => '0');
else
r_load <= r_load + ("" & (r_istb and not i_stall_i));
r_got <= r_got + ("" & i_ack_i);
end if;
end if;
end process;
s_last_load <= f_opa_eq(r_load, c_num_load-1);
s_last_get <= f_opa_eq(r_got, c_num_load-1);
s_wen <= i_ack_i and s_last_get;
i_addr_o(c_fetch_align-1 downto c_reg_align) <= std_logic_vector(r_load);
end block;
end generate;
end rtl;
| gpl-3.0 | 3e3c22ead494ef321aa3c51e57f0c524 | 0.592285 | 2.910784 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/wrapper_complex_abs.vhd | 1 | 6,022 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 11:22:27
-- Design Name:
-- Module Name: wrapper_complex_abs - Structural
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--! @file wrapper_complex_abs.vhd
--! @author Antonio Riccio, Andrea Scognamiglio, Stefano Sorrentino
--! @brief Wrapper di @ref complex_abs che fornisce funzioni di comunicazione
--! @anchor wrapper_complex_abs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--! @brief Wrapper per l'entità @ref complex_abs
--! @details Questo componente arricchisce il modulo @ref complex_abs con funzionalità
--! di comunicazione. Queste funzionalità sono necessarie per collegare in cascata questo
--! blocco con quello di calcolo del massimo.
entity wrapper_complex_abs is
Generic ( complex_width : natural := 32 ); --! Parallelismo in bit del numero complesso (inteso come somma di parte reale e immaginaria)
Port ( clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
valid_in : in STD_LOGIC; --! Indica che il dato sulla linea di ingresso è valido
ready_in : in STD_LOGIC; --! Indica che il componente a valle è pronto ad accettare valori in ingresso
complex_value : in STD_LOGIC_VECTOR (complex_width-1 downto 0); --! Numero complesso di cui calcolare il modulo
complex_value_out : out STD_LOGIC_VECTOR(complex_width-1 downto 0); --! Valore registrato del numero complesso di cui calcolare il modulo
abs_value : out STD_LOGIC_VECTOR (complex_width-1 downto 0); --! Modulo del numero complesso
valid_out : out STD_LOGIC; --! Indica che il dato sulla linea di uscita è valido
ready_out : out STD_LOGIC); --! Indica che questo componente è pronto ad accettare valori in ingresso
end wrapper_complex_abs;
--! @brief Architettura del componente descritta nel dominio strutturale
--! @details L'archittettura utilizza due registri necessari a memorizzare il valore
--! complesso ed il suo modulo. Questo consente di svincolare il funzionamento del
--! calcolo del modulo dalla comunicazione del risultato ai componenti a valle.
architecture Structural of wrapper_complex_abs is
--! @brief Registro a parallelismo generico che opera sul fronte di salita del clock
component register_n_bit is
generic (
n : natural := 8
);
port (
I : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end component register_n_bit;
--! @brief Calcola il modulo di un numero complesso
--! @see complex_abs
component complex_abs is
generic (
complex_width : natural := 32
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
enable : in STD_LOGIC;
complex_value : in STD_LOGIC_VECTOR (complex_width-1 downto 0);
abs_value : out STD_LOGIC_VECTOR (complex_width-1 downto 0);
done : out STD_LOGIC
);
end component complex_abs;
--! @brief Parte di controllo di questo blocco
component fsm_complex_abs is
port (
clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
abs_done : in STD_LOGIC;
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC);
end component;
--! @brief Flip-flop D con reset 0-attivo asincrono
component d_edge_triggered
port (
data_in : in STD_LOGIC;
reset_n : in STD_LOGIC;
clock : in STD_LOGIC;
data_out : out STD_LOGIC
);
end component d_edge_triggered;
signal done_sig : std_logic := '0';
signal reset_abs_n : std_logic := '0';
signal ready_out_sig : std_logic := '0';
signal ready_out_delayed : std_logic := '0';
signal abs_value_sig : std_logic_vector(complex_width-1 downto 0) := (others => '0');
begin
--! @brief Componente che calcola il modulo del valore complesso in ingresso
complex_abs_inst : complex_abs
generic map (
complex_width => complex_width
)
port map (
clock => clock,
reset_n => reset_n,
enable => valid_in,
complex_value => complex_value,
abs_value => abs_value_sig,
done => done_sig
);
--! @brief Automa a stati finiti per la gestione dei segnali di comunicazione
fsm_complex_abs_inst : fsm_complex_abs
port map (
clk => clock,
reset_n => reset_n,
valid_in => valid_in,
ready_in => ready_in,
abs_done => done_sig,
valid_out => valid_out,
ready_out => ready_out_sig
);
--! @brief Memorizza il modulo del numero complesso
--! @details Questo registro è necessario per memorizzare il risultato di complex_abs
--! dato che il componente si resetta dopo che ha terminato l'elaborazione.
reg_abs_value: register_n_bit
generic map (
n => complex_width
)
port map (
I => abs_value_sig,
clock => clock,
load => done_sig,
reset_n => reset_n,
O => abs_value
);
ff_load_complex_value : d_edge_triggered
port map (
data_in => ready_out_sig,
reset_n => reset_n,
clock => clock,
data_out => ready_out_delayed
);
--! @brief Memorizza il numero complesso in ingresso
--! @details Questo registro è necessario per conservare l'associazione tra valore
--! complesso in ingresso e modulo calcolato dal blocco complex_abs.
reg_complex_value_out : register_n_bit
generic map (
n => complex_width
)
port map (
I => complex_value,
clock => clock,
load => ready_out_delayed,
reset_n => reset_n,
O => complex_value_out
);
ready_out <= ready_out_sig;
end Structural;
| gpl-2.0 | 0b7e5e3d32709f1e7529bee23a8a8dd8 | 0.670547 | 3.420364 | false | false | false | false |
AleChir/Digital_Filter_VHDL | Testbench/clk_gen.vhd | 1 | 1,050 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clk_gen is
end clk_gen;
architecture behavior of clk_gen is
component filter
port( data_ext: in std_logic_vector( 7 downto 0);
clock, start, rst: in std_logic;
done: out std_logic);
end component;
signal data_ext: std_logic_vector( 7 downto 0);
signal int_data: integer:=0;
signal clk, start, rst: std_logic;
signal done: std_logic;
signal resettato: integer:=0;
begin
clock_process : process
begin
clk<= '0'; wait for 100 ns; clk <= '1'; wait for 100 ns;
int_data<=int_data+1;
data_ext<=std_logic_vector(to_unsigned(int_data,8));
if(resettato=2) then
start<='0';
end if;
if(resettato=1) then
rst <= '1';
resettato<=2;
end if;
if(resettato=0) then
rst <= '0';
start<='1';
resettato<=1;
end if;
end process;
stimulate: filter port map(data_ext, clk, start, rst, done);
end behavior;
| gpl-3.0 | e6934f2cbbf7e8709bac52e5714021fa | 0.581905 | 3.333333 | false | false | false | false |
terpstra/opa | opa_tdpram.vhd | 1 | 6,339 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
-- Inputs are registered
-- Read output from a port during a write is undefined
-- Simultaneous write to the same address writes 'X's
-- Data read from one port while written by another outputs 'X'
entity opa_tdpram is
generic(
g_width : natural;
g_size : natural;
g_hunks : natural := 1);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
a_wen_i : in std_logic;
a_sel_i : in std_logic_vector(g_hunks-1 downto 0) := (others => '1');
a_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
a_data_i : in std_logic_vector(g_hunks*g_width-1 downto 0);
a_data_o : out std_logic_vector(g_hunks*g_width-1 downto 0);
b_wen_i : in std_logic;
b_sel_i : in std_logic_vector(g_hunks-1 downto 0) := (others => '1');
b_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
b_data_i : in std_logic_vector(g_hunks*g_width-1 downto 0);
b_data_o : out std_logic_vector(g_hunks*g_width-1 downto 0));
end opa_tdpram;
architecture rtl of opa_tdpram is
begin
nobe : if g_hunks = 1 generate
simple : block is
type t_memory is array(g_size-1 downto 0) of std_logic_vector(g_width-1 downto 0);
shared variable v_memory : t_memory;
signal a_idx : integer;
signal b_idx : integer;
begin
a_idx <= to_integer(unsigned(a_addr_i));
b_idx <= to_integer(unsigned(b_addr_i));
a : process(clk_i) is
begin
if rising_edge(clk_i) then
if (a_wen_i and a_sel_i(0)) = '1' then
v_memory(a_idx) := a_data_i;
end if;
a_data_o <= v_memory(a_idx);
-- Output undefined during write
if a_wen_i = '1' or (b_wen_i = '1' and a_idx = b_idx) then
a_data_o <= (others => 'X');
end if;
end if;
end process;
b : process(clk_i) is
begin
if rising_edge(clk_i) then
if (b_wen_i and b_sel_i(0)) = '1' then
v_memory(b_idx) := b_data_i;
end if;
b_data_o <= v_memory(b_idx);
-- Output undefined during write
if b_wen_i = '1' or (a_wen_i = '1' and a_idx = b_idx) then
b_data_o <= (others => 'X');
end if;
end if;
end process;
fatal : process(clk_i) is
begin
if rising_edge(clk_i) then
assert (a_idx /= b_idx or a_wen_i = '0' or b_wen_i = '0')
report "Two writes to the same address in opa_tdpram"
severity failure;
end if;
end process;
end block;
end generate;
-- Reduce the dpram to multiple dprams per byte enable
be : if g_hunks > 1 generate
recurse : block is
signal s_clk_i : std_logic;
signal s_rst_n_i : std_logic;
signal s_a_wen_i : std_logic;
signal s_a_sel_i : std_logic_vector(g_hunks-1 downto 0) := (others => '1');
signal s_a_addr_i : std_logic_vector(f_opa_log2(g_size)-1 downto 0);
signal s_a_data_i : std_logic_vector(g_hunks*g_width-1 downto 0);
signal s_a_data_o : std_logic_vector(g_hunks*g_width-1 downto 0);
signal s_b_wen_i : std_logic;
signal s_b_sel_i : std_logic_vector(g_hunks-1 downto 0) := (others => '1');
signal s_b_addr_i : std_logic_vector(f_opa_log2(g_size)-1 downto 0);
signal s_b_data_i : std_logic_vector(g_hunks*g_width-1 downto 0);
signal s_b_data_o : std_logic_vector(g_hunks*g_width-1 downto 0);
begin
-- We have to rename so they don't conflict in recursive component
s_clk_i <= clk_i;
s_rst_n_i <= rst_n_i;
s_a_wen_i <= a_wen_i;
s_a_sel_i <= a_sel_i;
s_a_addr_i <= a_addr_i;
s_a_data_i <= a_data_i;
a_data_o <= s_a_data_o;
s_b_wen_i <= b_wen_i;
s_b_sel_i <= b_sel_i;
s_b_addr_i <= b_addr_i;
s_b_data_i <= b_data_i;
b_data_o <= s_b_data_o;
bex : for i in 0 to g_hunks-1 generate
ram : entity opa_tdpram
generic map(
g_width => g_width,
g_size => g_size)
port map(
clk_i => s_clk_i,
rst_n_i => s_rst_n_i,
a_wen_i => s_a_wen_i,
a_sel_i => s_a_sel_i(i downto i),
a_addr_i => s_a_addr_i,
a_data_i => s_a_data_i((i+1)*g_width-1 downto i*g_width),
a_data_o => s_a_data_o((i+1)*g_width-1 downto i*g_width),
b_wen_i => s_b_wen_i,
b_sel_i => s_b_sel_i(i downto i),
b_addr_i => s_b_addr_i,
b_data_i => s_b_data_i((i+1)*g_width-1 downto i*g_width),
b_data_o => s_b_data_o((i+1)*g_width-1 downto i*g_width));
end generate;
end block;
end generate;
end rtl;
| gpl-3.0 | 8316e2e0105077e8b383dfa512a944db | 0.577063 | 2.967697 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/add_sub/add_sub.vhd | 1 | 2,454 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:00:31 11/13/2015
-- Design Name:
-- Module Name: add_sub - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity add_sub is
generic ( n : natural := 8);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
subtract : in STD_LOGIC;
ovfl : out STD_LOGIC;
S : out STD_LOGIC_VECTOR (n-1 downto 0));
end add_sub;
architecture Structural of add_sub is
COMPONENT ripple_carry_adder
generic ( n : natural := 4);
PORT(
A : IN std_logic_vector(n-1 downto 0);
B : IN std_logic_vector(n-1 downto 0);
c_in : IN std_logic;
ovfl : OUT std_logic;
S : OUT std_logic_vector(n-1 downto 0)
);
END COMPONENT;
COMPONENT carry_lookahead_n_bit
generic ( n : natural := 4);
PORT(
A : IN std_logic_vector(n-1 downto 0);
B : IN std_logic_vector(n-1 downto 0);
c_in : IN std_logic;
ovfl : OUT std_logic;
S : OUT std_logic_vector(n-1 downto 0)
);
END COMPONENT;
COMPONENT carry_select_4n_bit
generic ( n : natural := 8);
PORT (
A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
c_in : in STD_LOGIC;
ovfl : out STD_LOGIC;
S : out STD_LOGIC_VECTOR (n-1 downto 0)
);
END COMPONENT;
signal b_sig: std_logic_vector (n-1 downto 0);
begin
b_sig <= B xor (B'range => subtract);
ripple_carry : ripple_carry_adder
generic map (n)
PORT MAP(A => A, B => b_sig, c_in => subtract, ovfl => ovfl, S => S);
--carry_lookahead : carry_lookahead_n_bit
-- generic map (n)
-- PORT MAP(A => A, B => b_sig, c_in => subtract, ovfl => ovfl, S => S);
--carry_select : carry_select_4n_bit
-- generic map (n)
-- PORT MAP(A => A, B => b_sig, c_in => subtract, ovfl => ovfl, S => S);
end Structural;
| gpl-2.0 | eb9bac88046c0ba2b52eaf1c3df0e13e | 0.57987 | 3.114213 | false | false | false | false |
terpstra/opa | opa_components_pkg.vhd | 1 | 31,295 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
package opa_components_pkg is
type t_dpram_equal is (OPA_OLD, OPA_NEW, OPA_UNDEF);
component opa_dpram is
generic(
g_width : natural;
g_size : natural;
g_equal : t_dpram_equal;
g_regin : boolean;
g_regout : boolean);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
r_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
r_data_o : out std_logic_vector(g_width-1 downto 0);
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
w_data_i : in std_logic_vector(g_width-1 downto 0));
end component;
-- Inputs are registered
-- Read output from a port during a write is undefined
-- Simultaneous write to the same address writes 'X's
-- Data read from one port while written by another outputs 'X'
component opa_tdpram is
generic(
g_width : natural;
g_size : natural;
g_hunks : natural := 1);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
a_wen_i : in std_logic;
a_sel_i : in std_logic_vector(g_hunks-1 downto 0) := (others => '1');
a_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
a_data_i : in std_logic_vector(g_hunks*g_width-1 downto 0);
a_data_o : out std_logic_vector(g_hunks*g_width-1 downto 0);
b_wen_i : in std_logic;
b_sel_i : in std_logic_vector(g_hunks-1 downto 0) := (others => '1');
b_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
b_data_i : in std_logic_vector(g_hunks*g_width-1 downto 0);
b_data_o : out std_logic_vector(g_hunks*g_width-1 downto 0));
end component;
-- Inhibit optimization between these points
component opa_lcell is
port(
a_i : in std_logic;
b_o : out std_logic);
end component;
component opa_prim_ternary is
generic(
g_wide : natural);
port(
a_i : in unsigned(g_wide-1 downto 0);
b_i : in unsigned(g_wide-1 downto 0);
c_i : in unsigned(g_wide-1 downto 0);
x_o : out unsigned(g_wide-1 downto 0));
end component;
component opa_prim_mul is
generic(
g_wide : natural;
g_regout : boolean;
g_regwal : boolean;
g_target : t_opa_target);
port(
clk_i : in std_logic;
a_i : in std_logic_vector( g_wide-1 downto 0);
b_i : in std_logic_vector( g_wide-1 downto 0);
x_o : out std_logic_vector(2*g_wide-1 downto 0));
end component;
component opa_prefixsum is
generic(
g_target : t_opa_target;
g_width : natural;
g_count : natural);
port(
bits_i : in std_logic_vector(g_width-1 downto 0);
count_o : out t_opa_matrix(g_count-1 downto 0, g_width-1 downto 0);
total_o : out std_logic_vector(g_width-1 downto 0));
end component;
component opa_lfsr is
generic(
g_entropy : natural := 0;
g_bits : natural);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
random_o : out std_logic_vector(g_bits-1 downto 0));
end component;
component opa_predict is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Deliver our prediction
icache_stall_i : in std_logic;
icache_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_hit_o : out std_logic;
decode_jump_o : out std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
-- Push a return stack entry
decode_push_i : in std_logic;
decode_ret_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Fixup PC to new target
decode_fault_i : in std_logic;
decode_return_i : in std_logic;
decode_jump_i : in std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
decode_source_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_target_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_return_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
component opa_icache is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
predict_stall_o : out std_logic;
predict_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_stb_o : out std_logic;
decode_stall_i : in std_logic;
decode_fault_i : in std_logic;
decode_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_dat_o : out std_logic_vector(f_opa_fetch_bits(g_isa,g_config)-1 downto 0);
i_cyc_o : out std_logic;
i_stb_o : out std_logic;
i_stall_i : in std_logic;
i_ack_i : in std_logic;
i_err_i : in std_logic;
i_addr_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto 0);
i_data_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end component;
component opa_decode is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Predicted jumps?
predict_hit_i : in std_logic;
predict_jump_i : in std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
-- Push a return stack entry
predict_push_o : out std_logic;
predict_ret_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Fixup PC to new target
predict_fault_o : out std_logic;
predict_return_o : out std_logic;
predict_jump_o : out std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
predict_source_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
predict_target_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
predict_return_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Instructions delivered from icache
icache_stb_i : in std_logic;
icache_stall_o : out std_logic;
icache_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
icache_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
icache_dat_i : in std_logic_vector(f_opa_fetch_bits(g_isa,g_config)-1 downto 0);
-- Feed data to the renamer
rename_stb_o : out std_logic;
rename_stall_i : in std_logic;
rename_fast_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_slow_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_order_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_setx_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_geta_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_getb_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_aux_o : out std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
rename_archx_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
rename_archa_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
rename_archb_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
-- Accept faults
rename_fault_i : in std_logic;
rename_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
rename_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
rename_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Give the regfile the information EUs will need for these operations
regfile_stb_o : out std_logic;
regfile_aux_o : out std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
regfile_arg_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
component opa_rename is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Values the decoder needs to provide us
decode_stb_i : in std_logic;
decode_stall_o : out std_logic;
decode_fast_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_slow_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_order_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_setx_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_geta_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_getb_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
decode_aux_i : in std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
decode_archx_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
decode_archa_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
decode_archb_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
-- Values we provide to the issuer
issue_stb_o : out std_logic;
issue_stall_i : in std_logic;
issue_fast_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_slow_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_order_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_geta_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_getb_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_aux_o : out std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
issue_bakx_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
issue_baka_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
issue_bakb_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
issue_stata_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_stat_wide(g_config) -1 downto 0);
issue_statb_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_stat_wide(g_config) -1 downto 0);
issue_bakx_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- Feed faults back up the pipeline
issue_fault_i : in std_logic;
issue_mask_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
issue_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
issue_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
issue_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_fault_o : out std_logic;
decode_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
decode_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
component opa_issue is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Values the renamer provides us
rename_stb_i : in std_logic;
rename_stall_o : out std_logic;
rename_fast_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_slow_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_order_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_geta_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_getb_i : in std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_aux_i : in std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
rename_bakx_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
rename_baka_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
rename_bakb_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
rename_stata_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_stat_wide(g_config) -1 downto 0);
rename_statb_i : in t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_stat_wide(g_config) -1 downto 0);
rename_bakx_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- Exceptions from the EUs
eu_oldest_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
eu_retry_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
eu_fault_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
eu_pc_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
eu_pcf_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
eu_pcn_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Selected fault fed back up pipeline
rename_fault_o : out std_logic;
rename_mask_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
rename_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
rename_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Regfile needs to fetch these for EU
regfile_rstb_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
regfile_geta_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
regfile_getb_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
regfile_aux_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_aux_wide (g_config)-1 downto 0);
regfile_dec_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_ren_wide (g_config)-1 downto 0);
regfile_baka_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
regfile_bakb_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- Regfile should capture result from EU
regfile_wstb_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
regfile_bakx_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- Gather information from L1d about aliased loads
l1d_store_i : in std_logic;
l1d_load_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
l1d_addr_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_alias_high(g_isa) downto f_opa_alias_low(g_config));
l1d_mask_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)/8-1 downto 0));
end component;
component opa_regfile is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Record PC + immediate data
decode_stb_i : in std_logic;
decode_aux_i : in std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
decode_arg_i : in t_opa_matrix(f_opa_renamers (g_config)-1 downto 0, f_opa_arg_wide(g_config)-1 downto 0);
decode_imm_i : in t_opa_matrix(f_opa_renamers (g_config)-1 downto 0, f_opa_imm_wide(g_isa) -1 downto 0);
decode_pc_i : in t_opa_matrix(f_opa_renamers (g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
decode_pcf_i : in t_opa_matrix(f_opa_renamers (g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
decode_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Issue has dispatched these instructions to us
issue_rstb_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
issue_geta_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
issue_getb_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
issue_aux_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_aux_wide (g_config)-1 downto 0);
issue_dec_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_ren_wide (g_config)-1 downto 0);
issue_baka_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide (g_isa,g_config)-1 downto 0);
issue_bakb_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide (g_isa,g_config)-1 downto 0);
-- Feed the EUs one cycle later (they register this => result is two cycles later)
eu_stb_o : out std_logic_vector(f_opa_executers(g_config)-1 downto 0);
eu_rega_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
eu_regb_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
eu_arg_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_arg_wide(g_config)-1 downto 0);
eu_imm_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_imm_wide(g_isa) -1 downto 0);
eu_pc_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
eu_pcf_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
eu_pcn_o : out t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Issue has indicated these EUs will write now
issue_wstb_i : in std_logic_vector(f_opa_executers(g_config)-1 downto 0);
issue_bakx_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_back_wide(g_isa,g_config)-1 downto 0);
-- The results arrive two cycles after the issue said they would
eu_regx_i : in t_opa_matrix(f_opa_executers(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0));
end component;
component opa_fast is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
regfile_stb_i : in std_logic;
regfile_rega_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_regb_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_arg_i : in std_logic_vector(f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_i : in std_logic_vector(f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_regx_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
issue_oldest_i : in std_logic;
issue_retry_o : out std_logic;
issue_fault_o : out std_logic;
issue_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
issue_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
issue_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
component opa_slow is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
regfile_stb_i : in std_logic;
regfile_rega_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_regb_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_arg_i : in std_logic_vector(f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_i : in std_logic_vector(f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_regx_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_stb_o : out std_logic;
l1d_we_o : out std_logic;
l1d_sext_o : out std_logic;
l1d_size_o : out std_logic_vector(1 downto 0);
l1d_addr_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_data_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
l1d_oldest_o : out std_logic; -- delivered 1 cycle after stb
l1d_retry_i : in std_logic; -- valid 1 cycle after stb_o
l1d_data_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0); -- 2 cycles
issue_oldest_i : in std_logic;
issue_retry_o : out std_logic;
issue_fault_o : out std_logic;
issue_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
issue_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
issue_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end component;
type t_opa_dbus_request is (
OPA_DBUS_WIPE,
OPA_DBUS_IDLE,
OPA_DBUS_WAIT_STORE_LOAD,
OPA_DBUS_STORE_LOAD, -- request forbidden
OPA_DBUS_LOAD_STORE,
OPA_DBUS_WAIT_LOAD,
OPA_DBUS_WAIT_STORE,
OPA_DBUS_LOAD,
OPA_DBUS_STORE); -- request forbidden
component opa_l1d is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- read/writes come from the slow EUs
slow_stb_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_we_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_sext_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_size_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, 1 downto 0);
slow_addr_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
slow_data_i : in t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
slow_oldest_i : in std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_retry_o : out std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
slow_data_o : out t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)-1 downto 0);
-- Share information about the addresses we are loading/storing
issue_store_o : out std_logic;
issue_load_o : out std_logic_vector(f_opa_num_slow(g_config)-1 downto 0);
issue_addr_o : out t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_alias_high(g_isa) downto f_opa_alias_low(g_config));
issue_mask_o : out t_opa_matrix(f_opa_num_slow(g_config)-1 downto 0, f_opa_reg_wide(g_config)/8-1 downto 0);
-- L1d requests action
dbus_req_o : out t_opa_dbus_request;
dbus_radr_o : out std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
dbus_way_o : out std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
dbus_wadr_o : out std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
dbus_dirty_o : out std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
dbus_data_o : out std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0);
dbus_busy_i : in std_logic; -- can accept a req_i
dbus_we_i : in std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
dbus_adr_i : in std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
dbus_valid_i : in std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
dbus_data_i : in std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0);
pbus_stall_i : in std_logic;
pbus_req_o : out std_logic;
pbus_we_o : out std_logic;
pbus_addr_o : out std_logic_vector(f_opa_adr_wide(g_config) -1 downto 0);
pbus_sel_o : out std_logic_vector(f_opa_reg_wide(g_config)/8-1 downto 0);
pbus_dat_o : out std_logic_vector(f_opa_reg_wide(g_config) -1 downto 0);
pbus_pop_o : out std_logic;
pbus_full_i : in std_logic;
pbus_err_i : in std_logic;
pbus_dat_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end component;
component opa_dbus is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
d_cyc_o : out std_logic;
d_stb_o : out std_logic;
d_we_o : out std_logic;
d_stall_i : in std_logic;
d_ack_i : in std_logic;
d_err_i : in std_logic;
d_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
d_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
d_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
d_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- L1d requests action
l1d_req_i : in t_opa_dbus_request;
l1d_radr_i : in std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_way_i : in std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
l1d_wadr_i : in std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_dirty_i : in std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
l1d_data_i : in std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0);
l1d_busy_o : out std_logic; -- can accept a req_i
l1d_we_o : out std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
l1d_adr_o : out std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_valid_o : out std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
l1d_data_o : out std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0));
end component;
component opa_pbus is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
p_cyc_o : out std_logic;
p_stb_o : out std_logic;
p_we_o : out std_logic;
p_stall_i : in std_logic;
p_ack_i : in std_logic;
p_err_i : in std_logic;
p_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
p_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
p_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
p_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- L1d requests action
l1d_stall_o : out std_logic; -- stall has an async dep on addr
l1d_req_i : in std_logic;
l1d_we_i : in std_logic;
l1d_addr_i : in std_logic_vector(f_opa_adr_wide(g_config) -1 downto 0);
l1d_sel_i : in std_logic_vector(f_opa_reg_wide(g_config)/8-1 downto 0);
l1d_dat_i : in std_logic_vector(f_opa_reg_wide(g_config) -1 downto 0);
l1d_pop_i : in std_logic;
l1d_full_o : out std_logic;
l1d_err_o : out std_logic;
l1d_dat_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0));
end component;
end package;
| gpl-3.0 | 95d3c6fcc7e7bf4a7d68746c35e9f9e2 | 0.613485 | 2.715401 | false | true | false | false |
AleChir/Digital_Filter_VHDL | Digital_Filter/ram_1024X8.vhd | 1 | 936 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram_1024X8 is
port( data_in: in std_logic_vector(7 downto 0);
address: in integer range 1023 downto 0;
cs: in std_logic;
clk: in std_logic;
wr_rd_n: in std_logic;
data_out: out std_logic_vector (7 downto 0));
end ram_1024X8;
architecture Behaviour of ram_1024X8 is
type ram is array(1023 downto 0) of std_logic_vector(7 downto 0);
begin
process(clk)
variable mem:ram;
begin
if(clk'event and clk='1') then
data_out <= (others => 'Z');
if (cs = '1') then
if (wr_rd_n = '0') then
data_out <= mem(address);
elsif (wr_rd_n = '1') then
mem(address) := data_in;
end if;
end if;
end if;
end process;
end Behaviour; | gpl-3.0 | 6ae706b33c52a43c7ff23d87ec2398e5 | 0.510684 | 3.532075 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/DualPortRam.vhd | 1 | 1,588 | --------------------------------------------------------------------------------
--! @file DualPortRam.vhd
--! @brief Dual port RAM
--! @author Takehiro Shiozaki
--! @date 2013-11-05
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity DualPortRam is
generic(
G_WIDTH : integer;
G_DEPTH : integer
);
port( -- write
WCLK : in std_logic;
DIN : in std_logic_vector(G_WIDTH - 1 downto 0);
WADDR : in std_logic_vector(G_DEPTH - 1 downto 0);
WE : in std_logic;
-- read
RCLK : in std_logic;
DOUT : out std_logic_vector(G_WIDTH - 1 downto 0);
RADDR : in std_logic_vector(G_DEPTH - 1 downto 0)
);
end DualPortRam;
architecture RTL of DualPortRam is
subtype RamWord is std_logic_vector(G_WIDTH - 1 downto 0);
type RamArray is array (0 to 2 ** G_DEPTH - 1) of RamWord;
signal RamData : RamArray;
signal WriteAddress : integer range 0 to 2 ** G_DEPTH - 1;
signal ReadAddress : integer range 0 to 2 ** G_DEPTH - 1;
begin
WriteAddress <= conv_integer(WADDR);
ReadAddress <= conv_integer(RADDR);
process(WCLK)
begin
if(WCLK'event and WCLK = '1') then
if(WE = '1') then
RamData(WriteAddress) <= DIN;
end if;
end if;
end process;
process(RCLK)
begin
if(RCLK'event and RCLK = '1') then
DOUT <= RamData(ReadAddress);
end if;
end process;
end RTL;
| mit | 1b38fee94a5de75f55f43109e96880d0 | 0.5233 | 3.91133 | false | false | false | false |
jfdelnero/CPLD_USBHxCFloppyEmulator | rtl/vhdl/HxCFloppyEmu.vhd | 1 | 11,453 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------H----H--X----X-----CCCCC----22222----0000-----0000------11----------
----------H----H----X-X-----C--------------2---0----0---0----0--1--1-----------
---------HHHHHH-----X------C----------22222---0----0---0----0-----1------------
--------H----H----X--X----C----------2-------0----0---0----0-----1-------------
-------H----H---X-----X---CCCCC-----222222----0000-----0000----1111------------
-------------------------------------------------------------------------------
----------------------------------------- http://jeanfrancoisdelnero.free.fr --
--============================================================================-
-- HxCFloppyEmu
-- Floppy drive emulator Project
--
-- http://jeanfrancoisdelnero.free.fr
-- HxC2001 - 2006 - 2008
--
-- Design units :
--
-- File name : HxCFloppyEmu.vhd (top file)
--
-- Purpose : Implements an floppy drive emulator.
-- This design are based on the USB chip FT245BM.
--
--
-- Dependencies : IEEE.Std_Logic_1164
-- IEEE.STD_LOGIC_arith
--
--============================================================================-
-- --
-- Copyright (C) 2006, 2007, 2008 Jean-François DEL NERO --
-- --
-- This file is part of HxCFloppyEmulator. --
-- --
-- HxCFloppyEmulator may be used and distributed without restriction provided--
-- that this copyright statement is not removed from the file and that any --
-- derivative work contains the original copyright notice and the associated --
-- disclaimer. --
-- --
-- HxCFloppyEmulator is free software; you can redistribute it --
-- and/or modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 2 --
-- of the License, or (at your option) any later version. --
-- --
-- HxCFloppyEmulator is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. --
-- See the GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with HxCFloppyEmulator; if not, write to the Free Software --
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA--
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 Jean-François DEL NERO 23 march 2008 Major update:
--
-- MFM/FM output generator (HeadShifter) rewritten.
-- It can now do any bitrate between
-- 63kbit/s and 1Mbit/s with a 62.5ns step.
-- The emulator can now handle bitrate-protected floppies ;-)
--
-- The SRAM is now used like a ring buffer (1 buffer of 8KB).
--
-- The master state machine run now at 16Mhz
-- to allow fast opcode execution / mfm loading.
--
-- "Validate Track" opcode removed (same functionnality in "SENDTRACKCODE opcode".
-- "SETINDEX" opcode modified:
-- "SENDTRACKCODE" added (2 byte : 0x3 <track number>)
-- "SETBITRATE" opcode added (2 bytes: 0xD <period value>)
-- "NOP" opcode added (2 bytes : 0x7 XX)
-- "Disk Changed" and "Ready" signals
-- are now software driven
--
-- Track position register is now 8 bits.
--
-- SRAM_CS_not is now driven (for the SRAM standby mode)
--
-- 0.5 Jean-François DEL NERO 19 November 2006 Jumper-free drive select added
-- jeanfrancoisdelnero < > free.fr
-- 0.4 Jean-François DEL NERO 11 November 2006 500kbits/s support added
-- 2*1Ko and 2*2Ko buffer size available
-- Write protect signal added
-- Shugart and IBM PC mode available
-- 0.2 Jean-François DEL NERO 16 September 2006 MFM Pulse Generator rewritten
-- 0.1 Jean-François DEL NERO 25 June 2006 First public version
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- package FloppyEmu
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
--------------------------------------------------------------------------------
entity HxCFloppyEmu is
port (
-- FTDI chip interface
FTDI_DATA : inout std_logic_vector(7 downto 0);
FTDI_RD_not : out std_logic;
FTDI_WR : out std_logic;
FTDI_TXE_not: in std_logic;
FTDI_RXF_not: in std_logic;
-- 32Ko SRAM
SRAM_DATA : inout std_logic_vector(7 downto 0);
SRAM_ADDR : out std_logic_vector(14 downto 0);
SRAM_CS_not : out std_logic;
SRAM_WRITE_not : out std_logic;
SRAM_READ_not : out std_logic;
-- Floppy interface
FLOPPY_DS0: in std_logic;
FLOPPY_DS1: in std_logic;
FLOPPY_DS2: in std_logic;
FLOPPY_MTRON: in std_logic;
-- Head control lines
FLOPPY_SIDE: in std_logic;
FLOPPY_STEP: in std_logic;
FLOPPY_DIR: in std_logic;
FLOPPY_TRK00 : out std_logic;
-- Others floppy control lines
FLOPPY_WPT : out std_logic;
FLOPPY_INDEX: out std_logic;
FLOPPY_DATA : out std_logic;
FLOPPY_DSKCHG : out std_logic;
FLOPPY_READY : out std_logic;
-- Some Leds...
LED1_not: out std_logic;
LED2_not: out std_logic;
LED3_not: out std_logic;
-- Clock Input
clock: in std_logic;
reset_not: in std_logic
);
end HxCFloppyEmu;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture struct of HxCFloppyEmu is
------------------------------------------------------
-- Control core of the Floppy Emulator
--
component ControlCore is
port (
-- FTDI chip if
FTDI_DATA: inout std_logic_vector(7 downto 0);
FTDI_RD_not: out std_logic;
FTDI_WR: out std_logic;
FTDI_TXE_not: in std_logic;
FTDI_RXF_not: in std_logic;
-- SRAM IF
SRAM_DATA: inout std_logic_vector(7 downto 0);
SRAM_ADR: out std_logic_vector(14 downto 0);
SRAM_RD_not: out std_logic;
SRAM_WR_not: out std_logic;
SRAM_CS_not: out std_logic;
-- Track position
Head_Position: in std_logic_vector(6 downto 0);
Clear_Head_Position: out std_logic;
Head_moved : in std_logic;
Ack_head_move : out std_logic;
-- Floppy IF
FLOPPY_READYSIGNAL: out std_logic;
FLOPPY_SIDE: in std_logic;
FLOPPY_DSKCHG : out std_logic;
FLOPPY_INDEX: out std_logic;
FLOPPY_WPT: out std_logic;
FLOPPY_SEL0: in std_logic;
FLOPPY_SEL1: in std_logic;
FLOPPY_SEL2: in std_logic;
FLOPPY_SEL3: in std_logic;
FLOPPY_SELECT: out std_logic;
FLOPPY_DATA: out std_logic;
Step_LED: out std_logic;
-- Clock and reset
clock: in std_logic;
reset_not: in std_logic
);
end component;
------------------------------------------------------
-- Track position counter...
--
component TrackCore
port (
FLOPPY_DRIVE_SELECT: in std_logic;
HEADTRACKPOSITION: out std_logic_vector(7 downto 0); -- track position value
HEADMOVED: out std_logic;
ackheadmove: in std_logic;
FLOPPY_STEP: in std_logic; -- Step command
FLOPPY_DIR: in std_logic; -- Step direction
FLOPPY_TRK00 : out std_logic; -- Track 0 indicator
clear_cnt: in std_logic;
clock: in std_logic;
reset_not: in std_logic
);
end component;
------------------------------------------------------
signal trackvalue : std_logic_vector(6 downto 0);
signal step_led : std_logic;
signal FLOPPY_SEL: std_logic;
signal clear_track_cnt: std_logic;
signal headmoved: std_logic;
signal ackheadmoved: std_logic;
begin
LED1_not<=not(FLOPPY_SEL); -- floppy activity led
LED2_not<=not(step_led); -- step led
LED3_not<=FTDI_RXF_not; -- usb activity led
THM: TrackCore port map
(
FLOPPY_DRIVE_SELECT=>FLOPPY_SEL,
HEADTRACKPOSITION(6 downto 0)=>trackvalue,
HEADMOVED=>headmoved,
ackheadmove=>ackheadmoved,
FLOPPY_STEP=>FLOPPY_STEP,
FLOPPY_DIR=>FLOPPY_DIR,
FLOPPY_TRK00=>FLOPPY_TRK00,
clear_cnt=>clear_track_cnt,
clock=>clock,
reset_not=>reset_not
);
CC: ControlCore port map
(
-- usb / ftdi bus
FTDI_DATA=>FTDI_DATA,
FTDI_RD_not=>FTDI_RD_not,
FTDI_WR=>FTDI_WR,
FTDI_TXE_not=>FTDI_TXE_not,
FTDI_RXF_not=>FTDI_RXF_not,
-- sram bus
SRAM_DATA=>SRAM_DATA,
SRAM_ADR=>SRAM_ADDR,
SRAM_RD_not=>SRAM_READ_not,
SRAM_WR_not=>SRAM_WRITE_not,
SRAM_CS_not=>SRAM_CS_not,
-- head position signals
Head_Position=>trackvalue,
Clear_Head_Position=>clear_track_cnt,
Head_moved=>headmoved,
Ack_head_move=>ackheadmoved,
-- external floppy signals
FLOPPY_READYSIGNAL=>FLOPPY_READY,
FLOPPY_SIDE=>FLOPPY_SIDE,
FLOPPY_DSKCHG=>FLOPPY_DSKCHG,
FLOPPY_INDEX=>FLOPPY_INDEX,
FLOPPY_WPT=>FLOPPY_WPT,
FLOPPY_SEL0=>FLOPPY_DS0,
FLOPPY_SEL1=>FLOPPY_DS1,
FLOPPY_SEL2=>FLOPPY_DS2,
FLOPPY_SEL3=>FLOPPY_MTRON,
FLOPPY_SELECT=>FLOPPY_SEL,
FLOPPY_DATA=>FLOPPY_DATA,
step_led=>step_led,
-- clock & reset
clock=>clock,
reset_not=>reset_not
);
end struct;
| gpl-3.0 | fcf2cf4ba1dd9127b913051dff8fe9ce | 0.455514 | 3.92226 | false | false | false | false |
terpstra/opa | syn/jtag.vhd | 1 | 5,277 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity jtag is
port(
addr_o : out std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
data_i : in std_logic_vector(31 downto 0);
gpio_o : out std_logic_vector( 3 downto 0);
we_xor_o : out std_logic;
rstn_o : out std_logic);
end jtag;
architecture rtl of jtag is
constant c_ir_wide : natural := 2;
constant c_IR_GPIO : std_logic_vector := "00";
constant c_IR_ADDR : std_logic_vector := "10";
constant c_IR_DATA : std_logic_vector := "11";
-- Virtual JTAG pins
signal s_tck : std_logic;
signal s_tdi : std_logic;
signal s_tdo : std_logic;
signal s_virtual_state_cdr : std_logic;
signal s_virtual_state_sdr : std_logic;
signal s_virtual_state_udr : std_logic;
signal s_virtual_state_uir : std_logic;
signal s_ir : std_logic_vector(c_ir_wide-1 downto 0);
signal r_ir : std_logic_vector(c_ir_wide-1 downto 0);
signal r_rstn : std_logic := '0';
signal r_xor : std_logic := '0';
signal r_gpio : std_logic_vector( 5 downto 0) := (others => '0');
signal r_addr : std_logic_vector(31 downto 0);
signal r_data : std_logic_vector(31 downto 0);
begin
vjtag : sld_virtual_jtag
generic map(
sld_instance_index => 99,
sld_ir_width => c_ir_wide)
port map(
ir_in => s_ir,
ir_out => r_ir,
jtag_state_cdr => open,
jtag_state_cir => open,
jtag_state_e1dr => open,
jtag_state_e1ir => open,
jtag_state_e2dr => open,
jtag_state_e2ir => open,
jtag_state_pdr => open,
jtag_state_pir => open,
jtag_state_rti => open,
jtag_state_sdr => open,
jtag_state_sdrs => open,
jtag_state_sir => open,
jtag_state_sirs => open,
jtag_state_tlr => open,
jtag_state_udr => open,
jtag_state_uir => open,
tck => s_tck,
tdi => s_tdi,
tdo => s_tdo,
tms => open,
virtual_state_cdr => s_virtual_state_cdr,
virtual_state_cir => open,
virtual_state_e1dr => open,
virtual_state_e2dr => open,
virtual_state_pdr => open,
virtual_state_sdr => s_virtual_state_sdr,
virtual_state_udr => s_virtual_state_udr,
virtual_state_uir => s_virtual_state_uir);
jtag : process(s_tck) is
begin
if rising_edge(s_tck) then
if s_virtual_state_uir = '1' then
r_ir <= s_ir;
end if;
if s_virtual_state_cdr = '1' then
case r_ir is
when c_IR_DATA => r_data <= data_i;
when others => null;
end case;
end if;
if s_virtual_state_sdr = '1' then
case r_ir is
when c_IR_GPIO => r_gpio <= s_tdi & r_gpio(r_gpio'high downto r_gpio'low+1);
when c_IR_ADDR => r_addr <= s_tdi & r_addr(r_addr'high downto r_addr'low+1);
when c_IR_DATA => r_data <= s_tdi & r_data(r_data'high downto r_data'low+1);
when others => null;
end case;
end if;
if s_virtual_state_udr = '1' then
case r_ir is
when c_IR_GPIO => r_rstn <= r_gpio(5); r_xor <= r_xor xor r_gpio(4);
when others => null;
end case;
end if;
end if;
end process;
with r_ir select
s_tdo <=
r_gpio(r_gpio'low) when c_IR_GPIO,
r_addr(r_addr'low) when c_IR_ADDR,
r_data(r_data'low) when c_IR_DATA,
'-' when others;
addr_o <= r_addr;
data_o <= r_data;
gpio_o <= r_gpio(gpio_o'range);
we_xor_o <= r_xor;
rstn_o <= r_rstn;
end rtl;
| gpl-3.0 | f84d307a1c81207e33f9bd66ef1dc111 | 0.575327 | 3.320957 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Card_Interface.vhd | 2 | 19,817 | -------------------------------------------------------------------------------------
-- This module is an interface to the Secure Data Card. This module is intended to be
-- used with the DE2 board.
--
-- This version of the interface supports only a 1-bit serial data transfer. This
-- allows the interface to support a MultiMedia card as well.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Interface is
component Altera_UP_SD_Card_Clock
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end component;
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
component Altera_UP_SD_CRC16_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end component;
component Altera_UP_SD_Signal_Trigger
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_signal : in std_logic;
o_trigger : out std_logic
);
end component;
component Altera_UP_SD_Card_48_bit_Command_Generator
generic (
-- Basic commands
COMMAND_0_GO_IDLE : STD_LOGIC_VECTOR(5 downto 0) := "000000";
COMMAND_2_ALL_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "000010";
COMMAND_3_SEND_RCA : STD_LOGIC_VECTOR(5 downto 0) := "000011";
COMMAND_4_SET_DSR : STD_LOGIC_VECTOR(5 downto 0) := "000100";
COMMAND_6_SWITCH_FUNCTION : STD_LOGIC_VECTOR(5 downto 0) := "000110";
COMMAND_7_SELECT_CARD : STD_LOGIC_VECTOR(5 downto 0) := "000111";
COMMAND_9_SEND_CSD : STD_LOGIC_VECTOR(5 downto 0) := "001001";
COMMAND_10_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "001010";
COMMAND_12_STOP_TRANSMISSION : STD_LOGIC_VECTOR(5 downto 0) := "001100";
COMMAND_13_SEND_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
COMMAND_15_GO_INACTIVE : STD_LOGIC_VECTOR(5 downto 0) := "001111";
-- Block oriented read/write/lock commands
COMMAND_16_SET_BLOCK_LENGTH : STD_LOGIC_VECTOR(5 downto 0) := "010000";
-- Block oriented read commands
COMMAND_17_READ_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "010001";
COMMAND_18_READ_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010010";
-- Block oriented write commands
COMMAND_24_WRITE_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "011000";
COMMAND_25_WRITE_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "011001";
COMMAND_27_PROGRAM_CSD : STD_LOGIC_VECTOR(5 downto 0) := "011011";
-- Block oriented write-protection commands
COMMAND_28_SET_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011100";
COMMAND_29_CLEAR_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011101";
COMMAND_30_SEND_PROTECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "011110";
-- Erase commands
COMMAND_32_ERASE_BLOCK_START : STD_LOGIC_VECTOR(5 downto 0) := "100000";
COMMAND_33_ERASE_BLOCK_END : STD_LOGIC_VECTOR(5 downto 0) := "100001";
COMMAND_38_ERASE_SELECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "100110";
-- Block lock commands
COMMAND_42_LOCK_UNLOCK : STD_LOGIC_VECTOR(5 downto 0) := "101010";
-- Command Type Settings
COMMAND_55_APP_CMD : STD_LOGIC_VECTOR(5 downto 0) := "110111";
COMMAND_56_GEN_CMD : STD_LOGIC_VECTOR(5 downto 0) := "111000";
-- Application Specific commands - must be preceeded with command 55.
ACOMMAND_6_SET_BUS_WIDTH : STD_LOGIC_VECTOR(5 downto 0) := "000110";
ACOMMAND_13_SD_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
ACOMMAND_22_SEND_NUM_WR_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010100";
ACOMMAND_23_SET_BLK_ERASE_COUNT : STD_LOGIC_VECTOR(5 downto 0) := "010101";
ACOMMAND_41_SEND_OP_CONDITION : STD_LOGIC_VECTOR(5 downto 0) := "101001";
ACOMMAND_42_SET_CLR_CARD_DETECT : STD_LOGIC_VECTOR(5 downto 0) := "101010";
ACOMMAND_51_SEND_SCR : STD_LOGIC_VECTOR(5 downto 0) := "110011";
-- First custom_command
FIRST_NON_PREDEFINED_COMMAND : STD_LOGIC_VECTOR(3 downto 0) := "1010"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_message_bit_out : in std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_predefined_message : in std_logic_vector(3 downto 0);
i_generate : in std_logic;
i_DSR : in std_logic_vector(15 downto 0);
i_OCR : in std_logic_vector(31 downto 0);
i_RCA : in std_logic_vector(15 downto 0);
o_dataout : out std_logic;
o_message_done : out std_logic;
o_valid : out std_logic;
o_returning_ocr : out std_logic;
o_returning_cid : out std_logic;
o_returning_rca : out std_logic;
o_returning_csd : out std_logic;
o_returning_status : out std_logic;
o_data_read : out std_logic;
o_data_write : out std_logic;
o_wait_cmd_busy : out std_logic;
o_last_cmd_was_55 : out std_logic;
o_response_type : out std_logic_vector(2 downto 0)
);
end component;
component Altera_UP_SD_Card_Response_Receiver
generic (
TIMEOUT : std_logic_vector(7 downto 0) := "00111000";
BUSY_WAIT : std_logic_vector(7 downto 0) := "00110000";
PROCESSING_DELAY : std_logic_vector(7 downto 0) := "00001000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_begin : in std_logic;
i_scan_pulse : in std_logic;
i_datain : in std_logic;
i_wait_cmd_busy : in std_logic;
i_response_type : in std_logic_vector(2 downto 0);
o_data : out std_logic_vector(127 downto 0);
o_CRC_passed : out std_logic;
o_timeout : out std_logic;
o_done : out std_logic
);
end component;
component Altera_UP_SD_Card_Control_FSM
generic (
PREDEFINED_COMMAND_GET_STATUS : STD_LOGIC_VECTOR(3 downto 0) := "1001"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC;
-- FSM Inputs
i_user_command_ready : in std_logic;
i_response_received : in STD_LOGIC;
i_response_timed_out : in STD_LOGIC;
i_response_crc_passed : in STD_LOGIC;
i_command_sent : in STD_LOGIC;
i_powerup_busy_n : in STD_LOGIC;
i_clocking_pulse_enable : in std_logic;
i_current_clock_mode : in std_logic;
i_user_message_valid : in std_logic;
i_last_cmd_was_55 : in std_logic;
i_allow_partial_rw : in std_logic;
-- FSM Outputs
o_generate_command : out STD_LOGIC;
o_predefined_command_ID : out STD_LOGIC_VECTOR(3 downto 0);
o_receive_response : out STD_LOGIC;
o_drive_CMD_line : out STD_LOGIC;
o_SD_clock_mode : out STD_LOGIC; -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_resetting : out std_logic;
o_card_connected : out STD_LOGIC;
o_command_completed : out std_logic;
o_clear_response_register : out std_logic;
o_enable_clock_generator : out std_logic
);
end component;
component Altera_UP_SD_Card_Buffer
generic (
TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- 1 bit port to transmit and receive data on the data line.
i_begin : in std_logic;
i_sd_clock_pulse_trigger : in std_logic;
i_transmit : in std_logic;
i_1bit_data_in : in std_logic;
o_1bit_data_out : out std_logic;
o_operation_complete : out std_logic;
o_crc_passed : out std_logic;
o_timed_out : out std_logic;
o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port : in std_logic;
i_address_16bit_port : in std_logic_vector(7 downto 0);
i_write_16bit : in std_logic;
i_16bit_data_in : in std_logic_vector(15 downto 0);
o_16bit_data_out : out std_logic_vector(15 downto 0)
);
end component;
-- Local wires
-- REGISTERED
signal sd_mode : std_logic;
-- SD Card Registers:
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_driver_stage_register : std_logic_vector(15 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_status_register_valid : std_logic;
-- UNREGISTERED
signal data_from_buffer : std_logic_vector(15 downto 0);
signal clock_generator_mode, enable_generator, SD_clock, create_message : std_logic;
signal send_next_bit, receive_next_bit : std_logic;
signal timed_out, response_done, passed_crc, begin_reading_response, resetting : std_logic;
signal returning_cid, returning_rca, returning_csd, returning_ocr : std_logic;
signal response_type : std_logic_vector(2 downto 0);
signal message_valid, messange_sent, data_to_CMD_line, CMD_tristate_buffer_enable, message_sent : std_logic;
signal predef_message_ID : std_logic_vector(3 downto 0);
signal receive_data_out : std_logic_vector(127 downto 0);
signal data_line_done, data_line_crc, data_line_timeout, data_line_direction, data_line_out : std_logic;
signal data_read, data_write, wait_cmd_busy, clear_response_register : std_logic;
signal response_done_combined : std_logic;
signal timeout_combined : std_logic;
signal crc_combined, allow_partial_rw : std_logic;
signal begin_data_line_operations, last_cmd_was_55, message_sent_trigger, returning_status : std_logic;
begin
-- Glue logic
SD_REG_driver_stage_register <= (OTHERS => '0');
response_done_combined <= (response_done and (not data_read) and (not data_write)) or
(response_done and (data_read or data_write) and data_line_done);
timeout_combined <= (timed_out and (not data_read) and (not data_write)) or
(timed_out and (data_read or data_write) and data_line_timeout);
crc_combined <= (passed_crc and (not data_read) and (not data_write)) or
(passed_crc and (data_read or data_write) and data_line_crc);
begin_data_line_operations <= (data_read and message_sent) or (data_write and response_done);
-- Partial read and write are only allowed when both bit 79 (partial read allowed) is high and
-- bit 21 (partial write allowed) is high.
allow_partial_rw <= SD_REG_card_specific_data(79) and SD_REG_card_specific_data(21);
-- SD Card control registers
control_regs: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
SD_REG_operating_conditions_register <= (OTHERS => '0');
SD_REG_card_identification_number <= (OTHERS => '0');
SD_REG_relative_card_address <= (OTHERS => '0');
SD_REG_card_specific_data <= (OTHERS => '0');
SD_REG_status_register <= (OTHERS => '0');
SD_REG_response_R1 <= (OTHERS => '1');
SD_REG_status_register_valid <= '0';
elsif (rising_edge(i_clock)) then
if ((response_type = "001") and (response_done = '1') and (returning_status = '0') and (clear_response_register = '0')) then
SD_REG_response_R1 <= receive_data_out(31 downto 0);
elsif (clear_response_register = '1') then
SD_REG_response_R1 <= (OTHERS => '1');
end if;
if (resetting = '1') then
SD_REG_operating_conditions_register <= (OTHERS => '0');
elsif ((returning_ocr = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_operating_conditions_register <= receive_data_out(31 downto 0);
end if;
if ((returning_cid = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_card_identification_number <= receive_data_out;
end if;
if ((returning_rca = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_relative_card_address <= receive_data_out(31 downto 16);
end if;
if ((returning_csd = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_card_specific_data <= receive_data_out;
end if;
if (message_sent_trigger = '1') then
SD_REG_status_register_valid <= '0';
elsif ((returning_status = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
SD_REG_status_register <= receive_data_out(31 downto 0);
SD_REG_status_register_valid <= '1';
end if;
end if;
end process;
-- Instantiated components
command_generator: Altera_UP_SD_Card_48_bit_Command_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_message_bit_out => send_next_bit,
i_command_ID => i_command_ID,
i_argument => i_argument,
i_predefined_message => predef_message_ID,
i_generate => create_message,
i_DSR => SD_REG_driver_stage_register,
i_OCR => SD_REG_operating_conditions_register,
i_RCA => SD_REG_relative_card_address,
o_dataout => data_to_CMD_line,
o_message_done => message_sent,
o_valid => message_valid,
o_returning_ocr => returning_ocr,
o_returning_cid => returning_cid,
o_returning_rca => returning_rca,
o_returning_csd => returning_csd,
o_returning_status => returning_status,
o_data_read => data_read,
o_data_write => data_write,
o_wait_cmd_busy => wait_cmd_busy,
o_last_cmd_was_55 => last_cmd_was_55,
o_response_type => response_type
);
response_receiver: Altera_UP_SD_Card_Response_Receiver PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_begin => begin_reading_response,
i_scan_pulse => receive_next_bit,
i_datain => b_SD_cmd,
i_response_type => response_type,
i_wait_cmd_busy => wait_cmd_busy,
o_data => receive_data_out,
o_CRC_passed => passed_crc,
o_timeout => timed_out,
o_done => response_done
);
control_FSM: Altera_UP_SD_Card_Control_FSM PORT MAP
(
-- Clock and Reset signals
i_clock => i_clock,
i_reset_n => i_reset_n,
-- FSM Inputs
i_user_command_ready => i_user_command_ready,
i_clocking_pulse_enable => receive_next_bit,
i_response_received => response_done_combined,
i_response_timed_out => timeout_combined,
i_response_crc_passed => crc_combined,
i_command_sent => message_sent,
i_powerup_busy_n => SD_REG_operating_conditions_register(31),
i_current_clock_mode => clock_generator_mode,
i_user_message_valid => message_valid,
i_last_cmd_was_55 => last_cmd_was_55,
i_allow_partial_rw => allow_partial_rw,
-- FSM Outputs
o_generate_command => create_message,
o_predefined_command_ID => predef_message_ID,
o_receive_response => begin_reading_response,
o_drive_CMD_line => CMD_tristate_buffer_enable,
o_SD_clock_mode => sd_mode, -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
o_card_connected => o_card_connected,
o_command_completed => o_command_completed,
o_resetting => resetting,
o_clear_response_register => clear_response_register,
o_enable_clock_generator => enable_generator
);
clock_generator: Altera_UP_SD_Card_Clock PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_mode => sd_mode,
i_enable => enable_generator,
o_SD_clock => SD_clock,
o_clock_mode => clock_generator_mode,
o_trigger_receive => receive_next_bit,
o_trigger_send => send_next_bit
);
SD_clock_pulse_trigger: Altera_UP_SD_Signal_Trigger PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_signal => message_sent,
o_trigger => message_sent_trigger
);
data_line: Altera_UP_SD_Card_Buffer
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- 1 bit port to transmit and receive data on the data line.
i_begin => begin_data_line_operations,
i_sd_clock_pulse_trigger => (data_write and send_next_bit) or ((not data_write) and receive_next_bit),
i_transmit => data_write,
i_1bit_data_in => b_SD_dat,
o_1bit_data_out => data_line_out,
o_operation_complete => data_line_done,
o_crc_passed => data_line_crc,
o_timed_out => data_line_timeout,
o_dat_direction => data_line_direction,
-- 16 bit port to be accessed by a user circuit.
i_enable_16bit_port => i_buffer_enable,
i_address_16bit_port => i_buffer_address,
i_write_16bit => i_buffer_write,
i_16bit_data_in => i_buffer_data_in,
o_16bit_data_out => data_from_buffer
);
-- Buffer output registers.
buff_regs: process(i_clock, i_reset_n, data_from_buffer)
begin
if (i_reset_n = '0') then
o_buffer_data_out <= (OTHERS=> '0');
elsif (rising_edge(i_clock)) then
o_buffer_data_out <= data_from_buffer;
end if;
end process;
-- Circuit outputs.
o_command_valid <= message_valid;
o_command_timed_out <= timeout_combined;
o_command_crc_failed <= not crc_combined;
o_SD_clock <= SD_clock;
b_SD_cmd <= data_to_CMD_line when (CMD_tristate_buffer_enable = '1') else 'Z';
b_SD_dat <= data_line_out when (data_line_direction = '1') else 'Z';
b_SD_dat3 <= 'Z'; -- Set SD card to SD mode.
-- SD card registers
o_SD_REG_card_identification_number <= SD_REG_card_identification_number;
o_SD_REG_relative_card_address <= SD_REG_relative_card_address;
o_SD_REG_operating_conditions_register <= SD_REG_operating_conditions_register;
o_SD_REG_card_specific_data <= SD_REG_card_specific_data;
o_SD_REG_status_register <= SD_REG_status_register;
o_SD_REG_response_R1 <= SD_REG_response_R1;
o_SD_REG_status_register_valid <= SD_REG_status_register_valid;
end rtl;
| mit | 34fcb3866b689c686bc9fc5cddf20e42 | 0.647727 | 2.718754 | false | false | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/Adder_2x16.vhd | 1 | 796 | library ieee;
use ieee.std_logic_1164.all;
entity Adder_2x16 is
port (
isSubtraction: in STD_LOGIC;
input_A, input_B: in STD_LOGIC_VECTOR(15 DOWNTO 0);
carry_out: out STD_LOGIC;
output: out STD_LOGIC_VECTOR(15 DOWNTO 0));
end Adder_2x16;
architecture skeleton of Adder_2x16 is
begin
process(input_A, input_B, isSubtraction)
variable sum, bOrNotb : STD_LOGIC_VECTOR(15 downto 0);
variable carry : STD_LOGIC;
begin
if (isSubtraction = '1') then
bOrNotb := NOT input_B;
else
bOrNotb := input_B;
end if;
carry := isSubtraction;
for i in 0 to 15 loop
sum(i) := input_A(i) xor bOrNotb(i) xor carry;
carry := (input_A(i) and bOrNotb(i)) or ((input_A(i) xor bOrNotb(i)) and carry);
end loop;
carry_out <= carry;
output <= sum;
end process;
end skeleton; | gpl-3.0 | fe3e6df6af6f353224e48ee1a23d0bec | 0.673367 | 2.584416 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/livelli2impulsi.vhd | 1 | 1,547 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:10:06 12/28/2015
-- Design Name:
-- Module Name: livelli2impulsi - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity livelli2impulsi is
Port ( input : in STD_LOGIC;
clock : in STD_LOGIC;
output : out STD_LOGIC);
end livelli2impulsi;
architecture Behavioral of livelli2impulsi is
signal output_sig : std_logic := '0';
begin
output <= output_sig;
generazione_segnale_impulsivo : process(clock)
variable state : std_logic := '0';
begin
if(rising_edge(clock)) then
if(state = '0' and input = '1') then
output_sig <= '1';
state := '1';
elsif(state = '1' and input = '1') then
output_sig <= '0';
else -- Se input = '0' e si trova in qualsiasi stato
state := '0';
output_sig <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 05a1d1d898bad506efac7f659f8457d5 | 0.564964 | 3.507937 | false | false | false | false |
quicky2000/top_alphanumeric | top_alphanumeric.vhd | 1 | 4,101 | --
-- This file is part of top_alphanumeric
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_alphanumeric is
Port ( clk : in STD_LOGIC;
w1a : inout STD_LOGIC_VECTOR (15 downto 0);
w1b : inout STD_LOGIC_VECTOR (15 downto 0);
w2c : inout STD_LOGIC_VECTOR (15 downto 0);
rx : in STD_LOGIC;
tx : inout STD_LOGIC
);
end top_alphanumeric;
architecture Behavioral of top_alphanumeric is
COMPONENT clock_25mhz
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
-- Clock signal
signal clk_25mhz : std_logic;
signal reset : std_logic;
-- Screen control signals
signal vsync : std_logic;
signal hsync : std_logic;
signal enable : std_logic;
signal screen_right_left : std_logic;
signal screen_up_down : std_logic;
signal r : std_logic_vector ( 5 downto 0);
signal g : std_logic_vector ( 5 downto 0);
signal b : std_logic_vector ( 5 downto 0);
-- Audio signals
signal audio_right : std_logic;
signal audio_left : std_logic;
-- Signals coming from image contoler
signal x_out : std_logic_vector( 9 downto 0);
signal y_out : std_logic_vector( 8 downto 0);
signal vsync_ok : std_logic;
signal hsync_ok : std_logic;
signal enable_ok : std_logic;
-- Signals to write in screen memory
signal addr : std_logic_vector(12 downto 0) := (others => '0');
signal char_code : std_logic_vector(7 downto 0);
signal color_code : std_logic_vector(9 downto 0);
signal write_enable : std_logic := '0';
begin
Inst_clock_25mhz: clock_25mhz PORT MAP(
CLKIN_IN => clk,
CLKFX_OUT => clk_25mhz,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
Inst_giovanni_card : entity work.giovanni_card PORT MAP(
w1a => w1a,
w1b => w1b,
scr_red => r,
scr_green => g,
scr_blue => b,
scr_clk => clk_25mhz,
scr_hsync => hsync_ok,
scr_vsync => vsync_ok,
scr_enable => enable_ok,
scr_right_left => screen_right_left,
scr_up_down => screen_up_down,
audio_right => audio_right,
audio_left => audio_left,
audio_stereo_ok => open,
audio_plugged => open,
io => open
);
Inst_driver_sharp : entity work.driver_sharp(behavorial) PORT MAP(
clk => clk_25mhz,
rst => reset,
vsync => vsync,
hsync => hsync,
enable => enable,
x_out => x_out,
y_out => y_out
);
inst_image_controler : entity work.image_controler PORT MAP(
clk => clk_25mhz,
rst => reset,
r => r,
g => g,
b => b,
x => x_out,
y => y_out,
hsync_in => hsync,
vsync_in => vsync,
enable_in => enable,
write_enable => write_enable,
write_addr => addr,
char_code => char_code,
color_code => color_code,
hsync_out => hsync_ok,
vsync_out => vsync_ok,
enable_out => enable_ok
);
reset <= '0';
screen_right_left <= '1';
screen_up_down <= '1';
audio_right <= '0';
audio_left <= '0';
end Behavioral;
| gpl-3.0 | d1355404991c6bafa84fa951d58106e5 | 0.634723 | 3.272945 | false | false | false | false |
terpstra/opa | opa_prim_mul.vhd | 1 | 14,474 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
-- Used to implement FP and integer multipliers
entity opa_prim_mul is
generic(
g_wide : natural;
g_regout : boolean;
g_regwal : boolean;
g_target : t_opa_target);
port(
clk_i : in std_logic;
a_i : in std_logic_vector( g_wide-1 downto 0);
b_i : in std_logic_vector( g_wide-1 downto 0);
x_o : out std_logic_vector(2*g_wide-1 downto 0));
end opa_prim_mul;
architecture rtl of opa_prim_mul is
constant c_lut_width : natural := g_target.lut_width;
constant c_add_width : natural := g_target.add_width;
constant c_post_adder : boolean := g_target.post_adder;
-------------------------------------------------------------------------------------------
-- Wallace adder tree section --
-------------------------------------------------------------------------------------------
-- Helpful to simplify wallace recursion
function f_submatrix(rows : natural; x : t_opa_matrix) return t_opa_matrix is
variable result : t_opa_matrix(x'low(1)+rows-1 downto x'low(1), x'range(2));
begin
for i in result'range(1) loop
for j in result'range(2) loop
result(i,j) := x(i,j);
end loop;
end loop;
return result;
end f_submatrix;
-- Reasonable Wallace-tree reduction sizes
type t_options is array(natural range <>) of natural;
constant c_wallace_options : t_options(4 downto 0) := (1, 3, 5, 6, 7);
constant c_wallace_bits_out : natural := f_opa_log2(c_wallace_options(0)+1);
subtype t_wallace_bits_out is std_logic_vector(c_wallace_bits_out-1 downto 0);
type t_wallace_lut is array(natural range <>) of t_wallace_bits_out;
function f_wallace_table(bits : natural) return t_wallace_lut is
variable row_in : unsigned(bits-1 downto 0);
variable row_out : unsigned(t_wallace_bits_out'range);
variable result : t_wallace_lut(2**bits-1 downto 0);
variable c : natural := 0;
begin
for i in result'range loop
row_in := to_unsigned(i, bits);
c := 0; -- count bits
for i in row_in'range loop
if row_in(i) = '1' then c := c + 1; end if;
end loop;
row_out := to_unsigned(c, c_wallace_bits_out);
for j in row_out'range loop
result(i)(j) := row_out(j);
end loop;
end loop;
return result;
end f_wallace_table;
constant c_wallace_lut1 : t_wallace_lut(2**1-1 downto 0) := f_wallace_table(1);
constant c_wallace_lut3 : t_wallace_lut(2**3-1 downto 0) := f_wallace_table(3);
constant c_wallace_lut5 : t_wallace_lut(2**5-1 downto 0) := f_wallace_table(5);
constant c_wallace_lut6 : t_wallace_lut(2**6-1 downto 0) := f_wallace_table(6);
constant c_wallace_lut7 : t_wallace_lut(2**7-1 downto 0) := f_wallace_table(7);
function f_wallace_lut(bits : natural; x : std_logic_vector) return std_logic_vector is
constant c_bad : t_wallace_bits_out := (others => 'X');
begin
if f_opa_safe(x) = '1' then
if bits = 1 then return c_wallace_lut1(to_integer(unsigned(x(0 downto 0)))); end if;
if bits = 3 then return c_wallace_lut3(to_integer(unsigned(x(2 downto 0)))); end if;
if bits = 5 then return c_wallace_lut5(to_integer(unsigned(x(4 downto 0)))); end if;
if bits = 6 then return c_wallace_lut6(to_integer(unsigned(x(5 downto 0)))); end if;
if bits = 7 then return c_wallace_lut7(to_integer(unsigned(x(6 downto 0)))); end if;
assert (false) report "Invalid Wallace reduction" severity failure;
end if;
return c_bad;
end f_wallace_lut;
function f_wallace(x : t_opa_matrix) return t_opa_matrix is
constant rows_in : natural := x'length(1); -- How many rows to combine?
variable rows_out : natural := 0;
variable row : natural := 0;
variable step_in : natural;
variable step_out : natural;
variable result : t_opa_matrix(x'range(1), x'range(2)) := (others => (others => '0'));
variable pad : t_opa_matrix(c_add_width-1 downto 0, x'range(2)) := (others => (others => '0'));
variable chunk : std_logic_vector(c_wallace_options(0)-1 downto 0);
begin
if x'length(1) <= c_add_width then
for i in x'range(1) loop
for j in x'range(2) loop
pad(i,j) := x(i,j);
end loop;
end loop;
return pad;
end if;
while row < rows_in loop
-- Pick reduction step size
step_in := 99; -- should never be read
for i in c_wallace_options'range loop
if c_wallace_options(i) <= c_lut_width and -- supported by hardware?
c_wallace_options(i) <= rows_in-row then -- not too big?
step_in := c_wallace_options(i);
end if;
end loop;
-- This results in a reduction to
step_out := f_opa_log2(step_in+1);
-- Map the wallace tree
for i in x'range(2) loop
chunk := (others => '0');
for j in 0 to step_in-1 loop
chunk(j) := x(row+j, i);
end loop;
chunk(t_wallace_bits_out'range) := f_wallace_lut(step_in, chunk);
for j in 0 to step_out-1 loop
if i+j <= result'high(2) then -- we know multiplication will never carry
result(rows_out+j, i+j) := chunk(j);
end if;
end loop;
end loop;
row := row + step_in;
rows_out := rows_out + step_out;
end loop;
return f_wallace(f_submatrix(rows_out, result));
end f_wallace;
-------------------------------------------------------------------------------------------
-- DSP hardware multiplier section --
-------------------------------------------------------------------------------------------
-- Plan the reduction. Either using a post_adder (_add_) or not (_raw_).
-- If using the post adder, must make sure to use full width so the shift is supported.
constant c_dsp_wide : natural := g_target.mul_width;
constant c_raw_parts : natural := (g_wide+c_dsp_wide-1)/c_dsp_wide;
constant c_raw_mul_wide : natural := (g_wide+c_raw_parts-1)/c_raw_parts; -- use smallest possible
constant c_raw_wallace : natural := 2*c_raw_parts-1;
constant c_raw_wide : natural := c_raw_mul_wide*c_raw_parts;
constant c_add_parts : natural := ((g_wide+2*c_dsp_wide-1)/(2*c_dsp_wide))*2; -- must be even
constant c_add_mul_wide : natural := c_dsp_wide; -- must use HW width so shift is acceptable
constant c_add_wallace : natural := c_add_parts+(c_add_parts/2)-1;
constant c_add_wide : natural := c_add_mul_wide*c_add_parts;
constant c_wallace : natural := f_opa_choose(c_post_adder, c_add_wallace, c_raw_wallace);
constant c_wide : natural := f_opa_choose(c_post_adder, c_add_wide, c_raw_wide);
constant c_num_sum : natural := f_opa_choose(c_wallace<c_add_width, c_wallace, c_add_width);
constant c_zeros : unsigned(c_add_mul_wide-1 downto 0) := (others => '0');
-- Register stages
type t_raw_mul_out is array(c_raw_parts*c_raw_parts -1 downto 0) of unsigned(2*c_raw_mul_wide-1 downto 0);
type t_add_mul_out is array(c_add_parts*c_add_parts/2-1 downto 0) of unsigned(3*c_add_mul_wide-1 downto 0);
type t_sum_in is array(c_num_sum-1 downto 0) of unsigned(2*c_wide-1 downto 0);
signal r_a : unsigned(c_wide-1 downto 0);
signal r_b : unsigned(c_wide-1 downto 0);
signal s_mul_a : t_add_mul_out;
signal s_mul_r : t_raw_mul_out;
signal r_mul_a : t_add_mul_out; -- optional register (g_regwal)
signal r_mul_r : t_raw_mul_out; -- optional register (g_regwal)
signal s_wal_i : t_opa_matrix(c_wallace -1 downto 0, 2*c_wide-1 downto 0) := (others => (others => '0'));
signal s_wal_o : t_opa_matrix(c_add_width-1 downto 0, 2*c_wide-1 downto 0);
signal r_wal : t_sum_in; -- result of wallace tree
signal s_sum3 : unsigned(2*c_wide-1 downto 0);
signal s_sumx : unsigned(2*c_wide-1 downto 0);
signal s_sum : unsigned(2*c_wide-1 downto 0);
signal r_sum : unsigned(2*c_wide-1 downto 0);
begin
check_add_width :
assert (g_target.add_width > 1)
report "add_width must be greater than 1"
severity failure;
check_mul_width :
assert (g_target.mul_width > 0)
report "mul_width must be greater than 0"
severity failure;
-- Register and pad the inputs
edge1 : process(clk_i) is
begin
if rising_edge(clk_i) then
r_a <= (others => '0');
r_b <= (others => '0');
r_a(a_i'range) <= unsigned(a_i);
r_b(b_i'range) <= unsigned(b_i);
end if;
end process;
-- Deal with simple DSP hardware
raw_mul : if not c_post_adder generate
mul_rows : for i in 0 to c_raw_parts-1 generate
mul_cols : for j in 0 to c_raw_parts-1 generate
s_mul_r(i*c_raw_parts + j) <=
r_a(c_raw_mul_wide*(i+1)-1 downto c_raw_mul_wide*i) *
r_b(c_raw_mul_wide*(j+1)-1 downto c_raw_mul_wide*j);
end generate;
end generate;
-- Register the results of native DSP blocks
-- This is bypassed when g_regwal is false
edge2 : process(clk_i) is
begin
if rising_edge(clk_i) then
r_mul_r <= s_mul_r;
end if;
end process;
-- Remap the DSP outputs into the wallace input
-- Example: 7 parts => 12 rows = 2*x - 2
-- AAAAAAA
-- AAAAAAA
-- BBBBBBB
-- BBBBBBB
-- CCCCCCC
-- CCCCCCC
-- DDDDDDD
-- DDDDDDD
-- EEEEEEE
-- EEEEEEE
-- FFFFFFF
-- FFFFFFF
-- GGGGGGG
--GGGGGGG <<= wraps around
rows : for i in 0 to c_raw_parts-1 generate
cols : for j in 0 to c_raw_parts-1 generate
bitsl : for b in 0 to c_raw_mul_wide-1 generate
s_wal_i((2*i + 0) mod c_wallace, (i+j)*c_raw_mul_wide + b) <=
r_mul_r(i*c_raw_parts + j)(b) when g_regwal else
s_mul_r(i*c_raw_parts + j)(b);
end generate;
bitsh : for b in c_raw_mul_wide to 2*c_raw_mul_wide-1 generate
s_wal_i((2*i + 1) mod c_wallace, (i+j)*c_raw_mul_wide + b) <=
r_mul_r(i*c_raw_parts + j)(b) when g_regwal else
s_mul_r(i*c_raw_parts + j)(b);
end generate;
end generate;
end generate;
end generate;
-- Exploit DSP mul+add architecture
add_mul : if c_post_adder generate
mul_rows : for i in 0 to c_add_parts/2-1 generate
mul_cols : for j in 0 to c_add_parts-1 generate
s_mul_a(i*c_add_parts + j) <=
(c_zeros &
(r_a(c_add_mul_wide*(2*i+1)-1 downto c_add_mul_wide*(2*i+0)) *
r_b(c_add_mul_wide*( j+1)-1 downto c_add_mul_wide* j))) +
((r_a(c_add_mul_wide*(2*i+2)-1 downto c_add_mul_wide*(2*i+1)) *
r_b(c_add_mul_wide*( j+1)-1 downto c_add_mul_wide* j)) &
c_zeros);
end generate;
end generate;
edge2 : process(clk_i) is
begin
if rising_edge(clk_i) then
r_mul_a <= s_mul_a;
end if;
end process;
-- Example: 128 has 8 parts => 11 to combine (instead of 15)
-- AAA
-- BBBAAA
-- CCCBBBAAA
-- DDDCCCBBBAAA
-- EEEDDDCCCBBB
-- FFFEEEDDDCCC
-- GGGFFFEEEDDD
-- HHHGGGFFFEEE
-- HHHGGGFFF
-- HHHGGG
-- HHH
rows : for i in 0 to c_add_parts/2-1 generate
cols : for j in 0 to c_add_parts-1 generate -- j = the letters in the example
bits : for b in 0 to 3*c_add_mul_wide-1 generate
s_wal_i(c_add_parts/2-1-i+j, (2*i+j)*c_add_mul_wide + b) <=
r_mul_a(i*c_add_parts + j)(b) when g_regwal else
s_mul_a(i*c_add_parts + j)(b);
end generate;
end generate;
end generate;
end generate;
-- Compute the Wallace tree result
s_wal_o <= f_wallace(s_wal_i);
-- Register the result of a wallace tree
edge3 : process(clk_i) is
begin
if rising_edge(clk_i) then
for i in 0 to c_num_sum-1 loop
r_wal(i) <= unsigned(f_opa_select_row(s_wal_o, i));
end loop;
end if;
end process;
-- Hold quartus' hand. Appalling.
ternary : if c_num_sum = 3 generate
prim : opa_prim_ternary
generic map(
g_wide => 2*c_wide)
port map(
a_i => r_wal(0),
b_i => r_wal(1),
c_i => r_wal(2),
x_o => s_sum3);
end generate;
-- Finally, sum the output
sum : process(r_wal) is
variable acc : unsigned(s_sumx'range);
begin
acc := r_wal(0);
for i in 1 to c_num_sum-1 loop
acc := acc + r_wal(i);
end loop;
s_sumx <= acc;
end process;
s_sum <= s_sum3 when c_num_sum=3 else s_sumx;
reg : process(clk_i) is
begin
if rising_edge(clk_i) then
r_sum <= s_sum;
end if;
end process;
x_o <= std_logic_vector(r_sum(x_o'range)) when g_regout else
std_logic_vector(s_sum(x_o'range));
end rtl;
| gpl-3.0 | b028509f43fca9dd3fb04079cd84c741 | 0.580904 | 3.106675 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core1/fsm_dds_wrapper.vhd | 1 | 2,911 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 16:36:50
-- Design Name:
-- Module Name: fsm_dds_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm_dds_wrapper is
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
count_hit : in STD_LOGIC;
valid_in_out : out STD_LOGIC;
reset_n_all : out STD_LOGIC;
done : out STD_LOGIC);
end fsm_dds_wrapper;
architecture Behavioral of fsm_dds_wrapper is
type state is (idle, reset_dds, waiting_for_count_hit, op_done);
signal current_state, next_state : state := idle;
begin
registro_stato : process(clock, reset_n, next_state)
begin
if(reset_n = '0') then
current_state <= idle;
elsif(rising_edge(clock)) then
current_state <= next_state;
end if;
end process;
fsm_next_state : process(current_state, reset_n, valid_in, count_hit)
begin
case current_state is
when idle =>
if(valid_in = '1') then
next_state <= reset_dds;
else
next_state <= idle;
end if;
when reset_dds =>
next_state <= waiting_for_count_hit;
when waiting_for_count_hit =>
if(count_hit = '1') then
next_state <= op_done;
else
next_state <= waiting_for_count_hit;
end if;
when op_done =>
if(valid_in = '1') then
next_state <= reset_dds;
else
next_state <= op_done;
end if;
end case;
end process;
fsm_output : process(current_state)
begin
valid_in_out <= '0';
reset_n_all <= '1';
done <= '0';
case current_state is
when idle =>
reset_n_all <= '0';
when reset_dds =>
valid_in_out <= '1';
reset_n_all <= '0';
when waiting_for_count_hit =>
when op_done =>
reset_n_all <= '0';
done <= '1';
end case;
end process;
end Behavioral;
| gpl-2.0 | 08271055c84b3eb6022e7c9a6801ab3e | 0.489523 | 4.134943 | false | false | false | false |
terpstra/opa | opa_riscv_pkg.vhd | 1 | 27,132 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
-- RISC-V ISA
package opa_riscv_pkg is
constant c_opa_rv32 : t_opa_isa_info := (
big_endian => false,
num_arch => 32,
imm_wide => 32,
op_wide => 32,
page_size => 4096);
function f_opa_accept_rv32(config : t_opa_config) return std_logic;
function f_opa_decode_rv32(config : t_opa_config; x : std_logic_vector) return t_opa_op;
end package;
package body opa_riscv_pkg is
constant c_arch_wide : natural := f_opa_log2(c_opa_rv32.num_arch);
function f_zero(x : std_logic_vector) return std_logic is
begin
return f_opa_and(not x(c_arch_wide-1 downto 0));
end f_zero;
function f_one(x : std_logic_vector) return std_logic is
begin
return f_opa_and(not x(c_arch_wide-1 downto 1)) and x(0);
end f_one;
function f_parse_rtype (x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archb(c_arch_wide-1 downto 0) := x(24 downto 20);
result.archa(c_arch_wide-1 downto 0) := x(19 downto 15);
result.archx(c_arch_wide-1 downto 0) := x(11 downto 7);
result.geta := '1'; -- use both input registers
result.getb := '1';
result.setx := not f_zero(x);
result.bad := '0';
result.jump := '0';
result.take := '0';
result.force := '0';
result.order := '0';
return result;
end f_parse_rtype;
function f_parse_itype (x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archa(c_arch_wide-1 downto 0) := x(19 downto 15);
result.archx(c_arch_wide-1 downto 0) := x(11 downto 7);
result.getb := '0'; -- immediate
result.geta := '1';
result.setx := not f_zero(result.archx);
result.bad := '0';
result.jump := '0';
result.take := '0';
result.force := '0';
result.order := '0';
result.imm := (others => x(31));
result.imm(10 downto 0) := x(30 downto 20);
return result;
end f_parse_itype;
function f_parse_stype (x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archb(c_arch_wide-1 downto 0) := x(24 downto 20);
result.archa(c_arch_wide-1 downto 0) := x(19 downto 15);
result.getb := '1';
result.geta := '1';
result.setx := '0';
result.bad := '0';
result.jump := '0';
result.take := '0';
result.force := '0';
result.order := '1';
result.imm := (others => x(31));
result.imm(10 downto 5) := x(30 downto 25);
result.imm( 4 downto 0) := x(11 downto 7);
return result;
end f_parse_stype;
function f_parse_utype (x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archx(c_arch_wide-1 downto 0) := x(11 downto 7);
result.geta := '0';
result.getb := '0';
result.setx := not f_zero(result.archx);
result.bad := '0';
result.jump := '0';
result.take := '0';
result.force := '0';
result.order := '0';
result.imm(31 downto 12) := x(31 downto 12);
result.imm(11 downto 0) := (others => '0');
return result;
end f_parse_utype;
function f_parse_sbtype(x : std_logic_vector) return t_opa_op is
variable result : t_opa_op := c_opa_op_undef;
begin
result.archb(c_arch_wide-1 downto 0) := x(24 downto 20);
result.archa(c_arch_wide-1 downto 0) := x(19 downto 15);
result.getb := '1';
result.geta := '1';
result.setx := '0';
result.bad := '0';
result.jump := '1';
result.take := x(31); -- static prediction: negative = taken
result.force := '0';
result.pop := '0';
result.push := '0';
result.order := '0';
result.imm := (others => x(31));
result.imm(11) := x(7);
result.imm(10 downto 5) := x(30 downto 25);
result.imm( 4 downto 1) := x(11 downto 8);
result.imm(0) := '0';
result.immb := result.imm;
return result;
end f_parse_sbtype;
-- JAL has a special format
function f_decode_jal (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := c_opa_op_undef;
begin
op.archx(c_arch_wide-1 downto 0) := x(11 downto 7);
op.getb := '0'; -- imm
op.geta := '0'; -- PC
op.setx := not f_zero(op.archx);
op.bad := '0';
op.jump := '1';
op.take := '1';
op.force := '1';
op.order := '0';
op.pop := '0';
op.push := f_one(op.archx);
-- a very strange immediate format:
op.imm := (others => x(31));
op.imm(19 downto 12) := x(19 downto 12);
op.imm(11) := x(20);
op.imm(10 downto 1) := x(30 downto 21);
op.imm(0) := '0';
op.immb := op.imm;
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '-';
op.arg.fmode := c_opa_fast_jump;
op.fast := '1';
return op;
end f_decode_jal;
function f_decode_jalr (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
variable ret : std_logic;
begin
-- immb stays don't care as we can't make a static prediction anyway
ret := f_zero(op.archx) and f_one(op.archa); -- is this a return?
op.jump := '1';
op.take := ret;
op.force := '0';
op.pop := ret;
op.push := f_one(op.archx);
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '-';
op.arg.fmode := c_opa_fast_jump;
op.fast := '1';
return op;
end f_decode_jalr;
function f_decode_lui (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_utype(x);
begin
op.arg.lut := "1010"; -- X = B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_lui;
function f_decode_auipc(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_utype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addl;
op.fast := '1';
return op;
end f_decode_auipc;
function f_decode_beq (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_sbtype(x);
begin
op.arg.adder.eq := '1';
op.arg.adder.nota := '1';
op.arg.adder.notb := '0';
op.arg.adder.cin := '1';
op.arg.adder.sign := '0';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_beq;
function f_decode_bne (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_sbtype(x);
begin
op.arg.adder.eq := '1';
op.arg.adder.nota := '0';
op.arg.adder.notb := '1';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bne;
function f_decode_blt (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_sbtype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '1'; -- x=(a<b)=(b-a>0)=(b-a-1>=0)=overflow(b-a-1)=overflow(b+!a)
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '1';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_blt;
function f_decode_bge (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_sbtype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>=b)=(a-b>=0)=overflow(a-b)=overflow(a+!b+1)
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '1';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bge;
function f_decode_bltu (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_sbtype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '1'; -- x=(a<b)=(b-a>0)=(b-a-1>=0)=overflow(b-a-1)=overflow(b+!a)
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bltu;
function f_decode_bgeu (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_sbtype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '0'; -- x=(a>=b)=(a-b>=0)=overflow(a-b)=overflow(a+!b+1)
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '0';
op.arg.adder.fault := '1';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_bgeu;
function f_decode_lb (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.ldst.store := '0';
op.arg.ldst.sext := '1';
op.arg.ldst.size := c_opa_ldst_byte;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lb;
function f_decode_lh (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.ldst.store := '0';
op.arg.ldst.sext := '1';
op.arg.ldst.size := c_opa_ldst_half;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lh;
function f_decode_lw (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.ldst.store := '0';
op.arg.ldst.sext := '1';
op.arg.ldst.size := c_opa_ldst_word;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lw;
function f_decode_lbu (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.ldst.store := '0';
op.arg.ldst.sext := '0';
op.arg.ldst.size := c_opa_ldst_byte;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lbu;
function f_decode_lhu (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.ldst.store := '0';
op.arg.ldst.sext := '0';
op.arg.ldst.size := c_opa_ldst_half;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_lhu;
function f_decode_sb (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_stype(x);
begin
op.arg.ldst.store := '1';
op.arg.ldst.sext := '-';
op.arg.ldst.size := c_opa_ldst_byte;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_sb;
function f_decode_sh (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_stype(x);
begin
op.arg.ldst.store := '1';
op.arg.ldst.sext := '-';
op.arg.ldst.size := c_opa_ldst_half;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_sh;
function f_decode_sw (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_stype(x);
begin
op.arg.ldst.store := '1';
op.arg.ldst.sext := '-';
op.arg.ldst.size := c_opa_ldst_word;
op.arg.smode := c_opa_slow_ldst;
op.fast := '0';
return op;
end f_decode_sw;
function f_decode_addi (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addl;
op.fast := '1';
return op;
end f_decode_addi;
function f_decode_slti (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '1'; -- x=(a<b)=(b-a>0)=(b-a-1>=0)=overflow(b-a-1)=overflow(b+!a)
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '1';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_slti;
function f_decode_sltiu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '1'; -- x=(a<b)=(b-a>0)=(b-a-1>=0)=overflow(b-a-1)=overflow(b+!a)
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_sltiu;
function f_decode_xori (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.lut := "0110"; -- X = A xor B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_xori;
function f_decode_ori (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.lut := "1110"; -- X = A or B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_ori;
function f_decode_andi (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.lut := "1000"; -- X = A and B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_andi;
function f_decode_slli (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.shift.right := '0';
op.arg.shift.sext := '0';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_slli;
function f_decode_srli (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.shift.right := '1';
op.arg.shift.sext := '0';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_srli;
function f_decode_srai (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_itype(x);
begin
op.arg.shift.right := '1';
op.arg.shift.sext := '1';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_srai;
function f_decode_add (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '-';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addl;
op.fast := '1';
return op;
end f_decode_add;
function f_decode_sub (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '0';
op.arg.adder.notb := '1';
op.arg.adder.cin := '1';
op.arg.adder.sign := '-';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addl;
op.fast := '1';
return op;
end f_decode_sub;
function f_decode_slt (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '1'; -- x=(a<b)=(b-a>0)=(b-a-1>=0)=overflow(b-a-1)=overflow(b+!a)
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '1';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_slt;
function f_decode_sltu (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.adder.eq := '0';
op.arg.adder.nota := '1'; -- x=(a<b)=(b-a>0)=(b-a-1>=0)=overflow(b-a-1)=overflow(b+!a)
op.arg.adder.notb := '0';
op.arg.adder.cin := '0';
op.arg.adder.sign := '0';
op.arg.adder.fault := '0';
op.arg.fmode := c_opa_fast_addh;
op.fast := '1';
return op;
end f_decode_sltu;
function f_decode_xor (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.lut := "0110"; -- X = A xor B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_xor;
function f_decode_or (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.lut := "1110"; -- X = A or B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_or;
function f_decode_and (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.lut := "1000"; -- X = A and B
op.arg.fmode := c_opa_fast_lut;
op.fast := '1';
return op;
end f_decode_and;
function f_decode_sll (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.shift.right := '0';
op.arg.shift.sext := '0';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_sll;
function f_decode_srl (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.shift.right := '1';
op.arg.shift.sext := '0';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_srl;
function f_decode_sra (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.shift.right := '1';
op.arg.shift.sext := '1';
op.arg.smode := c_opa_slow_shift;
op.fast := '0';
return op;
end f_decode_sra;
function f_decode_mul (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.mul.sexta := '-';
op.arg.mul.sextb := '-';
op.arg.mul.high := '0';
op.arg.mul.divide := '0';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_mul;
function f_decode_mulh (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.mul.sexta := '1';
op.arg.mul.sextb := '1';
op.arg.mul.high := '1';
op.arg.mul.divide := '0';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_mulh;
function f_decode_mulhsu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.mul.sexta := '1';
op.arg.mul.sextb := '0';
op.arg.mul.high := '1';
op.arg.mul.divide := '0';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_mulhsu;
function f_decode_mulhu(x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.mul.sexta := '0';
op.arg.mul.sextb := '0';
op.arg.mul.high := '1';
op.arg.mul.divide := '0';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_mulhu;
function f_decode_div (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.mul.sexta := '-';
op.arg.mul.sextb := '1';
op.arg.mul.high := '0';
op.arg.mul.divide := '1';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_div;
function f_decode_divu (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.mul.sexta := '-';
op.arg.mul.sextb := '0';
op.arg.mul.high := '0';
op.arg.mul.divide := '1';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_divu;
function f_decode_rem (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.mul.sexta := '1';
op.arg.mul.sextb := '1';
op.arg.mul.high := '1';
op.arg.mul.divide := '1';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_rem;
function f_decode_remu (x : std_logic_vector) return t_opa_op is
variable op : t_opa_op := f_parse_rtype(x);
begin
op.arg.mul.sexta := '0';
op.arg.mul.sextb := '0';
op.arg.mul.high := '1';
op.arg.mul.divide := '1';
op.arg.smode := c_opa_slow_mul;
op.fast := '0';
return op;
end f_decode_remu;
function f_opa_accept_rv32(config : t_opa_config) return std_logic is
begin
assert (config.reg_width = 32) report "RV32 requires 32-bit registers" severity failure;
return '1';
end f_opa_accept_rv32;
function f_opa_decode_rv32(config : t_opa_config; x : std_logic_vector) return t_opa_op is
constant c_opcode : std_logic_vector(6 downto 0) := x( 6 downto 0);
constant c_funct3 : std_logic_vector(2 downto 0) := x(14 downto 12);
constant c_funct7 : std_logic_vector(6 downto 0) := x(31 downto 25);
begin
case c_opcode is
when "0110111" => return f_decode_lui(x);
when "0010111" => return f_decode_auipc(x);
when "1101111" => return f_decode_jal(x);
when "1100111" => --
case c_funct3 is
when "000" => return f_decode_jalr(x);
when others => return c_opa_op_bad;
end case;
when "1100011" => --
case c_funct3 is
when "000" => return f_decode_beq(x);
when "001" => return f_decode_bne(x);
when "100" => return f_decode_blt(x);
when "101" => return f_decode_bge(x);
when "110" => return f_decode_bltu(x);
when "111" => return f_decode_bgeu(x);
when others => return c_opa_op_bad;
end case;
when "0000011" => --
case c_funct3 is
when "000" => return f_decode_lb(x);
when "001" => return f_decode_lh(x);
when "010" => return f_decode_lw(x);
when "100" => return f_decode_lbu(x);
when "101" => return f_decode_lhu(x);
when others => return c_opa_op_bad;
end case;
when "0100011" => --
case c_funct3 is
when "000" => return f_decode_sb(x);
when "001" => return f_decode_sh(x);
when "010" => return f_decode_sw(x);
when others => return c_opa_op_bad;
end case;
when "0010011" => --
case c_funct3 is
when "000" => return f_decode_addi(x);
when "010" => return f_decode_slti(x);
when "011" => return f_decode_sltiu(x);
when "100" => return f_decode_xori(x);
when "110" => return f_decode_ori(x);
when "111" => return f_decode_andi(x);
when "001" => --
case c_funct7 is
when "0000000" => return f_decode_slli(x);
when others => return c_opa_op_bad;
end case;
when "101" => --
case c_funct7 is
when "0000000" => return f_decode_srli(x);
when "0100000" => return f_decode_srai(x);
when others => return c_opa_op_bad;
end case;
when others => return c_opa_op_bad;
end case;
when "0110011" => --
case c_funct7 is
when "0000000" => --
case c_funct3 is
when "000" => return f_decode_add(x);
when "001" => return f_decode_sll(x);
when "010" => return f_decode_slt(x);
when "011" => return f_decode_sltu(x);
when "100" => return f_decode_xor(x);
when "101" => return f_decode_srl(x);
when "110" => return f_decode_or(x);
when "111" => return f_decode_and(x);
when others => return c_opa_op_bad;
end case;
when "0100000" => --
case c_funct3 is
when "000" => return f_decode_sub(x);
when "101" => return f_decode_sra(x);
when others => return c_opa_op_bad;
end case;
when "0000001" => --
case c_funct3 is
when "000" => return f_decode_mul(x);
when "001" => return f_decode_mulh(x);
when "010" => return f_decode_mulhsu(x);
when "011" => return f_decode_mulhu(x);
when "100" => return f_decode_div(x);
when "101" => return f_decode_divu(x);
when "110" => return f_decode_rem(x);
when "111" => return f_decode_remu(x);
when others => return c_opa_op_bad;
end case;
when others => return c_opa_op_bad;
end case;
when others => return c_opa_op_bad;
end case;
end f_opa_decode_rv32;
end opa_riscv_pkg;
| gpl-3.0 | 6fb65b1a9d283fea60b7656aa04108e8 | 0.541243 | 2.804051 | false | false | false | false |
jfdelnero/CPLD_USBHxCFloppyEmulator | rtl/vhdl/ControlCore.vhd | 1 | 20,655 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------H----H--X----X-----CCCCC----22222----0000-----0000------11----------
----------H----H----X-X-----C--------------2---0----0---0----0--1--1-----------
---------HHHHHH-----X------C----------22222---0----0---0----0-----1------------
--------H----H----X--X----C----------2-------0----0---0----0-----1-------------
-------H----H---X-----X---CCCCC-----222222----0000-----0000----1111------------
-------------------------------------------------------------------------------
----------------------------------------- http://jeanfrancoisdelnero.free.fr --
--============================================================================-
-- HxCFloppyEmu
-- Floppy drive emulator Project
--
-- http://jeanfrancoisdelnero.free.fr
-- HxC2001 - 2006 - 2008
--
-- Design units :
--
-- File name : ControlCore.vhd
--
-- Purpose : Main part of the floppy emulator : Core State machine
--
--
-- Dependencies : IEEE.Std_Logic_1164
-- IEEE.STD_LOGIC_arith
--
--============================================================================-
-- --
-- Copyright (C) 2006, 2007, 2008 Jean-François DEL NERO --
-- --
-- This file is part of HxCFloppyEmulator. --
-- --
-- HxCFloppyEmulator may be used and distributed without restriction provided--
-- that this copyright statement is not removed from the file and that any --
-- derivative work contains the original copyright notice and the associated --
-- disclaimer. --
-- --
-- HxCFloppyEmulator is free software; you can redistribute it --
-- and/or modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 2 --
-- of the License, or (at your option) any later version. --
-- --
-- HxCFloppyEmulator is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. --
-- See the GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with HxCFloppyEmulator; if not, write to the Free Software --
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA--
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 Jean-François DEL NERO 23 march 2008 Major update:
--
-- MFM/FM output generator (HeadShifter) rewritten.
-- It can now do any bitrate between
-- 63kbit/s and 1Mbit/s with a 62.5ns step.
-- The emulator can now handle bitrate-protected floppies ;-)
--
-- The SRAM is now used like a ring buffer (1 buffer of 8KB).
--
-- The master state machine run now at 16Mhz
-- to allow fast opcode execution / mfm loading.
--
-- "Validate Track" opcode removed (same functionnality in "SENDTRACKCODE opcode".
-- "SETINDEX" opcode modified:
-- "SENDTRACKCODE" added (2 byte : 0x3 <track number>)
-- "SETBITRATE" opcode added (2 bytes: 0xD <period value>)
-- "NOP" opcode added (2 bytes : 0x7 XX)
-- "Disk Changed" and "Ready" signals
-- are now software driven
--
-- Track position register is now 8 bits.
--
-- SRAM_CS_not is now driven (for the SRAM standby mode)
--
-- 0.5 Jean-François DEL NERO 19 November 2006 Jumper-free drive select added
-- jeanfrancoisdelnero < > free.fr
-- 0.4 Jean-François DEL NERO 11 November 2006 500kbits/s support added
-- 2*1Ko and 2*2Ko buffer size available
-- Write protect signal added
-- Shugart and IBM PC mode available
-- 0.2 Jean-François DEL NERO 16 September 2006 MFM Pulse Generator rewritten
-- 0.1 Jean-François DEL NERO 25 June 2006 First public version
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- package ControlCore
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
entity ControlCore is
port (
-- FTDI chip if
FTDI_DATA: inout std_logic_vector(7 downto 0);
FTDI_RD_not: out std_logic;
FTDI_WR: out std_logic;
FTDI_TXE_not: in std_logic;
FTDI_RXF_not: in std_logic;
-- SRAM IF
SRAM_DATA: inout std_logic_vector(7 downto 0);
SRAM_ADR: out std_logic_vector(14 downto 0);
SRAM_RD_not: out std_logic;
SRAM_WR_not: out std_logic;
SRAM_CS_not: out std_logic;
-- Track position
Head_Position: in std_logic_vector(6 downto 0);
Clear_Head_Position: out std_logic;
Head_moved : in std_logic;
Ack_head_move : out std_logic;
-- Floppy IF
FLOPPY_READYSIGNAL: out std_logic;
FLOPPY_SIDE: in std_logic;
FLOPPY_DSKCHG : out std_logic;
FLOPPY_INDEX: out std_logic;
FLOPPY_WPT: out std_logic;
FLOPPY_SEL0: in std_logic;
FLOPPY_SEL1: in std_logic;
FLOPPY_SEL2: in std_logic;
FLOPPY_SEL3: in std_logic;
FLOPPY_SELECT: out std_logic;
FLOPPY_DATA: out std_logic;
Step_LED: out std_logic;
-- Clock and reset
clock: in std_logic;
reset_not: in std_logic
);
end ControlCore;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture arch of ControlCore is
constant ADDRESSBUSWITDH: natural:=13;
------------------------------------------------------
-- FM/MFM data shifter
--
component HeadShifter
port (
-- input // data bus
DATABUS: in std_logic_vector(3 downto 0);
SPEEDCONFIG: in std_logic_vector(7 downto 0);
DATALOADED: out std_logic;
FLOPPY_DATA: out std_logic; -- FM/MFM data line
clock: in std_logic; -- Clock the shifter
reset_not: in std_logic
);
end component;
------------------------------------------------------
-- Opcode / data latch
--
component Latch4 is
port (
D: in std_logic_vector(3 DOWNTO 0); -- Data in
Q: out std_logic_vector(3 DOWNTO 0);-- Data out
wr: in std_logic; --Store command
clock: in std_logic;
reset_not: in std_logic
);
end component;
---------------------------------------------------------------------------------
type master_state_machine_type is
(
IDLE,
SPRELOADS0,SPRELOADS1,SPRELOADS2, SPRELOADS3,SPRELOADS4,SPRELOADS5,
SENDTRACKNUMBER0,SENDTRACKNUMBER1,SENDTRACKNUMBER2,
WRITES0,WRITES1,WRITES2,WRITES3,WRITES4,WRITES5
);
signal master_fsm: master_state_machine_type ;
---------------------------------
signal preload : std_logic_vector(3 downto 0);
signal preloaded : std_logic_vector(3 downto 0);
signal pload : std_logic;
---------------------------------
signal write_adr: std_logic_vector(ADDRESSBUSWITDH-1 downto 0); -- write address
signal read_adr: std_logic_vector(ADDRESSBUSWITDH-1 downto 0); -- read address
signal SRAM_busdir: std_logic; -- sram bus state 1:write 0:read
------------------------------------------------------------------
signal ftdibusdir: std_logic; -- ftdi bus state 1:write 0:read
signal FLOPPY_SEL: std_logic;
signal FLOPPY_SELreg: std_logic_vector(1 downto 0);
signal FLOPPY_SELdisable: std_logic;
signal index_signal: std_logic;
signal writeprotect_signal: std_logic;
signal diskchanged_signal: std_logic;
signal ready_signal: std_logic;
signal mfm_speed_config : std_logic_vector(7 downto 0);
signal rxfstate : std_logic;
signal FLOPPY_DATA_shifter : std_logic;
signal FLOPPY_DATA_MASK : std_logic;
signal amigareadymode : std_logic;
signal shiftertoggle : std_logic;
signal loadtoggle: std_logic;
signal FTDI_RXF_not_synced: std_logic;
signal increadadr: std_logic;
signal incwriteadr: std_logic;
signal FLOPPY_SIDE_synced: std_logic;
begin
HDC: HeadShifter port map(preloaded,mfm_speed_config,shiftertoggle,FLOPPY_DATA_shifter,clock,reset_not);
PL : Latch4 port map(preload,preloaded,pload,clock,reset_not);
Clear_Head_Position<=FLOPPY_SELdisable;
---------------------------------------------------------------------------------------
-- Floppy signals process
--
floppyif : process(Head_moved,FLOPPY_DATA_shifter,FLOPPY_SEL,index_signal,writeprotect_signal,diskchanged_signal,amigareadymode,ready_signal)
begin
if(Head_moved='0')
then
step_led<='0';
FLOPPY_DATA<= FLOPPY_DATA_shifter and FLOPPY_SEL;
else
step_led<='1';
FLOPPY_DATA<='0';
end if;
FLOPPY_SELECT<=FLOPPY_SEL;
FLOPPY_INDEX<= index_signal and FLOPPY_SEL;
FLOPPY_WPT <= writeprotect_signal and FLOPPY_SEL;
FLOPPY_DSKCHG<= diskchanged_signal and FLOPPY_SEL;
if(amigareadymode='0')
then
FLOPPY_READYSIGNAL<=ready_signal and FLOPPY_SEL;
else
if(Head_moved='0')
then
FLOPPY_READYSIGNAL<=ready_signal and FLOPPY_SEL;
else
FLOPPY_READYSIGNAL<='0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Select signals decoder
selectproc : process(reset_not,FLOPPY_SELdisable,FLOPPY_SELreg,FLOPPY_SEL0,FLOPPY_SEL1,FLOPPY_SEL2,FLOPPY_SEL3)
begin
if (FLOPPY_SELdisable='0')
then
case FLOPPY_SELreg is
when "00" =>
FLOPPY_SEL<=FLOPPY_SEL0;
when "01" =>
FLOPPY_SEL<=FLOPPY_SEL1;
when "10" =>
FLOPPY_SEL<=FLOPPY_SEL2;
when "11" =>
FLOPPY_SEL<=FLOPPY_SEL3;
end case;
else
FLOPPY_SEL<='0';
end if;
end process;
--------------------------------------------------------------------------
--SRAM access mux
srammux : process(FTDI_DATA,SRAM_busdir,read_adr,write_adr,reset_not)
begin
SRAM_ADR<=(others=>'0');
if(SRAM_busdir='1')
then
-- FTDI -> SRAM
SRAM_ADR(ADDRESSBUSWITDH-1 downto 0)<=write_adr(ADDRESSBUSWITDH-1 downto 0);
SRAM_DATA<= FTDI_DATA;
else
-- SRAM -> shifter/opcode register
SRAM_ADR(ADDRESSBUSWITDH-1 downto 0)<=read_adr(ADDRESSBUSWITDH-1 downto 0);
SRAM_DATA<=(others=>'Z');
end if;
end process;
--------------------------------------------------------------------------
-- Send track number Circuit
readtrackpos : process(Head_moved,ftdibusdir,Head_Position,FLOPPY_SEL)
begin
if( ftdibusdir='1')
then
-- Head position -> FTDI chip
FTDI_DATA<=Head_moved & Head_Position(6 downto 0);
else
-- FTDI chip -> CPLD
FTDI_DATA<=(others=>'Z');
end if;
end process;
--------------------------------------------------------------------------
--data bus Mux (side)
sidemux : process(FLOPPY_SIDE_synced,SRAM_DATA)
begin
if(FLOPPY_SIDE_synced='1')
then
-- Side 1
preload<=SRAM_DATA(3 downto 0);
else
-- Side 0
preload<=SRAM_DATA(7 downto 4);
end if;
end process;
--------------------------------------------------------------------------
-- read & write address incrementer (ring buffer)
process (clock, reset_not)
begin
if(reset_not='0')
then
write_adr<=(others=>'0');
read_adr<=(others=>'0');
elsif (clock'event and clock = '1')
then
if(incwriteadr='1')
then
write_adr<=write_adr + conv_std_logic_vector(1, ADDRESSBUSWITDH);
end if;
if(increadadr='1')
then
read_adr<=read_adr + conv_std_logic_vector(1, ADDRESSBUSWITDH);
end if;
end if;
end process;
------------------------------------------------------------------
------------------------------------------------------------------
-- Master State Machine
------------------------------------------------------------------
------------------------------------------------------------------
process (clock,reset_not)
begin
if (reset_not = '0')
then
master_fsm <= IDLE;
loadtoggle<='0';
mfm_speed_config<="01000000";
FLOPPY_SELdisable<='1';
elsif (clock'event and clock = '1')
then
FTDI_RXF_not_synced<=FTDI_RXF_not;
-- a step append > We need to "hide" the actual datas
Ack_head_move<='0';
-- default values
SRAM_busdir<='0';
SRAM_RD_not<='1';
SRAM_WR_not<='1';
SRAM_CS_not<='0';
FTDI_RD_not<='1';
FTDI_WR<='0';
pload<='0';
ftdibusdir<='0';
increadadr<='0';
incwriteadr<='0';
case master_fsm is
----------------------------------------------------------------
-- Idle state : wait for a shifter event or USB data.
--
when IDLE =>
if (loadtoggle/=shiftertoggle)
then
-- first priority -> load the shifter
FLOPPY_SIDE_synced<=FLOPPY_SIDE;
master_fsm <= SPRELOADS0;
else
if(FTDI_RXF_not_synced='0')
then
-- second priority -> write usb data to the sram
master_fsm <= WRITES0;
else
-- stay in idle state
SRAM_CS_not<='1';
master_fsm <= IDLE;
end if;
end if;
----------------------------------------------------------------
-- Preload data/opcode from sram
--
--
when SPRELOADS0 =>
SRAM_RD_not<='0'; --read data from sram
master_fsm <= SPRELOADS1;
when SPRELOADS1 =>
SRAM_RD_not<='0';
pload<='1'; -- store data in the latch (next cycle)
increadadr<='1'; -- increment the read address (next cycle)
master_fsm <= SPRELOADS2;
when SPRELOADS2 =>
SRAM_RD_not<='1';
master_fsm <= SPRELOADS3;
when SPRELOADS3 =>
SRAM_RD_not<='0'; -- read data from sram
master_fsm <= SPRELOADS4;
when SPRELOADS4 =>
SRAM_RD_not<='0'; -- read data from sram
master_fsm <= SPRELOADS5;
when SPRELOADS5 =>
-- decode the opcode
case preloaded is
when "1100" => --SETINDEX opcode
index_signal<= SRAM_DATA(0); -- change index state
ready_signal<= SRAM_DATA(1);
diskchanged_signal<= SRAM_DATA(2);
writeprotect_signal<= SRAM_DATA(3);
amigareadymode<= SRAM_DATA(4);
FLOPPY_SELdisable<= SRAM_DATA(5);
FLOPPY_SELreg(0)<= SRAM_DATA(6);
FLOPPY_SELreg(1)<= SRAM_DATA(7);
increadadr<='1';
master_fsm <= IDLE;
when "1101" => --SETBITRATE opcode
mfm_speed_config<=SRAM_DATA(7 downto 0);
increadadr<='1';
master_fsm <= IDLE;
when "0011" => --SENDTRACKCODE opcode
if(FTDI_TXE_not='0')
then
SRAM_RD_not<='0'; -- read data from sram
master_fsm <= SENDTRACKNUMBER0;
else
master_fsm <= IDLE;
increadadr<='1';
end if;
when "0111" => --NOP opcode
increadadr<='1';
master_fsm <= IDLE;
when others => -- it's not an opcode -> data already loaded.
loadtoggle<=shiftertoggle;
master_fsm <= IDLE;
end case;
----------------------------------------------------------------
-- Send track position to the PC.
--
-- |T11___T12_
-- TXE# _________________/ \____
-- ___T7____ T8 ___
-- WR ____/ \___________/
-- | T9 | T10|
-- D -------T3< D >----------
--
--
-- T7 - WR Active Pulse Width (min 50ns)
-- T8 - WR to RD Pre-Charge Time (min 50ns)
-- T9 - Data Setup Time before WR Inactive (min 20ns)
-- T10 - Data Hold Time from WR Inactive (min 0ns)
-- T11 - WR Inactive to TXE# (min 5ns max 25ns)
-- T12 - TXE Inactive After WR Cycle (min 80ns)
when SENDTRACKNUMBER0 =>
FTDI_WR<='1';
ftdibusdir<='1'; -- put the track position on the ftdi bus
SRAM_RD_not<='0'; -- read data from sram
master_fsm <= SENDTRACKNUMBER1;
when SENDTRACKNUMBER1 =>
FTDI_WR<='1'; --add some delay...
SRAM_RD_not<='0'; -- read data from sram
ftdibusdir<='1';
master_fsm <= SENDTRACKNUMBER2;
when SENDTRACKNUMBER2 =>
ftdibusdir<='1'; -- write to the usb fifo
if(Head_Position(6 downto 0)=SRAM_DATA(6 downto 0))
then
Ack_head_move<='1';
end if;
increadadr<='1';
master_fsm <= IDLE;
----------------------------------------------------------------
-- store data from the USB FIFO FT245 to the sram
--
-- ______ ____
-- RXF# \_______________/ \____
-- _______ T5_______
-- RD# \____T1_____/ \___
--
-- D -------T3< D >-------------
--
--
-- T1 - RD Active Pulse Width (min 50ns)
-- T2 - RD to RD Pre-Charge Time (min 50ns +T6)
-- T3 - RD Active to Valid Data (max 50ns)
-- T4 - Valid Data Hold Time from RD Inactive (min 0 ns)
-- T5 - RD Inactive to RXF# (max 25ns)
-- T6 - RXF Inactive After RD Cycle (min 80ns)
--
when WRITES0 =>
SRAM_busdir<='1'; -- sram bus in write mode
FTDI_RD_not<='0';-- read from ftdi chip
master_fsm <= WRITES1;
when WRITES1 =>
SRAM_busdir<='1';
SRAM_WR_not<='0'; -- write to sram
FTDI_RD_not<='0';-- read from ftdi chip
master_fsm <= WRITES2;
when WRITES2 =>
SRAM_busdir<='1'; -- sram bus in write mode
SRAM_WR_not<='0'; -- write to sram
FTDI_RD_not<='0'; -- read from ftdi chip
master_fsm <= WRITES3;
when WRITES3 =>
SRAM_busdir<='1'; -- sram bus in write mode
incwriteadr<='1'; -- increment the write address
master_fsm <= WRITES4;
when WRITES4 => --add 62.5ns delay...
master_fsm <= WRITES5;
when WRITES5 => --add 62.5ns delay...
master_fsm <= IDLE;
when others => master_fsm <= IDLE;
end case;
end if;
end process;
END arch;
| gpl-3.0 | 40e8738d759a2450144ba759ca82615b | 0.453207 | 3.870152 | false | false | false | false |
imr/Mandelbrot-VHDL | src/Mandelbrot.vhd | 1 | 1,444 | -- Ian Roth
-- ECE 8455
-- Mandelbrot Calculation, final project
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
USE work.fixed_pkg.all;
ENTITY Mandelbrot IS
PORT(
x_const, y_const :IN sfixed(3 downto -32);
x_in, y_in :IN sfixed(3 downto -32);
iteration_in :IN unsigned(15 downto 0);
done_in, clk, rst :IN STD_LOGIC;
x_const_out, y_const_out :OUT sfixed(3 downto -32);
x_out, y_out :OUT sfixed(3 downto -32);
iteration_out :OUT unsigned(15 downto 0);
done_out :OUT STD_LOGIC
);
END ENTITY Mandelbrot;
ARCHITECTURE Behavior of Mandelbrot IS
CONSTANT limit :sfixed(3 downto 0) := X"2";
SIGNAL x_sqr, y_sqr :sfixed(3 downto -32);
BEGIN
x_sqr <= resize(x_in * x_in, x_sqr);
y_sqr <= resize(y_in * y_in, y_sqr);
Process(clk,rst)
BEGIN
IF (clk'EVENT and clk = '1') THEN
IF (rst = '1') THEN
iteration_out <= X"0000";
done_out <= '0';
ELSE
x_out <= resize(x_sqr - y_sqr + x_const, x_sqr);
y_out <= resize(((x_in * y_in) sll 1) + y_const, y_sqr);
x_const_out <= x_const;
y_const_out <= y_const;
IF (done_in = '1') THEN
done_out <= '1';
iteration_out <= iteration_in;
ELSE
IF (resize(x_sqr + y_sqr, x_sqr) > limit) THEN
done_out <= '1';
iteration_out <= iteration_in;
ELSE
done_out <= '0';
iteration_out <= iteration_in + 1;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END Behavior; | bsd-3-clause | a21dc8b13fd164e838199c2cd6a7aaf0 | 0.605263 | 2.560284 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/integration_task/integrazione_task.vhd | 1 | 7,916 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: Scognamiglio, Riccio, Sorrentino
--
-- Create Date: 17.07.2017 16:04:17
-- Design Name:
-- Module Name: integrazione_task - Structural
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity integrazione_task is
Generic ( campione : natural := 20460;
doppler : natural := 11;
satellite : natural := 10);
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
poff_pinc : in STD_LOGIC_VECTOR (47 downto 0);
dds_out : out STD_LOGIC_VECTOR (31 downto 0); --SI PUO' TOGLIERE
dds_done : out STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC;
fft1_in : in STD_LOGIC_VECTOR(31 downto 0);
fft1_ready_out : out STD_LOGIC;
fft1_valid_in : in STD_LOGIC;
ifft_out : out STD_LOGIC_VECTOR (31 downto 0); --SI PUO' TOGLIERE
fft1_out : out STD_LOGIC_VECTOR (31 downto 0); --SI PUO' TOGLIERE
fft2_out : out STD_LOGIC_VECTOR (31 downto 0); --SI PUO' TOGLIERE
pos_campione : out STD_LOGIC_VECTOR (natural(ceil(log2(real(campione))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR (natural(ceil(log2(real(doppler))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR (natural(ceil(log2(real(satellite))))-1 downto 0);
sample_max : out STD_LOGIC_VECTOR (31 downto 0);
max : out STD_LOGIC_VECTOR (31 downto 0));
end integrazione_task;
architecture Structural of integrazione_task is
component test_dds_wrapper is
generic ( campioni : natural := 20460 ); --! Numero di campioni da generare
port (
clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
poff_pinc : in STD_LOGIC_VECTOR(47 downto 0); --! Spiazzamenti di fase e di frequenza (poff + pinc)
valid_in : in STD_LOGIC; --! Indica che il dato sulla linea di ingresso è valido
ready_in : in STD_LOGIC; --! Indica che il componente a valle è pronto ad accettare valori in ingresso
valid_out : out STD_LOGIC; --! Indica che il dato sulla linea di uscita è valido
ready_out : out STD_LOGIC; --! Indica che questo componente è pronto ad accettare valori in ingresso
sine_cosine : out STD_LOGIC_VECTOR(31 downto 0); --! Campioni complessi del segnale periodico (immaginaria + reale)
done : out STD_LOGIC --! Segnale di terminazione delle operazioni
);
end component test_dds_wrapper;
component design_1_wrapper is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
ifft_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
ifft_tready : in STD_LOGIC;
ifft_tvalid : out STD_LOGIC;
mul_out : out STD_LOGIC_VECTOR ( 79 downto 0 );
sgn_1_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
sgn_1_tready : out STD_LOGIC;
sgn_1_tvalid : in STD_LOGIC;
sgn_2_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
sgn_2_tready : out STD_LOGIC;
sgn_2_tvalid : in STD_LOGIC;
sig_1_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
sig_2_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_1_wrapper;
component complex_max is
Generic ( sample_width : natural := 32; --! Parallelismo in bit del del campione
s : natural := 5; --! Numero di satelliti
d : natural := 4; --! Numero di intervalli doppler
c : natural := 5 ); --! Numero di campioni per intervallo doppler
Port ( clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
valid_in : in STD_LOGIC; --! Indica che il dato sulla linea di ingresso è valido
ready_in : in STD_LOGIC; --! Indica che il componente a valle è pronto ad accettare valori in ingresso
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Valore complesso del campione associato al modulo
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Valore complesso del massimo
max : out STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Modulo del campione massimo
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0); --! Posizione del massimo nell'intervallo doppler
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0); --! Intervallo di frequenze doppler al quale appartiene il massimo
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0); --! Satellite associato al massimo
valid_out : out STD_LOGIC; --! Indica che il dato sulla linea di uscita è valido
ready_out : out STD_LOGIC); --! Indica che questo componente è pronto ad accettare valori in ingresso
end component complex_max;
--!Signal
signal ready_out_fft2, valid_in_fft2, valid_out_ifft, ready_out_complex_max : STD_LOGIC := '0';
signal fft2_in : STD_LOGIC_VECTOR(31 downto 0);
signal ifft_out_sig : STD_LOGIC_VECTOR(31 downto 0);
begin
--Collegamenti che andranno eliminati
ifft_out <= ifft_out_sig;
dds_out <= fft2_in;
dds_inst: test_dds_wrapper
generic map ( campioni => campione )
port map ( clock => clock,
reset_n => reset_n,
poff_pinc => poff_pinc,
valid_in => valid_in,
ready_in => ready_out_fft2,
valid_out => valid_in_fft2,
ready_out => ready_out,
sine_cosine => fft2_in,
done => dds_done);
task1_inst: design_1_wrapper
port map ( aclk => clock,
aclken => '1',
aresetn => reset_n,
ifft_out => ifft_out_sig,
ifft_tready => ready_out_complex_max,
ifft_tvalid => valid_out_ifft,
mul_out => open,
sgn_1_in => fft1_in,
sgn_1_tready => fft1_ready_out,
sgn_1_tvalid => fft1_valid_in,
sgn_2_in => fft2_in,
sgn_2_tready => ready_out_fft2,
sgn_2_tvalid => valid_in_fft2,
sig_1_out => fft1_out, --SI PUO' METTERE OPEN
sig_2_out => fft2_out); --SI PUO' METTERE OPEN
complex_max_inst: complex_max
generic map ( sample_width => 32,
s => satellite,
d => doppler,
c => campione)
port map ( clock => clock,
reset_n => reset_n,
valid_in => valid_out_ifft,
ready_in => ready_in,
sample => ifft_out_sig,
sample_max => sample_max,
max => max,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
valid_out => valid_out,
ready_out => ready_out_complex_max);
end Structural;
| gpl-2.0 | cca1bd133fbe1816a47ecf5315b0dc39 | 0.574102 | 3.592912 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/RBCP_Receiver.vhd | 1 | 1,735 | --------------------------------------------------------------------------------
--! @file RBCP_Receiver.vhd
--! @brief convert RBCP signal to SRAM write signal
--! @author Takehiro Shiozaki
--! @date 2013-11-01
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RBCP_Receiver is
generic(
G_ADDR : std_logic_vector(31 downto 0);
G_LEN : integer;
G_ADDR_WIDTH : integer
);
port(
CLK : in std_logic;
RESET : in std_logic;
-- RBCP interface
RBCP_ACT : in std_logic;
RBCP_ADDR : in std_logic_vector(31 downto 0);
RBCP_WE : in std_logic;
RBCP_WD : in std_logic_vector(7 downto 0);
RBCP_ACK : out std_logic;
-- output
ADDR : out std_logic_vector(G_ADDR_WIDTH - 1 downto 0);
WE : out std_logic;
WD : out std_logic_vector(7 downto 0)
);
end RBCP_Receiver;
architecture RTL of RBCP_Receiver is
signal int_WE : std_logic;
signal DelayedWe : std_logic_vector(1 downto 0);
begin
WD <= RBCP_WD;
int_WE <= '1' when(RBCP_ACT = '1' and RBCP_WE = '1' and
G_ADDR <= RBCP_ADDR and RBCP_ADDR <= G_ADDR + G_LEN - 1) else
'0';
WE <= int_WE;
process(CLK, RESET)
begin
if(RESET = '1') then
DelayedWe <= (others => '0');
elsif(CLK'event and CLK = '1') then
DelayedWe(0) <= int_WE;
DelayedWe(1) <= DelayedWe(0);
end if;
end process;
RBCP_ACK <= DelayedWe(1);
ADDR <= conv_std_logic_vector(conv_integer(RBCP_ADDR - G_ADDR), G_ADDR_WIDTH);
end RTL;
| mit | 359af3e314918a4d52208a83234ae80d | 0.515274 | 3.330134 | false | false | false | false |
Xion345/fpga-projects | projects/vga-tiled-framebuffer/vga_tiled_framebuffer_top.vhd | 1 | 3,589 | -- VGA controller with tiled frambuffer
-- Video mode: 640x480 60Hz 8 bit pixel depth
-- Tiles: 8x16 - 256 Tiles
-- UART: 115200 bauds - 8 bits - No parity
library ieee;
use ieee.std_logic_1164.all;
entity vga_tiled_framebuffer_top is
port(clk, reset: in std_logic;
-- UART
rx: in std_logic;
tx: out std_logic;
-- VGA
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(2 downto 1);
hsync: out std_logic;
vsync: out std_logic
);
end vga_tiled_framebuffer_top;
architecture vga_tiled_framebuffer_top_arch of vga_tiled_framebuffer_top is
constant ADDR_BYTES: integer := 2;
-- VGA Sync.
signal pixel_tick: std_logic;
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal video_on: std_logic;
-- VGA Tiling system
signal addr_index: std_logic_vector(13 downto 0);
signal data_in_index: std_logic_vector(7 downto 0);
signal data_out_index: std_logic_vector(7 downto 0);
signal wr_index: std_logic;
--
signal addr_tiles: std_logic_vector(14 downto 0);
signal data_in_tiles: std_logic_vector(7 downto 0);
signal data_out_tiles: std_logic_vector(7 downto 0);
signal wr_tiles: std_logic;
-- DMA
signal dma_addr: std_logic_vector(15 downto 0);
signal dma_data_in: std_logic_vector(7 downto 0);
signal dma_data_out: std_logic_vector(7 downto 0);
signal dma_wr: std_logic;
-- UART
signal rx_done_tick: std_logic;
signal tx_done_tick: std_logic;
signal data_rx: std_logic_vector(7 downto 0);
signal data_tx: std_logic_vector(7 downto 0);
signal tx_start_tick: std_logic;
begin
-- VGA Synchronization
vga_sync: entity work.vga_sync
port map(clk => clk, reset => reset,
pixel_tick => pixel_tick,
x => pixel_x, y => pixel_y,
hsync => hsync, vsync => vsync, video_on => video_on);
-- VGA Tiled Framebuffer
vga_tiling: entity work.vga_tiling_8x16
port map(
clk => clk, reset => reset,
pixel_tick => pixel_tick, video_on => video_on,
pixel_x => pixel_x, pixel_y => pixel_y,
--
addr_index => addr_index,
data_in_index => data_in_index,
data_out_index => data_out_index,
wr_index => wr_index,
--
addr_tiles => addr_tiles,
data_in_tiles => data_in_tiles,
data_out_tiles => data_out_tiles,
wr_tiles => wr_tiles,
-- Output
pixel_value(7 downto 5) => red,
pixel_value(4 downto 2) => green,
pixel_value(1 downto 0) => blue
);
-- DMA
dma: entity work.uart_dma
generic map(
RAM_READ_TICKS => 1, ADDR_BYTES => 2)
port map(
clk => clk, reset => reset,
rx_done_tick => rx_done_tick,
tx_done_tick => tx_done_tick,
data_rx => data_rx,
data_tx => data_tx,
tx_start_tick => tx_start_tick,
--
data_ram_rd => dma_data_in,
data_ram_wr => dma_data_out,
addr(22 downto 16) => open,
addr(15 downto 0) => dma_addr,
wr => dma_wr
);
-- Memory multiplexing (on shared bus)
-- Multiplex on 16th byte address (dma_addr(15))
addr_index <= dma_addr(13 downto 0);
addr_tiles <= dma_addr(14 downto 0);
data_in_tiles <= dma_data_out;
data_in_index <= dma_data_out;
dma_data_in <= data_out_tiles when dma_addr(15) = '0' else data_out_index;
wr_tiles <= dma_wr when dma_addr(15) = '0' else '0';
wr_index <= dma_wr when dma_addr(15) = '1' else '0';
-- UART
uart_rxtx: entity work.uart_rxtx_clock
port map(
clk => clk, reset => reset,
rx => rx, tx => tx,
data_rx => data_rx, data_tx => data_tx,
rx_done_tick => rx_done_tick, tx_done_tick => tx_done_tick,
tx_start => tx_start_tick
);
end vga_tiled_framebuffer_top_arch;
| mit | 93374cc65446fa0f73ee0fbcc2fdeb6d | 0.643076 | 2.712774 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/moltiplicatore_booth/parte_operativa.vhd | 1 | 3,593 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:59:58 11/21/2015
-- Design Name:
-- Module Name: parte_operativa - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- Prodotto m*n
entity parte_operativa is
generic ( n : natural := 4;
m : natural := 4);
Port ( X : in STD_LOGIC_VECTOR (n-1 downto 0);
Y : in STD_LOGIC_VECTOR (m-1 downto 0);
load_a : in STD_LOGIC;
load_q : in STD_LOGIC;
load_m : in STD_LOGIC;
reset_n : in STD_LOGIC;
shift : in STD_LOGIC;
sub : in STD_LOGIC;
clock : in STD_LOGIC;
q0 : out STD_LOGIC;
q_1 : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (n+m-1 downto 0)
);
end parte_operativa;
architecture Structural of parte_operativa is
COMPONENT register_n_bit
generic (n : natural := 8;
delay : time := 0 ns);
Port ( I : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (n-1 downto 0));
END COMPONENT;
COMPONENT add_sub
generic ( n : natural := 4);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
subtract : in STD_LOGIC;
ovfl : out STD_LOGIC;
S : out STD_LOGIC_VECTOR (n-1 downto 0));
END COMPONENT;
COMPONENT shift_register_n_bit
generic (n : natural := 8;
delay : time := 0 ns);
Port (D_IN : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
load : in STD_LOGIC;
shift : in STD_LOGIC;
lt_rt : in STD_LOGIC;
sh_in : in STD_LOGIC;
sh_out : out STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (n-1 downto 0));
END COMPONENT;
signal ingresso_a, uscita_a, moltiplicando : std_logic_vector(n-1 downto 0) := (others => '0');
signal uscita_q : std_logic_vector(m-1 downto 0) := (others => '0');
signal q_1_sig, sh_out_a_q : std_logic := '0';
alias AI is ingresso_a;
alias AU is uscita_a;
alias QU is uscita_q;
alias QU0 is uscita_q(0);
alias QU_1 is q_1_sig;
begin
P <= (AU & QU);
q0 <= QU0;
q_1 <= QU_1;
registro_moltiplicando : register_n_bit
generic map(n)
PORT MAP(I => X, clock => clock, load => load_m, reset_n => reset_n,
O => moltiplicando);
a : shift_register_n_bit
generic map(n)
PORT MAP(D_IN => AI, clock => clock, reset_n => reset_n, load => load_a, shift => shift,
lt_rt => '1', sh_in => uscita_a(n-1), sh_out => sh_out_a_q , D_OUT => AU);
q : shift_register_n_bit
generic map(m)
PORT MAP(D_IN=> Y, clock => clock, reset_n => reset_n, load => load_q, shift => shift,
lt_rt => '1', sh_in => sh_out_a_q, sh_out => q_1_sig, D_OUT => QU);
adder_subtracter : add_sub
generic map(n)
PORT MAP(A => AU, B => moltiplicando, subtract => sub, ovfl => open, S => AI);
end Structural;
| gpl-2.0 | eb610b0e1fc4609ff8603fc163afe675 | 0.55469 | 3.102763 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/moltiplicatore_booth/moltiplicatore_booth.vhd | 1 | 4,209 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:39:58 11/23/2015
-- Design Name:
-- Module Name: moltiplicatore_booth - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- Moltilplicando A, moltplicatore B
entity moltiplicatore_booth is
generic ( n : natural := 4;
m : natural := 4);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (m-1 downto 0);
enable : in STD_LOGIC;
reset_n : in STD_LOGIC;
clock : in STD_LOGIC;
done : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (n+m-1 downto 0));
end moltiplicatore_booth;
architecture Structural of moltiplicatore_booth is
COMPONENT parte_controllo
generic ( n : natural := 4;
m : natural := 4);
PORT(
clock : in STD_LOGIC;
reset_n_all : in STD_LOGIC;
q0 : in STD_LOGIC;
q_1 : in STD_LOGIC;
enable : in STD_LOGIC;
conteggio : in STD_LOGIC;
load_a : out STD_LOGIC;
load_m : out STD_LOGIC;
load_q : out STD_LOGIC;
reset_n : out STD_LOGIC;
shift : out STD_LOGIC;
sub : out STD_LOGIC;
count_en : out STD_LOGIC;
done : out STD_LOGIC);
END COMPONENT;
COMPONENT parte_operativa
generic ( n : natural := 4;
m : natural := 4);
PORT(
X : in STD_LOGIC_VECTOR (n-1 downto 0);
Y : in STD_LOGIC_VECTOR (m-1 downto 0);
load_a : in STD_LOGIC;
load_q : in STD_LOGIC;
load_m : in STD_LOGIC;
reset_n : in STD_LOGIC;
shift : in STD_LOGIC;
sub : in STD_LOGIC;
clock : in STD_LOGIC;
q0 : out STD_LOGIC;
q_1 : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (n+m-1 downto 0)
);
END COMPONENT;
COMPONENT contatore_modulo_n
generic (n : natural := 4);
PORT ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
count_en : in STD_LOGIC;
up_down : in STD_LOGIC;
mod_n : out STD_LOGIC);
END COMPONENT;
signal reset_n_sig, q0_sig, load_a_sig, load_q_sig, load_m_sig, q_1_sig,
shift_sig, sub_sig, cnt_en_sig, mod_n_sig, done_sig : std_logic := '0';
signal p_sig : std_logic_vector(n+m-1 downto 0);
signal sign : std_logic := '0';
begin
-- L'assegnazione condizionata viene utilizzata per risolvere il problema del segno dello zero (la prima)
-- e della moltiplicazione per il massimo numero rappresentabile con n bit quando questo è il moltiplicatore
-- (seconda riga: risolto complementando a 2 il risultato) es. 1*(-8),
sign <= '0' when (A = (A'range => '0')) or (B = (B'range => '0')) else
(A(n-1) xor B(m-1));
P <= ((not p_sig) + 1) and (p_sig'range => done_sig) when ((A(n-1) = '1') and (unsigned(A(n-2 downto 0)) = 0)) else
(sign & p_sig(n+m-2 downto 0)) and (p_sig'range => done_sig);
done <= done_sig;
PC: parte_controllo
generic map(n,m)
PORT MAP(
clock => clock,
reset_n_all => reset_n,
q0 => q0_sig,
q_1 => q_1_sig,
enable => enable,
conteggio => mod_n_sig,
load_a => load_a_sig,
load_m => load_m_sig,
load_q => load_q_sig,
reset_n => reset_n_sig,
shift => shift_sig,
sub => sub_sig,
count_en => cnt_en_sig,
done => done_sig
);
PO: parte_operativa
generic map(n,m)
PORT MAP(
X => A,
Y => B,
sub => sub_sig,
load_a => load_a_sig,
load_q => load_q_sig,
load_m => load_m_sig,
reset_n => reset_n_sig,
shift => shift_sig,
clock => clock,
q0 => q0_sig,
q_1 => q_1_sig,
P => p_sig
);
contatore: contatore_modulo_n
generic map(m)
PORT MAP(
clock => clock,
reset_n => reset_n_sig,
count_en => cnt_en_sig,
up_down => '0',
mod_n => mod_n_sig
);
end Structural;
| gpl-2.0 | 60cda10aef5c552caf25a0498137d217 | 0.585076 | 2.829859 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/counter_modulo_n.vhd | 1 | 2,508 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:49:26 12/20/2015
-- Design Name:
-- Module Name: counter_modulo_n - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter_modulo_n is
generic ( n : natural := 16 );
Port ( clock : in STD_LOGIC;
count_en : in STD_LOGIC;
reset_n : in STD_LOGIC;
up_down : in STD_LOGIC;
load_conteggio : in STD_LOGIC;
conteggio_in : in STD_LOGIC_VECTOR (natural(ceil(log2(real(n))))-1 downto 0);
conteggio_out : out STD_LOGIC_VECTOR ((natural(ceil(log2(real(n)))))-1 downto 0);
count_hit : out STD_LOGIC);
end counter_modulo_n;
architecture Behavioral of counter_modulo_n is
signal pre_conteggio_out : std_logic_vector (natural(ceil(log2(real(n))))-1 downto 0);
begin
contatore : process(clock, reset_n, up_down)
begin
if (reset_n = '0') then
count_hit <= '0';
if(up_down = '0') then
pre_conteggio_out <= (others => '0');
else
pre_conteggio_out <= conv_STD_LOGIC_VECTOR(n-1, natural(ceil(log2(real(n)))));
end if;
elsif (rising_edge(clock)) then
if (load_conteggio = '1') then
pre_conteggio_out <= conteggio_in;
elsif (count_en = '1') then
if (up_down = '0') then
if (pre_conteggio_out = n-1) then
count_hit <= '1';
pre_conteggio_out <= (others => '0');
else
count_hit <= '0';
pre_conteggio_out <= pre_conteggio_out + 1;
end if;
else
if (pre_conteggio_out = 0) then
count_hit <= '1';
pre_conteggio_out <= conv_STD_LOGIC_VECTOR(n-1, natural(ceil(log2(real(n)))));
else
count_hit <= '0';
pre_conteggio_out <= pre_conteggio_out - 1;
end if;
end if;
end if;
end if;
end process;
conteggio_out <= pre_conteggio_out;
end Behavioral;
| gpl-2.0 | dd0a31da2f651b867d65ab534cd98a8a | 0.594896 | 3.054811 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/tb_compute_max.vhd | 1 | 13,652 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:30:47 06/28/2017
-- Design Name:
-- Module Name: tb_compute_max.vhd
-- Project Name: compute_max
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: compute_max
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_compute_max IS
END tb_compute_max;
ARCHITECTURE behavior OF tb_compute_max IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT compute_max
GENERIC ( sample_width : natural := 32;
s : natural := 2;
d : natural := 2;
c : natural := 3);
PORT(
clock : IN std_logic;
reset_n : IN std_logic;
enable : IN std_logic;
sample_abs : IN std_logic_vector(sample_width-1 downto 0);
sample : IN std_logic_vector(sample_width-1 downto 0);
pos_campione : OUT std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : OUT std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : OUT std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0);
max : OUT std_logic_vector(sample_width-1 downto 0);
sample_max : OUT std_logic_vector(sample_width-1 downto 0);
done : OUT std_logic
);
END COMPONENT;
-- for all : compute_max use entity work.compute_max(Behavioral);
for all : compute_max use entity work.compute_max(Structural);
constant sample_width : natural:= 32;
constant s : natural:= 5;
constant d : natural:= 4;
constant c : natural:= 5;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '0';
signal enable : std_logic := '0';
signal sample_abs : std_logic_vector(sample_width-1 downto 0) := (others => '0');
signal sample : std_logic_vector(sample_width-1 downto 0) := (others => '0');
--Outputs
signal pos_campione : std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0);
signal pos_doppler : std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0);
signal pos_satellite : std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0);
signal max : std_logic_vector(sample_width-1 downto 0);
signal done : std_logic;
signal sample_max : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: compute_max
GENERIC MAP(
sample_width => 32,
s => 5,
d => 4,
c => 5
)
PORT MAP (
clock => clock,
reset_n => reset_n,
enable => enable,
sample_abs => sample_abs,
pos_campione => pos_campione,
sample => sample,
sample_max => sample_max,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
max => max,
done => done
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
reset_n <= '1';
wait for clock_period;
wait for 5 ns;
sample <= x"00010001";
-- TEST CASE: primo in assoluto (0,0,0,0x00010001)
--sample_abs <= x"00000050";
sample_abs <= x"00000002";
enable <= '1';
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000008";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000007";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000002";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000001E";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000b";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000f";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000009";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000008";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000002";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000002";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000002";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000a";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000b";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000c";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000002";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000007";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000a";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000008";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000f";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000014";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000010";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000011";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000012";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000013";
wait for clock_period;
sample <= sample + 65537;
-- TEST CASE: ultimo di un satellite (4,3,1,0x00280028)
--sample_abs <= x"00000050";
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
-- TEST CASE: primo di un satellite in mezzo (0,0,2,0x00290029)
--sample_abs <= x"00000050";
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000002";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000005";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000a";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000f";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000e";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000c";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000b";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000008";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000007";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000006";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000005";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000001c";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000010";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000008";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000006";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
-- TEST CASE: massimo interno all'intervallo doppler (2,1,3,0x00440044)
-- sample_abs <= x"00000050";
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000002";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"0000000a";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000009";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000007";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000002";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000005";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000006";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000008";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000008";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000001";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000005";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000004";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000005";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000000";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000006";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
sample_abs <= x"00000003";
wait for clock_period;
sample <= sample + 65537;
-- TEST CASE: ultimo in assoluto (4,3,4,0x00640064)
-- sample_abs <= x"00000050";
sample_abs <= x"0000000a";
wait for clock_period;
wait until done = '1';
wait for 20 ns;
reset_n <= '0';
wait;
end process;
END;
| gpl-2.0 | 963ef4b8a54f38c63e5be5d81d9027c6 | 0.598374 | 3.26681 | false | false | false | false |
shio-phys/SPI-FLASH-Programmer | fpga/Synchronizer.vhd | 1 | 1,158 | --------------------------------------------------------------------------------
--! @file Synchronizer.vhd
--! @brief Synchronize async signal
--! @author Takehiro Shiozaki
--! @date 2013-10-28
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity Synchronizer is
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic;
DOUT : out std_logic
);
end Synchronizer;
architecture RTL of Synchronizer is
signal temp : std_logic;
attribute dont_touch : string;
attribute dont_touch of DoubleFFSynchronizerFF1 : label is "true";
attribute dont_touch of DoubleFFSynchronizerFF2 : label is "true";
begin
DoubleFFSynchronizerFF1 : FDC
generic map(
INIT => '0'
)
port map(
Q => temp,
C => CLK,
CLR => RESET,
D => DIN
);
DoubleFFSynchronizerFF2 : FDC
generic map(
INIT => '0'
)
port map(
Q => DOUT,
C => CLK,
CLR => RESET,
D => temp
);
end RTL;
| mit | f68d2e5ab20b158d266d458ce3834efd | 0.496546 | 4.273063 | false | false | false | false |
freecores/grain | src/VHDL/test_synth/hw2_grain.vhd | 1 | 767 | --
-- synthesis test 2:
-- * without clock enable
-- * slow
--
--
-- Altera EP2C-8, Quartus 8.0: (same as hw1_grain)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw2_grain is
port (
CLK_I : in std_logic;
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw2_grain is
begin
top: entity work.grain
generic map (
DEBUG => false,
FAST => false
)
port map (
CLK_I => CLK_I,
CLKEN_I => '1',
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 | 373be17c39393476834d3a35a8b4c259 | 0.614081 | 2.427215 | false | false | false | false |
AleChir/Digital_Filter_VHDL | Digital_Filter/count_n.vhd | 1 | 746 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity count_n is
generic(N: integer:=16);
port( clk, clear, enable: IN std_logic;
q: OUT std_logic_vector(N-1 downto 0));
end count_n;
architecture behavior of count_n is
signal count: unsigned(N-1 downto 0):= (others => '0');
attribute keep: boolean;
attribute keep of count: signal is true;
begin
process (clk)
begin
if (clk'event and clk= '1') then
if (clear= '0') then
count<=(others => '0');
elsif (enable ='1') then
count<=count + 1;
end if;
end if;
end process;
q<=std_logic_vector(count);
end behavior; | gpl-3.0 | 78ae1d233e955dd159ab9022bfb483a4 | 0.546917 | 3.621359 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core1/tb_wrapper_dds.vhd | 1 | 3,184 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.07.2017 14:41:37
-- Design Name:
-- Module Name: tb_wrapper_dds - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_wrapper_dds is
end tb_wrapper_dds;
architecture Behavioral of tb_wrapper_dds is
component test_dds_wrapper
generic (
campioni : natural := 20460
);
port (
clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
poff_pinc : in STD_LOGIC_VECTOR(47 downto 0);
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC;
sine_cosine : out STD_LOGIC_VECTOR(31 downto 0);
done : out STD_LOGIC
);
end component test_dds_wrapper;
--Constants
constant c : natural:= 5;
constant sample_width : natural := 32;
constant clock_period : time := 10 ns;
--Inputs
signal clock : STD_LOGIC := '0';
signal reset_n : STD_LOGIC := '0';
signal valid_in : STD_LOGIC := '0';
signal poff_pinc : STD_LOGIC_VECTOR(47 downto 0);
--Utili per il test
signal poff : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
signal pinc : STD_LOGIC_VECTOR (23 downto 0) := (others => '0');
--Outputs
signal valid_out : STD_lOGIC := '0';
signal ready_out : STD_LOGIC := '0';
signal sine_cosine : std_logic_vector(sample_width-1 downto 0);
signal done : std_logic;
begin
poff_pinc(47 downto 24) <= poff;
poff_pinc(23 downto 0) <= pinc;
test_dds_wrapper_i : test_dds_wrapper
generic map (
campioni => c
)
port map (
clock => clock,
poff_pinc => poff_pinc,
ready_in => '1',
ready_out => ready_out,
reset_n => reset_n,
sine_cosine => sine_cosine,
valid_in => valid_in,
valid_out => valid_out,
done => done
);
clock_process: process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stimuli: process
begin
wait for clock_period*10;
reset_n <= '1';
poff <= x"000000";
pinc <= x"FFF597";
-- Genero c campioni
valid_in <= '1';
wait for clock_period * 2;
valid_in <= '0';
wait until done = '1';
poff <= x"000000";
pinc <= x"FFF797";
-- Genero ALTRI c campioni
valid_in <= '1';
wait for clock_period * 5;
valid_in <= '0';
wait until done = '1';
poff <= x"000FFF";
pinc <= x"FFF998";
-- Genero ALTRI c campioni
valid_in <= '1';
wait for clock_period;
valid_in <= '0';
wait;
end process;
end Behavioral;
| gpl-2.0 | be8262496dad54a923e603402906dc7a | 0.572864 | 3.394456 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/add_sub/ripple_carry_adder.vhd | 1 | 1,794 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:21:14 11/13/2015
-- Design Name:
-- Module Name: ripple_carry_adder - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ripple_carry_adder is
generic ( n : natural := 4 );
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
c_in : in STD_LOGIC;
c_out : out STD_LOGIC;
ovfl : out STD_LOGIC;
S : out STD_LOGIC_VECTOR (n-1 downto 0));
end ripple_carry_adder;
architecture Structural of ripple_carry_adder is
COMPONENT full_adder
PORT(
a : IN std_logic;
b : IN std_logic;
c_in : IN std_logic;
c_out : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
signal d_sig : std_logic_vector (n downto 0);
begin
d_sig(0) <= c_in;
-- Uscita di overflow (overflow per numeri in complementi a 2)
ovfl <= d_sig(n) xor d_sig(n-1);
-- Uscita di carry_out (overflow per numeri binari naturali)
c_out <= d_sig(n);
adder_gen : for k in n-1 downto 0 generate
full_adder_i: full_adder
port map(a => A(k), b => B(k), c_in => d_sig(k), c_out => d_sig(k+1), s => S(k));
end generate;
end Structural; | gpl-2.0 | 2099bcd013f9f8048e685ae6fda0f2e7 | 0.586957 | 3.261818 | false | false | false | false |
jfdelnero/CPLD_USBHxCFloppyEmulator | rtl/vhdl/HeadShifter.vhd | 1 | 8,994 | -------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-----------H----H--X----X-----CCCCC----22222----0000-----0000------11----------
----------H----H----X-X-----C--------------2---0----0---0----0--1--1-----------
---------HHHHHH-----X------C----------22222---0----0---0----0-----1------------
--------H----H----X--X----C----------2-------0----0---0----0-----1-------------
-------H----H---X-----X---CCCCC-----222222----0000-----0000----1111------------
-------------------------------------------------------------------------------
----------------------------------------- http://jeanfrancoisdelnero.free.fr --
--===========================================================================--
-- HxCFloppyEmu
-- Floppy drive emulator Project
--
-- http://jeanfrancoisdelnero.free.fr
-- HxC2001 - 2006 - 2008
--
-- Design units :
--
-- File name : HeadShifter.vhd
--
-- Purpose : MFM data shifter
--
--
-- Dependencies : IEEE.Std_Logic_1164
-- IEEE.std_logic_signed
--
--============================================================================-
-- --
-- Copyright (C) 2006, 2007, 2008 Jean-François DEL NERO --
-- --
-- This file is part of HxCFloppyEmulator. --
-- --
-- HxCFloppyEmulator may be used and distributed without restriction provided--
-- that this copyright statement is not removed from the file and that any --
-- derivative work contains the original copyright notice and the associated --
-- disclaimer. --
-- --
-- HxCFloppyEmulator is free software; you can redistribute it --
-- and/or modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 2 --
-- of the License, or (at your option) any later version. --
-- --
-- HxCFloppyEmulator is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. --
-- See the GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with HxCFloppyEmulator; if not, write to the Free Software --
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA--
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revision list
-- Version Author Date Changes
--
-- 1.0 Jean-François DEL NERO 23 march 2008 Major update:
--
-- MFM/FM output generator (HeadShifter) rewritten.
-- It can now do any bitrate between
-- 63kbit/s and 1Mbit/s with a 62.5ns step.
-- The emulator can now handle bitrate-protected floppies ;-)
--
-- The SRAM is now used like a ring buffer (1 buffer of 8KB).
--
-- The master state machine run now at 16Mhz
-- to allow fast opcode execution / mfm loading.
--
-- "Validate Track" opcode removed (same functionnality in "SENDTRACKCODE opcode".
-- "SETINDEX" opcode modified:
-- "SENDTRACKCODE" added (2 byte : 0x3 <track number>)
-- "SETBITRATE" opcode added (2 bytes: 0xD <period value>)
-- "NOP" opcode added (2 bytes : 0x7 XX)
-- "Disk Changed" and "Ready" signals
-- are now software driven
--
-- Track position register is now 8 bits.
--
-- SRAM_CS_not is now driven (for the SRAM standby mode)
--
-- 0.5 Jean-François DEL NERO 19 November 2006 Jumper-free drive select added
-- jeanfrancoisdelnero < > free.fr
-- 0.4 Jean-François DEL NERO 11 November 2006 500kbits/s support added
-- 2*1Ko and 2*2Ko buffer size available
-- Write protect signal added
-- Shugart and IBM PC mode available
-- 0.2 Jean-François DEL NERO 16 September 2006 MFM Pulse Generator rewritten
-- 0.1 Jean-François DEL NERO 25 June 2006 First public version
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- package HeadShifter
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------
-- MFM data shifter
--
entity HeadShifter is
port (
-- input // data bus
DATABUS: in std_logic_vector(3 downto 0);
SPEEDCONFIG: in std_logic_vector(7 downto 0);
DATALOADED: out std_logic;
FLOPPY_DATA: out std_logic; -- MFM data line
clock: in std_logic; -- Clock the shifter
reset_not: in std_logic
);
end HeadShifter;
------------------------------------------------------------------------------------------
architecture arch of HeadShifter is
--------------------------------------------
type state_shifter is (STATE0,STATE1,STATE2,STATE3);
signal FLOPPYDATAH0 : std_logic; -- shifter -> pulse generator link
signal speedcnt: std_logic_vector(7 downto 0);
signal tmp: std_logic_vector(3 downto 0);
signal bitcnt: state_shifter;
signal bitcounter: std_logic_vector(1 downto 0);
signal loadtoggle: std_logic;
------------------------------------------------------------------------------------------
BEGIN
process (speedcnt,SPEEDCONFIG,tmp,clock,reset_not)
begin
if (reset_not = '0')
then
speedcnt(7 downto 0)<="00000000";
bitcounter<="00";
loadtoggle<='0';
tmp<="0000";
elsif (clock'event and clock = '1')
then
if(speedcnt(7 downto 1)/="0000000")
then
-- decrement the bitrate prescaler
speedcnt(7 downto 1)<=speedcnt(7 downto 1)-"0000001";
else
-- test we have done a full mfm code (2 bits)
--
if(bitcounter(0)='0' or speedcnt(0)='0')
then
-- increment the bit counter
bitcounter<=bitcounter+"01";
-- shift the data register
tmp <= tmp(2 downto 0) & '0';
if(bitcounter="00")
then
-- we have done all the four bits (2 mfm bits)
-- we need to reload the shifter.
loadtoggle<=not(loadtoggle);
tmp<=DATABUS;
end if;
-- reload of the bitrate prescaler
if(SPEEDCONFIG(7 downto 0)<"00001110")
then
-- the bitrate can't be higher than 1Mbits/s
speedcnt<="00001110";
else
speedcnt<=SPEEDCONFIG;
end if;
else
-- to have the 62.5ns step precision for 2 bits (1 mfm bit).
if(speedcnt(0)='1')
then
speedcnt(0)<='0';
end if;
end if;
end if;
end if;
-- 25% duty cycle signal generator
if(speedcnt(7 downto 1)>('0' & SPEEDCONFIG(7 downto 2)))
then
FLOPPY_DATA <= tmp(3);
else
FLOPPY_DATA <= '0';
end if;
end process;
DATALOADED<=loadtoggle;
END arch; | gpl-3.0 | 67ccb44fc89a150e8fc325686c228341 | 0.396264 | 4.738672 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Card_Avalon_Interface.vhd | 1 | 22,381 | ----------------------------------------------------------------------------------------------------------------
-- This is an FSM that allows access to the SD Card IP core via the Avalon Interconnect.
--
-- This module takes a range of addresses on the Avalon Interconnect. Specifically:
-- - 0x00000000 to 0x000001ff
-- word addressable buffer space. The data to be written to the SD card as well
-- as data read from the SD card can be accessed here.
--
-- - 0x00000200 to 0x0000020f
-- 128-bit containing the Card Identification Number. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000210 to 0x0000021f
-- 128-bit register containing Card Specific Data. The meaning of each bit is described in the
-- SD Card Physical Layer Specification Document.
--
-- - 0x00000220 to 0x00000223
-- 32-bit register containing Operating Conditions Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document.
--
-- - 0x00000224 to 0x00000227
-- 32-bit register containing the Status Register. The meaning of each bit is described
-- in the SD Card Physical Layer Specification Document. However, if the card is not connected or the
-- status register could not be read from the SD card, this register will contain invalid data. In such
-- a case, wait for a card to be connected by checking the Auxiliary Status Register (UP Core Specific), and
-- a command 13 (SEND_STATUS) to update the contents of this register when possible. If a card is connected then
-- the Auxiliary Status Register can be polled until such a time that Status Register is valid, as the SD Card
-- interface circuit updates the status register approximately every 0.1 of a second, and after every command
-- is executed.
--
-- - 0x00000228 to 0x000000229
-- 16-bit register containing the Relative Card Address. This address uniquely identifies a card
-- connected to the SD Card slot.
--
-- - 0x0000022C to 0x00000022F
-- 32-bit register used to set the argument for a command to be sent to the SD Card.
--
-- - 0x00000230 to 0x000000231
-- 16-bit register used to send a command to an SD card. Once written, the interface will issue the
-- specified command. The meaning of each bit in this register is as follows:
-- - 0-5 - command index. This is a command index as per SD Card Physical Layer specification document.
-- - 6 - use most recent RCA. If this bit is set, the command argument will be replaced with the contents of
-- the Relative Card Address register, followed by 16 0s. For commands that require RCA to be sent as
-- an argument, this bit should be set and users will not need to specify RCA themselves.
-- - 7-15 - currently unused bits. They will be ignored.
-- NOTE: If a specified command is determined to be invalid, or the card is not connected to the SD Card socket,
-- then the SD Card interface circuit will not issue the command.
--
-- - 0x00000234 to 0x00000235
-- 16-bit register with Auxiliary Status Register. This is the Altera UP SD Card Interface status. The meaning of
-- the bits is as follows:
-- - 0 - last command valid - Set to '1' if the most recently user issued command was valid.
-- - 1 - card connected - Set to '1' if at present an SD card
-- - 2 - execution in progress - Set to '1' if the command recently issued is currently being executed. If true,
-- then the current state of SD Card registers should be ignored.
-- - 3 - status register valid - Set to '1' if the status register is valid.
-- - 4 - command timed out - Set to '1' if the last command timed out.
-- - 5 - crc failed - Set to '1' if the last command failed a CRC check.
-- - 6-15 - unused.
--
-- - 0x00000238 to 0x0000023B
-- 32-bit register containing the 32-bit R1 response message. Use it to test validity of the response. This register
-- will not store the response to SEND_STATUS command. Insteand, read the SD_status register at location 0x00000224.
--
-- Date: December 8, 2008
-- NOTES/REVISIONS:
-- December 17, 2008 - added R1 response register to the core. It is now available at 0x00000238.
----------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Avalon_Interface is
generic (
ADDRESS_BUFFER : std_logic_vector(7 downto 0) := "00000000";
ADDRESS_CID : std_logic_vector(7 downto 0) := "10000000";
ADDRESS_CSD : std_logic_vector(7 downto 0) := "10000100";
ADDRESS_OCR : std_logic_vector(7 downto 0) := "10001000";
ADDRESS_SR : std_logic_vector(7 downto 0) := "10001001";
ADDRESS_RCA : std_logic_vector(7 downto 0) := "10001010";
ADDRESS_ARGUMENT : std_logic_vector(7 downto 0) := "10001011";
ADDRESS_COMMAND : std_logic_vector(7 downto 0) := "10001100";
ADDRESS_ASR : std_logic_vector(7 downto 0) := "10001101";
ADDRESS_R1 : std_logic_vector(7 downto 0) := "10001110"
);
port
(
-- Clock and Reset signals
i_clock : in STD_LOGIC;
i_reset_n : in STD_LOGIC; -- Asynchronous reset
-- Avalon Interconnect Signals
i_avalon_address : in STD_LOGIC_VECTOR(7 downto 0);
i_avalon_chip_select : in STD_LOGIC;
i_avalon_read : in STD_LOGIC;
i_avalon_write : in STD_LOGIC;
i_avalon_byteenable : in STD_LOGIC_VECTOR(3 downto 0);
i_avalon_writedata : in STD_LOGIC_VECTOR(31 downto 0);
o_avalon_readdata : out STD_LOGIC_VECTOR(31 downto 0);
o_avalon_waitrequest : out STD_LOGIC;
-- SD Card interface ports
b_SD_cmd : inout STD_LOGIC;
b_SD_dat : inout STD_LOGIC;
b_SD_dat3 : inout STD_LOGIC;
o_SD_clock : out STD_LOGIC
);
end entity;
architecture rtl of Altera_UP_SD_Card_Avalon_Interface is
component Altera_UP_SD_Card_Interface is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
-- Command interface
b_SD_cmd : inout std_logic;
b_SD_dat : inout std_logic;
b_SD_dat3 : inout std_logic;
i_command_ID : in std_logic_vector(5 downto 0);
i_argument : in std_logic_vector(31 downto 0);
i_user_command_ready : in std_logic;
o_SD_clock : out std_logic;
o_card_connected : out std_logic;
o_command_completed : out std_logic;
o_command_valid : out std_logic;
o_command_timed_out : out std_logic;
o_command_crc_failed : out std_logic;
-- Buffer access
i_buffer_enable : in std_logic;
i_buffer_address : in std_logic_vector(7 downto 0);
i_buffer_write : in std_logic;
i_buffer_data_in : in std_logic_vector(15 downto 0);
o_buffer_data_out : out std_logic_vector(15 downto 0);
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
o_SD_REG_status_register : out std_logic_vector(31 downto 0);
o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
o_SD_REG_status_register_valid : out std_logic
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type buffer_state_type is ( s_RESET, s_WAIT_REQUEST, s_READ_FIRST_WORD, s_READ_SECOND_WORD, s_RECEIVE_FIRST_WORD,
s_RECEIVE_SECOND_WORD, s_WR_READ_FIRST_WORD, s_WR_READ_FIRST_WORD_DELAY, s_WRITE_FIRST_BYTE, s_WRITE_FIRST_WORD,
s_WR_READ_SECOND_WORD, s_WR_READ_SECOND_WORD_DELAY, s_WRITE_SECOND_BYTE, s_WRITE_SECOND_WORD, s_WAIT_RELEASE);
type command_state_type is (s_RESET_CMD, s_WAIT_COMMAND, s_WAIT_RESPONSE, s_UPDATE_AUX_SR);
-- Register to hold the current state
signal current_state : buffer_state_type;
signal next_state : buffer_state_type;
signal current_cmd_state : command_state_type;
signal next_cmd_state : command_state_type;
-------------------
-- Local signals
-------------------
-- REGISTERED
signal auxiliary_status_reg : std_logic_vector(5 downto 0);
signal buffer_data_out_reg : std_logic_vector(31 downto 0);
signal buffer_data_in_reg : std_logic_vector(31 downto 0);
signal buffer_data_out : std_logic_vector(15 downto 0);
signal command_ID_reg : std_logic_vector( 5 downto 0);
signal argument_reg : std_logic_vector(31 downto 0);
signal avalon_address : std_logic_vector(7 downto 0);
signal avalon_byteenable : std_logic_vector(3 downto 0);
-- UNREGISTERED
signal buffer_address : std_logic_vector(7 downto 0);
signal buffer_data_in : std_logic_vector(15 downto 0);
signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
signal SD_REG_status_register : std_logic_vector(31 downto 0);
signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
signal command_ready, send_command_ready,
command_valid, command_completed, card_connected : std_logic;
signal status_reg_valid, argument_write : std_logic;
signal read_buffer_request, write_buffer_request, buffer_enable, buffer_write : std_logic;
signal command_timed_out, command_crc_failed : std_logic;
begin
-- Define state transitions for buffer interface.
state_transitions_buffer: process (current_state, read_buffer_request, write_buffer_request, i_avalon_byteenable, avalon_byteenable)
begin
case current_state is
when s_RESET =>
-- Reset local registers.
next_state <= s_WAIT_REQUEST;
when s_WAIT_REQUEST =>
-- Wait for a user command.
if (read_buffer_request = '1') then
next_state <= s_READ_FIRST_WORD;
elsif (write_buffer_request = '1') then
if ((i_avalon_byteenable(1) = '1') and (i_avalon_byteenable(0) = '1')) then
next_state <= s_WRITE_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') and (i_avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((i_avalon_byteenable(1) = '1') or (i_avalon_byteenable(0) = '1')) then
next_state <= s_WR_READ_FIRST_WORD;
elsif ((i_avalon_byteenable(3) = '1') or (i_avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_REQUEST;
end if;
else
next_state <= s_WAIT_REQUEST;
end if;
when s_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_READ_SECOND_WORD;
when s_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_RECEIVE_FIRST_WORD;
when s_RECEIVE_FIRST_WORD =>
-- Store first word read
next_state <= s_RECEIVE_SECOND_WORD;
when s_RECEIVE_SECOND_WORD =>
-- Store second word read
next_state <= s_WAIT_RELEASE;
-- The following states control writing to the buffer. To write a single byte it is necessary to read a
-- word and then write it back, changing only on of its bytes.
when s_WR_READ_FIRST_WORD =>
-- Read first 16-bit word from the buffer
next_state <= s_WR_READ_FIRST_WORD_DELAY;
when s_WR_READ_FIRST_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_FIRST_BYTE;
when s_WRITE_FIRST_BYTE =>
-- Write one of the bytes in the given word into the memory.
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WR_READ_SECOND_WORD =>
-- Read second 16-bit word from the buffer
next_state <= s_WR_READ_SECOND_WORD_DELAY;
when s_WR_READ_SECOND_WORD_DELAY =>
-- Wait a cycle
next_state <= s_WRITE_SECOND_BYTE;
when s_WRITE_SECOND_BYTE =>
-- Write one of the bytes in the given word into the memory.
next_state <= s_WAIT_RELEASE;
-- Full word writing can be done without reading the word in the first place.
when s_WRITE_FIRST_WORD =>
-- Write the first word into memory
if ((avalon_byteenable(3) = '1') and (avalon_byteenable(2) = '1')) then
next_state <= s_WRITE_SECOND_WORD;
elsif ((avalon_byteenable(3) = '1') or (avalon_byteenable(2) = '1')) then
next_state <= s_WR_READ_SECOND_WORD;
else
next_state <= s_WAIT_RELEASE;
end if;
when s_WRITE_SECOND_WORD =>
-- Write the second word into memory
next_state <= s_WAIT_RELEASE;
when s_WAIT_RELEASE =>
if ((read_buffer_request = '1') or (write_buffer_request = '1')) then
next_state <= s_WAIT_RELEASE;
else
next_state <= s_WAIT_REQUEST;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_state <= s_RESET;
end case;
end process;
-- State Registers
buffer_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_RESET;
elsif(rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
helper_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
avalon_address <= (OTHERS => '0');
buffer_data_out_reg <= (OTHERS => '0');
buffer_data_in_reg <= (OTHERS => '0');
avalon_byteenable <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
if (current_state = s_WAIT_REQUEST) then
avalon_address <= i_avalon_address;
buffer_data_in_reg <= i_avalon_writedata;
avalon_byteenable <= i_avalon_byteenable;
end if;
if (current_state = s_RECEIVE_FIRST_WORD) then
buffer_data_out_reg(15 downto 0) <= buffer_data_out;
end if;
if (current_state = s_RECEIVE_SECOND_WORD) then
buffer_data_out_reg(31 downto 16) <= buffer_data_out;
end if;
end if;
end process;
-- FSM outputs
o_avalon_waitrequest <= (read_buffer_request or write_buffer_request) when (not (current_state = s_WAIT_RELEASE)) else '0';
buffer_address(7 downto 1) <= avalon_address(6 downto 0);
buffer_address(0) <= '1' when ( (current_state = s_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_WORD) or
(current_state = s_WR_READ_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_enable <= '1' when ( (current_state = s_READ_FIRST_WORD) or (current_state = s_WR_READ_FIRST_WORD) or
(current_state = s_READ_SECOND_WORD) or (current_state = s_WR_READ_SECOND_WORD) or
(current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_write <= '1' when ( (current_state = s_WRITE_FIRST_WORD) or (current_state = s_WRITE_FIRST_BYTE) or
(current_state = s_WRITE_SECOND_WORD) or (current_state = s_WRITE_SECOND_BYTE)) else
'0';
buffer_data_in <= (buffer_data_out(15 downto 8) & buffer_data_in_reg(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "01")) else
(buffer_data_in_reg(15 downto 8) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_FIRST_BYTE) and (avalon_byteenable(1 downto 0) = "10")) else
(buffer_data_out(15 downto 8) & buffer_data_in_reg(23 downto 16)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "01")) else
(buffer_data_in_reg(31 downto 24) & buffer_data_out(7 downto 0)) when ((current_state = s_WRITE_SECOND_BYTE) and (avalon_byteenable(3 downto 2) = "10")) else
buffer_data_in_reg(15 downto 0) when (current_state = s_WRITE_FIRST_WORD) else
buffer_data_in_reg(31 downto 16);
-- Glue Logic
read_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_read);
write_buffer_request <= (not i_avalon_address(7)) and (i_avalon_chip_select) and (i_avalon_write);
-- Define state transitions for command interface.
state_transitions_cmd: process (current_cmd_state, command_completed, command_valid, command_ready)
begin
case current_cmd_state is
when s_RESET_CMD =>
-- Reset local registers.
next_cmd_state <= s_WAIT_COMMAND;
when s_WAIT_COMMAND =>
-- Wait for a user command.
if (command_ready = '1') then
next_cmd_state <= s_WAIT_RESPONSE;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when s_WAIT_RESPONSE =>
-- Generate a predefined command to the SD card. This is the identification process for the SD card.
if ((command_completed = '1') or (command_valid = '0')) then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_RESPONSE;
end if;
when s_UPDATE_AUX_SR =>
-- Update the Auxiliary status register.
if (command_ready = '1') then
next_cmd_state <= s_UPDATE_AUX_SR;
else
next_cmd_state <= s_WAIT_COMMAND;
end if;
when others =>
-- Make sure to start in the reset state if the circuit powers up in an odd state.
next_cmd_state <= s_RESET_CMD;
end case;
end process;
-- State registers
cmd_state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_cmd_state <= s_RESET_CMD;
elsif(rising_edge(i_clock)) then
current_cmd_state <= next_cmd_state;
end if;
end process;
-- FSM outputs
send_command_ready <= '1' when ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) else '0';
-- Glue logic
command_ready <= '1' when ( (i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_COMMAND)) else '0';
argument_write <= '1' when ((i_avalon_chip_select = '1') and (i_avalon_write = '1') and
(i_avalon_address = ADDRESS_ARGUMENT)) else '0';
-- Local Registers
local_regs: process(i_clock, i_reset_n, current_cmd_state, card_connected, command_valid, i_avalon_writedata, command_completed, command_ready)
begin
if (i_reset_n = '0') then
auxiliary_status_reg <= "000000";
command_ID_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- AUX Status Register
if ((current_cmd_state = s_WAIT_RESPONSE) or (current_cmd_state = s_UPDATE_AUX_SR)) then
auxiliary_status_reg(2) <= not command_completed;
auxiliary_status_reg(4) <= command_timed_out;
auxiliary_status_reg(5) <= command_crc_failed;
end if;
auxiliary_status_reg(0) <= command_valid;
auxiliary_status_reg(1) <= card_connected;
auxiliary_status_reg(3) <= status_reg_valid;
-- Command
if (command_ready = '1') then
command_ID_reg <= i_avalon_writedata(5 downto 0);
end if;
end if;
end process;
argument_regs_processing: process(i_clock, i_reset_n, current_cmd_state, i_avalon_writedata, command_ready)
begin
if (i_reset_n = '0') then
argument_reg <= (OTHERS => '0');
elsif(rising_edge(i_clock)) then
-- Argument register
if ((command_ready = '1') and ( i_avalon_writedata(6) = '1')) then
argument_reg <= SD_REG_relative_card_address & "0000000000000000";
elsif (argument_write = '1') then
argument_reg <= i_avalon_writedata;
end if;
end if;
end process;
o_avalon_readdata <= buffer_data_out_reg when (not (current_state = s_WAIT_REQUEST)) else
SD_REG_card_identification_number(31 downto 0) when (i_avalon_address = ADDRESS_CID) else
SD_REG_card_identification_number(63 downto 32) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "01") else
SD_REG_card_identification_number(95 downto 64) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "10") else
SD_REG_card_identification_number(127 downto 96) when (i_avalon_address = ADDRESS_CID(7 downto 2) & "11") else
SD_REG_card_specific_data(31 downto 0) when (i_avalon_address = ADDRESS_CSD) else
SD_REG_card_specific_data(63 downto 32) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "01") else
SD_REG_card_specific_data(95 downto 64) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "10") else
SD_REG_card_specific_data(127 downto 96) when (i_avalon_address = ADDRESS_CSD(7 downto 2) & "11") else
SD_REG_operating_conditions_register when (i_avalon_address = ADDRESS_OCR) else
SD_REG_status_register when (i_avalon_address = ADDRESS_SR) else
("0000000000000000" & SD_REG_relative_card_address)when (i_avalon_address = ADDRESS_RCA) else
argument_reg when (i_avalon_address = ADDRESS_ARGUMENT) else
("00000000000000000000000000" & command_ID_reg) when (i_avalon_address = ADDRESS_COMMAND) else
SD_REG_response_R1 when (i_avalon_address = ADDRESS_R1) else
("00000000000000000000000000" & auxiliary_status_reg);
-- Instantiated Components
SD_Card_Port: Altera_UP_SD_Card_Interface
port map
(
i_clock => i_clock,
i_reset_n => i_reset_n,
-- Command interface
b_SD_cmd => b_SD_cmd,
b_SD_dat => b_SD_dat,
b_SD_dat3 => b_SD_dat3,
i_command_ID => command_ID_reg,
i_argument => argument_reg,
i_user_command_ready => send_command_ready,
o_SD_clock => o_SD_clock,
o_card_connected => card_connected,
o_command_completed => command_completed,
o_command_valid => command_valid,
o_command_timed_out => command_timed_out,
o_command_crc_failed => command_crc_failed,
-- Buffer access
i_buffer_enable => buffer_enable,
i_buffer_address => buffer_address,
i_buffer_write => buffer_write,
i_buffer_data_in => buffer_data_in,
o_buffer_data_out => buffer_data_out,
-- Show SD Card registers as outputs
o_SD_REG_card_identification_number => SD_REG_card_identification_number,
o_SD_REG_relative_card_address => SD_REG_relative_card_address,
o_SD_REG_operating_conditions_register => SD_REG_operating_conditions_register,
o_SD_REG_card_specific_data => SD_REG_card_specific_data,
o_SD_REG_status_register => SD_REG_status_register,
o_SD_REG_response_R1 => SD_REG_response_R1,
o_SD_REG_status_register_valid => status_reg_valid
);
end rtl;
| mit | fe8d0b8d405b54c978475b608472f20b | 0.662392 | 3.096431 | false | false | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/ArithmeticalComparator_x16.vhd | 1 | 1,443 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ArithmeticalComparator_x16 is
Port (
opcodeComp : STD_LOGIC_VECTOR(2 downto 0);
input_A, input_B : STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end ArithmeticalComparator_x16;
architecture skeleton of ArithmeticalComparator_x16 is
component Multiplexer_3x16 is
Port ( Selector : in STD_LOGIC_VECTOR (2 downto 0);
input_A, input_B, input_C, input_D, input_E, input_F, input_G, input_H: in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
signal output000, output001, output010, output011, output100, output101, output111 : STD_LOGIC_Vector(15 downto 0);
begin
output000 <= "1111111111111111" when (input_A = input_B) else "0000000000000000";
output001 <= "1111111111111111" when (input_A /= input_B) else "0000000000000000";
output010 <= "1111111111111111" when (input_A < input_B) else "0000000000000000";
output011 <= "1111111111111111" when (input_A <= input_B) else "0000000000000000";
output100 <= "1111111111111111" when (input_A > input_B) else "0000000000000000";
output101 <= "1111111111111111" when (input_A >= input_B) else "0000000000000000";
output111 <= "0000000000000000";
F1: Multiplexer_3x16 port map (opcodeComp, output000,output001 ,output010 ,output011 ,output100 , output101, output111, output111, output);
end skeleton; | gpl-3.0 | e7b71d737dd7eaa41becf0f97327ff1f | 0.717949 | 3.332564 | false | false | false | false |
Xion345/fpga-projects | library/basic/counter_mod_m.vhd | 1 | 1,083 | -- Simple modulo m counter
-- 20/07/2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_mod_m is
generic(
N: integer := 4; -- Number of bits
M: integer := 10 -- Maximum value
);
port(
clk: in std_logic;
reset: in std_logic; -- Asynchronous reset
max_tick: out std_logic; -- Maximum value reached tick
q: out std_logic_vector(N-1 downto 0) -- Current value
);
end counter_mod_m;
architecture counter_mod_m_arch of counter_mod_m is
signal r_reg: unsigned(N-1 downto 0);
signal r_next: unsigned(N-1 downto 0);
begin
-- State register
process(clk, reset)
begin
if (reset='1') then
r_reg <= (others => '0');
elsif (rising_edge(clk)) then
r_reg <= r_next;
end if;
end process;
-- Next state logic
r_next <= r_reg + 1 when r_reg /= (M-1) else
(others => '0');
-- Output logic
q <= std_logic_vector(r_reg);
max_tick <= '1' when r_reg = (M-1) else '0';
end counter_mod_m_arch;
| mit | 3ef9f48f383d4aa0ae6fcc9488ac6e85 | 0.56602 | 3.301829 | false | false | false | false |
quicky2000/top_alphanumeric | image_controler.vhd | 1 | 7,624 | --
-- This file is part of top_alphanumeric
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity image_controler is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
r : out STD_LOGIC_VECTOR (5 downto 0);
g : out STD_LOGIC_VECTOR (5 downto 0);
b : out STD_LOGIC_VECTOR (5 downto 0);
x : in STD_LOGIC_VECTOR (9 downto 0);
y : in STD_LOGIC_VECTOR (8 downto 0);
enable_in : in std_logic;
hsync_in : in std_logic;
vsync_in : in std_logic;
write_enable : in std_logic;
write_addr : in std_logic_vector(12 downto 0);
char_code : in std_logic_vector(7 downto 0);
color_code : in std_logic_vector(9 downto 0);
enable_out : out std_logic;
hsync_out : out std_logic;
vsync_out : out std_logic);
end image_controler;
architecture Behavioral of image_controler is
------------ Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component ram
port (
clka: IN std_logic;
wea: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(12 downto 0);
dina: IN std_logic_VECTOR(17 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(12 downto 0);
doutb: OUT std_logic_VECTOR(17 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of ram: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
component character_rom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(10 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box of character_rom: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component color_rom
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(9 downto 0);
douta: OUT std_logic_VECTOR(17 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box of color_rom: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- Signals needed to write in memory
signal ram_write_enable : std_logic_vector(0 downto 0);
signal ram_data_in : std_logic_vector(17 downto 0);
-- Signals needed to read from ram
signal ram_read_addr : std_logic_vector(12 downto 0) := (others => '0');
signal ram_data_out : std_logic_vector(17 downto 0);
-- SIgnals to read from character rom
signal read_char_addr : std_logic_vector(10 downto 0);
signal read_char_data : std_logic_vector(7 downto 0);
-- SIgnals to read from character rom
signal read_color_addr : std_logic_vector(9 downto 0);
signal read_color_data : std_logic_vector(17 downto 0);
-- Signal defining column
signal column : std_logic_vector(6 downto 0) := (others => '0');
signal line : std_logic_vector(5 downto 0) := (others => '0');
signal pixel_state : std_logic ;
signal x_delayed : std_logic_vector(2 downto 0) ;
-- Constant defining the delay introduced by the image controler
constant controler_delay : natural := 2;
begin
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
my_ram : ram
port map (
clka => clk,
wea => ram_write_enable,
addra => write_addr,
dina => ram_data_in,
clkb => clk,
addrb => ram_read_addr,
doutb => ram_data_out);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
my_character_rom : character_rom
port map (
clka => clk,
addra => read_char_addr,
douta => read_char_data);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
my_color_rom : color_rom
port map (
clka => clk,
addra => read_color_addr,
douta => read_color_data);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- Block to introduce delays need to have control signals
-- synchronous with colour signals
hsync_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => hsync_in,
output => hsync_out);
vsync_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => vsync_in,
output => vsync_out);
enable_delayer : entity work.bit_delay
generic map (
size => controler_delay)
port map (
clk => clk,
rst => rst,
input => enable_in,
output => enable_out);
x_delayer : entity work.delay_register
generic map(
width => 3,
delay => controler_delay)
port map(
clk => clk,
rst => rst,
input => x(2 downto 0), -- input
output => x_delayed); -- output
-- Process controling adress of read port
--TO DELETE process(clk,rst)
--TO DELETE begin
--TO DELETE if rst = '1' then
--TO DELETE read_addr <= (others => '0');
--TO DELETE elsif rising_edge(clk) and enable_in = '1' and x(2 downto 0) = "111" and y(2 downto 0) = "111" then
--TO DELETE if unsigned(read_addr) /= 4799 then
--TO DELETE read_addr <= std_logic_vector(unsigned(read_addr) + 1);
--TO DELETE else
--TO DELETE read_addr <= (others => '0');
--TO DELETE end if;
--TO DELETE end if;
--TO DELETE end process;
-- Extracting coordinate from pixel in term of character array
column <= x(9 downto 3);
line <= y(8 downto 3);
-- Rebulding corresponding memory addr
ram_read_addr <= line & column;
-- Getting char and color code
read_color_addr <= ram_data_out(17 downto 8);
read_char_addr <= ram_data_out(7 downto 0) & y(2 downto 0);
-- with x(2 downto 0) select
with x_delayed select
pixel_state <= read_char_data(7) when "000",
read_char_data(6) when "001",
read_char_data(5) when "010",
read_char_data(4) when "011",
read_char_data(3) when "100",
read_char_data(2) when "101",
read_char_data(1) when "110",
read_char_data(0) when "111",
'0' when others;
-- Getting color value and pixel value
r <= read_color_data(17 downto 12) when pixel_state = '1' else (others => '0');
g <= read_color_data(11 downto 6) when pixel_state = '1' else (others => '0');
b <= read_color_data(5 downto 0) when pixel_state = '1' else (others => '0');
ram_write_enable <= (others => write_enable);
ram_data_in <= color_code & char_code;
end Behavioral;
| gpl-3.0 | 934c1ba45e2dfad3fe43ebb80d26c7f4 | 0.637198 | 3.560953 | false | false | false | false |
terpstra/opa | opa_lfsr.vhd | 1 | 2,680 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_lfsr is
generic(
g_entropy : natural := 0;
g_bits : natural);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
random_o : out std_logic_vector(g_bits-1 downto 0));
end opa_lfsr;
architecture rtl of opa_lfsr is
-- We only want to work with trinomial irreducible polynomials
-- They build-up less xor chains when we do multiple shifts at once
constant c_size : natural := 18; -- Has a nice trionmial irreducible polynomial
constant c_tap : natural := 11; -- x^18 + x^11 + 1 is irreducible
signal r_reg : std_logic_vector(c_size-1 downto 0);
begin
main : process(clk_i, rst_n_i) is
variable result : std_logic_vector(r_reg'range);
begin
if rst_n_i = '0' then
r_reg <= (others => '1');
elsif rising_edge(clk_i) then
result := r_reg;
for i in 0 to g_bits-1 loop
result := result(result'high-1 downto result'low) & result(result'high);
result(c_tap) := result(c_tap) xor result(result'low);
end loop;
r_reg <= result;
end if;
end process;
random_o <= r_reg(random_o'range);
end rtl;
| gpl-3.0 | 9ccaa07921f34c8ddc9f335c667e3a2b | 0.676119 | 3.521682 | false | false | false | false |
terpstra/opa | opa_isa_base_pkg.vhd | 1 | 9,967 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package opa_isa_base_pkg is
type t_opa_isa_info is record
big_endian : boolean;
num_arch : natural;
imm_wide : natural;
op_wide : natural;
page_size : natural;
end record t_opa_isa_info;
-- All processors must fit under these limits. Increase them if needed.
constant c_imm_wide_max : natural := 128;
constant c_log_arch_max : natural := 8; -- log2(num_arch)
-- Fast execute units operate in one of four modes
-- An example of instructions each mode can handle:
-- lut: XORI, ORI, ANDI, XOR, OR, AND, LUI
-- addlu: AUIPC, ADDI, ADD, SUB
-- addhs: BLT, BGE, SLTI, SLT, BLTU, BGEU, SLTIU, SLTU, BEQ, BNE
-- jump: JAL, JALR
constant c_opa_fast_lut : std_logic_vector(1 downto 0) := "00";
constant c_opa_fast_addl : std_logic_vector(1 downto 0) := "01";
constant c_opa_fast_addh : std_logic_vector(1 downto 0) := "10";
constant c_opa_fast_jump : std_logic_vector(1 downto 0) := "11";
type t_opa_adder is record
eq : std_logic;
nota : std_logic;
notb : std_logic;
cin : std_logic;
sign : std_logic;
fault : std_logic;
end record t_opa_adder;
-- Slow execute units operate in one of four modes
-- mul (00)
-- shift (01)
-- load (10)
-- store (11)
-- An example of instructions each mode can handle:
-- mul: MUL, MULH, MULHSU, MULHU [DIV, DIVU, REM, REMU]
-- shift: SLLI, SRLI, SRAI, SLL, SRL, SRA
-- load: LB, LH, LW, LBU, LHU
-- store: SB, SH, SW
constant c_opa_slow_mul : std_logic_vector(1 downto 0) := "00";
constant c_opa_slow_shift : std_logic_vector(1 downto 0) := "01";
constant c_opa_slow_ldst : std_logic_vector(1 downto 0) := "10";
constant c_opa_slow_sext : std_logic_vector(1 downto 0) := "11";
type t_opa_mul is record
sexta : std_logic; -- DIV|DIVU
sextb : std_logic;
high : std_logic; -- MULH|REM vs. MUL|DIV
divide : std_logic;
end record t_opa_mul;
type t_opa_shift is record
right : std_logic;
sext : std_logic;
end record t_opa_shift;
constant c_opa_ldst_byte : std_logic_vector(1 downto 0) := "00";
constant c_opa_ldst_half : std_logic_vector(1 downto 0) := "01";
constant c_opa_ldst_word : std_logic_vector(1 downto 0) := "10";
constant c_opa_ldst_quad : std_logic_vector(1 downto 0) := "11";
type t_opa_ldst is record
store : std_logic;
sext : std_logic;
size : std_logic_vector(1 downto 0); -- 1,2,4,8
end record t_opa_ldst;
type t_opa_sext is record
size : std_logic_vector(1 downto 0);
end record t_opa_sext;
type t_opa_arg is record
fmode : std_logic_vector(1 downto 0);
adder : t_opa_adder;
lut : std_logic_vector(3 downto 0);
smode : std_logic_vector(1 downto 0);
mul : t_opa_mul;
shift : t_opa_shift;
ldst : t_opa_ldst;
sext : t_opa_sext;
end record t_opa_arg;
-- General information every instruction must provide
type t_opa_op is record
-- Information for the rename stage
archa : std_logic_vector(c_log_arch_max-1 downto 0);
archb : std_logic_vector(c_log_arch_max-1 downto 0);
archx : std_logic_vector(c_log_arch_max-1 downto 0);
geta : std_logic; -- 1=rega, 0=PC
getb : std_logic; -- 1=regb, 0=imm
setx : std_logic;
-- Information for the decode stage
bad : std_logic;
jump : std_logic;
take : std_logic; -- true => jump
force : std_logic; -- true => take
pop : std_logic; -- pop return stack; '-' when jump=0
push : std_logic; -- push return stack; '-' when jump=0
immb : std_logic_vector(c_imm_wide_max-1 downto 0); -- branch immediates; less cases than imm.
-- Information for the issue stage
fast : std_logic; -- goes to fast/slow EU
order : std_logic; -- don't issue it unless it is last
-- Information for the execute stage
imm : std_logic_vector(c_imm_wide_max-1 downto 0);
arg : t_opa_arg;
end record t_opa_op;
constant c_opa_op_bad : t_opa_op := (
archa => (others => '-'),
archb => (others => '-'),
archx => (others => '-'),
geta => '-',
getb => '-',
setx => '-',
bad => '1',
jump => '-',
take => '-',
force => '-',
pop => '-',
push => '-',
immb => (others => '-'),
fast => '-',
order => '-',
imm => (others => '-'),
arg => (
fmode => (others => '-'),
adder => (eq => '-', nota => '-', notb => '-', cin => '-', sign => '-', fault => '-'),
lut => (others => '-'),
smode => (others => '-'),
mul => (sexta => '-', sextb => '-', high => '-', divide => '-'),
shift => (right => '-', sext => '-'),
ldst => (store => '-', sext => '-', size => (others => '-')),
sext => (size => (others => '-'))));
constant c_opa_op_undef : t_opa_op := (
archa => (others => 'X'),
archb => (others => 'X'),
archx => (others => 'X'),
geta => 'X',
getb => 'X',
setx => 'X',
bad => 'X',
jump => 'X',
take => 'X',
force => 'X',
pop => 'X',
push => 'X',
immb => (others => 'X'),
fast => 'X',
order => 'X',
imm => (others => 'X'),
arg => (
fmode => (others => 'X'),
adder => (eq => 'X', nota => 'X', notb => 'X', cin => 'X', sign => 'X', fault => 'X'),
lut => (others => 'X'),
smode => (others => 'X'),
mul => (sexta => 'X', sextb => 'X', high => 'X', divide => 'X'),
shift => (right => 'X', sext => 'X'),
ldst => (store => 'X', sext => 'X', size => (others => 'X')),
sext => (size => (others => 'X'))));
-- Even ISAs need this function
function f_opa_log2(x : natural) return natural;
function f_opa_and(x : std_logic_vector) return std_logic;
function f_opa_or(x : std_logic_vector) return std_logic;
-- Define the arguments needed for operations in our execution units
constant c_arg_wide : natural := 26;
function f_opa_vec_from_arg(x : t_opa_arg) return std_logic_vector;
function f_opa_arg_from_vec(x : std_logic_vector(c_arg_wide-1 downto 0)) return t_opa_arg;
end package;
package body opa_isa_base_pkg is
function f_opa_vec_from_arg(x : t_opa_arg) return std_logic_vector is
variable result : std_logic_vector(c_arg_wide-1 downto 0);
begin
result :=
x.fmode &
x.adder.eq & x.adder.nota & x.adder.notb & x.adder.cin & x.adder.sign & x.adder.fault &
x.lut &
x.smode &
x.mul.sexta & x.mul.sextb & x.mul.high & x.mul.high &
x.shift.right & x.shift.sext &
x.ldst.store & x.ldst.sext & x.ldst.size &
x.sext.size;
return result;
end f_opa_vec_from_arg;
function f_opa_arg_from_vec(x : std_logic_vector(c_arg_wide-1 downto 0)) return t_opa_arg is
variable result : t_opa_arg;
begin
result.fmode := x(25 downto 24);
result.adder.eq := x(23);
result.adder.nota := x(22);
result.adder.notb := x(21);
result.adder.cin := x(20);
result.adder.sign := x(19);
result.adder.fault := x(18);
result.lut := x(17 downto 14);
result.smode := x(13 downto 12);
result.mul.sexta := x(11);
result.mul.sextb := x(10);
result.mul.high := x(9);
result.mul.divide := x(8);
result.shift.right := x(7);
result.shift.sext := x(6);
result.ldst.store := x(5);
result.ldst.sext := x(4);
result.ldst.size := x(3 downto 2);
result.sext.size := x(1 downto 0);
return result;
end f_opa_arg_from_vec;
function f_opa_log2(x : natural) return natural is
begin
if x <= 1
then return 0;
else return f_opa_log2((x+1)/2)+1;
end if;
end f_opa_log2;
function f_opa_or(x : std_logic_vector) return std_logic is
alias y : std_logic_vector(x'length-1 downto 0) is x;
constant c_mid : natural := (y'high + y'low) / 2;
begin
if y'length = 0 then return '0'; end if;
if y'length = 1 then return y(y'low); end if;
return f_opa_or(y(y'high downto c_mid+1)) or
f_opa_or(y(c_mid downto y'low));
end f_opa_or;
function f_opa_and(x : std_logic_vector) return std_logic is
alias y : std_logic_vector(x'length-1 downto 0) is x;
constant c_mid : natural := (y'high + y'low) / 2;
begin
if y'length = 0 then return '1'; end if;
if y'length = 1 then return y(y'left); end if;
return f_opa_and(y(y'high downto c_mid+1)) and
f_opa_and(y(c_mid downto y'low));
end f_opa_and;
end opa_isa_base_pkg;
| gpl-3.0 | dff53f12006946ea7219055a3ef18175 | 0.57881 | 3.077184 | false | false | false | false |
terpstra/opa | opa_dbus.vhd | 1 | 16,055 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_dbus is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
d_cyc_o : out std_logic;
d_stb_o : out std_logic;
d_we_o : out std_logic;
d_stall_i : in std_logic;
d_ack_i : in std_logic;
d_err_i : in std_logic;
d_addr_o : out std_logic_vector(g_config.adr_width -1 downto 0);
d_sel_o : out std_logic_vector(g_config.reg_width/8-1 downto 0);
d_data_o : out std_logic_vector(g_config.reg_width -1 downto 0);
d_data_i : in std_logic_vector(g_config.reg_width -1 downto 0);
-- L1d requests action
l1d_req_i : in t_opa_dbus_request;
l1d_radr_i : in std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_way_i : in std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
l1d_wadr_i : in std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_dirty_i : in std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
l1d_data_i : in std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0);
l1d_busy_o : out std_logic; -- can accept a req_i
l1d_we_o : out std_logic_vector(f_opa_num_dway (g_config) -1 downto 0);
l1d_adr_o : out std_logic_vector(f_opa_adr_wide (g_config) -1 downto 0);
l1d_valid_o : out std_logic_vector(f_opa_dline_size(g_config) -1 downto 0);
l1d_data_o : out std_logic_vector(f_opa_dline_size(g_config)*8-1 downto 0));
end opa_dbus;
architecture rtl of opa_dbus is
constant c_big_endian:boolean := f_opa_big_endian(g_isa);
constant c_page_size: natural := f_opa_page_size(g_isa);
constant c_dline_size:natural := f_opa_dline_size(g_config);
constant c_reg_wide : natural := f_opa_reg_wide(g_config);
constant c_adr_wide : natural := f_opa_adr_wide(g_config);
constant c_num_slow : natural := f_opa_num_slow(g_config);
constant c_num_dway : natural := f_opa_num_dway(g_config);
constant c_idx_low : natural := f_opa_log2(c_reg_wide/8);
constant c_idx_high : natural := f_opa_log2(c_dline_size);
constant c_idx_wide : natural := c_idx_high - c_idx_low;
constant c_line_words : natural := 2**c_idx_wide;
constant c_page_high : natural := f_opa_log2(c_page_size);
constant c_ones : std_logic_vector(c_page_high-1 downto c_idx_high) := (others => '1');
signal r_state : t_opa_dbus_request := OPA_DBUS_WIPE;
signal r_cyc : std_logic := '0';
signal r_stb : std_logic := '0';
signal r_we : std_logic := '1'; -- May only be '0' if r_cyc='1'
signal r_idle1 : std_logic; -- was idle last cycle?
signal s_sel : std_logic_vector(c_reg_wide/8-1 downto 0);
signal r_sel : std_logic_vector(c_reg_wide/8-1 downto 0);
signal r_radr : std_logic_vector(c_adr_wide-1 downto 0) := (others => '0');
signal s_way_en : std_logic_vector(c_num_dway-1 downto 0);
signal r_way : std_logic_vector(c_num_dway-1 downto 0);
signal r_wadr : std_logic_vector(c_adr_wide-1 downto 0) := (others => '0');
signal s_dirty : std_logic_vector(c_dline_size-1 downto 0);
signal r_dirty : std_logic_vector(c_dline_size-1 downto 0);
signal s_storeline: std_logic_vector(c_dline_size*8-1 downto 0);
signal r_storeline: std_logic_vector(c_dline_size*8-1 downto 0);
signal r_adr : std_logic_vector(c_adr_wide-1 downto 0) := (others => '0');
signal s_last_ack : std_logic;
signal s_last_stb : std_logic;
signal s_loadat_in: std_logic_vector(c_line_words-1 downto 0);
signal s_loadat : std_logic_vector(c_line_words-1 downto 0);
signal r_loadat : std_logic_vector(c_line_words-1 downto 0) := (others => '0');
signal r_loaded : std_logic_vector(c_line_words-1 downto 0) := (others => '0');
signal s_loaded_b : std_logic_vector(c_dline_size-1 downto 0);
signal s_loadline : std_logic_vector(c_dline_size*8-1 downto 0);
signal r_loadline : std_logic_vector(c_dline_size*8-1 downto 0) := (others => '0');
signal s_way_ack : std_logic_vector(c_num_dway-1 downto 0);
signal s_wipe : std_logic_vector(c_num_dway-1 downto 0);
signal s_lineout : std_logic_vector(c_reg_wide-1 downto 0);
signal s_dirty_mux: std_logic_vector(c_dline_size-1 downto 0);
signal s_storeline_mux : std_logic_vector(c_dline_size*8-1 downto 0);
signal s_wadr_mux : std_logic_vector(c_adr_wide-1 downto 0);
begin
radr : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_radr <= (others => '0');
elsif rising_edge(clk_i) then
case r_state is
when OPA_DBUS_WIPE =>
r_radr <= r_radr;
r_radr(c_ones'high downto c_ones'low)
<= std_logic_vector(unsigned(r_radr(c_ones'high downto c_ones'low)) + 1);
when OPA_DBUS_IDLE =>
r_radr <= l1d_radr_i;
when others =>
r_radr <= r_radr;
end case;
end if;
end process;
way : process(clk_i) is
begin
if rising_edge(clk_i) then
if r_state = OPA_DBUS_IDLE then
r_way <= l1d_way_i;
end if;
end if;
end process;
count : if c_line_words > 1 generate
b : block is
signal r_out : unsigned(c_idx_wide-1 downto 0);
signal r_in : unsigned(c_idx_wide-1 downto 0);
begin
counters : process(clk_i) is
begin
if rising_edge(clk_i) then
if r_stb = '0' then
r_out <= (others => '0');
elsif d_stall_i = '0' then
r_out <= r_out + 1;
end if;
if r_cyc = '0' then
r_in <= (others => '0');
elsif d_ack_i = '1' then
r_in <= r_in + 1;
end if;
end if;
end process;
s_last_ack <= d_ack_i and f_opa_eq(r_in, c_line_words-1);
s_last_stb <= not d_stall_i and f_opa_eq(r_out, c_line_words-1);
end block;
end generate;
nocount : if c_line_words = 1 generate
s_last_ack <= d_ack_i;
s_last_stb <= not d_stall_i;
end generate;
fsm : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_state <= OPA_DBUS_WIPE;
r_cyc <= '0';
r_stb <= '0';
r_we <= '1';
r_sel <= (others => '-');
elsif rising_edge(clk_i) then
case r_state is
when OPA_DBUS_WIPE =>
if r_radr(c_ones'range) = c_ones then
r_state <= OPA_DBUS_IDLE;
else
r_state <= OPA_DBUS_WIPE;
end if;
r_cyc <= '0';
r_stb <= '0';
r_we <= '1';
r_sel <= (others => '1');
when OPA_DBUS_IDLE =>
r_state <= l1d_req_i;
r_sel <= (others => '1');
case l1d_req_i is
when OPA_DBUS_IDLE =>
r_cyc <= '0';
r_stb <= '0';
r_we <= '1';
when OPA_DBUS_WAIT_STORE_LOAD | OPA_DBUS_WAIT_STORE =>
r_cyc <= '0';
r_stb <= '0';
r_we <= '1';
when OPA_DBUS_LOAD_STORE | OPA_DBUS_LOAD =>
r_cyc <= '1';
r_stb <= '1';
r_we <= '0';
when others => -- impossible cases
r_cyc <= '-';
r_stb <= '-';
r_we <= '-';
end case;
when OPA_DBUS_WAIT_STORE_LOAD =>
r_state <= OPA_DBUS_STORE_LOAD;
r_cyc <= '1';
r_stb <= '1';
r_we <= '1';
r_sel <= s_sel;
when OPA_DBUS_STORE_LOAD =>
r_stb <= r_stb and not s_last_stb;
if s_last_ack = '1' then
r_state <= OPA_DBUS_WAIT_LOAD;
r_cyc <= '0';
r_we <= '1';
r_sel <= (others => '-');
else
r_state <= OPA_DBUS_STORE_LOAD;
r_cyc <= '1';
r_we <= '1';
r_sel <= s_sel;
end if;
when OPA_DBUS_LOAD_STORE =>
r_stb <= r_stb and not s_last_stb;
if s_last_ack = '1' then
r_state <= OPA_DBUS_WAIT_STORE;
r_cyc <= '0';
r_we <= '1';
r_sel <= (others => '-');
else
r_state <= OPA_DBUS_LOAD_STORE;
r_cyc <= '1';
r_we <= '0';
r_sel <= (others => '1');
end if;
when OPA_DBUS_WAIT_LOAD =>
r_state <= OPA_DBUS_LOAD;
r_cyc <= '1';
r_stb <= '1';
r_we <= '0';
r_sel <= (others => '1');
when OPA_DBUS_WAIT_STORE =>
r_state <= OPA_DBUS_STORE;
r_cyc <= '1';
r_stb <= '1';
r_we <= '1';
r_sel <= s_sel;
when OPA_DBUS_LOAD =>
r_stb <= r_stb and not s_last_stb;
if s_last_ack = '1' then
r_state <= OPA_DBUS_IDLE;
r_cyc <= '0';
r_we <= '1';
r_sel <= (others => '-');
else
r_state <= OPA_DBUS_LOAD;
r_cyc <= '1';
r_we <= '0';
r_sel <= (others => '1');
end if;
when OPA_DBUS_STORE =>
r_stb <= r_stb and not s_last_stb;
if s_last_ack = '1' then
r_state <= OPA_DBUS_IDLE;
r_cyc <= '0';
r_we <= '1';
r_sel <= (others => '-');
else
r_state <= OPA_DBUS_STORE;
r_cyc <= '1';
r_we <= '1';
r_sel <= s_sel;
end if;
end case;
end if;
end process;
endian : if c_line_words > 1 generate
load_big : if c_big_endian generate
s_loadat <= std_logic_vector(rotate_right(unsigned(r_loadat), 1));
onehot : for i in 0 to c_line_words-1 generate
s_loadat_in(i) <= f_opa_eq(unsigned(l1d_radr_i(c_idx_high-1 downto c_idx_low)), (c_line_words-1)-i);
end generate;
end generate;
load_small : if not c_big_endian generate
s_loadat <= std_logic_vector(rotate_left(unsigned(r_loadat), 1));
onehot : for i in 0 to c_line_words-1 generate
s_loadat_in(i) <= f_opa_eq(unsigned(l1d_radr_i(c_idx_high-1 downto c_idx_low)), i);
end generate;
end generate;
end generate;
noendian : if c_line_words = 1 generate
s_loadat <= (others => '1');
s_loadat_in <= (others => '1');
end generate;
datin : for i in 0 to c_line_words-1 generate
s_loadline(c_reg_wide*(i+1)-1 downto c_reg_wide*i) <=
f_opa_mux(r_loadat(i), d_data_i, r_loadline(c_reg_wide*(i+1)-1 downto c_reg_wide*i));
end generate;
loadat : process(clk_i) is
begin
if rising_edge(clk_i) then
if r_state = OPA_DBUS_WIPE then
r_loadat <= (others => '0');
r_loaded <= (others => '0');
elsif r_state = OPA_DBUS_IDLE then
r_loadat <= s_loadat_in;
r_loaded <= s_loadat_in;
else
if d_ack_i = '1' then
-- does not matter if this rotates also on writes => complete rotation before read
r_loadat <= s_loadat;
end if;
if (not r_we and d_ack_i) = '1' then
-- need to be more careful here; note: r_we=0 implies r_cyc=1
r_loaded <= r_loaded or s_loadat;
end if;
end if;
end if;
end process;
loaded_bytes : for i in 0 to c_dline_size-1 generate
s_loaded_b(i) <= r_loaded(i / (c_reg_wide/8));
end generate;
loadline : process(clk_i) is
begin
if rising_edge(clk_i) then
if r_state = OPA_DBUS_WIPE then
r_loadline <= (others => '0');
elsif d_ack_i = '1' then
-- ack only needs to be '1' at the correct times during a load cycle
-- any garbage accepted will just get overwritten => harmless
r_loadline <= s_loadline;
end if;
end if;
end process;
address : process(clk_i) is
begin
if rising_edge(clk_i) then
case r_state is
when OPA_DBUS_WIPE =>
r_adr <= (others => '-');
when OPA_DBUS_IDLE =>
r_adr(l1d_radr_i'range) <= l1d_radr_i;
when OPA_DBUS_WAIT_STORE_LOAD | OPA_DBUS_WAIT_STORE =>
r_adr(r_wadr'range) <= s_wadr_mux;
when OPA_DBUS_WAIT_LOAD =>
r_adr(r_radr'range) <= r_radr;
when OPA_DBUS_STORE_LOAD | OPA_DBUS_LOAD_STORE | OPA_DBUS_LOAD | OPA_DBUS_STORE =>
r_adr <= r_adr;
if d_stall_i = '0' and c_line_words > 1 then -- next output address
r_adr(c_idx_high-1 downto c_idx_low) <=
std_logic_vector(unsigned(r_adr(c_idx_high-1 downto c_idx_low)) + 1);
end if;
end case;
end if;
end process;
write_big : if c_big_endian generate
s_dirty <= std_logic_vector(rotate_left(unsigned(r_dirty), c_reg_wide/8));
s_storeline <= std_logic_vector(rotate_left(unsigned(r_storeline), c_reg_wide));
s_lineout <= r_storeline(c_dline_size*8-1 downto c_dline_size*8-c_reg_wide);
s_sel <= s_dirty_mux(c_dline_size-1 downto c_dline_size-c_reg_wide/8);
end generate;
write_little : if not c_big_endian generate
s_dirty <= std_logic_vector(rotate_right(unsigned(r_dirty), c_reg_wide/8));
s_storeline <= std_logic_vector(rotate_right(unsigned(r_storeline), c_reg_wide));
s_lineout <= r_storeline(c_reg_wide-1 downto 0);
s_sel <= s_dirty_mux(c_reg_wide/8-1 downto 0);
end generate;
-- Need this bypass to setup r_sel and r_adr
s_dirty_mux <=
s_dirty when (r_stb and not d_stall_i) = '1' else
l1d_dirty_i when r_idle1 = '1' else
r_dirty;
s_storeline_mux <=
s_storeline when (r_stb and not d_stall_i) = '1' else
l1d_data_i when r_idle1 = '1' else
r_storeline;
s_wadr_mux <= l1d_wadr_i when r_idle1 = '1' else r_wadr;
wdata : process(clk_i) is
begin
if rising_edge(clk_i) then
r_idle1 <= f_opa_bit(r_state = OPA_DBUS_IDLE);
r_wadr <= s_wadr_mux;
r_dirty <= s_dirty_mux;
r_storeline <= s_storeline_mux;
end if;
end process;
d_cyc_o <= r_cyc;
d_stb_o <= r_stb;
d_we_o <= r_we;
d_addr_o <= r_adr;
d_sel_o <= r_sel;
d_data_o <= s_lineout;
l1d_busy_o <= not f_opa_bit(r_state = OPA_DBUS_IDLE);
s_way_ack <= (others => d_ack_i and not r_we);
s_wipe <= (others => f_opa_bit(r_state = OPA_DBUS_WIPE));
l1d_we_o <= (r_way and s_way_ack) or s_wipe;
l1d_adr_o <= r_radr(l1d_adr_o'range);
l1d_valid_o <= s_loaded_b;
l1d_data_o <= s_loadline;
end rtl;
| gpl-3.0 | 15678c1a5b78457ca5da4ee6366f7fd1 | 0.546434 | 2.90378 | false | false | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/Demultiplexer_4x16.vhd | 1 | 2,065 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Demultiplexer_4x16 is
Port ( Selector : in STD_LOGIC_VECTOR(3 downto 0);
input: in STD_LOGIC_VECTOR (15 downto 0);
output_A, output_B, output_C, output_D, output_E, output_F, output_G, output_H : out STD_LOGIC_VECTOR (15 downto 0);
output_I, output_J, output_K, output_L, output_M, output_N, output_O, output_P : out STD_LOGIC_VECTOR (15 downto 0));
end Demultiplexer_4x16;
architecture skeleton of Demultiplexer_4x16 is
begin
with Selector select
output_A <= input when "0000",
"0000000000000000" when others;
with Selector select
output_B <= input when "0001",
"0000000000000000" when others;
with Selector select
output_C <= input when "0010",
"0000000000000000" when others;
with Selector select
output_D <= input when "0011",
"0000000000000000" when others;
with Selector select
output_E <= input when "0100",
"0000000000000000" when others;
with Selector select
output_F <= input when "0101",
"0000000000000000" when others;
with Selector select
output_G <= input when "0110",
"0000000000000000" when others;
with Selector select
output_H <= input when "0111",
"0000000000000000" when others;
with Selector select
output_I <= input when "1000",
"0000000000000000" when others;
with Selector select
output_J <= input when "1001",
"0000000000000000" when others;
with Selector select
output_K <= input when "1010",
"0000000000000000" when others;
with Selector select
output_L <= input when "1011",
"0000000000000000" when others;
with Selector select
output_M <= input when "1100",
"0000000000000000" when others;
with Selector select
output_N <= input when "1101",
"0000000000000000" when others;
with Selector select
output_O <= input when "1110",
"0000000000000000" when others;
with Selector select
output_P <= input when "1111",
"0000000000000000" when others;
end skeleton; | gpl-3.0 | 50df9431ed4b4c6424951393f6d2b0f6 | 0.672639 | 3.560345 | false | false | false | false |
terpstra/opa | opa_dpram.vhd | 1 | 4,182 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_dpram is
generic(
g_width : natural;
g_size : natural;
g_equal : t_dpram_equal;
g_regin : boolean;
g_regout : boolean);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
r_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
r_data_o : out std_logic_vector(g_width-1 downto 0);
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
w_data_i : in std_logic_vector(g_width-1 downto 0));
end opa_dpram;
architecture rtl of opa_dpram is
type t_memory is array(g_size-1 downto 0) of std_logic_vector(g_width-1 downto 0);
signal r_memory : t_memory := (others => (others => '0'));
signal s_bypass : std_logic;
signal r_bypass : std_logic;
signal sr_bypass : std_logic;
signal s_data_memory : std_logic_vector(g_width-1 downto 0);
signal r_data_memory : std_logic_vector(g_width-1 downto 0);
signal sr_data_memory : std_logic_vector(g_width-1 downto 0);
signal s_data_bypass : std_logic_vector(g_width-1 downto 0);
signal r_data_bypass : std_logic_vector(g_width-1 downto 0);
signal sr_data_bypass : std_logic_vector(g_width-1 downto 0);
signal sr_data : std_logic_vector(g_width-1 downto 0);
signal srr_data : std_logic_vector(g_width-1 downto 0);
begin
nohw :
assert (g_equal /= OPA_OLD or g_regin)
report "opa_dpram cannot be used in OPA_OLD mode without a registered input"
severity failure;
s_data_bypass <= w_data_i;
s_data_memory <= r_memory(to_integer(unsigned(r_addr_i))) when f_opa_safe(r_addr_i)='1' else (others => 'X');
s_bypass <= f_opa_eq(r_addr_i, w_addr_i) and w_en_i;
main : process(clk_i) is
begin
if rising_edge(clk_i) then
if w_en_i = '1' then
assert (f_opa_safe(w_addr_i) = '1') report "Attempt to write to a meta-valued address" severity failure;
r_memory(to_integer(unsigned(w_addr_i))) <= w_data_i;
end if;
r_data_bypass <= s_data_bypass;
r_data_memory <= s_data_memory;
r_bypass <= s_bypass;
srr_data <= sr_data;
end if;
end process;
sr_data_bypass <= r_data_bypass when g_regin else s_data_bypass;
sr_data_memory <= r_data_memory when g_regin else s_data_memory;
sr_bypass <= r_bypass when g_regin else s_bypass;
sr_data <=
sr_data_memory when sr_bypass = '0' or g_equal = OPA_OLD else
sr_data_bypass when g_equal = OPA_NEW else
(others => 'X');
r_data_o <= srr_data when g_regout else sr_data;
end rtl;
| gpl-3.0 | b373e5976f0d56ee05db5798bc726f6f | 0.653993 | 3.175399 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Card_Clock.vhd | 2 | 2,224 | -------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; | mit | 92e376ee8f308e428aba199e746ad30a | 0.601169 | 3.172611 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_CRC16_Generator.vhd | 2 | 1,938 | ----------------------------------------------------------------------------------------
-- This generates the necessary 16-CRC for Command and Response
-- Implementation: serial input/parallel output
-- When input stream ends, the crcout output is the CRC checksum for them
--
-- NOTES/REVISIONS:
----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Altera_UP_SD_CRC16_Generator is
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_sync_reset : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of Altera_UP_SD_CRC16_Generator is
-- Local wires
-- REGISTERED
signal shift_register : std_logic_vector(15 downto 0);
begin
process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_register <= (OTHERS => '0');
else
if (rising_edge(i_clock)) then
if (i_sync_reset = '1') then
shift_register <= (OTHERS => '0');
elsif (i_enable = '1') then
if (i_shift = '0') then
shift_register(0) <= i_datain XOR shift_register(15);
shift_register(4 downto 1) <= shift_register(3 downto 0);
shift_register(5) <= shift_register(4) XOR i_datain XOR shift_register(15);
shift_register(11 downto 6) <= shift_register(10 downto 5);
shift_register(12) <= shift_register(11) XOR i_datain XOR shift_register(15);
shift_register(15 downto 13) <= shift_register(14 downto 12);
else -- shift CRC out (no more calculation now)
shift_register(15 downto 1) <= shift_register(14 downto 0);
shift_register(0) <= '0';
end if;
end if;
end if;
end if;
end process;
o_dataout <= shift_register(15);
o_crcout <= shift_register;
end rtl;
| mit | ede5471eb79f12ef46527b789b71f3d1 | 0.585139 | 3.135922 | false | false | false | false |
db-electronics/NESMappers | MMC1/src/MMC1.vhd | 1 | 10,556 |
--Signal types are listed in parenthesis:
--
--(r) this line goes to the ROM only.
--(s) this line is Shared between the ROM, MMC/chip, and Nintendo
--(n) this line connects to the NES cart edge only, and not the ROM
--(w) this line connects to the WRAM only and nowhere else
--
--
--MMC1 Chip: (24 pin shrink-DIP)
------------
--Comes in several varieties: 'MMC1', 'MMC1A', and 'MMC1B2'
--
-- .---\/---.
-- PRG A14 (r) - |01 24| - +5V
-- PRG A15 (r) - |02 23| - M2
-- PRG A16 (r) - |03 22| - PRG A13 (s)
-- PRG A17 (r) - |04 21| - PRG A14 (n)
-- PRG /CE (r) - |05 20| - PRG /CE (n)
-- WRAM CE (w) - |06 19| - PRG D7 (s)
-- CHR A12 (r) - |07 18| - PRG D0 (s)
-- CHR A13 (r) - |08 17| - PRG R/W
-- CHR A14 (r) - |09 16| - CIRAM A10 (n)
-- CHR A15 (r) - |10 15| - CHR A12 (n)
-- CHR A16 (r) or WRAM /CE (w) - |11 14| - CHR A11 (s)
-- GND - |12 13| - CHR A10 (s)
-- `--------'
--
-- MMC1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library altera;
use altera.altera_primitives_components.all;
entity MMC1 is
port (
--reset generator (if required)
--note there are ports specified here which are not required
--for MMC1, this is because the PCB will support other mappers as
--well
nRST_p : in std_logic;
--input from NES
CPUDATA_p : in std_logic_vector(7 downto 0);
CPURnW_p : in std_logic;
nROMSEL_p : in std_logic;
CPUA14_p : in std_logic;
CPUA13_p : in std_logic;
CPUA0_p : in std_logic;
nPPUA13_p : in std_logic;
PPUA13_p : in std_logic;
PPUA12_p : in std_logic;
PPUA11_p : in std_logic;
PPUA10_p : in std_logic;
nPPURD_p : in std_logic;
nPPUWR_p : in std_logic;
M2_p : in std_logic;
CLK_p : in std_logic;
--output to Program ROM / WRAM
PRGA18_p : out std_logic;
PRGA17_p : out std_logic;
PRGA16_p : out std_logic;
PRGA15_p : out std_logic;
PRGA14_p : out std_logic;
PRGA13_p : out std_logic;
nPRGCE_p : out std_logic;
nWRAMCE_p : out std_logic;
--output to Character ROM
CHRA17_p : out std_logic;
CHRA16_p : out std_logic;
CHRA15_p : out std_logic;
CHRA14_p : out std_logic;
CHRA13_p : out std_logic;
CHRA12_p : out std_logic;
CHRA11_p : out std_logic;
CHRA10_p : out std_logic;
--output to NES
nIRQ_p : out std_logic;
nCIRAMCE_p : out std_logic;
CIRAMA10_p : out std_logic
);
end entity;
architecture MMC1_a of MMC1 is
signal RomAddr17to14_s : std_logic_vector(3 downto 0);
signal ChrAddr16to12_s : std_logic_vector(4 downto 0);
signal cpuA15_s : std_logic;
signal MMCReg0_s : std_logic_vector(4 downto 0);
signal MMCReg1_s : std_logic_vector(4 downto 0);
signal MMCReg2_s : std_logic_vector(4 downto 0);
signal MMCReg3_s : std_logic_vector(4 downto 0);
signal TempReg_s : std_logic_vector(4 downto 0);
signal CHRMirr_s : std_logic_vector(1 downto 0);
--state machine for serial writes to registers
signal resetState : std_logic;
type state_type is (s0,s1,s2,s3,s4);
signal current_s,next_s : state_type;
signal cpuAddr15to13_s : std_logic_vector(2 downto 0);
begin
--no IRQ in MMC1
nIRQ_p <= 'Z';
--CIRAM always enabled
nCIRAMCE_p <= nPPUA13_p;
--determine A15
cpuA15_s <= '0' when (M2_p = '1' and nROMSEL_p = '0') else '1';
--group higher addresses for easier reading
cpuAddr15to13_s <= cpuA15_s & CPUA14_p & CPUA13_p;
--**************************************************************
--WRAM
--CPU $6000-$7FFF: 8 KB PRG RAM bank, fixed on all boards but SOROM and SXROM
--M2 is high when address is valid
--0b0110 -> 0b0111
nWRAMCE_p <= '0' when (M2_p = '1' and cpuAddr15to13_s = "011" and MMCReg3_s(4) = '0') else '1';
--**************************************************************
--Mirroring
--To configure a cartridge board for horizontal mirroring, connect PPU A11 to CIRAM A10
--To configure a cartridge board for vertical mirroring, connect PPU A10 to CIRAM A10
--00b - 1-screen mirroring (nametable 0)
--01b - 1-screen mirroring (nametable 1)
--10b - Vert. mirroring
--11b - Horiz. mirroring
CHRMirr_s <= MMCReg0_s(1 downto 0);
CIRAMA10_p <= '0' when CHRMirr_s = "00" else
'1' when CHRMirr_s = "01" else
PPUA10_p when CHRMirr_s = "10" else
PPUA11_p when CHRMirr_s = "11" else
'0';
--**************************************************************
--CHR ROM banking
CHRA10_p <= PPUA10_p;
CHRA11_p <= PPUA11_p;
CHRA12_p <= ChrAddr16to12_s(0);
CHRA13_p <= ChrAddr16to12_s(1);
CHRA14_p <= ChrAddr16to12_s(2);
CHRA15_p <= ChrAddr16to12_s(3);
CHRA16_p <= ChrAddr16to12_s(4);
CHRA17_p <= '0';
CHRBanking : process (PPUA13_p, PPUA12_p)
begin
--check bank size
if (MMCReg0_s(4) = '0') then
--0 - Single 8K bank in CHR space.
--8K bank mode, this selects a full 8K bank at 0000h on the PPU space.
ChrAddr16to12_s <= MMCReg1_s(4 downto 1) & PPUA12_p;
else
--1 - Two 4K banks in CHR space.
--4K bank mode, this selects a 4K bank at 0000h on the PPU space.
if (PPUA12_p = '0') then
ChrAddr16to12_s <= MMCReg1_s(4 downto 0);
else
ChrAddr16to12_s <= MMCReg2_s(4 downto 0);
end if;
end if;
end process;
--**************************************************************
--PRG ROM banking
nPRGCE_p <= nROMSEL_p;
PRGA13_p <= CPUA13_p;
PRGA14_p <= RomAddr17to14_s(0);
PRGA15_p <= RomAddr17to14_s(1);
PRGA16_p <= RomAddr17to14_s(2);
PRGA17_p <= RomAddr17to14_s(3);
PRGA18_p <= '0';
PRGBanking : process (nROMSEL_p, CPUA14_p)
begin
--check bank size
if (MMCReg0_s(3) = '1') then
--16K mode, this selects a 16K bank in either 8000-BFFFh
--or C000-FFFFh depending on the state of the "H" bit in register 0.
--check which bank is swappable
if (MMCReg0_s(2) = '1') then
--1 - Bank C000-FFFFh is fixed, while 8000-FFFFh is swappable. (power-on default)
--fix last bank at $C000 and switch 16 KB bank at $8000
if (CPUA14_p = '0') then --first bank
RomAddr17to14_s <= MMCReg3_s(3 downto 0);
else --last bank
RomAddr17to14_s <= "1111";
end if;
else
--0 - Bank 8000-BFFFh is fixed, while C000-FFFFh is swappable
--fix first bank at $8000 and switch 16 KB bank at $C000;
if (CPUA14_p = '1') then --last bank
RomAddr17to14_s <= MMCReg3_s(3 downto 0);
else --first bank
RomAddr17to14_s <= "0000";
end if;
end if;
else
--32K mode, this selects a full 32K bank in the PRG space.
--Only the upper 3 bits are used then.
RomAddr17to14_s(3 downto 0) <= MMCReg3_s(3 downto 1) & CPUA14_p;
end if;
end process;
--write to mapper registers state machine
--use A14 and A13 to determine the register being written to
--The first bit in is the LSB, while the last bit in is the MSB.
process (nROMSEL_p, CPURnW_p)
begin
if (falling_edge(CPURnW_p)) then
if (nROMSEL_p = '0') then
current_s <= next_s; --state change.
end if;
end if;
end process;
process (current_s, CPUDATA_p, nROMSEL_p)
begin
if (rising_edge(nROMSEL_p)) then
if (CPURnW_p = '0') then
case current_s is
when s0 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
tempReg_s(3 downto 0) <= tempReg_s(4 downto 1);
tempReg_s(4) <= CPUDATA_p(0);
next_s <= s1;
end if;
when s1 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
tempReg_s(3 downto 0) <= tempReg_s(4 downto 1);
tempReg_s(4) <= CPUDATA_p(0);
next_s <= s2;
end if;
when s2 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
tempReg_s(3 downto 0) <= tempReg_s(4 downto 1);
tempReg_s(4) <= CPUDATA_p(0);
next_s <= s3;
end if;
when s3 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
tempReg_s(3 downto 0) <= tempReg_s(4 downto 1);
tempReg_s(4) <= CPUDATA_p(0);
next_s <= s4;
end if;
when s4 =>
if (CPUDATA_p(7) = '1') then
next_s <= s0;
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s <= "01100";
when "01" =>
MMCReg1_s <= "00000";
when "10" =>
MMCReg2_s <= "00000";
when "11" =>
MMCReg3_s <= "00000";
end case;
else
case cpuAddr15to13_s(1 downto 0) is
when "00" =>
MMCReg0_s(3 downto 0) <= tempReg_s(4 downto 1);
MMCReg0_s(4) <= CPUDATA_p(0);
when "01" =>
MMCReg1_s(3 downto 0) <= tempReg_s(4 downto 1);
MMCReg1_s(4) <= CPUDATA_p(0);
when "10" =>
MMCReg2_s(3 downto 0) <= tempReg_s(4 downto 1);
MMCReg2_s(4) <= CPUDATA_p(0);
when "11" =>
MMCReg3_s(3 downto 0) <= tempReg_s(4 downto 1);
MMCReg3_s(4) <= CPUDATA_p(0);
end case;
next_s <= s0;
end if;
when others =>
next_s <= s0;
end case;
end if;
end if;
end process;
end MMC1_a; | gpl-2.0 | ae90b238ae8114353a7348405c9c225c | 0.530978 | 2.591065 | false | false | false | false |
freecores/grain | src/VHDL/test_synth/hw4_grain.vhd | 1 | 763 | --
-- synthesis test 4:
-- * without clock enable
-- * fast
--
-- Altera EP2C-8, Quartus 8.0: (same as hw3_grain)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw4_grain is
port (
CLK_I : in std_logic;
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw4_grain is
begin
top: entity work.grain
generic map (
DEBUG => false,
FAST => true
)
port map (
CLK_I => CLK_I,
CLKEN_I => '1',
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 | b9a51a127904974eccfef9b5364d1608 | 0.61599 | 2.429936 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/add_sub/full_adder.vhd | 1 | 1,542 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:05:40 11/13/2015
-- Design Name:
-- Module Name: full_adder - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c_in : in STD_LOGIC;
c_out : out STD_LOGIC;
s : out STD_LOGIC);
end full_adder;
architecture Structural of full_adder is
COMPONENT half_adder
PORT(
a : IN std_logic;
b : IN std_logic;
c : OUT std_logic;
s : OUT std_logic
);
END COMPONENT;
signal internal_sig : std_logic_vector (2 downto 0);
begin
half_adder1: half_adder
port map(a => a, b => b, c=> internal_sig(1), s => internal_sig(0));
half_adder2: half_adder
port map(a => internal_sig(0), b => c_in, c=> internal_sig(2), s => s);
c_out <= internal_sig(2) or internal_sig(1);
end Structural;
| gpl-2.0 | 14e3065be84ac7fdafcdb140f63d07d0 | 0.557069 | 3.544828 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/tb_wrapper_compute_max_esaustivo.vhd | 1 | 6,354 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 16:57:25
-- Design Name:
-- Module Name: tb_wrapper_compute_max - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.math_real.all;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tb_wrapper_compute_max is
end tb_wrapper_compute_max;
architecture Behavioral of tb_wrapper_compute_max is
component wrapper_compute_max is
Generic ( sample_width : natural := 32;
s : natural := 2;
d : natural := 2;
c : natural := 3);
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
ready_in : in STD_LOGIC;
sample_abs : in STD_LOGIC_VECTOR (sample_width-1 downto 0);
sample : in STD_LOGIC_VECTOR (sample_width-1 downto 0);
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0);
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0);
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0);
max : out STD_LOGIC_VECTOR (sample_width-1 downto 0);
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0);
valid_in : in STD_LOGIC;
ready_out : out STD_LOGIC;
valid_out : out STD_LOGIC);
end component wrapper_compute_max;
--Constants
constant clock_period : time := 10 ns;
constant sample_width : natural := 32;
constant s : natural := 5;
constant d: natural := 4;
constant c : natural := 5;
constant num_cicli : natural := s*c*d;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '1';
signal sample_abs : STD_LOGIC_VECTOR (sample_width-1 downto 0) := (others => '0');
signal sample : STD_LOGIC_VECTOR (sample_width-1 downto 0) := (others => '0');
signal valid_in : STD_LOGIC := '0';
signal ready_in : STD_LOGIC := '0';
--Outputs
signal pos_campione : STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0) := (others => '0');
signal pos_doppler : STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0) := (others => '0');
signal pos_satellite : STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0) := (others => '0');
signal max : STD_LOGIC_VECTOR (sample_width-1 downto 0) := (others => '0');
signal sample_max : STD_LOGIC_VECTOR(sample_width-1 downto 0) := (others => '0');
signal ready_out : STD_LOGIC := '0';
signal valid_out : STD_LOGIC := '0';
begin
uut : wrapper_compute_max
Generic map ( sample_width => sample_width,
s => s,
d => d,
c => c)
Port map(clock => clock,
reset_n => reset_n,
ready_in => ready_in,
valid_in => valid_in,
sample_abs => sample_abs,
sample => sample,
pos_campione => pos_campione,
pos_doppler => pos_doppler,
pos_satellite => pos_satellite,
max => max,
sample_max => sample_max,
ready_out => ready_out,
valid_out => valid_out );
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
--! processo di stimolazione esaustivo
stim_proc: process
variable sample_abs_variable, massimo : std_logic_vector(sample_width-1 downto 0) := (others => '0');
variable massimo_complesso : std_logic_vector(sample_width-1 downto 0) := (others => '0');
variable pos_campione_variable : integer :=0;
variable pos_doppler_variable : integer :=0;
variable pos_satellite_variable : integer :=0;
begin
-- hold reset state for 100 ns.
reset_n<='0';
sample_abs <= (others => '0');
wait for 95 ns;
reset_n<='1';
ready_in <= '1';
for j in 0 to num_cicli-1 loop
--ready_in <= '0';
for i in 0 to num_cicli-1 loop
if (i /= j) then
sample_abs <= STD_LOGIC_VECTOR(to_unsigned(i, sample_width));
sample_abs_variable := STD_LOGIC_VECTOR(to_unsigned(i, sample_width));
else
sample_abs <= std_logic_vector(to_unsigned(num_cicli, sample_width));
sample_abs_variable := std_logic_vector(to_unsigned(num_cicli, sample_width));
end if;
sample <= std_logic_vector(to_unsigned(i*10, sample_width));
if(sample_abs_variable > massimo)then
massimo := sample_abs_variable;
pos_campione_variable := i mod c;
pos_doppler_variable := (i/c)mod d;
pos_satellite_variable := i/(c*d);
massimo_complesso := std_logic_vector(to_unsigned(i*10, sample_width));
end if;
wait for clock_period * 2;
valid_in <='1';
wait for clock_period * 2;
valid_in <= '0';
wait until ready_out = '1';
end loop;
assert(max = massimo) report "Test Fallito massimo trovato errato!";
assert(sample_max = massimo_complesso) report "Test Fallito complesso trovato errato!";
assert(pos_campione_variable = pos_campione) report "Test Fallito pos_campione trovata errata!";
assert(pos_doppler_variable = pos_doppler) report "Test Fallito pos_doppler trovata errata!";
assert(pos_satellite_variable = pos_satellite) report "Test Fallito pos_satellite trovata errata!";
massimo := (others => '0');
reset_n <= '0';
wait for clock_period;
reset_n <= '1';
--ready_in <= '1';
end loop;
wait;
end process;
end Behavioral;
| gpl-2.0 | 9d38b2c5bb82d70fe0c1865971effbe7 | 0.575071 | 3.563657 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/Altera_UP_SD_Card_Memory_Block.vhd | 1 | 11,790 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: Altera_UP_SD_Card_Memory_Block.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.0 Build 215 05/29/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY Altera_UP_SD_Card_Memory_Block IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
enable_a : IN STD_LOGIC := '1';
enable_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END Altera_UP_SD_Card_Memory_Block;
ARCHITECTURE SYN OF altera_up_sd_card_memory_block IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
init_file_layout : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
clocken0 : IN STD_LOGIC ;
clocken1 : IN STD_LOGIC ;
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(0 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "initial_data.mif",
init_file_layout => "PORT_A",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 4096,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 8,
widthad_b => 12,
width_a => 16,
width_b => 1,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
clocken0 => enable_a,
clocken1 => enable_b,
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "1"
-- Retrieval info: PRIVATE: MIFfilename STRING "initial_data.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "1"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "1"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
-- Retrieval info: CONSTANT: INIT_FILE STRING "initial_data.mif"
-- Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
-- Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL address_b[11..0]
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
-- Retrieval info: USED_PORT: data_b 0 0 1 0 INPUT NODEFVAL data_b[0..0]
-- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC enable_a
-- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC enable_b
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
-- Retrieval info: USED_PORT: q_b 0 0 1 0 OUTPUT NODEFVAL q_b[0..0]
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q_b 0 0 1 0 @q_b 0 0 1 0
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
-- Retrieval info: CONNECT: @data_b 0 0 1 0 data_b 0 0 1 0
-- Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
-- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Altera_UP_SD_Card_Memory_Block_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit | 78c205740b0043bf60094f80a4f97ab7 | 0.680237 | 3.240792 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/compute_max.vhd | 1 | 26,093 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:23:18 06/28/2017
-- Design Name:
-- Module Name: compute_max - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
--! @file compute_max.vhd
--! @author Antonio Riccio, Andrea Scognamiglio, Stefano Sorrentino
--! @brief Blocco che calcola il massimo in un insieme di campioni
--! @example tb_compute_max.vhd
--! @anchor compute_max
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.math_real.ceil;
use IEEE.math_real.log2;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--! @brief Componente che calcola il massimo in un insieme di campioni di dimensione s*d*c
--! @details Il componente calcola il massimo di un insieme di campioni espressi
--! mediante il loro modulo
entity compute_max is
Generic ( sample_width : natural := 32; --! Parallelismo in bit del campione
s : natural := 2; --! Numero di satelliti
d : natural := 2; --! Numero di intervalli doppler
c : natural := 3); --! Numero di campioni per intervallo doppler
Port ( clock : in STD_LOGIC; --! Segnale di temporizzazione
reset_n : in STD_LOGIC; --! Segnale di reset 0-attivo
enable : in STD_LOGIC; --! Segnale di abilitazione
sample_abs : in STD_LOGIC_VECTOR (sample_width-1 downto 0); --! Modulo del campione
sample : in STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Valore complesso del campione associato al modulo
pos_campione : out STD_LOGIC_VECTOR(natural(ceil(log2(real(c))))-1 downto 0); --! Posizione del massimo nell'intervallo doppler
pos_doppler : out STD_LOGIC_VECTOR(natural(ceil(log2(real(d))))-1 downto 0); --! Intervallo di frequenze doppler del massimo
pos_satellite : out STD_LOGIC_VECTOR(natural(ceil(log2(real(s))))-1 downto 0); --! Satellite associato al massimo
max : out STD_LOGIC_VECTOR (sample_width-1 downto 0); --! Modulo del massimo
sample_max : out STD_LOGIC_VECTOR(sample_width-1 downto 0); --! Valore complesso del massimo
done : out STD_LOGIC); --! Segnale di terminazione delle operazioni
end compute_max;
--! @brief Architettura del componente descritta nel dominio comportamentale
--! @details L'architettura è stata specificata in fase di prototipazione del componente
--! per verificarne la correttezza funzionale.
--! E' caratterizzata da due processi: uno che elabora il valore dei conteggi e l'altro
--! che effettua i confronti necessari al calcolo del massimo.
--! Per approfondimenti riguardanti le singole fasi dell'algoritmo si rimanda al
--! codice sorgente
architecture Behavioral of compute_max is
--! Contatore dei campioni di un intervallo doppler
signal cont_campioni : std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0) := (others => '0');
--! Registro che memorizza la posizione, nell'intervallo doppler, del massimo
signal posizione_campione : std_logic_vector(natural(ceil(log2(real(c))))-1 downto 0) := (others => '0');
--! Contatore degli intervalli di frequenze doppler
signal cont_doppler : std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0) := (others => '0');
--! Registro che memorizza l'intervallo di frequenze doppler al quale appartiene il massimo
signal posizione_doppler : std_logic_vector(natural(ceil(log2(real(d))))-1 downto 0) := (others => '0');
--! Contatore dei satelliti
signal cont_satelliti : std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0) := (others => '0');
--! Registro che memorizza il satellite associato al massimo
signal posizione_satellite : std_logic_vector(natural(ceil(log2(real(s))))-1 downto 0) := (others => '0');
signal max_satellite, sample_sig : std_logic_vector(sample_width-1 downto 0);
begin
--! @brief Processo che elabora i contatori
--! @details Il processo resetta i contatori opportunamente in base alla posizione del campione attuale
compute_counters : process(clock, reset_n, sample_abs, cont_campioni, cont_doppler, cont_satelliti)
begin
if(reset_n = '0') then
cont_campioni <= (others => '0');
cont_doppler <= (others => '0');
cont_satelliti <= (others => '0');
done <= '0';
elsif (rising_edge(clock) and enable = '1') then
-- Se il campione appena arrivato appartiene allo stesso intervallo di frequenze
-- doppler del campione precedente
-- ovvero il campione è INTERNO ad un intervallo doppler ma non è il primo dell'intervallo
if(cont_campioni < c) then
-- Incrementa il contatore dei campioni per quella frequenza doppler
cont_campioni <= cont_campioni + 1;
else -- Il campione appena arrivato è il PRIMO di un intervallo di frequenze
-- Resetta il contatore dei campioni
cont_campioni <= (0 => '1', others => '0');
-- Segnala l'inizio dell'analisi di un nuovo intervallo di frequenze
-- incrementando il contatore delle frequenze doppler
cont_doppler <= cont_doppler + 1;
-- Se ho finito le frequenze doppler per questo satellite
-- ovvero il campione è l'ULTIMO campione del satellite
if(cont_doppler >= d-1) then
-- Resetta il contatore degli intervalli doppler
cont_doppler <= (others => '0');
-- Segnala la terminazione dell'analisi del satellite
-- incrementandone il relativo contatore
cont_satelliti <= cont_satelliti + 1;
-- Se ho finito di analizzare tutti i satelliti l'algoritmo termina
-- ovvero viene asserito il segnale done
if(cont_satelliti >= s-1) then
done <= '1';
end if;
end if;
end if;
end if;
end process;
--! @brief Processo che elabora il massimo
--! @details Il processo memorizza il valore ed il modulo del massimo e ne aggiorna
--! opportunamente le coordinate in base alla posizione nell'insime di campioni
compute_maximum : process(clock, reset_n, sample_abs, cont_campioni, cont_doppler, cont_satelliti, posizione_campione, posizione_doppler, posizione_satellite, max_satellite, sample)
begin
if(reset_n = '0') then
posizione_campione <= (others => '0');
posizione_doppler <= (others => '0');
posizione_satellite <= (others => '0');
sample_sig <= (others => '0');
max_satellite <= (others => '0');
elsif (rising_edge(clock) and enable = '1') then
-- Confronta il campione appena arrivato con l'attuale max_satellite (valore massimo)
if(sample_abs > max_satellite) then
-- Se il sample_abs è maggiore di max_satellite allora quest'ulitmo viene aggiornato
-- sia nell'informazione riguardante il modulo che nel valore complesso
max_satellite <= sample_abs;
sample_sig <= sample;
-- Vengono aggiornate anche le posizioni del massimo
-- Se il campione appena arrivato appartiene allo stesso intervallo di frequenze
-- doppler del campione precedente
-- ovvero il campione è INTERNO ad un intervallo doppler ma non è il primo dell'intervallo
if(cont_campioni < c) then
posizione_campione <= cont_campioni;
posizione_doppler <= cont_doppler;
posizione_satellite <= cont_satelliti;
else -- Il campione appena arrivato è il PRIMO di un intervallo di frequenze
posizione_campione <= (others => '0');
-- Se il campione è l'ULTIMO campione del satellite
if(cont_doppler >= d-1) then
posizione_doppler <= (others => '0');
posizione_satellite <= cont_satelliti + 1;
else -- Il campione è il primo di un intervallo di frequenze doppler
-- ma NON è il primo campione di un nuovo satellite
posizione_doppler <= cont_doppler + 1;
posizione_satellite <= cont_satelliti;
end if;
end if;
end if;
end if;
pos_campione <= posizione_campione;
pos_doppler <= posizione_doppler;
pos_satellite <= posizione_satellite;
sample_max <= sample_sig;
max <= max_satellite;
end process;
end Behavioral;
--! @brief Architettura del componente descritta nel dominio strutturale
--! @details L'architettura fa uso di componenti già sviluppati in precedenza
architecture Structural of compute_max is
--! @brief Registro a parallelismo generico che opera sul fronte di salita del clock
component register_n_bit
generic (
n : natural := 8
);
port (
I : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end component register_n_bit;
--! @brief Contatore modulo-n di tipo up-down con caricamento del valore di conteggio e
--! segnali di uscita indicanti valore e fine del conteggio
component counter_modulo_n
generic (
n : natural := 16
);
port (
clock : in STD_LOGIC;
count_en : in STD_LOGIC;
reset_n : in STD_LOGIC;
up_down : in STD_LOGIC;
load_conteggio : in STD_LOGIC;
conteggio_in : in STD_LOGIC_VECTOR (natural(ceil(log2(real(n))))-1 downto 0);
conteggio_out : out STD_LOGIC_VECTOR ((natural(ceil(log2(real(n)))))-1 downto 0);
count_hit : out STD_LOGIC
);
end component counter_modulo_n;
--! @brief Comparatore a parallelismo generico che verifica la relazione di maggioranza tra i due input
component comparatore
generic (
width : natural := 31
);
port (
enable : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
AbiggerB : out STD_LOGIC
);
end component comparatore;
--! @brief Automa a stati per la generazione di un segnale impulsivo a partire da uno a livelli
component livelli2impulsi
port (
input : in STD_LOGIC;
clock : in STD_LOGIC;
output : out STD_LOGIC
);
end component livelli2impulsi;
--! @brief Flip-flop D con reset 0-attivo asincrono
component d_edge_triggered
port (
data_in : in STD_LOGIC;
reset_n : in STD_LOGIC;
clock : in STD_LOGIC;
data_out : out STD_LOGIC
);
end component d_edge_triggered;
--! Segnale di uscita del contatore dei campioni (collegato alla linea dato del registro che memorizza la posizione del campione massimo)
signal contatore_campione_out : STD_LOGIC_VECTOR (natural(ceil(log2(real(c))))-1 downto 0);
--! Segnale di uscita del contatore degli intervalli doppler (collegato alla linea dato del registro che memorizza la doppler associata al massimo)
signal contatore_doppler_out : STD_LOGIC_VECTOR (natural(ceil(log2(real(d))))-1 downto 0);
--! Segnale di uscita del contatore dei satelliti (collegato alla linea dato del registro che memorizza il satellite associato al massimo)
signal contatore_satellite_out : STD_LOGIC_VECTOR (natural(ceil(log2(real(s))))-1 downto 0);
signal max_sig, sample_abs_sig, sample_sig : STD_LOGIC_VECTOR(sample_width-1 downto 0);
signal comparatore_out, enable_count_campioni, enable_count_doppler, enable_count_satellite_livelli, enable_count_satellite_impulsi, load_register_doppler_delayed, load_register_satellite_delayed, load_register_satellite_delayed2 : STD_LOGIC;
begin
enable_count_campioni <= enable;
max <= max_sig;
--! Contatore dei campioni di un intervallo doppler
counter_campioni : counter_modulo_n
generic map (
n => c
)
port map (
clock => clock,
count_en => enable_count_campioni,
reset_n => reset_n,
up_down => '0',
load_conteggio => '0',
conteggio_in => (others => '0'),
conteggio_out => contatore_campione_out,
count_hit => enable_count_doppler
);
--! Registro che memorizza la posizione del massimo nell'intervallo doppler
register_campione : register_n_bit
generic map (
n => natural(ceil(log2(real(c))))
)
port map (
I => contatore_campione_out,
clock => clock,
load => comparatore_out,
reset_n => reset_n,
O => pos_campione
);
--! @brief Ritardo imposto al segnale di caricamento del registro doppler
--! @details Questo flip-flop è necessario per consentire il caricamento del valore corretto
--! di conteggio nel registro doppler solo dopo che il contatore abbia commutato la
--! propria uscita (problema che si pone in corrispondenza del primo campione di
--! una nuova frame)
ff_load_doppler : d_edge_triggered
port map (
data_in => comparatore_out,
reset_n => reset_n,
clock => clock,
data_out => load_register_doppler_delayed
);
--! Contatore delle frequenze doppler relative ad un satellite
counter_doppler : counter_modulo_n
generic map (
n => d
)
port map (
clock => clock,
count_en => enable_count_doppler,
reset_n => reset_n,
up_down => '0',
load_conteggio => '0',
conteggio_in => (others => '0'),
conteggio_out => contatore_doppler_out,
count_hit => enable_count_satellite_livelli
);
--! Registro che memorizza l'intervallo di frequenza doppler associato al campione massimo
register_doppler : register_n_bit
generic map (
n => natural(ceil(log2(real(d))))
)
port map (
I => contatore_doppler_out,
clock => clock,
load => load_register_doppler_delayed,
reset_n => reset_n,
O => pos_doppler
);
--! @brief Automa a stati per la gestione del segnale di count_hit
--! @details Questo automa è necessario per convertire il segnale di count_hit del contatore doppler
--! in un segnale impulsivo che va ad abilitare il contatore dei satelliti per un solo conteggio. Senza questo
--! componente il contatore dei satelliti sarebbe abilitato a contare per più di un valore.
enable_count_satellite_impulsivo : livelli2impulsi
port map (
input => enable_count_satellite_livelli,
clock => clock,
output => enable_count_satellite_impulsi
);
--! Contatore dei satelliti
counter_satelliti : counter_modulo_n
generic map (
n => s
)
port map (
clock => clock,
count_en => enable_count_satellite_impulsi,
reset_n => reset_n,
up_down => '0',
load_conteggio => '0',
conteggio_in => (others => '0'),
conteggio_out => contatore_satellite_out,
count_hit => done
);
--! @brief Ritardo imposto al segnale di caricamento del registro satellite
--! @details Questo flip-flop è necessario per consentire il caricamento del valore corretto
--! di conteggio nel registro satellite solo dopo che il contatore abbia commutato la
--! propria uscita (problema che si pone in corrispondenza dell'ultimo campione di
--! un satellite)
ff_load_satellite : d_edge_triggered
port map (
data_in => load_register_doppler_delayed,
reset_n => reset_n,
clock => clock,
data_out => load_register_satellite_delayed
);
--! @brief Secondo ritardo imposto al segnale di caricamento del registro satellite
--! @details Questo secondo ritardo tiene in conto anche dell'ulteriore ritardo inposto
--! contatore delle doppler
ff_load_satellite2 : d_edge_triggered
port map (
data_in => load_register_satellite_delayed,
reset_n => reset_n,
clock => clock,
data_out => load_register_satellite_delayed2
);
--! Registro che memorizza il satellite associato al campione massimo
register_satellite : register_n_bit
generic map (
n => natural(ceil(log2(real(s))))
)
port map (
I => contatore_satellite_out,
clock => clock,
load => load_register_satellite_delayed2,
reset_n => reset_n,
O => pos_satellite
);
--! Ritardo che consente la memorizzazione corretta del modulo del campione massimo
register_sample_abs : register_n_bit
generic map (
n => sample_width
)
port map (
I => sample_abs,
clock => clock,
load => reset_n,
reset_n => reset_n,
O => sample_abs_sig
);
--! Registro che memorizza il modulo associato al campione massimo
register_max : register_n_bit
generic map (
n => sample_width
)
port map (
I => sample_abs_sig,
clock => clock,
load => comparatore_out,
reset_n => reset_n,
O => max_sig
);
--! Ritardo che consente la memorizzazione corretta del campione massimo
register_sample : register_n_bit
generic map (
n => sample_width
)
port map (
I => sample,
clock => clock,
load => reset_n,
reset_n => reset_n,
O => sample_sig
);
--! Registro che memorizza il valore complesso associato al campione massimo
register_sample_max : register_n_bit
generic map (
n => sample_width
)
port map (
I => sample_sig,
clock => clock,
load => comparatore_out,
reset_n => reset_n,
O => sample_max
);
--! Comparatore necessario a comparare il campione in ingresso con il massimo
comparatore_i : comparatore
generic map (
width => sample_width
)
port map (
enable => enable,
A => sample_abs,
B => max_sig,
AbiggerB => comparatore_out
);
end Structural;
architecture Structural_non_continous of compute_max is
--! @brief Registro a parallelismo generico che opera sul fronte di salita del clock
component register_n_bit
generic (
n : natural := 8
);
port (
I : in STD_LOGIC_VECTOR (n-1 downto 0);
clock : in STD_LOGIC;
load : in STD_LOGIC;
reset_n : in STD_LOGIC;
O : out STD_LOGIC_VECTOR (n-1 downto 0)
);
end component register_n_bit;
--! @brief Contatore modulo-n di tipo up-down con caricamento del valore di conteggio e
--! segnali di uscita indicanti valore e fine del conteggio
component counter_modulo_n
generic (
n : natural := 16
);
port (
clock : in STD_LOGIC;
count_en : in STD_LOGIC;
reset_n : in STD_LOGIC;
up_down : in STD_LOGIC;
load_conteggio : in STD_LOGIC;
conteggio_in : in STD_LOGIC_VECTOR (natural(ceil(log2(real(n))))-1 downto 0);
conteggio_out : out STD_LOGIC_VECTOR ((natural(ceil(log2(real(n)))))-1 downto 0);
count_hit : out STD_LOGIC
);
end component counter_modulo_n;
--! @brief Comparatore a parallelismo generico che verifica la relazione di maggioranza tra i due input
component comparatore
generic (
width : natural := 31
);
port (
enable : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
AbiggerB : out STD_LOGIC
);
end component comparatore;
--! @brief Automa a stati per la generazione di un segnale impulsivo a partire da uno a livelli
component livelli2impulsi
port (
input : in STD_LOGIC;
clock : in STD_LOGIC;
output : out STD_LOGIC
);
end component livelli2impulsi;
--! @brief Flip-flop D con reset 0-attivo asincrono
component d_edge_triggered
port (
data_in : in STD_LOGIC;
reset_n : in STD_LOGIC;
clock : in STD_LOGIC;
data_out : out STD_LOGIC
);
end component d_edge_triggered;
--! Segnale di uscita del contatore dei campioni (collegato alla linea dato del registro che memorizza la posizione del campione massimo)
signal contatore_campione_out : STD_LOGIC_VECTOR (natural(ceil(log2(real(c))))-1 downto 0);
--! Segnale di uscita del contatore degli intervalli doppler (collegato alla linea dato del registro che memorizza la doppler associata al massimo)
signal contatore_doppler_out : STD_LOGIC_VECTOR (natural(ceil(log2(real(d))))-1 downto 0);
--! Segnale di uscita del contatore dei satelliti (collegato alla linea dato del registro che memorizza il satellite associato al massimo)
signal contatore_satellite_out : STD_LOGIC_VECTOR (natural(ceil(log2(real(s))))-1 downto 0);
signal max_sig, sample_abs_sig, sample_sig : STD_LOGIC_VECTOR(sample_width-1 downto 0);
signal comparatore_out, enable_count_campioni, enable_count_doppler_livelli, enable_count_doppler_impulsi, enable_count_satellite_livelli, enable_count_satellite_impulsi, load_register_doppler_delayed, load_register_doppler_delayed2, load_register_satellite_delayed, load_register_satellite_delayed2 : STD_LOGIC;
begin
enable_count_campioni <= enable;
max <= max_sig;
--! Contatore dei campioni di un intervallo doppler
counter_campioni : counter_modulo_n
generic map (
n => c
)
port map (
clock => clock,
count_en => enable_count_campioni,
reset_n => reset_n,
up_down => '0',
load_conteggio => '0',
conteggio_in => (others => '0'),
conteggio_out => contatore_campione_out,
count_hit => enable_count_doppler_livelli
);
enable_count_doppler_impulsivo : livelli2impulsi
port map (
input => enable_count_doppler_livelli,
clock => clock,
output => enable_count_doppler_impulsi
);
--! Registro che memorizza la posizione del massimo nell'intervallo doppler
register_campione : register_n_bit
generic map (
n => natural(ceil(log2(real(c))))
)
port map (
I => contatore_campione_out,
clock => clock,
load => comparatore_out,
reset_n => reset_n,
O => pos_campione
);
--! Contatore delle frequenze doppler relative ad un satellite
counter_doppler : counter_modulo_n
generic map (
n => d
)
port map (
clock => clock,
count_en => enable_count_doppler_impulsi,
reset_n => reset_n,
up_down => '0',
load_conteggio => '0',
conteggio_in => (others => '0'),
conteggio_out => contatore_doppler_out,
count_hit => enable_count_satellite_livelli
);
--! @brief Ritardo imposto al segnale di caricamento del registro doppler
--! @details Questo flip-flop è necessario per consentire il caricamento del valore corretto
--! di conteggio nel registro doppler solo dopo che il contatore abbia commutato la
--! propria uscita (problema che si pone in corrispondenza del primo campione di
--! una nuova frame)
ff_load_doppler : d_edge_triggered
port map (
data_in => comparatore_out,
reset_n => reset_n,
clock => clock,
data_out => load_register_doppler_delayed
);
ff_load_doppler2 : d_edge_triggered
port map (
data_in => load_register_doppler_delayed,
reset_n => reset_n,
clock => clock,
data_out => load_register_doppler_delayed2
);
--! Registro che memorizza l'intervallo di frequenza doppler associato al campione massimo
register_doppler : register_n_bit
generic map (
n => natural(ceil(log2(real(d))))
)
port map (
I => contatore_doppler_out,
clock => clock,
load => load_register_doppler_delayed2,
reset_n => reset_n,
O => pos_doppler
);
--! @brief Automa a stati per la gestione del segnale di count_hit
--! @details Questo automa è necessario per convertire il segnale di count_hit del contatore doppler
--! in un segnale impulsivo che va ad abilitare il contatore dei satelliti per un solo conteggio. Senza questo
--! componente il contatore dei satelliti sarebbe abilitato a contare per più di un valore.
enable_count_satellite_impulsivo : livelli2impulsi
port map (
input => enable_count_satellite_livelli,
clock => clock,
output => enable_count_satellite_impulsi
);
--! Contatore dei satelliti
counter_satelliti : counter_modulo_n
generic map (
n => s
)
port map (
clock => clock,
count_en => enable_count_satellite_impulsi,
reset_n => reset_n,
up_down => '0',
load_conteggio => '0',
conteggio_in => (others => '0'),
conteggio_out => contatore_satellite_out,
count_hit => done
);
--! @brief Ritardo imposto al segnale di caricamento del registro satellite
--! @details Questo flip-flop è necessario per consentire il caricamento del valore corretto
--! di conteggio nel registro satellite solo dopo che il contatore abbia commutato la
--! propria uscita (problema che si pone in corrispondenza dell'ultimo campione di
--! un satellite)
ff_load_satellite : d_edge_triggered
port map (
data_in => load_register_doppler_delayed,
reset_n => reset_n,
clock => clock,
data_out => load_register_satellite_delayed
);
--! @brief Secondo ritardo imposto al segnale di caricamento del registro satellite
--! @details Questo secondo ritardo tiene in conto anche dell'ulteriore ritardo inposto
--! contatore delle doppler
ff_load_satellite2 : d_edge_triggered
port map (
data_in => load_register_satellite_delayed,
reset_n => reset_n,
clock => clock,
data_out => load_register_satellite_delayed2
);
--! Registro che memorizza il satellite associato al campione massimo
register_satellite : register_n_bit
generic map (
n => natural(ceil(log2(real(s))))
)
port map (
I => contatore_satellite_out,
clock => clock,
load => load_register_satellite_delayed2,
reset_n => reset_n,
O => pos_satellite
);
sample_abs_sig <= sample_abs;
--! Registro che memorizza il modulo associato al campione massimo
register_max : register_n_bit
generic map (
n => sample_width
)
port map (
I => sample_abs_sig,
clock => clock,
load => comparatore_out,
reset_n => reset_n,
O => max_sig
);
sample_sig <= sample;
--! Registro che memorizza il valore complesso associato al campione massimo
register_sample_max : register_n_bit
generic map (
n => sample_width
)
port map (
I => sample_sig,
clock => clock,
load => comparatore_out,
reset_n => reset_n,
O => sample_max
);
--! Comparatore necessario a comparare il campione in ingresso con il massimo
comparatore_i : comparatore
generic map (
width => sample_width
)
port map (
enable => enable,
A => sample_abs,
B => max_sig,
AbiggerB => comparatore_out
);
end Structural_non_continous;
| gpl-2.0 | 63cf29fb3120fc343b80b03ec176025e | 0.670183 | 3.174093 | false | false | false | false |
terpstra/opa | opa_dpram_altera.vhd | 1 | 6,694 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity opa_dpram is
generic(
g_width : natural;
g_size : natural;
g_equal : t_dpram_equal;
g_regin : boolean;
g_regout : boolean);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
r_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
r_data_o : out std_logic_vector(g_width-1 downto 0);
w_en_i : in std_logic;
w_addr_i : in std_logic_vector(f_opa_log2(g_size)-1 downto 0);
w_data_i : in std_logic_vector(g_width-1 downto 0));
end opa_dpram;
architecture syn of opa_dpram is
constant c_m10k : boolean := g_regin; -- (g_regin and g_size > 32) or (g_equal = OPA_OLD);
constant c_mlab_cin : string := f_opa_choose(g_regin, "OUTCLOCK", "UNREGISTERED");
constant c_mlab_cout : string := f_opa_choose(g_regout, "OUTCLOCK", "UNREGISTERED");
constant c_m10k_cout : string := f_opa_choose(g_regout, "CLOCK0", "UNREGISTERED");
signal s_rdata : std_logic_vector(g_width-1 downto 0);
signal s_bypass : std_logic;
signal r_bypass1 : std_logic;
signal r_bypass2 : std_logic;
signal s_mux_bypass : std_logic;
signal s_wdata : std_logic_vector(g_width-1 downto 0);
signal r_wdata1 : std_logic_vector(g_width-1 downto 0);
signal r_wdata2 : std_logic_vector(g_width-1 downto 0);
signal s_mux_wdata : std_logic_vector(g_width-1 downto 0);
begin
nohw :
assert (g_equal /= OPA_OLD or g_regin)
report "opa_dpram cannot be used in OPA_OLD mode without a registered input"
severity failure;
regout : if not c_m10k generate
ram : altdpram
generic map(
intended_device_family => "Arria V",
indata_aclr => "OFF",
indata_reg => "INCLOCK",
lpm_type => "altdpram",
outdata_aclr => "OFF",
outdata_reg => c_mlab_cout,
ram_block_type => "MLAB",
rdaddress_aclr => "OFF",
rdaddress_reg => c_mlab_cin,
rdcontrol_aclr => "OFF",
rdcontrol_reg => "UNREGISTERED",
read_during_write_mode_mixed_ports => "DONT_CARE",
width => g_width,
widthad => f_opa_log2(g_size),
width_byteena => 1,
wraddress_aclr => "OFF",
wraddress_reg => "INCLOCK",
wrcontrol_aclr => "OFF",
wrcontrol_reg => "INCLOCK")
port map(
outclock => clk_i,
wren => w_en_i,
wraddress => w_addr_i,
data => w_data_i,
inclock => clk_i,
rdaddress => r_addr_i,
q => s_rdata);
end generate;
regin : if c_m10k generate
ram : altsyncram
generic map(
intended_device_family => "Arria V",
address_aclr_b => "NONE",
address_reg_b => "CLOCK0", -- always registered
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_b => "BYPASS",
lpm_type => "altsyncram",
numwords_a => g_size,
numwords_b => g_size,
operation_mode => "DUAL_PORT",
outdata_aclr_b => "NONE",
outdata_reg_b => c_m10k_cout,
power_up_uninitialized => "FALSE",
ram_block_type => "M10K",
read_during_write_mode_mixed_ports => "OLD_DATA",
widthad_a => f_opa_log2(g_size),
widthad_b => f_opa_log2(g_size),
width_a => g_width,
width_b => g_width,
width_byteena_a => 1)
port map(
clock0 => clk_i,
wren_a => w_en_i,
address_a => w_addr_i,
data_a => w_data_i,
address_b => r_addr_i,
q_b => s_rdata);
end generate;
s_wdata <= w_data_i;
s_bypass <= f_opa_bit(r_addr_i = w_addr_i) and w_en_i;
main : process(clk_i) is
begin
if rising_edge(clk_i) then
r_wdata1 <= s_wdata;
r_wdata2 <= r_wdata1;
r_bypass1 <= s_bypass;
r_bypass2 <= r_bypass1;
end if;
end process;
s_mux_bypass <=
s_bypass when (not g_regin and not g_regout) else
r_bypass2 when ( g_regin and g_regout) else
r_bypass1;
s_mux_wdata <=
s_wdata when (not g_regin and not g_regout) else
r_wdata2 when ( g_regin and g_regout) else
r_wdata1;
r_data_o <= s_mux_wdata when (g_equal = OPA_NEW and s_mux_bypass = '1') else s_rdata;
end syn;
| gpl-3.0 | 62a9ecd8174cd646411398833efcecc5 | 0.533313 | 3.602799 | false | false | false | false |
freecores/grain | src/VHDL/test_synth/hw1_grain128.vhd | 1 | 842 | --
-- synthesis test 1:
-- * with clock enable
-- * slow
--
--
-- Altera EP2C-8, Quartus 8.0: 229 LEs,60 bits mem, fmax = 163 MHz (320 requested)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw1_grain128 is
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw1_grain128 is
begin
top: entity work.grain128
generic map (
DEBUG => false,
FAST => false
)
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 | a651bea18bf165129d71ce68cca8f6db | 0.619952 | 2.469208 | false | false | false | false |
terpstra/opa | opa_fast.vhd | 1 | 9,801 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
entity opa_fast is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
regfile_stb_i : in std_logic;
regfile_rega_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_regb_i : in std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
regfile_arg_i : in std_logic_vector(f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_i : in std_logic_vector(f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_regx_o : out std_logic_vector(f_opa_reg_wide(g_config)-1 downto 0);
issue_oldest_i : in std_logic;
issue_retry_o : out std_logic;
issue_fault_o : out std_logic;
issue_pc_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
issue_pcf_o : out std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
issue_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end opa_fast;
architecture rtl of opa_fast is
constant c_imm_wide : natural := f_opa_imm_wide(g_isa);
constant c_adr_wide : natural := f_opa_adr_wide(g_config);
constant c_sum_wide : natural := f_opa_choose(c_imm_wide<c_adr_wide,c_imm_wide,c_adr_wide);
signal s_arg : t_opa_arg;
signal s_adder : t_opa_adder;
signal s_lut : std_logic_vector(3 downto 0);
signal r_rega : std_logic_vector(regfile_rega_i'range);
signal r_regb : std_logic_vector(regfile_regb_i'range);
signal r_imm : std_logic_vector(regfile_imm_i'range);
signal r_pcf : std_logic_vector(regfile_pcf_i'range);
signal r_pc : std_logic_vector(regfile_pc_i'range);
signal r_pcn : std_logic_vector(regfile_pcn_i'range);
signal r_pcf1 : std_logic_vector(regfile_pcf_i'range);
signal r_pc1 : std_logic_vector(regfile_pc_i'range);
signal r_pcn1 : std_logic_vector(regfile_pcn_i'range);
signal r_lut : std_logic_vector(3 downto 0);
signal r_nota : std_logic;
signal r_notb : std_logic;
signal r_cin : std_logic;
signal r_sign : std_logic;
signal r_eq : std_logic;
signal r_fault: std_logic;
signal r_mode : std_logic_vector(1 downto 0);
type t_logic is array(natural range <>) of unsigned(1 downto 0);
signal s_logic_in : t_logic(r_rega'range);
signal s_logic : std_logic_vector(r_rega'range);
signal s_nota : std_logic_vector(r_rega'range);
signal s_notb : std_logic_vector(r_rega'range);
signal s_eq : std_logic_vector(r_rega'range);
signal s_widea : std_logic_vector(r_rega'left+2 downto 0);
signal s_wideb : std_logic_vector(r_rega'left+2 downto 0);
signal s_widex : std_logic_vector(r_rega'left+2 downto 0);
signal s_sum_low : std_logic_vector(r_rega'range);
signal s_comparison : std_logic_vector(r_rega'range);
signal s_pc_next_pad: std_logic_vector(r_rega'range) := (others => '0');
signal s_pc_imm : unsigned(regfile_pcn_i'range);
signal s_pc_next : std_logic_vector(regfile_pcn_i'range);
signal r_pc_next : std_logic_vector(regfile_pcn_i'range);
signal r_pc_jump : std_logic_vector(regfile_pcn_i'range);
signal r_pc_sum : std_logic_vector(regfile_pcn_i'range);
signal r_fmux : std_logic_vector(1 downto 0);
signal s_br_fault : std_logic;
signal s_br_target : std_logic_vector(regfile_pcn_i'range);
attribute dont_merge : boolean;
attribute maxfan : natural;
-- Do not merge these registers; they are used in different places!
attribute dont_merge of r_lut : signal is true;
attribute dont_merge of r_eq : signal is true;
attribute dont_merge of r_nota : signal is true;
attribute dont_merge of r_notb : signal is true;
attribute dont_merge of r_cin : signal is true;
attribute dont_merge of r_sign : signal is true;
attribute dont_merge of r_fault: signal is true;
attribute dont_merge of r_mode : signal is true;
-- These are fanned out to 64 bits; make it easier to fit
-- attribute maxfan of r_lut : signal is 8;
-- attribute maxfan of r_mode : signal is 8;
begin
s_arg <= f_opa_arg_from_vec(regfile_arg_i);
s_adder <= s_arg.adder;
s_lut <= s_arg.lut;
-- Register our inputs
main : process(clk_i) is
begin
if rising_edge(clk_i) then
r_rega <= regfile_rega_i;
r_regb <= regfile_regb_i;
r_imm <= regfile_imm_i;
r_pcf <= regfile_pcf_i;
r_pc <= regfile_pc_i;
r_pcn <= regfile_pcn_i;
r_mode <= s_arg.fmode;
r_lut <= s_lut;
r_eq <= s_adder.eq;
r_nota <= s_adder.nota;
r_notb <= s_adder.notb;
r_cin <= s_adder.cin;
r_sign <= s_adder.sign;
r_fault<= s_adder.fault;
end if;
end process;
-- Result is a logic function
logic : for i in r_rega'range generate
s_logic_in(i)(1) <= r_rega(i);
s_logic_in(i)(0) <= r_regb(i);
s_logic(i) <= f_opa_index(r_lut, s_logic_in(i));
end generate;
-- Result is an adder function
s_nota <= (others => r_nota);
s_notb <= (others => r_notb);
s_eq <= (others => r_eq);
s_widea(r_rega'left+2) <= '0';
s_wideb(r_rega'left+2) <= '0';
-- !!! this is too slow: ... find a way to get it into the adder
s_widea(r_rega'left+1 downto 1) <= s_nota xor r_rega xor (r_regb and s_eq);
s_wideb(r_rega'left+1 downto 1) <= s_notb xor (r_regb and not s_eq);
s_widea(0) <= '1';
s_wideb(0) <= r_cin;
s_widex <= std_logic_vector(unsigned(s_widea) + unsigned(s_wideb));
s_sum_low <= s_widex(r_rega'left+1 downto 1);
-- Result is a comparison
s_comparison(0) <= s_widex(r_rega'left+2) xor ((r_rega(31) xor r_regb(31)) and r_sign);
s_comparison(r_rega'left downto 1) <= (others => '0');
-- Result is a jump return address
s_pc_next <= std_logic_vector(unsigned(r_pc) + 1);
s_pc_next_pad(s_pc_next'high-1 downto s_pc_next'low) <= std_logic_vector(s_pc_next(s_pc_next'high-1 downto s_pc_next'low));
s_pc_next_pad(r_rega'high downto s_pc_next'high) <= (others => s_pc_next(s_pc_next'high));
-- Send result to regfile
with r_mode select
regfile_regx_o <=
s_logic when c_opa_fast_lut,
s_sum_low when c_opa_fast_addl,
s_comparison when c_opa_fast_addh,
s_pc_next_pad when c_opa_fast_jump,
(others => 'X') when others;
-- Pack immediate into sum format
s_pc_imm(c_sum_wide-2 downto r_pc'low) <= unsigned(r_imm(c_sum_wide-2 downto r_pc'low));
s_pc_imm(r_pc'high downto c_sum_wide-1) <= (others => r_imm(c_sum_wide-1));
faults : process(clk_i) is
begin
if rising_edge(clk_i) then
r_pcf1 <= r_pcf;
r_pc1 <= r_pc;
r_pcn1 <= r_pcn;
r_pc_next <= s_pc_next;
r_pc_jump <= std_logic_vector(unsigned(r_pc) + s_pc_imm);
r_pc_sum <= s_sum_low(r_pc_sum'range);
case r_mode is
when c_opa_fast_lut => r_fmux <= "11";
when c_opa_fast_addl => r_fmux <= "11";
when c_opa_fast_addh => r_fmux(0) <= not r_fault or s_comparison(0);
r_fmux(1) <= not r_fault;
when c_opa_fast_jump => r_fmux <= "10";
when others => r_fmux <= "XX";
end case;
end if;
end process;
with r_fmux select
s_br_fault <=
not f_opa_eq(r_pc_next, r_pcn1) when "00", -- addh, fault, and comparison=0
not f_opa_eq(r_pc_jump, r_pcn1) when "01", -- addh, fault, and comparison=1
not f_opa_eq(r_pc_sum, r_pcn1) when "10", -- jump
'0' when "11",
'X' when others;
with r_fmux select
s_br_target <=
r_pc_next when "00",
r_pc_jump when "01",
r_pc_sum when "10",
(others => 'X') when others;
issue_retry_o <= s_br_fault;
issue_fault_o <= s_br_fault and issue_oldest_i;
issue_pcf_o <= r_pcf1;
issue_pc_o <= r_pc1;
issue_pcn_o <= s_br_target;
end rtl;
| gpl-3.0 | cbe631a04afafebe849bc6739bccc0b2 | 0.622283 | 2.861606 | false | true | false | false |
freecores/grain | src/VHDL/grain128.vhd | 1 | 3,340 | --
-- Grain128
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain128 is
generic (
DEBUG : boolean := false; -- output debug information
FAST : boolean := false -- attempt manual register balancing
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of grain128 is
type state_t is (IDLE, INIT_KEYIV, INIT_RUN);
signal state : state_t;
signal cnt : unsigned(8 downto 0);
signal inject_input, set_injected_iv , allow_output : std_logic;
signal add_output : std_logic;
signal output_bit, output_bit_d, allow_output_d : std_logic;
begin
KEYSTREAM_O <= output_bit_d;
KEYSTREAM_VALID_O <= allow_output_d;
slow_design: if FAST = false generate
begin
functions0: entity work.grain128_datapath_slow
generic map ( DEBUG => DEBUG )
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INJECT_INPUT_I => inject_input,
PAD_IV_I => set_injected_iv,
ADD_OUTPUT_I => add_output,
H_O => output_bit
);
end generate;
fast_design: if FAST = true generate
begin
functions1: entity work.grain128_datapath_fast
generic map ( DEBUG => DEBUG )
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INJECT_INPUT_I => inject_input,
PAD_IV_I => set_injected_iv,
ADD_OUTPUT_I => add_output,
H_O => output_bit
);
end generate;
-- output registers:
-- (in case the "user" forgets this is at
-- his end and kills my fmax)
--
output_reg: process(CLK_I, ARESET_I)
begin
if ARESET_I = '1' then
output_bit_d <= '0';
allow_output_d <= '0';
elsif rising_edge(CLK_I) then
if CLKEN_I = '1' then
output_bit_d <= output_bit;
allow_output_d <= allow_output;
end if;
end if;
end process;
-- the counter:
cnt_proc: process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
if state = IDLE then
cnt <= b"0_0000_0001";
else
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
-- the controller fsm:
ctrl_proc: process(CLK_I, ARESET_I)
begin
if ARESET_I = '1' then
state <= IDLE;
inject_input <= '0';
set_injected_iv <= '0';
add_output <= '0';
allow_output <= '0';
elsif rising_edge(CLK_I) then
if CLKEN_I = '1' then
case state is
when IDLE =>
if INIT_I = '1' then
state <= INIT_KEYIV;
inject_input <= '1';
set_injected_iv <= '0';
allow_output <= '0';
end if;
when INIT_KEYIV =>
if cnt(6 downto 5) = "11" then
set_injected_iv <= '1';
end if;
if cnt(7) = '1' then
state <= INIT_RUN;
inject_input <= '0';
add_output <= '1';
end if;
when INIT_RUN =>
if cnt(8 downto 7) = "11" then
state <= IDLE;
add_output <= '0';
allow_output <= '1';
end if;
when others => state <= IDLE;
end case;
end if;
end if;
end process;
end behav;
| lgpl-3.0 | 48ba450871be273306c03bab4bc78276 | 0.562275 | 2.755776 | false | false | false | false |
Xion345/fpga-projects | projects/vga-palette/vga_palette.vhd | 1 | 1,257 | -- VGA Palette Pixel Generation Circuit
--
library ieee;
use ieee.std_logic_1164.ALL;
entity vga_palette is
generic(
SQUARE_SIDE_BITS: integer := 2
);
port(
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(2 downto 1);
pixel_x: in std_logic_vector(SQUARE_SIDE_BITS + 4 downto 0);
pixel_y: in std_logic_vector(SQUARE_SIDE_BITS + 4 downto 0);
video_on: in std_logic;
red_on: in std_logic; -- Activate red component
green_on: in std_logic; -- Activate green component
blue_on: in std_logic -- Activate blue component
);
end vga_palette;
architecture vga_palette_arch of vga_palette is
begin
blue <= pixel_x(SQUARE_SIDE_BITS+2 downto SQUARE_SIDE_BITS+1) when video_on = '1' and blue_on = '1'
else "00";
green(1 downto 0) <= pixel_x(SQUARE_SIDE_BITS+4 downto SQUARE_SIDE_BITS+3) when video_on = '1' and green_on = '1'
else "00";
green(2) <= pixel_y(SQUARE_SIDE_BITS+1) when video_on = '1' and green_on = '1'
else '0';
red <= pixel_y(SQUARE_SIDE_BITS+4 downto SQUARE_SIDE_BITS+2) when video_on = '1' and red_on = '1'
else "000";
end vga_palette_arch;
| mit | 12d49191ecbd3622153595031bb9b13c | 0.620525 | 3.134663 | false | false | false | false |
terpstra/opa | opa_isa_pkg.vhd | 1 | 2,700 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_riscv_pkg.all;
use work.opa_lm32_pkg.all;
package opa_isa_pkg is
function f_opa_isa_info(isa : t_opa_isa) return t_opa_isa_info;
function f_opa_isa_accept(isa : t_opa_isa; config : t_opa_config) return std_logic;
function f_opa_isa_decode(isa : t_opa_isa; config : t_opa_config; x : std_logic_vector) return t_opa_op;
end package;
package body opa_isa_pkg is
function f_opa_isa_info(isa : t_opa_isa) return t_opa_isa_info is
begin
case isa is
when T_OPA_RV32 => return c_opa_rv32;
when T_OPA_LM32 => return c_opa_lm32;
end case;
end f_opa_isa_info;
function f_opa_isa_accept(isa : t_opa_isa; config : t_opa_config) return std_logic is
begin
case isa is
when T_OPA_RV32 => return f_opa_accept_rv32(config);
when T_OPA_LM32 => return f_opa_accept_lm32(config);
end case;
end f_opa_isa_accept;
function f_opa_isa_decode(isa : t_opa_isa; config : t_opa_config; x : std_logic_vector) return t_opa_op is
alias y : std_logic_vector(x'length-1 downto 0) is x;
begin
case isa is
when T_OPA_RV32 => return f_opa_decode_rv32(config, y);
when T_OPA_LM32 => return f_opa_decode_lm32(config, y);
end case;
end f_opa_isa_decode;
end opa_isa_pkg;
| gpl-3.0 | df8e18a06e2839566d9cb9fd3a8bb0c3 | 0.687037 | 3.249097 | false | true | false | false |
Scientistt/Processador_FabioVitor | Code/Holocron battle droid 16 bits/ControlUnity_x16.vhd | 1 | 3,966 | library ieee;
use ieee.std_logic_1164.all;
entity ControlUnity_x16 is
port (
opcode : in STD_LOGIC_VECTOR(4 downto 0);
funct : in STD_LOGIC_VECTOR(2 downto 0);
ulaop, reg1w, reg1r : out std_logic_vector(3 downto 0);
wr1, wr2, regOrNum, row, dvc, sri, memOrUla : out std_logic;
bool : out std_logic_vector(1 downto 0));
end ControlUnity_x16;
architecture skeleton of ControlUnity_x16 is
begin
-- Flag para indicar se o valor que será escrito no registradoro 1 é prveniente da memória RAM ou da ULA
with opcode select
memOrUla <= '0' when "10110",
'0' when "10111",
'0' when "11000",
'0' when "11001",
'1' when others;
-- Flag para verificar se o salto será feito direto - valores imediatos - ou para um endereço no registrador.
with opcode select
sri <= '0' when "10000",
'0' when "10010",
'0' when "10011",
'1' when others;
-- Flag para verificar se deve ser checado o valor do registrador BOOL para confirmar o salto
with opcode select
bool <= "00" when "10011",
"00" when "10101",
"11" when "10010",
"11" when "10100",
"10" when others;
-- Flag para indicar se existe a intenção de haver um salto nas instruções.
with opcode select
dvc <= '1' when "10000",
'1' when "10001",
'1' when "10010",
'1' when "10011",
'1' when "10100",
'1' when "10101",
'0' when others;
-- Flag para indicar para a memória RAM se é para ler do endereço passado ou para escrever nele.
with opcode select
row <= '1' when "11000",
'1' when "11001",
'0' when others;
-- O banco de registradores deve escrever o dado recebido 2 no endereço do registrador 2.
with opcode select
wr2 <= '1' when "01110",
'1' when "01111",
'0' when others;
-- O banco de registradores deve escrever o dado recebido 1 no endereço do registrador 1
with opcode select
wr1 <= '0' when "10000",
'0' when "10001",
'0' when "10010",
'0' when "10011",
'0' when "10100",
'0' when "10101",
'0' when "11000",
'0' when "11001",
'1' when others;
-- Flag para verificar se Código para saber de onde o dado 1 será lido.
with opcode select
reg1r <= "0011" when "10010",
"0011" when "10011",
"0011" when "10100",
"0011" when "10101",
"0000" when others;
-- Código para saber onde o dado 1 será gravado.
with opcode select
reg1w <= "0010" when "01110",
"0010" when "01111",
"0011" when "01000",
"0011" when "01001",
"0011" when "01010",
"0011" when "01011",
"0011" when "01100",
"0011" when "01101",
"0000" when others;
-- Código de operação que sairá para a ULA
with opcode select
ulaop <= "0000" when "00001",
"0001" when "11010",
opcode(3 downto 0) when others;
-- Flag para verificar se a ULA deverá usar o valor no Registrador 2 ou o número como constante na operação
with opcode select
regOrNum <= funct(0) when "01000",
funct(0) when "01001",
funct(0) when "01010",
funct(0) when "01011",
funct(0) when "01100",
funct(0) when "01101",
funct(0) when "01110",
funct(0) when "01111",
funct(0) when "11010",
opcode(0) when "10110",
opcode(0) when "10111",
opcode(0) when "11000",
opcode(0) when "11001",
opcode(0) when "00000",
opcode(0) when "00001",
'0' when "00101",
'0' when "00110",
'0' when "00111",
funct(1) when "00010",
funct(1) when "00011",
funct(1) when "00100",
'0' when others;
end skeleton; | gpl-3.0 | a4fcb02b27fcc3dd547e417903176de1 | 0.552538 | 3.240132 | false | false | false | false |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Card_Response_Receiver.vhd | 2 | 10,743 | -------------------------------------------------------------------------------------
-- This module looks at the data on the CMD line and waits to receive a response.
-- It begins examining the data lines when the i_begin signal is asserted. It then
-- waits for a first '0'. It then proceeds to store as many bits as are required by
-- the response packet. Each message bit passes through the CRC7 circuit so that
-- the CRC check sum can be verified at the end of transmission. The circuit then produces
-- the o_data and o_CRC_passed outputs to indicate the message received and if the CRC
-- check passed.
--
-- If for some reason the requested response does not arrive within 56 clock cycles
-- then the circuit will produce a '1' on the o_timeout output. In such a case the
-- o_data should be ignored.
--
-- In case of a response that is not 001, 010, 011 or 110, the circuit expects
-- no response.
--
-- A signal o_done is asserted when the circuit has completed response retrieval. In
-- a case when a response is not expected, just wait for the CD Card to process the
-- command. This is done by waiting 8 (=PROCESSING_DELAY) clock cycles.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Response_Receiver is
generic (
TIMEOUT : std_logic_vector(7 downto 0) := "00111000";
BUSY_WAIT : std_logic_vector(7 downto 0) := "00110000";
PROCESSING_DELAY : std_logic_vector(7 downto 0) := "00001000"
);
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_begin : in std_logic;
i_scan_pulse : in std_logic;
i_datain : in std_logic;
i_wait_cmd_busy : in std_logic;
i_response_type : in std_logic_vector(2 downto 0);
o_data : out std_logic_vector(127 downto 0);
o_CRC_passed : out std_logic;
o_timeout : out std_logic;
o_done : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Response_Receiver is
component Altera_UP_SD_CRC7_Generator
port
(
i_clock : in std_logic;
i_enable : in std_logic;
i_reset_n : in std_logic;
i_shift : in std_logic;
i_datain : in std_logic;
o_dataout : out std_logic;
o_crcout : out std_logic_vector(6 downto 0)
);
end component;
-- Build an enumerated type for the state machine. On reset always reset the DE2 and read the state
-- of the switches.
type state_type is (s_WAIT_BEGIN, s_WAIT_END, s_WAIT_PROCESSING_DELAY, s_WAIT_BUSY, s_WAIT_BUSY_END, s_WAIT_BEGIN_DEASSERT);
-- Register to hold the current state
signal current_state : state_type;
signal next_state : state_type;
-- Local wires
-- REGISTERED
signal registered_data_input : std_logic_vector(127 downto 0);
signal response_incoming : std_logic;
signal counter, timeout_counter : std_logic_vector(7 downto 0);
signal crc_shift, keep_reading_bits, shift_crc_bits : std_logic;
-- UNREGISTERED
signal limit, limit_minus_1 : std_logic_vector(7 downto 0);
signal check_crc : std_logic;
signal CRC_bits : std_logic_vector(6 downto 0);
signal start_reading_bits, operation_complete, enable_crc_unit : std_logic;
begin
-- Control FSM. Begin operation when i_begin is raised, then wait for the operation to end and i_begin to be deasserted.
state_regs: process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
current_state <= s_WAIT_BEGIN;
elsif (rising_edge(i_clock)) then
current_state <= next_state;
end if;
end process;
state_transitions: process(current_state, i_begin, operation_complete, timeout_counter, i_wait_cmd_busy, i_scan_pulse, i_datain)
begin
case current_state is
when s_WAIT_BEGIN =>
if (i_begin = '1') then
next_state <= s_WAIT_END;
else
next_state <= s_WAIT_BEGIN;
end if;
when s_WAIT_END =>
if (operation_complete = '1') then
if (timeout_counter = TIMEOUT) then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_PROCESSING_DELAY;
end if;
else
next_state <= s_WAIT_END;
end if;
when s_WAIT_PROCESSING_DELAY =>
if (timeout_counter = PROCESSING_DELAY) then
if (i_wait_cmd_busy = '1') then
next_state <= s_WAIT_BUSY;
else
next_state <= s_WAIT_BEGIN_DEASSERT;
end if;
else
next_state <= s_WAIT_PROCESSING_DELAY;
end if;
when s_WAIT_BUSY =>
if ((i_scan_pulse = '1') and (i_datain = '0')) then
next_state <= s_WAIT_BUSY_END;
else
if (timeout_counter = BUSY_WAIT) then
-- If the card did not become busy, then it would not have raised the optional busy signal.
-- In such a case, proceeed further as the command has finished correctly.
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BUSY;
end if;
end if;
when s_WAIT_BUSY_END =>
if ((i_scan_pulse = '1') and (i_datain = '1')) then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BUSY_END;
end if;
when s_WAIT_BEGIN_DEASSERT =>
if (i_begin = '1') then
next_state <= s_WAIT_BEGIN_DEASSERT;
else
next_state <= s_WAIT_BEGIN;
end if;
when others =>
next_state <= s_WAIT_BEGIN;
end case;
end process;
-- Store the response as it appears on the i_datain line.
received_data_buffer: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
registered_data_input <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Only read new data and update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
registered_data_input(127 downto 1) <= registered_data_input(126 downto 0);
registered_data_input(0) <= i_datain;
end if;
end if;
end if;
end process;
-- Counter received bits
data_read_counter: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Reset he counter every time you being reading the response.
if (current_state = s_WAIT_BEGIN) then
counter <= (OTHERS => '0');
end if;
-- Update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
counter <= counter + '1';
end if;
end if;
end if;
end process;
operation_complete <= '1' when (((counter = limit) and (not (limit = "00000000"))) or
(timeout_counter = TIMEOUT) or
((timeout_counter = PROCESSING_DELAY) and (limit = "00000000"))) else '0';
-- Count the number of scan pulses before the response is received. If the counter
-- exceeds TIMEOUT value, then an error must have occured when the SD card received a message.
timeout_counter_control: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
timeout_counter <= (OTHERS=>'0');
elsif (rising_edge(i_clock)) then
-- Reset the counter every time you begin reading the response.
if ((current_state = s_WAIT_BEGIN) or ((current_state = s_WAIT_END) and (operation_complete = '1') and (not (timeout_counter = TIMEOUT)))) then
timeout_counter <= (OTHERS => '0');
end if;
-- Update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if (((start_reading_bits = '0') and (keep_reading_bits = '0') and (current_state = s_WAIT_END) and (not (timeout_counter = TIMEOUT))) or
(current_state = s_WAIT_PROCESSING_DELAY) or (current_state = s_WAIT_BUSY)) then
timeout_counter <= timeout_counter + '1';
end if;
end if;
end if;
end process;
-- Enable data storing only after you see the first 0.
read_enable_logic: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
keep_reading_bits <= '0';
elsif (rising_edge(i_clock)) then
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or ((keep_reading_bits = '1') and (not (counter = limit_minus_1)))) then
keep_reading_bits <= '1';
else
keep_reading_bits <= '0';
end if;
end if;
end if;
end process;
start_reading_bits <= '1' when ((current_state = s_WAIT_END) and (i_datain = '0') and
(counter = "00000000") and (not (limit = "00000000"))) else '0';
-- CRC7 checker.
crc_checker: Altera_UP_SD_CRC7_Generator PORT MAP
(
i_clock => i_clock,
i_reset_n => i_reset_n,
i_enable => enable_crc_unit,
i_shift => shift_crc_bits,
i_datain => registered_data_input(7),
o_crcout => CRC_bits
);
enable_crc_unit <= '1' when ((i_scan_pulse = '1') and (current_state = s_WAIT_END)) else '0';
-- Clear CRC7 registers before processing the response bits
crc_control_register: process (i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
shift_crc_bits <= '1';
elsif (rising_edge(i_clock)) then
-- Reset he counter every time you being reading the response.
if (current_state = s_WAIT_BEGIN) then
-- clear the CRC7 contents before you process the next message.
shift_crc_bits <= '1';
end if;
-- Only read new data and update the counter value when the scan pulse is high.
if (i_scan_pulse = '1') then
if ((start_reading_bits = '1') or (keep_reading_bits = '1')) then
if (counter = "00000111") then
-- Once the 7-bits of the CRC checker have been cleared you can process the message and
-- compute its CRC bits to verify the validity of the transmission.
shift_crc_bits <= '0';
end if;
end if;
end if;
end if;
end process;
-- Indicate the number of bits to expect in the response packet.
limit <= "00110000" when ((i_response_type = "001") or
(i_response_type = "011") or
(i_response_type = "110")) else
"10001000" when (i_response_type = "010") else
"00000000"; -- No response
limit_minus_1 <=
"00101111" when ((i_response_type = "001") or
(i_response_type = "011") or
(i_response_type = "110")) else
"10000111" when (i_response_type = "010") else
"00000000"; -- No response
check_crc <= '1' when ((i_response_type = "001") or (i_response_type = "110")) else '0';
-- Generate Circuit outputs
o_data <= (registered_data_input(127 downto 1) & '1') when (i_response_type = "010") else
(CONV_STD_LOGIC_VECTOR(0, 96) & registered_data_input(39 downto 8));
o_CRC_passed <= '1' when ((check_crc = '0') or
((registered_data_input(0) = '1') and (CRC_bits = registered_data_input(7 downto 1)))) else '0';
o_timeout <= '1' when (timeout_counter = TIMEOUT) else '0';
o_done <= '1' when (current_state = s_WAIT_BEGIN_DEASSERT) else '0';
end rtl; | mit | 937a3cb59cb6edb527df58e4775c7aff | 0.63446 | 3.090621 | false | false | false | false |
imr/Mandelbrot-VHDL | src/Control.vhd | 1 | 4,532 | -- Ian Roth
-- ECE 8455
-- control logic, final project
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.fixed_pkg.all;
ENTITY Control IS
PORT(
clk, rst :IN STD_LOGIC;
Zoom, ZoomX, ZoomY :IN STD_LOGIC;
x_const, y_const :OUT STD_LOGIC_VECTOR(35 downto 0);
x_addr, y_addr, w_addr :OUT STD_LOGIC_VECTOR(9 downto 0);
WE_const, WE :OUT STD_LOGIC
);
END ENTITY Control;
ARCHITECTURE Behavior OF Control IS
TYPE state_type IS (A,B,C,D,E,F,G);
SIGNAL cur_state :state_type;
SIGNAL x_counter :UNSIGNED(9 downto 0);
SIGNAL y_counter :UNSIGNED(9 downto 0);
SIGNAL w_counter :UNSIGNED(9 downto 0);
SIGNAL pixel_counter :UNSIGNED(19 downto 0);
SIGNAL x_com_min, x_com_max, y_com_min, y_com_max, x_span, y_span :sfixed(3 downto -32);
SIGNAL h_pixel, w_pixel, h_npixel, w_npixel, x_int_const, y_int_const :sfixed(3 downto -32);
SIGNAL iteration_counter :UNSIGNED(15 downto 0);
CONSTANT x_size :sfixed(10 downto 0) := "10000000000"; -- 1024
CONSTANT y_size :sfixed(10 downto 0) := "01100000000"; -- 768
BEGIN
x_const <= STD_LOGIC_VECTOR(x_int_const);
y_const <= STD_LOGIC_VECTOR(y_int_const);
x_addr <= STD_LOGIC_VECTOR(x_counter);
y_addr <= STD_LOGIC_VECTOR(y_counter);
w_addr <= STD_LOGIC_VECTOR(w_counter);
w_npixel <= resize((x_span sra 1) / x_size, w_npixel);
h_npixel <= resize((y_span sra 1) / y_size, h_npixel);
PROCESS(clk, rst)
BEGIN
IF (clk'EVENT and clk = '1') THEN
IF (rst = '1') THEN
x_com_min <= to_sfixed(-2, x_com_min);
x_com_max <= to_sfixed(1, x_com_max);
y_com_min <= to_sfixed(-1, y_com_min);
y_com_max <= to_sfixed(1, y_com_max);
x_int_const <= to_sfixed(-2, x_int_const);
y_int_const <= to_sfixed(1, y_int_const);
w_pixel <= to_sfixed(0.0029296875, w_pixel);
h_pixel <= to_sfixed(0.0026146667, h_pixel);
x_span <= to_sfixed(4, x_span);
y_span <= to_sfixed(2, y_span);
WE_const <= '1';
WE <= '0';
cur_state <= A;
ELSE
CASE cur_state IS
WHEN A =>
x_counter <= "0000000000";
y_counter <= "0000000000";
w_counter <= "0000000000";
pixel_counter <= X"00000";
WE_const <= '1';
WE <= '0';
cur_state <= B;
WHEN B => -- Load first constants for complex x y plane
x_int_const <= resize(x_int_const + w_pixel, x_int_const);
y_int_const <= resize(y_int_const - h_pixel, y_int_const);
w_counter <= w_counter + 1;
WE_const <= '1';
WE <= '0';
cur_state <= C;
WHEN C => -- Start Pipeline, 23 (pipeline length) cycles
x_int_const <= resize(x_int_const + w_pixel, x_int_const);
y_int_const <= resize(y_int_const - h_pixel, y_int_const);
w_counter <= w_counter + 1;
WE_const <= '1';
WE <= '0';
x_counter <= x_counter + 1;
IF (x_counter = 22) THEN
cur_state <= D;
END IF;
WHEN D => -- Write into memory
x_int_const <= resize(x_int_const + w_pixel, x_int_const);
y_int_const <= resize(y_int_const - h_pixel, y_int_const);
w_counter <= w_counter + 1;
WE_const <= '1';
WE <= '1';
x_counter <= x_counter + 1;
pixel_counter <= pixel_counter + 1; -- Actual written pixels
IF (w_counter = 1022) THEN
cur_state <= E;
END IF;
WHEN E => -- Stop constants
WE_const <= '0';
WE <= '1';
x_counter <= x_counter + 1;
pixel_counter <= pixel_counter + 1; -- Actual written pixels
IF (x_counter = 1023) THEN
y_counter <= y_counter + 1;
ELSE
y_counter <= y_counter;
END IF;
IF (pixel_counter = X"BFFFF") THEN
cur_state <= F;
END IF;
WHEN F => -- Stop writing to memory
WE_const <= '0';
WE <= '0';
IF (Zoom = '0') THEN
IF (ZoomX = '0') THEN -- Zoom in on right
x_com_min <= resize(x_com_min + (x_span sra 1), x_com_min);
ELSE
x_com_max <= resize(x_com_max - (x_span sra 1), x_com_max);
END IF;
IF (ZoomY = '0') THEN -- Zoom in on top
y_com_min <= resize(y_com_min + (y_span sra 1), x_com_min);
ELSE
y_com_max <= resize(y_com_max - (y_span sra 1), x_com_max);
END IF;
w_pixel <= w_npixel;
h_pixel <= h_npixel;
x_span <= x_span sra 1;
y_span <= y_span sra 1;
cur_state <= G;
END IF;
WHEN G =>
x_int_const <= x_com_min;
y_int_const <= y_com_max;
IF (Zoom = '1') THEN
cur_state <= A;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
END Behavior; | bsd-3-clause | 051e578c869784b89653218c1f22be0f | 0.563107 | 2.659624 | false | false | false | false |
terpstra/opa | opa_decode.vhd | 1 | 20,004 | -- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_isa_base_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
use work.opa_isa_pkg.all;
entity opa_decode is
generic(
g_isa : t_opa_isa;
g_config : t_opa_config;
g_target : t_opa_target);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Predicted jumps?
predict_hit_i : in std_logic;
predict_jump_i : in std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
-- Push a return stack entry
predict_push_o : out std_logic;
predict_ret_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Fixup PC to new target
predict_fault_o : out std_logic;
predict_return_o : out std_logic;
predict_jump_o : out std_logic_vector(f_opa_fetchers(g_config)-1 downto 0);
predict_source_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
predict_target_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
predict_return_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Instructions delivered from icache
icache_stb_i : in std_logic;
icache_stall_o : out std_logic;
icache_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
icache_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
icache_dat_i : in std_logic_vector(f_opa_fetch_bits(g_isa,g_config)-1 downto 0);
-- Feed data to the renamer
rename_stb_o : out std_logic;
rename_stall_i : in std_logic;
rename_fast_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_slow_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_order_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_setx_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_geta_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_getb_o : out std_logic_vector(f_opa_renamers(g_config)-1 downto 0);
rename_aux_o : out std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
rename_archx_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
rename_archa_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
rename_archb_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arch_wide(g_isa)-1 downto 0);
-- Accept faults
rename_fault_i : in std_logic;
rename_pc_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
rename_pcf_i : in std_logic_vector(f_opa_fet_wide(g_config)-1 downto 0);
rename_pcn_i : in std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
-- Give the regfile the information EUs will need for these operations
regfile_stb_o : out std_logic;
regfile_aux_o : out std_logic_vector(f_opa_aux_wide(g_config)-1 downto 0);
regfile_arg_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_arg_wide(g_config)-1 downto 0);
regfile_imm_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_imm_wide(g_isa) -1 downto 0);
regfile_pc_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa));
regfile_pcf_o : out t_opa_matrix(f_opa_renamers(g_config)-1 downto 0, f_opa_fet_wide(g_config)-1 downto 0);
regfile_pcn_o : out std_logic_vector(f_opa_adr_wide(g_config)-1 downto f_opa_op_align(g_isa)));
end opa_decode;
architecture rtl of opa_decode is
constant c_big_endian:boolean := f_opa_big_endian(g_isa);
constant c_op_align : natural := f_opa_op_align(g_isa);
constant c_op_wide : natural := f_opa_op_wide (g_isa);
constant c_imm_wide : natural := f_opa_imm_wide(g_isa);
constant c_arch_wide: natural := f_opa_arch_wide(g_isa);
constant c_fetchers : natural := f_opa_fetchers(g_config);
constant c_renamers : natural := f_opa_renamers(g_config);
constant c_buffers : natural := c_fetchers + 2*c_renamers - 1;
constant c_num_aux : natural := f_opa_num_aux (g_config);
constant c_adr_wide : natural := f_opa_adr_wide(g_config);
constant c_fet_wide : natural := f_opa_fet_wide(g_config);
constant c_buf_wide : natural := f_opa_log2(c_buffers+1); -- [0, c_buffers] inclusive
constant c_aux_wide : natural := f_opa_aux_wide(g_config);
constant c_fetch_align : natural := f_opa_fetch_align(g_isa,g_config);
constant c_min_imm_pc : natural := f_opa_choose(c_imm_wide<c_adr_wide, c_imm_wide, c_adr_wide);
type t_op_array is array(natural range <>) of t_opa_op;
type t_pc_array is array(natural range <>) of std_logic_vector(c_adr_wide-1 downto c_op_align);
type t_pcf_array is array(natural range <>) of std_logic_vector(c_fet_wide-1 downto 0);
function f_flip(x : natural) return natural is
begin
if c_big_endian then
return c_fetchers-1-x;
else
return x;
end if;
end f_flip;
signal s_pc_off : unsigned(c_fet_wide-1 downto 0);
signal s_ops_in : t_op_array(c_fetchers-1 downto 0);
signal s_pc_in : t_pc_array(c_fetchers-1 downto 0);
signal s_immb_in : t_pc_array(c_fetchers-1 downto 0);
signal s_pred_in : t_pc_array(c_fetchers-1 downto 0);
signal s_mask_skip : std_logic_vector(c_fetchers-1 downto 0);
signal s_mask_tail : std_logic_vector(c_fetchers-1 downto 0);
signal s_jump : std_logic_vector(c_fetchers-1 downto 0);
signal s_take : std_logic_vector(c_fetchers-1 downto 0);
signal s_force : std_logic_vector(c_fetchers-1 downto 0);
signal s_push : std_logic_vector(c_fetchers-1 downto 0);
signal s_pop : std_logic_vector(c_fetchers-1 downto 0);
signal s_hit : std_logic_vector(c_fetchers-1 downto 0);
signal s_bad_jump : std_logic_vector(c_fetchers-1 downto 0);
signal s_use_static : std_logic;
signal r_use_static : std_logic := '0';
signal s_static_jumps : std_logic_vector(c_fetchers-1 downto 0);
signal s_static_jump : std_logic_vector(c_fetchers-1 downto 0);
signal s_static_targets: t_opa_matrix(c_fetchers-1 downto 0, c_adr_wide-1 downto c_op_align);
signal s_static_target : std_logic_vector(c_adr_wide-1 downto c_op_align);
signal s_rename_jump : std_logic_vector(c_fetchers-1 downto 0);
signal s_rename_source : std_logic_vector(c_adr_wide-1 downto c_op_align);
signal s_jump_taken : std_logic_vector(c_fetchers-1 downto 0);
signal s_ret_taken : std_logic;
signal s_pcn_taken : std_logic_vector(c_adr_wide-1 downto c_op_align);
signal r_pcn_taken : std_logic_vector(c_adr_wide-1 downto c_op_align);
signal s_jal_pc : std_logic_vector(c_adr_wide-1 downto c_op_align);
signal s_ops : t_op_array (c_buffers-1 downto 0);
signal r_ops : t_op_array (c_buffers-1 downto 0);
signal s_pc : t_pc_array (c_buffers-1 downto 0);
signal r_pc : t_pc_array (c_buffers-1 downto 0);
signal s_pcf : t_pcf_array(c_buffers-1 downto 0);
signal r_pcf : t_pcf_array(c_buffers-1 downto 0);
signal s_stb : std_logic;
signal s_stall : std_logic;
signal s_pcn_reg : std_logic;
signal s_progress : std_logic;
signal s_accept : std_logic;
signal s_ops_sub : unsigned(c_fet_wide-1 downto 0);
signal r_fill : unsigned(c_buf_wide-1 downto 0) := (others => '0');
signal r_aux : unsigned(c_aux_wide-1 downto 0) := (others => '0');
begin
check : process(clk_i) is
begin
if rising_edge(clk_i) then
-- control inputs (safe for when/if)
assert (f_opa_safe(predict_hit_i) = '1') report "decode: predict_hit_i has metavalue" severity failure;
assert (f_opa_safe(predict_jump_i) = '1') report "decode: predict_jump_i has metavalue" severity failure;
assert (f_opa_safe(icache_stb_i) = '1') report "decode: icache_stb_i has metavalue" severity failure;
assert (f_opa_safe(rename_stall_i) = '1') report "decode: rename_stall_i has metavalue" severity failure;
assert (f_opa_safe(rename_fault_i) = '1') report "decode: rename_fault_i has metavalue" severity failure;
-- combinatorial control (safe for when/if)
assert (f_opa_safe(s_stall) = '1') report "decode: s_stall has metavalue" severity failure;
assert (f_opa_safe(s_stb) = '1') report "decode: s_stb has metavalue" severity failure;
assert (f_opa_safe(s_pcn_reg) = '1') report "decode: s_pcn_reg has metavalue" severity failure;
assert (f_opa_safe(s_progress) = '1') report "decode: s_progress has metavalue" severity failure;
assert (f_opa_safe(s_accept) = '1') report "decode: s_accept has metavalue" severity failure;
-- registered control
assert (f_opa_safe(r_use_static) = '1') report "decode: r_use_static has metavalue" severity failure;
assert (f_opa_safe(r_fill) = '1') report "decode: r_fill has metavalue" severity failure;
assert (f_opa_safe(r_aux) = '1') report "decode: r_aux has metavalue" severity failure;
end if;
end process;
-- Decode the flow control information from the instructions
off1p : if c_fetchers > 1 generate
s_pc_off <= unsigned(icache_pc_i(c_fetch_align-1 downto c_op_align));
s_ops_sub <= unsigned(f_opa_1hot_dec(f_opa_reverse(s_jump_taken))) + s_pc_off;
end generate;
off1 : if c_fetchers = 1 generate
s_pc_off <= "0";
s_ops_sub <= "0";
end generate;
s_mask_tail(0) <= '0';
decode : for i in 0 to c_fetchers-1 generate
s_ops_in(i) <= f_opa_isa_decode(g_isa, g_config, icache_dat_i((f_flip(i)+1)*c_op_wide-1 downto f_flip(i)*c_op_wide));
fet1 : if c_fetchers = 1 generate
s_pc_in(i) <= icache_pc_i(c_adr_wide-1 downto c_fetch_align);
end generate;
fet1p : if c_fetchers > 1 generate
s_pc_in(i) <= icache_pc_i(c_adr_wide-1 downto c_fetch_align) & std_logic_vector(to_unsigned(i, c_fet_wide));
end generate;
s_immb_in(i)(c_min_imm_pc-2 downto c_op_align) <= s_ops_in(i).immb(c_min_imm_pc-2 downto c_op_align);
s_immb_in(i)(c_adr_wide-1 downto c_min_imm_pc-1) <= (others => s_ops_in(i).immb(c_min_imm_pc-1));
s_pred_in(i) <= std_logic_vector(unsigned(s_pc_in(i)) + unsigned(s_immb_in(i)));
s_mask_skip(i) <= f_opa_lt(i, s_pc_off); -- Unused ops before loaded PC
tail : if i > 0 generate
s_mask_tail(i) <= s_mask_tail(i-1) or predict_jump_i(i-1); -- Ops following a taken jump
end generate;
s_jump(i) <= s_ops_in(i).jump;
s_take(i) <= s_ops_in(i).take;
s_force(i) <= s_ops_in(i).force;
s_pop(i) <= s_ops_in(i).pop;
s_push(i) <= s_ops_in(i).push;
end generate;
-- Decide if we want to accept the fetch prediction
s_hit <= (others => predict_hit_i);
s_bad_jump <= ((not s_jump and predict_jump_i) or
(s_force and not predict_jump_i) or
(s_take and not s_hit))
and not s_mask_skip and not s_mask_tail;
s_use_static <= f_opa_or(s_bad_jump);
-- What is our prediction?
s_static_jumps<= s_take and not s_mask_skip; -- need to assign valid range before picking
s_static_jump <= f_opa_pick_small(s_static_jumps);
targets : for d in 0 to c_fetchers-1 generate
bits : for b in c_op_align to c_adr_wide-1 generate
s_static_targets(d,b) <= s_pred_in(d)(b);
end generate;
end generate;
s_static_target <= f_opa_product(f_opa_transpose(s_static_targets), s_static_jump);
s_jump_taken <= f_opa_mux(s_use_static, s_static_jump, predict_jump_i);
s_ret_taken <= f_opa_or(s_pop and s_static_jump);
-- pcn MUST be what gets loaded next, b/c instructions compare against it.
-- if issue faults, all this gets blown away, so that doesn't matter
-- if there is no fault, the usual prediction goes through the pipeline
-- if decode faults, then we need to pick whatever the predictor picks!
-- the predictor will always go where we tell it, except for a return.
s_pcn_taken <=
f_opa_mux(s_use_static,
f_opa_mux(s_ret_taken, predict_return_i, s_static_target),
icache_pcn_i);
-- Decode renamer's fault information
s_rename_source(c_adr_wide-1 downto c_fetch_align) <= rename_pc_i(c_adr_wide-1 downto c_fetch_align);
src_fet1p : if c_fetchers > 1 generate
s_rename_source(c_fetch_align-1 downto c_op_align) <= rename_pcf_i;
jumps : for i in 0 to c_fetchers-1 generate
s_rename_jump(i) <= f_opa_eq(unsigned(rename_pc_i(c_fetch_align-1 downto c_op_align)), i);
end generate;
end generate;
src_fet1 : if c_fetchers = 1 generate
s_rename_jump <= "1";
end generate;
-- Feed back information to fetch
predict_fault_o <= (s_use_static and s_accept) or rename_fault_i;
predict_return_o <= s_accept and not rename_fault_i and s_ret_taken;
predict_jump_o <= s_rename_jump when rename_fault_i='1' else s_static_jump;
predict_source_o <= s_rename_source when rename_fault_i='1' else icache_pc_i;
predict_target_o <= rename_pcn_i when rename_fault_i='1' else s_static_target;
-- Do we need to push the PC?
s_jal_pc(c_adr_wide -1 downto c_fetch_align) <= icache_pc_i(c_adr_wide-1 downto c_fetch_align);
subpc : if c_fetchers > 1 generate
s_jal_pc(c_fetch_align-1 downto c_op_align) <= f_opa_1hot_dec(s_jump_taken);
end generate;
predict_push_o <= f_opa_or(s_push and s_jump_taken) and s_accept;
predict_ret_o <= std_logic_vector(1 + unsigned(s_jal_pc));
-- Flow control from fetch and to rename
s_stall <= '1' when r_fill >= 2*c_renamers else '0';
s_stb <= '1' when r_fill >= c_renamers else '0';
s_pcn_reg <= '1' when r_fill = c_renamers else '0';
s_progress <= s_stb and not rename_stall_i;
s_accept <= icache_stb_i and not r_use_static and not s_stall;
-- Select the new buffer fill state
buf1p : if c_fetchers > 1 generate
index : block is
type t_idx_array is array(natural range <>) of unsigned(c_fet_wide-1 downto 0);
signal s_idx_base : unsigned(c_fet_wide-1 downto 0);
signal s_idx : t_idx_array(c_buffers-1 downto 0);
begin
s_idx_base <= s_pc_off - r_fill(s_idx_base'range);
ops : for i in 0 to c_buffers-1 generate
s_idx(i) <= s_idx_base + to_unsigned(i mod c_fetchers, c_fet_wide);
s_ops(i) <= r_ops(i) when i < r_fill else s_ops_in(to_integer(s_idx(i))) when f_opa_safe(s_idx(i))='1' else c_opa_op_undef;
s_pc (i) <= r_pc (i) when i < r_fill else s_pc_in (to_integer(s_idx(i))) when f_opa_safe(s_idx(i))='1' else (others => 'X');
s_pcf(i) <= r_pcf(i) when i < r_fill else icache_pc_i(c_fetch_align-1 downto c_op_align);
end generate;
end block;
end generate;
buf1 : if c_fetchers = 1 generate
ops : for i in 0 to c_buffers-1 generate
s_ops(i) <= r_ops(i) when i < r_fill else s_ops_in(0);
s_pc (i) <= r_pc (i) when i < r_fill else s_pc_in (0);
s_pcf(i) <= "0";
end generate;
end generate;
fill : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_use_static <= '0';
r_fill <= (others => '0');
elsif rising_edge(clk_i) then
if rename_fault_i = '1' then
r_use_static <= '1';
r_fill <= (others => '0');
else
-- On a static predicition, we ignore the next valid icache strobe
if (icache_stb_i and not s_stall) = '1' then
if r_use_static = '1' then
r_use_static <= '0';
else
r_use_static <= s_use_static;
end if;
end if;
if s_progress = '1' then
if s_accept = '1' then
r_fill <= (r_fill + c_fetchers) - c_renamers - s_ops_sub;
else
r_fill <= r_fill - c_renamers;
end if;
else
if s_accept = '1' then
r_fill <= (r_fill + c_fetchers) - s_ops_sub;
else
r_fill <= r_fill;
end if;
end if;
end if;
end if;
end process;
aux : process(clk_i, rst_n_i) is
begin
if rst_n_i = '0' then
r_aux <= (others => '0');
elsif rising_edge(clk_i) then
if s_progress = '1' then
if r_aux = c_num_aux-1 then
r_aux <= (others => '0');
else
r_aux <= r_aux+1;
end if;
end if;
end if;
end process;
main : process(clk_i) is
begin
if rising_edge(clk_i) then
if s_progress = '1' then
r_ops(c_buffers-c_renamers-1 downto 0) <= s_ops(c_buffers-1 downto c_renamers);
r_pcf(c_buffers-c_renamers-1 downto 0) <= s_pcf(c_buffers-1 downto c_renamers);
r_pc (c_buffers-c_renamers-1 downto 0) <= s_pc (c_buffers-1 downto c_renamers);
else
r_ops <= s_ops;
r_pcf <= s_pcf;
r_pc <= s_pc;
end if;
end if;
end process;
latch_pcn : process(clk_i) is
begin
if rising_edge(clk_i) then
if s_accept = '1' then
r_pcn_taken <= s_pcn_taken;
end if;
end if;
end process;
icache_stall_o <= s_stall and not rename_fault_i;
rename_stb_o <= s_stb;
rename_aux_o <= std_logic_vector(r_aux);
ops_out : for d in 0 to c_renamers-1 generate
rename_fast_o (d) <= r_ops(d).fast;
rename_slow_o (d) <= not r_ops(d).fast;
rename_order_o(d) <= r_ops(d).order;
rename_setx_o (d) <= r_ops(d).setx;
rename_geta_o (d) <= r_ops(d).geta;
rename_getb_o (d) <= r_ops(d).getb;
bits : for b in 0 to c_arch_wide-1 generate
rename_archx_o(d,b) <= r_ops(d).archx(b);
rename_archa_o(d,b) <= r_ops(d).archa(b);
rename_archb_o(d,b) <= r_ops(d).archb(b);
end generate;
end generate;
regfile_stb_o <= s_stb;
regfile_aux_o <= std_logic_vector(r_aux);
rf_out : for d in 0 to c_renamers-1 generate
arg : for b in 0 to c_arg_wide-1 generate
regfile_arg_o(d,b) <= f_opa_vec_from_arg(r_ops(d).arg)(b);
end generate;
imm : for b in 0 to c_imm_wide-1 generate
regfile_imm_o(d,b) <= r_ops(d).imm(b);
end generate;
pc : for b in c_op_align to c_adr_wide-1 generate
regfile_pc_o(d,b) <= r_pc(d)(b);
end generate;
pcf : for b in 0 to c_fet_wide-1 generate
regfile_pcf_o(d,b) <= r_pcf(d)(b);
end generate;
end generate;
pcn : for b in c_op_align to c_adr_wide-1 generate
regfile_pcn_o(b) <= r_pcn_taken(b) when s_pcn_reg='1' else r_pc(c_renamers)(b);
end generate;
end rtl;
| gpl-3.0 | 6ceed56dc989d05a3e44d1a8f289718f | 0.627824 | 2.822633 | false | true | false | false |
Xion345/fpga-projects | library/uart/uart_rx.vhd | 1 | 3,309 | -- UART Receiver
-- 20/07/2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
port(
clk, reset: in std_logic; -- Clock and reset
rx: in std_logic; -- UART RX (Receive) pin
baud16_tick: in std_logic; -- 16x oversampled baud tick
data_out: out std_logic_vector(7 downto 0); -- Received data byte
rx_done_tick: out std_logic -- Receive done tick
);
end uart_rx;
architecture uart_rx_arch of uart_rx is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type; -- State register
signal data_reg, data_next: std_logic_vector(7 downto 0); -- Data register
signal remaining_reg, remaining_next: unsigned(2 downto 0); -- Remaining bits
signal ticks_reg, ticks_next: unsigned(3 downto 0); -- Ticks count (oversampling)
begin
-- State and data registers
process(clk, reset)
begin
if reset='1' then
state_reg <= idle;
ticks_reg <= (others => '0');
remaining_reg <= (others => '0');
data_reg <= (others => '0');
elsif rising_edge(clk) then
state_reg <= state_next;
ticks_reg <= ticks_next;
remaining_reg <= remaining_next;
data_reg <= data_next;
end if;
end process;
-- Next state logic and data path
process(state_reg, ticks_reg, remaining_reg, data_reg, baud16_tick, rx)
begin
state_next <= state_reg;
ticks_next <= ticks_reg;
remaining_next <= remaining_reg;
data_next <= data_reg;
rx_done_tick <= '0';
case state_reg is
--
when idle =>
if rx = '0' then
state_next <= start;
ticks_next <= (others => '0');
end if;
--
when start =>
if baud16_tick = '1' then
if ticks_reg=7 then
state_next <= data;
ticks_next <= (others => '0');
remaining_next <= (others => '0');
else
ticks_next <= ticks_reg + 1;
end if;
end if;
--
when data =>
if baud16_tick = '1' then
if ticks_reg=15 then -- Move to next byte
ticks_next <= (others => '0');
data_next <= rx & data_reg(7 downto 1);
if remaining_reg = 7 then -- Last byte ?
state_next <= stop;
else
remaining_next <= remaining_reg + 1;
end if;
else
ticks_next <= ticks_reg + 1;
end if;
end if;
--
when stop =>
if baud16_tick = '1' then
if ticks_reg=15 then
state_next <= idle;
rx_done_tick <= '1';
else
ticks_next <= ticks_reg + 1;
end if;
end if;
end case;
end process;
data_out <= data_reg;
end uart_rx_arch;
| mit | 1aacee74bea18720ab35ebc89c2cf33b | 0.453309 | 4.331152 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/parte_controllo_complex_abs.vhd | 1 | 2,475 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:25:37 06/26/2017
-- Design Name:
-- Module Name: parte_controllo_complex_abs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity parte_controllo_complex_abs is
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
enable : in STD_LOGIC;
done_mul : in STD_LOGIC;
reset_n_all : out STD_LOGIC;
enable_mul : out STD_LOGIC;
done : out STD_LOGIC);
end parte_controllo_complex_abs;
architecture Behavioral of parte_controllo_complex_abs is
type state is (reset, waiting_mul, add, op_done);
signal current_state, next_state : state := reset;
begin
registro_stato : process(clock, reset_n)
begin
if(reset_n = '0') then
current_state <= reset;
elsif(clock = '1' and clock'event) then
current_state <= next_state;
end if;
end process;
fsm_next_state : process(current_state, reset_n, done_mul, enable)
begin
case current_state is
when reset =>
if(enable = '1') then
next_state <= waiting_mul;
else
next_state <= reset;
end if;
when waiting_mul =>
if(done_mul = '1') then
next_state <= add;
else
next_state <= waiting_mul;
end if;
when add =>
next_state <= op_done;
when op_done =>
next_state <= reset;
end case;
end process;
fsm_output : process(current_state)
begin
enable_mul <= '0';
reset_n_all <= '1';
done <= '0';
case current_state is
when reset =>
reset_n_all <= '0';
when waiting_mul =>
enable_mul <= '1';
when add =>
when op_done =>
done <= '1';
end case;
end process;
end Behavioral;
| gpl-2.0 | 705ff8cba2d23c99f405f7317151b898 | 0.541818 | 3.867188 | false | false | false | false |
freecores/grain | src/VHDL/test_synth/hw1_grain.vhd | 1 | 836 | --
-- synthesis test 1:
-- * with clock enable
-- * slow
--
--
-- Altera EP2C-8, Quartus 8.0: 195 LEs, 0 memory bits, fmax = 204 MHz (320 requested)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity hw1_grain is
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INIT_I: in std_logic;
KEYSTREAM_O : out std_logic;
KEYSTREAM_VALID_O : out std_logic
);
end entity;
architecture behav of hw1_grain is
begin
top: entity work.grain
generic map (
DEBUG => false,
FAST => false
)
port map (
CLK_I => CLK_I,
CLKEN_I => CLKEN_I,
ARESET_I => ARESET_I,
KEY_I => KEY_I,
IV_I => IV_I,
INIT_I=> INIT_I,
KEYSTREAM_O => KEYSTREAM_O,
KEYSTREAM_VALID_O => KEYSTREAM_VALID_O
);
end behav;
| lgpl-3.0 | 193f697fed67a677a80a8e0a15fdabed | 0.616029 | 2.473373 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/compute_max/fsm_compute_max.vhd | 1 | 3,713 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 16:36:50
-- Design Name:
-- Module Name: fsm_compute_max - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm_compute_max is
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
max_done : in STD_LOGIC;
start : out STD_LOGIC;
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC;
reset_n_all : out STD_LOGIC);
end fsm_compute_max;
architecture Behavioral of fsm_compute_max is
type state is (reset, waiting_for_valid_in, elaboration, done, waiting_for_ready_in, waiting_1, waiting_2, waiting_3, waiting_4);
signal current_state, next_state : state := reset;
begin
registro_stato : process(clock, reset_n, next_state)
begin
if(reset_n = '0') then
current_state <= reset;
elsif(rising_edge(clock)) then
current_state <= next_state;
end if;
end process;
fsm_next_state : process(current_state, reset_n, valid_in, ready_in, max_done)
begin
case current_state is
when reset =>
if(reset_n = '0')then
next_state <= reset;
else
next_state <= waiting_for_valid_in;
end if;
when waiting_for_valid_in =>
if(valid_in = '0')then
next_state <= waiting_for_valid_in;
else
next_state <= elaboration;
end if;
when elaboration =>
next_state <= waiting_1;
when waiting_1 =>
next_state <= waiting_2;
when waiting_2 =>
next_state <= waiting_3;
when waiting_3 =>
next_state <= waiting_4;
when waiting_4 =>
next_state <= done;
when done =>
if(max_done = '1') then
next_state <= waiting_for_ready_in;
else
next_state <= waiting_for_valid_in;
end if;
when waiting_for_ready_in =>
if(ready_in = '1')then
next_state <= reset;
else
next_state <= waiting_for_ready_in;
end if;
end case;
end process;
fsm_output : process(current_state)
begin
valid_out <= '0';
ready_out <= '0';
start <= '0';
reset_n_all <= '1';
case current_state is
when reset =>
reset_n_all <= '0';
when waiting_for_valid_in =>
ready_out <= '1';
when elaboration =>
start <= '1';
when waiting_1 =>
when waiting_2 =>
when waiting_3 =>
when waiting_4 =>
when done =>
when waiting_for_ready_in =>
valid_out <= '1';
end case;
end process;
end Behavioral;
| gpl-2.0 | dfc82efe0e5a116336616c2a657134ee | 0.485322 | 4.243429 | false | false | false | false |
freecores/grain | src/VHDL/grain128_datapath_slow.vhd | 1 | 1,843 |
--
-- Grain128 datapath, slow and small implementation
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain128_datapath_slow is
generic (
DEBUG : boolean := false -- output debug information
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INJECT_INPUT_I : in std_logic;
PAD_IV_I : in std_logic;
ADD_OUTPUT_I : in std_logic;
H_O : out std_logic
);
end entity;
architecture behav of grain128_datapath_slow is
signal lfsr, nfsr : unsigned(0 to 127);
signal func_h, func_g, func_f : std_logic;
begin
-- outputs:
H_O <= func_h;
-- copy pasted from grain128.c from Hell
func_h <=
nfsr(2) xor nfsr(15) xor nfsr(36) xor nfsr(45) xor nfsr(64) xor nfsr(73)
xor nfsr(89) xor lfsr(93) xor (nfsr(12) and lfsr(8)) xor (lfsr(13) and lfsr(20))
xor (nfsr(95) and lfsr(42)) xor (lfsr(60) and lfsr(79))
xor (nfsr(12) and nfsr(95) and lfsr(95));
func_g <=
lfsr(0) xor nfsr(0) xor nfsr(26) xor nfsr(56) xor nfsr(91) xor nfsr(96)
xor (nfsr(3) and nfsr(67)) xor (nfsr(11) and nfsr(13)) xor (nfsr(17) and nfsr(18))
xor (nfsr(27) and nfsr(59)) xor (nfsr(40) and nfsr(48)) xor (nfsr(61) and nfsr(65))
xor (nfsr(68) and nfsr(84));
func_f <=
lfsr(0) xor lfsr(7) xor lfsr(38) xor lfsr(70) xor lfsr(81) xor lfsr(96);
-- the shift registers:
sr_proc : process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
lfsr <= lfsr sll 1;
nfsr <= nfsr sll 1;
if INJECT_INPUT_I = '1' then
lfsr(127) <= IV_I or PAD_IV_I;
nfsr(127) <= KEY_I;
else
lfsr(127) <= func_f xor (ADD_OUTPUT_I and func_h);
nfsr(127) <= func_g xor (ADD_OUTPUT_I and func_h);
end if;
end if;
end if;
end process;
end behav;
| lgpl-3.0 | ebb91be6aac216b5078cde16d57bd614 | 0.611503 | 2.450798 | false | false | false | false |
Xion345/fpga-projects | library/vga/vga_tiles.vhd | 1 | 4,413 | -- VGA Tiled Framebuffer
-- 8x16 tiles (8 bits per pixel) - 640x480 screen
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_tiling_8x16 is
port(
clk, reset: in std_logic;
-- VGA Sync.
pixel_tick, video_on: in std_logic;
pixel_x: in std_logic_vector(9 downto 0);
pixel_y: in std_logic_vector(9 downto 0);
-- Indexes memory
addr_index: in std_logic_vector(13 downto 0);
data_in_index: in std_logic_vector(7 downto 0);
data_out_index: out std_logic_vector(7 downto 0);
wr_index: in std_logic;
-- Tiles memory
addr_tiles: in std_logic_vector(14 downto 0);
data_in_tiles: in std_logic_vector(7 downto 0);
data_out_tiles: out std_logic_vector(7 downto 0);
wr_tiles: in std_logic;
-- Output
pixel_value: out std_logic_vector(7 downto 0)
);
end vga_tiling_8x16;
architecture vga_tile_arch of vga_tiling_8x16 is
-- Indexes memory
signal addr_rd_index: std_logic_vector(13 downto 0);
signal data_rd_index: std_logic_vector(7 downto 0);
-- Tiles memory
signal addr_rd_tiles: std_logic_vector(14 downto 0);
signal data_rd_tiles: std_logic_vector(7 downto 0);
--
signal tile_x_reg, tile_x_next: unsigned(11 downto 0);
signal tile_y_reg, tile_y_next: unsigned(11 downto 0);
begin
-- Indexes memory block (16K x 8 bits)
index_mem: entity work.block_ram
generic map(DATA_WIDTH => 8, ADDR_WIDTH => 14)
port map(
clk => clk,
-- Port A (read, internal)
wr_a => '0',
addr_a => addr_rd_index,
data_out_a => data_rd_index,
data_in_a => (others => '0'),
-- Port B (write/read, external)
wr_b => wr_index,
addr_b => addr_index,
data_out_b => data_out_index,
data_in_b => data_in_index
);
-- Tiles memory block (32K x 8 bits)
tiles_mem: entity work.block_ram
generic map(DATA_WIDTH => 8, ADDR_WIDTH => 15)
port map(
clk => clk,
-- Port A (read, internal)
wr_a => '0',
addr_a => addr_rd_tiles,
data_out_a => data_rd_tiles,
data_in_a => (others => '0'),
-- Port B (write/read, external)
wr_b => wr_tiles,
addr_b => addr_tiles,
data_out_b => data_out_tiles,
data_in_b => data_in_tiles
);
-- Registers
process(clk, reset)
begin
if reset = '1' then
tile_x_reg <= (others => '0');
tile_y_reg <= (others => '0');
elsif rising_edge(clk) then
tile_x_reg <= tile_x_next;
tile_y_reg <= tile_y_next;
end if;
end process;
-- Next state
process(pixel_tick, video_on, pixel_x, pixel_y,
tile_x_reg, tile_y_reg)
begin
tile_y_next <= tile_y_reg;
tile_x_next <= tile_x_reg;
if video_on = '1' and pixel_tick = '1' and pixel_x(2 downto 0) = "111" then -- End of tile x
if pixel_x = "1001111111" then -- End of screen x
if pixel_y(3 downto 0) = "1111" then -- End of tile y
if pixel_y = "0111011111" then -- End of screen y
tile_x_next <= (others => '0');
tile_y_next <= (others => '0');
else
tile_y_next <= tile_y_reg + tile_x_reg + 1;
end if;
end if;
tile_x_next <= (others => '0');
else
tile_x_next <= tile_x_reg + 1;
end if;
end if;
end process;
-- Memory wiring
addr_rd_index(13 downto 12) <= (others => '0');
addr_rd_index(11 downto 0) <= std_logic_vector(tile_y_reg + tile_x_reg);
addr_rd_tiles(14 downto 7) <= data_rd_index;
addr_rd_tiles(6 downto 3) <= pixel_y(3 downto 0);
addr_rd_tiles(2 downto 0) <= pixel_x(2 downto 0);
-- Output
pixel_value <= data_rd_tiles when video_on = '1' else "00000000"; -- Black is the new video off !
end vga_tile_arch;
| mit | b61ea0b71760f1e97ffdbefc121cb21d | 0.493995 | 3.499603 | false | false | false | false |
artic92/sistemi-embedded-task2 | src/ip_core2/complex_abs/fsm_complex_abs.vhd | 1 | 3,103 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 11:30:11
-- Design Name:
-- Module Name: fsm_complex_abs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm_complex_abs is
Port ( clk : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
ready_in : in STD_LOGIC;
abs_done : in STD_LOGIC;
valid_out : out STD_LOGIC;
ready_out : out STD_LOGIC);
end fsm_complex_abs;
architecture Behavioral of fsm_complex_abs is
type state is (reset , waiting_for_valid_in , elaborazione , waiting_for_ready_in);
signal current_state, next_state : state := reset;
begin
registro_stato : process(clk, reset_n, next_state)
begin
if(reset_n = '0') then
current_state <= reset;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
fsm_next_state : process(current_state, reset_n, valid_in, abs_done, ready_in)
begin
case current_state is
when reset =>
if(reset_n = '0') then
next_state <= reset;
else
next_state <= waiting_for_valid_in;
end if;
when waiting_for_valid_in =>
if(valid_in = '0') then
next_state <= waiting_for_valid_in;
else
next_state <= elaborazione;
end if;
when elaborazione =>
if(abs_done <= '0') then
next_state <= elaborazione;
else
next_state <= waiting_for_ready_in;
end if;
when waiting_for_ready_in =>
if(ready_in = '0') then
next_state <= waiting_for_ready_in;
else
next_state <= waiting_for_valid_in;
end if;
end case;
end process;
fsm_uscita : process(current_state)
begin
valid_out <= '0';
ready_out <= '0';
case current_state is
when reset =>
when waiting_for_valid_in =>
ready_out<='1';
when elaborazione =>
when waiting_for_ready_in =>
valid_out <= '1';
end case;
end process;
end Behavioral;
| gpl-2.0 | 992ab9a7b8c97b04300a3a55ea20de64 | 0.486626 | 4.364276 | false | false | false | false |
Xion345/fpga-projects | projects/vga-palette/vga_palette_top.vhd | 1 | 1,205 | -- VGA Palette testing circuit
--
library ieee;
use ieee.std_logic_1164.ALL;
entity vga_palette_top is
port(
clk, reset: in std_logic;
red: out std_logic_vector(2 downto 0);
green: out std_logic_vector(2 downto 0);
blue: out std_logic_vector(2 downto 1);
hsync: out std_logic;
vsync: out std_logic;
blue_on: in std_logic;
green_on: in std_logic;
red_on: in std_logic
);
end vga_palette_top;
architecture vga_palette_top_arch of vga_palette_top is
-- VGA Sync.
signal pixel_tick: std_logic;
signal pixel_x, pixel_y: std_logic_vector(9 downto 0);
signal video_on: std_logic;
begin
vga_sync: entity work.vga_sync
port map(clk => clk, reset => reset,
pixel_tick => pixel_tick,
x => pixel_x, y => pixel_y,
hsync => hsync, vsync => vsync, video_on => video_on);
vga_palette: entity work.vga_palette
port map(pixel_x => pixel_x(6 downto 0), pixel_y => pixel_y(6 downto 0),
video_on => video_on,
red => red, green => green, blue => blue,
red_on => red_on, green_on => green_on, blue_on => blue_on);
end vga_palette_top_arch;
| mit | 68b5c054fce8554fe0c9ecc63f53336a | 0.588382 | 3.204787 | false | false | false | false |
freecores/grain | src/VHDL/grain_datapath_fast.vhd | 1 | 3,694 |
--
-- Grain datapath, faster but larger implementation
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain_datapath_fast is
generic (
DEBUG : boolean := false -- output debug information
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INJECT_INPUT_I : in std_logic;
PAD_IV_I : in std_logic;
ADD_OUTPUT_I : in std_logic;
H_O : out std_logic
);
end entity;
architecture behav of grain_datapath_fast is
-- On Altera devices, this will make things bigger but also faster
-- by stopping Quartus from using memories instead of shift registers
-- (since Altera lacks SLR16 primitives, puh!)
attribute altera_attribute : string;
attribute altera_attribute of behav : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
signal lfsr, nfsr : unsigned(0 to 79);
signal func_h, func_g, func_f : std_logic;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7 : std_logic;
begin
-- outputs:
H_O <= func_h;
-- register balancing:
--
-- this is just a dumb example I made up, you should instead
-- use your synthesizer which does a much better job!
--
func_h <= tmp1 xor tmp2;
func_g <= tmp3 xor tmp4 xor tmp5 xor tmp6;
func_f <= tmp7;
retime_proc: process(CLK_I)
variable nfsr_e, lfsr_e : unsigned(0 to 79);
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
nfsr_e := nfsr sll 1;
lfsr_e := lfsr sll 1;
-- H (well, Z really)
tmp1 <=
nfsr_e(1) xor nfsr_e(2) xor nfsr_e(4) xor nfsr_e(10) xor nfsr_e(31) xor nfsr_e(43) xor nfsr_e(56) xor
lfsr_e(25) xor nfsr_e(63);
tmp2 <=
(lfsr_e(3) and lfsr_e(64)) xor
(lfsr_e(46) and lfsr_e(64)) xor
(lfsr_e(64) and nfsr_e(63)) xor
(lfsr_e(3) and lfsr_e(25) and lfsr_e(46)) xor
(lfsr_e(3) and lfsr_e(46) and lfsr_e(64)) xor
(lfsr_e(3) and lfsr_e(46) and nfsr_e(63)) xor
(lfsr_e(25) and lfsr_e(46) and nfsr_e(63)) xor
(lfsr_e(46) and lfsr_e(64) and nfsr_e(63));
-- G
tmp3 <=
lfsr_e(0) xor nfsr_e(37) xor
nfsr_e(33) xor nfsr_e(28) xor nfsr_e(21) xor nfsr_e(14) xor nfsr_e(9) xor nfsr_e(0);
tmp4 <=
(nfsr_e(63) and nfsr_e(60)) xor (nfsr_e(37) and nfsr_e(33)) xor
(nfsr_e(15) and nfsr_e(9)) xor
(nfsr_e(60) and nfsr_e(52) and nfsr_e(45));
tmp5<=
(nfsr_e(33) and nfsr_e(28) and nfsr_e(21)) xor
(nfsr_e(63) and nfsr_e(45) and nfsr_e(28) and nfsr_e(9)) xor
(nfsr_e(60) and nfsr_e(52) and nfsr_e(37) and nfsr_e(33)) xor
(nfsr_e(63) and nfsr_e(60) and nfsr_e(21) and nfsr_e(15));
tmp6 <=
nfsr_e(62) xor nfsr_e(60) xor nfsr_e(52) xor nfsr_e(45) xor
(nfsr_e(63) and nfsr_e(60) and nfsr_e(52) and nfsr_e(45) and nfsr_e(37)) xor
(nfsr_e(33) and nfsr_e(28) and nfsr_e(21) and nfsr_e(15) and nfsr_e(9)) xor
(nfsr_e(52) and nfsr_e(45) and nfsr_e(37) and nfsr_e(33) and nfsr_e(28) and nfsr_e(21));
-- F
tmp7 <=
lfsr_e(62) xor lfsr_e(51) xor lfsr_e(38) xor lfsr_e(23) xor lfsr_e(13) xor lfsr_e(0);
end if;
end if;
end process;
-- the shift registers:
sr_proc : process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
lfsr <= lfsr sll 1;
nfsr <= nfsr sll 1;
if INJECT_INPUT_I = '1' then
lfsr(79) <= IV_I or PAD_IV_I;
nfsr(79) <= KEY_I;
else
lfsr(79) <= func_f xor (ADD_OUTPUT_I and func_h);
nfsr(79) <= func_g xor (ADD_OUTPUT_I and func_h);
end if;
end if;
end if;
end process;
end behav;
| lgpl-3.0 | 906c974c0491d6d54bac0ca05adf6621 | 0.58392 | 2.443122 | false | false | false | false |
freecores/grain | src/VHDL/grain128_datapath_fast.vhd | 1 | 2,546 |
--
-- Grain128 datapath, faster but larger implementation
--
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity grain128_datapath_fast is
generic (
DEBUG : boolean := false -- output debug information
);
port (
CLK_I : in std_logic;
CLKEN_I : in std_logic := '1';
ARESET_I : in std_logic;
KEY_I : in std_logic;
IV_I : in std_logic;
INJECT_INPUT_I : in std_logic;
PAD_IV_I : in std_logic;
ADD_OUTPUT_I : in std_logic;
H_O : out std_logic
);
end entity;
architecture behav of grain128_datapath_fast is
-- On Altera devices, this will make things bigger but also faster
-- by stopping Quartus from using memories instead of shift registers
-- (since Altera lacks SLR16 primitives, puh!)
attribute altera_attribute : string;
attribute altera_attribute of behav : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
signal lfsr, nfsr : unsigned(0 to 127);
signal func_h, func_g, func_f : std_logic;
signal tmp1, tmp2, tmp3, tmp4, tmp5 : std_logic;
begin
-- outputs:
H_O <= func_h;
-- register balancing:
-- usualy, you can (should) leave this to the
-- synthesizer which does a much better job
func_h <= tmp1 xor tmp2;
func_g <= tmp3 xor tmp4;
func_f <= tmp5;
retime_proc: process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
tmp1 <= nfsr(37) xor nfsr(46) xor nfsr(65) xor nfsr(74) xor nfsr(90) xor lfsr(94) xor (nfsr(13) and lfsr(9)) xor (lfsr(14) and lfsr(21));
tmp2 <= nfsr(3) xor nfsr(16) xor (nfsr(96) and lfsr(43)) xor (lfsr(61) and lfsr(80)) xor (nfsr(13) and nfsr(96) and lfsr(96));
tmp3 <= nfsr(27) xor nfsr(57) xor nfsr(92) xor nfsr(97) xor (nfsr(4) and nfsr(68)) xor (nfsr(12) and nfsr(14)) xor (nfsr(18) and nfsr(19));
tmp4 <= lfsr(1) xor nfsr(1) xor (nfsr(28) and nfsr(60)) xor (nfsr(41) and nfsr(49)) xor (nfsr(62) and nfsr(66)) xor (nfsr(69) and nfsr(85));
tmp5 <= lfsr(1) xor lfsr(8) xor lfsr(39) xor lfsr(71) xor lfsr(82) xor lfsr(97);
end if;
end if;
end process;
-- the shift registers:
sr_proc : process(CLK_I)
begin
if rising_edge(CLK_I) then
if CLKEN_I = '1' then
lfsr <= lfsr sll 1;
nfsr <= nfsr sll 1;
if INJECT_INPUT_I = '1' then
lfsr(127) <= IV_I or PAD_IV_I;
nfsr(127) <= KEY_I;
else
lfsr(127) <= func_f xor (ADD_OUTPUT_I and func_h);
nfsr(127) <= func_g xor (ADD_OUTPUT_I and func_h);
end if;
end if;
end if;
end process;
end behav;
| lgpl-3.0 | 2678d393b6448baa97be0e3171d34f79 | 0.623723 | 2.705632 | false | false | false | false |
Subsets and Splits