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Verilogdata4pretrainCODET5

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JayZhang1 commited on Apr 9, 2023

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351b3f3

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1 Parent(s): 47e0b49

Upload shard_Verilog_Dataset_0.csv

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.gitattributes +1 -0
shard_Verilog_Dataset_0.csv +3 -0

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@@ -148,3 +148,4 @@ shard_Verilog_bigquery_GitHub_92.csv filter=lfs diff=lfs merge=lfs -text
 shard_Verilog_bigquery_GitHub_93.csv filter=lfs diff=lfs merge=lfs -text
 shard_Verilog_bigquery_GitHub_94.csv filter=lfs diff=lfs merge=lfs -text
 shard_Verilog_bigquery_GitHub_95.csv filter=lfs diff=lfs merge=lfs -text

 shard_Verilog_bigquery_GitHub_93.csv filter=lfs diff=lfs merge=lfs -text
 shard_Verilog_bigquery_GitHub_94.csv filter=lfs diff=lfs merge=lfs -text
 shard_Verilog_bigquery_GitHub_95.csv filter=lfs diff=lfs merge=lfs -text
+shard_Verilog_Dataset_0.csv filter=lfs diff=lfs merge=lfs -text

shard_Verilog_Dataset_0.csv ADDED Viewed

	@@ -0,0 +1,3 @@

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+size 45400178