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// Quartus II Verilog Template
// Barrel shifter
module barrel_shifter
#(parameter M=8, parameter N=2**M)
(
input [N-1:0] data,
input [M-1:0] distance,
input clk, enable, shift_left,
output reg [N-1:0] sr_out
);
// Declare temporary registers
reg [2*N-1:0] tmp;
// Shift/rotate in the specified direction and
// by the specified amount
always @ (posedge clk)
begin
tmp = {data,data};
if (enable == 1'b1)
if (shift_left)
begin
tmp = tmp << distance;
sr_out <= tmp[2*N-1:N];
end
else
begin
tmp = tmp >> distance;
sr_out <= tmp[N-1:0];
end
end
endmodule
|
module top_module( input in, output out );
assign out = in;
endmodule
|
module top_module(
input a,b,c,
output w,x,y,z );
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
|
module top_module( input in, output out );
assign out = ~in;
endmodule
|
module top_module(
input a,
input b,
output out );
assign out = a&b;
endmodule
|
module top_module(
input a,
input b,
output out );
assign out = ~(a|b);
endmodule
|
module top_module(
input a,
input b,
output out );
assign out = ~a^b;
endmodule
|
`default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire in1,in2;
assign in1 = a & b;
assign in2 = c & d;
assign out = in1 | in2;
assign out_n = ~(in1 | in2);
endmodule
|
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
assign p2y = (p2a & p2b) | (p2d & p2c);
endmodule
|
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0 ); // Module body starts after module declaration
assign outv = vec;
assign o2 = vec[2];
assign o1 = vec[1];
assign o0 = vec[0];
endmodule
|
`default_nettype none // Disable implicit nets. Reduces some types of bugs.
module top_module(
input wire [15:0] in,
output wire [7:0] out_hi,
output wire [7:0] out_lo );
assign {out_hi,out_lo} = in;
endmodule
|
module top_module(
input [31:0] in,
output [31:0] out );//
assign {out[7:0],out[15:8],out[23:16],out[31:24]} = in;
endmodule
|
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not[2:0] = ~a; // Part-select on left side is o.
assign out_not[5:3] = ~b; //Assigning to [5:3] does not conflict with [2:0]
endmodule |
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[0] & in[1] & in[2] & in[3] ;
assign out_or = in[0] | in[1] | in[2] | in[3];
assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];
endmodule
|
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
assign w = {a[4:0],b[4:2]};
assign x = {b[1:0],c[4:0],d[4]};
assign y = {d[3:0],e[4:1]};
assign z = {e[0],f[4:0],2'b11};
endmodule
|
module top_module(
input [7:0] in,
output [7:0] out
);
assign out[7:0] = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
/*
// I know you're dying to know how to use a loop to do this:
// Create a combinational always block. This creates combinational logic that computes the same result
// as sequential code. for-loops describe circuit *behaviour*, not *structure*, so they can only be used
// inside procedural blocks (e.g., always block).
// The circuit created (wires and gates) does NOT do any iteration: It only produces the same result
// AS IF the iteration occurred. In reality, a logic synthesizer will do the iteration at compile time to
// figure out what circuit to produce. (In contrast, a Verilog simulator will execute the loop sequentially
// during simulation.)
always @(*) begin
for (int i=0; i<8; i++) // int is a SystemVerilog type. Use integer for pure Verilog.
out[i] = in[8-i-1];
end
// It is also possible to do this with a generate-for loop. Generate loops look like procedural for loops,
// but are quite different in concept, and not easy to understand. Generate loops are used to make instantiations
// of "things" (Unlike procedural loops, it doesn't describe actions). These "things" are assign statements,
// module instantiations, net/variable declarations, and procedural blocks (things you can create when NOT inside
// a procedure). Generate loops (and genvars) are evaluated entirely at compile time. You can think of generate
// blocks as a form of preprocessing to generate more code, which is then run though the logic synthesizer.
// In the example below, the generate-for loop first creates 8 assign statements at compile time, which is then
// synthesized.
// Note that because of its intended usage (generating code at compile time), there are some restrictions
// on how you use them. Examples: 1. Quartus requires a generate-for loop to have a named begin-end block
// attached (in this example, named "my_block_name"). 2. Inside the loop body, genvars are read only.
generate
genvar i;
for (i=0; i<8; i = i+1) begin: my_block_name
assign out[i] = in[8-i-1];
end
endgenerate
*/
endmodule
|
module top_module (
input [7:0] in,
output [31:0] out );//
assign out = {{24{in[7]}},{in}};
endmodule
|
module top_module (
input a, b, c, d, e,
output [24:0] out );//
wire [4:0] k = {a,b,c,d,e};
assign out[24:20] = ~ {5{a}} ^ k;
assign out[19:15] = ~ {5{b}} ^ k;
assign out[14:10] = ~ {5{c}} ^ k;
assign out[9:5] = ~ {5{d}} ^ k;
assign out[4:0] = ~ {5{e}} ^ k;
endmodule
|
module top_module (
input a,
input b,
output out
);
// Create an instance of "mod_a" named "inst1", and connect ports by name:
mod_a inst1 (
.in1(a), // Port"in1"connects to wire "a"
.in2(b), // Port "in2" connects to wire "b"
.out(out) // Port "out" connects to wire "out"
// (Note: mod_a's port "out" is not related to top_module's wire "out".
// It is simply coincidence that they have the same name)
);
/*
// Create an instance of "mod_a" named "inst2", and connect ports by position:
mod_a inst2 ( a, b, out ); // The three wires are connected to ports in1, in2, and out, respectively.
*/
endmodule |
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a aa(out1,out2,a,b,c,d);
endmodule
|
module top_module (
input a,
input b,
input c,
input d,
output out1,
output out2
);
mod_a aaaa(.out1(out1),.out2(out2),.in1(a),.in2(b),.in3(c),.in4(d));
endmodule
|
module top_module ( input clk, input d, output q );
wire q1,q2;
my_dff d1(clk,d,q1);
my_dff d2(clk,q1,q2);
my_dff d3(clk,q2,q);
endmodule |
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output reg [7:0] q
);
wire [7:0] o1, o2, o3; // output of each my_dff8
// Instantiate three my_dff8s
my_dff8 d1 ( clk, d, o1 );
my_dff8 d2 ( clk, o1, o2 );
my_dff8 d3 ( clk, o2, o3 );
// This is one way to make a 4-to-1 multiplexer
always @(*) // Combinational always block
case(sel)
2'h0: q = d;
2'h1: q = o1;
2'h2: q = o2;
2'h3: q = o3;
endcase
endmodule |
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire con1, con2;
add16 adder_1(a[15:0], b[15:0], 0, sum[15:0], con1);
add16 adder_2(a[31:16], b[31:16], con1, sum[31:16], con2);
endmodule
|
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);//
wire con1, con2;
add16 adder_1(a[15:0], b[15:0], 0, sum[15:0], con1);
add16 adder_2(a[31:16], b[31:16], con1, sum[31:16], con2);
endmodule
module add1 ( input a, input b, input cin, output sum, output cout );
assign sum = a^b^cin;
assign cout = a&b | a&cin | b&cin;
endmodule
|
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire cout1,cout2a,cout2b;
wire [15:0] sum2a,sum2b;
add16 add1(a[15:0],b[15:0],0,sum[15:0],cout1);
add16 add2a(a[31:16],b[31:16],0,sum2a,cout2a);
add16 add2b(a[31:16],b[31:16],1,sum2b,cout2b);
always @(*) begin
case (cout1)
0: sum[31:16] = sum2a;
1: sum[31:16] = sum2b;
endcase
end
endmodule |
module top_module(
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] sum
);
wire cout,cout2;
wire [31:0] b_in;
assign b_in = b^{32{sub}};
add16 a1(a[15:0],b_in[15:0],sub,sum[15:0],cout);
add16 a2(a[31:16],b_in[31:16],cout,sum[31:16],cout2);
endmodule
|
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
output wire out_assign,
output reg out_alwaysblock
);
assign out_assign = a&b;
always @(*) out_alwaysblock = a&b;
endmodule
|
// synthesis verilog_input_version verilog_2001
module top_module(
input clk,
input a,
input b,
output wire out_assign,
output reg out_always_comb,
output reg out_always_ff );
assign out_assign = a^b;
always @(*) out_always_comb = a^b;
always @(posedge clk) out_always_ff <= a^b;
endmodule
|
// synthesis verilog_input_version verilog_2001
module top_module(
input a,
input b,
input sel_b1,
input sel_b2,
output wire out_assign,
output reg out_always );
assign out_assign = (sel_b1&sel_b2)?b:a;
always@(*) begin
if (sel_b1&sel_b2) begin
out_always = b;
end
else begin
out_always = a;
end
end
endmodule
|
// synthesis verilog_input_version verilog_2001
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving ); //
always @(*) begin
if (cpu_overheated)
shut_off_computer = 1;
end
always @(*) begin
if (~arrived)
keep_driving = ~gas_tank_empty;
end
endmodule
|
// synthesis verilog_input_version verilog_2001
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out );//
always@(*) begin // This is a combinational circuit
case(sel)
3'b000: out = data0;
3'b001: out = data1;
3'b010: out = data2;
3'b011: out = data3;
3'b100: out = data4;
3'b101: out = data5;
default: out = 4'b0000;
endcase
end
endmodule
|
// synthesis verilog_input_version verilog_2001
module top_module (
input [3:0] in,
output reg [1:0] pos );
always @(*) begin
pos = (in[0]&1)?2'd0:(in[1]&1)?2'd1:(in[2]&1)?2'd2:(in[3]&1)?2'd3:2'd0;
end
endmodule
|
module top_module (
input [7:0] in,
output reg [2:0] pos );
// casez treats bits that have the value z as don't-care in the comparison.
//Notice how there are certain inputs (e.g., 4'b1111) that will match more than one case item.
//The first match is chosen (so 4'b1111 matches the first item, out = 0, but not any of the later ones).
//There is also a similar casex that treats both x and z as don't-care. I don't see much purpose to using it over casez.
//The digit ? is a synonym for z. so 2'bz0 is the same as 2'b?0
always @(*) begin
casez (in[7:0])
8'bzzzzzzz1: pos = 0;
8'bzzzzzz1z: pos = 1;
8'bzzzzz1zz: pos = 2;
8'bzzzz1zzz: pos = 3;
8'bzzz1zzzz: pos = 4;
8'bzz1zzzzz: pos = 5;
8'bz1zzzzzz: pos = 6;
8'b1zzzzzzz: pos = 7;
default: pos = 0;
endcase
end
endmodule |
// synthesis verilog_input_version verilog_2001
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up );
always @(*) begin
up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
case (scancode)
16'he06b: left = 1'b1;
16'he072: down = 1'b1;
16'he074: right = 1'b1;
16'he075: up = 1'b1;
endcase
end
endmodule
|
module top_module (
input [7:0] a, b, c, d,
output [7:0] min);//
wire [7:0] min1 = (a<b)?a:b;
wire [7:0] min2 = (c<d)?c:d;
assign min = (min1<min2)? min1 : min2;
endmodule |
module top_module (
input [7:0] in,
output parity);
assign parity = ^ in;
endmodule
|
module top_module(
input [99:0] in,
output out_and,
output out_or,
output out_xor
);
assign {out_and,out_or,out_xor} = {&in,|in,^in};
endmodule
|
module top_module(
input [99:0] in,
output [99:0] out
);
integer i;
always @(in) begin
for(i=0;i<100;i++) begin
out[i] = in[99-i];
end
end
endmodule
|
module top_module (
input [254:0] in,
output reg [7:0] out
);
always @(*) begin // Combinational always block
out = 0;
for (int i=0;i<255;i++)
out = out + in[i];
end
endmodule
|
module top_module(
input [99:0] a, b,
input cin,
output [99:0] cout,
output [99:0] sum );
integer i;
always @(*) begin
sum[0] = a[0] ^ b[0] ^ cin;
cout[0] = a[0] & b[0] | cin & (a[0]|b[0]);
for (i = 1; i<100; i++) begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
cout[i] = a[i] & b[i] | cout[i-1] & (a[i]|b[i]);
end
end
endmodule
|
module top_module(
input [399:0] a, b,
input cin,
output cout,
output [399:0] sum );
wire[99:0] cout_wires;
genvar i;
generate
bcd_fadd(a[3:0], b[3:0], cin, cout_wires[0],sum[3:0]);
for (i=4; i<400; i=i+4) begin: bcd_adder_instances
bcd_fadd bcd_adder(a[i+3:i], b[i+3:i], cout_wires[i/4-1],cout_wires[i/4],sum[i+3:i]);
end
endgenerate
assign cout = cout_wires[99];
endmodule
|
module top_module (
input in,
output out);
assign out = in;
endmodule
|
module top_module (input x, input y, output z);
assign z = (x^y) & x;
endmodule
|
module top_module (input x, input y, output z);
assign z = ~(x^y);
endmodule
|
module top_module(
input x,
input y,
output z);
wire o1, o2, o3, o4;
A ia1 (x, y, o1);
B ib1 (x, y, o2);
A ia2 (x, y, o3);
B ib2 (x, y, o4);
assign z = (o1 | o2) ^ (o3 & o4);
// Or you could simplify the circuit including the sub-modules:
// assign z = x|~y;
endmodule
module A (
input x,
input y,
output z);
assign z = (x^y) & x;
endmodule
module B (
input x,
input y,
output z);
assign z = ~(x^y);
endmodule
|
module top_module(
input ring,
input vibrate_mode,
output ringer,
output motor
);
// When should ringer be on? When (phone is ringing) and (phone is not in vibrate mode)
assign ringer = ring & ~vibrate_mode;
// When should motor be on? When (phone is ringing) and (phone is in vibrate mode)
assign motor = ring & vibrate_mode;
endmodule
|
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign fan = fan_on | heater | aircon;
assign heater = mode & too_cold;
assign aircon = ~mode & too_hot;
endmodule
|
module top_module(
input [2:0] in,
output [1:0] out );
integer i,count;
always @ * begin
count = 0;
for (i=0; i<3;i=i+1) begin
if (in[i]==1'b1) count=count+1;
end
out = count;
end
endmodule |
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
assign out_both = {in[3]&in[2],in[2]&in[1],in[1]&in[0]};
assign out_any = {in[3]|in[2],in[2]|in[1],in[1]|in[0]};
assign out_different = {in[0]^in[3],in[3]^in[2],in[2]^in[1],in[1]^in[0]};
/*
// Use bitwise operators and part-select to do the entire calculation in one line of code
// in[3:1] is this vector: in[3] in[2] in[1]
// in[2:0] is this vector: in[2] in[1] in[0]
// Bitwise-OR produces a 3 bit vector. | | |
// Assign this 3-bit result to out_any[3:1]: o_a[3] o_a[2] o_a[1]
// Thus, each output bit is the OR of the input bit and its neighbour to the right:
// e.g., out_any[1] = in[1] | in[0];
// Notice how this works even for long vectors.
assign out_any = in[3:1] | in[2:0];
assign out_both = in[2:0] & in[3:1];
// XOR 'in' with a vector that is 'in' rotated to the right by 1 position: {in[0], in[3:1]}
// The rotation is accomplished by using part selects[] and the concatenation operator{}.
assign out_different = in ^ {in[0], in[3:1]};
*/
endmodule
|
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
assign out_any = in[99:1] | in[98:0];
assign out_both = in[98:0] & in[99:1];
assign out_different = in ^ {in[0], in[99:1]};
endmodule
|
module top_module (
output out);
assign out = 1'b0;
endmodule
|
module top_module (
input in1,
input in2,
output out);
assign out = ~ (in1|in2);
endmodule
|
module top_module (
input in1,
input in2,
input in3,
output out);
assign out = in3 ^ ~(in1^in2);
endmodule
|
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a&b;
assign out_or = a|b;
assign out_xor = a^b;
assign out_nand = ~out_and;
assign out_nor = ~out_or;
assign out_xnor = ~out_xor;
assign out_anotb = a&~b;
endmodule
|
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a && p1b && p1c && p1d);
assign p2y = ~(p2a && p2b && p2c && p2d);
endmodule
|
module top_module (
input x3,
input x2,
input x1,
output f
);
// This truth table has four minterms.
assign f = ( ~x3 & x2 & ~x1 ) |
( ~x3 & x2 & x1 ) |
( x3 & ~x2 & x1 ) |
( x3 & x2 & x1 ) ;
// It can be simplified, by boolean algebra or Karnaugh maps.
// assign f = (~x3 & x2) | (x3 & x1);
// You may then notice that this is actually a 2-to-1 mux, selected by x3:
// assign f = x3 ? x1 : x2;
endmodule
|
module top_module(
input [1:0] A,
input [1:0] B,
output z);
// assign z = (A[0] == B[0]) && (A[1] == B[1]);
assign z = (A[1:0]==B[1:0]); // Comparisons produce a 1 or 0 result.
// Another option is to use a 16-entry truth table ( {A,B} is 4 bits, with 16 combinations ).
// There are 4 rows with a 1 result. 0000, 0101, 1010, and 1111.
endmodule
|
module top_module(
input a, b, sel,
output out );
assign out = (sel==1)?b:a;
endmodule |
module top_module(
input [99:0] a, b,
input sel,
output [99:0] out );
assign out = (sel)? b:a;
endmodule
|
module top_module(
input [15:0] a, b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always @(*) begin
case (sel)
4'd0: out = a;
4'd1: out = b;
4'd2: out = c;
4'd3: out = d;
4'd4: out = e;
4'd5: out = f;
4'd6: out = g;
4'd7: out = h;
4'd8: out = i;
default: out = {16{1'b1}};
endcase
end
endmodule
/*
module top_module (
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [15:0] e,
input [15:0] f,
input [15:0] g,
input [15:0] h,
input [15:0] i,
input [3:0] sel,
output logic [15:0] out
);
// Case statements can only be used inside procedural blocks (always block)
// This is a combinational circuit, so use a combinational always @(*) block.
always @(*) begin
out = '1; // '1 is a special literal syntax for a number with all bits set to 1.
// '0, 'x, and 'z are also valid.
// I prefer to assign a default value to 'out' instead of using a
// default case.
case (sel)
4'h0: out = a;
4'h1: out = b;
4'h2: out = c;
4'h3: out = d;
4'h4: out = e;
4'h5: out = f;
4'h6: out = g;
4'h7: out = h;
4'h8: out = i;
endcase
end
endmodule
*/
|
module top_module(
input [255:0] in,
input [7:0] sel,
output out );
assign out = in[sel];
endmodule
|
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
// We can't part-select multiple bits without an error, but we can select one bit at a time,
// four times, then concatenate them together.
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
// Alternatively, "indexed vector part select" works better, but has an unfamiliar syntax:
// assign out = in[sel*4 +: 4]; // Select starting at index "sel*4", then select a total width of 4 bits with increasing (+:) index number.
// assign out = in[sel*4+3 -: 4]; // Select starting at index "sel*4+3", then select a total width of 4 bits with decreasing (-:) index number.
// Note: The width (4 in this case) must be constant.
endmodule
|
module top_module(
input a, b,
output cout, sum );
assign cout = a&b;
assign sum = a^b;
endmodule
|
module top_module(
input a, b, cin,
output cout, sum );
assign cout = a&b | b&cin | a&cin;
assign sum = a^b^cin;
endmodule
|
module top_module(
input [2:0] a, b,
input cin,
output [2:0] cout,
output [2:0] sum );
FA FA1(a[0],b[0],cin,cout[0],sum[0]);
FA FA2(a[1],b[1],cout[0],cout[1],sum[1]);
FA FA3(a[2],b[2],cout[1],cout[2],sum[2]);
endmodule
module FA(
input a, b, cin,
output cout, sum );
assign cout = a&b | b&cin | a&cin;
assign sum = a^b^cin;
endmodule |
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
// This circuit is a 4-bit ripple-carry adder with carry-out.
assign sum = x+y; // Verilog addition automatically produces the carry-out bit.
// Verilog quirk: Even though the value of (x+y) includes the carry-out, (x+y) is still considered to be a 4-bit number (The max width of the two operands).
// This is correct:
// assign sum = (x+y);
// But this is incorrect:
// assign sum = {x+y}; // Concatenation operator: This discards the carry-out
endmodule
|
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
wire [8:0] sum;
assign sum = a+b;
assign s = sum[7:0];
assign overflow = a[7]&&b[7]&&(~s[7]) || (~a[7])&&(~b[7])&&(s[7]);
endmodule
|
module top_module(
input [99:0] a, b,
input cin,
output cout,
output [99:0] sum );
assign {cout,sum} = a+b+cin;
endmodule
|
module top_module(
input [15:0] a, b,
input cin,
output cout,
output [15:0] sum );
wire c1,c2,c3;
bcd_fadd b1(a[3:0],b[3:0],cin,c1,sum[3:0]);
bcd_fadd b2(a[7:4],b[7:4],c1,c2,sum[7:4]);
bcd_fadd b3(a[11:8],b[11:8],c2,c3,sum[11:8]);
bcd_fadd b4(a[15:12],b[15:12],c3,cout,sum[15:12]);
endmodule
|
module top_module(
input a,
input b,
input c,
output out );
assign out = (a | b | c);
endmodule
|
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = ~d&~a | ~c&~b | c&d&(a|b);
endmodule
|
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a | ~b&c;
endmodule
|
module top_module(
input a,
input b,
input c,
input d,
output out );
assign out = a^b^c^d;
endmodule
|
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c&d)|(~a&~b&c);
assign out_pos = c&(~b|~c|d)&(~a|~c|d);
endmodule
|
module top_module (
input [4:1] x,
output f );
assign f = ~x[1]&x[3] | x[1]&x[2]&x[4];
endmodule
|
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1]&x[3])|(~x[2]&~x[4])|(x[2]&x[3]&x[4]);
endmodule
|
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in = (c&d)?4'b1001:(c)?4'b0101:(d)?4'b0001:4'b0100;
endmodule
|
module top_module(
input clk,
input d,
output reg q);
// Use non-blocking assignment for edge-triggered always blocks
always @(posedge clk)
q <= d;
// Undefined simulation behaviour can occur if there is more than one edge-triggered
// always block and blocking assignment is used. Which always block is simulated first?
endmodule
|
module top_module (
input clk,
input in,
output out);
always @(posedge clk) begin
out <= out^in;
end
endmodule
|
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
always @ (posedge clk) begin
case (L)
1'b0 : Q <= q_in;
1'b1 : Q <= r_in;
endcase
end
endmodule |
module top_module (
input clk,
input w, R, E, L,
output Q
);
wire [1:0] con = {E,L};
always @(posedge clk) begin
case(con)
2'b00: Q <= Q;
2'b01: Q <= R;
2'b11: Q <= R;
2'b10: Q <= w;
endcase
end
endmodule
|
module top_module (
input clk,
input x,
output z
);
reg q,q1,q2;
always @(posedge clk)
begin
q<= q^x;
q1<= ~q1 && x;
q2<= ~q2 || x;
end
assign z=~(q | q1 | q2);
endmodule |
module top_module (
input clk,
input j,
input k,
output Q);
always @ (posedge clk) begin
case ({j,k})
2'b00: Q <= Q;
2'b01: Q <= 1'b0;
2'b10: Q <= 1'b1;
2'b11: Q <= ~Q;
endcase
end
endmodule
|
module top_module(
input clk,
input [7:0] in,
output reg [7:0] pedge);
reg [7:0] d_last;
always @(posedge clk) begin
d_last <= in; // Remember the state of the previous cycle
pedge <= in & ~d_last; // A positive edge occurred if input was 0 and is now 1.
end
endmodule
|
module top_module (
input clk,
input [7:0] in,
output [7:0] anyedge
);
reg [7:0]dlast;
always @ (posedge clk) begin
dlast <= in;
anyedge <= dlast ^ in;
end
endmodule
|
module top_module (
input clk,
input reset,
input [31:0] in,
output [31:0] out
);
reg [31:0] d_last;
wire [31:0] state;
assign state = d_last & ~in;
always@( posedge clk) begin
d_last <= in;
if (reset) begin
out <= '0;
end
else begin
for (int i = 0; i<32; i++) begin
if(state[i] == 1'b1)
out[i] <= 1'b1;
end
end
end
endmodule
|
module top_module(
input clk,
input d,
output q);
reg p, n;
// A positive-edge triggered flip-flop
always @(posedge clk)
p <= d ^ n;
// A negative-edge triggered flip-flop
always @(negedge clk)
n <= d ^ p;
// Why does this work?
// After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
// After negedge clk, n changes to p^n. Thus q = (p^n) = (p^p^n) = d.
// At each (positive or negative) clock edge, p and n FFs alternately
// load a value that will cancel out the other and cause the new value of d to remain.
assign q = p ^ n;
// Can't synthesize this.
/*always @(posedge clk, negedge clk) begin
q <= d;
end*/
endmodule
/*
module top_module (
input clk,
input d,
output q
);
reg q1,q2;
assign q = clk? q1:q2;
always@(posedge clk) begin
q1 <= d;
end
always@(negedge clk) begin
q2 <= d;
end
endmodule
*/ |
module top_module(
input clk,
input [7:0] d,
output reg [7:0] q);
// Because q is a vector, this creates multiple DFFs.
always @(posedge clk)
q <= d;
endmodule
|
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= (reset)?8'd0:d;
end
endmodule
|
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
q <= (reset)? 8'h34:d;
end
endmodule
|
module top_module(
input clk,
input [7:0] d,
input areset,
output reg [7:0] q);
// The only difference in code compared to synchronous reset is in the sensitivity list.
always @(posedge clk, posedge areset)
if (areset)
q <= 0;
else
q <= d;
// In Verilog, the sensitivity list looks strange. The FF's reset is sensitive to the
// *level* of areset, so why does using "posedge areset" work?
// To see why it works, consider the truth table for all events that change the input
// signals, assuming clk and areset do not switch at precisely the same time:
// clk areset output
// x 0->1 q <= 0; (because areset = 1)
// x 1->0 no change (always block not triggered)
// 0->1 0 q <= d; (not resetting)
// 0->1 1 q <= 0; (still resetting, q was 0 before too)
// 1->0 x no change (always block not triggered)
endmodule
|
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
case(byteena)
2'b01: q <= (~resetn)? 16'd0:{q[15:8],d[7:0]};
2'b10: q <= (~resetn)? 16'd0:{d[15:8],q[7:0]};
2'b11: q <= (~resetn)? 16'd0:{d[15:8],d[7:0]};
endcase
end
endmodule
|
module top_module (
input d,
input ena,
output q);
always @ (*) begin
if (ena) q<=d;
end
endmodule
|
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q);
always @(posedge clk or posedge ar) begin
q <= (ar)? 0 : d;
end
endmodule
|
module top_module (
input clk,
input d,
input r, // synchronous reset
output q);
always @(posedge clk) begin
q <= (r)? 0:d;
end
endmodule
|
module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= q+1; // Because q is 4 bits, it rolls over from 15 -> 0.
// If you want a counter that counts a range different from 0 to (2^n)-1,
// then you need to add another rule to reset q to 0 when roll-over should occur.
endmodule
|
module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset || q == 9) // Count to 10 requires rolling over 9->0 instead of the more natural 15->0
q <= 0;
else
q <= q+1;
endmodule
|
module top_module (
input clk,
input reset,
output [3:0] q);
always @(posedge clk) begin
if (reset || q == 4'd10)
q <= 4'd1;
else
q <= q + 1;
end
endmodule
|
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always @(posedge clk) begin
if (slowena) begin
if (q == 4'd9)
q<=0;
else
q<=q+1;
end
if(reset) begin
q<=0;
end
end
endmodule
|