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# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# IP: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci
# IP: The module: 'xlnx_axi_dwidth_converter_dm_master' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_clocks.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_dwidth_converter_dm_master'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_dwidth_converter_dm_master'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# IP: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci
# IP: The module: 'xlnx_axi_dwidth_converter_dm_master' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_clocks.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_dwidth_converter_dm_master'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_dwidth_converter_dm_master'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="xlnx_axi_dwidth_converter_dm_master_synth_1" LaunchPart="xc7k325tffg900-2" LaunchTime="1663646805">
<File Type="VDS-TIMING-PB" Name="xlnx_axi_dwidth_converter_dm_master_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="xlnx_axi_dwidth_converter_dm_master_timing_summary_synth.rpt"/>
<File Type="RDS-RDS" Name="xlnx_axi_dwidth_converter_dm_master.vds"/>
<File Type="REPORTS-TCL" Name="xlnx_axi_dwidth_converter_dm_master_reports.tcl"/>
<File Type="PA-TCL" Name="xlnx_axi_dwidth_converter_dm_master.tcl"/>
<File Type="RDS-DCP" Name="xlnx_axi_dwidth_converter_dm_master.dcp"/>
<File Type="RDS-PROPCONSTRS" Name="xlnx_axi_dwidth_converter_dm_master_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="xlnx_axi_dwidth_converter_dm_master_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="xlnx_axi_dwidth_converter_dm_master_utilization_synth.pb"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_dwidth_converter_dm_master">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_dwidth_converter_dm_master"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_dwidth_converter_dm_master">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_dwidth_converter_dm_master"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
|
#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
vivado -log xlnx_axi_dwidth_converter_dm_master.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_master.tcl
|
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
|
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
cmd_exists()
{
command -v "$1" >/dev/null 2>&1
}
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if cmd_exists hostname
then
ISE_HOST=$(hostname)
elif cmd_exists uname
then
ISE_HOST=$(uname -n)
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
|
version:1
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5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3738313137396166346566613466326361376235393238343631353564363263:506172656e742050412070726f6a656374204944:00
eof:3670928724
|
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//
echo "This script was generated under a different operating system."
echo "Please update the PATH variable below, before executing this script"
exit
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64;/home/monir/Software/Vivado/2021.2/bin;";
} else {
PathVal = "/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64;/home/monir/Software/Vivado/2021.2/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
"-log xlnx_axi_dwidth_converter_dm_master.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_master.tcl" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
|
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
set PATH=%SYSTEMROOT%\system32;%PATH%
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
*** Running vivado
with args -log xlnx_axi_dwidth_converter_dm_master.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_master.tcl
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xlnx_axi_dwidth_converter_dm_master.tcl -notrace
Command: synth_design -top xlnx_axi_dwidth_converter_dm_master -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 45344
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 4904 ; free virtual = 12182
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'xlnx_axi_dwidth_converter_dm_master' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/synth/xlnx_axi_dwidth_converter_dm_master.v:58]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_axi_upsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7038]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_w_upsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:5563]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_w_upsizer' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:5563]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_a_upsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:3603]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_command_fifo' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/generic_baseblocks_v2_1_vl_rfs.v:655]
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_command_fifo' (2#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/generic_baseblocks_v2_1_vl_rfs.v:655]
INFO: [Synth 8-6157] synthesizing module 'generic_baseblocks_v2_1_0_command_fifo__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/generic_baseblocks_v2_1_vl_rfs.v:655]
INFO: [Synth 8-6155] done synthesizing module 'generic_baseblocks_v2_1_0_command_fifo__parameterized0' (2#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/generic_baseblocks_v2_1_vl_rfs.v:655]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_a_upsizer' (3#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:3603]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_r_upsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:4653]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_r_upsizer' (4#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:4653]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axi_register_slice' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:3726]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (5#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (6#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice' (7#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized0' (7#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized1' (7#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized2' (7#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axi_register_slice' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:3726]
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_25_axi_register_slice' is unconnected for instance 'mi_register_slice_inst' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:8475]
WARNING: [Synth 8-7023] instance 'mi_register_slice_inst' of module 'axi_register_slice_v2_1_25_axi_register_slice' has 93 connections declared, but only 92 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:8475]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_a_upsizer__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:3603]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_a_upsizer__parameterized0' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:3603]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axi_register_slice__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:3726]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:60]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized3' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized3' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized4' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized4' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized5' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized5' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized6' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axic_register_slice__parameterized6' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1498]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_25_axi_register_slice__parameterized0' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:3726]
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_25_axi_register_slice' is unconnected for instance 'si_register_slice_inst' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7379]
WARNING: [Synth 8-7023] instance 'si_register_slice_inst' of module 'axi_register_slice_v2_1_25_axi_register_slice' has 93 connections declared, but only 92 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7379]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_axi_upsizer' (9#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7038]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_top' (10#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462]
INFO: [Synth 8-6155] done synthesizing module 'xlnx_axi_dwidth_converter_dm_master' (11#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/synth/xlnx_axi_dwidth_converter_dm_master.v:58]
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_25_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_25_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlock[1] in module axi_dwidth_converter_v2_1_25_axi_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlock[1] in module axi_dwidth_converter_v2_1_25_axi_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_aresetn in module axi_dwidth_converter_v2_1_25_axi_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_aclk in module axi_dwidth_converter_v2_1_25_axi_upsizer is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5855 ; free virtual = 13134
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5860 ; free virtual = 13138
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5860 ; free virtual = 13138
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5859 ; free virtual = 13136
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master_ooc.xdc] for cell 'inst'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2944.527 ; gain = 0.000 ; free physical = 5757 ; free virtual = 13036
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2944.527 ; gain = 0.000 ; free physical = 5757 ; free virtual = 13035
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5829 ; free virtual = 13108
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5829 ; free virtual = 13108
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5829 ; free virtual = 13108
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5827 ; free virtual = 13107
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 8 Bit Adders := 4
2 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 4
2 Input 4 Bit Adders := 2
2 Input 3 Bit Adders := 4
+---Registers :
73 Bit Registers := 2
68 Bit Registers := 2
67 Bit Registers := 2
64 Bit Registers := 1
62 Bit Registers := 2
41 Bit Registers := 2
37 Bit Registers := 2
30 Bit Registers := 2
8 Bit Registers := 19
6 Bit Registers := 2
5 Bit Registers := 4
3 Bit Registers := 5
2 Bit Registers := 11
1 Bit Registers := 59
+---Muxes :
2 Input 73 Bit Muxes := 2
2 Input 68 Bit Muxes := 2
2 Input 41 Bit Muxes := 2
2 Input 37 Bit Muxes := 2
2 Input 32 Bit Muxes := 9
2 Input 8 Bit Muxes := 22
8 Input 8 Bit Muxes := 4
2 Input 3 Bit Muxes := 11
8 Input 3 Bit Muxes := 6
2 Input 2 Bit Muxes := 9
2 Input 1 Bit Muxes := 61
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-3936] Found unconnected internal register 'gen_upsizer.gen_full_upsizer.axi_upsizer_inst/USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst/r.r_pipe/m_payload_i_reg' and it is trimmed from '68' to '67' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_master/hdl/axi_register_slice_v2_1_vl_rfs.v:1731]
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5801 ; free virtual = 13085
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5696 ; free virtual = 12980
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5678 ; free virtual = 12962
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5679 ; free virtual = 12963
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5665 ; free virtual = 12960
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5665 ; free virtual = 12960
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5665 ; free virtual = 12960
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5665 ; free virtual = 12960
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5665 ; free virtual = 12960
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5665 ; free virtual = 12960
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Dynamic Shift Register Report:
+------------+-------------------------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
+------------+-------------------------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl | USE_RTL_FIFO.data_srl_reg[31] | 6 | 6 | 0 | 6 | 0 | 0 | 0 |
|dsrl__1 | USE_RTL_FIFO.data_srl_reg[31] | 30 | 30 | 0 | 30 | 0 | 0 | 0 |
|dsrl__4 | USE_RTL_FIFO.data_srl_reg[31] | 30 | 30 | 0 | 30 | 0 | 0 | 0 |
+------------+-------------------------------+--------+------------+--------+---------+--------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+--------+------+
| |Cell |Count |
+------+--------+------+
|1 |LUT1 | 5|
|2 |LUT2 | 23|
|3 |LUT3 | 106|
|4 |LUT4 | 55|
|5 |LUT5 | 137|
|6 |LUT6 | 217|
|7 |SRLC32E | 68|
|8 |FDRE | 621|
|9 |FDSE | 4|
+------+--------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 2944.527 ; gain = 78.828 ; free physical = 5665 ; free virtual = 12960
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2944.527 ; gain = 0.000 ; free physical = 5726 ; free virtual = 13021
Synthesis Optimization Complete : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 2944.535 ; gain = 78.828 ; free physical = 5726 ; free virtual = 13021
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2944.535 ; gain = 0.000 ; free physical = 5812 ; free virtual = 13107
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2944.535 ; gain = 0.000 ; free physical = 5751 ; free virtual = 13046
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: 49a12aa6
INFO: [Common 17-83] Releasing license: Synthesis
59 Infos, 28 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2944.535 ; gain = 86.840 ; free physical = 5941 ; free virtual = 13236
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/xlnx_axi_dwidth_converter_dm_master.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_dwidth_converter_dm_master, cache-ID = 15ef9eb66837654a
INFO: [Coretcl 2-1174] Renamed 15 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/xlnx_axi_dwidth_converter_dm_master.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_dwidth_converter_dm_master_utilization_synth.rpt -pb xlnx_axi_dwidth_converter_dm_master_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:07:38 2022...
|
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
if [ -z "$PATH" ]; then
PATH=/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64:/home/monir/Software/Vivado/2021.2/bin
else
PATH=/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64:/home/monir/Software/Vivado/2021.2/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
EAStep vivado -log xlnx_axi_dwidth_converter_dm_master.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_master.tcl
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:06:47 2022
# Process ID: 45332
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1
# Command line: vivado -log xlnx_axi_dwidth_converter_dm_master.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_master.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/xlnx_axi_dwidth_converter_dm_master.vds
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/xlnx_axi_dwidth_converter_dm_master.runs/xlnx_axi_dwidth_converter_dm_master_synth_1/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 3687.247 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source xlnx_axi_dwidth_converter_dm_master.tcl -notrace
|
PROJECT:=xlnx_axi_dwidth_converter_dm_slave
include ../common.mk
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:07:46 2022
# Process ID: 45498
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave
# Command line: vivado -mode batch -source tcl/run.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/vivado.log
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 3689.370 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source tcl/run.tcl
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:07:46 2022
# Process ID: 45498
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave
# Command line: vivado -mode batch -source tcl/run.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/vivado.log
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 3689.370 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source tcl/run.tcl
# set partNumber $::env(XILINX_PART)
# set boardName $::env(XILINX_BOARD)
# set ipName xlnx_axi_dwidth_converter_dm_slave
# create_project $ipName . -force -part $partNumber
# set_property board_part $boardName [current_project]
# create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/monir/Software/Vivado/2021.2/data/ip'.
WARNING: [IP_Flow 19-4832] The IP name 'xlnx_axi_dwidth_converter_dm_slave' you have specified is long. The Windows operating system has path length limitations. It is recommended you use shorter names to reduce the likelihood of issues.
# set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {6} CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName]
# generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_dwidth_converter_dm_slave'...
# generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_dwidth_converter_dm_slave'...
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc'
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_dwidth_converter_dm_slave'...
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
INFO: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_dwidth_converter_dm_slave'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_dwidth_converter_dm_slave'...
# create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
# launch_run -jobs 8 ${ipName}_synth_1
[Tue Sep 20 00:08:00 2022] Launched xlnx_axi_dwidth_converter_dm_slave_synth_1...
Run output will be captured here: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/runme.log
# wait_on_run ${ipName}_synth_1
[Tue Sep 20 00:08:00 2022] Waiting for xlnx_axi_dwidth_converter_dm_slave_synth_1 to finish...
*** Running vivado
with args -log xlnx_axi_dwidth_converter_dm_slave.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_slave.tcl
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xlnx_axi_dwidth_converter_dm_slave.tcl -notrace
Command: synth_design -top xlnx_axi_dwidth_converter_dm_slave -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 45600
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 4872 ; free virtual = 12175
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'xlnx_axi_dwidth_converter_dm_slave' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/synth/xlnx_axi_dwidth_converter_dm_slave.v:58]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_axi_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2380]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_b_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1251]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_b_downsizer' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1251]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_a_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_24_axic_fifo' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_24_fifo_gen' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (2#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_24_fifo_gen' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_24_axic_fifo' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_24_axic_fifo__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_24_fifo_gen__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_24_fifo_gen__parameterized0' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_24_axic_fifo__parameterized0' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64]
WARNING: [Synth 8-6014] Unused sequential element cmd_empty_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1053]
WARNING: [Synth 8-6014] Unused sequential element cmd_depth_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1054]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_a_downsizer' (22#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_w_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2016]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_w_downsizer' (23#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2016]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_a_downsizer__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64]
WARNING: [Synth 8-6014] Unused sequential element cmd_b_push_block_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:976]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_a_downsizer__parameterized0' (23#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_r_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1533]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_r_downsizer' (24#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1533]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_axi_downsizer' (25#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2380]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_top' (26#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462]
INFO: [Synth 8-6155] done synthesizing module 'xlnx_axi_dwidth_converter_dm_slave' (27#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/synth/xlnx_axi_dwidth_converter_dm_slave.v:58]
WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[5] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[5] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[5] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[4] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[3] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[2] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[1] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[0] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[4] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[4] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[4] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[4] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load
WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load
WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[4] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[4] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[4] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[4] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[4] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 5824 ; free virtual = 13128
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 5829 ; free virtual = 13133
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 5829 ; free virtual = 13133
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 5823 ; free virtual = 13127
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc] for cell 'inst'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc]
INFO: [Project 1-1714] 3 XPM XDC files have been applied to the design.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2948.531 ; gain = 0.000 ; free physical = 5728 ; free virtual = 13032
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2948.531 ; gain = 0.000 ; free physical = 5728 ; free virtual = 13032
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5797 ; free virtual = 13101
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5797 ; free virtual = 13101
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc, line 9).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_WRITE.write_addr_inst /\USE_B_CHANNEL.cmd_b_queue /inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_WRITE.write_addr_inst /cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_READ.read_addr_inst /cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5797 ; free virtual = 13101
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft'
INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
invalid | 00 | 00
stage1_valid | 10 | 10
both_stages_valid | 11 | 11
stage2_valid | 01 | 01
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5792 ; free virtual = 13097
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 2
2 Input 8 Bit Adders := 7
3 Input 8 Bit Adders := 2
2 Input 6 Bit Adders := 2
2 Input 5 Bit Adders := 6
2 Input 3 Bit Adders := 4
+---XORs :
2 Input 1 Bit XORs := 60
+---Registers :
32 Bit Registers := 10
26 Bit Registers := 4
11 Bit Registers := 2
9 Bit Registers := 2
8 Bit Registers := 13
7 Bit Registers := 2
6 Bit Registers := 6
5 Bit Registers := 14
4 Bit Registers := 9
3 Bit Registers := 10
2 Bit Registers := 11
1 Bit Registers := 62
+---Muxes :
8 Input 32 Bit Muxes := 2
2 Input 32 Bit Muxes := 7
2 Input 11 Bit Muxes := 2
2 Input 8 Bit Muxes := 11
8 Input 7 Bit Muxes := 2
8 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 6
8 Input 3 Bit Muxes := 4
2 Input 2 Bit Muxes := 44
4 Input 2 Bit Muxes := 3
5 Input 2 Bit Muxes := 3
3 Input 1 Bit Muxes := 3
2 Input 1 Bit Muxes := 27
4 Input 1 Bit Muxes := 7
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5762 ; free virtual = 13072
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 9 | RAM32M x 2 |
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 |
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 |
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5657 ; free virtual = 12968
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5616 ; free virtual = 12926
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 9 | RAM32M x 2 |
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 |
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 |
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5604 ; free virtual = 12915
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12915
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |CARRY4 | 18|
|2 |LUT1 | 51|
|3 |LUT2 | 164|
|4 |LUT3 | 113|
|5 |LUT4 | 140|
|6 |LUT5 | 126|
|7 |LUT6 | 319|
|8 |RAM32M | 10|
|9 |RAM32X1D | 4|
|10 |FDCE | 69|
|11 |FDPE | 33|
|12 |FDRE | 639|
|13 |FDSE | 5|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1604 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2948.531 ; gain = 0.000 ; free physical = 5666 ; free virtual = 12978
Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2948.539 ; gain = 82.828 ; free physical = 5666 ; free virtual = 12978
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2948.539 ; gain = 0.000 ; free physical = 5755 ; free virtual = 13068
INFO: [Netlist 29-17] Analyzing 32 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2948.539 ; gain = 0.000 ; free physical = 5689 ; free virtual = 12999
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 14 instances were transformed.
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 10 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete, checksum: 503b1bae
INFO: [Common 17-83] Releasing license: Synthesis
44 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:38 . Memory (MB): peak = 2948.539 ; gain = 90.840 ; free physical = 5902 ; free virtual = 13214
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/xlnx_axi_dwidth_converter_dm_slave.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_dwidth_converter_dm_slave, cache-ID = d3420769e5b1fbda
INFO: [Coretcl 2-1174] Renamed 58 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/xlnx_axi_dwidth_converter_dm_slave.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_dwidth_converter_dm_slave_utilization_synth.rpt -pb xlnx_axi_dwidth_converter_dm_slave_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:08:56 2022...
[Tue Sep 20 00:08:59 2022] xlnx_axi_dwidth_converter_dm_slave_synth_1 finished
wait_on_runs: Time (s): cpu = 00:01:01 ; elapsed = 00:01:00 . Memory (MB): peak = 2909.055 ; gain = 0.000 ; free physical = 7096 ; free virtual = 14407
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:08:59 2022...
|
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="56" Path="/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
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<Option Name="Part" Val="xc7k325tffg900-2"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2021.2"/>
<Option Name="SimulatorVersionModelSim" Val="2020.4"/>
<Option Name="SimulatorVersionQuesta" Val="2020.4"/>
<Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
<Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
<Option Name="SimulatorVersionRiviera" Val="2020.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
<Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
<Option Name="BoardPart" Val="digilentinc.com:genesys2:part0:1.1"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="genesys2"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="xlnx_axi_dwidth_converter_dm_slave" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_dwidth_converter_dm_slave" RelGenDir="$PGENDIR/xlnx_axi_dwidth_converter_dm_slave">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_dwidth_converter_dm_slave"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="xlnx_axi_dwidth_converter_dm_slave_synth_1" Type="Ft3:Synth" SrcSet="xlnx_axi_dwidth_converter_dm_slave" Part="xc7k325tffg900-2" ConstrsSet="xlnx_axi_dwidth_converter_dm_slave" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/xlnx_axi_dwidth_converter_dm_slave_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/xlnx_axi_dwidth_converter_dm_slave_synth_1">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Desc>Default settings for Implementation.</Desc>
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="xlnx_axi_dwidth_converter_dm_slave_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xlnx_axi_dwidth_converter_dm_slave" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="xlnx_axi_dwidth_converter_dm_slave_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/xlnx_axi_dwidth_converter_dm_slave_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Desc>Default settings for Implementation.</Desc>
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
|
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_axi_dwidth_converter_dm_slave
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.SI_DATA_WIDTH {64} CONFIG.SI_ID_WIDTH {6} CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1
|
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</spirit:design>
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333573:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323934382e3533394d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:39302e3834304d42:00:00
eof:1135122403
|
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
|
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="xlnx_axi_dwidth_converter_dm_slave_synth_1" LaunchDir="/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
|
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="monir" Host="ubuntu" Pid="45550" HostCore="4" HostMemory="16273612">
</Process>
</ProcessHandle>
|
# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# IP: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci
# IP: The module: 'xlnx_axi_dwidth_converter_dm_slave' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_clocks.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_dwidth_converter_dm_slave'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_dwidth_converter_dm_slave'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# IP: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.srcs/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci
# IP: The module: 'xlnx_axi_dwidth_converter_dm_slave' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_clocks.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_dwidth_converter_dm_slave'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_dwidth_converter_dm_slave'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="xlnx_axi_dwidth_converter_dm_slave_synth_1" LaunchPart="xc7k325tffg900-2" LaunchTime="1663646880">
<File Type="VDS-TIMING-PB" Name="xlnx_axi_dwidth_converter_dm_slave_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="xlnx_axi_dwidth_converter_dm_slave_timing_summary_synth.rpt"/>
<File Type="RDS-RDS" Name="xlnx_axi_dwidth_converter_dm_slave.vds"/>
<File Type="REPORTS-TCL" Name="xlnx_axi_dwidth_converter_dm_slave_reports.tcl"/>
<File Type="PA-TCL" Name="xlnx_axi_dwidth_converter_dm_slave.tcl"/>
<File Type="RDS-DCP" Name="xlnx_axi_dwidth_converter_dm_slave.dcp"/>
<File Type="RDS-PROPCONSTRS" Name="xlnx_axi_dwidth_converter_dm_slave_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="xlnx_axi_dwidth_converter_dm_slave_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="xlnx_axi_dwidth_converter_dm_slave_utilization_synth.pb"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_dwidth_converter_dm_slave">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_dwidth_converter_dm_slave"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_dwidth_converter_dm_slave">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_dwidth_converter_dm_slave"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
|
#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
vivado -log xlnx_axi_dwidth_converter_dm_slave.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_slave.tcl
|
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
|
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
cmd_exists()
{
command -v "$1" >/dev/null 2>&1
}
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if cmd_exists hostname
then
ISE_HOST=$(hostname)
elif cmd_exists uname
then
ISE_HOST=$(uname -n)
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
|
version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:32:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:32:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c6178695f6477696474685f636f6e7665727465725f76325f315f32355c786c6e785f6178695f6477696474685f636f6e7665727465725f646d5f736c617665:636f72655f636f6e7461696e6572:66616c7365:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3530323165623737616539653464316162623862363830326563303333323833:506172656e742050412070726f6a656374204944:00
eof:436300918
|
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//
echo "This script was generated under a different operating system."
echo "Please update the PATH variable below, before executing this script"
exit
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64;/home/monir/Software/Vivado/2021.2/bin;";
} else {
PathVal = "/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64;/home/monir/Software/Vivado/2021.2/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
"-log xlnx_axi_dwidth_converter_dm_slave.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_slave.tcl" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
|
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
set PATH=%SYSTEMROOT%\system32;%PATH%
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
*** Running vivado
with args -log xlnx_axi_dwidth_converter_dm_slave.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_slave.tcl
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xlnx_axi_dwidth_converter_dm_slave.tcl -notrace
Command: synth_design -top xlnx_axi_dwidth_converter_dm_slave -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 45600
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 4872 ; free virtual = 12175
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'xlnx_axi_dwidth_converter_dm_slave' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/synth/xlnx_axi_dwidth_converter_dm_slave.v:58]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_axi_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2380]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_b_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1251]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_b_downsizer' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1251]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_a_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_24_axic_fifo' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_24_fifo_gen' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (2#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_24_fifo_gen' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_24_axic_fifo' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_24_axic_fifo__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_data_fifo_v2_1_24_fifo_gen__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_24_fifo_gen__parameterized0' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:168]
INFO: [Synth 8-6155] done synthesizing module 'axi_data_fifo_v2_1_24_axic_fifo__parameterized0' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_data_fifo_v2_1_vl_rfs.v:64]
WARNING: [Synth 8-6014] Unused sequential element cmd_empty_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1053]
WARNING: [Synth 8-6014] Unused sequential element cmd_depth_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1054]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_a_downsizer' (22#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_w_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2016]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_w_downsizer' (23#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2016]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_a_downsizer__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64]
WARNING: [Synth 8-6014] Unused sequential element cmd_b_push_block_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:976]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_a_downsizer__parameterized0' (23#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:64]
INFO: [Synth 8-6157] synthesizing module 'axi_dwidth_converter_v2_1_25_r_downsizer' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1533]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_r_downsizer' (24#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:1533]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_axi_downsizer' (25#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:2380]
INFO: [Synth 8-6155] done synthesizing module 'axi_dwidth_converter_v2_1_25_top' (26#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:14462]
INFO: [Synth 8-6155] done synthesizing module 'xlnx_axi_dwidth_converter_dm_slave' (27#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/synth/xlnx_axi_dwidth_converter_dm_slave.v:58]
WARNING: [Synth 8-7129] Port ALMOST_FULL_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ALMOST_EMPTY_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_ACK_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port VALID_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port OVERFLOW_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port UNDERFLOW_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[5] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[4] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[3] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[2] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[1] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DATA_COUNT_I[0] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[5] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[4] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[3] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[2] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[1] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_DATA_COUNT_I[0] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[5] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[4] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[3] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[2] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[1] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_DATA_COUNT_I[0] in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port SBITERR_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port DBITERR_I in module output_blk__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST_FULL_FF in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_RST in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SAFETY_CKT_WR_RST in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[4] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[3] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[2] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[1] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS2[0] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[4] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[3] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[2] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[1] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS3[0] in module wr_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module wr_bin_cntr is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_EN_INTO_LOGIC in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_RST_INTO_LOGIC in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_EN in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_RST_BUSY in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port EMPTY in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port ALMOST_EMPTY in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[4] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[3] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[2] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[1] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH[0] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[4] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[3] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[2] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[1] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_ASSERT[0] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[4] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[3] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[2] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[1] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_FULL_THRESH_NEGATE[0] in module wr_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module rd_fwft is either unconnected or has no load
WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_fwft is either unconnected or has no load
WARNING: [Synth 8-7129] Port RAM_ALMOST_EMPTY in module rd_fwft is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SAFETY_CKT_RD_RST in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[4] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[3] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[2] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[1] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_PNTR_PLUS2[0] in module rd_status_flags_ss is either unconnected or has no load
WARNING: [Synth 8-7129] Port SRST in module rd_bin_cntr is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_EN_INTO_LOGIC in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_RST_INTO_LOGIC in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port RD_RST_BUSY in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port RST_FULL_FF in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port ALMOST_FULL_FB in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port FULL in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[4] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[3] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[2] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[1] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port WR_PNTR_PLUS1_RD[0] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[4] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[3] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[2] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[1] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH[0] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[4] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[3] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[2] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[1] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_ASSERT[0] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[4] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[3] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[2] in module rd_logic is either unconnected or has no load
WARNING: [Synth 8-7129] Port PROG_EMPTY_THRESH_NEGATE[1] in module rd_logic is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 5824 ; free virtual = 13128
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 5829 ; free virtual = 13133
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 5829 ; free virtual = 13133
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2865.703 ; gain = 0.000 ; free physical = 5823 ; free virtual = 13127
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.gen/sources_1/ip/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave_ooc.xdc] for cell 'inst'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc]
INFO: [Project 1-1714] 3 XPM XDC files have been applied to the design.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2948.531 ; gain = 0.000 ; free physical = 5728 ; free virtual = 13032
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2948.531 ; gain = 0.000 ; free physical = 5728 ; free virtual = 13032
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5797 ; free virtual = 13101
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5797 ; free virtual = 13101
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/dont_touch.xdc, line 9).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_WRITE.write_addr_inst /\USE_B_CHANNEL.cmd_b_queue /inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_WRITE.write_addr_inst /cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst /\USE_READ.read_addr_inst /cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5797 ; free virtual = 13101
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft'
INFO: [Synth 8-6159] Found Keep on FSM register 'gpregsm1.curr_fwft_state_reg' in module 'rd_fwft', re-encoding will not be performed
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
invalid | 00 | 00
stage1_valid | 10 | 10
both_stages_valid | 11 | 11
stage2_valid | 01 | 01
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5792 ; free virtual = 13097
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 2
2 Input 8 Bit Adders := 7
3 Input 8 Bit Adders := 2
2 Input 6 Bit Adders := 2
2 Input 5 Bit Adders := 6
2 Input 3 Bit Adders := 4
+---XORs :
2 Input 1 Bit XORs := 60
+---Registers :
32 Bit Registers := 10
26 Bit Registers := 4
11 Bit Registers := 2
9 Bit Registers := 2
8 Bit Registers := 13
7 Bit Registers := 2
6 Bit Registers := 6
5 Bit Registers := 14
4 Bit Registers := 9
3 Bit Registers := 10
2 Bit Registers := 11
1 Bit Registers := 62
+---Muxes :
8 Input 32 Bit Muxes := 2
2 Input 32 Bit Muxes := 7
2 Input 11 Bit Muxes := 2
2 Input 8 Bit Muxes := 11
8 Input 7 Bit Muxes := 2
8 Input 5 Bit Muxes := 2
2 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 6
8 Input 3 Bit Muxes := 4
2 Input 2 Bit Muxes := 44
4 Input 2 Bit Muxes := 3
5 Input 2 Bit Muxes := 3
3 Input 1 Bit Muxes := 3
2 Input 1 Bit Muxes := 27
4 Input 1 Bit Muxes := 7
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5762 ; free virtual = 13072
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 9 | RAM32M x 2 |
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 |
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 |
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5657 ; free virtual = 12968
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5616 ; free virtual = 12926
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 9 | RAM32M x 2 |
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 |
|inst/\gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 32 x 26 | RAM32M x 5 |
+------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+----------------+----------------------+-------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5604 ; free virtual = 12915
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12915
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |CARRY4 | 18|
|2 |LUT1 | 51|
|3 |LUT2 | 164|
|4 |LUT3 | 113|
|5 |LUT4 | 140|
|6 |LUT5 | 126|
|7 |LUT6 | 319|
|8 |RAM32M | 10|
|9 |RAM32X1D | 4|
|10 |FDCE | 69|
|11 |FDPE | 33|
|12 |FDRE | 639|
|13 |FDSE | 5|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2948.531 ; gain = 82.828 ; free physical = 5602 ; free virtual = 12914
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1604 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2948.531 ; gain = 0.000 ; free physical = 5666 ; free virtual = 12978
Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 2948.539 ; gain = 82.828 ; free physical = 5666 ; free virtual = 12978
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2948.539 ; gain = 0.000 ; free physical = 5755 ; free virtual = 13068
INFO: [Netlist 29-17] Analyzing 32 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2948.539 ; gain = 0.000 ; free physical = 5689 ; free virtual = 12999
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 14 instances were transformed.
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 10 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances
Synth Design complete, checksum: 503b1bae
INFO: [Common 17-83] Releasing license: Synthesis
44 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:38 . Memory (MB): peak = 2948.539 ; gain = 90.840 ; free physical = 5902 ; free virtual = 13214
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/xlnx_axi_dwidth_converter_dm_slave.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_dwidth_converter_dm_slave, cache-ID = d3420769e5b1fbda
INFO: [Coretcl 2-1174] Renamed 58 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/xlnx_axi_dwidth_converter_dm_slave.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_dwidth_converter_dm_slave_utilization_synth.rpt -pb xlnx_axi_dwidth_converter_dm_slave_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:08:56 2022...
|
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
if [ -z "$PATH" ]; then
PATH=/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64:/home/monir/Software/Vivado/2021.2/bin
else
PATH=/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64:/home/monir/Software/Vivado/2021.2/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
EAStep vivado -log xlnx_axi_dwidth_converter_dm_slave.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_slave.tcl
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:08:02 2022
# Process ID: 45591
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1
# Command line: vivado -log xlnx_axi_dwidth_converter_dm_slave.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_dwidth_converter_dm_slave.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/xlnx_axi_dwidth_converter_dm_slave.vds
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/xlnx_axi_dwidth_converter_dm_slave.runs/xlnx_axi_dwidth_converter_dm_slave_synth_1/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 3688.895 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source xlnx_axi_dwidth_converter_dm_slave.tcl -notrace
|
PROJECT:=xlnx_axi_gpio
include ../common.mk
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:10:24 2022
# Process ID: 46106
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio
# Command line: vivado -mode batch -source tcl/run.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/vivado.log
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 1200.000 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source tcl/run.tcl
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:10:24 2022
# Process ID: 46106
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio
# Command line: vivado -mode batch -source tcl/run.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/vivado.log
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 1200.000 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source tcl/run.tcl
# set partNumber $::env(XILINX_PART)
# set boardName $::env(XILINX_BOARD)
# set ipName xlnx_axi_gpio
# create_project $ipName . -force -part $partNumber
# set_property board_part $boardName [current_project]
# create_ip -name axi_gpio -vendor xilinx.com -library ip -module_name $ipName
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/monir/Software/Vivado/2021.2/data/ip'.
# set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.C_INTERRUPT_PRESENT {0}] [get_ips $ipName]
# generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_gpio'...
# generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_gpio'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_gpio'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_gpio'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_gpio'...
# create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
# launch_run -jobs 8 ${ipName}_synth_1
[Tue Sep 20 00:10:38 2022] Launched xlnx_axi_gpio_synth_1...
Run output will be captured here: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/runme.log
# wait_on_run ${ipName}_synth_1
[Tue Sep 20 00:10:39 2022] Waiting for xlnx_axi_gpio_synth_1 to finish...
*** Running vivado
with args -log xlnx_axi_gpio.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_gpio.tcl
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xlnx_axi_gpio.tcl -notrace
Command: synth_design -top xlnx_axi_gpio -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 46271
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5275 ; free virtual = 12672
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'xlnx_axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:87]
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_GPIO_WIDTH bound to: 8 - type: integer
Parameter C_GPIO2_WIDTH bound to: 8 - type: integer
Parameter C_ALL_INPUTS bound to: 0 - type: integer
Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS bound to: 0 - type: integer
Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer
Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer
Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000
Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111
Parameter C_IS_DUAL bound to: 1 - type: integer
Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000
Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111
INFO: [Synth 8-3491] module 'axi_gpio' declared at '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1265' bound to instance 'U0' of component 'axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:175]
INFO: [Synth 8-638] synthesizing module 'axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (2#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (3#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (4#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:835]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (5#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:106]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (6#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (7#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
INFO: [Synth 8-256] done synthesizing module 'xlnx_axi_gpio' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:87]
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_in in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[1] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[2] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[3] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[4] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[7] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[8] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[0] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[1] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[2] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[3] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[0] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[1] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[2] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[3] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[4] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[7] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[8] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus_RNW in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[3] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[2] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[1] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[0] in module slave_attachment is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 4732 ; free virtual = 12130
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5594 ; free virtual = 13006
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5594 ; free virtual = 13006
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5587 ; free virtual = 13003
INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5558 ; free virtual = 12965
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 96 instances were transformed.
FDR => FDRE: 96 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5558 ; free virtual = 12964
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5633 ; free virtual = 13026
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5632 ; free virtual = 13025
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5633 ; free virtual = 13026
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 0001 | 00
iSTATE | 0010 | 01
iSTATE0 | 0100 | 10
iSTATE1 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5634 ; free virtual = 13028
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
32 Bit Registers := 2
9 Bit Registers := 1
8 Bit Registers := 6
4 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 18
+---Muxes :
2 Input 9 Bit Muxes := 1
2 Input 8 Bit Muxes := 5
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 5
2 Input 2 Bit Muxes := 3
3 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 28
4 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port s_axi_wdata[31] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[30] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[29] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[28] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[27] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[26] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[25] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[24] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[23] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[22] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[21] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[20] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[19] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[18] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[17] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[16] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[15] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[14] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[13] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[12] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[11] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[10] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[9] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[8] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[3] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[2] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[1] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[0] in module axi_gpio is either unconnected or has no load
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5613 ; free virtual = 13010
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5481 ; free virtual = 12909
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5464 ; free virtual = 12893
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5458 ; free virtual = 12892
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT1 | 2|
|2 |LUT2 | 9|
|3 |LUT3 | 9|
|4 |LUT4 | 4|
|5 |LUT5 | 43|
|6 |LUT6 | 16|
|7 |FDR | 64|
|8 |FDRE | 95|
|9 |FDSE | 17|
+------+-----+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 29 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5552 ; free virtual = 12948
Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.723 ; gain = 32.016 ; free physical = 5552 ; free virtual = 12948
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2897.723 ; gain = 0.000 ; free physical = 5548 ; free virtual = 12945
INFO: [Netlist 29-17] Analyzing 64 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2897.723 ; gain = 0.000 ; free physical = 5580 ; free virtual = 12982
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 64 instances were transformed.
FDR => FDRE: 64 instances
Synth Design complete, checksum: c9e1738b
INFO: [Common 17-83] Releasing license: Synthesis
123 Infos, 71 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2897.723 ; gain = 40.027 ; free physical = 5766 ; free virtual = 13171
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_gpio, cache-ID = 71108036a61446df
INFO: [Coretcl 2-1174] Renamed 7 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_gpio_utilization_synth.rpt -pb xlnx_axi_gpio_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:11:22 2022...
[Tue Sep 20 00:11:26 2022] xlnx_axi_gpio_synth_1 finished
wait_on_runs: Time (s): cpu = 00:00:50 ; elapsed = 00:00:47 . Memory (MB): peak = 2909.051 ; gain = 0.000 ; free physical = 6906 ; free virtual = 14298
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:11:26 2022...
|
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="56" Path="/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="2ba0ab3dde42477e96c5ecd98edf7054"/>
<Option Name="Part" Val="xc7k325tffg900-2"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2021.2"/>
<Option Name="SimulatorVersionModelSim" Val="2020.4"/>
<Option Name="SimulatorVersionQuesta" Val="2020.4"/>
<Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
<Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
<Option Name="SimulatorVersionRiviera" Val="2020.10"/>
<Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
<Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
<Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
<Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
<Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
<Option Name="BoardPart" Val="digilentinc.com:genesys2:part0:1.1"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="genesys2"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="xlnx_axi_gpio" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_gpio" RelGenDir="$PGENDIR/xlnx_axi_gpio">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_gpio"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="xlnx_axi_gpio_synth_1" Type="Ft3:Synth" SrcSet="xlnx_axi_gpio" Part="xc7k325tffg900-2" ConstrsSet="xlnx_axi_gpio" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/xlnx_axi_gpio_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/xlnx_axi_gpio_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="xlnx_axi_gpio_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xlnx_axi_gpio" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="xlnx_axi_gpio_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/xlnx_axi_gpio_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
|
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_axi_gpio
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_gpio -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS_2 {1} CONFIG.C_INTERRUPT_PRESENT {0}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1
|
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>71108036a61446df</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>xlnx_axi_gpio</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_gpio" spirit:version="2.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS_2">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT">0x00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO2_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IS_DUAL">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xlnx_axi_gpio</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:genesys2:part0:1.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">71108036a61446df</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3358895 $</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">aaec294b</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">30</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">27</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
|
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
// Date : Tue Sep 20 00:11:21 2022
// Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_gpio_sim_netlist.v
// Design : xlnx_axi_gpio
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(reg1,
reg3,
reg2,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
gpio_io_o,
gpio_io_t,
ip2bus_wrack_i,
ip2bus_rdack_i,
\Dual.gpio2_OE_reg[0]_0 ,
\Dual.gpio2_Data_In_reg[0]_0 ,
s_axi_aclk,
Read_Reg2_In,
SS,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ,
Q,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
gpio2_io_i,
E,
s_axi_wdata,
\Dual.gpio_OE_reg[0]_0 ,
\Dual.gpio2_OE_reg[0]_1 );
output [7:0]reg1;
output [7:0]reg3;
output [7:0]reg2;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
output ip2bus_wrack_i;
output ip2bus_rdack_i;
output [7:0]\Dual.gpio2_OE_reg[0]_0 ;
output [7:0]\Dual.gpio2_Data_In_reg[0]_0 ;
input s_axi_aclk;
input [0:7]Read_Reg2_In;
input [0:0]SS;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ;
input [0:0]Q;
input bus2ip_rnw;
input bus2ip_cs;
input [7:0]gpio_io_i;
input [7:0]gpio2_io_i;
input [0:0]E;
input [7:0]s_axi_wdata;
input [0:0]\Dual.gpio_OE_reg[0]_0 ;
input [0:0]\Dual.gpio2_OE_reg[0]_1 ;
wire Bus_RNW_reg;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ;
wire [7:0]\Dual.gpio2_Data_In_reg[0]_0 ;
wire [7:0]\Dual.gpio2_OE_reg[0]_0 ;
wire [0:0]\Dual.gpio2_OE_reg[0]_1 ;
wire [0:0]\Dual.gpio_OE_reg[0]_0 ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire GPIO_xferAck_i;
wire [0:0]Q;
wire [0:7]Read_Reg2_In;
wire Read_Reg_Rst;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire [7:0]gpio2_io_i;
wire [0:7]gpio2_io_i_d2;
wire [0:7]gpio_Data_In;
wire [7:0]gpio_io_i;
wire [0:7]gpio_io_i_d2;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i;
wire [7:0]reg1;
wire [7:0]reg2;
wire [7:0]reg3;
wire s_axi_aclk;
wire [7:0]s_axi_wdata;
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[0]),
.Q(reg3[7]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[1]),
.Q(reg3[6]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[2]),
.Q(reg3[5]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[3]),
.Q(reg3[4]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[4]),
.Q(reg3[3]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[5]),
.Q(reg3[2]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[6]),
.Q(reg3[1]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[7]),
.Q(reg3[0]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1
(.I0(gpio_Data_In[0]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[7]),
.I4(gpio_io_t[7]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0 ),
.Q(reg1[7]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1
(.I0(gpio_Data_In[0]),
.I1(gpio_io_t[7]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[7]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0 ),
.Q(reg2[7]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1
(.I0(gpio_Data_In[1]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[6]),
.I4(gpio_io_t[6]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0 ),
.Q(reg1[6]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1
(.I0(gpio_Data_In[1]),
.I1(gpio_io_t[6]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[6]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0 ),
.Q(reg2[6]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1
(.I0(gpio_Data_In[2]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[5]),
.I4(gpio_io_t[5]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0 ),
.Q(reg1[5]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1
(.I0(gpio_Data_In[2]),
.I1(gpio_io_t[5]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[5]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0 ),
.Q(reg2[5]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1
(.I0(gpio_Data_In[3]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[4]),
.I4(gpio_io_t[4]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0 ),
.Q(reg1[4]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1
(.I0(gpio_Data_In[3]),
.I1(gpio_io_t[4]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[4]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0 ),
.Q(reg2[4]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1
(.I0(gpio_Data_In[4]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[3]),
.I4(gpio_io_t[3]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0 ),
.Q(reg1[3]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1
(.I0(gpio_Data_In[4]),
.I1(gpio_io_t[3]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[3]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0 ),
.Q(reg2[3]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1
(.I0(gpio_Data_In[5]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[2]),
.I4(gpio_io_t[2]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0 ),
.Q(reg1[2]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1
(.I0(gpio_Data_In[5]),
.I1(gpio_io_t[2]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[2]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0 ),
.Q(reg2[2]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1
(.I0(gpio_Data_In[6]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[1]),
.I4(gpio_io_t[1]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0 ),
.Q(reg1[1]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1
(.I0(gpio_Data_In[6]),
.I1(gpio_io_t[1]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[1]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0 ),
.Q(reg2[1]),
.R(Read_Reg_Rst));
LUT4 #(
.INIT(16'hEFFF))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_1
(.I0(GPIO_xferAck_i),
.I1(gpio_xferAck_Reg),
.I2(bus2ip_rnw),
.I3(bus2ip_cs),
.O(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2
(.I0(gpio_Data_In[7]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[0]),
.I4(gpio_io_t[0]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0 ),
.Q(reg1[0]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1
(.I0(gpio_Data_In[7]),
.I1(gpio_io_t[0]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[0]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0 ),
.Q(reg2[0]),
.R(Read_Reg_Rst));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \Dual.INPUT_DOUBLE_REGS4
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \Dual.INPUT_DOUBLE_REGS5
(.gpio2_io_i(gpio2_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3],gpio2_io_i_d2[4],gpio2_io_i_d2[5],gpio2_io_i_d2[6],gpio2_io_i_d2[7]}));
FDRE \Dual.gpio2_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[0]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [7]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[1]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [6]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[2]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [5]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[3]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [4]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[4]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [3]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[5]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [2]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[6]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [1]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[7]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [0]),
.R(1'b0));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[0]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[7]),
.Q(\Dual.gpio2_OE_reg[0]_0 [7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[1]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[6]),
.Q(\Dual.gpio2_OE_reg[0]_0 [6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[2]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[5]),
.Q(\Dual.gpio2_OE_reg[0]_0 [5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[3]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[4]),
.Q(\Dual.gpio2_OE_reg[0]_0 [4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[4]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[3]),
.Q(\Dual.gpio2_OE_reg[0]_0 [3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[5]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[2]),
.Q(\Dual.gpio2_OE_reg[0]_0 [2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[6]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[1]),
.Q(\Dual.gpio2_OE_reg[0]_0 [1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[7]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[0]),
.Q(\Dual.gpio2_OE_reg[0]_0 [0]),
.S(SS));
FDRE \Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(gpio_Data_In[0]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(gpio_Data_In[1]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(gpio_Data_In[2]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(gpio_Data_In[3]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(gpio_Data_In[4]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[5]),
.Q(gpio_Data_In[5]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[6]),
.Q(gpio_Data_In[6]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[7]),
.Q(gpio_Data_In[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[7]),
.Q(gpio_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[6]),
.Q(gpio_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[5]),
.Q(gpio_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[4]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[7]),
.Q(gpio_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[6]),
.Q(gpio_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[5]),
.Q(gpio_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[4]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[0]),
.Q(gpio_io_t[0]),
.S(SS));
LUT5 #(
.INIT(32'h00040448))
GPIO_DBus
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.O(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h04))
iGPIO_xferAck_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_cs),
.I2(gpio_xferAck_Reg),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
Bus_RNW_reg_reg_0,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 ,
E,
bus2ip_rnw_i_reg,
bus2ip_rnw_i_reg_0,
ip2bus_rdack_i_D1_reg,
ip2bus_wrack_i_D1_reg,
D,
Q,
s_axi_aclk,
\Dual.gpio_Data_Out_reg[0] ,
Bus_RNW_reg_reg_1,
s_axi_aresetn,
ip2bus_rdack_i_D1,
s_axi_arready,
s_axi_arready_0,
ip2bus_wrack_i_D1,
s_axi_awready,
\ip2bus_data_i_D1_reg[31] ,
reg1,
reg2,
reg3);
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
output Bus_RNW_reg_reg_0;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 ;
output [0:0]E;
output [0:0]bus2ip_rnw_i_reg;
output [0:0]bus2ip_rnw_i_reg_0;
output ip2bus_rdack_i_D1_reg;
output ip2bus_wrack_i_D1_reg;
output [8:0]D;
input Q;
input s_axi_aclk;
input [2:0]\Dual.gpio_Data_Out_reg[0] ;
input Bus_RNW_reg_reg_1;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input s_axi_arready;
input [3:0]s_axi_arready_0;
input ip2bus_wrack_i_D1;
input s_axi_awready;
input \ip2bus_data_i_D1_reg[31] ;
input [7:0]reg1;
input [7:0]reg2;
input [7:0]reg3;
wire Bus_RNW_reg_i_1_n_0;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire [8:0]D;
wire [2:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 ;
wire Q;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire cs_ce_clr;
wire \ip2bus_data_i_D1[24]_i_2_n_0 ;
wire \ip2bus_data_i_D1[25]_i_2_n_0 ;
wire \ip2bus_data_i_D1[26]_i_2_n_0 ;
wire \ip2bus_data_i_D1[27]_i_2_n_0 ;
wire \ip2bus_data_i_D1[28]_i_2_n_0 ;
wire \ip2bus_data_i_D1[29]_i_2_n_0 ;
wire \ip2bus_data_i_D1[30]_i_2_n_0 ;
wire \ip2bus_data_i_D1[31]_i_2_n_0 ;
wire \ip2bus_data_i_D1_reg[31] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_rdack_i_D1_reg;
wire ip2bus_wrack_i_D1;
wire ip2bus_wrack_i_D1_reg;
wire [7:0]reg1;
wire [7:0]reg2;
wire [7:0]reg3;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [3:0]s_axi_arready_0;
wire s_axi_awready;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(Bus_RNW_reg_reg_1),
.I1(Q),
.I2(Bus_RNW_reg_reg_0),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(Bus_RNW_reg_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hFD))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_3
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\Dual.gpio_Data_Out_reg[0] [2]),
.I2(\Dual.gpio_Data_Out_reg[0] [1]),
.O(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h10000000))
\Dual.gpio2_OE[0]_i_1
(.I0(Bus_RNW_reg_reg_1),
.I1(\Dual.gpio_Data_Out_reg[0] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\Dual.gpio_Data_Out_reg[0] [1]),
.I4(\Dual.gpio_Data_Out_reg[0] [0]),
.O(bus2ip_rnw_i_reg_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000100))
\Dual.gpio_Data_Out[0]_i_1
(.I0(Bus_RNW_reg_reg_1),
.I1(\Dual.gpio_Data_Out_reg[0] [1]),
.I2(\Dual.gpio_Data_Out_reg[0] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\Dual.gpio_Data_Out_reg[0] [0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h01000000))
\Dual.gpio_OE[0]_i_1
(.I0(Bus_RNW_reg_reg_1),
.I1(\Dual.gpio_Data_Out_reg[0] [1]),
.I2(\Dual.gpio_Data_Out_reg[0] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\Dual.gpio_Data_Out_reg[0] [0]),
.O(bus2ip_rnw_i_reg));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h1))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\Dual.gpio_Data_Out_reg[0] [1]),
.I1(\Dual.gpio_Data_Out_reg[0] [0]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_3),
.Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h4))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\Dual.gpio_Data_Out_reg[0] [1]),
.I1(\Dual.gpio_Data_Out_reg[0] [0]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_2),
.Q(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h4))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\Dual.gpio_Data_Out_reg[0] [0]),
.I1(\Dual.gpio_Data_Out_reg[0] [1]),
.O(ce_expnd_i_1));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_1),
.Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hEF))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(ip2bus_wrack_i_D1_reg),
.I1(ip2bus_rdack_i_D1_reg),
.I2(s_axi_aresetn),
.O(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(\Dual.gpio_Data_Out_reg[0] [1]),
.I1(\Dual.gpio_Data_Out_reg[0] [0]),
.O(ce_expnd_i_0));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(Q),
.I2(s_axi_aresetn),
.I3(ip2bus_rdack_i_D1_reg),
.I4(ip2bus_wrack_i_D1_reg),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h80))
\ip2bus_data_i_D1[0]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.O(D[8]));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[24]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[7]),
.I4(\ip2bus_data_i_D1[24]_i_2_n_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[24]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[7]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[7]),
.O(\ip2bus_data_i_D1[24]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[25]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[6]),
.I4(\ip2bus_data_i_D1[25]_i_2_n_0 ),
.O(D[6]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[25]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[6]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[6]),
.O(\ip2bus_data_i_D1[25]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[26]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[5]),
.I4(\ip2bus_data_i_D1[26]_i_2_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[26]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[5]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[5]),
.O(\ip2bus_data_i_D1[26]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[27]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[4]),
.I4(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.O(D[4]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[27]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[4]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[4]),
.O(\ip2bus_data_i_D1[27]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[28]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[3]),
.I4(\ip2bus_data_i_D1[28]_i_2_n_0 ),
.O(D[3]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[28]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[3]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[3]),
.O(\ip2bus_data_i_D1[28]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[29]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[2]),
.I4(\ip2bus_data_i_D1[29]_i_2_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[29]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[2]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[2]),
.O(\ip2bus_data_i_D1[29]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[30]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[1]),
.I4(\ip2bus_data_i_D1[30]_i_2_n_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[30]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[1]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[1]),
.O(\ip2bus_data_i_D1[30]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[31]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[0]),
.I4(\ip2bus_data_i_D1[31]_i_2_n_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[31]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[0]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[0]),
.O(\ip2bus_data_i_D1[31]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(s_axi_arready),
.I2(s_axi_arready_0[2]),
.I3(s_axi_arready_0[1]),
.I4(s_axi_arready_0[3]),
.I5(s_axi_arready_0[0]),
.O(ip2bus_rdack_i_D1_reg));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(s_axi_awready),
.I2(s_axi_arready_0[2]),
.I3(s_axi_arready_0[1]),
.I4(s_axi_arready_0[3]),
.I5(s_axi_arready_0[0]),
.O(ip2bus_wrack_i_D1_reg));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "1" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "kintex7" *) (* C_GPIO2_WIDTH = "8" *) (* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* sigis = "Clk" *) input s_axi_aclk;
(* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [7:0]gpio2_io_i;
output [7:0]gpio2_io_o;
output [7:0]gpio2_io_t;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_10;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire [0:31]GPIO_DBus;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire [0:7]Read_Reg2_In;
wire [6:6]bus2ip_addr;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:7]gpio2_Data_In;
wire [7:0]gpio2_io_i;
wire gpio_core_1_n_24;
wire gpio_core_1_n_43;
wire gpio_core_1_n_44;
wire gpio_core_1_n_45;
wire gpio_core_1_n_46;
wire gpio_core_1_n_47;
wire gpio_core_1_n_48;
wire gpio_core_1_n_49;
wire gpio_core_1_n_50;
wire [7:0]gpio_io_i;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i;
wire ip2bus_wrack_i_D1;
wire [24:31]reg1;
wire [24:31]reg2;
wire [24:31]reg3;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [30:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wvalid;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[7] = \<const0> ;
assign gpio2_io_t[6] = \<const0> ;
assign gpio2_io_t[5] = \<const0> ;
assign gpio2_io_t[4] = \<const0> ;
assign gpio2_io_t[3] = \<const0> ;
assign gpio2_io_t[2] = \<const0> ;
assign gpio2_io_t[1] = \<const0> ;
assign gpio2_io_t[0] = \<const0> ;
assign ip2intc_irpt = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [30];
assign s_axi_rdata[30] = \^s_axi_rdata [30];
assign s_axi_rdata[29] = \^s_axi_rdata [30];
assign s_axi_rdata[28] = \^s_axi_rdata [30];
assign s_axi_rdata[27] = \^s_axi_rdata [30];
assign s_axi_rdata[26] = \^s_axi_rdata [30];
assign s_axi_rdata[25] = \^s_axi_rdata [30];
assign s_axi_rdata[24] = \^s_axi_rdata [30];
assign s_axi_rdata[23] = \^s_axi_rdata [30];
assign s_axi_rdata[22] = \^s_axi_rdata [30];
assign s_axi_rdata[21] = \^s_axi_rdata [30];
assign s_axi_rdata[20] = \^s_axi_rdata [30];
assign s_axi_rdata[19] = \^s_axi_rdata [30];
assign s_axi_rdata[18] = \^s_axi_rdata [30];
assign s_axi_rdata[17] = \^s_axi_rdata [30];
assign s_axi_rdata[16] = \^s_axi_rdata [30];
assign s_axi_rdata[15] = \^s_axi_rdata [30];
assign s_axi_rdata[14] = \^s_axi_rdata [30];
assign s_axi_rdata[13] = \^s_axi_rdata [30];
assign s_axi_rdata[12] = \^s_axi_rdata [30];
assign s_axi_rdata[11] = \^s_axi_rdata [30];
assign s_axi_rdata[10] = \^s_axi_rdata [30];
assign s_axi_rdata[9] = \^s_axi_rdata [30];
assign s_axi_rdata[8] = \^s_axi_rdata [30];
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_wready = s_axi_awready;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.D({GPIO_DBus[0],GPIO_DBus[24],GPIO_DBus[25],GPIO_DBus[26],GPIO_DBus[27],GPIO_DBus[28],GPIO_DBus[29],GPIO_DBus[30],GPIO_DBus[31]}),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ({gpio_core_1_n_43,gpio_core_1_n_44,gpio_core_1_n_45,gpio_core_1_n_46,gpio_core_1_n_47,gpio_core_1_n_48,gpio_core_1_n_49,gpio_core_1_n_50}),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7]}),
.E(AXI_LITE_IPIF_I_n_12),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (AXI_LITE_IPIF_I_n_10),
.Q(bus2ip_addr),
.Read_Reg2_In(Read_Reg2_In),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_13),
.bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_14),
.\ip2bus_data_i_D1_reg[31] (gpio_core_1_n_24),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_rdack_i_D1_reg(s_axi_arready),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.ip2bus_wrack_i_D1_reg(s_axi_awready),
.reg1({reg1[24],reg1[25],reg1[26],reg1[27],reg1[28],reg1[29],reg1[30],reg1[31]}),
.reg2({reg2[24],reg2[25],reg2[26],reg2[27],reg2[28],reg2[29],reg2[30],reg2[31]}),
.reg3({reg3[24],reg3[25],reg3[26],reg3[27],reg3[28],reg3[29],reg3[30],reg3[31]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid_i_reg(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [30],\^s_axi_rdata [7:0]}),
.\s_axi_rdata_i_reg[31] ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid_i_reg(s_axi_rvalid),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 (AXI_LITE_IPIF_I_n_10),
.\Dual.gpio2_Data_In_reg[0]_0 ({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7]}),
.\Dual.gpio2_OE_reg[0]_0 ({gpio_core_1_n_43,gpio_core_1_n_44,gpio_core_1_n_45,gpio_core_1_n_46,gpio_core_1_n_47,gpio_core_1_n_48,gpio_core_1_n_49,gpio_core_1_n_50}),
.\Dual.gpio2_OE_reg[0]_1 (AXI_LITE_IPIF_I_n_14),
.\Dual.gpio_OE_reg[0]_0 (AXI_LITE_IPIF_I_n_13),
.E(AXI_LITE_IPIF_I_n_12),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (gpio_core_1_n_24),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.Q(bus2ip_addr),
.Read_Reg2_In(Read_Reg2_In),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.gpio2_io_i(gpio2_io_i),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i(ip2bus_wrack_i),
.reg1({reg1[24],reg1[25],reg1[26],reg1[27],reg1[28],reg1[29],reg1[30],reg1[31]}),
.reg2({reg2[24],reg2[25],reg2[26],reg2[27],reg2[28],reg2[29],reg2[30],reg2[31]}),
.reg3({reg3[24],reg3[25],reg3[26],reg3[27],reg3[28],reg3[29],reg3[30],reg3[31]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[7:0]));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_i),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(bus2ip_reset,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
bus2ip_rnw,
Bus_RNW_reg,
s_axi_rvalid_i_reg,
s_axi_bvalid_i_reg,
bus2ip_cs,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
Q,
E,
bus2ip_rnw_i_reg,
bus2ip_rnw_i_reg_0,
Read_Reg2_In,
ip2bus_rdack_i_D1_reg,
ip2bus_wrack_i_D1_reg,
s_axi_rdata,
D,
s_axi_aclk,
s_axi_arvalid,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ,
s_axi_rready,
s_axi_bready,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
\s_axi_rdata_i_reg[31] ,
\ip2bus_data_i_D1_reg[31] ,
reg1,
reg2,
reg3,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_araddr,
s_axi_awaddr);
output bus2ip_reset;
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
output bus2ip_rnw;
output Bus_RNW_reg;
output s_axi_rvalid_i_reg;
output s_axi_bvalid_i_reg;
output bus2ip_cs;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output [0:0]Q;
output [0:0]E;
output [0:0]bus2ip_rnw_i_reg;
output [0:0]bus2ip_rnw_i_reg_0;
output [0:7]Read_Reg2_In;
output ip2bus_rdack_i_D1_reg;
output ip2bus_wrack_i_D1_reg;
output [8:0]s_axi_rdata;
output [8:0]D;
input s_axi_aclk;
input s_axi_arvalid;
input [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
input [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ;
input s_axi_rready;
input s_axi_bready;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input [8:0]\s_axi_rdata_i_reg[31] ;
input \ip2bus_data_i_D1_reg[31] ;
input [7:0]reg1;
input [7:0]reg2;
input [7:0]reg3;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
wire Bus_RNW_reg;
wire [8:0]D;
wire [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
wire [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [0:0]Q;
wire [0:7]Read_Reg2_In;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire \ip2bus_data_i_D1_reg[31] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_rdack_i_D1_reg;
wire ip2bus_wrack_i_D1;
wire ip2bus_wrack_i_D1_reg;
wire [7:0]reg1;
wire [7:0]reg2;
wire [7:0]reg3;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid_i_reg;
wire [8:0]s_axi_rdata;
wire [8:0]\s_axi_rdata_i_reg[31] ;
wire s_axi_rready;
wire s_axi_rvalid_i_reg;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.Bus_RNW_reg_reg(Bus_RNW_reg),
.D(D),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ),
.E(E),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.Q(Q),
.Read_Reg2_In(Read_Reg2_In),
.SR(bus2ip_reset),
.bus2ip_rnw_i_reg_0(bus2ip_rnw),
.bus2ip_rnw_i_reg_1(bus2ip_rnw_i_reg),
.bus2ip_rnw_i_reg_2(bus2ip_rnw_i_reg_0),
.\ip2bus_data_i_D1_reg[31] (\ip2bus_data_i_D1_reg[31] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_rdack_i_D1_reg(ip2bus_rdack_i_D1_reg),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.ip2bus_wrack_i_D1_reg(ip2bus_wrack_i_D1_reg),
.reg1(reg1),
.reg2(reg2),
.reg3(reg3),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid_i_reg_0(s_axi_bvalid_i_reg),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rdata_i_reg[31]_0 (\s_axi_rdata_i_reg[31] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid_i_reg_0(s_axi_rvalid_i_reg),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [7:0]scndry_vect_out;
input [7:0]gpio_io_i;
input s_axi_aclk;
wire [7:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire [7:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(scndry_vect_out,
gpio2_io_i,
s_axi_aclk);
output [7:0]scndry_vect_out;
input [7:0]gpio2_io_i;
input s_axi_aclk;
wire [7:0]gpio2_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire [7:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(SR,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
bus2ip_rnw_i_reg_0,
Bus_RNW_reg_reg,
s_axi_rvalid_i_reg_0,
s_axi_bvalid_i_reg_0,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
Q,
E,
bus2ip_rnw_i_reg_1,
bus2ip_rnw_i_reg_2,
Read_Reg2_In,
ip2bus_rdack_i_D1_reg,
ip2bus_wrack_i_D1_reg,
s_axi_rdata,
D,
s_axi_aclk,
s_axi_arvalid,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ,
s_axi_rready,
s_axi_bready,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
\s_axi_rdata_i_reg[31]_0 ,
\ip2bus_data_i_D1_reg[31] ,
reg1,
reg2,
reg3,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_araddr,
s_axi_awaddr);
output [0:0]SR;
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
output bus2ip_rnw_i_reg_0;
output Bus_RNW_reg_reg;
output s_axi_rvalid_i_reg_0;
output s_axi_bvalid_i_reg_0;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output [0:0]Q;
output [0:0]E;
output [0:0]bus2ip_rnw_i_reg_1;
output [0:0]bus2ip_rnw_i_reg_2;
output [0:7]Read_Reg2_In;
output ip2bus_rdack_i_D1_reg;
output ip2bus_wrack_i_D1_reg;
output [8:0]s_axi_rdata;
output [8:0]D;
input s_axi_aclk;
input s_axi_arvalid;
input [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
input [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ;
input s_axi_rready;
input s_axi_bready;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input [8:0]\s_axi_rdata_i_reg[31]_0 ;
input \ip2bus_data_i_D1_reg[31] ;
input [7:0]reg1;
input [7:0]reg2;
input [7:0]reg3;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
wire Bus_RNW_reg_reg;
wire [8:0]D;
wire [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
wire [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ;
wire [0:0]E;
wire \FSM_onehot_state[0]_i_1_n_0 ;
wire \FSM_onehot_state[1]_i_1_n_0 ;
wire \FSM_onehot_state[2]_i_1_n_0 ;
wire \FSM_onehot_state[3]_i_1_n_0 ;
wire \FSM_onehot_state_reg_n_0_[0] ;
wire \FSM_onehot_state_reg_n_0_[3] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire [0:0]Q;
wire [0:7]Read_Reg2_In;
wire [0:0]SR;
wire [0:5]bus2ip_addr;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire bus2ip_rnw_i_reg_0;
wire [0:0]bus2ip_rnw_i_reg_1;
wire [0:0]bus2ip_rnw_i_reg_2;
wire clear;
wire \ip2bus_data_i_D1_reg[31] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_rdack_i_D1_reg;
wire ip2bus_wrack_i_D1;
wire ip2bus_wrack_i_D1_reg;
wire is_read_i_1_n_0;
wire is_read_reg_n_0;
wire is_write_i_1_n_0;
wire is_write_i_2_n_0;
wire is_write_reg_n_0;
wire [8:2]p_1_in;
wire p_5_in;
wire [3:0]plusOp;
wire [7:0]reg1;
wire [7:0]reg2;
wire [7:0]reg3;
wire rst_i_1_n_0;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bresp_i;
wire s_axi_bvalid_i_i_1_n_0;
wire s_axi_bvalid_i_reg_0;
wire [8:0]s_axi_rdata;
wire [8:0]\s_axi_rdata_i_reg[31]_0 ;
wire s_axi_rready;
wire s_axi_rresp_i;
wire s_axi_rvalid_i_i_1_n_0;
wire s_axi_rvalid_i_reg_0;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire state1__2;
wire \state[0]_i_1_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state_reg_n_0_[0] ;
wire \state_reg_n_0_[1] ;
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3[24]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [7]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [7]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[0]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3[25]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [6]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [6]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[1]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3[26]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [5]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [5]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[2]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3[27]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [4]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [4]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[3]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3[28]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [3]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [3]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[4]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3[29]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [2]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [2]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[5]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3[30]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [1]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [1]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[6]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [0]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [0]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[7]));
LUT6 #(
.INIT(64'hFFFF150015001500))
\FSM_onehot_state[0]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(\FSM_onehot_state_reg_n_0_[0] ),
.I4(state1__2),
.I5(\FSM_onehot_state_reg_n_0_[3] ),
.O(\FSM_onehot_state[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8F88))
\FSM_onehot_state[1]_i_1
(.I0(s_axi_arvalid),
.I1(\FSM_onehot_state_reg_n_0_[0] ),
.I2(ip2bus_rdack_i_D1_reg),
.I3(s_axi_rresp_i),
.O(\FSM_onehot_state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800FFFF08000800))
\FSM_onehot_state[2]_i_1
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.I3(\FSM_onehot_state_reg_n_0_[0] ),
.I4(ip2bus_wrack_i_D1_reg),
.I5(s_axi_bresp_i),
.O(\FSM_onehot_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF888F888FFFFF888))
\FSM_onehot_state[3]_i_1
(.I0(ip2bus_wrack_i_D1_reg),
.I1(s_axi_bresp_i),
.I2(s_axi_rresp_i),
.I3(ip2bus_rdack_i_D1_reg),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(state1__2),
.O(\FSM_onehot_state[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'hF888))
\FSM_onehot_state[3]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid_i_reg_0),
.I2(s_axi_rready),
.I3(s_axi_rvalid_i_reg_0),
.O(state1__2));
(* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_onehot_state[0]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[0] ),
.S(SR));
(* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_onehot_state[1]_i_1_n_0 ),
.Q(s_axi_rresp_i),
.R(SR));
(* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_onehot_state[2]_i_1_n_0 ),
.Q(s_axi_bresp_i),
.R(SR));
(* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_onehot_state[3]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[3] ),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(\state_reg_n_0_[0] ),
.I1(\state_reg_n_0_[1] ),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.Bus_RNW_reg_reg_0(Bus_RNW_reg_reg),
.Bus_RNW_reg_reg_1(bus2ip_rnw_i_reg_0),
.D(D),
.\Dual.gpio_Data_Out_reg[0] ({bus2ip_addr[0],bus2ip_addr[5],Q}),
.E(E),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 (\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.Q(start2),
.bus2ip_rnw_i_reg(bus2ip_rnw_i_reg_1),
.bus2ip_rnw_i_reg_0(bus2ip_rnw_i_reg_2),
.\ip2bus_data_i_D1_reg[31] (\ip2bus_data_i_D1_reg[31] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_rdack_i_D1_reg(ip2bus_rdack_i_D1_reg),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.ip2bus_wrack_i_D1_reg(ip2bus_wrack_i_D1_reg),
.reg1(reg1),
.reg2(reg2),
.reg3(reg3),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(is_read_reg_n_0),
.s_axi_arready_0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg ),
.s_axi_awready(is_write_reg_n_0));
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(s_axi_arvalid),
.O(p_1_in[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(s_axi_arvalid),
.O(p_1_in[3]));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(\state_reg_n_0_[1] ),
.I4(\state_reg_n_0_[0] ),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(s_axi_arvalid),
.O(p_1_in[8]));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(p_1_in[2]),
.Q(Q),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(p_1_in[3]),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(p_1_in[8]),
.Q(bus2ip_addr[0]),
.R(SR));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(s_axi_arvalid),
.Q(bus2ip_rnw_i_reg_0),
.R(SR));
LUT5 #(
.INIT(32'h8BBB8888))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\FSM_onehot_state_reg_n_0_[0] ),
.I2(state1__2),
.I3(\FSM_onehot_state_reg_n_0_[3] ),
.I4(is_read_reg_n_0),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read_reg_n_0),
.R(SR));
LUT6 #(
.INIT(64'h2000FFFF20000000))
is_write_i_1
(.I0(\FSM_onehot_state_reg_n_0_[0] ),
.I1(s_axi_arvalid),
.I2(s_axi_awvalid),
.I3(s_axi_wvalid),
.I4(is_write_i_2_n_0),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hFFEAEAEAAAAAAAAA))
is_write_i_2
(.I0(\FSM_onehot_state_reg_n_0_[0] ),
.I1(s_axi_bready),
.I2(s_axi_bvalid_i_reg_0),
.I3(s_axi_rready),
.I4(s_axi_rvalid_i_reg_0),
.I5(\FSM_onehot_state_reg_n_0_[3] ),
.O(is_write_i_2_n_0));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(rst_i_1_n_0));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rst_i_1_n_0),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(ip2bus_wrack_i_D1_reg),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.I3(s_axi_bready),
.I4(s_axi_bvalid_i_reg_0),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid_i_reg_0),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [8]),
.Q(s_axi_rdata[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [7]),
.Q(s_axi_rdata[7]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(ip2bus_rdack_i_D1_reg),
.I1(\state_reg_n_0_[0] ),
.I2(\state_reg_n_0_[1] ),
.I3(s_axi_rready),
.I4(s_axi_rvalid_i_reg_0),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid_i_reg_0),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(\state_reg_n_0_[1] ),
.I4(\state_reg_n_0_[0] ),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h0FCAFFCA))
\state[0]_i_1
(.I0(s_axi_arvalid),
.I1(ip2bus_wrack_i_D1_reg),
.I2(\state_reg_n_0_[1] ),
.I3(\state_reg_n_0_[0] ),
.I4(state1__2),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h55FFFF0C5500FF0C))
\state[1]_i_1
(.I0(state1__2),
.I1(p_5_in),
.I2(s_axi_arvalid),
.I3(\state_reg_n_0_[1] ),
.I4(\state_reg_n_0_[0] ),
.I5(ip2bus_rdack_i_D1_reg),
.O(\state[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\state[1]_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(p_5_in));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\state_reg_n_0_[0] ),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(\state_reg_n_0_[1] ),
.R(SR));
endmodule
(* CHECK_LICENSE_TYPE = "xlnx_axi_gpio,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2021.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) input [7:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [7:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [7:0]gpio_io_t;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE" *) input [7:0]gpio2_io_i;
wire \<const0> ;
wire [7:0]gpio2_io_i;
wire [7:0]gpio_io_i;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [7:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [7:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_GPIO2_WIDTH = "8" *)
(* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[7:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[7:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],1'b0,1'b0,1'b0,1'b0,s_axi_araddr[3:2],1'b0,1'b0}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],1'b0,1'b0,1'b0,1'b0,s_axi_awaddr[3:2],1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axi_wdata[7:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Tue Sep 20 00:11:21 2022
-- Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_gpio_sim_netlist.vhdl
-- Design : xlnx_axi_gpio
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : out STD_LOGIC;
Bus_RNW_reg_reg_0 : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2bus_rdack_i_D1_reg : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Dual.gpio_Data_Out_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Bus_RNW_reg_reg_1 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
s_axi_arready : in STD_LOGIC;
s_axi_arready_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
\ip2bus_data_i_D1_reg[31]\ : in STD_LOGIC;
reg1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \^bus_rnw_reg_reg_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \ip2bus_data_i_D1[24]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[25]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[26]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[27]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[28]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[29]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[30]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[31]_i_2_n_0\ : STD_LOGIC;
signal \^ip2bus_rdack_i_d1_reg\ : STD_LOGIC;
signal \^ip2bus_wrack_i_d1_reg\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio2_OE[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_OE[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair2";
begin
Bus_RNW_reg_reg_0 <= \^bus_rnw_reg_reg_0\;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ <= \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ <= \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ <= \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ <= \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
ip2bus_rdack_i_D1_reg <= \^ip2bus_rdack_i_d1_reg\;
ip2bus_wrack_i_D1_reg <= \^ip2bus_wrack_i_d1_reg\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Bus_RNW_reg_reg_1,
I1 => Q,
I2 => \^bus_rnw_reg_reg_0\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^bus_rnw_reg_reg_0\,
R => '0'
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \Dual.gpio_Data_Out_reg[0]\(2),
I2 => \Dual.gpio_Data_Out_reg[0]\(1),
O => \MEM_DECODE_GEN[0].cs_out_i_reg[0]_1\
);
\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => Bus_RNW_reg_reg_1,
I1 => \Dual.gpio_Data_Out_reg[0]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \Dual.gpio_Data_Out_reg[0]\(1),
I4 => \Dual.gpio_Data_Out_reg[0]\(0),
O => bus2ip_rnw_i_reg_0(0)
);
\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => Bus_RNW_reg_reg_1,
I1 => \Dual.gpio_Data_Out_reg[0]\(1),
I2 => \Dual.gpio_Data_Out_reg[0]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \Dual.gpio_Data_Out_reg[0]\(0),
O => E(0)
);
\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => Bus_RNW_reg_reg_1,
I1 => \Dual.gpio_Data_Out_reg[0]\(1),
I2 => \Dual.gpio_Data_Out_reg[0]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \Dual.gpio_Data_Out_reg[0]\(0),
O => bus2ip_rnw_i_reg(0)
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \Dual.gpio_Data_Out_reg[0]\(1),
I1 => \Dual.gpio_Data_Out_reg[0]\(0),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \Dual.gpio_Data_Out_reg[0]\(1),
I1 => \Dual.gpio_Data_Out_reg[0]\(0),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \Dual.gpio_Data_Out_reg[0]\(0),
I1 => \Dual.gpio_Data_Out_reg[0]\(1),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^ip2bus_wrack_i_d1_reg\,
I1 => \^ip2bus_rdack_i_d1_reg\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \Dual.gpio_Data_Out_reg[0]\(1),
I1 => \Dual.gpio_Data_Out_reg[0]\(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => Q,
I2 => s_axi_aresetn,
I3 => \^ip2bus_rdack_i_d1_reg\,
I4 => \^ip2bus_wrack_i_d1_reg\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
O => D(8)
);
\ip2bus_data_i_D1[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(7),
I4 => \ip2bus_data_i_D1[24]_i_2_n_0\,
O => D(7)
);
\ip2bus_data_i_D1[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(7),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(7),
O => \ip2bus_data_i_D1[24]_i_2_n_0\
);
\ip2bus_data_i_D1[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(6),
I4 => \ip2bus_data_i_D1[25]_i_2_n_0\,
O => D(6)
);
\ip2bus_data_i_D1[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(6),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(6),
O => \ip2bus_data_i_D1[25]_i_2_n_0\
);
\ip2bus_data_i_D1[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(5),
I4 => \ip2bus_data_i_D1[26]_i_2_n_0\,
O => D(5)
);
\ip2bus_data_i_D1[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(5),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(5),
O => \ip2bus_data_i_D1[26]_i_2_n_0\
);
\ip2bus_data_i_D1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(4),
I4 => \ip2bus_data_i_D1[27]_i_2_n_0\,
O => D(4)
);
\ip2bus_data_i_D1[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(4),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(4),
O => \ip2bus_data_i_D1[27]_i_2_n_0\
);
\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(3),
I4 => \ip2bus_data_i_D1[28]_i_2_n_0\,
O => D(3)
);
\ip2bus_data_i_D1[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(3),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(3),
O => \ip2bus_data_i_D1[28]_i_2_n_0\
);
\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(2),
I4 => \ip2bus_data_i_D1[29]_i_2_n_0\,
O => D(2)
);
\ip2bus_data_i_D1[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(2),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(2),
O => \ip2bus_data_i_D1[29]_i_2_n_0\
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(1),
I4 => \ip2bus_data_i_D1[30]_i_2_n_0\,
O => D(1)
);
\ip2bus_data_i_D1[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(1),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(1),
O => \ip2bus_data_i_D1[30]_i_2_n_0\
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(0),
I4 => \ip2bus_data_i_D1[31]_i_2_n_0\,
O => D(0)
);
\ip2bus_data_i_D1[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(0),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(0),
O => \ip2bus_data_i_D1[31]_i_2_n_0\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => s_axi_arready,
I2 => s_axi_arready_0(2),
I3 => s_axi_arready_0(1),
I4 => s_axi_arready_0(3),
I5 => s_axi_arready_0(0),
O => \^ip2bus_rdack_i_d1_reg\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => s_axi_awready,
I2 => s_axi_arready_0(2),
I3 => s_axi_arready_0(1),
I4 => s_axi_arready_0(3),
I5 => s_axi_arready_0(0),
O => \^ip2bus_wrack_i_d1_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
reg1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
reg3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
reg2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
\Dual.gpio2_OE_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.gpio2_Data_In_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
Read_Reg2_In : in STD_LOGIC_VECTOR ( 0 to 7 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.gpio_OE_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_OE_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0\ : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal gpio2_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 7 );
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 7 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal \^reg2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ip2bus_wrack_i_D1_i_1 : label is "soft_lutpair9";
begin
gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0);
gpio_io_t(7 downto 0) <= \^gpio_io_t\(7 downto 0);
reg2(7 downto 0) <= \^reg2\(7 downto 0);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(0),
Q => reg3(7),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(1),
Q => reg3(6),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(2),
Q => reg3(5),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(3),
Q => reg3(4),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(4),
Q => reg3(3),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(5),
Q => reg3(2),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(6),
Q => reg3(1),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(7),
Q => reg3(0),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(0),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(7),
I4 => \^gpio_io_t\(7),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0\,
Q => reg1(7),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(0),
I1 => \^gpio_io_t\(7),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(7),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0\,
Q => \^reg2\(7),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(1),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(6),
I4 => \^gpio_io_t\(6),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0\,
Q => reg1(6),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(1),
I1 => \^gpio_io_t\(6),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(6),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0\,
Q => \^reg2\(6),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(2),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(5),
I4 => \^gpio_io_t\(5),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0\,
Q => reg1(5),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(2),
I1 => \^gpio_io_t\(5),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(5),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0\,
Q => \^reg2\(5),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(3),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(4),
I4 => \^gpio_io_t\(4),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0\,
Q => reg1(4),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(3),
I1 => \^gpio_io_t\(4),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(4),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0\,
Q => \^reg2\(4),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(4),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(3),
I4 => \^gpio_io_t\(3),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0\,
Q => reg1(3),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(4),
I1 => \^gpio_io_t\(3),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(3),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0\,
Q => \^reg2\(3),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(5),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(2),
I4 => \^gpio_io_t\(2),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0\,
Q => reg1(2),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(5),
I1 => \^gpio_io_t\(2),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(2),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0\,
Q => \^reg2\(2),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(6),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(1),
I4 => \^gpio_io_t\(1),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0\,
Q => reg1(1),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(6),
I1 => \^gpio_io_t\(1),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(1),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0\,
Q => \^reg2\(1),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => GPIO_xferAck_i,
I1 => gpio_xferAck_Reg,
I2 => bus2ip_rnw,
I3 => bus2ip_cs,
O => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(7),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(0),
I4 => \^gpio_io_t\(0),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0\,
Q => reg1(0),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(7),
I1 => \^gpio_io_t\(0),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(0),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0\,
Q => \^reg2\(0),
R => Read_Reg_Rst
);
\Dual.INPUT_DOUBLE_REGS4\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
gpio_io_i(7 downto 0) => gpio_io_i(7 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(7) => gpio_io_i_d2(0),
scndry_vect_out(6) => gpio_io_i_d2(1),
scndry_vect_out(5) => gpio_io_i_d2(2),
scndry_vect_out(4) => gpio_io_i_d2(3),
scndry_vect_out(3) => gpio_io_i_d2(4),
scndry_vect_out(2) => gpio_io_i_d2(5),
scndry_vect_out(1) => gpio_io_i_d2(6),
scndry_vect_out(0) => gpio_io_i_d2(7)
);
\Dual.INPUT_DOUBLE_REGS5\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(7) => gpio2_io_i_d2(0),
scndry_vect_out(6) => gpio2_io_i_d2(1),
scndry_vect_out(5) => gpio2_io_i_d2(2),
scndry_vect_out(4) => gpio2_io_i_d2(3),
scndry_vect_out(3) => gpio2_io_i_d2(4),
scndry_vect_out(2) => gpio2_io_i_d2(5),
scndry_vect_out(1) => gpio2_io_i_d2(6),
scndry_vect_out(0) => gpio2_io_i_d2(7)
);
\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(0),
Q => \Dual.gpio2_Data_In_reg[0]_0\(7),
R => '0'
);
\Dual.gpio2_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(1),
Q => \Dual.gpio2_Data_In_reg[0]_0\(6),
R => '0'
);
\Dual.gpio2_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(2),
Q => \Dual.gpio2_Data_In_reg[0]_0\(5),
R => '0'
);
\Dual.gpio2_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(3),
Q => \Dual.gpio2_Data_In_reg[0]_0\(4),
R => '0'
);
\Dual.gpio2_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(4),
Q => \Dual.gpio2_Data_In_reg[0]_0\(3),
R => '0'
);
\Dual.gpio2_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(5),
Q => \Dual.gpio2_Data_In_reg[0]_0\(2),
R => '0'
);
\Dual.gpio2_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(6),
Q => \Dual.gpio2_Data_In_reg[0]_0\(1),
R => '0'
);
\Dual.gpio2_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(7),
Q => \Dual.gpio2_Data_In_reg[0]_0\(0),
R => '0'
);
\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(7),
Q => \Dual.gpio2_OE_reg[0]_0\(7),
S => SS(0)
);
\Dual.gpio2_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(6),
Q => \Dual.gpio2_OE_reg[0]_0\(6),
S => SS(0)
);
\Dual.gpio2_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(5),
Q => \Dual.gpio2_OE_reg[0]_0\(5),
S => SS(0)
);
\Dual.gpio2_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(4),
Q => \Dual.gpio2_OE_reg[0]_0\(4),
S => SS(0)
);
\Dual.gpio2_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(3),
Q => \Dual.gpio2_OE_reg[0]_0\(3),
S => SS(0)
);
\Dual.gpio2_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(2),
Q => \Dual.gpio2_OE_reg[0]_0\(2),
S => SS(0)
);
\Dual.gpio2_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(1),
Q => \Dual.gpio2_OE_reg[0]_0\(1),
S => SS(0)
);
\Dual.gpio2_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(0),
Q => \Dual.gpio2_OE_reg[0]_0\(0),
S => SS(0)
);
\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => gpio_Data_In(0),
R => '0'
);
\Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => gpio_Data_In(1),
R => '0'
);
\Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => gpio_Data_In(2),
R => '0'
);
\Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => gpio_Data_In(3),
R => '0'
);
\Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => gpio_Data_In(4),
R => '0'
);
\Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(5),
Q => gpio_Data_In(5),
R => '0'
);
\Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(6),
Q => gpio_Data_In(6),
R => '0'
);
\Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(7),
Q => gpio_Data_In(7),
R => '0'
);
\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => \^gpio_io_o\(7),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => \^gpio_io_o\(6),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => \^gpio_io_o\(5),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => \^gpio_io_o\(4),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => \^gpio_io_o\(3),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => \^gpio_io_o\(2),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => \^gpio_io_o\(1),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => \^gpio_io_o\(0),
R => SS(0)
);
\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(7),
Q => \^gpio_io_t\(7),
S => SS(0)
);
\Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(6),
Q => \^gpio_io_t\(6),
S => SS(0)
);
\Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(5),
Q => \^gpio_io_t\(5),
S => SS(0)
);
\Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(4),
Q => \^gpio_io_t\(4),
S => SS(0)
);
\Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(3),
Q => \^gpio_io_t\(3),
S => SS(0)
);
\Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(2),
Q => \^gpio_io_t\(2),
S => SS(0)
);
\Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(1),
Q => \^gpio_io_t\(1),
S => SS(0)
);
\Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(0),
Q => \^gpio_io_t\(0),
S => SS(0)
);
GPIO_DBus: unisim.vcomponents.LUT5
generic map(
INIT => X"00040448"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
O => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_xferAck_i,
Q => gpio_xferAck_Reg,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => GPIO_xferAck_i,
I1 => bus2ip_cs,
I2 => gpio_xferAck_Reg,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => GPIO_xferAck_i,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => GPIO_xferAck_i,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => GPIO_xferAck_i,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : out STD_LOGIC;
bus2ip_rnw_i_reg_0 : out STD_LOGIC;
Bus_RNW_reg_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_bvalid_i_reg_0 : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 7 );
ip2bus_rdack_i_D1_reg : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\ip2bus_data_i_D1_reg[31]\ : in STD_LOGIC;
reg1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[0]\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 5 );
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \^bus2ip_rnw_i_reg_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal \^ip2bus_rdack_i_d1_reg\ : STD_LOGIC;
signal \^ip2bus_wrack_i_d1_reg\ : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_read_reg_n_0 : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_i_2_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 8 downto 2 );
signal p_5_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_i_1_n_0 : STD_LOGIC;
signal s_axi_bresp_i : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_bvalid_i_reg_0\ : STD_LOGIC;
signal s_axi_rresp_i : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal \state1__2\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[0]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[1]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[2]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[3]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair5";
begin
Q(0) <= \^q\(0);
SR(0) <= \^sr\(0);
bus2ip_rnw_i_reg_0 <= \^bus2ip_rnw_i_reg_0\;
ip2bus_rdack_i_D1_reg <= \^ip2bus_rdack_i_d1_reg\;
ip2bus_wrack_i_D1_reg <= \^ip2bus_wrack_i_d1_reg\;
s_axi_bvalid_i_reg_0 <= \^s_axi_bvalid_i_reg_0\;
s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(7),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(7),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(0)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(6),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(6),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(1)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(5),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(5),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(2)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(4),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(4),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(3)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(3),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(3),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(4)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(2),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(2),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(5)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(1),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(1),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(6)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(0),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(0),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(7)
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF150015001500"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_wvalid,
I2 => s_axi_awvalid,
I3 => \FSM_onehot_state_reg_n_0_[0]\,
I4 => \state1__2\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_arvalid,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \^ip2bus_rdack_i_d1_reg\,
I3 => s_axi_rresp_i,
O => \FSM_onehot_state[1]_i_1_n_0\
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800FFFF08000800"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
I3 => \FSM_onehot_state_reg_n_0_[0]\,
I4 => \^ip2bus_wrack_i_d1_reg\,
I5 => s_axi_bresp_i,
O => \FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F888F888FFFFF888"
)
port map (
I0 => \^ip2bus_wrack_i_d1_reg\,
I1 => s_axi_bresp_i,
I2 => s_axi_rresp_i,
I3 => \^ip2bus_rdack_i_d1_reg\,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => \state1__2\,
O => \FSM_onehot_state[3]_i_1_n_0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid_i_reg_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid_i_reg_0\,
O => \state1__2\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_onehot_state[1]_i_1_n_0\,
Q => s_axi_rresp_i,
R => \^sr\(0)
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_onehot_state[2]_i_1_n_0\,
Q => s_axi_bresp_i,
R => \^sr\(0)
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_onehot_state[3]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => \^sr\(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg,
Bus_RNW_reg_reg_1 => \^bus2ip_rnw_i_reg_0\,
D(8 downto 0) => D(8 downto 0),
\Dual.gpio_Data_Out_reg[0]\(2) => bus2ip_addr(0),
\Dual.gpio_Data_Out_reg[0]\(1) => bus2ip_addr(5),
\Dual.gpio_Data_Out_reg[0]\(0) => \^q\(0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\,
Q => start2,
bus2ip_rnw_i_reg(0) => bus2ip_rnw_i_reg_1(0),
bus2ip_rnw_i_reg_0(0) => bus2ip_rnw_i_reg_2(0),
\ip2bus_data_i_D1_reg[31]\ => \ip2bus_data_i_D1_reg[31]\,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_rdack_i_D1_reg => \^ip2bus_rdack_i_d1_reg\,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
ip2bus_wrack_i_D1_reg => \^ip2bus_wrack_i_d1_reg\,
reg1(7 downto 0) => reg1(7 downto 0),
reg2(7 downto 0) => reg2(7 downto 0),
reg3(7 downto 0) => reg3(7 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => is_read_reg_n_0,
s_axi_arready_0(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3 downto 0),
s_axi_awready => is_write_reg_n_0
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => s_axi_arvalid,
O => p_1_in(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => s_axi_arvalid,
O => p_1_in(3)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => s_axi_arvalid,
O => p_1_in(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => p_1_in(2),
Q => \^q\(0),
R => \^sr\(0)
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => p_1_in(3),
Q => bus2ip_addr(5),
R => \^sr\(0)
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => p_1_in(8),
Q => bus2ip_addr(0),
R => \^sr\(0)
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => s_axi_arvalid,
Q => \^bus2ip_rnw_i_reg_0\,
R => \^sr\(0)
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8888"
)
port map (
I0 => s_axi_arvalid,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \state1__2\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => is_read_reg_n_0,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read_reg_n_0,
R => \^sr\(0)
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"2000FFFF20000000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => s_axi_arvalid,
I2 => s_axi_awvalid,
I3 => s_axi_wvalid,
I4 => is_write_i_2_n_0,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAEAEAAAAAAAAA"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid_i_reg_0\,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid_i_reg_0\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => is_write_i_2_n_0
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\(0)
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => rst_i_1_n_0
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_i_1_n_0,
Q => \^sr\(0),
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^ip2bus_wrack_i_d1_reg\,
I1 => \state_reg_n_0_[1]\,
I2 => \state_reg_n_0_[0]\,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid_i_reg_0\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid_i_reg_0\,
R => \^sr\(0)
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(0),
Q => s_axi_rdata(0),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(1),
Q => s_axi_rdata(1),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(2),
Q => s_axi_rdata(2),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(8),
Q => s_axi_rdata(8),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(3),
Q => s_axi_rdata(3),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(4),
Q => s_axi_rdata(4),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(5),
Q => s_axi_rdata(5),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(6),
Q => s_axi_rdata(6),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(7),
Q => s_axi_rdata(7),
R => \^sr\(0)
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^ip2bus_rdack_i_d1_reg\,
I1 => \state_reg_n_0_[0]\,
I2 => \state_reg_n_0_[1]\,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid_i_reg_0\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid_i_reg_0\,
R => \^sr\(0)
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\(0)
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCAFFCA"
)
port map (
I0 => s_axi_arvalid,
I1 => \^ip2bus_wrack_i_d1_reg\,
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
I4 => \state1__2\,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FFFF0C5500FF0C"
)
port map (
I0 => \state1__2\,
I1 => p_5_in,
I2 => s_axi_arvalid,
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \^ip2bus_rdack_i_d1_reg\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => p_5_in
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => \^sr\(0)
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 7 );
ip2bus_rdack_i_D1_reg : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\ip2bus_data_i_D1_reg[31]\ : in STD_LOGIC;
reg1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
Bus_RNW_reg_reg => Bus_RNW_reg,
D(8 downto 0) => D(8 downto 0),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(7 downto 0) => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(7 downto 0),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(7 downto 0) => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(7 downto 0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
Q(0) => Q(0),
Read_Reg2_In(0 to 7) => Read_Reg2_In(0 to 7),
SR(0) => bus2ip_reset,
bus2ip_rnw_i_reg_0 => bus2ip_rnw,
bus2ip_rnw_i_reg_1(0) => bus2ip_rnw_i_reg(0),
bus2ip_rnw_i_reg_2(0) => bus2ip_rnw_i_reg_0(0),
\ip2bus_data_i_D1_reg[31]\ => \ip2bus_data_i_D1_reg[31]\,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_rdack_i_D1_reg => ip2bus_rdack_i_D1_reg,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
ip2bus_wrack_i_D1_reg => ip2bus_wrack_i_D1_reg,
reg1(7 downto 0) => reg1(7 downto 0),
reg2(7 downto 0) => reg2(7 downto 0),
reg3(7 downto 0) => reg3(7 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg_0 => s_axi_bvalid_i_reg,
s_axi_rdata(8 downto 0) => s_axi_rdata(8 downto 0),
\s_axi_rdata_i_reg[31]_0\(8 downto 0) => \s_axi_rdata_i_reg[31]\(8 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "kintex7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 8;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal GPIO_DBus : STD_LOGIC_VECTOR ( 0 to 31 );
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal Read_Reg2_In : STD_LOGIC_VECTOR ( 0 to 7 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 6 to 6 );
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio2_Data_In : STD_LOGIC_VECTOR ( 0 to 7 );
signal gpio_core_1_n_24 : STD_LOGIC;
signal gpio_core_1_n_43 : STD_LOGIC;
signal gpio_core_1_n_44 : STD_LOGIC;
signal gpio_core_1_n_45 : STD_LOGIC;
signal gpio_core_1_n_46 : STD_LOGIC;
signal gpio_core_1_n_47 : STD_LOGIC;
signal gpio_core_1_n_48 : STD_LOGIC;
signal gpio_core_1_n_49 : STD_LOGIC;
signal gpio_core_1_n_50 : STD_LOGIC;
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal reg1 : STD_LOGIC_VECTOR ( 24 to 31 );
signal reg2 : STD_LOGIC_VECTOR ( 24 to 31 );
signal reg3 : STD_LOGIC_VECTOR ( 24 to 31 );
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
attribute sigis : string;
attribute sigis of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
attribute sigis of s_axi_aclk : signal is "Clk";
attribute sigis of s_axi_aresetn : signal is "Rst";
begin
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(7) <= \<const0>\;
gpio2_io_t(6) <= \<const0>\;
gpio2_io_t(5) <= \<const0>\;
gpio2_io_t(4) <= \<const0>\;
gpio2_io_t(3) <= \<const0>\;
gpio2_io_t(2) <= \<const0>\;
gpio2_io_t(1) <= \<const0>\;
gpio2_io_t(0) <= \<const0>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_awready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(30);
s_axi_rdata(30) <= \^s_axi_rdata\(30);
s_axi_rdata(29) <= \^s_axi_rdata\(30);
s_axi_rdata(28) <= \^s_axi_rdata\(30);
s_axi_rdata(27) <= \^s_axi_rdata\(30);
s_axi_rdata(26) <= \^s_axi_rdata\(30);
s_axi_rdata(25) <= \^s_axi_rdata\(30);
s_axi_rdata(24) <= \^s_axi_rdata\(30);
s_axi_rdata(23) <= \^s_axi_rdata\(30);
s_axi_rdata(22) <= \^s_axi_rdata\(30);
s_axi_rdata(21) <= \^s_axi_rdata\(30);
s_axi_rdata(20) <= \^s_axi_rdata\(30);
s_axi_rdata(19) <= \^s_axi_rdata\(30);
s_axi_rdata(18) <= \^s_axi_rdata\(30);
s_axi_rdata(17) <= \^s_axi_rdata\(30);
s_axi_rdata(16) <= \^s_axi_rdata\(30);
s_axi_rdata(15) <= \^s_axi_rdata\(30);
s_axi_rdata(14) <= \^s_axi_rdata\(30);
s_axi_rdata(13) <= \^s_axi_rdata\(30);
s_axi_rdata(12) <= \^s_axi_rdata\(30);
s_axi_rdata(11) <= \^s_axi_rdata\(30);
s_axi_rdata(10) <= \^s_axi_rdata\(30);
s_axi_rdata(9) <= \^s_axi_rdata\(30);
s_axi_rdata(8) <= \^s_axi_rdata\(30);
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_awready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(8) => GPIO_DBus(0),
D(7) => GPIO_DBus(24),
D(6) => GPIO_DBus(25),
D(5) => GPIO_DBus(26),
D(4) => GPIO_DBus(27),
D(3) => GPIO_DBus(28),
D(2) => GPIO_DBus(29),
D(1) => GPIO_DBus(30),
D(0) => GPIO_DBus(31),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(7) => gpio_core_1_n_43,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(6) => gpio_core_1_n_44,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(5) => gpio_core_1_n_45,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(4) => gpio_core_1_n_46,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(3) => gpio_core_1_n_47,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(2) => gpio_core_1_n_48,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(1) => gpio_core_1_n_49,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(0) => gpio_core_1_n_50,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(7) => gpio2_Data_In(0),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(6) => gpio2_Data_In(1),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(5) => gpio2_Data_In(2),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(4) => gpio2_Data_In(3),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(3) => gpio2_Data_In(4),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(2) => gpio2_Data_In(5),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(1) => gpio2_Data_In(6),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(0) => gpio2_Data_In(7),
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_10,
Q(0) => bus2ip_addr(6),
Read_Reg2_In(0 to 7) => Read_Reg2_In(0 to 7),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_13,
bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_14,
\ip2bus_data_i_D1_reg[31]\ => gpio_core_1_n_24,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_rdack_i_D1_reg => s_axi_arready,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
ip2bus_wrack_i_D1_reg => \^s_axi_awready\,
reg1(7) => reg1(24),
reg1(6) => reg1(25),
reg1(5) => reg1(26),
reg1(4) => reg1(27),
reg1(3) => reg1(28),
reg1(2) => reg1(29),
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(7) => reg2(24),
reg2(6) => reg2(25),
reg2(5) => reg2(26),
reg2(4) => reg2(27),
reg2(3) => reg2(28),
reg2(2) => reg2(29),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
reg3(7) => reg3(24),
reg3(6) => reg3(25),
reg3(5) => reg3(26),
reg3(4) => reg3(27),
reg3(3) => reg3(28),
reg3(2) => reg3(29),
reg3(1) => reg3(30),
reg3(0) => reg3(31),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg => s_axi_bvalid,
s_axi_rdata(8) => \^s_axi_rdata\(30),
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
\s_axi_rdata_i_reg[31]\(8) => ip2bus_data_i_D1(0),
\s_axi_rdata_i_reg[31]\(7) => ip2bus_data_i_D1(24),
\s_axi_rdata_i_reg[31]\(6) => ip2bus_data_i_D1(25),
\s_axi_rdata_i_reg[31]\(5) => ip2bus_data_i_D1(26),
\s_axi_rdata_i_reg[31]\(4) => ip2bus_data_i_D1(27),
\s_axi_rdata_i_reg[31]\(3) => ip2bus_data_i_D1(28),
\s_axi_rdata_i_reg[31]\(2) => ip2bus_data_i_D1(29),
\s_axi_rdata_i_reg[31]\(1) => ip2bus_data_i_D1(30),
\s_axi_rdata_i_reg[31]\(0) => ip2bus_data_i_D1(31),
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg => s_axi_rvalid,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\ => AXI_LITE_IPIF_I_n_10,
\Dual.gpio2_Data_In_reg[0]_0\(7) => gpio2_Data_In(0),
\Dual.gpio2_Data_In_reg[0]_0\(6) => gpio2_Data_In(1),
\Dual.gpio2_Data_In_reg[0]_0\(5) => gpio2_Data_In(2),
\Dual.gpio2_Data_In_reg[0]_0\(4) => gpio2_Data_In(3),
\Dual.gpio2_Data_In_reg[0]_0\(3) => gpio2_Data_In(4),
\Dual.gpio2_Data_In_reg[0]_0\(2) => gpio2_Data_In(5),
\Dual.gpio2_Data_In_reg[0]_0\(1) => gpio2_Data_In(6),
\Dual.gpio2_Data_In_reg[0]_0\(0) => gpio2_Data_In(7),
\Dual.gpio2_OE_reg[0]_0\(7) => gpio_core_1_n_43,
\Dual.gpio2_OE_reg[0]_0\(6) => gpio_core_1_n_44,
\Dual.gpio2_OE_reg[0]_0\(5) => gpio_core_1_n_45,
\Dual.gpio2_OE_reg[0]_0\(4) => gpio_core_1_n_46,
\Dual.gpio2_OE_reg[0]_0\(3) => gpio_core_1_n_47,
\Dual.gpio2_OE_reg[0]_0\(2) => gpio_core_1_n_48,
\Dual.gpio2_OE_reg[0]_0\(1) => gpio_core_1_n_49,
\Dual.gpio2_OE_reg[0]_0\(0) => gpio_core_1_n_50,
\Dual.gpio2_OE_reg[0]_1\(0) => AXI_LITE_IPIF_I_n_14,
\Dual.gpio_OE_reg[0]_0\(0) => AXI_LITE_IPIF_I_n_13,
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => gpio_core_1_n_24,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
Q(0) => bus2ip_addr(6),
Read_Reg2_In(0 to 7) => Read_Reg2_In(0 to 7),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
gpio_io_i(7 downto 0) => gpio_io_i(7 downto 0),
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
reg1(7) => reg1(24),
reg1(6) => reg1(25),
reg1(5) => reg1(26),
reg1(4) => reg1(27),
reg1(3) => reg1(28),
reg1(2) => reg1(29),
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(7) => reg2(24),
reg2(6) => reg2(25),
reg2(5) => reg2(26),
reg2(4) => reg2(27),
reg2(3) => reg2(28),
reg2(2) => reg2(29),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
reg3(7) => reg3(24),
reg3(6) => reg3(25),
reg3(5) => reg3(26),
reg3(4) => reg3(27),
reg3(3) => reg3(28),
reg3(2) => reg3(29),
reg3(1) => reg3(30),
reg3(0) => reg3(31),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "xlnx_axi_gpio,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2021.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 8;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute x_interface_info : string;
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of gpio2_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
attribute x_interface_parameter of gpio2_io_i : signal is "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute x_interface_parameter of gpio_io_i : signal is "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_o : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
attribute x_interface_info of gpio_io_t : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
gpio2_io_o(7 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(7 downto 0),
gpio2_io_t(7 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(7 downto 0),
gpio_io_i(7 downto 0) => gpio_io_i(7 downto 0),
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8) => s_axi_araddr(8),
s_axi_araddr(7 downto 4) => B"0000",
s_axi_araddr(3 downto 2) => s_axi_araddr(3 downto 2),
s_axi_araddr(1 downto 0) => B"00",
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8) => s_axi_awaddr(8),
s_axi_awaddr(7 downto 4) => B"0000",
s_axi_awaddr(3 downto 2) => s_axi_awaddr(3 downto 2),
s_axi_awaddr(1 downto 0) => B"00",
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 8) => B"000000000000000000000000",
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
// Date : Tue Sep 20 00:11:21 2022
// Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_gpio_stub.v
// Design : xlnx_axi_gpio
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2021.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t,
gpio2_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[7:0],gpio_io_o[7:0],gpio_io_t[7:0],gpio2_io_i[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [7:0]gpio2_io_i;
endmodule
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Tue Sep 20 00:11:21 2022
-- Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_gpio_stub.vhdl
-- Design : xlnx_axi_gpio
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[7:0],gpio_io_o[7:0],gpio_io_t[7:0],gpio2_io_i[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2021.2";
begin
end;
|
version:1
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eof:
|
version:1
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|
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_gpio:2.0
// IP Revision: 27
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
xlnx_axi_gpio your_instance_name (
.s_axi_aclk(s_axi_aclk), // input wire s_axi_aclk
.s_axi_aresetn(s_axi_aresetn), // input wire s_axi_aresetn
.s_axi_awaddr(s_axi_awaddr), // input wire [8 : 0] s_axi_awaddr
.s_axi_awvalid(s_axi_awvalid), // input wire s_axi_awvalid
.s_axi_awready(s_axi_awready), // output wire s_axi_awready
.s_axi_wdata(s_axi_wdata), // input wire [31 : 0] s_axi_wdata
.s_axi_wstrb(s_axi_wstrb), // input wire [3 : 0] s_axi_wstrb
.s_axi_wvalid(s_axi_wvalid), // input wire s_axi_wvalid
.s_axi_wready(s_axi_wready), // output wire s_axi_wready
.s_axi_bresp(s_axi_bresp), // output wire [1 : 0] s_axi_bresp
.s_axi_bvalid(s_axi_bvalid), // output wire s_axi_bvalid
.s_axi_bready(s_axi_bready), // input wire s_axi_bready
.s_axi_araddr(s_axi_araddr), // input wire [8 : 0] s_axi_araddr
.s_axi_arvalid(s_axi_arvalid), // input wire s_axi_arvalid
.s_axi_arready(s_axi_arready), // output wire s_axi_arready
.s_axi_rdata(s_axi_rdata), // output wire [31 : 0] s_axi_rdata
.s_axi_rresp(s_axi_rresp), // output wire [1 : 0] s_axi_rresp
.s_axi_rvalid(s_axi_rvalid), // output wire s_axi_rvalid
.s_axi_rready(s_axi_rready), // input wire s_axi_rready
.gpio_io_i(gpio_io_i), // input wire [7 : 0] gpio_io_i
.gpio_io_o(gpio_io_o), // output wire [7 : 0] gpio_io_o
.gpio_io_t(gpio_io_t), // output wire [7 : 0] gpio_io_t
.gpio2_io_i(gpio2_io_i) // input wire [7 : 0] gpio2_io_i
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file xlnx_axi_gpio.v when simulating
// the core, xlnx_axi_gpio. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
|
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 27
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT xlnx_axi_gpio
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : xlnx_axi_gpio
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file xlnx_axi_gpio.vhd when simulating
-- the core, xlnx_axi_gpio. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
|
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set_false_path -to [get_pins -hier *cdc_to*/D]
|
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>xlnx_axi_gpio</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>S_AXI</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
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</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
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</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_awready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_awvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
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<spirit:name>s_axi_bready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
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</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
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</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_rdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_rready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
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</spirit:logicalPort>
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</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
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</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_wdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_wready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
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<spirit:physicalPort>
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</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
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</spirit:portMap>
</spirit:portMaps>
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<spirit:vendorExtensions>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:value>
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<spirit:vendorExtensions>
<xilinx:parameterInfo>
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<spirit:parameter>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">9</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
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<spirit:parameter>
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<spirit:parameter>
<spirit:name>HAS_WSTRB</spirit:name>
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<spirit:vendorExtensions>
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<spirit:parameter>
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<spirit:vendorExtensions>
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</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_RRESP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:value>
<spirit:vendorExtensions>
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</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
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<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MAX_BURST_LENGTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_THREADS</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_THREADS</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S_AXI_ACLK</spirit:name>
<spirit:displayName>s_axi_aclk</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_aclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">S_AXI</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_PORT</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_PORT"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>S_AXI_ARESETN</spirit:name>
<spirit:displayName>s_axi_aresetn</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_aresetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY">ACTIVE_LOW</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>IP2INTC_IRQ</spirit:name>
<spirit:displayName>IP2Intc_irq</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ip2intc_irpt</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SENSITIVITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.IP2INTC_IRQ.SENSITIVITY">LEVEL_HIGH</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PortWidth</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.IP2INTC_IRQ.PortWidth">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.IP2INTC_IRQ" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERRUPT_PRESENT'))=1">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>GPIO</spirit:name>
<spirit:displayName>GPIO</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gpio_io_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gpio_io_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gpio_io_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO.BOARD.ASSOCIATED_PARAM">GPIO_BOARD_INTERFACE</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:presence>required</xilinx:presence>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>GPIO2</spirit:name>
<spirit:displayName>GPIO2</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="gpio_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gpio2_io_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gpio2_io_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TRI_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gpio2_io_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.GPIO2.BOARD.ASSOCIATED_PARAM">GPIO2_BOARD_INTERFACE</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:presence>required</xilinx:presence>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.GPIO2" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_IS_DUAL')) = 1">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>S_AXI</spirit:name>
<spirit:displayName>S_AXI_MEM</spirit:displayName>
<spirit:description>Memory Map for S_AXI</spirit:description>
<spirit:addressBlock>
<spirit:name>Reg</spirit:name>
<spirit:displayName>Reg</spirit:displayName>
<spirit:description>Register Block</spirit:description>
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
<spirit:range spirit:format="long">4096</spirit:range>
<spirit:width spirit:format="long">32</spirit:width>
<spirit:usage>register</spirit:usage>
<spirit:access>read-write</spirit:access>
<spirit:register>
<spirit:name>GPIO_DATA</spirit:name>
<spirit:displayName>Channel_1_GPIO_DATA</spirit:displayName>
<spirit:description>Channel-1 AXI GPIO Data register</spirit:description>
<spirit:addressOffset>0x0</spirit:addressOffset>
<spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_GPIO_WIDTH')))">8</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Channel_1_GPIO_DATA</spirit:name>
<spirit:displayName>Channel_1_GPIO_DATA</spirit:displayName>
<spirit:description>AXI GPIO Data Register.
For each I/O bit programmed as input
R - Reads value on the input pin.
W - No effect.
For each I/O bit programmed as output
R - Reads value on GPIO_O pins
W - Writes value to the corresponding AXI GPIO
data register bit and output pin
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_GPIO_WIDTH')))">8</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
</spirit:register>
<spirit:register>
<spirit:name>GPIO_TRI</spirit:name>
<spirit:displayName>Channel_1_GPIO_TRI</spirit:displayName>
<spirit:description>Channel-1 AXI GPIO 3-State Control register</spirit:description>
<spirit:addressOffset>0x4</spirit:addressOffset>
<spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_GPIO_WIDTH')))">8</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Channel_1_GPIO_TRI</spirit:name>
<spirit:displayName>Channel_1_GPIO_DATA</spirit:displayName>
<spirit:description>AXI GPIO 3-State Control Register
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_GPIO_WIDTH')))">8</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
</spirit:register>
<spirit:register>
<spirit:name>GPIO2_DATA</spirit:name>
<spirit:displayName>Channel_2_GPIO_DATA</spirit:displayName>
<spirit:description>Channel-2 AXI GPIO Data register</spirit:description>
<spirit:addressOffset>0x8</spirit:addressOffset>
<spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_GPIO2_WIDTH')))">8</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Channel_2_GPIO_DATA</spirit:name>
<spirit:displayName>Channel_2_GPIO_DATA</spirit:displayName>
<spirit:description>AXI GPIO Data Register.
For each I/O bit programmed as input
R - Reads value on the input pin.
W - No effect.
For each I/O bit programmed as output
R - Reads value on GPIO_O pins
W - Writes value to the corresponding AXI GPIO
data register bit and output pin
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_GPIO2_WIDTH')))">8</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
</spirit:register>
<spirit:register>
<spirit:name>GPIO2_TRI</spirit:name>
<spirit:displayName>Channel_2_GPIO_TRI</spirit:displayName>
<spirit:description>Channel-2 AXI GPIO 3-State Control register</spirit:description>
<spirit:addressOffset>0xC</spirit:addressOffset>
<spirit:size spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_GPIO2_WIDTH')))">8</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Channel_2_GPIO_TRI</spirit:name>
<spirit:displayName>Channel_2_GPIO_DATA</spirit:displayName>
<spirit:description>AXI GPIO 3-State Control Register
Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_GPIO2_WIDTH')))">8</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
</spirit:register>
<spirit:register>
<spirit:name>GIER</spirit:name>
<spirit:displayName>Global_Interrupt_Enable register</spirit:displayName>
<spirit:description>Global_Interrupt_Enable register</spirit:description>
<spirit:addressOffset>0x11C</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Global_Interrupt_Enable</spirit:name>
<spirit:displayName>Global_Interrupt_Enable</spirit:displayName>
<spirit:description>Master enable for the device interrupt output
0 - Disabled
1 - Enabled
</spirit:description>
<spirit:bitOffset>31</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
</spirit:register>
<spirit:register>
<spirit:name>IP_IER</spirit:name>
<spirit:displayName>IP Interrupt Enable register</spirit:displayName>
<spirit:description>IP Interrupt Enable register</spirit:description>
<spirit:addressOffset>0x128</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Channel_1_Interrupt_Enable</spirit:name>
<spirit:displayName>Channel_1_Interrupt_Enable</spirit:displayName>
<spirit:description>Enable Channel 1 Interrupt
0 - Disabled (masked)
1 - Enabled
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Channel_2_Interrupt_Enable</spirit:name>
<spirit:displayName>Channel_2_Interrupt_Enable</spirit:displayName>
<spirit:description>Enable Channel 2 Interrupt
0 - Disabled (masked)
1 - Enabled
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
</spirit:register>
<spirit:register>
<spirit:name>IP_ISR</spirit:name>
<spirit:displayName>IP Interrupt Status register</spirit:displayName>
<spirit:description>IP Interrupt Status register</spirit:description>
<spirit:addressOffset>0x120</spirit:addressOffset>
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1 - Channel 2 input interrupt
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<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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<xilinx:enablement>
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<spirit:port>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:wireTypeDef>
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<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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<xilinx:portInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.gpio2_io_t" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_IS_DUAL'))= 1) and (spirit:decode(id('MODELPARAM_VALUE.C_ALL_OUTPUTS_2')) =0) and (spirit:decode(id('MODELPARAM_VALUE.C_ALL_INPUTS_2'))=0)">false</xilinx:isEnabled>
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<spirit:name>C_FAMILY</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:value>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
<spirit:displayName>C S Axi Addr Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">9</spirit:value>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
<spirit:displayName>C S Axi Data Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
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<spirit:modelParameter spirit:dataType="integer">
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<spirit:displayName>GPIO Width</spirit:displayName>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_GPIO2_WIDTH</spirit:name>
<spirit:displayName>GPIO2 Data Width</spirit:displayName>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_ALL_INPUTS</spirit:name>
<spirit:displayName>All Inputs</spirit:displayName>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_ALL_INPUTS_2</spirit:name>
<spirit:displayName>All Inputs</spirit:displayName>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_ALL_OUTPUTS</spirit:name>
<spirit:displayName>All Outputs</spirit:displayName>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_ALL_OUTPUTS_2</spirit:name>
<spirit:displayName>All Outputs</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ALL_OUTPUTS_2" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_INTERRUPT_PRESENT</spirit:name>
<spirit:displayName>Enable Interrupt</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERRUPT_PRESENT" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
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<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
<spirit:name>C_DOUT_DEFAULT</spirit:name>
<spirit:displayName>Default DOUT value</spirit:displayName>
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<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
<spirit:name>C_TRI_DEFAULT</spirit:name>
<spirit:displayName>Default tri state value</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TRI_DEFAULT" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
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<spirit:modelParameter spirit:dataType="integer">
<spirit:name>C_IS_DUAL</spirit:name>
<spirit:displayName>Enable Dual channel</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IS_DUAL" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">1</spirit:value>
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<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
<spirit:name>C_DOUT_DEFAULT_2</spirit:name>
<spirit:displayName>Default DOUT value2</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_DEFAULT_2" spirit:bitStringLength="32">0x00000000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="std_logic_vector(31 downto 0)">
<spirit:name>C_TRI_DEFAULT_2</spirit:name>
<spirit:displayName>Default tri state value2</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_TRI_DEFAULT_2" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
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<spirit:choice>
<spirit:name>choice_list_2383d8cd</spirit:name>
<spirit:enumeration>Custom</spirit:enumeration>
<spirit:enumeration>dip_switches_8bits</spirit:enumeration>
<spirit:enumeration>hdmi_in_hpd_led</spirit:enumeration>
<spirit:enumeration>hdmi_out_hpd_led</spirit:enumeration>
<spirit:enumeration>led_8bits</spirit:enumeration>
<spirit:enumeration>push_buttons_5bits</spirit:enumeration>
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<spirit:choice>
<spirit:name>choice_pairs_4873554b</spirit:name>
<spirit:enumeration spirit:text="false">0</spirit:enumeration>
<spirit:enumeration spirit:text="true">1</spirit:enumeration>
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<spirit:fileSet>
<spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xlnx_axi_gpio.vho</spirit:name>
<spirit:userFileType>vhdlTemplate</spirit:userFileType>
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<spirit:file>
<spirit:name>xlnx_axi_gpio.veo</spirit:name>
<spirit:userFileType>verilogTemplate</spirit:userFileType>
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<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_axi_lite_ipif_3_0__ref_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/axi_lite_ipif_v3_0_vh_rfs.vhd</spirit:name>
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<spirit:logicalName>axi_lite_ipif_v3_0_4</spirit:logicalName>
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_lite_ipif" xilinx:version="3.0" xilinx:isGenerated="true" xilinx:checksum="db189391">
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<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
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<spirit:name>hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
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<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_interrupt_control_3_1__ref_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/interrupt_control_v3_1_vh_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>interrupt_control_v3_1_4</spirit:logicalName>
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<xilinx:subCoreRef>
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="interrupt_control" xilinx:version="3.1" xilinx:isGenerated="true" xilinx:checksum="40b9039f">
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<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xlnx_axi_gpio_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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<spirit:file>
<spirit:name>xlnx_axi_gpio.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
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<spirit:name>hdl/axi_lite_ipif_v3_0_vh_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
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<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="axi_lite_ipif" xilinx:version="3.0" xilinx:isGenerated="true" xilinx:checksum="db189391">
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<spirit:logicalName>axi_gpio_v2_0_27</spirit:logicalName>
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<spirit:name>xilinx_implementation_view_fileset</spirit:name>
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<spirit:name>xlnx_axi_gpio_board.xdc</spirit:name>
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<spirit:userFileType>USED_IN_board</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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<spirit:file>
<spirit:name>doc/axi_gpio_v2_0_changelog.txt</spirit:name>
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<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
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<spirit:name>xlnx_axi_gpio.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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<spirit:file>
<spirit:name>xlnx_axi_gpio_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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<spirit:file>
<spirit:name>xlnx_axi_gpio_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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<spirit:file>
<spirit:name>xlnx_axi_gpio_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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<spirit:parameter>
<spirit:name>C_TRI_DEFAULT</spirit:name>
<spirit:displayName>Default Tri State Value</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TRI_DEFAULT" spirit:order="2000" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
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<spirit:parameter>
<spirit:name>C_GPIO_WIDTH</spirit:name>
<spirit:displayName>GPIO Width</spirit:displayName>
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<spirit:displayName>GPIO Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_GPIO2_WIDTH" spirit:order="1800" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">8</spirit:value>
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<spirit:name>C_IS_DUAL</spirit:name>
<spirit:displayName>Enable Dual Channel</spirit:displayName>
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<spirit:name>C_ALL_INPUTS</spirit:name>
<spirit:displayName>All Inputs</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALL_INPUTS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1300">0</spirit:value>
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<spirit:parameter>
<spirit:name>C_TRI_DEFAULT_2</spirit:name>
<spirit:displayName>Default Tri State Value</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TRI_DEFAULT_2" spirit:order="1400" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
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<spirit:parameter>
<spirit:name>C_DOUT_DEFAULT_2</spirit:name>
<spirit:displayName>Default Output Value</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DOUT_DEFAULT_2" spirit:order="1500" spirit:bitStringLength="32">0x00000000</spirit:value>
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<spirit:parameter>
<spirit:name>C_DOUT_DEFAULT</spirit:name>
<spirit:displayName>Default Output Value</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DOUT_DEFAULT" spirit:order="1600" spirit:bitStringLength="32">0x00000000</spirit:value>
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<spirit:name>C_ALL_INPUTS_2</spirit:name>
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<spirit:parameter>
<spirit:name>C_INTERRUPT_PRESENT</spirit:name>
<spirit:displayName>Enable Interrupt</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_INTERRUPT_PRESENT" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1100">0</spirit:value>
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</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xlnx_axi_gpio</spirit:value>
<spirit:vendorExtensions>
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<xilinx:enablement>
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</spirit:parameter>
<spirit:parameter>
<spirit:name>USE_BOARD_FLOW</spirit:name>
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1000">false</spirit:value>
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<spirit:parameter>
<spirit:name>GPIO_BOARD_INTERFACE</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.GPIO_BOARD_INTERFACE" spirit:choiceRef="choice_list_2383d8cd" spirit:order="1001">Custom</spirit:value>
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<xilinx:enablement>
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<spirit:parameter>
<spirit:name>GPIO2_BOARD_INTERFACE</spirit:name>
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<spirit:parameter>
<spirit:name>C_ALL_OUTPUTS</spirit:name>
<spirit:displayName>All Outputs</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALL_OUTPUTS" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2100">0</spirit:value>
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<spirit:parameter>
<spirit:name>C_ALL_OUTPUTS_2</spirit:name>
<spirit:displayName>All Outputs</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_ALL_OUTPUTS_2" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2200">0</spirit:value>
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<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>AXI GPIO</xilinx:displayName>
<xilinx:coreRevision>27</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ALL_INPUTS_2" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GPIO2_WIDTH" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IS_DUAL" xilinx:valueSource="user"/>
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="c44adf9c"/>
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</spirit:vendorExtensions>
</spirit:component>
|
#--------------------Physical Constraints-----------------
|
################################################################################
# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
################################################################################
# This XDC is used only for OOC mode of synthesis, implementation
# User should update the correct clock period before proceeding further
# This constraints file contains default clock frequencies to be used during
# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
# For best results the frequencies should be modified# to match the target
# frequencies.
create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
################################################################################
|
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
// Date : Tue Sep 20 00:11:22 2022
// Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
// Command : write_verilog -force -mode funcsim
// /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_sim_netlist.v
// Design : xlnx_axi_gpio
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "xlnx_axi_gpio,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2021.2" *)
(* NotValidForBitStream *)
module xlnx_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) input [7:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [7:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [7:0]gpio_io_t;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE" *) input [7:0]gpio2_io_i;
wire \<const0> ;
wire [7:0]gpio2_io_i;
wire [7:0]gpio_io_i;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [7:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [7:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_GPIO2_WIDTH = "8" *)
(* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
xlnx_axi_gpio_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[7:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[7:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],1'b0,1'b0,1'b0,1'b0,s_axi_araddr[3:2],1'b0,1'b0}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],1'b0,1'b0,1'b0,1'b0,s_axi_awaddr[3:2],1'b0,1'b0}),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axi_wdata[7:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module xlnx_axi_gpio_GPIO_Core
(reg1,
reg3,
reg2,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
gpio_io_o,
gpio_io_t,
ip2bus_wrack_i,
ip2bus_rdack_i,
\Dual.gpio2_OE_reg[0]_0 ,
\Dual.gpio2_Data_In_reg[0]_0 ,
s_axi_aclk,
Read_Reg2_In,
SS,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ,
Q,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
gpio2_io_i,
E,
s_axi_wdata,
\Dual.gpio_OE_reg[0]_0 ,
\Dual.gpio2_OE_reg[0]_1 );
output [7:0]reg1;
output [7:0]reg3;
output [7:0]reg2;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
output ip2bus_wrack_i;
output ip2bus_rdack_i;
output [7:0]\Dual.gpio2_OE_reg[0]_0 ;
output [7:0]\Dual.gpio2_Data_In_reg[0]_0 ;
input s_axi_aclk;
input [0:7]Read_Reg2_In;
input [0:0]SS;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ;
input [0:0]Q;
input bus2ip_rnw;
input bus2ip_cs;
input [7:0]gpio_io_i;
input [7:0]gpio2_io_i;
input [0:0]E;
input [7:0]s_axi_wdata;
input [0:0]\Dual.gpio_OE_reg[0]_0 ;
input [0:0]\Dual.gpio2_OE_reg[0]_1 ;
wire Bus_RNW_reg;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0 ;
wire \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ;
wire [7:0]\Dual.gpio2_Data_In_reg[0]_0 ;
wire [7:0]\Dual.gpio2_OE_reg[0]_0 ;
wire [0:0]\Dual.gpio2_OE_reg[0]_1 ;
wire [0:0]\Dual.gpio_OE_reg[0]_0 ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire GPIO_xferAck_i;
wire [0:0]Q;
wire [0:7]Read_Reg2_In;
wire Read_Reg_Rst;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire [7:0]gpio2_io_i;
wire [0:7]gpio2_io_i_d2;
wire [0:7]gpio_Data_In;
wire [7:0]gpio_io_i;
wire [0:7]gpio_io_i_d2;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i;
wire [7:0]reg1;
wire [7:0]reg2;
wire [7:0]reg3;
wire s_axi_aclk;
wire [7:0]s_axi_wdata;
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[0]),
.Q(reg3[7]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[1]),
.Q(reg3[6]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[2]),
.Q(reg3[5]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[3]),
.Q(reg3[4]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[4]),
.Q(reg3[3]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[5]),
.Q(reg3[2]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[6]),
.Q(reg3[1]),
.R(Read_Reg_Rst));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg2_In[7]),
.Q(reg3[0]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1
(.I0(gpio_Data_In[0]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[7]),
.I4(gpio_io_t[7]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0 ),
.Q(reg1[7]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1
(.I0(gpio_Data_In[0]),
.I1(gpio_io_t[7]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[7]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0 ),
.Q(reg2[7]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1
(.I0(gpio_Data_In[1]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[6]),
.I4(gpio_io_t[6]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0 ),
.Q(reg1[6]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1
(.I0(gpio_Data_In[1]),
.I1(gpio_io_t[6]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[6]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0 ),
.Q(reg2[6]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1
(.I0(gpio_Data_In[2]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[5]),
.I4(gpio_io_t[5]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0 ),
.Q(reg1[5]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1
(.I0(gpio_Data_In[2]),
.I1(gpio_io_t[5]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[5]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0 ),
.Q(reg2[5]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1
(.I0(gpio_Data_In[3]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[4]),
.I4(gpio_io_t[4]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0 ),
.Q(reg1[4]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1
(.I0(gpio_Data_In[3]),
.I1(gpio_io_t[4]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[4]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0 ),
.Q(reg2[4]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1
(.I0(gpio_Data_In[4]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[3]),
.I4(gpio_io_t[3]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0 ),
.Q(reg1[3]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1
(.I0(gpio_Data_In[4]),
.I1(gpio_io_t[3]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[3]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0 ),
.Q(reg2[3]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1
(.I0(gpio_Data_In[5]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[2]),
.I4(gpio_io_t[2]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0 ),
.Q(reg1[2]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1
(.I0(gpio_Data_In[5]),
.I1(gpio_io_t[2]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[2]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0 ),
.Q(reg2[2]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1
(.I0(gpio_Data_In[6]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[1]),
.I4(gpio_io_t[1]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0 ),
.Q(reg1[1]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1
(.I0(gpio_Data_In[6]),
.I1(gpio_io_t[1]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[1]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0 ),
.Q(reg2[1]),
.R(Read_Reg_Rst));
LUT4 #(
.INIT(16'hEFFF))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_1
(.I0(GPIO_xferAck_i),
.I1(gpio_xferAck_Reg),
.I2(bus2ip_rnw),
.I3(bus2ip_cs),
.O(Read_Reg_Rst));
LUT5 #(
.INIT(32'h3232CF00))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2
(.I0(gpio_Data_In[7]),
.I1(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I2(Q),
.I3(gpio_io_o[0]),
.I4(gpio_io_t[0]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0 ),
.Q(reg1[0]),
.R(Read_Reg_Rst));
LUT5 #(
.INIT(32'h33CB00C8))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1
(.I0(gpio_Data_In[7]),
.I1(gpio_io_t[0]),
.I2(Q),
.I3(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 ),
.I4(reg2[0]),
.O(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0 ));
FDRE \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0 ),
.Q(reg2[0]),
.R(Read_Reg_Rst));
xlnx_axi_gpio_cdc_sync \Dual.INPUT_DOUBLE_REGS4
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7]}));
xlnx_axi_gpio_cdc_sync_0 \Dual.INPUT_DOUBLE_REGS5
(.gpio2_io_i(gpio2_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3],gpio2_io_i_d2[4],gpio2_io_i_d2[5],gpio2_io_i_d2[6],gpio2_io_i_d2[7]}));
FDRE \Dual.gpio2_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[0]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [7]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[1]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [6]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[2]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [5]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[3]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [4]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[4]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [3]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[5]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [2]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[6]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [1]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[7]),
.Q(\Dual.gpio2_Data_In_reg[0]_0 [0]),
.R(1'b0));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[0]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[7]),
.Q(\Dual.gpio2_OE_reg[0]_0 [7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[1]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[6]),
.Q(\Dual.gpio2_OE_reg[0]_0 [6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[2]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[5]),
.Q(\Dual.gpio2_OE_reg[0]_0 [5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[3]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[4]),
.Q(\Dual.gpio2_OE_reg[0]_0 [4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[4]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[3]),
.Q(\Dual.gpio2_OE_reg[0]_0 [3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[5]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[2]),
.Q(\Dual.gpio2_OE_reg[0]_0 [2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[6]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[1]),
.Q(\Dual.gpio2_OE_reg[0]_0 [1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[7]
(.C(s_axi_aclk),
.CE(\Dual.gpio2_OE_reg[0]_1 ),
.D(s_axi_wdata[0]),
.Q(\Dual.gpio2_OE_reg[0]_0 [0]),
.S(SS));
FDRE \Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(gpio_Data_In[0]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(gpio_Data_In[1]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(gpio_Data_In[2]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(gpio_Data_In[3]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(gpio_Data_In[4]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[5]),
.Q(gpio_Data_In[5]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[6]),
.Q(gpio_Data_In[6]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[7]),
.Q(gpio_Data_In[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[7]),
.Q(gpio_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[6]),
.Q(gpio_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[5]),
.Q(gpio_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[4]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[3]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[2]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[1]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(s_axi_wdata[0]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[7]),
.Q(gpio_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[6]),
.Q(gpio_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[5]),
.Q(gpio_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[4]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[3]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[2]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[1]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(\Dual.gpio_OE_reg[0]_0 ),
.D(s_axi_wdata[0]),
.Q(gpio_io_t[0]),
.S(SS));
LUT5 #(
.INIT(32'h00040448))
GPIO_DBus
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.O(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h04))
iGPIO_xferAck_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_cs),
.I2(gpio_xferAck_Reg),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module xlnx_axi_gpio_address_decoder
(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
Bus_RNW_reg_reg_0,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 ,
E,
bus2ip_rnw_i_reg,
bus2ip_rnw_i_reg_0,
ip2bus_rdack_i_D1_reg,
ip2bus_wrack_i_D1_reg,
D,
Q,
s_axi_aclk,
\Dual.gpio_Data_Out_reg[0] ,
Bus_RNW_reg_reg_1,
s_axi_aresetn,
ip2bus_rdack_i_D1,
s_axi_arready,
s_axi_arready_0,
ip2bus_wrack_i_D1,
s_axi_awready,
\ip2bus_data_i_D1_reg[31] ,
reg1,
reg2,
reg3);
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
output Bus_RNW_reg_reg_0;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 ;
output [0:0]E;
output [0:0]bus2ip_rnw_i_reg;
output [0:0]bus2ip_rnw_i_reg_0;
output ip2bus_rdack_i_D1_reg;
output ip2bus_wrack_i_D1_reg;
output [8:0]D;
input Q;
input s_axi_aclk;
input [2:0]\Dual.gpio_Data_Out_reg[0] ;
input Bus_RNW_reg_reg_1;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input s_axi_arready;
input [3:0]s_axi_arready_0;
input ip2bus_wrack_i_D1;
input s_axi_awready;
input \ip2bus_data_i_D1_reg[31] ;
input [7:0]reg1;
input [7:0]reg2;
input [7:0]reg3;
wire Bus_RNW_reg_i_1_n_0;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire [8:0]D;
wire [2:0]\Dual.gpio_Data_Out_reg[0] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 ;
wire Q;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire cs_ce_clr;
wire \ip2bus_data_i_D1[24]_i_2_n_0 ;
wire \ip2bus_data_i_D1[25]_i_2_n_0 ;
wire \ip2bus_data_i_D1[26]_i_2_n_0 ;
wire \ip2bus_data_i_D1[27]_i_2_n_0 ;
wire \ip2bus_data_i_D1[28]_i_2_n_0 ;
wire \ip2bus_data_i_D1[29]_i_2_n_0 ;
wire \ip2bus_data_i_D1[30]_i_2_n_0 ;
wire \ip2bus_data_i_D1[31]_i_2_n_0 ;
wire \ip2bus_data_i_D1_reg[31] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_rdack_i_D1_reg;
wire ip2bus_wrack_i_D1;
wire ip2bus_wrack_i_D1_reg;
wire [7:0]reg1;
wire [7:0]reg2;
wire [7:0]reg3;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [3:0]s_axi_arready_0;
wire s_axi_awready;
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(Bus_RNW_reg_reg_1),
.I1(Q),
.I2(Bus_RNW_reg_reg_0),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(Bus_RNW_reg_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hFD))
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_3
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(\Dual.gpio_Data_Out_reg[0] [2]),
.I2(\Dual.gpio_Data_Out_reg[0] [1]),
.O(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h10000000))
\Dual.gpio2_OE[0]_i_1
(.I0(Bus_RNW_reg_reg_1),
.I1(\Dual.gpio_Data_Out_reg[0] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\Dual.gpio_Data_Out_reg[0] [1]),
.I4(\Dual.gpio_Data_Out_reg[0] [0]),
.O(bus2ip_rnw_i_reg_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000100))
\Dual.gpio_Data_Out[0]_i_1
(.I0(Bus_RNW_reg_reg_1),
.I1(\Dual.gpio_Data_Out_reg[0] [1]),
.I2(\Dual.gpio_Data_Out_reg[0] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\Dual.gpio_Data_Out_reg[0] [0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h01000000))
\Dual.gpio_OE[0]_i_1
(.I0(Bus_RNW_reg_reg_1),
.I1(\Dual.gpio_Data_Out_reg[0] [1]),
.I2(\Dual.gpio_Data_Out_reg[0] [2]),
.I3(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I4(\Dual.gpio_Data_Out_reg[0] [0]),
.O(bus2ip_rnw_i_reg));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h1))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\Dual.gpio_Data_Out_reg[0] [1]),
.I1(\Dual.gpio_Data_Out_reg[0] [0]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_3),
.Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h4))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\Dual.gpio_Data_Out_reg[0] [1]),
.I1(\Dual.gpio_Data_Out_reg[0] [0]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_2),
.Q(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h4))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\Dual.gpio_Data_Out_reg[0] [0]),
.I1(\Dual.gpio_Data_Out_reg[0] [1]),
.O(ce_expnd_i_1));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_1),
.Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hEF))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(ip2bus_wrack_i_D1_reg),
.I1(ip2bus_rdack_i_D1_reg),
.I2(s_axi_aresetn),
.O(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(\Dual.gpio_Data_Out_reg[0] [1]),
.I1(\Dual.gpio_Data_Out_reg[0] [0]),
.O(ce_expnd_i_0));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(Q),
.I2(s_axi_aresetn),
.I3(ip2bus_rdack_i_D1_reg),
.I4(ip2bus_wrack_i_D1_reg),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h80))
\ip2bus_data_i_D1[0]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.O(D[8]));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[24]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[7]),
.I4(\ip2bus_data_i_D1[24]_i_2_n_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[24]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[7]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[7]),
.O(\ip2bus_data_i_D1[24]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[25]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[6]),
.I4(\ip2bus_data_i_D1[25]_i_2_n_0 ),
.O(D[6]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[25]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[6]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[6]),
.O(\ip2bus_data_i_D1[25]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[26]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[5]),
.I4(\ip2bus_data_i_D1[26]_i_2_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[26]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[5]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[5]),
.O(\ip2bus_data_i_D1[26]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[27]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[4]),
.I4(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.O(D[4]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[27]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[4]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[4]),
.O(\ip2bus_data_i_D1[27]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[28]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[3]),
.I4(\ip2bus_data_i_D1[28]_i_2_n_0 ),
.O(D[3]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[28]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[3]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[3]),
.O(\ip2bus_data_i_D1[28]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[29]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[2]),
.I4(\ip2bus_data_i_D1[29]_i_2_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[29]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[2]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[2]),
.O(\ip2bus_data_i_D1[29]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[30]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[1]),
.I4(\ip2bus_data_i_D1[30]_i_2_n_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[30]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[1]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[1]),
.O(\ip2bus_data_i_D1[30]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAAAA8000))
\ip2bus_data_i_D1[31]_i_1
(.I0(\ip2bus_data_i_D1_reg[31] ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(reg1[0]),
.I4(\ip2bus_data_i_D1[31]_i_2_n_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'hCCCCC888C888C888))
\ip2bus_data_i_D1[31]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I3(reg2[0]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 ),
.I5(reg3[0]),
.O(\ip2bus_data_i_D1[31]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(s_axi_arready),
.I2(s_axi_arready_0[2]),
.I3(s_axi_arready_0[1]),
.I4(s_axi_arready_0[3]),
.I5(s_axi_arready_0[0]),
.O(ip2bus_rdack_i_D1_reg));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(s_axi_awready),
.I2(s_axi_arready_0[2]),
.I3(s_axi_arready_0[1]),
.I4(s_axi_arready_0[3]),
.I5(s_axi_arready_0[0]),
.O(ip2bus_wrack_i_D1_reg));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "1" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "kintex7" *) (* C_GPIO2_WIDTH = "8" *) (* C_GPIO_WIDTH = "8" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module xlnx_axi_gpio_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* sigis = "Clk" *) input s_axi_aclk;
(* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [7:0]gpio2_io_i;
output [7:0]gpio2_io_o;
output [7:0]gpio2_io_t;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_10;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire [0:31]GPIO_DBus;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire [0:7]Read_Reg2_In;
wire [6:6]bus2ip_addr;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:7]gpio2_Data_In;
wire [7:0]gpio2_io_i;
wire gpio_core_1_n_24;
wire gpio_core_1_n_43;
wire gpio_core_1_n_44;
wire gpio_core_1_n_45;
wire gpio_core_1_n_46;
wire gpio_core_1_n_47;
wire gpio_core_1_n_48;
wire gpio_core_1_n_49;
wire gpio_core_1_n_50;
wire [7:0]gpio_io_i;
wire [7:0]gpio_io_o;
wire [7:0]gpio_io_t;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i;
wire ip2bus_wrack_i_D1;
wire [24:31]reg1;
wire [24:31]reg2;
wire [24:31]reg3;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [30:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wvalid;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[7] = \<const0> ;
assign gpio2_io_t[6] = \<const0> ;
assign gpio2_io_t[5] = \<const0> ;
assign gpio2_io_t[4] = \<const0> ;
assign gpio2_io_t[3] = \<const0> ;
assign gpio2_io_t[2] = \<const0> ;
assign gpio2_io_t[1] = \<const0> ;
assign gpio2_io_t[0] = \<const0> ;
assign ip2intc_irpt = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [30];
assign s_axi_rdata[30] = \^s_axi_rdata [30];
assign s_axi_rdata[29] = \^s_axi_rdata [30];
assign s_axi_rdata[28] = \^s_axi_rdata [30];
assign s_axi_rdata[27] = \^s_axi_rdata [30];
assign s_axi_rdata[26] = \^s_axi_rdata [30];
assign s_axi_rdata[25] = \^s_axi_rdata [30];
assign s_axi_rdata[24] = \^s_axi_rdata [30];
assign s_axi_rdata[23] = \^s_axi_rdata [30];
assign s_axi_rdata[22] = \^s_axi_rdata [30];
assign s_axi_rdata[21] = \^s_axi_rdata [30];
assign s_axi_rdata[20] = \^s_axi_rdata [30];
assign s_axi_rdata[19] = \^s_axi_rdata [30];
assign s_axi_rdata[18] = \^s_axi_rdata [30];
assign s_axi_rdata[17] = \^s_axi_rdata [30];
assign s_axi_rdata[16] = \^s_axi_rdata [30];
assign s_axi_rdata[15] = \^s_axi_rdata [30];
assign s_axi_rdata[14] = \^s_axi_rdata [30];
assign s_axi_rdata[13] = \^s_axi_rdata [30];
assign s_axi_rdata[12] = \^s_axi_rdata [30];
assign s_axi_rdata[11] = \^s_axi_rdata [30];
assign s_axi_rdata[10] = \^s_axi_rdata [30];
assign s_axi_rdata[9] = \^s_axi_rdata [30];
assign s_axi_rdata[8] = \^s_axi_rdata [30];
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_wready = s_axi_awready;
xlnx_axi_gpio_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.D({GPIO_DBus[0],GPIO_DBus[24],GPIO_DBus[25],GPIO_DBus[26],GPIO_DBus[27],GPIO_DBus[28],GPIO_DBus[29],GPIO_DBus[30],GPIO_DBus[31]}),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ({gpio_core_1_n_43,gpio_core_1_n_44,gpio_core_1_n_45,gpio_core_1_n_46,gpio_core_1_n_47,gpio_core_1_n_48,gpio_core_1_n_49,gpio_core_1_n_50}),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7]}),
.E(AXI_LITE_IPIF_I_n_12),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (AXI_LITE_IPIF_I_n_10),
.Q(bus2ip_addr),
.Read_Reg2_In(Read_Reg2_In),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_13),
.bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_14),
.\ip2bus_data_i_D1_reg[31] (gpio_core_1_n_24),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_rdack_i_D1_reg(s_axi_arready),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.ip2bus_wrack_i_D1_reg(s_axi_awready),
.reg1({reg1[24],reg1[25],reg1[26],reg1[27],reg1[28],reg1[29],reg1[30],reg1[31]}),
.reg2({reg2[24],reg2[25],reg2[26],reg2[27],reg2[28],reg2[29],reg2[30],reg2[31]}),
.reg3({reg3[24],reg3[25],reg3[26],reg3[27],reg3[28],reg3[29],reg3[30],reg3[31]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid_i_reg(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [30],\^s_axi_rdata [7:0]}),
.\s_axi_rdata_i_reg[31] ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid_i_reg(s_axi_rvalid),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
xlnx_axi_gpio_GPIO_Core gpio_core_1
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0 (AXI_LITE_IPIF_I_n_10),
.\Dual.gpio2_Data_In_reg[0]_0 ({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7]}),
.\Dual.gpio2_OE_reg[0]_0 ({gpio_core_1_n_43,gpio_core_1_n_44,gpio_core_1_n_45,gpio_core_1_n_46,gpio_core_1_n_47,gpio_core_1_n_48,gpio_core_1_n_49,gpio_core_1_n_50}),
.\Dual.gpio2_OE_reg[0]_1 (AXI_LITE_IPIF_I_n_14),
.\Dual.gpio_OE_reg[0]_0 (AXI_LITE_IPIF_I_n_13),
.E(AXI_LITE_IPIF_I_n_12),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (gpio_core_1_n_24),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.Q(bus2ip_addr),
.Read_Reg2_In(Read_Reg2_In),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.gpio2_io_i(gpio2_io_i),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i(ip2bus_wrack_i),
.reg1({reg1[24],reg1[25],reg1[26],reg1[27],reg1[28],reg1[29],reg1[30],reg1[31]}),
.reg2({reg2[24],reg2[25],reg2[26],reg2[27],reg2[28],reg2[29],reg2[30],reg2[31]}),
.reg3({reg3[24],reg3[25],reg3[26],reg3[27],reg3[28],reg3[29],reg3[30],reg3[31]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[7:0]));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_i),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module xlnx_axi_gpio_axi_lite_ipif
(bus2ip_reset,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
bus2ip_rnw,
Bus_RNW_reg,
s_axi_rvalid_i_reg,
s_axi_bvalid_i_reg,
bus2ip_cs,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
Q,
E,
bus2ip_rnw_i_reg,
bus2ip_rnw_i_reg_0,
Read_Reg2_In,
ip2bus_rdack_i_D1_reg,
ip2bus_wrack_i_D1_reg,
s_axi_rdata,
D,
s_axi_aclk,
s_axi_arvalid,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ,
s_axi_rready,
s_axi_bready,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
\s_axi_rdata_i_reg[31] ,
\ip2bus_data_i_D1_reg[31] ,
reg1,
reg2,
reg3,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_araddr,
s_axi_awaddr);
output bus2ip_reset;
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
output bus2ip_rnw;
output Bus_RNW_reg;
output s_axi_rvalid_i_reg;
output s_axi_bvalid_i_reg;
output bus2ip_cs;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output [0:0]Q;
output [0:0]E;
output [0:0]bus2ip_rnw_i_reg;
output [0:0]bus2ip_rnw_i_reg_0;
output [0:7]Read_Reg2_In;
output ip2bus_rdack_i_D1_reg;
output ip2bus_wrack_i_D1_reg;
output [8:0]s_axi_rdata;
output [8:0]D;
input s_axi_aclk;
input s_axi_arvalid;
input [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
input [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ;
input s_axi_rready;
input s_axi_bready;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input [8:0]\s_axi_rdata_i_reg[31] ;
input \ip2bus_data_i_D1_reg[31] ;
input [7:0]reg1;
input [7:0]reg2;
input [7:0]reg3;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
wire Bus_RNW_reg;
wire [8:0]D;
wire [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
wire [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [0:0]Q;
wire [0:7]Read_Reg2_In;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire \ip2bus_data_i_D1_reg[31] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_rdack_i_D1_reg;
wire ip2bus_wrack_i_D1;
wire ip2bus_wrack_i_D1_reg;
wire [7:0]reg1;
wire [7:0]reg2;
wire [7:0]reg3;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid_i_reg;
wire [8:0]s_axi_rdata;
wire [8:0]\s_axi_rdata_i_reg[31] ;
wire s_axi_rready;
wire s_axi_rvalid_i_reg;
wire s_axi_wvalid;
xlnx_axi_gpio_slave_attachment I_SLAVE_ATTACHMENT
(.Bus_RNW_reg_reg(Bus_RNW_reg),
.D(D),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ),
.E(E),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.Q(Q),
.Read_Reg2_In(Read_Reg2_In),
.SR(bus2ip_reset),
.bus2ip_rnw_i_reg_0(bus2ip_rnw),
.bus2ip_rnw_i_reg_1(bus2ip_rnw_i_reg),
.bus2ip_rnw_i_reg_2(bus2ip_rnw_i_reg_0),
.\ip2bus_data_i_D1_reg[31] (\ip2bus_data_i_D1_reg[31] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_rdack_i_D1_reg(ip2bus_rdack_i_D1_reg),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.ip2bus_wrack_i_D1_reg(ip2bus_wrack_i_D1_reg),
.reg1(reg1),
.reg2(reg2),
.reg3(reg3),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid_i_reg_0(s_axi_bvalid_i_reg),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rdata_i_reg[31]_0 (\s_axi_rdata_i_reg[31] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid_i_reg_0(s_axi_rvalid_i_reg),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module xlnx_axi_gpio_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [7:0]scndry_vect_out;
input [7:0]gpio_io_i;
input s_axi_aclk;
wire [7:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire [7:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module xlnx_axi_gpio_cdc_sync_0
(scndry_vect_out,
gpio2_io_i,
s_axi_aclk);
output [7:0]scndry_vect_out;
input [7:0]gpio2_io_i;
input s_axi_aclk;
wire [7:0]gpio2_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire [7:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module xlnx_axi_gpio_slave_attachment
(SR,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
bus2ip_rnw_i_reg_0,
Bus_RNW_reg_reg,
s_axi_rvalid_i_reg_0,
s_axi_bvalid_i_reg_0,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
Q,
E,
bus2ip_rnw_i_reg_1,
bus2ip_rnw_i_reg_2,
Read_Reg2_In,
ip2bus_rdack_i_D1_reg,
ip2bus_wrack_i_D1_reg,
s_axi_rdata,
D,
s_axi_aclk,
s_axi_arvalid,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ,
s_axi_rready,
s_axi_bready,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
\s_axi_rdata_i_reg[31]_0 ,
\ip2bus_data_i_D1_reg[31] ,
reg1,
reg2,
reg3,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_araddr,
s_axi_awaddr);
output [0:0]SR;
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
output bus2ip_rnw_i_reg_0;
output Bus_RNW_reg_reg;
output s_axi_rvalid_i_reg_0;
output s_axi_bvalid_i_reg_0;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output [0:0]Q;
output [0:0]E;
output [0:0]bus2ip_rnw_i_reg_1;
output [0:0]bus2ip_rnw_i_reg_2;
output [0:7]Read_Reg2_In;
output ip2bus_rdack_i_D1_reg;
output ip2bus_wrack_i_D1_reg;
output [8:0]s_axi_rdata;
output [8:0]D;
input s_axi_aclk;
input s_axi_arvalid;
input [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
input [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ;
input s_axi_rready;
input s_axi_bready;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input [8:0]\s_axi_rdata_i_reg[31]_0 ;
input \ip2bus_data_i_D1_reg[31] ;
input [7:0]reg1;
input [7:0]reg2;
input [7:0]reg3;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
wire Bus_RNW_reg_reg;
wire [8:0]D;
wire [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
wire [7:0]\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 ;
wire [0:0]E;
wire \FSM_onehot_state[0]_i_1_n_0 ;
wire \FSM_onehot_state[1]_i_1_n_0 ;
wire \FSM_onehot_state[2]_i_1_n_0 ;
wire \FSM_onehot_state[3]_i_1_n_0 ;
wire \FSM_onehot_state_reg_n_0_[0] ;
wire \FSM_onehot_state_reg_n_0_[3] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire [0:0]Q;
wire [0:7]Read_Reg2_In;
wire [0:0]SR;
wire [0:5]bus2ip_addr;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire bus2ip_rnw_i_reg_0;
wire [0:0]bus2ip_rnw_i_reg_1;
wire [0:0]bus2ip_rnw_i_reg_2;
wire clear;
wire \ip2bus_data_i_D1_reg[31] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_rdack_i_D1_reg;
wire ip2bus_wrack_i_D1;
wire ip2bus_wrack_i_D1_reg;
wire is_read_i_1_n_0;
wire is_read_reg_n_0;
wire is_write_i_1_n_0;
wire is_write_i_2_n_0;
wire is_write_reg_n_0;
wire [8:2]p_1_in;
wire p_5_in;
wire [3:0]plusOp;
wire [7:0]reg1;
wire [7:0]reg2;
wire [7:0]reg3;
wire rst_i_1_n_0;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bresp_i;
wire s_axi_bvalid_i_i_1_n_0;
wire s_axi_bvalid_i_reg_0;
wire [8:0]s_axi_rdata;
wire [8:0]\s_axi_rdata_i_reg[31]_0 ;
wire s_axi_rready;
wire s_axi_rresp_i;
wire s_axi_rvalid_i_i_1_n_0;
wire s_axi_rvalid_i_reg_0;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire state1__2;
wire \state[0]_i_1_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state_reg_n_0_[0] ;
wire \state_reg_n_0_[1] ;
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3[24]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [7]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [7]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[0]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3[25]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [6]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [6]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[1]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3[26]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [5]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [5]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[2]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3[27]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [4]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [4]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[3]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3[28]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [3]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [3]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[4]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3[29]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [2]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [2]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[5]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3[30]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [1]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [1]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[6]));
LUT5 #(
.INIT(32'h0A000C00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_1
(.I0(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] [0]),
.I1(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0 [0]),
.I2(bus2ip_addr[0]),
.I3(bus2ip_addr[5]),
.I4(Q),
.O(Read_Reg2_In[7]));
LUT6 #(
.INIT(64'hFFFF150015001500))
\FSM_onehot_state[0]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(\FSM_onehot_state_reg_n_0_[0] ),
.I4(state1__2),
.I5(\FSM_onehot_state_reg_n_0_[3] ),
.O(\FSM_onehot_state[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8F88))
\FSM_onehot_state[1]_i_1
(.I0(s_axi_arvalid),
.I1(\FSM_onehot_state_reg_n_0_[0] ),
.I2(ip2bus_rdack_i_D1_reg),
.I3(s_axi_rresp_i),
.O(\FSM_onehot_state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800FFFF08000800))
\FSM_onehot_state[2]_i_1
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.I3(\FSM_onehot_state_reg_n_0_[0] ),
.I4(ip2bus_wrack_i_D1_reg),
.I5(s_axi_bresp_i),
.O(\FSM_onehot_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF888F888FFFFF888))
\FSM_onehot_state[3]_i_1
(.I0(ip2bus_wrack_i_D1_reg),
.I1(s_axi_bresp_i),
.I2(s_axi_rresp_i),
.I3(ip2bus_rdack_i_D1_reg),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(state1__2),
.O(\FSM_onehot_state[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'hF888))
\FSM_onehot_state[3]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid_i_reg_0),
.I2(s_axi_rready),
.I3(s_axi_rvalid_i_reg_0),
.O(state1__2));
(* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_onehot_state[0]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[0] ),
.S(SR));
(* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_onehot_state[1]_i_1_n_0 ),
.Q(s_axi_rresp_i),
.R(SR));
(* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_onehot_state[2]_i_1_n_0 ),
.Q(s_axi_bresp_i),
.R(SR));
(* FSM_ENCODED_STATES = "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_onehot_state[3]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[3] ),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(\state_reg_n_0_[0] ),
.I1(\state_reg_n_0_[1] ),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg [3]),
.R(clear));
xlnx_axi_gpio_address_decoder I_DECODER
(.Bus_RNW_reg_reg_0(Bus_RNW_reg_reg),
.Bus_RNW_reg_reg_1(bus2ip_rnw_i_reg_0),
.D(D),
.\Dual.gpio_Data_Out_reg[0] ({bus2ip_addr[0],bus2ip_addr[5],Q}),
.E(E),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3] ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1 (\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.Q(start2),
.bus2ip_rnw_i_reg(bus2ip_rnw_i_reg_1),
.bus2ip_rnw_i_reg_0(bus2ip_rnw_i_reg_2),
.\ip2bus_data_i_D1_reg[31] (\ip2bus_data_i_D1_reg[31] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_rdack_i_D1_reg(ip2bus_rdack_i_D1_reg),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.ip2bus_wrack_i_D1_reg(ip2bus_wrack_i_D1_reg),
.reg1(reg1),
.reg2(reg2),
.reg3(reg3),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(is_read_reg_n_0),
.s_axi_arready_0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg ),
.s_axi_awready(is_write_reg_n_0));
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(s_axi_arvalid),
.O(p_1_in[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(s_axi_arvalid),
.O(p_1_in[3]));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(\state_reg_n_0_[1] ),
.I4(\state_reg_n_0_[0] ),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(s_axi_arvalid),
.O(p_1_in[8]));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(p_1_in[2]),
.Q(Q),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(p_1_in[3]),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(p_1_in[8]),
.Q(bus2ip_addr[0]),
.R(SR));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(s_axi_arvalid),
.Q(bus2ip_rnw_i_reg_0),
.R(SR));
LUT5 #(
.INIT(32'h8BBB8888))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\FSM_onehot_state_reg_n_0_[0] ),
.I2(state1__2),
.I3(\FSM_onehot_state_reg_n_0_[3] ),
.I4(is_read_reg_n_0),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read_reg_n_0),
.R(SR));
LUT6 #(
.INIT(64'h2000FFFF20000000))
is_write_i_1
(.I0(\FSM_onehot_state_reg_n_0_[0] ),
.I1(s_axi_arvalid),
.I2(s_axi_awvalid),
.I3(s_axi_wvalid),
.I4(is_write_i_2_n_0),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hFFEAEAEAAAAAAAAA))
is_write_i_2
(.I0(\FSM_onehot_state_reg_n_0_[0] ),
.I1(s_axi_bready),
.I2(s_axi_bvalid_i_reg_0),
.I3(s_axi_rready),
.I4(s_axi_rvalid_i_reg_0),
.I5(\FSM_onehot_state_reg_n_0_[3] ),
.O(is_write_i_2_n_0));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(rst_i_1_n_0));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rst_i_1_n_0),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(ip2bus_wrack_i_D1_reg),
.I1(\state_reg_n_0_[1] ),
.I2(\state_reg_n_0_[0] ),
.I3(s_axi_bready),
.I4(s_axi_bvalid_i_reg_0),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid_i_reg_0),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [8]),
.Q(s_axi_rdata[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rresp_i),
.D(\s_axi_rdata_i_reg[31]_0 [7]),
.Q(s_axi_rdata[7]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(ip2bus_rdack_i_D1_reg),
.I1(\state_reg_n_0_[0] ),
.I2(\state_reg_n_0_[1] ),
.I3(s_axi_rready),
.I4(s_axi_rvalid_i_reg_0),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid_i_reg_0),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(\state_reg_n_0_[1] ),
.I4(\state_reg_n_0_[0] ),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h0FCAFFCA))
\state[0]_i_1
(.I0(s_axi_arvalid),
.I1(ip2bus_wrack_i_D1_reg),
.I2(\state_reg_n_0_[1] ),
.I3(\state_reg_n_0_[0] ),
.I4(state1__2),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h55FFFF0C5500FF0C))
\state[1]_i_1
(.I0(state1__2),
.I1(p_5_in),
.I2(s_axi_arvalid),
.I3(\state_reg_n_0_[1] ),
.I4(\state_reg_n_0_[0] ),
.I5(ip2bus_rdack_i_D1_reg),
.O(\state[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\state[1]_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(p_5_in));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\state_reg_n_0_[0] ),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(\state_reg_n_0_[1] ),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Tue Sep 20 00:11:22 2022
-- Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_sim_netlist.vhdl
-- Design : xlnx_axi_gpio
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xlnx_axi_gpio_address_decoder is
port (
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : out STD_LOGIC;
Bus_RNW_reg_reg_0 : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2bus_rdack_i_D1_reg : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Dual.gpio_Data_Out_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Bus_RNW_reg_reg_1 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
s_axi_arready : in STD_LOGIC;
s_axi_arready_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
\ip2bus_data_i_D1_reg[31]\ : in STD_LOGIC;
reg1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of xlnx_axi_gpio_address_decoder : entity is "address_decoder";
end xlnx_axi_gpio_address_decoder;
architecture STRUCTURE of xlnx_axi_gpio_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \^bus_rnw_reg_reg_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \ip2bus_data_i_D1[24]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[25]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[26]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[27]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[28]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[29]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[30]_i_2_n_0\ : STD_LOGIC;
signal \ip2bus_data_i_D1[31]_i_2_n_0\ : STD_LOGIC;
signal \^ip2bus_rdack_i_d1_reg\ : STD_LOGIC;
signal \^ip2bus_wrack_i_d1_reg\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio2_OE[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_OE[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair2";
begin
Bus_RNW_reg_reg_0 <= \^bus_rnw_reg_reg_0\;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ <= \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ <= \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ <= \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ <= \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
ip2bus_rdack_i_D1_reg <= \^ip2bus_rdack_i_d1_reg\;
ip2bus_wrack_i_D1_reg <= \^ip2bus_wrack_i_d1_reg\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Bus_RNW_reg_reg_1,
I1 => Q,
I2 => \^bus_rnw_reg_reg_0\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^bus_rnw_reg_reg_0\,
R => '0'
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \Dual.gpio_Data_Out_reg[0]\(2),
I2 => \Dual.gpio_Data_Out_reg[0]\(1),
O => \MEM_DECODE_GEN[0].cs_out_i_reg[0]_1\
);
\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => Bus_RNW_reg_reg_1,
I1 => \Dual.gpio_Data_Out_reg[0]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \Dual.gpio_Data_Out_reg[0]\(1),
I4 => \Dual.gpio_Data_Out_reg[0]\(0),
O => bus2ip_rnw_i_reg_0(0)
);
\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000100"
)
port map (
I0 => Bus_RNW_reg_reg_1,
I1 => \Dual.gpio_Data_Out_reg[0]\(1),
I2 => \Dual.gpio_Data_Out_reg[0]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \Dual.gpio_Data_Out_reg[0]\(0),
O => E(0)
);
\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => Bus_RNW_reg_reg_1,
I1 => \Dual.gpio_Data_Out_reg[0]\(1),
I2 => \Dual.gpio_Data_Out_reg[0]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \Dual.gpio_Data_Out_reg[0]\(0),
O => bus2ip_rnw_i_reg(0)
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \Dual.gpio_Data_Out_reg[0]\(1),
I1 => \Dual.gpio_Data_Out_reg[0]\(0),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \Dual.gpio_Data_Out_reg[0]\(1),
I1 => \Dual.gpio_Data_Out_reg[0]\(0),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => \Dual.gpio_Data_Out_reg[0]\(0),
I1 => \Dual.gpio_Data_Out_reg[0]\(1),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^ip2bus_wrack_i_d1_reg\,
I1 => \^ip2bus_rdack_i_d1_reg\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \Dual.gpio_Data_Out_reg[0]\(1),
I1 => \Dual.gpio_Data_Out_reg[0]\(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => Q,
I2 => s_axi_aresetn,
I3 => \^ip2bus_rdack_i_d1_reg\,
I4 => \^ip2bus_wrack_i_d1_reg\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
O => D(8)
);
\ip2bus_data_i_D1[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(7),
I4 => \ip2bus_data_i_D1[24]_i_2_n_0\,
O => D(7)
);
\ip2bus_data_i_D1[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(7),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(7),
O => \ip2bus_data_i_D1[24]_i_2_n_0\
);
\ip2bus_data_i_D1[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(6),
I4 => \ip2bus_data_i_D1[25]_i_2_n_0\,
O => D(6)
);
\ip2bus_data_i_D1[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(6),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(6),
O => \ip2bus_data_i_D1[25]_i_2_n_0\
);
\ip2bus_data_i_D1[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(5),
I4 => \ip2bus_data_i_D1[26]_i_2_n_0\,
O => D(5)
);
\ip2bus_data_i_D1[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(5),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(5),
O => \ip2bus_data_i_D1[26]_i_2_n_0\
);
\ip2bus_data_i_D1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(4),
I4 => \ip2bus_data_i_D1[27]_i_2_n_0\,
O => D(4)
);
\ip2bus_data_i_D1[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(4),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(4),
O => \ip2bus_data_i_D1[27]_i_2_n_0\
);
\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(3),
I4 => \ip2bus_data_i_D1[28]_i_2_n_0\,
O => D(3)
);
\ip2bus_data_i_D1[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(3),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(3),
O => \ip2bus_data_i_D1[28]_i_2_n_0\
);
\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(2),
I4 => \ip2bus_data_i_D1[29]_i_2_n_0\,
O => D(2)
);
\ip2bus_data_i_D1[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(2),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(2),
O => \ip2bus_data_i_D1[29]_i_2_n_0\
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(1),
I4 => \ip2bus_data_i_D1[30]_i_2_n_0\,
O => D(1)
);
\ip2bus_data_i_D1[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(1),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(1),
O => \ip2bus_data_i_D1[30]_i_2_n_0\
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA8000"
)
port map (
I0 => \ip2bus_data_i_D1_reg[31]\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[0].ce_out_i_reg[0]_0\,
I3 => reg1(0),
I4 => \ip2bus_data_i_D1[31]_i_2_n_0\,
O => D(0)
);
\ip2bus_data_i_D1[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCCC888C888C888"
)
port map (
I0 => \^gen_bkend_ce_registers[3].ce_out_i_reg[3]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \^gen_bkend_ce_registers[1].ce_out_i_reg[1]_0\,
I3 => reg2(0),
I4 => \^gen_bkend_ce_registers[2].ce_out_i_reg[2]_0\,
I5 => reg3(0),
O => \ip2bus_data_i_D1[31]_i_2_n_0\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => s_axi_arready,
I2 => s_axi_arready_0(2),
I3 => s_axi_arready_0(1),
I4 => s_axi_arready_0(3),
I5 => s_axi_arready_0(0),
O => \^ip2bus_rdack_i_d1_reg\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => s_axi_awready,
I2 => s_axi_arready_0(2),
I3 => s_axi_arready_0(1),
I4 => s_axi_arready_0(3),
I5 => s_axi_arready_0(0),
O => \^ip2bus_wrack_i_d1_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xlnx_axi_gpio_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of xlnx_axi_gpio_cdc_sync : entity is "cdc_sync";
end xlnx_axi_gpio_cdc_sync;
architecture STRUCTURE of xlnx_axi_gpio_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xlnx_axi_gpio_cdc_sync_0 is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of xlnx_axi_gpio_cdc_sync_0 : entity is "cdc_sync";
end xlnx_axi_gpio_cdc_sync_0;
architecture STRUCTURE of xlnx_axi_gpio_cdc_sync_0 is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xlnx_axi_gpio_GPIO_Core is
port (
reg1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
reg3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
reg2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
ip2bus_wrack_i : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
\Dual.gpio2_OE_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.gpio2_Data_In_reg[0]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
Read_Reg2_In : in STD_LOGIC_VECTOR ( 0 to 7 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.gpio_OE_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_OE_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of xlnx_axi_gpio_GPIO_Core : entity is "GPIO_Core";
end xlnx_axi_gpio_GPIO_Core;
architecture STRUCTURE of xlnx_axi_gpio_GPIO_Core is
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0\ : STD_LOGIC;
signal \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0\ : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal Read_Reg_Rst : STD_LOGIC;
signal gpio2_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 7 );
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 7 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal \^reg2\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ip2bus_wrack_i_D1_i_1 : label is "soft_lutpair9";
begin
gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0);
gpio_io_t(7 downto 0) <= \^gpio_io_t\(7 downto 0);
reg2(7 downto 0) <= \^reg2\(7 downto 0);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(0),
Q => reg3(7),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(1),
Q => reg3(6),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(2),
Q => reg3(5),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(3),
Q => reg3(4),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(4),
Q => reg3(3),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(5),
Q => reg3(2),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(6),
Q => reg3(1),
R => Read_Reg_Rst
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(7),
Q => reg3(0),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(0),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(7),
I4 => \^gpio_io_t\(7),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg1[24]_i_1_n_0\,
Q => reg1(7),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(0),
I1 => \^gpio_io_t\(7),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(7),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].reg2[24]_i_1_n_0\,
Q => \^reg2\(7),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(1),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(6),
I4 => \^gpio_io_t\(6),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg1[25]_i_1_n_0\,
Q => reg1(6),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(1),
I1 => \^gpio_io_t\(6),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(6),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].reg2[25]_i_1_n_0\,
Q => \^reg2\(6),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(2),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(5),
I4 => \^gpio_io_t\(5),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg1[26]_i_1_n_0\,
Q => reg1(5),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(2),
I1 => \^gpio_io_t\(5),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(5),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].reg2[26]_i_1_n_0\,
Q => \^reg2\(5),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(3),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(4),
I4 => \^gpio_io_t\(4),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg1[27]_i_1_n_0\,
Q => reg1(4),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(3),
I1 => \^gpio_io_t\(4),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(4),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].reg2[27]_i_1_n_0\,
Q => \^reg2\(4),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(4),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(3),
I4 => \^gpio_io_t\(3),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg1[28]_i_1_n_0\,
Q => reg1(3),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(4),
I1 => \^gpio_io_t\(3),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(3),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].reg2[28]_i_1_n_0\,
Q => \^reg2\(3),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(5),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(2),
I4 => \^gpio_io_t\(2),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg1[29]_i_1_n_0\,
Q => reg1(2),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(5),
I1 => \^gpio_io_t\(2),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(2),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].reg2[29]_i_1_n_0\,
Q => \^reg2\(2),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(6),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(1),
I4 => \^gpio_io_t\(1),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg1[30]_i_1_n_0\,
Q => reg1(1),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(6),
I1 => \^gpio_io_t\(1),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(1),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].reg2[30]_i_1_n_0\,
Q => \^reg2\(1),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => GPIO_xferAck_i,
I1 => gpio_xferAck_Reg,
I2 => bus2ip_rnw,
I3 => bus2ip_cs,
O => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"3232CF00"
)
port map (
I0 => gpio_Data_In(7),
I1 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I2 => Q(0),
I3 => \^gpio_io_o\(0),
I4 => \^gpio_io_t\(0),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg1[31]_i_2_n_0\,
Q => reg1(0),
R => Read_Reg_Rst
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"33CB00C8"
)
port map (
I0 => gpio_Data_In(7),
I1 => \^gpio_io_t\(0),
I2 => Q(0),
I3 => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\,
I4 => \^reg2\(0),
O => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0\
);
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2[31]_i_1_n_0\,
Q => \^reg2\(0),
R => Read_Reg_Rst
);
\Dual.INPUT_DOUBLE_REGS4\: entity work.xlnx_axi_gpio_cdc_sync
port map (
gpio_io_i(7 downto 0) => gpio_io_i(7 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(7) => gpio_io_i_d2(0),
scndry_vect_out(6) => gpio_io_i_d2(1),
scndry_vect_out(5) => gpio_io_i_d2(2),
scndry_vect_out(4) => gpio_io_i_d2(3),
scndry_vect_out(3) => gpio_io_i_d2(4),
scndry_vect_out(2) => gpio_io_i_d2(5),
scndry_vect_out(1) => gpio_io_i_d2(6),
scndry_vect_out(0) => gpio_io_i_d2(7)
);
\Dual.INPUT_DOUBLE_REGS5\: entity work.xlnx_axi_gpio_cdc_sync_0
port map (
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(7) => gpio2_io_i_d2(0),
scndry_vect_out(6) => gpio2_io_i_d2(1),
scndry_vect_out(5) => gpio2_io_i_d2(2),
scndry_vect_out(4) => gpio2_io_i_d2(3),
scndry_vect_out(3) => gpio2_io_i_d2(4),
scndry_vect_out(2) => gpio2_io_i_d2(5),
scndry_vect_out(1) => gpio2_io_i_d2(6),
scndry_vect_out(0) => gpio2_io_i_d2(7)
);
\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(0),
Q => \Dual.gpio2_Data_In_reg[0]_0\(7),
R => '0'
);
\Dual.gpio2_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(1),
Q => \Dual.gpio2_Data_In_reg[0]_0\(6),
R => '0'
);
\Dual.gpio2_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(2),
Q => \Dual.gpio2_Data_In_reg[0]_0\(5),
R => '0'
);
\Dual.gpio2_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(3),
Q => \Dual.gpio2_Data_In_reg[0]_0\(4),
R => '0'
);
\Dual.gpio2_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(4),
Q => \Dual.gpio2_Data_In_reg[0]_0\(3),
R => '0'
);
\Dual.gpio2_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(5),
Q => \Dual.gpio2_Data_In_reg[0]_0\(2),
R => '0'
);
\Dual.gpio2_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(6),
Q => \Dual.gpio2_Data_In_reg[0]_0\(1),
R => '0'
);
\Dual.gpio2_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(7),
Q => \Dual.gpio2_Data_In_reg[0]_0\(0),
R => '0'
);
\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(7),
Q => \Dual.gpio2_OE_reg[0]_0\(7),
S => SS(0)
);
\Dual.gpio2_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(6),
Q => \Dual.gpio2_OE_reg[0]_0\(6),
S => SS(0)
);
\Dual.gpio2_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(5),
Q => \Dual.gpio2_OE_reg[0]_0\(5),
S => SS(0)
);
\Dual.gpio2_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(4),
Q => \Dual.gpio2_OE_reg[0]_0\(4),
S => SS(0)
);
\Dual.gpio2_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(3),
Q => \Dual.gpio2_OE_reg[0]_0\(3),
S => SS(0)
);
\Dual.gpio2_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(2),
Q => \Dual.gpio2_OE_reg[0]_0\(2),
S => SS(0)
);
\Dual.gpio2_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(1),
Q => \Dual.gpio2_OE_reg[0]_0\(1),
S => SS(0)
);
\Dual.gpio2_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio2_OE_reg[0]_1\(0),
D => s_axi_wdata(0),
Q => \Dual.gpio2_OE_reg[0]_0\(0),
S => SS(0)
);
\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => gpio_Data_In(0),
R => '0'
);
\Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => gpio_Data_In(1),
R => '0'
);
\Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => gpio_Data_In(2),
R => '0'
);
\Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => gpio_Data_In(3),
R => '0'
);
\Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => gpio_Data_In(4),
R => '0'
);
\Dual.gpio_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(5),
Q => gpio_Data_In(5),
R => '0'
);
\Dual.gpio_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(6),
Q => gpio_Data_In(6),
R => '0'
);
\Dual.gpio_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(7),
Q => gpio_Data_In(7),
R => '0'
);
\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => \^gpio_io_o\(7),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => \^gpio_io_o\(6),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => \^gpio_io_o\(5),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => \^gpio_io_o\(4),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => \^gpio_io_o\(3),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => \^gpio_io_o\(2),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => \^gpio_io_o\(1),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => \^gpio_io_o\(0),
R => SS(0)
);
\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(7),
Q => \^gpio_io_t\(7),
S => SS(0)
);
\Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(6),
Q => \^gpio_io_t\(6),
S => SS(0)
);
\Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(5),
Q => \^gpio_io_t\(5),
S => SS(0)
);
\Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(4),
Q => \^gpio_io_t\(4),
S => SS(0)
);
\Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(3),
Q => \^gpio_io_t\(3),
S => SS(0)
);
\Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(2),
Q => \^gpio_io_t\(2),
S => SS(0)
);
\Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(1),
Q => \^gpio_io_t\(1),
S => SS(0)
);
\Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => \Dual.gpio_OE_reg[0]_0\(0),
D => s_axi_wdata(0),
Q => \^gpio_io_t\(0),
S => SS(0)
);
GPIO_DBus: unisim.vcomponents.LUT5
generic map(
INIT => X"00040448"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
O => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_xferAck_i,
Q => gpio_xferAck_Reg,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => GPIO_xferAck_i,
I1 => bus2ip_cs,
I2 => gpio_xferAck_Reg,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => GPIO_xferAck_i,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => GPIO_xferAck_i,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => GPIO_xferAck_i,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xlnx_axi_gpio_slave_attachment is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : out STD_LOGIC;
bus2ip_rnw_i_reg_0 : out STD_LOGIC;
Bus_RNW_reg_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_bvalid_i_reg_0 : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_1 : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 7 );
ip2bus_rdack_i_D1_reg : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\ip2bus_data_i_D1_reg[31]\ : in STD_LOGIC;
reg1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of xlnx_axi_gpio_slave_attachment : entity is "slave_attachment";
end xlnx_axi_gpio_slave_attachment;
architecture STRUCTURE of xlnx_axi_gpio_slave_attachment is
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[0]\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 5 );
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \^bus2ip_rnw_i_reg_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal \^ip2bus_rdack_i_d1_reg\ : STD_LOGIC;
signal \^ip2bus_wrack_i_d1_reg\ : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_read_reg_n_0 : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_i_2_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 8 downto 2 );
signal p_5_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_i_1_n_0 : STD_LOGIC;
signal s_axi_bresp_i : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_bvalid_i_reg_0\ : STD_LOGIC;
signal s_axi_rresp_i : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal \state1__2\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[0]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[1]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[2]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[3]\ : label is "iSTATE:0010,iSTATE0:0100,iSTATE1:1000,iSTATE2:0001";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_2\ : label is "soft_lutpair5";
begin
Q(0) <= \^q\(0);
SR(0) <= \^sr\(0);
bus2ip_rnw_i_reg_0 <= \^bus2ip_rnw_i_reg_0\;
ip2bus_rdack_i_D1_reg <= \^ip2bus_rdack_i_d1_reg\;
ip2bus_wrack_i_D1_reg <= \^ip2bus_wrack_i_d1_reg\;
s_axi_bvalid_i_reg_0 <= \^s_axi_bvalid_i_reg_0\;
s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(7),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(7),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(0)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(6),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(6),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(1)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(5),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(5),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(2)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(4),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(4),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(3)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(3),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(3),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(4)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(2),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(2),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(5)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(1),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(1),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(6)
);
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A000C00"
)
port map (
I0 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(0),
I1 => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(0),
I2 => bus2ip_addr(0),
I3 => bus2ip_addr(5),
I4 => \^q\(0),
O => Read_Reg2_In(7)
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF150015001500"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_wvalid,
I2 => s_axi_awvalid,
I3 => \FSM_onehot_state_reg_n_0_[0]\,
I4 => \state1__2\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F88"
)
port map (
I0 => s_axi_arvalid,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \^ip2bus_rdack_i_d1_reg\,
I3 => s_axi_rresp_i,
O => \FSM_onehot_state[1]_i_1_n_0\
);
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800FFFF08000800"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
I3 => \FSM_onehot_state_reg_n_0_[0]\,
I4 => \^ip2bus_wrack_i_d1_reg\,
I5 => s_axi_bresp_i,
O => \FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F888F888FFFFF888"
)
port map (
I0 => \^ip2bus_wrack_i_d1_reg\,
I1 => s_axi_bresp_i,
I2 => s_axi_rresp_i,
I3 => \^ip2bus_rdack_i_d1_reg\,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => \state1__2\,
O => \FSM_onehot_state[3]_i_1_n_0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid_i_reg_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid_i_reg_0\,
O => \state1__2\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[0]\,
S => \^sr\(0)
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_onehot_state[1]_i_1_n_0\,
Q => s_axi_rresp_i,
R => \^sr\(0)
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_onehot_state[2]_i_1_n_0\,
Q => s_axi_bresp_i,
R => \^sr\(0)
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_onehot_state[3]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => \^sr\(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3),
R => clear
);
I_DECODER: entity work.xlnx_axi_gpio_address_decoder
port map (
Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg,
Bus_RNW_reg_reg_1 => \^bus2ip_rnw_i_reg_0\,
D(8 downto 0) => D(8 downto 0),
\Dual.gpio_Data_Out_reg[0]\(2) => bus2ip_addr(0),
\Dual.gpio_Data_Out_reg[0]\(1) => bus2ip_addr(5),
\Dual.gpio_Data_Out_reg[0]\(0) => \^q\(0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]_0\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_1\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\,
Q => start2,
bus2ip_rnw_i_reg(0) => bus2ip_rnw_i_reg_1(0),
bus2ip_rnw_i_reg_0(0) => bus2ip_rnw_i_reg_2(0),
\ip2bus_data_i_D1_reg[31]\ => \ip2bus_data_i_D1_reg[31]\,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_rdack_i_D1_reg => \^ip2bus_rdack_i_d1_reg\,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
ip2bus_wrack_i_D1_reg => \^ip2bus_wrack_i_d1_reg\,
reg1(7 downto 0) => reg1(7 downto 0),
reg2(7 downto 0) => reg2(7 downto 0),
reg3(7 downto 0) => reg3(7 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => is_read_reg_n_0,
s_axi_arready_0(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg\(3 downto 0),
s_axi_awready => is_write_reg_n_0
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => s_axi_arvalid,
O => p_1_in(2)
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => s_axi_arvalid,
O => p_1_in(3)
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => s_axi_arvalid,
O => p_1_in(8)
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => p_1_in(2),
Q => \^q\(0),
R => \^sr\(0)
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => p_1_in(3),
Q => bus2ip_addr(5),
R => \^sr\(0)
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => p_1_in(8),
Q => bus2ip_addr(0),
R => \^sr\(0)
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => s_axi_arvalid,
Q => \^bus2ip_rnw_i_reg_0\,
R => \^sr\(0)
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8888"
)
port map (
I0 => s_axi_arvalid,
I1 => \FSM_onehot_state_reg_n_0_[0]\,
I2 => \state1__2\,
I3 => \FSM_onehot_state_reg_n_0_[3]\,
I4 => is_read_reg_n_0,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read_reg_n_0,
R => \^sr\(0)
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"2000FFFF20000000"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => s_axi_arvalid,
I2 => s_axi_awvalid,
I3 => s_axi_wvalid,
I4 => is_write_i_2_n_0,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAEAEAAAAAAAAA"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[0]\,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid_i_reg_0\,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid_i_reg_0\,
I5 => \FSM_onehot_state_reg_n_0_[3]\,
O => is_write_i_2_n_0
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\(0)
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => rst_i_1_n_0
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_i_1_n_0,
Q => \^sr\(0),
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^ip2bus_wrack_i_d1_reg\,
I1 => \state_reg_n_0_[1]\,
I2 => \state_reg_n_0_[0]\,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid_i_reg_0\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid_i_reg_0\,
R => \^sr\(0)
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(0),
Q => s_axi_rdata(0),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(1),
Q => s_axi_rdata(1),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(2),
Q => s_axi_rdata(2),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(8),
Q => s_axi_rdata(8),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(3),
Q => s_axi_rdata(3),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(4),
Q => s_axi_rdata(4),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(5),
Q => s_axi_rdata(5),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(6),
Q => s_axi_rdata(6),
R => \^sr\(0)
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rresp_i,
D => \s_axi_rdata_i_reg[31]_0\(7),
Q => s_axi_rdata(7),
R => \^sr\(0)
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^ip2bus_rdack_i_d1_reg\,
I1 => \state_reg_n_0_[0]\,
I2 => \state_reg_n_0_[1]\,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid_i_reg_0\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid_i_reg_0\,
R => \^sr\(0)
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\(0)
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FCAFFCA"
)
port map (
I0 => s_axi_arvalid,
I1 => \^ip2bus_wrack_i_d1_reg\,
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
I4 => \state1__2\,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FFFF0C5500FF0C"
)
port map (
I0 => \state1__2\,
I1 => p_5_in,
I2 => s_axi_arvalid,
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \^ip2bus_rdack_i_d1_reg\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => p_5_in
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => \^sr\(0)
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xlnx_axi_gpio_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 7 );
ip2bus_rdack_i_D1_reg : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\ip2bus_data_i_D1_reg[31]\ : in STD_LOGIC;
reg1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
reg3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of xlnx_axi_gpio_axi_lite_ipif : entity is "axi_lite_ipif";
end xlnx_axi_gpio_axi_lite_ipif;
architecture STRUCTURE of xlnx_axi_gpio_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.xlnx_axi_gpio_slave_attachment
port map (
Bus_RNW_reg_reg => Bus_RNW_reg,
D(8 downto 0) => D(8 downto 0),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(7 downto 0) => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(7 downto 0),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(7 downto 0) => \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(7 downto 0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
Q(0) => Q(0),
Read_Reg2_In(0 to 7) => Read_Reg2_In(0 to 7),
SR(0) => bus2ip_reset,
bus2ip_rnw_i_reg_0 => bus2ip_rnw,
bus2ip_rnw_i_reg_1(0) => bus2ip_rnw_i_reg(0),
bus2ip_rnw_i_reg_2(0) => bus2ip_rnw_i_reg_0(0),
\ip2bus_data_i_D1_reg[31]\ => \ip2bus_data_i_D1_reg[31]\,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_rdack_i_D1_reg => ip2bus_rdack_i_D1_reg,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
ip2bus_wrack_i_D1_reg => ip2bus_wrack_i_D1_reg,
reg1(7 downto 0) => reg1(7 downto 0),
reg2(7 downto 0) => reg2(7 downto 0),
reg3(7 downto 0) => reg3(7 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg_0 => s_axi_bvalid_i_reg,
s_axi_rdata(8 downto 0) => s_axi_rdata(8 downto 0),
\s_axi_rdata_i_reg[31]_0\(8 downto 0) => \s_axi_rdata_i_reg[31]\(8 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xlnx_axi_gpio_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of xlnx_axi_gpio_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of xlnx_axi_gpio_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of xlnx_axi_gpio_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of xlnx_axi_gpio_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of xlnx_axi_gpio_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of xlnx_axi_gpio_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of xlnx_axi_gpio_axi_gpio : entity is "kintex7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of xlnx_axi_gpio_axi_gpio : entity is 8;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of xlnx_axi_gpio_axi_gpio : entity is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of xlnx_axi_gpio_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of xlnx_axi_gpio_axi_gpio : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of xlnx_axi_gpio_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of xlnx_axi_gpio_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of xlnx_axi_gpio_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of xlnx_axi_gpio_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of xlnx_axi_gpio_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of xlnx_axi_gpio_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of xlnx_axi_gpio_axi_gpio : entity is "LOGICORE";
end xlnx_axi_gpio_axi_gpio;
architecture STRUCTURE of xlnx_axi_gpio_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal GPIO_DBus : STD_LOGIC_VECTOR ( 0 to 31 );
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal Read_Reg2_In : STD_LOGIC_VECTOR ( 0 to 7 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 6 to 6 );
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio2_Data_In : STD_LOGIC_VECTOR ( 0 to 7 );
signal gpio_core_1_n_24 : STD_LOGIC;
signal gpio_core_1_n_43 : STD_LOGIC;
signal gpio_core_1_n_44 : STD_LOGIC;
signal gpio_core_1_n_45 : STD_LOGIC;
signal gpio_core_1_n_46 : STD_LOGIC;
signal gpio_core_1_n_47 : STD_LOGIC;
signal gpio_core_1_n_48 : STD_LOGIC;
signal gpio_core_1_n_49 : STD_LOGIC;
signal gpio_core_1_n_50 : STD_LOGIC;
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal reg1 : STD_LOGIC_VECTOR ( 24 to 31 );
signal reg2 : STD_LOGIC_VECTOR ( 24 to 31 );
signal reg3 : STD_LOGIC_VECTOR ( 24 to 31 );
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
attribute sigis : string;
attribute sigis of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
attribute sigis of s_axi_aclk : signal is "Clk";
attribute sigis of s_axi_aresetn : signal is "Rst";
begin
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(7) <= \<const0>\;
gpio2_io_t(6) <= \<const0>\;
gpio2_io_t(5) <= \<const0>\;
gpio2_io_t(4) <= \<const0>\;
gpio2_io_t(3) <= \<const0>\;
gpio2_io_t(2) <= \<const0>\;
gpio2_io_t(1) <= \<const0>\;
gpio2_io_t(0) <= \<const0>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_awready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(30);
s_axi_rdata(30) <= \^s_axi_rdata\(30);
s_axi_rdata(29) <= \^s_axi_rdata\(30);
s_axi_rdata(28) <= \^s_axi_rdata\(30);
s_axi_rdata(27) <= \^s_axi_rdata\(30);
s_axi_rdata(26) <= \^s_axi_rdata\(30);
s_axi_rdata(25) <= \^s_axi_rdata\(30);
s_axi_rdata(24) <= \^s_axi_rdata\(30);
s_axi_rdata(23) <= \^s_axi_rdata\(30);
s_axi_rdata(22) <= \^s_axi_rdata\(30);
s_axi_rdata(21) <= \^s_axi_rdata\(30);
s_axi_rdata(20) <= \^s_axi_rdata\(30);
s_axi_rdata(19) <= \^s_axi_rdata\(30);
s_axi_rdata(18) <= \^s_axi_rdata\(30);
s_axi_rdata(17) <= \^s_axi_rdata\(30);
s_axi_rdata(16) <= \^s_axi_rdata\(30);
s_axi_rdata(15) <= \^s_axi_rdata\(30);
s_axi_rdata(14) <= \^s_axi_rdata\(30);
s_axi_rdata(13) <= \^s_axi_rdata\(30);
s_axi_rdata(12) <= \^s_axi_rdata\(30);
s_axi_rdata(11) <= \^s_axi_rdata\(30);
s_axi_rdata(10) <= \^s_axi_rdata\(30);
s_axi_rdata(9) <= \^s_axi_rdata\(30);
s_axi_rdata(8) <= \^s_axi_rdata\(30);
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_awready\;
AXI_LITE_IPIF_I: entity work.xlnx_axi_gpio_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(8) => GPIO_DBus(0),
D(7) => GPIO_DBus(24),
D(6) => GPIO_DBus(25),
D(5) => GPIO_DBus(26),
D(4) => GPIO_DBus(27),
D(3) => GPIO_DBus(28),
D(2) => GPIO_DBus(29),
D(1) => GPIO_DBus(30),
D(0) => GPIO_DBus(31),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(7) => gpio_core_1_n_43,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(6) => gpio_core_1_n_44,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(5) => gpio_core_1_n_45,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(4) => gpio_core_1_n_46,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(3) => gpio_core_1_n_47,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(2) => gpio_core_1_n_48,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(1) => gpio_core_1_n_49,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]\(0) => gpio_core_1_n_50,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(7) => gpio2_Data_In(0),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(6) => gpio2_Data_In(1),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(5) => gpio2_Data_In(2),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(4) => gpio2_Data_In(3),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(3) => gpio2_Data_In(4),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(2) => gpio2_Data_In(5),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(1) => gpio2_Data_In(6),
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]_0\(0) => gpio2_Data_In(7),
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_10,
Q(0) => bus2ip_addr(6),
Read_Reg2_In(0 to 7) => Read_Reg2_In(0 to 7),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_13,
bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_14,
\ip2bus_data_i_D1_reg[31]\ => gpio_core_1_n_24,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_rdack_i_D1_reg => s_axi_arready,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
ip2bus_wrack_i_D1_reg => \^s_axi_awready\,
reg1(7) => reg1(24),
reg1(6) => reg1(25),
reg1(5) => reg1(26),
reg1(4) => reg1(27),
reg1(3) => reg1(28),
reg1(2) => reg1(29),
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(7) => reg2(24),
reg2(6) => reg2(25),
reg2(5) => reg2(26),
reg2(4) => reg2(27),
reg2(3) => reg2(28),
reg2(2) => reg2(29),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
reg3(7) => reg3(24),
reg3(6) => reg3(25),
reg3(5) => reg3(26),
reg3(4) => reg3(27),
reg3(3) => reg3(28),
reg3(2) => reg3(29),
reg3(1) => reg3(30),
reg3(0) => reg3(31),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg => s_axi_bvalid,
s_axi_rdata(8) => \^s_axi_rdata\(30),
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
\s_axi_rdata_i_reg[31]\(8) => ip2bus_data_i_D1(0),
\s_axi_rdata_i_reg[31]\(7) => ip2bus_data_i_D1(24),
\s_axi_rdata_i_reg[31]\(6) => ip2bus_data_i_D1(25),
\s_axi_rdata_i_reg[31]\(5) => ip2bus_data_i_D1(26),
\s_axi_rdata_i_reg[31]\(4) => ip2bus_data_i_D1(27),
\s_axi_rdata_i_reg[31]\(3) => ip2bus_data_i_D1(28),
\s_axi_rdata_i_reg[31]\(2) => ip2bus_data_i_D1(29),
\s_axi_rdata_i_reg[31]\(1) => ip2bus_data_i_D1(30),
\s_axi_rdata_i_reg[31]\(0) => ip2bus_data_i_D1(31),
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg => s_axi_rvalid,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
gpio_core_1: entity work.xlnx_axi_gpio_GPIO_Core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].reg2_reg[31]_0\ => AXI_LITE_IPIF_I_n_10,
\Dual.gpio2_Data_In_reg[0]_0\(7) => gpio2_Data_In(0),
\Dual.gpio2_Data_In_reg[0]_0\(6) => gpio2_Data_In(1),
\Dual.gpio2_Data_In_reg[0]_0\(5) => gpio2_Data_In(2),
\Dual.gpio2_Data_In_reg[0]_0\(4) => gpio2_Data_In(3),
\Dual.gpio2_Data_In_reg[0]_0\(3) => gpio2_Data_In(4),
\Dual.gpio2_Data_In_reg[0]_0\(2) => gpio2_Data_In(5),
\Dual.gpio2_Data_In_reg[0]_0\(1) => gpio2_Data_In(6),
\Dual.gpio2_Data_In_reg[0]_0\(0) => gpio2_Data_In(7),
\Dual.gpio2_OE_reg[0]_0\(7) => gpio_core_1_n_43,
\Dual.gpio2_OE_reg[0]_0\(6) => gpio_core_1_n_44,
\Dual.gpio2_OE_reg[0]_0\(5) => gpio_core_1_n_45,
\Dual.gpio2_OE_reg[0]_0\(4) => gpio_core_1_n_46,
\Dual.gpio2_OE_reg[0]_0\(3) => gpio_core_1_n_47,
\Dual.gpio2_OE_reg[0]_0\(2) => gpio_core_1_n_48,
\Dual.gpio2_OE_reg[0]_0\(1) => gpio_core_1_n_49,
\Dual.gpio2_OE_reg[0]_0\(0) => gpio_core_1_n_50,
\Dual.gpio2_OE_reg[0]_1\(0) => AXI_LITE_IPIF_I_n_14,
\Dual.gpio_OE_reg[0]_0\(0) => AXI_LITE_IPIF_I_n_13,
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => gpio_core_1_n_24,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
Q(0) => bus2ip_addr(6),
Read_Reg2_In(0 to 7) => Read_Reg2_In(0 to 7),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
gpio_io_i(7 downto 0) => gpio_io_i(7 downto 0),
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i => ip2bus_wrack_i,
reg1(7) => reg1(24),
reg1(6) => reg1(25),
reg1(5) => reg1(26),
reg1(4) => reg1(27),
reg1(3) => reg1(28),
reg1(2) => reg1(29),
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(7) => reg2(24),
reg2(6) => reg2(25),
reg2(5) => reg2(26),
reg2(4) => reg2(27),
reg2(3) => reg2(28),
reg2(2) => reg2(29),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
reg3(7) => reg3(24),
reg3(6) => reg3(25),
reg3(5) => reg3(26),
reg3(4) => reg3(27),
reg3(3) => reg3(28),
reg3(2) => reg3(29),
reg3(1) => reg3(30),
reg3(0) => reg3(31),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0)
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_i,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity xlnx_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of xlnx_axi_gpio : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of xlnx_axi_gpio : entity is "xlnx_axi_gpio,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of xlnx_axi_gpio : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of xlnx_axi_gpio : entity is "axi_gpio,Vivado 2021.2";
end xlnx_axi_gpio;
architecture STRUCTURE of xlnx_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 1;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 8;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute x_interface_info : string;
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of gpio2_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
attribute x_interface_parameter of gpio2_io_i : signal is "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute x_interface_parameter of gpio_io_i : signal is "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_o : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
attribute x_interface_info of gpio_io_t : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.xlnx_axi_gpio_axi_gpio
port map (
gpio2_io_i(7 downto 0) => gpio2_io_i(7 downto 0),
gpio2_io_o(7 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(7 downto 0),
gpio2_io_t(7 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(7 downto 0),
gpio_io_i(7 downto 0) => gpio_io_i(7 downto 0),
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8) => s_axi_araddr(8),
s_axi_araddr(7 downto 4) => B"0000",
s_axi_araddr(3 downto 2) => s_axi_araddr(3 downto 2),
s_axi_araddr(1 downto 0) => B"00",
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8) => s_axi_awaddr(8),
s_axi_awaddr(7 downto 4) => B"0000",
s_axi_awaddr(3 downto 2) => s_axi_awaddr(3 downto 2),
s_axi_awaddr(1 downto 0) => B"00",
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 8) => B"000000000000000000000000",
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
// Date : Tue Sep 20 00:11:22 2022
// Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_stub.v
// Design : xlnx_axi_gpio
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2021.2" *)
module xlnx_axi_gpio(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t,
gpio2_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[7:0],gpio_io_o[7:0],gpio_io_t[7:0],gpio2_io_i[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [7:0]gpio_io_i;
output [7:0]gpio_io_o;
output [7:0]gpio_io_t;
input [7:0]gpio2_io_i;
endmodule
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Tue Sep 20 00:11:22 2022
-- Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_stub.vhdl
-- Design : xlnx_axi_gpio
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xlnx_axi_gpio is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end xlnx_axi_gpio;
architecture stub of xlnx_axi_gpio is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[7:0],gpio_io_o[7:0],gpio_io_t[7:0],gpio2_io_i[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2021.2";
begin
end;
|
2021.2:
* Version 2.0 (Rev. 27)
* Revision change in one or more subcores
2021.1.1:
* Version 2.0 (Rev. 26)
* No changes
2021.1:
* Version 2.0 (Rev. 26)
* Revision change in one or more subcores
2020.3:
* Version 2.0 (Rev. 25)
* Revision change in one or more subcores
2020.2.2:
* Version 2.0 (Rev. 24)
* No changes
2020.2.1:
* Version 2.0 (Rev. 24)
* No changes
2020.2:
* Version 2.0 (Rev. 24)
* General: No Functional changes
* Revision change in one or more subcores
2020.1.1:
* Version 2.0 (Rev. 23)
* No changes
2020.1:
* Version 2.0 (Rev. 23)
* Revision change in one or more subcores
2019.2.2:
* Version 2.0 (Rev. 22)
* No changes
2019.2.1:
* Version 2.0 (Rev. 22)
* No changes
2019.2:
* Version 2.0 (Rev. 22)
* General: No Functional changes
* Revision change in one or more subcores
2019.1.3:
* Version 2.0 (Rev. 21)
* No changes
2019.1.2:
* Version 2.0 (Rev. 21)
* No changes
2019.1.1:
* Version 2.0 (Rev. 21)
* No changes
2019.1:
* Version 2.0 (Rev. 21)
* General: No Functional changes
* Revision change in one or more subcores
2018.3.1:
* Version 2.0 (Rev. 20)
* No changes
2018.3:
* Version 2.0 (Rev. 20)
* General: Removed MAX_FANOUT attribute
* Revision change in one or more subcores
2018.2:
* Version 2.0 (Rev. 19)
* Revision change in one or more subcores
2018.1:
* Version 2.0 (Rev. 18)
* General: Updates to example design
* Revision change in one or more subcores
2017.4:
* Version 2.0 (Rev. 17)
* Revision change in one or more subcores
2017.3:
* Version 2.0 (Rev. 16)
* General: Updated the IP to report default value of registers
* Revision change in one or more subcores
2017.2:
* Version 2.0 (Rev. 15)
* Revision change in one or more subcores
2017.1:
* Version 2.0 (Rev. 14)
* Feature Enhancement: Register read option enabled for output data registers
* Other: SW access added to GPIO output data registers.
* Other: Updated example design subcore version. No Functional changes
* Revision change in one or more subcores
2016.4:
* Version 2.0 (Rev. 13)
* Revision change in one or more subcores
2016.3:
* Version 2.0 (Rev. 12)
* Bug Fix: Board flow related fix
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
* Revision change in one or more subcores
2016.2:
* Version 2.0 (Rev. 11)
* Revision change in one or more subcores
2016.1:
* Version 2.0 (Rev. 10)
* Updated example design subcore version.No functional changes
* Revision change in one or more subcores
2015.4.2:
* Version 2.0 (Rev. 9)
* No changes
2015.4.1:
* Version 2.0 (Rev. 9)
* No changes
2015.4:
* Version 2.0 (Rev. 9)
* Revision change in one or more subcores
2015.3:
* Version 2.0 (Rev. 8)
* IP update to support latest board flow, no functional or interface changes
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* Revision change in one or more subcores
2015.2.1:
* Version 2.0 (Rev. 7)
* No changes
2015.2:
* Version 2.0 (Rev. 7)
* No changes
2015.1:
* Version 2.0 (Rev. 7)
* Updated IP to get Bus Width from common utilities for Board.
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 2.0 (Rev. 6)
* No changes
2014.4:
* Version 2.0 (Rev. 6)
* No changes
2014.3:
* Version 2.0 (Rev. 6)
* Example design updated to have ATG mask change dynamically based on GPIO widths
* AXI GPIO uses new libraries and axi_lite_ipif subcores
* Updating core to use utils.tcl needed for board flow from common location
* Disabling customization of the appropriate GPIO if board interface has been used
2014.2:
* Version 2.0 (Rev. 5)
* Example design XDC update for timing DRC
* Updated board flow commands in sync with internal flow updates, no functional changes.
2014.1:
* Version 2.0 (Rev. 4)
* Internal device family name change, no functional changes
* Virtex UltraScale Pre-Production support.
2013.4:
* Version 2.0 (Rev. 3)
* Board interface connection for GPIO2 enabled by default
* Updated Example design to use Clocking Wizard to generate clocks
* Kintex UltraScale Pre-Production support
2013.3:
* Version 2.0 (Rev. 2)
* Added example design and demonstration testbench
* Reduced warnings in synthesis and simulation
* Enhanced support for IP Integrator
* Added support for Cadence IES and Synopsys VCS simulators
* Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
* Improved GUI speed and responsiveness, no functional changes
2013.2:
* Version 2.0 (Rev. 1)
* Enable support for future devices
* There have been no functional or interface changes to this IP.
2013.1:
* Version 2.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2012 - 2021 Xilinx, Inc. All rights reserved.
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PART OF THIS FILE AT ALL TIMES.
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
Bus2IP_RdCE : in std_logic_vector (0 to 3);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
--constant GPIO_G_W : integer = C_GPIO_WIDTH when (C_GPIO_WIDTH > C_GPIO2_WIDTH) else C_GPIO2_;
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
signal reg1, reg2 : std_logic_vector (0 to C_DW-1);
signal reg3, reg4 : std_logic_vector (0 to C_DW-1);
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
ALLOUT_ND : if (C_ALL_OUTPUTS = 1) generate
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
reg1(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i);
reg1(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
reg2 <= x"FFFFFFFF";
reg3 <= x"00000000";
reg4 <= x"FFFFFFFF";
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
end generate ALLOUT_ND;
ALLIN1_ND : if (C_ALL_INPUTS = 1) generate
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
reg1(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
reg1(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
reg2 <= x"FFFFFFFF";
reg3 <= x"00000000";
reg4 <= x"FFFFFFFF";
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
end generate ALLIN1_ND;
ALLOUT0_ND : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
reg1(i-C_GPIO_WIDTH+C_DW) <= '0';
reg2(i-C_GPIO_WIDTH+C_DW) <= '0';
else
if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0')then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i);
reg1(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i);
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
reg2(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
reg1(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
--GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
reg3 <= x"00000000";
reg4 <= x"FFFFFFFF";
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
reg2(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
end generate ALLOUT0_ND;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
-- GPIO_DBus <= GPIO_DBus_i;
with bus2ip_rdce(0 to 3) select
GPIO_DBus(0 to 31) <= reg1 when "1000",
reg2 when "0100",
reg3 when "0010",
reg4 when "0001",
(others=>'0') when others;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select,gpio_Data_Out) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
--Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
ALLOUT0_ND_G0 : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
reg1(i-C_GPIO_WIDTH+C_DW) <= '0';
reg2(i-C_GPIO_WIDTH+C_DW) <= '0';
else
if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0') then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i);
reg1(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i);
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
reg2(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
reg1(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
--GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
reg2(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
end generate ALLOUT0_ND_G0;
ALLIN0_ND_G0 : if (C_ALL_INPUTS = 1) generate
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
reg1(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
reg1(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
reg2 <= (others => '1');
end generate ALLIN0_ND_G0;
ALLOUT0_ND_G1 : if (C_ALL_OUTPUTS = 1) generate
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
reg1(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i);
reg1(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
reg2 <= (others => '1');
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
reg1(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
end generate ALLOUT0_ND_G1;
ALLIN0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 1) generate
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
reg3(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
reg3(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
--GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
reg4 <= (others => '1');
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
reg3(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
end generate ALLIN0_ND_G2;
ALLOUT0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 0) generate
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
reg3(i-C_GPIO2_WIDTH+C_DW) <= '0';
reg4(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
if (gpio2_OE(i) = '0' and gpio_OE_Select(1) = '0') then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i);
reg3(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i);
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
reg4(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
reg3(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
-- GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i) when (gpio2_OE(i) = '1') else Read_Reg2_In(i);
--GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
reg3(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
reg4(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
end generate ALLOUT0_ND_G2;
ALLOUT1_ND_G2 : if (C_ALL_OUTPUTS_2 = 1) generate
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
reg3(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i);
reg3(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
reg4 <= (others => '1');
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
reg3(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
end generate ALLOUT1_ND_G2;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
-- GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
-- (gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
-- else GPIO2_DBus_i;
with bus2ip_rdce(0 to 3) select
GPIO_DBus(0 to 31) <= reg1 when "1000",
reg2 when "0100",
reg3 when "0010",
reg4 when "0001",
(others=>'0') when others;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
--if (C_ALL_OUTPUTS = '1') then
-- gpio_Data_In <= gpio_Data_Out;
-- else
gpio_Data_In <= gpio_io_i_d2;
-- end if;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
-- if (C_ALL_OUTPUTS = '1') then
-- gpio2_Data_In <= gpio2_Data_Out;
-- else
gpio2_Data_In <= gpio2_io_i_d2;
-- end if;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select,gpio_Data_Out,gpio2_Data_Out) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
--Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
--Read_Reg2_In <= gpio2_Data_In;
--Read_Reg2_In<= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_27 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_27 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_4;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_27 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_27;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_27.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_ALL_OUTPUTS => C_ALL_OUTPUTS,
C_ALL_INPUTS => C_ALL_INPUTS,
C_ALL_INPUTS_2 => C_ALL_INPUTS_2,
C_ALL_OUTPUTS_2 => C_ALL_OUTPUTS_2,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
Bus2IP_RdCE => bus2ip_rdce (0 to 3),
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch1_full : for i in C_GPIO_WIDTH to C_S_AXI_DATA_WIDTH-1 generate
Bus2IP1_Data_i(i) <= '0' ;
end generate BUS_CONV_ch1_full;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
BUS_CONV_ch2_full : for i in C_GPIO2_WIDTH to C_S_AXI_DATA_WIDTH-1 generate
Bus2IP2_Data_i(i) <= '0';
end generate BUS_CONV_ch2_full;
end architecture imp;
|
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
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-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
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-- ** covered by a separate agreement. **
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-- ** "as-is" solely for use in developing programs and **
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-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
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-- ** **
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-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default_i : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function log2(x : natural) return integer;
function clog2(x : positive) return natural;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default_i : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default_i;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the user抯 sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-- type bo2sl_type is array (boolean) of std_logic;
-- constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end imp;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type:= ( ( others => ( others => '0' ) ) );
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_4.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in natural range 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_4.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v2.0
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
signal start2 : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rd_done1,wr_done1 : std_logic;
--signal rd_done2,wr_done2 : std_logic;
signal wrack_1,rdack_1 : std_logic;
--signal wrack_2,rdack_2 : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
signal is_read, is_write : std_logic;
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
--bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
-- else
-- '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
--bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
-- when (S_AXI_ARVALID='1')
-- else
-- ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
--start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
-- when (state = SM_IDLE)
-- else
-- '0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or (timeout and is_read);
wr_done <= IP2Bus_WrAck or (timeout and is_write);
--wr_done1 <= (not (wrack_1) and IP2Bus_WrAck) or timeout;
--rd_done1 <= (not (rdack_1) and IP2Bus_RdAck) or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v3_0_4.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start2,
Bus_RNW => bus2ip_rnw_i, --S_AXI_ARVALID,
Bus_RNW_Erly => bus2ip_rnw_i, --S_AXI_ARVALID,
CS_CE_ld_enable => start2,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start2,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
REGISTERING_RESET_P2 : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
-- wrack_1 <= '0';
-- rdack_1 <= '0';
-- wrack_2 <= '0';
-- rdack_2 <= '0';
-- wr_done2 <= '0';
-- rd_done2 <= '0';
bus2ip_rnw_i <= '0';
bus2ip_addr_i <= (others => '0');
start2 <= '0';
else
-- wrack_1 <= IP2Bus_WrAck;
-- rdack_1 <= IP2Bus_RdAck;
-- wrack_2 <= wrack_1;
-- rdack_2 <= rdack_1;
-- wr_done2 <= wr_done1;
-- rd_done2 <= rd_done1;
if (state = SM_IDLE and S_AXI_ARVALID='1') then
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '1';
start2 <= '1';
elsif (state = SM_IDLE and (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1')) then
bus2ip_addr_i <= ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
bus2ip_rnw_i <= '0';
start2 <= '1';
else
bus2ip_rnw_i <= bus2ip_rnw_i;
bus2ip_addr_i <= bus2ip_addr_i;
start2 <= '0';
end if;
end if;
end if;
end process REGISTERING_RESET_P2;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
is_read <= '0';
is_write <= '0';
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
is_read <='1';
is_write <= '0';
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
is_read <='0';
is_write <= '1';
else
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
is_read <='0';
is_write <= '0';
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= '1' when (dpto_cnt = C_DPHASE_TIMEOUT) else '0';
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_lite_ipif.vhd
-- Version: v2.0
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of axi_lite_ipif is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity axi_lite_ipif_v3_0_4.slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use proc_common_v4_0 library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v3_1
-- ~~~~~~
-- - Modified to used proc_common_v4_0 library
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of Interrupt Control to v3.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
bus2ip_clk : In std_logic;
bus2ip_reset : In std_logic;
bus2ip_data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
bus2ip_be : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
interrupt_rdce : In std_logic_vector(0 to C_NUM_CE-1);
interrupt_wrce : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
ipif_reg_interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
ipif_lvl_interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
ip2bus_intrevent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
intr2bus_devintr : Out std_logic;
-- Status Reply Outputs to the Bus
intr2bus_dbus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
intr2bus_wrack : Out std_logic;
intr2bus_rdack : Out std_logic;
intr2bus_error : Out std_logic;
intr2bus_retry : Out std_logic;
intr2bus_toutsup : Out std_logic
);
end interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
|
--Generic Help
--C_CDC_TYPE : Defines the type of CDC needed
-- 0 means pulse synchronizer. Used to transfer one clock pulse
-- from prmry domain to scndry domain.
-- 1 means level synchronizer. Used to transfer level signal.
-- 2 means level synchronizer with ack. Used to transfer level
-- signal. Input signal should change only when prmry_ack is detected
--
--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
-- Set to 0 when incoming signal is purely floped signal.
--
--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
-- it might be needed.
-- 0 means reset not needed for sync flops
-- 1 means reset needed for sync flops. i
-- In this case prmry_resetn should be in prmry clock,
-- while scndry_reset should be in scndry clock.
--
--C_SINGLE_BIT : CDC should normally be done for single bit signals only.
-- However, based on design buses can also be CDC'ed.
-- 0 means it is a bus. In this case input be connected to prmry_vect_in.
-- Output is on scndry_vect_out.
-- 1 means it is a single bit. In this case input be connected to prmry_in.
-- Output is on scndry_out.
--
--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
--
--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
-- Value of 0, 1 is allowed only for level CDC.
-- Min value for Pulse CDC is 2
--
--Whenever this file is used following XDC constraint has to be added
-- set_false_path -to [get_pins -hier *cdc_to*/D]
--IO Ports
--
-- prmry_aclk : clock of originating domain (source domain)
-- prmry_resetn : sync reset of originating clock domain (source domain)
-- prmry_in : input signal bit. This should be a pure flop output without
-- any combi logic. This is source.
-- prmry_vect_in : bus signal. From Source domain.
-- prmry_ack : Ack signal, valid for one clock period, in prmry_aclk domain.
-- Used only when C_CDC_TYPE = 2
-- scndry_aclk : destination clock.
-- scndry_resetn : sync reset of destination domain
-- scndry_out : sync'ed output in destination domain. Single bit.
-- scndry_vect_out : sync'ed output in destination domain. bus.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.FDR;
entity cdc_sync is
generic (
C_CDC_TYPE : integer range 0 to 2 := 1 ;
-- 0 is pulse synch
-- 1 is level synch
-- 2 is ack based level sync
C_RESET_STATE : integer range 0 to 1 := 0 ;
-- 0 is reset not needed
-- 1 is reset needed
C_SINGLE_BIT : integer range 0 to 1 := 1 ;
-- 0 is bus input
-- 1 is single bit input
C_FLOP_INPUT : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer range 0 to 64 := 32 ;
C_MTBF_STAGES : integer range 0 to 6 := 2
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
prmry_in : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_ack : out std_logic ;
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Primary to Secondary Clock Crossing --
scndry_out : out std_logic ; --
--
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end cdc_sync;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of cdc_sync is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
--attribute DONT_TOUCH : STRING;
--attribute KEEP : STRING;
--attribute DONT_TOUCH of implementation : architecture is "yes";
signal prmry_resetn1 : std_logic := '0';
signal scndry_resetn1 : std_logic := '0';
signal prmry_reset2 : std_logic := '0';
signal scndry_reset2 : std_logic := '0';
--attribute KEEP of prmry_resetn1 : signal is "true";
--attribute KEEP of scndry_resetn1 : signal is "true";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
HAS_RESET : if C_RESET_STATE = 1 generate
begin
prmry_resetn1 <= prmry_resetn;
scndry_resetn1 <= scndry_resetn;
end generate HAS_RESET;
HAS_NO_RESET : if C_RESET_STATE = 0 generate
begin
prmry_resetn1 <= '1';
scndry_resetn1 <= '1';
end generate HAS_NO_RESET;
prmry_reset2 <= not prmry_resetn1;
scndry_reset2 <= not scndry_resetn1;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_out_d1_cdc_to : signal is "true";
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_d5 : std_logic := '0';
signal s_out_d6 : std_logic := '0';
signal s_out_d7 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
signal srst_d1 : std_logic := '0';
signal srst_d2 : std_logic := '0';
signal srst_d3 : std_logic := '0';
signal srst_d4 : std_logic := '0';
signal srst_d5 : std_logic := '0';
signal srst_d6 : std_logic := '0';
signal srst_d7 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF REG_P_IN2_cdc_to : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d2 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d3 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d4 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d5 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d6 : label IS "true";
ATTRIBUTE async_reg OF P_IN_CROSS2SCNDRY_s_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
--------------------------------------REG_P_IN : process(prmry_aclk)
-------------------------------------- begin
-------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
-------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
-------------------------------------- p_in_d1_cdc_from <= '0';
-------------------------------------- else
-------------------------------------- p_in_d1_cdc_from <= prmry_in_xored;
-------------------------------------- end if;
-------------------------------------- end if;
-------------------------------------- end process REG_P_IN;
REG_P_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in_xored,
R => prmry_reset2
);
REG_P_IN2_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d1_cdc_to,
C => scndry_aclk,
D => p_in_d1_cdc_from,
R => scndry_reset2
);
------------------------------------ P_IN_CROSS2SCNDRY : process(scndry_aclk)
------------------------------------ begin
------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------ s_out_d2 <= '0';
------------------------------------ s_out_d3 <= '0';
------------------------------------ s_out_d4 <= '0';
------------------------------------ s_out_d5 <= '0';
------------------------------------ s_out_d6 <= '0';
------------------------------------ s_out_d7 <= '0';
------------------------------------ scndry_out <= '0';
------------------------------------ else
------------------------------------ s_out_d2 <= s_out_d1_cdc_to;
------------------------------------ s_out_d3 <= s_out_d2;
------------------------------------ s_out_d4 <= s_out_d3;
------------------------------------ s_out_d5 <= s_out_d4;
------------------------------------ s_out_d6 <= s_out_d5;
------------------------------------ s_out_d7 <= s_out_d6;
------------------------------------ scndry_out <= s_out_re;
------------------------------------ end if;
------------------------------------ end if;
------------------------------------ end process P_IN_CROSS2SCNDRY;
P_IN_CROSS2SCNDRY_s_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d2,
C => scndry_aclk,
D => s_out_d1_cdc_to,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d3,
C => scndry_aclk,
D => s_out_d2,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d4,
C => scndry_aclk,
D => s_out_d3,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d5,
C => scndry_aclk,
D => s_out_d4,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d6,
C => scndry_aclk,
D => s_out_d5,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_s_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => s_out_d7,
C => scndry_aclk,
D => s_out_d6,
R => scndry_reset2
);
P_IN_CROSS2SCNDRY_scndry_out : component FDR
generic map(INIT => '0'
)port map (
Q => scndry_out,
C => scndry_aclk,
D => s_out_re,
R => scndry_reset2
);
s_rst_d1 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d1,
C => scndry_aclk,
D => '1',
R => scndry_reset2
);
s_rst_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d2,
C => scndry_aclk,
D => srst_d1,
R => scndry_reset2
);
s_rst_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d3,
C => scndry_aclk,
D => srst_d2,
R => scndry_reset2
);
s_rst_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d4,
C => scndry_aclk,
D => srst_d3,
R => scndry_reset2
);
s_rst_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d5,
C => scndry_aclk,
D => srst_d4,
R => scndry_reset2
);
s_rst_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d6,
C => scndry_aclk,
D => srst_d5,
R => scndry_reset2
);
s_rst_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => srst_d7,
C => scndry_aclk,
D => srst_d6,
R => scndry_reset2
);
MTBF_2 : if C_MTBF_STAGES = 2 generate
begin
s_out_re <= (s_out_d2 xor s_out_d3) and (srst_d3);
end generate MTBF_2;
MTBF_3 : if C_MTBF_STAGES = 3 generate
begin
s_out_re <= (s_out_d3 xor s_out_d4) and (srst_d4);
end generate MTBF_3;
MTBF_4 : if C_MTBF_STAGES = 4 generate
begin
s_out_re <= (s_out_d4 xor s_out_d5) and (srst_d5);
end generate MTBF_4;
MTBF_5 : if C_MTBF_STAGES = 5 generate
begin
s_out_re <= (s_out_d5 xor s_out_d6) and (srst_d6);
end generate MTBF_5;
MTBF_6 : if C_MTBF_STAGES = 6 generate
begin
s_out_re <= (s_out_d6 xor s_out_d7) and (srst_d7);
end generate MTBF_6;
-- Feed secondary pulse out
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
begin
-- Primary to Secondary
SINGLE_BIT : if C_SINGLE_BIT = 1 generate
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
prmry_ack <= '0';
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
---------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
---------------------------------- begin
---------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
---------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
---------------------------------- p_level_in_d1_cdc_from <= '0';
---------------------------------- else
---------------------------------- p_level_in_d1_cdc_from <= prmry_in;
---------------------------------- end if;
---------------------------------- end if;
---------------------------------- end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------ begin
------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------ s_level_out_d2 <= '0';
------------------------------ s_level_out_d3 <= '0';
------------------------------ s_level_out_d4 <= '0';
------------------------------ s_level_out_d5 <= '0';
------------------------------ s_level_out_d6 <= '0';
------------------------------ else
------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------ end if;
------------------------------ end if;
------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_out <= s_level_out_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_out <= s_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out <= s_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out <= s_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out <= s_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out <= s_level_out_d6;
end generate MTBF_L6;
end generate SINGLE_BIT;
MULTI_BIT : if C_SINGLE_BIT = 0 generate
signal p_level_in_bus_int : std_logic_vector (C_VECTOR_WIDTH - 1 downto 0);
signal p_level_in_bus_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
--attribute DONT_TOUCH of s_level_out_bus_d1_cdc_to : signal is "true";
signal s_level_out_bus_d1_cdc_tig : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d2 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d3 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d4 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d5 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
signal s_level_out_bus_d6 : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d2 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d3 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d4 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d5 : SIGNAL IS "true";
-----------------ATTRIBUTE async_reg OF s_level_out_bus_d6 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_out <= '0';
prmry_ack <= '0';
INPUT_FLOP_BUS : if C_FLOP_INPUT = 1 generate
begin
----------------------------------- REG_PLEVEL_IN : process(prmry_aclk)
----------------------------------- begin
----------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
----------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------- p_level_in_bus_d1_cdc_from <= (others => '0');
----------------------------------- else
----------------------------------- p_level_in_bus_d1_cdc_from <= prmry_vect_in;
----------------------------------- end if;
----------------------------------- end if;
----------------------------------- end process REG_PLEVEL_IN;
FOR_REG_PLEVEL_IN: for i in 0 to (C_VECTOR_WIDTH-1) generate
begin
REG_PLEVEL_IN_p_level_in_bus_d1_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_bus_d1_cdc_from (i),
C => prmry_aclk,
D => prmry_vect_in (i),
R => prmry_reset2
);
end generate FOR_REG_PLEVEL_IN;
p_level_in_bus_int <= p_level_in_bus_d1_cdc_from;
end generate INPUT_FLOP_BUS;
NO_INPUT_FLOP_BUS : if C_FLOP_INPUT = 0 generate
begin
p_level_in_bus_int <= prmry_vect_in;
end generate NO_INPUT_FLOP_BUS;
FOR_IN_cdc_to: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d1_cdc_to (i),
C => scndry_aclk,
D => p_level_in_bus_int (i),
R => scndry_reset2
);
end generate FOR_IN_cdc_to;
----------------------------------------- CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
----------------------------------------- begin
----------------------------------------- if(scndry_aclk'EVENT and scndry_aclk ='1')then
----------------------------------------- if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
----------------------------------------- s_level_out_bus_d2 <= (others => '0');
----------------------------------------- s_level_out_bus_d3 <= (others => '0');
----------------------------------------- s_level_out_bus_d4 <= (others => '0');
----------------------------------------- s_level_out_bus_d5 <= (others => '0');
----------------------------------------- s_level_out_bus_d6 <= (others => '0');
----------------------------------------- else
----------------------------------------- s_level_out_bus_d2 <= s_level_out_bus_d1_cdc_to;
----------------------------------------- s_level_out_bus_d3 <= s_level_out_bus_d2;
----------------------------------------- s_level_out_bus_d4 <= s_level_out_bus_d3;
----------------------------------------- s_level_out_bus_d5 <= s_level_out_bus_d4;
----------------------------------------- s_level_out_bus_d6 <= s_level_out_bus_d5;
----------------------------------------- end if;
----------------------------------------- end if;
----------------------------------------- end process CROSS_PLEVEL_IN2SCNDRY;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d2 (i),
C => scndry_aclk,
D => s_level_out_bus_d1_cdc_to (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d3 (i),
C => scndry_aclk,
D => s_level_out_bus_d2 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d4 (i),
C => scndry_aclk,
D => s_level_out_bus_d3 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d5 (i),
C => scndry_aclk,
D => s_level_out_bus_d4 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5;
FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6: for i in 0 to (C_VECTOR_WIDTH-1) generate
ATTRIBUTE async_reg OF CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : label IS "true";
begin
CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_bus_d6 (i),
C => scndry_aclk,
D => s_level_out_bus_d5 (i),
R => scndry_reset2
);
end generate FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6;
MTBF_L1 : if C_MTBF_STAGES = 1 generate
begin
scndry_vect_out <= s_level_out_bus_d1_cdc_to;
end generate MTBF_L1;
MTBF_L2 : if C_MTBF_STAGES = 2 generate
begin
scndry_vect_out <= s_level_out_bus_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_vect_out <= s_level_out_bus_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_vect_out <= s_level_out_bus_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_vect_out <= s_level_out_bus_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_vect_out <= s_level_out_bus_d6;
end generate MTBF_L6;
end generate MULTI_BIT;
end generate GENERATE_LEVEL_P_S_CDC;
GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal p_level_in_int : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of s_level_out_d1_cdc_to : signal is "true";
signal s_level_out_d2 : std_logic := '0';
signal s_level_out_d3 : std_logic := '0';
signal s_level_out_d4 : std_logic := '0';
signal s_level_out_d5 : std_logic := '0';
signal s_level_out_d6 : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
--attribute DONT_TOUCH of p_level_out_d1_cdc_to : signal is "true";
signal p_level_out_d2 : std_logic := '0';
signal p_level_out_d3 : std_logic := '0';
signal p_level_out_d4 : std_logic := '0';
signal p_level_out_d5 : std_logic := '0';
signal p_level_out_d6 : std_logic := '0';
signal p_level_out_d7 : std_logic := '0';
signal scndry_out_int : std_logic := '0';
signal prmry_pulse_ack : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : label IS "true";
ATTRIBUTE async_reg OF CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : label IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
scndry_vect_out <= (others => '0');
INPUT_FLOP : if C_FLOP_INPUT = 1 generate
begin
------------------------------------------ REG_PLEVEL_IN : process(prmry_aclk)
------------------------------------------ begin
------------------------------------------ if(prmry_aclk'EVENT and prmry_aclk ='1')then
------------------------------------------ if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------ p_level_in_d1_cdc_from <= '0';
------------------------------------------ else
------------------------------------------ p_level_in_d1_cdc_from <= prmry_in;
------------------------------------------ end if;
------------------------------------------ end if;
------------------------------------------ end process REG_PLEVEL_IN;
REG_PLEVEL_IN_cdc_from : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_in_d1_cdc_from,
C => prmry_aclk,
D => prmry_in,
R => prmry_reset2
);
p_level_in_int <= p_level_in_d1_cdc_from;
end generate INPUT_FLOP;
NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
begin
p_level_in_int <= prmry_in;
end generate NO_INPUT_FLOP;
CROSS3_PLEVEL_IN2SCNDRY_IN_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d1_cdc_to,
C => scndry_aclk,
D => p_level_in_int,
R => scndry_reset2
);
------------------------------------------------ CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
------------------------------------------------ begin
------------------------------------------------ if(scndry_aclk'EVENT and scndry_aclk ='1')then
------------------------------------------------ if(scndry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
------------------------------------------------ s_level_out_d2 <= '0';
------------------------------------------------ s_level_out_d3 <= '0';
------------------------------------------------ s_level_out_d4 <= '0';
------------------------------------------------ s_level_out_d5 <= '0';
------------------------------------------------ s_level_out_d6 <= '0';
------------------------------------------------ else
------------------------------------------------ s_level_out_d2 <= s_level_out_d1_cdc_to;
------------------------------------------------ s_level_out_d3 <= s_level_out_d2;
------------------------------------------------ s_level_out_d4 <= s_level_out_d3;
------------------------------------------------ s_level_out_d5 <= s_level_out_d4;
------------------------------------------------ s_level_out_d6 <= s_level_out_d5;
------------------------------------------------ end if;
------------------------------------------------ end if;
------------------------------------------------ end process CROSS_PLEVEL_IN2SCNDRY;
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d2,
C => scndry_aclk,
D => s_level_out_d1_cdc_to,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d3,
C => scndry_aclk,
D => s_level_out_d2,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d4,
C => scndry_aclk,
D => s_level_out_d3,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d5,
C => scndry_aclk,
D => s_level_out_d4,
R => scndry_reset2
);
CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => s_level_out_d6,
C => scndry_aclk,
D => s_level_out_d5,
R => scndry_reset2
);
--------------------------------------------------- CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
--------------------------------------------------- begin
--------------------------------------------------- if(prmry_aclk'EVENT and prmry_aclk ='1')then
--------------------------------------------------- if(prmry_resetn1 = '0') then -- and C_RESET_STATE = 1)then
--------------------------------------------------- p_level_out_d1_cdc_to <= '0';
--------------------------------------------------- p_level_out_d2 <= '0';
--------------------------------------------------- p_level_out_d3 <= '0';
--------------------------------------------------- p_level_out_d4 <= '0';
--------------------------------------------------- p_level_out_d5 <= '0';
--------------------------------------------------- p_level_out_d6 <= '0';
--------------------------------------------------- p_level_out_d7 <= '0';
--------------------------------------------------- prmry_ack <= '0';
--------------------------------------------------- else
--------------------------------------------------- p_level_out_d1_cdc_to <= scndry_out_int;
--------------------------------------------------- p_level_out_d2 <= p_level_out_d1_cdc_to;
--------------------------------------------------- p_level_out_d3 <= p_level_out_d2;
--------------------------------------------------- p_level_out_d4 <= p_level_out_d3;
--------------------------------------------------- p_level_out_d5 <= p_level_out_d4;
--------------------------------------------------- p_level_out_d6 <= p_level_out_d5;
--------------------------------------------------- p_level_out_d7 <= p_level_out_d6;
--------------------------------------------------- prmry_ack <= prmry_pulse_ack;
--------------------------------------------------- end if;
--------------------------------------------------- end if;
--------------------------------------------------- end process CROSS_PLEVEL_SCNDRY2PRMRY;
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d1_cdc_to : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d1_cdc_to,
C => prmry_aclk,
D => scndry_out_int,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d2 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d2,
C => prmry_aclk,
D => p_level_out_d1_cdc_to,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d3 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d3,
C => prmry_aclk,
D => p_level_out_d2,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d4 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d4,
C => prmry_aclk,
D => p_level_out_d3,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d5 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d5,
C => prmry_aclk,
D => p_level_out_d4,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d6 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d6,
C => prmry_aclk,
D => p_level_out_d5,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_p_level_out_d7 : component FDR
generic map(INIT => '0'
)port map (
Q => p_level_out_d7,
C => prmry_aclk,
D => p_level_out_d6,
R => prmry_reset2
);
CROSS_PLEVEL_SCNDRY2PRMRY_prmry_ack : component FDR
generic map(INIT => '0'
)port map (
Q => prmry_ack,
C => prmry_aclk,
D => prmry_pulse_ack,
R => prmry_reset2
);
MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
begin
scndry_out_int <= s_level_out_d2;
--prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
prmry_pulse_ack <= (not p_level_out_d3) and p_level_out_d2;
end generate MTBF_L2;
MTBF_L3 : if C_MTBF_STAGES = 3 generate
begin
scndry_out_int <= s_level_out_d3;
--prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
prmry_pulse_ack <= (not p_level_out_d4) and p_level_out_d3;
end generate MTBF_L3;
MTBF_L4 : if C_MTBF_STAGES = 4 generate
begin
scndry_out_int <= s_level_out_d4;
--prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
prmry_pulse_ack <= (not p_level_out_d5) and p_level_out_d4;
end generate MTBF_L4;
MTBF_L5 : if C_MTBF_STAGES = 5 generate
begin
scndry_out_int <= s_level_out_d5;
--prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
prmry_pulse_ack <= (not p_level_out_d6) and p_level_out_d5;
end generate MTBF_L5;
MTBF_L6 : if C_MTBF_STAGES = 6 generate
begin
scndry_out_int <= s_level_out_d6;
--prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
prmry_pulse_ack <= (not p_level_out_d7) and p_level_out_d6;
end generate MTBF_L6;
scndry_out <= scndry_out_int;
end generate GENERATE_LEVEL_ACK_P_S_CDC;
end implementation;
|
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 27
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_27;
USE axi_gpio_v2_0_27.axi_gpio;
ENTITY xlnx_axi_gpio IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END xlnx_axi_gpio;
ARCHITECTURE xlnx_axi_gpio_arch OF xlnx_axi_gpio IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF xlnx_axi_gpio_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BI" &
"TS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "kintex7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 8,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i
);
END xlnx_axi_gpio_arch;
|
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 27
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_27;
USE axi_gpio_v2_0_27.axi_gpio;
ENTITY xlnx_axi_gpio IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END xlnx_axi_gpio;
ARCHITECTURE xlnx_axi_gpio_arch OF xlnx_axi_gpio IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF xlnx_axi_gpio_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF xlnx_axi_gpio_arch: ARCHITECTURE IS "axi_gpio,Vivado 2021.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF xlnx_axi_gpio_arch : ARCHITECTURE IS "xlnx_axi_gpio,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF xlnx_axi_gpio_arch: ARCHITECTURE IS "xlnx_axi_gpio,axi_gpio,{x_ipProduct=Vivado 2021.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=27,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=8,C_ALL_INPUTS=0,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BI" &
"TS_PER_BYTE 0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "kintex7",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 8,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i
);
END xlnx_axi_gpio_arch;
|
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
|
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="xlnx_axi_gpio_synth_1" LaunchDir="/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
|
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="monir" Host="ubuntu" Pid="46202" HostCore="4" HostMemory="16273612">
</Process>
</ProcessHandle>
|
# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# IP: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci
# IP: The module: 'xlnx_axi_gpio' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_gpio'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_gpio'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_gpio'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# IP: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci
# IP: The module: 'xlnx_axi_gpio' is the root of the design. Do not add the DONT_TOUCH constraint.
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_gpio'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_gpio'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
# XDC: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc
# XDC: The top module name and the constraint reference have the same name: 'xlnx_axi_gpio'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet
|
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="xlnx_axi_gpio_synth_1" LaunchPart="xc7k325tffg900-2" LaunchTime="1663647038">
<File Type="VDS-TIMING-PB" Name="xlnx_axi_gpio_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="xlnx_axi_gpio_timing_summary_synth.rpt"/>
<File Type="RDS-RDS" Name="xlnx_axi_gpio.vds"/>
<File Type="REPORTS-TCL" Name="xlnx_axi_gpio_reports.tcl"/>
<File Type="PA-TCL" Name="xlnx_axi_gpio.tcl"/>
<File Type="RDS-DCP" Name="xlnx_axi_gpio.dcp"/>
<File Type="RDS-PROPCONSTRS" Name="xlnx_axi_gpio_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="xlnx_axi_gpio_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="xlnx_axi_gpio_utilization_synth.pb"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_gpio">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_gpio"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_gpio">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_gpio"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
|
#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
vivado -log xlnx_axi_gpio.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_gpio.tcl
|
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
|
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
cmd_exists()
{
command -v "$1" >/dev/null 2>&1
}
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if cmd_exists hostname
then
ISE_HOST=$(hostname)
elif cmd_exists uname
then
ISE_HOST=$(uname -n)
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
|
version:1
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3262613061623364646534323437376539366335656364393865646637303534:506172656e742050412070726f6a656374204944:00
eof:385031591
|
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//
echo "This script was generated under a different operating system."
echo "Please update the PATH variable below, before executing this script"
exit
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64;/home/monir/Software/Vivado/2021.2/bin;";
} else {
PathVal = "/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64;/home/monir/Software/Vivado/2021.2/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
"-log xlnx_axi_gpio.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_gpio.tcl" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
|
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
set PATH=%SYSTEMROOT%\system32;%PATH%
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
*** Running vivado
with args -log xlnx_axi_gpio.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_gpio.tcl
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xlnx_axi_gpio.tcl -notrace
Command: synth_design -top xlnx_axi_gpio -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 46271
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5275 ; free virtual = 12672
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'xlnx_axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:87]
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_GPIO_WIDTH bound to: 8 - type: integer
Parameter C_GPIO2_WIDTH bound to: 8 - type: integer
Parameter C_ALL_INPUTS bound to: 0 - type: integer
Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS bound to: 0 - type: integer
Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer
Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer
Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000
Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111
Parameter C_IS_DUAL bound to: 1 - type: integer
Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000
Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111
INFO: [Synth 8-3491] module 'axi_gpio' declared at '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1265' bound to instance 'U0' of component 'axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:175]
INFO: [Synth 8-638] synthesizing module 'axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (2#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (3#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (4#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:835]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (5#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:106]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (6#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (7#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
INFO: [Synth 8-256] done synthesizing module 'xlnx_axi_gpio' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:87]
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_in in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[1] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[2] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[3] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[4] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[7] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[8] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[0] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[1] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[2] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[3] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[0] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[1] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[2] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[3] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[4] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[7] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[8] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus_RNW in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[3] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[2] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[1] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[0] in module slave_attachment is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 4732 ; free virtual = 12130
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5594 ; free virtual = 13006
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5594 ; free virtual = 13006
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5587 ; free virtual = 13003
INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5558 ; free virtual = 12965
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 96 instances were transformed.
FDR => FDRE: 96 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5558 ; free virtual = 12964
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5633 ; free virtual = 13026
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5632 ; free virtual = 13025
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5633 ; free virtual = 13026
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 0001 | 00
iSTATE | 0010 | 01
iSTATE0 | 0100 | 10
iSTATE1 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5634 ; free virtual = 13028
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
32 Bit Registers := 2
9 Bit Registers := 1
8 Bit Registers := 6
4 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 18
+---Muxes :
2 Input 9 Bit Muxes := 1
2 Input 8 Bit Muxes := 5
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 5
2 Input 2 Bit Muxes := 3
3 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 28
4 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port s_axi_wdata[31] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[30] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[29] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[28] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[27] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[26] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[25] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[24] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[23] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[22] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[21] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[20] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[19] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[18] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[17] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[16] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[15] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[14] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[13] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[12] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[11] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[10] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[9] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[8] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[3] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[2] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[1] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[0] in module axi_gpio is either unconnected or has no load
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5613 ; free virtual = 13010
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5481 ; free virtual = 12909
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5464 ; free virtual = 12893
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5458 ; free virtual = 12892
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT1 | 2|
|2 |LUT2 | 9|
|3 |LUT3 | 9|
|4 |LUT4 | 4|
|5 |LUT5 | 43|
|6 |LUT6 | 16|
|7 |FDR | 64|
|8 |FDRE | 95|
|9 |FDSE | 17|
+------+-----+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 29 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5552 ; free virtual = 12948
Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.723 ; gain = 32.016 ; free physical = 5552 ; free virtual = 12948
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2897.723 ; gain = 0.000 ; free physical = 5548 ; free virtual = 12945
INFO: [Netlist 29-17] Analyzing 64 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2897.723 ; gain = 0.000 ; free physical = 5580 ; free virtual = 12982
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 64 instances were transformed.
FDR => FDRE: 64 instances
Synth Design complete, checksum: c9e1738b
INFO: [Common 17-83] Releasing license: Synthesis
123 Infos, 71 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2897.723 ; gain = 40.027 ; free physical = 5766 ; free virtual = 13171
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_gpio, cache-ID = 71108036a61446df
INFO: [Coretcl 2-1174] Renamed 7 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_gpio_utilization_synth.rpt -pb xlnx_axi_gpio_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:11:22 2022...
|
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
if [ -z "$PATH" ]; then
PATH=/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64:/home/monir/Software/Vivado/2021.2/bin
else
PATH=/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64:/home/monir/Software/Vivado/2021.2/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
EAStep vivado -log xlnx_axi_gpio.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_gpio.tcl
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:10:41 2022
# Process ID: 46243
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1
# Command line: vivado -log xlnx_axi_gpio.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_gpio.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.vds
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 1000.000 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source xlnx_axi_gpio.tcl -notrace
|
#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.tcl"
variable category "vivado_synth"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
OPTRACE "xlnx_axi_gpio_synth_1" START { ROLLUP_AUTO }
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7k325tffg900-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.cache/wt [current_project]
set_property parent.project_path /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property board_part digilentinc.com:genesys2:part0:1.1 [current_project]
set_property ip_output_repo /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_ip -quiet /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.srcs/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xci
set_property used_in_implementation false [get_files -all /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc]
set_property used_in_implementation false [get_files -all /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
OPTRACE "Configure IP Cache" START { }
set cacheID [config_ip_cache -export -no_bom -dir /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1 -new_name xlnx_axi_gpio -ip [get_ips xlnx_axi_gpio]]
OPTRACE "Configure IP Cache" END { }
if { $cacheID == "" } {
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
synth_design -top xlnx_axi_gpio -part xc7k325tffg900-2 -mode out_of_context
OPTRACE "synth_design" END { }
OPTRACE "Write IP Cache" START { }
#---------------------------------------------------------
# Generate Checkpoint/Stub/Simulation Files For IP Cache
#---------------------------------------------------------
# disable binary constraint mode for IPCache checkpoints
set_param constraints.enableBinaryConstraints false
catch {
write_checkpoint -force -noxdef -rename_prefix xlnx_axi_gpio_ xlnx_axi_gpio.dcp
set ipCachedFiles {}
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_gpio_stub.v
lappend ipCachedFiles xlnx_axi_gpio_stub.v
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_gpio_stub.vhdl
lappend ipCachedFiles xlnx_axi_gpio_stub.vhdl
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_gpio_sim_netlist.v
lappend ipCachedFiles xlnx_axi_gpio_sim_netlist.v
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_gpio_sim_netlist.vhdl
lappend ipCachedFiles xlnx_axi_gpio_sim_netlist.vhdl
set TIME_taken [expr [clock seconds] - $TIME_start]
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
config_ip_cache -add -dcp xlnx_axi_gpio.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips xlnx_axi_gpio]
}
OPTRACE "Write IP Cache" END { }
}
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}
rename_ref -prefix_all xlnx_axi_gpio_
OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef xlnx_axi_gpio.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
create_report "xlnx_axi_gpio_synth_1_synth_report_utilization_0" "report_utilization -file xlnx_axi_gpio_utilization_synth.rpt -pb xlnx_axi_gpio_utilization_synth.pb"
OPTRACE "synth reports" END { }
if { [catch {
file copy -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
write_verilog -force -mode synth_stub /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
} else {
if { [catch {
file copy -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
file rename -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio_stub.v /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio_stub.vhdl /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio_sim_netlist.v /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio_sim_netlist.vhdl /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
}; # end if cacheID
if {[file isdir /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.ip_user_files/ip/xlnx_axi_gpio]} {
catch {
file copy -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_stub.v /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.ip_user_files/ip/xlnx_axi_gpio
}
}
if {[file isdir /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.ip_user_files/ip/xlnx_axi_gpio]} {
catch {
file copy -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_stub.vhdl /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.ip_user_files/ip/xlnx_axi_gpio
}
}
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "xlnx_axi_gpio_synth_1" END { }
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:10:41 2022
# Process ID: 46243
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1
# Command line: vivado -log xlnx_axi_gpio.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_gpio.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.vds
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 1000.000 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source xlnx_axi_gpio.tcl -notrace
Command: synth_design -top xlnx_axi_gpio -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 46271
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5275 ; free virtual = 12672
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'xlnx_axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:87]
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_GPIO_WIDTH bound to: 8 - type: integer
Parameter C_GPIO2_WIDTH bound to: 8 - type: integer
Parameter C_ALL_INPUTS bound to: 0 - type: integer
Parameter C_ALL_INPUTS_2 bound to: 1 - type: integer
Parameter C_ALL_OUTPUTS bound to: 0 - type: integer
Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer
Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer
Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000
Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111
Parameter C_IS_DUAL bound to: 1 - type: integer
Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000
Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111
INFO: [Synth 8-3491] module 'axi_gpio' declared at '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1265' bound to instance 'U0' of component 'axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:175]
INFO: [Synth 8-638] synthesizing module 'axi_gpio' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-638] synthesizing module 'address_decoder' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-638] synthesizing module 'pselect_f' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (2#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (3#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (4#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:835]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:736]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:772]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:804]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:821]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:837]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (5#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/lib_cdc_v1_0_rfs.vhd:106]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[0].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[1].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[2].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[3].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[4].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[5].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[6].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLOUT0_ND_G0.READ_REG_GEN[7].GPIO_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
WARNING: [Synth 8-6014] Unused sequential element Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].GPIO2_DBus_i_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:719]
INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (6#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (7#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
INFO: [Synth 8-256] done synthesizing module 'xlnx_axi_gpio' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/synth/xlnx_axi_gpio.vhd:87]
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_in in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[1] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[2] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[3] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[4] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[7] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port ABus_Reg[8] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[0] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[1] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[2] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port BE_Reg[3] in module GPIO_Core is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[0] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[1] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[2] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[3] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[4] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[7] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Address_In_Erly[8] in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus_RNW in module address_decoder is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[3] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[2] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[1] in module slave_attachment is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WSTRB[0] in module slave_attachment is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 4732 ; free virtual = 12130
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5594 ; free virtual = 13006
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5594 ; free virtual = 13006
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2865.699 ; gain = 0.000 ; free physical = 5587 ; free virtual = 13003
INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_ooc.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio_board.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.gen/sources_1/ip/xlnx_axi_gpio/xlnx_axi_gpio.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5558 ; free virtual = 12965
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 96 instances were transformed.
FDR => FDRE: 96 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5558 ; free virtual = 12964
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5633 ; free virtual = 13026
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5632 ; free virtual = 13025
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5633 ; free virtual = 13026
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE2 | 0001 | 00
iSTATE | 0010 | 01
iSTATE0 | 0100 | 10
iSTATE1 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5634 ; free virtual = 13028
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 4 Bit Adders := 1
+---Registers :
32 Bit Registers := 2
9 Bit Registers := 1
8 Bit Registers := 6
4 Bit Registers := 1
2 Bit Registers := 3
1 Bit Registers := 18
+---Muxes :
2 Input 9 Bit Muxes := 1
2 Input 8 Bit Muxes := 5
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 5
2 Input 2 Bit Muxes := 3
3 Input 2 Bit Muxes := 1
4 Input 2 Bit Muxes := 3
2 Input 1 Bit Muxes := 28
4 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port s_axi_wdata[31] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[30] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[29] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[28] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[27] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[26] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[25] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[24] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[23] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[22] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[21] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[20] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[19] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[18] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[17] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[16] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[15] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[14] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[13] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[12] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[11] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[10] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[9] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wdata[8] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[3] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[2] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[1] in module axi_gpio is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wstrb[0] in module axi_gpio is either unconnected or has no load
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS4/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Dual.INPUT_DOUBLE_REGS5/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5613 ; free virtual = 13010
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5481 ; free virtual = 12909
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5464 ; free virtual = 12893
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5458 ; free virtual = 12892
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT1 | 2|
|2 |LUT2 | 9|
|3 |LUT3 | 9|
|4 |LUT4 | 4|
|5 |LUT5 | 43|
|6 |LUT6 | 16|
|7 |FDR | 64|
|8 |FDRE | 95|
|9 |FDSE | 17|
+------+-----+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.715 ; gain = 32.016 ; free physical = 5487 ; free virtual = 12884
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 29 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2897.715 ; gain = 0.000 ; free physical = 5552 ; free virtual = 12948
Synthesis Optimization Complete : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2897.723 ; gain = 32.016 ; free physical = 5552 ; free virtual = 12948
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2897.723 ; gain = 0.000 ; free physical = 5548 ; free virtual = 12945
INFO: [Netlist 29-17] Analyzing 64 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2897.723 ; gain = 0.000 ; free physical = 5580 ; free virtual = 12982
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 64 instances were transformed.
FDR => FDRE: 64 instances
Synth Design complete, checksum: c9e1738b
INFO: [Common 17-83] Releasing license: Synthesis
123 Infos, 71 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 2897.723 ; gain = 40.027 ; free physical = 5766 ; free virtual = 13171
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_gpio, cache-ID = 71108036a61446df
INFO: [Coretcl 2-1174] Renamed 7 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_gpio/xlnx_axi_gpio.runs/xlnx_axi_gpio_synth_1/xlnx_axi_gpio.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_gpio_utilization_synth.rpt -pb xlnx_axi_gpio_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:11:22 2022...
|
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Tue Sep 20 00:11:22 2022
| Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
| Command : report_utilization -file xlnx_axi_gpio_utilization_synth.rpt -pb xlnx_axi_gpio_utilization_synth.pb
| Design : xlnx_axi_gpio
| Device : xc7k325tffg900-2
| Speed File : -2
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 73 | 0 | 0 | 203800 | 0.04 |
| LUT as Logic | 73 | 0 | 0 | 203800 | 0.04 |
| LUT as Memory | 0 | 0 | 0 | 64000 | 0.00 |
| Slice Registers | 176 | 0 | 0 | 407600 | 0.04 |
| Register as Flip Flop | 176 | 0 | 0 | 407600 | 0.04 |
| Register as Latch | 0 | 0 | 0 | 407600 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 101900 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 50950 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 17 | Yes | Set | - |
| 159 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 445 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 445 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 890 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 500 | 0.00 |
| Bonded IPADs | 0 | 0 | 0 | 50 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 32 | 0.00 |
| PHY_CONTROL | 0 | 0 | 0 | 10 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 10 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 40 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 40 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 10 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 480 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 0 | 4 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 40 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 40 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 500 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 8 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 500 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 500 | 0.00 |
+-----------------------------+------+-------+------------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 10 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 10 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 168 | 0.00 |
| BUFR | 0 | 0 | 0 | 40 | 0.00 |
+------------+------+-------+------------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
7. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 159 | Flop & Latch |
| LUT5 | 43 | LUT |
| FDSE | 17 | Flop & Latch |
| LUT6 | 16 | LUT |
| LUT3 | 9 | LUT |
| LUT2 | 9 | LUT |
| LUT4 | 4 | LUT |
| LUT1 | 2 | LUT |
+----------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
|
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IS_DUAL" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
<xilinx:boundaryDescriptionInfo>
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{"ip_boundary":{"ports":{"gpio2_io_i":[{"direction":"in","physical_left":"7","physical_right":"0","is_vector":"true"}],"gpio_io_i":[{"direction":"in","physical_left":"7","physical_right":"0","is_vector":"true"}],"gpio_io_o":[{"direction":"out","physical_left":"7","physical_right":"0","is_vector":"true"}],"gpio_io_t":[{"direction":"out","physical_left":"7","physical_right":"0","is_vector":"true"}],"s_axi_aclk":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_araddr":[{"direction":"in","physical_left":"8","physical_right":"0","is_vector":"true"}],"s_axi_aresetn":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_arready":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_arvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_awaddr":[{"direction":"in","physical_left":"8","physical_right":"0","is_vector":"true"}],"s_axi_awready":[
{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_awvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_bready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_bresp":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"s_axi_bvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_rdata":[{"direction":"out","physical_left":"31","physical_right":"0","is_vector":"true"}],"s_axi_rready":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_rresp":[{"direction":"out","physical_left":"1","physical_right":"0","is_vector":"true"}],"s_axi_rvalid":[{"direction":"out","physical_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_wdata":[{"direction":"in","physical_left":"31","physical_right":"0","is_vector":"true"}],"s_axi_wready":[{"direction":"out","physical
_left":"0","physical_right":"0","is_vector":"false"}],"s_axi_wstrb":[{"direction":"in","physical_left":"3","physical_right":"0","is_vector":"true"}],"s_axi_wvalid":[{"direction":"in","physical_left":"0","physical_right":"0","is_vector":"false"}]},"interfaces":{"GPIO":{"vlnv":"xilinx.com:interface:gpio:1.0","abstraction_type":"xilinx.com:interface:gpio_rtl:1.0","mode":"master","parameters":{"BOARD.ASSOCIATED_PARAM":[{"value":"GPIO_BOARD_INTERFACE","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"TRI_I":[{"physical_name":"gpio_io_i","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"TRI_O":[{"physical_name":"gpio_io_o","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"TRI_T":[{"physical_name":"gpio_io_t","physical_left":"7","physical_right":"0","logical_
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AXI","parameters":{"ADDR_WIDTH":[{"value":"9","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ARUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"AWUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"BUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"DATA_WIDTH":[{"value":"32","value_src":"constant","val
ue_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_BRESP":[{"value":"1","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_BURST":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_CACHE":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_LOCK":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none",
"is_ips_inferred":true,"is_static_object":false}],"HAS_PROT":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_QOS":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_REGION":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_RRESP":[{"value":"1","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"HAS_WSTRB":[{"value":"1","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ID_WIDTH":[{"value":"0","value_src"
:"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"MAX_BURST_LENGTH":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_OUTSTANDING":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_THREADS":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_OUTSTANDING":[{"value":"1","value_src":"default","value_permission":"user","resolve
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one","is_ips_inferred":true,"is_static_object":false}],"RUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SUPPORTS_NARROW_BURST":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"WUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"WUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"ARADDR":[{"physical_name":"s_axi_araddr","physical_left":"8","physical_right":"0","logical_left":"8","logical_right":"0","port_maps_used":"none"}],"ARREADY":[{"physical_name
":"s_axi_arready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARVALID":[{"physical_name":"s_axi_arvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWADDR":[{"physical_name":"s_axi_awaddr","physical_left":"8","physical_right":"0","logical_left":"8","logical_right":"0","port_maps_used":"none"}],"AWREADY":[{"physical_name":"s_axi_awready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWVALID":[{"physical_name":"s_axi_awvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BREADY":[{"physical_name":"s_axi_bready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BRESP":[{"physical_name":"s_axi_bresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_map
s_used":"none"}],"BVALID":[{"physical_name":"s_axi_bvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RDATA":[{"physical_name":"s_axi_rdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"RREADY":[{"physical_name":"s_axi_rready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RRESP":[{"physical_name":"s_axi_rresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"RVALID":[{"physical_name":"s_axi_rvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WDATA":[{"physical_name":"s_axi_wdata","physical_left":"31","physical_right":"0","logical_left":"31","logical_right":"0","port_maps_used":"none"}],"WREADY":[{"physical_name":"s_axi_wready","physical_left":"0","physical_right":"0","logical_left
":"0","logical_right":"0","port_maps_used":"none"}],"WSTRB":[{"physical_name":"s_axi_wstrb","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"WVALID":[{"physical_name":"s_axi_wvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"S_AXI_ACLK":{"vlnv":"xilinx.com:signal:clock:1.0","abstraction_type":"xilinx.com:signal:clock_rtl:1.0","mode":"slave","parameters":{"ASSOCIATED_BUSIF":[{"value":"S_AXI","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}],"ASSOCIATED_PORT":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"ASSOCIATED_RESET":[{"value":"s_axi_aresetn","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"str
ing","usage":"all","is_ips_inferred":false,"is_static_object":true}],"CLK_DOMAIN":[{"value":"","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_HZ":[{"value":"100000000","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"FREQ_TOLERANCE_HZ":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}]
},"port_maps":{"CLK":[{"physical_name":"s_axi_aclk","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}},"S_AXI_ARESETN":{"vlnv":"xilinx.com:signal:reset:1.0","abstraction_type":"xilinx.com:signal:reset_rtl:1.0","mode":"slave","parameters":{"INSERT_VIP":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"user","format":"long","usage":"simulation.rtl","is_ips_inferred":true,"is_static_object":false}],"POLARITY":[{"value":"ACTIVE_LOW","value_src":"constant","value_permission":"user","resolve_type":"immediate","format":"string","usage":"all","is_ips_inferred":false,"is_static_object":true}]},"port_maps":{"RST":[{"physical_name":"s_axi_aresetn","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}},"memory_maps":{"S_AXI":{"address_blocks":{"Reg":[{"base_address":"0","range":"4096","display_name":"Reg","description":"RegisterBlock","usage":"register","acces
s":"read-write"}]}}}}}"/>
</xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
|
PROJECT:=xlnx_axi_quad_spi
include ../common.mk
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:09:03 2022
# Process ID: 45744
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi
# Command line: vivado -mode batch -source tcl/run.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/vivado.log
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 2433.268 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source tcl/run.tcl
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:09:03 2022
# Process ID: 45744
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi
# Command line: vivado -mode batch -source tcl/run.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/vivado.log
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 2433.268 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source tcl/run.tcl
# set partNumber $::env(XILINX_PART)
# set boardName $::env(XILINX_BOARD)
# set ipName xlnx_axi_quad_spi
# create_project $ipName . -part $partNumber
# set_property board_part $boardName [current_project]
# create_ip -name axi_quad_spi -vendor xilinx.com -library ip -module_name $ipName
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/monir/Software/Vivado/2021.2/data/ip'.
WARNING: [IP_Flow 19-4052] Unable to find the parameter 'PROJECT_PARAM.ARCHTECTURE' for the proc 'update_PARAM_VALUE.C_S_AXI4_ID_WIDTH'.The proc 'update_PARAM_VALUE.C_S_AXI4_ID_WIDTH' will never be called.Please check and correct the proc
# set_property -dict [list CONFIG.C_USE_STARTUP {0} CONFIG.C_SCK_RATIO {4} CONFIG.C_FIFO_DEPTH {256} CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} CONFIG.C_S_AXI4_ID_WIDTH {0}] [get_ips $ipName]
# generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'xlnx_axi_quad_spi'...
# generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'xlnx_axi_quad_spi'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'xlnx_axi_quad_spi'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'xlnx_axi_quad_spi'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'xlnx_axi_quad_spi'...
# create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
# launch_run -jobs 8 ${ipName}_synth_1
[Tue Sep 20 00:09:17 2022] Launched xlnx_axi_quad_spi_synth_1...
Run output will be captured here: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/runme.log
# wait_on_run ${ipName}_synth_1
[Tue Sep 20 00:09:18 2022] Waiting for xlnx_axi_quad_spi_synth_1 to finish...
*** Running vivado
with args -log xlnx_axi_quad_spi.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_axi_quad_spi.tcl
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xlnx_axi_quad_spi.tcl -notrace
Command: synth_design -top xlnx_axi_quad_spi -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 45876
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2866.699 ; gain = 0.000 ; free physical = 4869 ; free virtual = 12202
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'xlnx_axi_quad_spi' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/synth/xlnx_axi_quad_spi.vhd:111]
Parameter Async_Clk bound to: 0 - type: integer
Parameter C_FAMILY bound to: kintex7 - type: string
Parameter C_SELECT_XPM bound to: 0 - type: integer
Parameter C_SUB_FAMILY bound to: kintex7 - type: string
Parameter C_INSTANCE bound to: axi_quad_spi_inst - type: string
Parameter C_SPI_MEM_ADDR_BITS bound to: 24 - type: integer
Parameter C_TYPE_OF_AXI4_INTERFACE bound to: 1 - type: integer
Parameter C_XIP_MODE bound to: 0 - type: integer
Parameter C_XIP_PERF_MODE bound to: 1 - type: integer
Parameter C_BYTE_LEVEL_INTERRUPT_EN bound to: 0 - type: integer
Parameter C_UC_FAMILY bound to: 0 - type: integer
Parameter C_FIFO_DEPTH bound to: 256 - type: integer
Parameter C_SCK_RATIO bound to: 4 - type: integer
Parameter C_DUAL_QUAD_MODE bound to: 0 - type: integer
Parameter C_NUM_SS_BITS bound to: 1 - type: integer
Parameter C_NUM_TRANSFER_BITS bound to: 8 - type: integer
Parameter C_NEW_SEQ_EN bound to: 1 - type: integer
Parameter C_SPI_MODE bound to: 0 - type: integer
Parameter C_USE_STARTUP bound to: 0 - type: integer
Parameter C_USE_STARTUP_EXT bound to: 0 - type: integer
Parameter C_SPI_MEMORY bound to: 1 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 7 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI4_ADDR_WIDTH bound to: 24 - type: integer
Parameter C_S_AXI4_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI4_ID_WIDTH bound to: 1 - type: integer
Parameter C_SHARED_STARTUP bound to: 0 - type: integer
Parameter C_S_AXI4_BASEADDR bound to: 32'b11111111111111111111111111111111
Parameter C_S_AXI4_HIGHADDR bound to: 32'b00000000000000000000000000000000
Parameter C_LSB_STUP bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'axi_quad_spi' declared at '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36498' bound to instance 'U0' of component 'axi_quad_spi' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/synth/xlnx_axi_quad_spi.vhd:318]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36738]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34994]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'IO0_I_REG' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:35463]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'IO1_I_REG' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:35474]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'IO2_I_REG' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:35485]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'IO3_I_REG' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:35497]
INFO: [Synth 8-638] synthesizing module 'axi_qspi_enhanced_mode' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:33966]
INFO: [Synth 8-638] synthesizing module 'qspi_address_decoder' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14202]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized0' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized1' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized2' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized3' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized3' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized4' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized4' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized5' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized5' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized6' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized6' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized7' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized7' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized8' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized8' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized9' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized9' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized10' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized10' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized11' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized11' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized12' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized12' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized13' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized13' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized14' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized14' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized15' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized15' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized16' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized16' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized17' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized17' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized18' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized18' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized19' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized19' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized20' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized20' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized21' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized21' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized22' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized22' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized23' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized23' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized24' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized24' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-638] synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized25' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_v3_2_24_pselect_f__parameterized25' (1#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:476]
INFO: [Synth 8-256] done synthesizing module 'qspi_address_decoder' (2#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14202]
WARNING: [Synth 8-6014] Unused sequential element axi_length_reg_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34263]
WARNING: [Synth 8-6014] Unused sequential element axi_size_reg_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34284]
WARNING: [Synth 8-6014] Unused sequential element axi_burst_reg_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34300]
WARNING: [Synth 8-6014] Unused sequential element last_data_cmb_w_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34314]
WARNING: [Synth 8-6014] Unused sequential element last_data_reg_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34432]
INFO: [Synth 8-3936] Found unconnected internal register 'bus2ip_addr_i_reg' and it is trimmed from '32' to '7' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34097]
INFO: [Synth 8-256] done synthesizing module 'axi_qspi_enhanced_mode' (3#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:33966]
INFO: [Synth 8-638] synthesizing module 'qspi_core_interface' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19206]
INFO: [Synth 8-638] synthesizing module 'reset_sync_module' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2426]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RESET_SYNC_AX2S_1' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2455]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RESET_SYNC_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2463]
INFO: [Synth 8-256] done synthesizing module 'reset_sync_module' (4#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2426]
INFO: [Synth 8-638] synthesizing module 'cross_clk_sync_fifo_1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14941]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CMD_ERR_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15224]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CMD_ERR_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15232]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPISEL_D1_REG_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15243]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPISEL_D1_REG_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15251]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPISEL_PULSE_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15277]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPISEL_PULSE_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15285]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPISEL_PULSE_S2AX_3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15293]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'MST_N_SLV_MODE_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15306]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'MST_N_SLV_MODE_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15314]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SLV_MODF_STRB_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15339]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SLV_MODF_STRB_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15347]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SLV_MODF_STRB_S2AX_3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15355]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'MODF_STROBE_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15380]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'MODF_STROBE_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15388]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'MODF_STROBE_S2AX_3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15396]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RX_FIFO_EMPTY_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15409]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RX_FIFO_EMPTY_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15417]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'TX_FIFO_EMPTY_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15429]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'TX_FIFO_EMPTY_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15437]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'TX_EMPT_4_SPISR_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15449]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'TX_EMPT_4_SPISR_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15457]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'TX_FIFO_FULL_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15468]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'TX_FIFO_FULL_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15476]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPIXFER_DONE_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15487]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPIXFER_DONE_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15495]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RX_FIFO_RST_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15520]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RX_FIFO_RST_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15528]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RX_FIFO_FULL_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15542]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'RX_FIFO_FULL_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15550]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SYNC_SPIXFER_DONE_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15573]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SYNC_SPIXFER_DONE_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15581]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SYNC_SPIXFER_DONE_S2AX_3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15589]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'DTR_UNDERRUN_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15599]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'DTR_UNDERRUN_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15607]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_0_LOOP_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15617]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_0_LOOP_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15625]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_1_SPE_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15636]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_1_SPE_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15644]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_2_MST_N_SLV_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15655]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_2_MST_N_SLV_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15663]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_3_CPOL_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15674]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_3_CPOL_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15682]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_4_CPHA_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15693]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_4_CPHA_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15701]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_5_TXFIFO_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15712]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_5_TXFIFO_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15720]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_6_RXFIFO_RST_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15731]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_6_RXFIFO_RST_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15739]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPICR_7_SS_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15750]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPICR_7_SS_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15758]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPICR_8_TR_INHIBIT_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15769]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPICR_8_TR_INHIBIT_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15777]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_9_LSB_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15788]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_9_LSB_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15796]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_BITS_7_8_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15812]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_BITS_7_8_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15820]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_BITS_7_8_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15812]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SPICR_BITS_7_8_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15820]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SR_3_MODF_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15833]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SR_3_MODF_AX2S_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15841]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPISSR_AX2S_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15858]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPISSR_SYNC_AXI_2_SPI_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15866]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'DRR_OVERRUN_S2AX_1_CDC' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15891]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'DRR_OVERRUN_S2AX_2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15899]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'DRR_OVERRUN_S2AX_3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:15907]
INFO: [Synth 8-256] done synthesizing module 'cross_clk_sync_fifo_1' (5#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14941]
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter FIFO_MEMORY_TYPE bound to: auto - type: string
Parameter FIFO_READ_LATENCY bound to: 0 - type: integer
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
Parameter FULL_RESET_VALUE bound to: 0 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
Parameter READ_DATA_WIDTH bound to: 8 - type: integer
Parameter READ_MODE bound to: fwft - type: string
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter USE_ADV_FEATURES bound to: 1f1f - type: string
Parameter WAKEUP_TIME bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
INFO: [Synth 8-3491] module 'xpm_fifo_async' declared at '/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2146' bound to instance 'RX_FIFO_II' of component 'xpm_fifo_async' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:21050]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2146]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn' (6#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized0' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized0' (6#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6157] synthesizing module 'xpm_memory_base' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6059] Synth Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:491]
WARNING: [Synth 8-6014] Unused sequential element gen_rd_b.gen_doutb_pipe.enb_pipe_reg[0] was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:3015]
INFO: [Synth 8-6155] done synthesizing module 'xpm_memory_base' (7#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv:57]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (8#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1884]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec' (9#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1884]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized0' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized0' (9#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_vec__parameterized0' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1884]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_vec__parameterized0' (9#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1884]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray__parameterized1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
WARNING: [Synth 8-6014] Unused sequential element dest_out_bin_ff_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:417]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray__parameterized1' (9#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284]
INFO: [Synth 8-226] default block is never used [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1206]
INFO: [Synth 8-226] default block is never used [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1273]
INFO: [Synth 8-226] default block is never used [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1295]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_reg_bit' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1906]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_reg_bit' (10#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1906]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized1' (10#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_rst' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1618]
INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_sync_rst' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059]
INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_sync_rst' (11#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1059]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_rst' (12#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1618]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized2' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized2' (12#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6157] synthesizing module 'xpm_counter_updn__parameterized3' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
INFO: [Synth 8-6155] done synthesizing module 'xpm_counter_updn__parameterized3' (12#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1858]
WARNING: [Synth 8-6014] Unused sequential element gdvld.data_valid_std_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:537]
WARNING: [Synth 8-6014] Unused sequential element gen_pf_ic_rc.gae_ic_std.ram_aempty_i_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:757]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1390]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base' (13#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async' (14#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2146]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:514]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:545]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:554]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:564]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:574]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (15#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-638] synthesizing module 'counter_f' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:669]
INFO: [Synth 8-256] done synthesizing module 'counter_f' (16#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:669]
INFO: [Synth 8-638] synthesizing module 'async_fifo_fg' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_fifo_v1_0_rfs.vhd:255]
Parameter FIFO_MEMORY_TYPE bound to: auto - type: string
Parameter FIFO_WRITE_DEPTH bound to: 256 - type: integer
Parameter RELATED_CLOCKS bound to: 0 - type: integer
Parameter WRITE_DATA_WIDTH bound to: 8 - type: integer
Parameter READ_MODE bound to: fwft - type: string
Parameter FIFO_READ_LATENCY bound to: 0 - type: integer
Parameter FULL_RESET_VALUE bound to: 1 - type: integer
Parameter USE_ADV_FEATURES bound to: 1F1F - type: string
Parameter READ_DATA_WIDTH bound to: 8 - type: integer
Parameter CDC_SYNC_STAGES bound to: 2 - type: integer
Parameter WR_DATA_COUNT_WIDTH bound to: 9 - type: integer
Parameter PROG_FULL_THRESH bound to: 10 - type: integer
Parameter RD_DATA_COUNT_WIDTH bound to: 9 - type: integer
Parameter PROG_EMPTY_THRESH bound to: 10 - type: integer
Parameter DOUT_RESET_VALUE bound to: 0 - type: string
Parameter ECC_MODE bound to: no_ecc - type: string
Parameter WAKEUP_TIME bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'xpm_fifo_async' declared at '/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2146' bound to instance 'xpm_fifo_async_inst' of component 'xpm_fifo_async' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_fifo_v1_0_rfs.vhd:1932]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_async__parameterized1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2146]
INFO: [Synth 8-6157] synthesizing module 'xpm_fifo_base__parameterized0' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-226] default block is never used [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1206]
INFO: [Synth 8-226] default block is never used [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1273]
INFO: [Synth 8-226] default block is never used [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1295]
WARNING: [Synth 8-6014] Unused sequential element gdvld.data_valid_std_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:537]
WARNING: [Synth 8-6014] Unused sequential element gen_pf_ic_rc.gae_ic_std.ram_aempty_i_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:757]
WARNING: [Synth 8-6014] Unused sequential element gen_fwft.empty_fwft_fb_reg was removed. [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:1390]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_base__parameterized0' (16#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:56]
INFO: [Synth 8-6155] done synthesizing module 'xpm_fifo_async__parameterized1' (16#1) [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv:2146]
INFO: [Synth 8-256] done synthesizing module 'async_fifo_fg' (17#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/lib_fifo_v1_0_rfs.vhd:255]
INFO: [Synth 8-638] synthesizing module 'qspi_fifo_ifmodule' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:13465]
INFO: [Synth 8-256] done synthesizing module 'qspi_fifo_ifmodule' (18#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:13465]
INFO: [Synth 8-638] synthesizing module 'qspi_occupancy_reg' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:3647]
INFO: [Synth 8-256] done synthesizing module 'qspi_occupancy_reg' (19#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:3647]
INFO: [Synth 8-638] synthesizing module 'qspi_mode_0_module' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:8775]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'MST_TRANS_INHIBIT_D1_I' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9350]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_II' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9378]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_III' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9390]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_IV' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9402]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_V' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9426]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'SPISEL_REG' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9505]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SCK_I_REG' to cell 'FD' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9588]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'SCK_O_EQ_4_FDRE_INST' to cell 'FDRE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:10833]
WARNING: [Synth 8-6014] Unused sequential element transfer_start_d2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9713]
WARNING: [Synth 8-6014] Unused sequential element transfer_start_d3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9714]
WARNING: [Synth 8-6014] Unused sequential element SPIXfer_done_int_pulse_d3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:9771]
WARNING: [Synth 8-6014] Unused sequential element SS_Asserted_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:10949]
WARNING: [Synth 8-6014] Unused sequential element SS_Asserted_1dly_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:10950]
WARNING: [Synth 8-6014] Unused sequential element MODF_strobe_int_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:10979]
INFO: [Synth 8-256] done synthesizing module 'qspi_mode_0_module' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:8775]
INFO: [Synth 8-638] synthesizing module 'qspi_cntrl_reg' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:13820]
INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_I' to cell 'FDRE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14027]
INFO: [Synth 8-113] binding component instance 'SPI_TRISTATE_CONTROL_I' to cell 'FDRE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:14027]
INFO: [Synth 8-256] done synthesizing module 'qspi_cntrl_reg' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:13820]
INFO: [Synth 8-638] synthesizing module 'qspi_status_slave_sel_reg' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2658]
INFO: [Synth 8-256] done synthesizing module 'qspi_status_slave_sel_reg' (22#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:2658]
INFO: [Synth 8-638] synthesizing module 'soft_reset' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:874]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Synth 8-113] binding component instance 'RST_FLOPS' to cell 'FDRSE' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:1005]
INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'soft_reset' (23#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:874]
INFO: [Synth 8-638] synthesizing module 'interrupt_control' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
INFO: [Synth 8-256] done synthesizing module 'interrupt_control' (24#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/interrupt_control_v3_1_vh_rfs.vhd:259]
WARNING: [Synth 8-6014] Unused sequential element ENHANCED_MD_WR_RD_ACK_GEN.Bus2IP_WrCE_d1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:20025]
WARNING: [Synth 8-6014] Unused sequential element ENHANCED_MD_WR_RD_ACK_GEN.Bus2IP_WrCE_d2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:20026]
WARNING: [Synth 8-6014] Unused sequential element ENHANCED_MD_WR_RD_ACK_GEN.Bus2IP_WrCE_d3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:20027]
WARNING: [Synth 8-6014] Unused sequential element ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:20057]
WARNING: [Synth 8-6014] Unused sequential element ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_d1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:20133]
WARNING: [Synth 8-6014] Unused sequential element ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:20135]
WARNING: [Synth 8-3848] Net cfgclk in module/entity qspi_core_interface does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19183]
WARNING: [Synth 8-3848] Net cfgmclk in module/entity qspi_core_interface does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19184]
WARNING: [Synth 8-3848] Net eos in module/entity qspi_core_interface does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19185]
WARNING: [Synth 8-3848] Net preq in module/entity qspi_core_interface does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19186]
WARNING: [Synth 8-3848] Net di in module/entity qspi_core_interface does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19187]
INFO: [Synth 8-256] done synthesizing module 'qspi_core_interface' (25#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:19206]
WARNING: [Synth 8-3848] Net s_axi_awready in module/entity axi_quad_spi_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34842]
WARNING: [Synth 8-3848] Net s_axi_wready in module/entity axi_quad_spi_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34849]
WARNING: [Synth 8-3848] Net s_axi_bresp in module/entity axi_quad_spi_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34853]
WARNING: [Synth 8-3848] Net s_axi_bvalid in module/entity axi_quad_spi_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34854]
WARNING: [Synth 8-3848] Net s_axi_arready in module/entity axi_quad_spi_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34861]
WARNING: [Synth 8-3848] Net s_axi_rdata in module/entity axi_quad_spi_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34865]
WARNING: [Synth 8-3848] Net s_axi_rresp in module/entity axi_quad_spi_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34866]
WARNING: [Synth 8-3848] Net s_axi_rvalid in module/entity axi_quad_spi_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34867]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi_top' (26#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:34994]
WARNING: [Synth 8-3848] Net io0_1_o in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36681]
WARNING: [Synth 8-3848] Net io0_1_t in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36682]
WARNING: [Synth 8-3848] Net io1_1_o in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36685]
WARNING: [Synth 8-3848] Net io1_1_t in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36686]
WARNING: [Synth 8-3848] Net io2_1_o in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36691]
WARNING: [Synth 8-3848] Net io2_1_t in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36692]
WARNING: [Synth 8-3848] Net io3_1_o in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36695]
WARNING: [Synth 8-3848] Net io3_1_t in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36696]
WARNING: [Synth 8-3848] Net ss_1_o in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36711]
WARNING: [Synth 8-3848] Net ss_1_t in module/entity axi_quad_spi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36712]
INFO: [Synth 8-256] done synthesizing module 'axi_quad_spi' (27#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/hdl/axi_quad_spi_v3_2_rfs.vhd:36738]
INFO: [Synth 8-256] done synthesizing module 'xlnx_axi_quad_spi' (28#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/synth/xlnx_axi_quad_spi.vhd:111]
WARNING: [Synth 8-7129] Port bus2ip_data[1] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[2] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[3] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[4] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[5] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[6] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[7] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[8] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[9] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[10] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[11] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[12] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[13] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[14] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[15] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[16] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_data[17] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_be[1] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_be[2] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port bus2ip_be[3] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[0] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[1] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[2] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[3] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[4] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[5] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[6] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[9] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[11] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[12] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[13] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[14] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_rdce[15] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[0] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[1] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[2] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[3] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[4] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[5] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[6] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[9] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[11] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[12] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[13] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[14] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port interrupt_wrce[15] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port ipif_reg_interrupts[0] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port ipif_reg_interrupts[1] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port ipif_lvl_interrupts[0] in module interrupt_control is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[0] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[1] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[2] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[3] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[4] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[5] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[6] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[7] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[8] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[9] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[10] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[11] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[12] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[13] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[14] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[15] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[16] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[17] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[18] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[19] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[20] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[21] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[22] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[23] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[24] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[25] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[26] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_Data[27] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_BE[0] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_BE[1] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_BE[2] in module soft_reset is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[0] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[1] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[2] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[3] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[4] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[5] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[6] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[7] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[8] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[9] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[10] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[11] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[12] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[13] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[14] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[15] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[16] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[17] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[18] in module qspi_status_slave_sel_reg is either unconnected or has no load
WARNING: [Synth 8-7129] Port Bus2IP_SPISSR_Data[19] in module qspi_status_slave_sel_reg is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2866.699 ; gain = 0.000 ; free physical = 5821 ; free virtual = 13155
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2866.699 ; gain = 0.000 ; free physical = 5826 ; free virtual = 13164
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2866.699 ; gain = 0.000 ; free physical = 5826 ; free virtual = 13164
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2866.699 ; gain = 0.000 ; free physical = 5817 ; free virtual = 13155
INFO: [Netlist 29-17] Analyzing 107 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_ooc.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_board.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_board.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xdc] for cell 'U0'
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/dont_touch.xdc]
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_clocks.xdc] for cell 'U0'
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.gen/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi_clocks.xdc] for cell 'U0'
INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst' of design 'preSynthElab_1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst' of design 'preSynthElab_1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Vivado 12-3272] Current instance is the top level cell 'U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst' of design 'preSynthElab_1' [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
WARNING: [XPM_CDC_GRAY: TCL-1000] The source and destination clocks are the same.
Instance: U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_dc_inst
This will add unnecessary latency to the design. Please check the design for the following:
1) Manually instantiated XPM_CDC modules: Xilinx recommends that you remove these modules.
2) Xilinx IP that contains XPM_CDC modules: Verify the connections to the IP to determine whether you can safely ignore this message.
[/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl:16]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_axi_quad_spi_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_axi_quad_spi_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/monir/Software/Vivado/2021.2/data/ip/xpm/xpm_fifo/tcl/xpm_fifo_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_axi_quad_spi_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_axi_quad_spi_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Project 1-1714] 14 XPM XDC files have been applied to the design.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2956.527 ; gain = 0.000 ; free physical = 5719 ; free virtual = 13049
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 107 instances were transformed.
FD => FDRE: 11 instances
FDR => FDRE: 79 instances
FDRSE => FDRSE (FDRE, LUT4, VCC): 17 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2956.527 ; gain = 0.000 ; free physical = 5719 ; free virtual = 13049
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Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5795 ; free virtual = 13124
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5794 ; free virtual = 13124
---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/dont_touch.xdc, line 9).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.rd_pntr_cdc_dc_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /\gen_cdc_pntr.wr_pntr_cdc_dc_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.rrst_wr_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst /\gnuram_async_fifo.xpm_fifo_base_inst /xpm_fifo_rst_inst/\gen_rst_ic.wrst_rd_inst . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.RX_FIFO_II . (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for U0/\NO_DUAL_QUAD_MODE.QSPI_NORMAL /\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I /\FIFO_EXISTS.TX_FIFO_II /\xpm_fifo_instance.xpm_fifo_async_inst . (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5797 ; free virtual = 13127
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'axi_full_sm_ps_reg' in module 'axi_qspi_enhanced_mode'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst'
INFO: [Synth 8-802] inferred FSM for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst'
INFO: [Synth 8-802] inferred FSM for state register 'gen_fwft.curr_fwft_state_reg' in module 'xpm_fifo_base__parameterized0'
INFO: [Synth 8-802] inferred FSM for state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' in module 'qspi_mode_0_module'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle | 00000001 | 0000
axi_rd | 00000010 | 0010
axi_single_rd | 00000100 | 0001
rd_last | 00001000 | 1010
axi_wr | 00010000 | 0100
axi_single_wr | 00100000 | 0011
wr_resp_1 | 01000000 | 0111
wr_resp_2 | 10000000 | 1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'axi_full_sm_ps_reg' using encoding 'one-hot' in module 'axi_qspi_enhanced_mode'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
WRST_IDLE | 00001 | 000
WRST_IN | 00010 | 010
WRST_OUT | 00100 | 111
WRST_EXIT | 01000 | 110
WRST_GO2IDLE | 10000 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst__xdcDup__1'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst__xdcDup__1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
RRST_IDLE | 00 | 00
RRST_IN | 01 | 10
RRST_OUT | 10 | 11
RRST_EXIT | 11 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst__xdcDup__1'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
invalid | 00 | 00
stage1_valid | 01 | 10
both_stages_valid | 10 | 11
stage2_valid | 11 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_wrst_state_reg' in module 'xpm_fifo_rst'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
WRST_IDLE | 00001 | 000
WRST_IN | 00010 | 010
WRST_OUT | 00100 | 111
WRST_EXIT | 01000 | 110
WRST_GO2IDLE | 10000 | 100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_wrst_state_reg' using encoding 'one-hot' in module 'xpm_fifo_rst'
INFO: [Synth 8-5552] Implemented safe state 'default_state' for state register 'gen_rst_ic.curr_rrst_state_reg' in module 'xpm_fifo_rst'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
RRST_IDLE | 00 | 00
RRST_IN | 01 | 10
RRST_OUT | 10 | 11
RRST_EXIT | 11 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_rst_ic.curr_rrst_state_reg' using encoding 'sequential' in module 'xpm_fifo_rst'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
invalid | 00 | 00
stage1_valid | 01 | 10
both_stages_valid | 10 | 11
stage2_valid | 11 | 01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'gen_fwft.curr_fwft_state_reg' using encoding 'sequential' in module 'xpm_fifo_base__parameterized0'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
idle | 00 | 00
transfer_okay | 01 | 01
temp_transfer_okay | 10 | 10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg' using encoding 'sequential' in module 'qspi_mode_0_module'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5791 ; free virtual = 13124
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
4 Input 9 Bit Adders := 6
2 Input 9 Bit Adders := 4
3 Input 9 Bit Adders := 4
2 Input 8 Bit Adders := 3
4 Input 8 Bit Adders := 10
3 Input 8 Bit Adders := 2
2 Input 5 Bit Adders := 1
4 Input 2 Bit Adders := 2
2 Input 1 Bit Adders := 1
+---XORs :
2 Input 9 Bit XORs := 4
2 Input 8 Bit XORs := 4
2 Input 1 Bit XORs := 90
+---Registers :
32 Bit Registers := 1
14 Bit Registers := 1
9 Bit Registers := 32
8 Bit Registers := 40
5 Bit Registers := 1
4 Bit Registers := 1
2 Bit Registers := 10
1 Bit Registers := 191
+---RAMs :
2K Bit (256 X 8 bit) RAMs := 2
+---Muxes :
2 Input 32 Bit Muxes := 3
3 Input 9 Bit Muxes := 2
2 Input 9 Bit Muxes := 2
2 Input 8 Bit Muxes := 24
8 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
6 Input 5 Bit Muxes := 2
2 Input 5 Bit Muxes := 17
2 Input 4 Bit Muxes := 1
2 Input 2 Bit Muxes := 68
5 Input 2 Bit Muxes := 2
4 Input 2 Bit Muxes := 14
11 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 115
8 Input 1 Bit Muxes := 11
6 Input 1 Bit Muxes := 4
5 Input 1 Bit Muxes := 6
4 Input 1 Bit Muxes := 5
3 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.CMD_ERR_S2AX_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.CMD_ERR_S2AX_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.MST_N_SLV_MODE_S2AX_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SLV_MODF_STRB_S2AX_3) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.MODF_STROBE_S2AX_3) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.RX_FIFO_EMPTY_AX2S_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.RX_FIFO_EMPTY_AX2S_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.TX_FIFO_EMPTY_S2AX_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.TX_FIFO_EMPTY_S2AX_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.TX_FIFO_FULL_AX2S_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.TX_FIFO_FULL_AX2S_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPIXFER_DONE_S2AX_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPIXFER_DONE_S2AX_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.RX_FIFO_FULL_S2AX_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.RX_FIFO_FULL_S2AX_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.DTR_UNDERRUN_S2AX_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.DTR_UNDERRUN_S2AX_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_5_TXFIFO_AX2S_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_6_RXFIFO_RST_AX2S_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SPICR_6_RXFIFO_RST_AX2S_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_1_CDC) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.CLK_CROSS_I/LOGIC_GENERATION_FDR.SR_3_MODF_AX2S_2) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/MST_TRANS_INHIBIT_D1_I) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SPISEL_REG) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/SCK_I_REG) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO2_I_REG) is unused and will be removed from module axi_quad_spi.
INFO: [Synth 8-3332] Sequential element (NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO3_I_REG) is unused and will be removed from module axi_quad_spi.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5764 ; free virtual = 13100
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Preliminary Mapping Report (see note below)
+-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 8(NO_CHANGE) | W | | 256 x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 8(NO_CHANGE) | W | | 256 x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
+-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5643 ; free virtual = 13016
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5596 ; free virtual = 12975
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
+-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 8(NO_CHANGE) | W | | 256 x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
|xpm_memory_base: | gen_wr_a.gen_word_narrow.mem_reg | 256 x 8(NO_CHANGE) | W | | 256 x 8(WRITE_FIRST) | | R | Port A and B | 1 | 0 |
+-----------------+----------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5520 ; free virtual = 12929
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5525 ; free virtual = 12923
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5525 ; free virtual = 12924
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5513 ; free virtual = 12923
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5511 ; free virtual = 12921
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5507 ; free virtual = 12919
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5507 ; free virtual = 12919
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |CARRY4 | 22|
|2 |LUT1 | 30|
|3 |LUT2 | 209|
|4 |LUT3 | 80|
|5 |LUT4 | 126|
|6 |LUT5 | 139|
|7 |LUT6 | 233|
|8 |RAMB18E1 | 2|
|9 |FD | 6|
|10 |FDR | 43|
|11 |FDRE | 749|
|12 |FDSE | 28|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2956.527 ; gain = 89.828 ; free physical = 5507 ; free virtual = 12919
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 202 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2956.527 ; gain = 0.000 ; free physical = 5571 ; free virtual = 12983
Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2956.535 ; gain = 89.828 ; free physical = 5571 ; free virtual = 12983
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2956.535 ; gain = 0.000 ; free physical = 5646 ; free virtual = 13058
INFO: [Netlist 29-17] Analyzing 73 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
WARNING: [Constraints 18-5572] Instance U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2956.535 ; gain = 0.000 ; free physical = 5579 ; free virtual = 12988
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 49 instances were transformed.
FD => FDRE: 6 instances
FDR => FDRE: 43 instances
Synth Design complete, checksum: 1ec12d00
INFO: [Common 17-83] Releasing license: Synthesis
327 Infos, 160 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:40 . Memory (MB): peak = 2956.535 ; gain = 97.840 ; free physical = 5773 ; free virtual = 13182
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/xlnx_axi_quad_spi.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_axi_quad_spi, cache-ID = 772dcc6fca29f6a8
INFO: [Coretcl 2-1174] Renamed 61 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.runs/xlnx_axi_quad_spi_synth_1/xlnx_axi_quad_spi.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_axi_quad_spi_utilization_synth.rpt -pb xlnx_axi_quad_spi_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:10:16 2022...
[Tue Sep 20 00:10:19 2022] xlnx_axi_quad_spi_synth_1 finished
wait_on_runs: Time (s): cpu = 00:01:03 ; elapsed = 00:01:02 . Memory (MB): peak = 2909.051 ; gain = 0.000 ; free physical = 6983 ; free virtual = 14358
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:10:19 2022...
|
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="56" Path="/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorVersionModelSim" Val="2020.4"/>
<Option Name="SimulatorVersionQuesta" Val="2020.4"/>
<Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
<Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
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<Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
<Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
<Option Name="BoardPart" Val="digilentinc.com:genesys2:part0:1.1"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="genesys2"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
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<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="ClassicSocBoot" Val="FALSE"/>
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<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="xlnx_axi_quad_spi" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_axi_quad_spi" RelGenDir="$PGENDIR/xlnx_axi_quad_spi">
<File Path="$PSRCDIR/sources_1/ip/xlnx_axi_quad_spi/xlnx_axi_quad_spi.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_axi_quad_spi"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
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<Simulator Name="XSim">
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<Option Name="CompiledLib" Val="0"/>
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<Option Name="Description" Val="ModelSim Simulator"/>
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<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulators>
<Runs Version="1" Minor="15">
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
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<Run Id="xlnx_axi_quad_spi_synth_1" Type="Ft3:Synth" SrcSet="xlnx_axi_quad_spi" Part="xc7k325tffg900-2" ConstrsSet="xlnx_axi_quad_spi" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/xlnx_axi_quad_spi_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/xlnx_axi_quad_spi_synth_1">
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<RQSFiles/>
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<Desc>Default settings for Implementation.</Desc>
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<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
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<Run Id="xlnx_axi_quad_spi_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xlnx_axi_quad_spi" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="xlnx_axi_quad_spi_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/xlnx_axi_quad_spi_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2021">
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2021"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
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<Board>
<Jumpers/>
</Board>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>
|
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_axi_quad_spi
create_project $ipName . -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_quad_spi -vendor xilinx.com -library ip -module_name $ipName
set_property -dict [list CONFIG.C_USE_STARTUP {0} CONFIG.C_SCK_RATIO {4} CONFIG.C_FIFO_DEPTH {256} CONFIG.C_TYPE_OF_AXI4_INTERFACE {1} CONFIG.C_S_AXI4_ID_WIDTH {0}] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1
|
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>772dcc6fca29f6a8</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>xlnx_axi_quad_spi</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_quad_spi" spirit:version="3.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_FULL.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.FULL_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Async_Clk">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_BYTE_LEVEL_INTERRUPT_EN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DUAL_QUAD_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FIFO_DEPTH">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INSTANCE">axi_quad_spi_inst</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_SS_BITS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_TRANSFER_BITS">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SCK_RATIO1">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SHARED_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MEMORY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MEM_ADDR_BITS">24</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SPI_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SUB_FAMILY">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_BASEADDR">0xFFFFFFFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_HIGHADDR">0x00000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI4_ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_STARTUP_INT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XIP_MODE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XIP_PERF_MODE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xlnx_axi_quad_spi</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_INCLUDED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_mode">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Multiples16">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.QSPI_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UC_FAMILY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">digilentinc.com:genesys2:part0:1.1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">772dcc6fca29f6a8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3358895 $</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">d179adad</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">45</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">24</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2021.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
|
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
// Date : Tue Sep 20 00:10:15 2022
// Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_quad_spi_sim_netlist.v
// Design : xlnx_axi_quad_spi
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_async_fifo_fg
(almost_full,
dout,
empty,
D,
\gen_wr_a.gen_word_narrow.mem_reg ,
rst,
s_axi4_aclk,
IP2Bus_WrAck_transmit_enable,
s_axi4_wdata,
ext_spi_clk,
rd_en,
\s_axi4_rdata_i_reg[0] ,
\s_axi4_rdata_i_reg[7] ,
\s_axi4_rdata_i_reg[7]_0 ,
\s_axi4_rdata_i_reg[0]_0 ,
\s_axi4_rdata_i_reg[1] ,
\s_axi4_rdata_i_reg[1]_0 ,
\s_axi4_rdata_i_reg[2] ,
\s_axi4_rdata_i_reg[2]_0 ,
\s_axi4_rdata_i_reg[3] ,
\s_axi4_rdata_i_reg[3]_0 ,
\s_axi4_rdata_i_reg[4] ,
\s_axi4_rdata_i_reg[4]_0 ,
\s_axi4_rdata_i_reg[5] ,
\s_axi4_rdata_i_reg[5]_0 ,
\s_axi4_rdata_i_reg[6] ,
\s_axi4_rdata_i_reg[6]_0 ,
\s_axi4_rdata_i_reg[7]_1 ,
\s_axi4_rdata_i_reg[7]_2 ,
\s_axi4_rdata_i_reg[7]_3 ,
p_2_in,
\s_axi4_rdata_i_reg[6]_1 ,
Bus_RNW_reg,
spicr_9_lsb_to_spi_clk);
output almost_full;
output [7:0]dout;
output empty;
output [7:0]D;
output \gen_wr_a.gen_word_narrow.mem_reg ;
input rst;
input s_axi4_aclk;
input IP2Bus_WrAck_transmit_enable;
input [7:0]s_axi4_wdata;
input ext_spi_clk;
input rd_en;
input \s_axi4_rdata_i_reg[0] ;
input [7:0]\s_axi4_rdata_i_reg[7] ;
input \s_axi4_rdata_i_reg[7]_0 ;
input \s_axi4_rdata_i_reg[0]_0 ;
input \s_axi4_rdata_i_reg[1] ;
input \s_axi4_rdata_i_reg[1]_0 ;
input \s_axi4_rdata_i_reg[2] ;
input \s_axi4_rdata_i_reg[2]_0 ;
input \s_axi4_rdata_i_reg[3] ;
input \s_axi4_rdata_i_reg[3]_0 ;
input \s_axi4_rdata_i_reg[4] ;
input \s_axi4_rdata_i_reg[4]_0 ;
input \s_axi4_rdata_i_reg[5] ;
input \s_axi4_rdata_i_reg[5]_0 ;
input \s_axi4_rdata_i_reg[6] ;
input \s_axi4_rdata_i_reg[6]_0 ;
input \s_axi4_rdata_i_reg[7]_1 ;
input \s_axi4_rdata_i_reg[7]_2 ;
input \s_axi4_rdata_i_reg[7]_3 ;
input p_2_in;
input \s_axi4_rdata_i_reg[6]_1 ;
input Bus_RNW_reg;
input spicr_9_lsb_to_spi_clk;
wire Bus_RNW_reg;
wire [7:0]D;
wire IP2Bus_WrAck_transmit_enable;
wire [8:0]Tx_FIFO_occ_Reversed;
wire almost_full;
wire [7:0]dout;
wire empty;
wire ext_spi_clk;
wire full;
wire \gen_wr_a.gen_word_narrow.mem_reg ;
wire p_2_in;
wire rd_en;
wire rst;
wire s_axi4_aclk;
wire \s_axi4_rdata_i[1]_i_2_n_0 ;
wire \s_axi4_rdata_i[2]_i_2_n_0 ;
wire \s_axi4_rdata_i[3]_i_2_n_0 ;
wire \s_axi4_rdata_i[4]_i_4_n_0 ;
wire \s_axi4_rdata_i[5]_i_2_n_0 ;
wire \s_axi4_rdata_i[6]_i_4_n_0 ;
wire \s_axi4_rdata_i[6]_i_5_n_0 ;
wire \s_axi4_rdata_i[6]_i_7_n_0 ;
wire \s_axi4_rdata_i[7]_i_6_n_0 ;
wire \s_axi4_rdata_i[7]_i_9_n_0 ;
wire \s_axi4_rdata_i_reg[0] ;
wire \s_axi4_rdata_i_reg[0]_0 ;
wire \s_axi4_rdata_i_reg[1] ;
wire \s_axi4_rdata_i_reg[1]_0 ;
wire \s_axi4_rdata_i_reg[2] ;
wire \s_axi4_rdata_i_reg[2]_0 ;
wire \s_axi4_rdata_i_reg[3] ;
wire \s_axi4_rdata_i_reg[3]_0 ;
wire \s_axi4_rdata_i_reg[4] ;
wire \s_axi4_rdata_i_reg[4]_0 ;
wire \s_axi4_rdata_i_reg[5] ;
wire \s_axi4_rdata_i_reg[5]_0 ;
wire \s_axi4_rdata_i_reg[6] ;
wire \s_axi4_rdata_i_reg[6]_0 ;
wire \s_axi4_rdata_i_reg[6]_1 ;
wire [7:0]\s_axi4_rdata_i_reg[7] ;
wire \s_axi4_rdata_i_reg[7]_0 ;
wire \s_axi4_rdata_i_reg[7]_1 ;
wire \s_axi4_rdata_i_reg[7]_2 ;
wire \s_axi4_rdata_i_reg[7]_3 ;
wire [7:0]s_axi4_wdata;
wire spicr_9_lsb_to_spi_clk;
wire wr_rst_busy;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_14 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_25 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_26 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_27 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_28 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_29 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_30 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_31 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_32 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_33 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_36 ;
wire \xpm_fifo_instance.xpm_fifo_async_inst_n_37 ;
wire \NLW_xpm_fifo_instance.xpm_fifo_async_inst_dbiterr_UNCONNECTED ;
wire \NLW_xpm_fifo_instance.xpm_fifo_async_inst_overflow_UNCONNECTED ;
wire \NLW_xpm_fifo_instance.xpm_fifo_async_inst_prog_empty_UNCONNECTED ;
wire \NLW_xpm_fifo_instance.xpm_fifo_async_inst_prog_full_UNCONNECTED ;
wire \NLW_xpm_fifo_instance.xpm_fifo_async_inst_rd_rst_busy_UNCONNECTED ;
wire \NLW_xpm_fifo_instance.xpm_fifo_async_inst_sbiterr_UNCONNECTED ;
wire \NLW_xpm_fifo_instance.xpm_fifo_async_inst_underflow_UNCONNECTED ;
LUT3 #(
.INIT(8'hB8))
\OTHER_RATIO_GENERATE.Serial_Dout_i_3
(.I0(dout[0]),
.I1(spicr_9_lsb_to_spi_clk),
.I2(dout[7]),
.O(\gen_wr_a.gen_word_narrow.mem_reg ));
LUT6 #(
.INIT(64'hFFAEFFAEFFFFFFAE))
\s_axi4_rdata_i[0]_i_1
(.I0(\s_axi4_rdata_i_reg[0] ),
.I1(\s_axi4_rdata_i_reg[7] [0]),
.I2(\s_axi4_rdata_i_reg[7]_0 ),
.I3(\s_axi4_rdata_i_reg[0]_0 ),
.I4(\s_axi4_rdata_i[6]_i_4_n_0 ),
.I5(Tx_FIFO_occ_Reversed[0]),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF22F2))
\s_axi4_rdata_i[1]_i_1
(.I0(\s_axi4_rdata_i_reg[7] [1]),
.I1(\s_axi4_rdata_i_reg[7]_0 ),
.I2(\s_axi4_rdata_i[6]_i_4_n_0 ),
.I3(\s_axi4_rdata_i[1]_i_2_n_0 ),
.I4(\s_axi4_rdata_i_reg[1] ),
.I5(\s_axi4_rdata_i_reg[1]_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h6))
\s_axi4_rdata_i[1]_i_2
(.I0(Tx_FIFO_occ_Reversed[0]),
.I1(Tx_FIFO_occ_Reversed[1]),
.O(\s_axi4_rdata_i[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF22F2))
\s_axi4_rdata_i[2]_i_1
(.I0(\s_axi4_rdata_i_reg[7] [2]),
.I1(\s_axi4_rdata_i_reg[7]_0 ),
.I2(\s_axi4_rdata_i[6]_i_4_n_0 ),
.I3(\s_axi4_rdata_i[2]_i_2_n_0 ),
.I4(\s_axi4_rdata_i_reg[2] ),
.I5(\s_axi4_rdata_i_reg[2]_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'h56))
\s_axi4_rdata_i[2]_i_2
(.I0(Tx_FIFO_occ_Reversed[2]),
.I1(Tx_FIFO_occ_Reversed[1]),
.I2(Tx_FIFO_occ_Reversed[0]),
.O(\s_axi4_rdata_i[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF22F2))
\s_axi4_rdata_i[3]_i_1
(.I0(\s_axi4_rdata_i_reg[7] [3]),
.I1(\s_axi4_rdata_i_reg[7]_0 ),
.I2(\s_axi4_rdata_i[6]_i_4_n_0 ),
.I3(\s_axi4_rdata_i[3]_i_2_n_0 ),
.I4(\s_axi4_rdata_i_reg[3] ),
.I5(\s_axi4_rdata_i_reg[3]_0 ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT4 #(
.INIT(16'h5556))
\s_axi4_rdata_i[3]_i_2
(.I0(Tx_FIFO_occ_Reversed[3]),
.I1(Tx_FIFO_occ_Reversed[0]),
.I2(Tx_FIFO_occ_Reversed[1]),
.I3(Tx_FIFO_occ_Reversed[2]),
.O(\s_axi4_rdata_i[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFAEFFAEFFFFFFAE))
\s_axi4_rdata_i[4]_i_1
(.I0(\s_axi4_rdata_i_reg[4] ),
.I1(\s_axi4_rdata_i_reg[7] [4]),
.I2(\s_axi4_rdata_i_reg[7]_0 ),
.I3(\s_axi4_rdata_i_reg[4]_0 ),
.I4(\s_axi4_rdata_i[6]_i_4_n_0 ),
.I5(\s_axi4_rdata_i[4]_i_4_n_0 ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT5 #(
.INIT(32'h55555556))
\s_axi4_rdata_i[4]_i_4
(.I0(Tx_FIFO_occ_Reversed[4]),
.I1(Tx_FIFO_occ_Reversed[2]),
.I2(Tx_FIFO_occ_Reversed[1]),
.I3(Tx_FIFO_occ_Reversed[0]),
.I4(Tx_FIFO_occ_Reversed[3]),
.O(\s_axi4_rdata_i[4]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF22F2))
\s_axi4_rdata_i[5]_i_1
(.I0(\s_axi4_rdata_i_reg[7] [5]),
.I1(\s_axi4_rdata_i_reg[7]_0 ),
.I2(\s_axi4_rdata_i[6]_i_4_n_0 ),
.I3(\s_axi4_rdata_i[5]_i_2_n_0 ),
.I4(\s_axi4_rdata_i_reg[5] ),
.I5(\s_axi4_rdata_i_reg[5]_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'h5555555555555556))
\s_axi4_rdata_i[5]_i_2
(.I0(Tx_FIFO_occ_Reversed[5]),
.I1(Tx_FIFO_occ_Reversed[3]),
.I2(Tx_FIFO_occ_Reversed[0]),
.I3(Tx_FIFO_occ_Reversed[1]),
.I4(Tx_FIFO_occ_Reversed[2]),
.I5(Tx_FIFO_occ_Reversed[4]),
.O(\s_axi4_rdata_i[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFAEFFAEFFFFFFAE))
\s_axi4_rdata_i[6]_i_1
(.I0(\s_axi4_rdata_i_reg[6] ),
.I1(\s_axi4_rdata_i_reg[7] [6]),
.I2(\s_axi4_rdata_i_reg[7]_0 ),
.I3(\s_axi4_rdata_i_reg[6]_0 ),
.I4(\s_axi4_rdata_i[6]_i_4_n_0 ),
.I5(\s_axi4_rdata_i[6]_i_5_n_0 ),
.O(D[6]));
LUT6 #(
.INIT(64'h0000FB0000000000))
\s_axi4_rdata_i[6]_i_4
(.I0(Tx_FIFO_occ_Reversed[7]),
.I1(\s_axi4_rdata_i[7]_i_9_n_0 ),
.I2(Tx_FIFO_occ_Reversed[8]),
.I3(Bus_RNW_reg),
.I4(\s_axi4_rdata_i_reg[6]_1 ),
.I5(p_2_in),
.O(\s_axi4_rdata_i[6]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h6))
\s_axi4_rdata_i[6]_i_5
(.I0(Tx_FIFO_occ_Reversed[6]),
.I1(\s_axi4_rdata_i[6]_i_7_n_0 ),
.O(\s_axi4_rdata_i[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_axi4_rdata_i[6]_i_7
(.I0(Tx_FIFO_occ_Reversed[5]),
.I1(Tx_FIFO_occ_Reversed[3]),
.I2(Tx_FIFO_occ_Reversed[0]),
.I3(Tx_FIFO_occ_Reversed[1]),
.I4(Tx_FIFO_occ_Reversed[2]),
.I5(Tx_FIFO_occ_Reversed[4]),
.O(\s_axi4_rdata_i[6]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF22F2))
\s_axi4_rdata_i[7]_i_1
(.I0(\s_axi4_rdata_i_reg[7] [7]),
.I1(\s_axi4_rdata_i_reg[7]_0 ),
.I2(\s_axi4_rdata_i_reg[7]_1 ),
.I3(\s_axi4_rdata_i_reg[7]_2 ),
.I4(\s_axi4_rdata_i_reg[7]_3 ),
.I5(\s_axi4_rdata_i[7]_i_6_n_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'h0000202020000000))
\s_axi4_rdata_i[7]_i_6
(.I0(p_2_in),
.I1(\s_axi4_rdata_i_reg[6]_1 ),
.I2(Bus_RNW_reg),
.I3(Tx_FIFO_occ_Reversed[8]),
.I4(\s_axi4_rdata_i[7]_i_9_n_0 ),
.I5(Tx_FIFO_occ_Reversed[7]),
.O(\s_axi4_rdata_i[7]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h1))
\s_axi4_rdata_i[7]_i_9
(.I0(Tx_FIFO_occ_Reversed[6]),
.I1(\s_axi4_rdata_i[6]_i_7_n_0 ),
.O(\s_axi4_rdata_i[7]_i_9_n_0 ));
(* CASCADE_HEIGHT = "0" *)
(* CDC_SYNC_STAGES = "2" *)
(* DOUT_RESET_VALUE = "0" *)
(* ECC_MODE = "no_ecc" *)
(* EN_ADV_FEATURE_ASYNC = "16'b0001111100011111" *)
(* FIFO_MEMORY_TYPE = "auto" *)
(* FIFO_READ_LATENCY = "0" *)
(* FIFO_WRITE_DEPTH = "256" *)
(* FULL_RESET_VALUE = "1" *)
(* PROG_EMPTY_THRESH = "10" *)
(* PROG_FULL_THRESH = "10" *)
(* P_COMMON_CLOCK = "0" *)
(* P_ECC_MODE = "0" *)
(* P_FIFO_MEMORY_TYPE = "0" *)
(* P_READ_MODE = "1" *)
(* P_WAKEUP_TIME = "2" *)
(* RD_DATA_COUNT_WIDTH = "9" *)
(* READ_DATA_WIDTH = "8" *)
(* READ_MODE = "fwft" *)
(* RELATED_CLOCKS = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* USE_ADV_FEATURES = "1F1F" *)
(* WAKEUP_TIME = "0" *)
(* WRITE_DATA_WIDTH = "8" *)
(* WR_DATA_COUNT_WIDTH = "9" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1 \xpm_fifo_instance.xpm_fifo_async_inst
(.almost_empty(\xpm_fifo_instance.xpm_fifo_async_inst_n_36 ),
.almost_full(almost_full),
.data_valid(\xpm_fifo_instance.xpm_fifo_async_inst_n_37 ),
.dbiterr(\NLW_xpm_fifo_instance.xpm_fifo_async_inst_dbiterr_UNCONNECTED ),
.din(s_axi4_wdata),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.overflow(\NLW_xpm_fifo_instance.xpm_fifo_async_inst_overflow_UNCONNECTED ),
.prog_empty(\NLW_xpm_fifo_instance.xpm_fifo_async_inst_prog_empty_UNCONNECTED ),
.prog_full(\NLW_xpm_fifo_instance.xpm_fifo_async_inst_prog_full_UNCONNECTED ),
.rd_clk(ext_spi_clk),
.rd_data_count({\xpm_fifo_instance.xpm_fifo_async_inst_n_25 ,\xpm_fifo_instance.xpm_fifo_async_inst_n_26 ,\xpm_fifo_instance.xpm_fifo_async_inst_n_27 ,\xpm_fifo_instance.xpm_fifo_async_inst_n_28 ,\xpm_fifo_instance.xpm_fifo_async_inst_n_29 ,\xpm_fifo_instance.xpm_fifo_async_inst_n_30 ,\xpm_fifo_instance.xpm_fifo_async_inst_n_31 ,\xpm_fifo_instance.xpm_fifo_async_inst_n_32 ,\xpm_fifo_instance.xpm_fifo_async_inst_n_33 }),
.rd_en(rd_en),
.rd_rst_busy(\NLW_xpm_fifo_instance.xpm_fifo_async_inst_rd_rst_busy_UNCONNECTED ),
.rst(rst),
.sbiterr(\NLW_xpm_fifo_instance.xpm_fifo_async_inst_sbiterr_UNCONNECTED ),
.sleep(1'b0),
.underflow(\NLW_xpm_fifo_instance.xpm_fifo_async_inst_underflow_UNCONNECTED ),
.wr_ack(\xpm_fifo_instance.xpm_fifo_async_inst_n_14 ),
.wr_clk(s_axi4_aclk),
.wr_data_count(Tx_FIFO_occ_Reversed),
.wr_en(IP2Bus_WrAck_transmit_enable),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_qspi_enhanced_mode
(p_1_in,
p_2_in,
p_4_in,
SR,
s_axi4_awready,
s_axi4_arready,
s_axi4_rresp,
ip2bus_error_int,
Bus_RNW_reg,
s_axi4_bvalid,
burst_tr_int,
s_axi4_rlast,
Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1,
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30] ,
ip2Bus_WrAck_core_reg0,
wr_ce_or_reduce_core_cmb,
ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole0,
s_axi_rvalid_i_reg_0,
Q,
\FSM_onehot_axi_full_sm_ps_reg[2]_0 ,
reset_trig0,
sw_rst_cond,
Transmit_ip2bus_error0,
s_axi4_wready,
IP2Bus_WrAck_transmit_enable,
rd_en,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27] ,
reset2ip_reset_int,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] ,
bus2ip_wrce_int,
irpt_wrack,
interrupt_wrce_strb,
\ip_irpt_enable_reg_reg[1] ,
\ip_irpt_enable_reg_reg[2] ,
\ip_irpt_enable_reg_reg[3] ,
\ip_irpt_enable_reg_reg[4] ,
\ip_irpt_enable_reg_reg[5] ,
\ip_irpt_enable_reg_reg[6] ,
\ip_irpt_enable_reg_reg[7] ,
irpt_rdack,
intr2bus_rdack0,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
\bus2ip_BE_reg_reg[3]_0 ,
rd_ce_or_reduce_core_cmb,
intr_controller_rd_ce_or_reduce,
s_axi4_wdata_0_sp_1,
\s_axi4_wdata[31] ,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ,
s_axi4_bresp,
s_axi4_rdata,
s_axi4_aclk,
E,
s_axi4_araddr,
s_axi4_arvalid,
s_axi4_awaddr,
s_axi4_rready,
ip2Bus_WrAck_core_reg,
empty,
ip2Bus_WrAck_core_reg_d1,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
s_axi4_bready,
s_axi4_awvalid,
s_axi4_wvalid,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
s_axi4_arlen,
s_axi4_awlen,
s_axi_rvalid_i_reg_1,
data_valid,
\FSM_onehot_axi_full_sm_ps_reg[3]_0 ,
transmit_ip2bus_error,
receive_ip2bus_error,
sw_rst_cond_d1,
s_axi4_wdata,
Tx_FIFO_Full_int,
almost_full,
ip2Bus_RdAck_core_reg,
s_axi4_aresetn,
s_axi4_wstrb,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] ,
\s_axi4_rdata_i_reg[8]_0 ,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
SPISSR_frm_axi_clk,
rx_fifo_empty_i,
spicr_0_loop_frm_axi_clk,
irpt_wrack_d1,
p_1_in34_in,
p_1_in31_in,
p_1_in28_in,
spicr_4_cpha_frm_axi_clk,
p_1_in25_in,
p_1_in22_in,
spicr_6_rxfifo_rst_frm_axi_clk,
p_1_in19_in,
p_1_in16_in,
spicr_7_ss_frm_axi_clk,
D,
spicr_8_tr_inhibit_frm_axi_clk,
p_1_in13_in,
p_0_in,
irpt_rdack_d1,
scndry_out,
spicr_1_spe_frm_axi_clk,
Tx_FIFO_Empty_SPISR_to_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk,
spisel_d1_reg_to_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk,
spicr_9_lsb_frm_axi_clk);
output p_1_in;
output p_2_in;
output p_4_in;
output [0:0]SR;
output s_axi4_awready;
output s_axi4_arready;
output [0:0]s_axi4_rresp;
output ip2bus_error_int;
output Bus_RNW_reg;
output s_axi4_bvalid;
output burst_tr_int;
output s_axi4_rlast;
output Bus_RNW_reg_reg;
output [0:0]Bus_RNW_reg_reg_0;
output Bus_RNW_reg_reg_1;
output \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30] ;
output ip2Bus_WrAck_core_reg0;
output wr_ce_or_reduce_core_cmb;
output ip2Bus_RdAck_intr_reg_hole0;
output ip2Bus_WrAck_intr_reg_hole0;
output s_axi_rvalid_i_reg_0;
output [0:0]Q;
output \FSM_onehot_axi_full_sm_ps_reg[2]_0 ;
output reset_trig0;
output sw_rst_cond;
output Transmit_ip2bus_error0;
output s_axi4_wready;
output IP2Bus_WrAck_transmit_enable;
output rd_en;
output \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27] ;
output reset2ip_reset_int;
output \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] ;
output [0:0]bus2ip_wrce_int;
output irpt_wrack;
output interrupt_wrce_strb;
output \ip_irpt_enable_reg_reg[1] ;
output \ip_irpt_enable_reg_reg[2] ;
output \ip_irpt_enable_reg_reg[3] ;
output \ip_irpt_enable_reg_reg[4] ;
output \ip_irpt_enable_reg_reg[5] ;
output \ip_irpt_enable_reg_reg[6] ;
output \ip_irpt_enable_reg_reg[7] ;
output irpt_rdack;
output intr2bus_rdack0;
output \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
output \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
output \bus2ip_BE_reg_reg[3]_0 ;
output rd_ce_or_reduce_core_cmb;
output intr_controller_rd_ce_or_reduce;
output s_axi4_wdata_0_sp_1;
output \s_axi4_wdata[31] ;
output \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ;
output \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ;
output [0:0]s_axi4_bresp;
output [10:0]s_axi4_rdata;
input s_axi4_aclk;
input [0:0]E;
input [4:0]s_axi4_araddr;
input s_axi4_arvalid;
input [4:0]s_axi4_awaddr;
input s_axi4_rready;
input ip2Bus_WrAck_core_reg;
input empty;
input ip2Bus_WrAck_core_reg_d1;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input s_axi4_bready;
input s_axi4_awvalid;
input s_axi4_wvalid;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input [7:0]s_axi4_arlen;
input [7:0]s_axi4_awlen;
input s_axi_rvalid_i_reg_1;
input data_valid;
input \FSM_onehot_axi_full_sm_ps_reg[3]_0 ;
input transmit_ip2bus_error;
input receive_ip2bus_error;
input sw_rst_cond_d1;
input [6:0]s_axi4_wdata;
input Tx_FIFO_Full_int;
input almost_full;
input ip2Bus_RdAck_core_reg;
input s_axi4_aresetn;
input [1:0]s_axi4_wstrb;
input \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] ;
input [8:0]\s_axi4_rdata_i_reg[8]_0 ;
input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
input SPISSR_frm_axi_clk;
input rx_fifo_empty_i;
input spicr_0_loop_frm_axi_clk;
input irpt_wrack_d1;
input p_1_in34_in;
input p_1_in31_in;
input p_1_in28_in;
input spicr_4_cpha_frm_axi_clk;
input p_1_in25_in;
input p_1_in22_in;
input spicr_6_rxfifo_rst_frm_axi_clk;
input p_1_in19_in;
input p_1_in16_in;
input spicr_7_ss_frm_axi_clk;
input [7:0]D;
input spicr_8_tr_inhibit_frm_axi_clk;
input p_1_in13_in;
input [0:0]p_0_in;
input irpt_rdack_d1;
input scndry_out;
input spicr_1_spe_frm_axi_clk;
input Tx_FIFO_Empty_SPISR_to_axi_clk;
input spicr_2_mst_n_slv_frm_axi_clk;
input spicr_3_cpol_frm_axi_clk;
input spisel_d1_reg_to_axi_clk;
input spicr_5_txfifo_rst_frm_axi_clk;
input spicr_9_lsb_frm_axi_clk;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire [0:0]Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ;
wire \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ;
wire [7:0]D;
wire [0:0]E;
wire \FSM_onehot_axi_full_sm_ps[0]_i_1_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[0]_i_2_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[1]_i_1_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[2]_i_1_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[3]_i_4_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[4]_i_1_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[4]_i_2_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[5]_i_1_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[6]_i_1_n_0 ;
wire \FSM_onehot_axi_full_sm_ps[7]_i_1_n_0 ;
wire \FSM_onehot_axi_full_sm_ps_reg[2]_0 ;
wire \FSM_onehot_axi_full_sm_ps_reg[3]_0 ;
wire \FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ;
wire \FSM_onehot_axi_full_sm_ps_reg_n_0_[3] ;
wire \FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ;
wire \FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ;
wire \FSM_onehot_axi_full_sm_ps_reg_n_0_[6] ;
wire \FSM_onehot_axi_full_sm_ps_reg_n_0_[7] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27] ;
wire \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30] ;
wire \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
wire \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
wire IP2Bus_WrAck_transmit_enable;
wire I_DECODER_n_13;
wire I_DECODER_n_14;
wire I_DECODER_n_15;
wire I_DECODER_n_21;
wire I_DECODER_n_24;
wire [0:0]Q;
wire [0:0]\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/IP2Bus_SPICR_Data_int ;
wire [0:0]\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/intr_ip2bus_data ;
wire \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] ;
wire SPISSR_frm_axi_clk;
wire [0:0]SR;
wire \S_AXI4_BRESP_i[1]_i_1_n_0 ;
wire Transmit_ip2bus_error0;
wire Tx_FIFO_Empty_SPISR_to_axi_clk;
wire Tx_FIFO_Full_int;
wire almost_full;
wire arready_cmb;
wire awready_cmb;
wire awready_i_i_10_n_0;
wire awready_i_i_3_n_0;
wire awready_i_i_5_n_0;
wire awready_i_i_6_n_0;
wire awready_i_i_7_n_0;
wire awready_i_i_8_n_0;
wire awready_i_i_9_n_0;
wire axi_full_sm_ps_IDLE_cmb;
wire burst_tr_int;
wire burst_transfer_cmb;
wire burst_transfer_reg_i_1_n_0;
wire \bus2ip_BE_reg[0]_i_1_n_0 ;
wire \bus2ip_BE_reg[3]_i_1_n_0 ;
wire \bus2ip_BE_reg_reg[3]_0 ;
wire [3:0]bus2ip_be_int;
wire [0:0]bus2ip_wrce_int;
wire clear;
wire data_valid;
wire empty;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_controller_rd_ce_or_reduce;
wire ip2Bus_RdAck_core_reg;
wire ip2Bus_RdAck_intr_reg_hole0;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_core_reg;
wire ip2Bus_WrAck_core_reg0;
wire ip2Bus_WrAck_core_reg_d1;
wire ip2Bus_WrAck_intr_reg_hole0;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [8:8]ip2bus_data_int;
wire ip2bus_error_int;
wire \ip_irpt_enable_reg_reg[1] ;
wire \ip_irpt_enable_reg_reg[2] ;
wire \ip_irpt_enable_reg_reg[3] ;
wire \ip_irpt_enable_reg_reg[4] ;
wire \ip_irpt_enable_reg_reg[5] ;
wire \ip_irpt_enable_reg_reg[6] ;
wire \ip_irpt_enable_reg_reg[7] ;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire last_data_acked_i_2_n_0;
wire last_data_acked_i_3_n_0;
wire last_data_acked_i_4_n_0;
wire last_data_acked_i_5_n_0;
wire last_data_acked_i_6_n_0;
wire last_data_acked_i_7_n_0;
wire \length_cntr[2]_i_2_n_0 ;
wire \length_cntr[3]_i_2_n_0 ;
wire \length_cntr[6]_i_2_n_0 ;
wire \length_cntr[7]_i_1_n_0 ;
wire \length_cntr[7]_i_3_n_0 ;
wire \length_cntr[7]_i_4_n_0 ;
wire \length_cntr[7]_i_5_n_0 ;
wire [7:0]length_cntr_reg;
wire [0:0]p_0_in;
wire [7:0]p_0_in__0;
wire p_1_in;
wire p_1_in13_in;
wire p_1_in16_in;
wire p_1_in19_in;
wire p_1_in22_in;
wire p_1_in25_in;
wire p_1_in28_in;
wire p_1_in31_in;
wire p_1_in34_in;
wire p_2_in;
wire p_4_in;
wire rd_ce_or_reduce_core_cmb;
wire rd_en;
wire receive_ip2bus_error;
wire reset2ip_reset_int;
wire reset_trig0;
wire rnw_cmb;
wire rnw_reg_i_2_n_0;
wire rnw_reg_i_3_n_0;
wire rnw_reg_reg_n_0;
wire rx_fifo_empty_i;
wire s_axi4_aclk;
wire [4:0]s_axi4_araddr;
wire s_axi4_aresetn;
wire [7:0]s_axi4_arlen;
wire s_axi4_arready;
wire s_axi4_arvalid;
wire [4:0]s_axi4_awaddr;
wire [7:0]s_axi4_awlen;
wire s_axi4_awready;
wire s_axi4_awvalid;
wire s_axi4_bready;
wire [0:0]s_axi4_bresp;
wire s_axi4_bvalid;
wire [10:0]s_axi4_rdata;
wire [8:0]\s_axi4_rdata_i_reg[8]_0 ;
wire s_axi4_rlast;
wire s_axi4_rready;
wire [0:0]s_axi4_rresp;
wire \s_axi4_rresp_i[1]_i_2_n_0 ;
wire [6:0]s_axi4_wdata;
wire \s_axi4_wdata[31] ;
wire s_axi4_wdata_0_sn_1;
wire s_axi4_wready;
wire [1:0]s_axi4_wstrb;
wire s_axi4_wvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire s_axi_rvalid_i_i_1_n_0;
wire s_axi_rvalid_i_i_2_n_0;
wire s_axi_rvalid_i_reg_0;
wire s_axi_rvalid_i_reg_1;
wire s_axi_wready_i;
wire s_axi_wready_i_i_1_n_0;
wire s_axi_wready_i_i_2_n_0;
wire scndry_out;
wire spicr_0_loop_frm_axi_clk;
wire spicr_1_spe_frm_axi_clk;
wire spicr_2_mst_n_slv_frm_axi_clk;
wire spicr_3_cpol_frm_axi_clk;
wire spicr_4_cpha_frm_axi_clk;
wire spicr_5_txfifo_rst_frm_axi_clk;
wire spicr_6_rxfifo_rst_frm_axi_clk;
wire spicr_7_ss_frm_axi_clk;
wire spicr_8_tr_inhibit_frm_axi_clk;
wire spicr_9_lsb_frm_axi_clk;
wire spisel_d1_reg_to_axi_clk;
wire start;
wire sw_rst_cond;
wire sw_rst_cond_d1;
wire transmit_ip2bus_error;
wire wr_ce_or_reduce_core_cmb;
wire \xpm_fifo_instance.xpm_fifo_async_inst_i_4_n_0 ;
assign s_axi4_wdata_0_sp_1 = s_axi4_wdata_0_sn_1;
FDRE Bus2IP_Reset_i_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(clear),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFFBA00))
\FSM_onehot_axi_full_sm_ps[0]_i_1
(.I0(\FSM_onehot_axi_full_sm_ps_reg_n_0_[3] ),
.I1(I_DECODER_n_21),
.I2(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.I3(s_axi4_rready),
.I4(\FSM_onehot_axi_full_sm_ps[0]_i_2_n_0 ),
.O(\FSM_onehot_axi_full_sm_ps[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h888888888FFF8888))
\FSM_onehot_axi_full_sm_ps[0]_i_2
(.I0(\FSM_onehot_axi_full_sm_ps_reg_n_0_[7] ),
.I1(s_axi4_bready),
.I2(s_axi4_awvalid),
.I3(s_axi4_wvalid),
.I4(axi_full_sm_ps_IDLE_cmb),
.I5(s_axi4_arvalid),
.O(\FSM_onehot_axi_full_sm_ps[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'hFF808080))
\FSM_onehot_axi_full_sm_ps[1]_i_1
(.I0(s_axi4_arvalid),
.I1(axi_full_sm_ps_IDLE_cmb),
.I2(burst_transfer_cmb),
.I3(I_DECODER_n_21),
.I4(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.O(\FSM_onehot_axi_full_sm_ps[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hFF404040))
\FSM_onehot_axi_full_sm_ps[2]_i_1
(.I0(burst_transfer_cmb),
.I1(s_axi4_arvalid),
.I2(axi_full_sm_ps_IDLE_cmb),
.I3(s_axi_rvalid_i_reg_1),
.I4(Q),
.O(\FSM_onehot_axi_full_sm_ps[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEEEAAAAA))
\FSM_onehot_axi_full_sm_ps[3]_i_2
(.I0(Q),
.I1(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.I2(last_data_acked_i_6_n_0),
.I3(I_DECODER_n_24),
.I4(s_axi4_rready),
.O(\FSM_onehot_axi_full_sm_ps_reg[2]_0 ));
LUT5 #(
.INIT(32'h55550004))
\FSM_onehot_axi_full_sm_ps[3]_i_4
(.I0(s_axi4_rready),
.I1(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.I2(last_data_acked_i_6_n_0),
.I3(I_DECODER_n_24),
.I4(\FSM_onehot_axi_full_sm_ps_reg_n_0_[3] ),
.O(\FSM_onehot_axi_full_sm_ps[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAEAAAAAAAAAAAAA))
\FSM_onehot_axi_full_sm_ps[4]_i_1
(.I0(\FSM_onehot_axi_full_sm_ps[4]_i_2_n_0 ),
.I1(s_axi4_wvalid),
.I2(s_axi4_awvalid),
.I3(s_axi4_arvalid),
.I4(axi_full_sm_ps_IDLE_cmb),
.I5(burst_transfer_cmb),
.O(\FSM_onehot_axi_full_sm_ps[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT4 #(
.INIT(16'hAA8A))
\FSM_onehot_axi_full_sm_ps[4]_i_2
(.I0(\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ),
.I1(almost_full),
.I2(s_axi4_wvalid),
.I3(I_DECODER_n_21),
.O(\FSM_onehot_axi_full_sm_ps[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0020FFFF00200020))
\FSM_onehot_axi_full_sm_ps[5]_i_1
(.I0(awready_i_i_3_n_0),
.I1(s_axi4_arvalid),
.I2(axi_full_sm_ps_IDLE_cmb),
.I3(burst_transfer_cmb),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I5(\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ),
.O(\FSM_onehot_axi_full_sm_ps[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'hF444))
\FSM_onehot_axi_full_sm_ps[6]_i_1
(.I0(I_DECODER_n_15),
.I1(\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I3(\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ),
.O(\FSM_onehot_axi_full_sm_ps[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\FSM_onehot_axi_full_sm_ps[7]_i_1
(.I0(\FSM_onehot_axi_full_sm_ps_reg_n_0_[6] ),
.I1(s_axi4_bready),
.I2(\FSM_onehot_axi_full_sm_ps_reg_n_0_[7] ),
.O(\FSM_onehot_axi_full_sm_ps[7]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_axi_full_sm_ps_reg[0]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FSM_onehot_axi_full_sm_ps[0]_i_1_n_0 ),
.Q(axi_full_sm_ps_IDLE_cmb),
.S(SR));
(* FSM_ENCODED_STATES = "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_axi_full_sm_ps_reg[1]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FSM_onehot_axi_full_sm_ps[1]_i_1_n_0 ),
.Q(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.R(SR));
(* FSM_ENCODED_STATES = "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_axi_full_sm_ps_reg[2]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FSM_onehot_axi_full_sm_ps[2]_i_1_n_0 ),
.Q(Q),
.R(SR));
(* FSM_ENCODED_STATES = "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_axi_full_sm_ps_reg[3]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(I_DECODER_n_14),
.Q(\FSM_onehot_axi_full_sm_ps_reg_n_0_[3] ),
.R(SR));
(* FSM_ENCODED_STATES = "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_axi_full_sm_ps_reg[4]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FSM_onehot_axi_full_sm_ps[4]_i_1_n_0 ),
.Q(\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ),
.R(SR));
(* FSM_ENCODED_STATES = "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_axi_full_sm_ps_reg[5]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FSM_onehot_axi_full_sm_ps[5]_i_1_n_0 ),
.Q(\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ),
.R(SR));
(* FSM_ENCODED_STATES = "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_axi_full_sm_ps_reg[6]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FSM_onehot_axi_full_sm_ps[6]_i_1_n_0 ),
.Q(\FSM_onehot_axi_full_sm_ps_reg_n_0_[6] ),
.R(SR));
(* FSM_ENCODED_STATES = "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_axi_full_sm_ps_reg[7]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FSM_onehot_axi_full_sm_ps[7]_i_1_n_0 ),
.Q(\FSM_onehot_axi_full_sm_ps_reg_n_0_[7] ),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_address_decoder I_DECODER
(.Bus_RNW_reg_reg_0(Bus_RNW_reg),
.Bus_RNW_reg_reg_1(Bus_RNW_reg_reg),
.Bus_RNW_reg_reg_2(Bus_RNW_reg_reg_0),
.Bus_RNW_reg_reg_3(Bus_RNW_reg_reg_1),
.Bus_RNW_reg_reg_4(ip2bus_error_int),
.\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] (\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ),
.\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] (\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ),
.D(I_DECODER_n_14),
.\FSM_onehot_axi_full_sm_ps_reg[0] (I_DECODER_n_13),
.\FSM_onehot_axi_full_sm_ps_reg[1] (length_cntr_reg),
.\FSM_onehot_axi_full_sm_ps_reg[3] (\FSM_onehot_axi_full_sm_ps_reg[2]_0 ),
.\FSM_onehot_axi_full_sm_ps_reg[3]_0 (\FSM_onehot_axi_full_sm_ps_reg[3]_0 ),
.\FSM_onehot_axi_full_sm_ps_reg[3]_1 (\FSM_onehot_axi_full_sm_ps[3]_i_4_n_0 ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ({\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ,\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ,\FSM_onehot_axi_full_sm_ps_reg_n_0_[3] ,Q,\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ,axi_full_sm_ps_IDLE_cmb}),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 (p_4_in),
.\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_1 (\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27] ),
.\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]_0 (\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30] ),
.\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 (\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] ),
.\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1 ({\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/intr_ip2bus_data ,\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/IP2Bus_SPICR_Data_int ,ip2bus_data_int}),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ),
.\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] (\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ),
.IP2Bus_WrAck_transmit_enable(IP2Bus_WrAck_transmit_enable),
.Q(bus2ip_be_int[3]),
.SPISSR_frm_axi_clk(SPISSR_frm_axi_clk),
.Transmit_ip2bus_error0(Transmit_ip2bus_error0),
.Tx_FIFO_Empty_SPISR_to_axi_clk(Tx_FIFO_Empty_SPISR_to_axi_clk),
.Tx_FIFO_Full_int(Tx_FIFO_Full_int),
.almost_full(almost_full),
.\bus2ip_BE_reg_reg[3] (\bus2ip_BE_reg_reg[3]_0 ),
.bus2ip_wrce_int(bus2ip_wrce_int),
.data_valid(data_valid),
.empty(empty),
.\guf.underflow_i_reg (s_axi_rvalid_i_i_2_n_0),
.\gwack.wr_ack_i_reg (burst_tr_int),
.\gwack.wr_ack_i_reg_0 (\xpm_fifo_instance.xpm_fifo_async_inst_i_4_n_0 ),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_controller_rd_ce_or_reduce(intr_controller_rd_ce_or_reduce),
.ip2Bus_RdAck_core_reg(ip2Bus_RdAck_core_reg),
.ip2Bus_RdAck_intr_reg_hole0(ip2Bus_RdAck_intr_reg_hole0),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_core_reg(ip2Bus_WrAck_core_reg),
.ip2Bus_WrAck_core_reg0(ip2Bus_WrAck_core_reg0),
.ip2Bus_WrAck_core_reg_d1(ip2Bus_WrAck_core_reg_d1),
.ip2Bus_WrAck_intr_reg_hole0(ip2Bus_WrAck_intr_reg_hole0),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.\ip_irpt_enable_reg_reg[1] (\ip_irpt_enable_reg_reg[1] ),
.\ip_irpt_enable_reg_reg[2] (\ip_irpt_enable_reg_reg[2] ),
.\ip_irpt_enable_reg_reg[3] (\ip_irpt_enable_reg_reg[3] ),
.\ip_irpt_enable_reg_reg[4] (\ip_irpt_enable_reg_reg[4] ),
.\ip_irpt_enable_reg_reg[5] (\ip_irpt_enable_reg_reg[5] ),
.\ip_irpt_enable_reg_reg[6] (\ip_irpt_enable_reg_reg[6] ),
.\ip_irpt_enable_reg_reg[7] (\ip_irpt_enable_reg_reg[7] ),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.last_data_acked_reg(last_data_acked_i_2_n_0),
.last_data_acked_reg_0(last_data_acked_i_3_n_0),
.last_data_acked_reg_1(last_data_acked_i_4_n_0),
.last_data_acked_reg_2(last_data_acked_i_5_n_0),
.\length_cntr_reg[2] (I_DECODER_n_24),
.\length_cntr_reg[6] (I_DECODER_n_21),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_1_in13_in(p_1_in13_in),
.p_1_in16_in(p_1_in16_in),
.p_1_in19_in(p_1_in19_in),
.p_1_in22_in(p_1_in22_in),
.p_1_in25_in(p_1_in25_in),
.p_1_in28_in(p_1_in28_in),
.p_1_in31_in(p_1_in31_in),
.p_1_in34_in(p_1_in34_in),
.p_2_in(p_2_in),
.rd_ce_or_reduce_core_cmb(rd_ce_or_reduce_core_cmb),
.rd_en(rd_en),
.receive_ip2bus_error(receive_ip2bus_error),
.reset2ip_reset_int(reset2ip_reset_int),
.reset_trig0(reset_trig0),
.rx_fifo_empty_i(rx_fifo_empty_i),
.s_axi4_aclk(s_axi4_aclk),
.s_axi4_araddr(s_axi4_araddr),
.s_axi4_aresetn(s_axi4_aresetn),
.s_axi4_arvalid(s_axi4_arvalid),
.s_axi4_awaddr(s_axi4_awaddr),
.s_axi4_awvalid(s_axi4_awvalid),
.\s_axi4_rdata_i_reg[8] (\s_axi4_rdata_i_reg[8]_0 ),
.s_axi4_rready(s_axi4_rready),
.\s_axi4_rresp_i_reg[1] (\s_axi4_rresp_i[1]_i_2_n_0 ),
.s_axi4_wdata({s_axi4_wdata[6:3],s_axi4_wdata[1:0]}),
.\s_axi4_wdata[31] (\s_axi4_wdata[31] ),
.s_axi4_wdata_0_sp_1(s_axi4_wdata_0_sn_1),
.s_axi4_wvalid(s_axi4_wvalid),
.s_axi4_wvalid_0(I_DECODER_n_15),
.s_axi_wready_i(s_axi_wready_i),
.scndry_out(scndry_out),
.spicr_0_loop_frm_axi_clk(spicr_0_loop_frm_axi_clk),
.spicr_1_spe_frm_axi_clk(spicr_1_spe_frm_axi_clk),
.spicr_2_mst_n_slv_frm_axi_clk(spicr_2_mst_n_slv_frm_axi_clk),
.spicr_3_cpol_frm_axi_clk(spicr_3_cpol_frm_axi_clk),
.spicr_4_cpha_frm_axi_clk(spicr_4_cpha_frm_axi_clk),
.spicr_5_txfifo_rst_frm_axi_clk(spicr_5_txfifo_rst_frm_axi_clk),
.spicr_6_rxfifo_rst_frm_axi_clk(spicr_6_rxfifo_rst_frm_axi_clk),
.spicr_7_ss_frm_axi_clk(spicr_7_ss_frm_axi_clk),
.spicr_8_tr_inhibit_frm_axi_clk(spicr_8_tr_inhibit_frm_axi_clk),
.spicr_9_lsb_frm_axi_clk(spicr_9_lsb_frm_axi_clk),
.spisel_d1_reg_to_axi_clk(spisel_d1_reg_to_axi_clk),
.start(start),
.sw_rst_cond(sw_rst_cond),
.sw_rst_cond_d1(sw_rst_cond_d1),
.transmit_ip2bus_error(transmit_ip2bus_error),
.wr_ce_or_reduce_core_cmb(wr_ce_or_reduce_core_cmb));
LUT2 #(
.INIT(4'hE))
RESET_SYNC_AX2S_1_i_1
(.I0(SR),
.I1(\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] ),
.O(reset2ip_reset_int));
LUT5 #(
.INIT(32'h0000ABA8))
\S_AXI4_BRESP_i[1]_i_1
(.I0(ip2bus_error_int),
.I1(\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ),
.I2(\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ),
.I3(s_axi4_bresp),
.I4(axi_full_sm_ps_IDLE_cmb),
.O(\S_AXI4_BRESP_i[1]_i_1_n_0 ));
FDRE \S_AXI4_BRESP_i_reg[1]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\S_AXI4_BRESP_i[1]_i_1_n_0 ),
.Q(s_axi4_bresp),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT2 #(
.INIT(4'h8))
arready_i_i_1
(.I0(axi_full_sm_ps_IDLE_cmb),
.I1(s_axi4_arvalid),
.O(arready_cmb));
FDRE arready_i_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(arready_cmb),
.Q(s_axi4_arready),
.R(SR));
LUT6 #(
.INIT(64'h88F8888888888888))
awready_i_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I1(\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ),
.I2(awready_i_i_3_n_0),
.I3(s_axi4_arvalid),
.I4(axi_full_sm_ps_IDLE_cmb),
.I5(burst_transfer_cmb),
.O(awready_cmb));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'h40))
awready_i_i_10
(.I0(s_axi4_awvalid),
.I1(axi_full_sm_ps_IDLE_cmb),
.I2(s_axi4_arvalid),
.O(awready_i_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT2 #(
.INIT(4'h8))
awready_i_i_3
(.I0(s_axi4_awvalid),
.I1(s_axi4_wvalid),
.O(awready_i_i_3_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
awready_i_i_4
(.I0(\length_cntr[3]_i_2_n_0 ),
.I1(awready_i_i_5_n_0),
.I2(awready_i_i_6_n_0),
.I3(awready_i_i_7_n_0),
.I4(awready_i_i_8_n_0),
.I5(awready_i_i_9_n_0),
.O(burst_transfer_cmb));
LUT6 #(
.INIT(64'hBBBBABBB8888A888))
awready_i_i_5
(.I0(s_axi4_arlen[2]),
.I1(\length_cntr[7]_i_5_n_0 ),
.I2(s_axi4_arvalid),
.I3(axi_full_sm_ps_IDLE_cmb),
.I4(s_axi4_awvalid),
.I5(s_axi4_awlen[2]),
.O(awready_i_i_5_n_0));
LUT6 #(
.INIT(64'hBBBBABBB8888A888))
awready_i_i_6
(.I0(s_axi4_arlen[5]),
.I1(\length_cntr[7]_i_5_n_0 ),
.I2(s_axi4_arvalid),
.I3(axi_full_sm_ps_IDLE_cmb),
.I4(s_axi4_awvalid),
.I5(s_axi4_awlen[5]),
.O(awready_i_i_6_n_0));
LUT6 #(
.INIT(64'hBBBBABBB8888A888))
awready_i_i_7
(.I0(s_axi4_arlen[0]),
.I1(\length_cntr[7]_i_5_n_0 ),
.I2(s_axi4_arvalid),
.I3(axi_full_sm_ps_IDLE_cmb),
.I4(s_axi4_awvalid),
.I5(s_axi4_awlen[0]),
.O(awready_i_i_7_n_0));
LUT6 #(
.INIT(64'hFFFFFFFACCCCCCFA))
awready_i_i_8
(.I0(s_axi4_awlen[4]),
.I1(s_axi4_arlen[4]),
.I2(s_axi4_awlen[1]),
.I3(awready_i_i_10_n_0),
.I4(\length_cntr[7]_i_5_n_0 ),
.I5(s_axi4_arlen[1]),
.O(awready_i_i_8_n_0));
LUT6 #(
.INIT(64'hFFFFFFFACCCCCCFA))
awready_i_i_9
(.I0(s_axi4_awlen[7]),
.I1(s_axi4_arlen[7]),
.I2(s_axi4_awlen[6]),
.I3(awready_i_i_10_n_0),
.I4(\length_cntr[7]_i_5_n_0 ),
.I5(s_axi4_arlen[6]),
.O(awready_i_i_9_n_0));
FDRE awready_i_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(awready_cmb),
.Q(s_axi4_awready),
.R(SR));
LUT4 #(
.INIT(16'hE200))
burst_transfer_reg_i_1
(.I0(burst_tr_int),
.I1(start),
.I2(burst_transfer_cmb),
.I3(s_axi4_aresetn),
.O(burst_transfer_reg_i_1_n_0));
FDRE burst_transfer_reg_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(burst_transfer_reg_i_1_n_0),
.Q(burst_tr_int),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT2 #(
.INIT(4'hE))
\bus2ip_BE_reg[0]_i_1
(.I0(s_axi4_wstrb[0]),
.I1(rnw_cmb),
.O(\bus2ip_BE_reg[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT2 #(
.INIT(4'hE))
\bus2ip_BE_reg[3]_i_1
(.I0(s_axi4_wstrb[1]),
.I1(rnw_cmb),
.O(\bus2ip_BE_reg[3]_i_1_n_0 ));
FDRE \bus2ip_BE_reg_reg[0]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\bus2ip_BE_reg[0]_i_1_n_0 ),
.Q(bus2ip_be_int[0]),
.R(SR));
FDRE \bus2ip_BE_reg_reg[3]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\bus2ip_BE_reg[3]_i_1_n_0 ),
.Q(bus2ip_be_int[3]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT2 #(
.INIT(4'h7))
last_data_acked_i_2
(.I0(s_axi4_rready),
.I1(s_axi4_rlast),
.O(last_data_acked_i_2_n_0));
LUT6 #(
.INIT(64'h0010000000000000))
last_data_acked_i_3
(.I0(last_data_acked_i_6_n_0),
.I1(last_data_acked_i_7_n_0),
.I2(length_cntr_reg[0]),
.I3(length_cntr_reg[1]),
.I4(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.I5(burst_tr_int),
.O(last_data_acked_i_3_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
last_data_acked_i_4
(.I0(burst_tr_int),
.I1(length_cntr_reg[4]),
.I2(length_cntr_reg[7]),
.I3(length_cntr_reg[5]),
.I4(length_cntr_reg[6]),
.I5(I_DECODER_n_24),
.O(last_data_acked_i_4_n_0));
LUT3 #(
.INIT(8'h40))
last_data_acked_i_5
(.I0(s_axi4_rready),
.I1(s_axi4_rlast),
.I2(burst_tr_int),
.O(last_data_acked_i_5_n_0));
LUT4 #(
.INIT(16'hFFFE))
last_data_acked_i_6
(.I0(length_cntr_reg[4]),
.I1(length_cntr_reg[7]),
.I2(length_cntr_reg[5]),
.I3(length_cntr_reg[6]),
.O(last_data_acked_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hEFFF))
last_data_acked_i_7
(.I0(length_cntr_reg[2]),
.I1(length_cntr_reg[3]),
.I2(s_axi_rvalid_i_reg_0),
.I3(s_axi4_rready),
.O(last_data_acked_i_7_n_0));
FDRE last_data_acked_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(I_DECODER_n_13),
.Q(s_axi4_rlast),
.R(1'b0));
LUT5 #(
.INIT(32'hB800B8FF))
\length_cntr[0]_i_1
(.I0(s_axi4_arlen[0]),
.I1(rnw_cmb),
.I2(s_axi4_awlen[0]),
.I3(start),
.I4(length_cntr_reg[0]),
.O(p_0_in__0[0]));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\length_cntr[1]_i_1
(.I0(s_axi4_arlen[1]),
.I1(rnw_cmb),
.I2(s_axi4_awlen[1]),
.I3(start),
.I4(length_cntr_reg[1]),
.I5(length_cntr_reg[0]),
.O(p_0_in__0[1]));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\length_cntr[2]_i_1
(.I0(s_axi4_arlen[2]),
.I1(rnw_cmb),
.I2(s_axi4_awlen[2]),
.I3(start),
.I4(length_cntr_reg[2]),
.I5(\length_cntr[2]_i_2_n_0 ),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT2 #(
.INIT(4'h1))
\length_cntr[2]_i_2
(.I0(length_cntr_reg[1]),
.I1(length_cntr_reg[0]),
.O(\length_cntr[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B8B88B))
\length_cntr[3]_i_1
(.I0(\length_cntr[3]_i_2_n_0 ),
.I1(start),
.I2(length_cntr_reg[3]),
.I3(length_cntr_reg[2]),
.I4(length_cntr_reg[1]),
.I5(length_cntr_reg[0]),
.O(p_0_in__0[3]));
LUT6 #(
.INIT(64'hBBBBABBB8888A888))
\length_cntr[3]_i_2
(.I0(s_axi4_arlen[3]),
.I1(\length_cntr[7]_i_5_n_0 ),
.I2(s_axi4_arvalid),
.I3(axi_full_sm_ps_IDLE_cmb),
.I4(s_axi4_awvalid),
.I5(s_axi4_awlen[3]),
.O(\length_cntr[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\length_cntr[4]_i_1
(.I0(s_axi4_arlen[4]),
.I1(rnw_cmb),
.I2(s_axi4_awlen[4]),
.I3(start),
.I4(length_cntr_reg[4]),
.I5(I_DECODER_n_24),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\length_cntr[5]_i_1
(.I0(s_axi4_arlen[5]),
.I1(rnw_cmb),
.I2(s_axi4_awlen[5]),
.I3(start),
.I4(length_cntr_reg[5]),
.I5(\length_cntr[7]_i_4_n_0 ),
.O(p_0_in__0[5]));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\length_cntr[6]_i_1
(.I0(s_axi4_arlen[6]),
.I1(rnw_cmb),
.I2(s_axi4_awlen[6]),
.I3(start),
.I4(length_cntr_reg[6]),
.I5(\length_cntr[6]_i_2_n_0 ),
.O(p_0_in__0[6]));
LUT6 #(
.INIT(64'h0000000000000001))
\length_cntr[6]_i_2
(.I0(length_cntr_reg[2]),
.I1(length_cntr_reg[3]),
.I2(length_cntr_reg[0]),
.I3(length_cntr_reg[1]),
.I4(length_cntr_reg[4]),
.I5(length_cntr_reg[5]),
.O(\length_cntr[6]_i_2_n_0 ));
LUT4 #(
.INIT(16'hF8FF))
\length_cntr[7]_i_1
(.I0(s_axi4_rready),
.I1(s_axi_rvalid_i_reg_0),
.I2(start),
.I3(\xpm_fifo_instance.xpm_fifo_async_inst_i_4_n_0 ),
.O(\length_cntr[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B88BB8))
\length_cntr[7]_i_2
(.I0(\length_cntr[7]_i_3_n_0 ),
.I1(start),
.I2(length_cntr_reg[7]),
.I3(\length_cntr[7]_i_4_n_0 ),
.I4(length_cntr_reg[6]),
.I5(length_cntr_reg[5]),
.O(p_0_in__0[7]));
LUT6 #(
.INIT(64'hBBBBABBB8888A888))
\length_cntr[7]_i_3
(.I0(s_axi4_arlen[7]),
.I1(\length_cntr[7]_i_5_n_0 ),
.I2(s_axi4_arvalid),
.I3(axi_full_sm_ps_IDLE_cmb),
.I4(s_axi4_awvalid),
.I5(s_axi4_awlen[7]),
.O(\length_cntr[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT5 #(
.INIT(32'h00000001))
\length_cntr[7]_i_4
(.I0(length_cntr_reg[4]),
.I1(length_cntr_reg[1]),
.I2(length_cntr_reg[0]),
.I3(length_cntr_reg[3]),
.I4(length_cntr_reg[2]),
.O(\length_cntr[7]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\length_cntr[7]_i_5
(.I0(rnw_reg_reg_n_0),
.I1(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.I2(Q),
.I3(\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ),
.I4(\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ),
.O(\length_cntr[7]_i_5_n_0 ));
FDRE \length_cntr_reg[0]
(.C(s_axi4_aclk),
.CE(\length_cntr[7]_i_1_n_0 ),
.D(p_0_in__0[0]),
.Q(length_cntr_reg[0]),
.R(clear));
FDRE \length_cntr_reg[1]
(.C(s_axi4_aclk),
.CE(\length_cntr[7]_i_1_n_0 ),
.D(p_0_in__0[1]),
.Q(length_cntr_reg[1]),
.R(clear));
FDRE \length_cntr_reg[2]
(.C(s_axi4_aclk),
.CE(\length_cntr[7]_i_1_n_0 ),
.D(p_0_in__0[2]),
.Q(length_cntr_reg[2]),
.R(clear));
FDRE \length_cntr_reg[3]
(.C(s_axi4_aclk),
.CE(\length_cntr[7]_i_1_n_0 ),
.D(p_0_in__0[3]),
.Q(length_cntr_reg[3]),
.R(clear));
FDRE \length_cntr_reg[4]
(.C(s_axi4_aclk),
.CE(\length_cntr[7]_i_1_n_0 ),
.D(p_0_in__0[4]),
.Q(length_cntr_reg[4]),
.R(clear));
FDRE \length_cntr_reg[5]
(.C(s_axi4_aclk),
.CE(\length_cntr[7]_i_1_n_0 ),
.D(p_0_in__0[5]),
.Q(length_cntr_reg[5]),
.R(clear));
FDRE \length_cntr_reg[6]
(.C(s_axi4_aclk),
.CE(\length_cntr[7]_i_1_n_0 ),
.D(p_0_in__0[6]),
.Q(length_cntr_reg[6]),
.R(clear));
FDRE \length_cntr_reg[7]
(.C(s_axi4_aclk),
.CE(\length_cntr[7]_i_1_n_0 ),
.D(p_0_in__0[7]),
.Q(length_cntr_reg[7]),
.R(clear));
LUT6 #(
.INIT(64'hFD00FD00FD00FFFF))
rnw_reg_i_1
(.I0(rnw_reg_i_2_n_0),
.I1(Q),
.I2(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.I3(rnw_reg_reg_n_0),
.I4(rnw_reg_i_3_n_0),
.I5(s_axi4_awvalid),
.O(rnw_cmb));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT2 #(
.INIT(4'h1))
rnw_reg_i_2
(.I0(\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ),
.I1(\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ),
.O(rnw_reg_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT2 #(
.INIT(4'h7))
rnw_reg_i_3
(.I0(s_axi4_arvalid),
.I1(axi_full_sm_ps_IDLE_cmb),
.O(rnw_reg_i_3_n_0));
FDRE rnw_reg_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(rnw_cmb),
.Q(rnw_reg_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
\s_axi4_rdata_i[31]_i_1
(.I0(s_axi4_aresetn),
.O(clear));
FDRE \s_axi4_rdata_i_reg[0]
(.C(s_axi4_aclk),
.CE(E),
.D(D[0]),
.Q(s_axi4_rdata[0]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[1]
(.C(s_axi4_aclk),
.CE(E),
.D(D[1]),
.Q(s_axi4_rdata[1]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[2]
(.C(s_axi4_aclk),
.CE(E),
.D(D[2]),
.Q(s_axi4_rdata[2]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[31]
(.C(s_axi4_aclk),
.CE(E),
.D(\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/intr_ip2bus_data ),
.Q(s_axi4_rdata[10]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[3]
(.C(s_axi4_aclk),
.CE(E),
.D(D[3]),
.Q(s_axi4_rdata[3]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[4]
(.C(s_axi4_aclk),
.CE(E),
.D(D[4]),
.Q(s_axi4_rdata[4]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[5]
(.C(s_axi4_aclk),
.CE(E),
.D(D[5]),
.Q(s_axi4_rdata[5]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[6]
(.C(s_axi4_aclk),
.CE(E),
.D(D[6]),
.Q(s_axi4_rdata[6]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[7]
(.C(s_axi4_aclk),
.CE(E),
.D(D[7]),
.Q(s_axi4_rdata[7]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[8]
(.C(s_axi4_aclk),
.CE(E),
.D(ip2bus_data_int),
.Q(s_axi4_rdata[8]),
.R(clear));
FDRE \s_axi4_rdata_i_reg[9]
(.C(s_axi4_aclk),
.CE(E),
.D(\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/IP2Bus_SPICR_Data_int ),
.Q(s_axi4_rdata[9]),
.R(clear));
LUT5 #(
.INIT(32'hFFFFDFFF))
\s_axi4_rresp_i[1]_i_2
(.I0(bus2ip_be_int[0]),
.I1(s_axi4_wdata[0]),
.I2(s_axi4_wdata[3]),
.I3(s_axi4_wdata[1]),
.I4(s_axi4_wdata[2]),
.O(\s_axi4_rresp_i[1]_i_2_n_0 ));
FDRE \s_axi4_rresp_i_reg[1]
(.C(s_axi4_aclk),
.CE(E),
.D(ip2bus_error_int),
.Q(s_axi4_rresp),
.R(clear));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'h72))
s_axi4_wready_INST_0
(.I0(\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ),
.I1(almost_full),
.I2(s_axi_wready_i),
.O(s_axi4_wready));
LUT4 #(
.INIT(16'hF200))
s_axi_bvalid_i_i_1
(.I0(s_axi4_bvalid),
.I1(s_axi4_bready),
.I2(\FSM_onehot_axi_full_sm_ps_reg_n_0_[6] ),
.I3(s_axi4_aresetn),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE s_axi_bvalid_i_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi4_bvalid),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFF222F))
s_axi_rvalid_i_i_1
(.I0(s_axi_rvalid_i_reg_0),
.I1(s_axi4_rready),
.I2(s_axi_rvalid_i_reg_1),
.I3(s_axi_rvalid_i_i_2_n_0),
.I4(I_DECODER_n_14),
.I5(axi_full_sm_ps_IDLE_cmb),
.O(s_axi_rvalid_i_i_1_n_0));
LUT6 #(
.INIT(64'h5555555555555557))
s_axi_rvalid_i_i_2
(.I0(\FSM_onehot_axi_full_sm_ps_reg_n_0_[1] ),
.I1(length_cntr_reg[4]),
.I2(length_cntr_reg[7]),
.I3(length_cntr_reg[5]),
.I4(length_cntr_reg[6]),
.I5(I_DECODER_n_24),
.O(s_axi_rvalid_i_i_2_n_0));
FDRE s_axi_rvalid_i_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid_i_reg_0),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFF8F8800000000))
s_axi_wready_i_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I1(\FSM_onehot_axi_full_sm_ps_reg_n_0_[5] ),
.I2(s_axi_wready_i_i_2_n_0),
.I3(burst_transfer_cmb),
.I4(\FSM_onehot_axi_full_sm_ps[4]_i_2_n_0 ),
.I5(s_axi4_aresetn),
.O(s_axi_wready_i_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'hF7FF))
s_axi_wready_i_i_2
(.I0(s_axi4_wvalid),
.I1(s_axi4_awvalid),
.I2(s_axi4_arvalid),
.I3(axi_full_sm_ps_IDLE_cmb),
.O(s_axi_wready_i_i_2_n_0));
FDRE s_axi_wready_i_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(s_axi_wready_i_i_1_n_0),
.Q(s_axi_wready_i),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'h8DFF))
\xpm_fifo_instance.xpm_fifo_async_inst_i_4
(.I0(\FSM_onehot_axi_full_sm_ps_reg_n_0_[4] ),
.I1(almost_full),
.I2(s_axi_wready_i),
.I3(s_axi4_wvalid),
.O(\xpm_fifo_instance.xpm_fifo_async_inst_i_4_n_0 ));
endmodule
(* Async_Clk = "0" *) (* C_BYTE_LEVEL_INTERRUPT_EN = "0" *) (* C_DUAL_QUAD_MODE = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FIFO_DEPTH = "256" *) (* C_INSTANCE = "axi_quad_spi_inst" *)
(* C_LSB_STUP = "0" *) (* C_NEW_SEQ_EN = "1" *) (* C_NUM_SS_BITS = "1" *)
(* C_NUM_TRANSFER_BITS = "8" *) (* C_SCK_RATIO = "4" *) (* C_SELECT_XPM = "0" *)
(* C_SHARED_STARTUP = "0" *) (* C_SPI_MEMORY = "1" *) (* C_SPI_MEM_ADDR_BITS = "24" *)
(* C_SPI_MODE = "0" *) (* C_SUB_FAMILY = "kintex7" *) (* C_S_AXI4_ADDR_WIDTH = "24" *)
(* C_S_AXI4_BASEADDR = "-1" *) (* C_S_AXI4_DATA_WIDTH = "32" *) (* C_S_AXI4_HIGHADDR = "0" *)
(* C_S_AXI4_ID_WIDTH = "1" *) (* C_S_AXI_ADDR_WIDTH = "7" *) (* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TYPE_OF_AXI4_INTERFACE = "1" *) (* C_UC_FAMILY = "0" *) (* C_USE_STARTUP = "0" *)
(* C_USE_STARTUP_EXT = "0" *) (* C_XIP_MODE = "0" *) (* C_XIP_PERF_MODE = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi
(ext_spi_clk,
s_axi_aclk,
s_axi_aresetn,
s_axi4_aclk,
s_axi4_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
s_axi4_awid,
s_axi4_awaddr,
s_axi4_awlen,
s_axi4_awsize,
s_axi4_awburst,
s_axi4_awlock,
s_axi4_awcache,
s_axi4_awprot,
s_axi4_awvalid,
s_axi4_awready,
s_axi4_wdata,
s_axi4_wstrb,
s_axi4_wlast,
s_axi4_wvalid,
s_axi4_wready,
s_axi4_bid,
s_axi4_bresp,
s_axi4_bvalid,
s_axi4_bready,
s_axi4_arid,
s_axi4_araddr,
s_axi4_arlen,
s_axi4_arsize,
s_axi4_arburst,
s_axi4_arlock,
s_axi4_arcache,
s_axi4_arprot,
s_axi4_arvalid,
s_axi4_arready,
s_axi4_rid,
s_axi4_rdata,
s_axi4_rresp,
s_axi4_rlast,
s_axi4_rvalid,
s_axi4_rready,
io0_i,
io0_o,
io0_t,
io1_i,
io1_o,
io1_t,
io2_i,
io2_o,
io2_t,
io3_i,
io3_o,
io3_t,
io0_1_i,
io0_1_o,
io0_1_t,
io1_1_i,
io1_1_o,
io1_1_t,
io2_1_i,
io2_1_o,
io2_1_t,
io3_1_i,
io3_1_o,
io3_1_t,
spisel,
sck_i,
sck_o,
sck_t,
ss_i,
ss_o,
ss_t,
ss_1_i,
ss_1_o,
ss_1_t,
cfgclk,
cfgmclk,
eos,
preq,
clk,
gsr,
gts,
keyclearb,
usrcclkts,
usrdoneo,
usrdonets,
pack,
ip2intc_irpt);
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi4_aclk;
input s_axi4_aresetn;
input [6:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [6:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [0:0]s_axi4_awid;
input [23:0]s_axi4_awaddr;
input [7:0]s_axi4_awlen;
input [2:0]s_axi4_awsize;
input [1:0]s_axi4_awburst;
input s_axi4_awlock;
input [3:0]s_axi4_awcache;
input [2:0]s_axi4_awprot;
input s_axi4_awvalid;
output s_axi4_awready;
input [31:0]s_axi4_wdata;
input [3:0]s_axi4_wstrb;
input s_axi4_wlast;
input s_axi4_wvalid;
output s_axi4_wready;
output [0:0]s_axi4_bid;
output [1:0]s_axi4_bresp;
output s_axi4_bvalid;
input s_axi4_bready;
input [0:0]s_axi4_arid;
input [23:0]s_axi4_araddr;
input [7:0]s_axi4_arlen;
input [2:0]s_axi4_arsize;
input [1:0]s_axi4_arburst;
input s_axi4_arlock;
input [3:0]s_axi4_arcache;
input [2:0]s_axi4_arprot;
input s_axi4_arvalid;
output s_axi4_arready;
output [0:0]s_axi4_rid;
output [31:0]s_axi4_rdata;
output [1:0]s_axi4_rresp;
output s_axi4_rlast;
output s_axi4_rvalid;
input s_axi4_rready;
input io0_i;
output io0_o;
output io0_t;
input io1_i;
output io1_o;
output io1_t;
input io2_i;
output io2_o;
output io2_t;
input io3_i;
output io3_o;
output io3_t;
input io0_1_i;
output io0_1_o;
output io0_1_t;
input io1_1_i;
output io1_1_o;
output io1_1_t;
input io2_1_i;
output io2_1_o;
output io2_1_t;
input io3_1_i;
output io3_1_o;
output io3_1_t;
(* initialval = "VCC" *) input spisel;
input sck_i;
output sck_o;
output sck_t;
input [0:0]ss_i;
output [0:0]ss_o;
output ss_t;
input ss_1_i;
output ss_1_o;
output ss_1_t;
output cfgclk;
output cfgmclk;
output eos;
output preq;
input clk;
input gsr;
input gts;
input keyclearb;
input usrcclkts;
input usrdoneo;
input usrdonets;
input pack;
output ip2intc_irpt;
wire \<const0> ;
wire ext_spi_clk;
wire io0_i;
wire io0_t;
wire io1_i;
wire io1_o;
wire io1_t;
wire ip2intc_irpt;
wire s_axi4_aclk;
wire [23:0]s_axi4_araddr;
wire s_axi4_aresetn;
wire [7:0]s_axi4_arlen;
wire s_axi4_arready;
wire s_axi4_arvalid;
wire [23:0]s_axi4_awaddr;
wire [7:0]s_axi4_awlen;
wire s_axi4_awready;
wire s_axi4_awvalid;
wire s_axi4_bready;
wire [1:1]\^s_axi4_bresp ;
wire s_axi4_bvalid;
wire [31:0]\^s_axi4_rdata ;
wire s_axi4_rlast;
wire s_axi4_rready;
wire [1:1]\^s_axi4_rresp ;
wire s_axi4_rvalid;
wire [31:0]s_axi4_wdata;
wire s_axi4_wready;
wire [3:0]s_axi4_wstrb;
wire s_axi4_wvalid;
wire sck_o;
wire sck_t;
wire [0:0]ss_o;
wire ss_t;
assign cfgclk = \<const0> ;
assign cfgmclk = \<const0> ;
assign eos = \<const0> ;
assign io0_1_o = \<const0> ;
assign io0_1_t = \<const0> ;
assign io0_o = io1_o;
assign io1_1_o = \<const0> ;
assign io1_1_t = \<const0> ;
assign io2_1_o = \<const0> ;
assign io2_1_t = \<const0> ;
assign io2_o = \<const0> ;
assign io2_t = \<const0> ;
assign io3_1_o = \<const0> ;
assign io3_1_t = \<const0> ;
assign io3_o = \<const0> ;
assign io3_t = \<const0> ;
assign preq = \<const0> ;
assign s_axi4_bid[0] = \<const0> ;
assign s_axi4_bresp[1] = \^s_axi4_bresp [1];
assign s_axi4_bresp[0] = \<const0> ;
assign s_axi4_rdata[31] = \^s_axi4_rdata [31];
assign s_axi4_rdata[30] = \<const0> ;
assign s_axi4_rdata[29] = \<const0> ;
assign s_axi4_rdata[28] = \<const0> ;
assign s_axi4_rdata[27] = \<const0> ;
assign s_axi4_rdata[26] = \<const0> ;
assign s_axi4_rdata[25] = \<const0> ;
assign s_axi4_rdata[24] = \<const0> ;
assign s_axi4_rdata[23] = \<const0> ;
assign s_axi4_rdata[22] = \<const0> ;
assign s_axi4_rdata[21] = \<const0> ;
assign s_axi4_rdata[20] = \<const0> ;
assign s_axi4_rdata[19] = \<const0> ;
assign s_axi4_rdata[18] = \<const0> ;
assign s_axi4_rdata[17] = \<const0> ;
assign s_axi4_rdata[16] = \<const0> ;
assign s_axi4_rdata[15] = \<const0> ;
assign s_axi4_rdata[14] = \<const0> ;
assign s_axi4_rdata[13] = \<const0> ;
assign s_axi4_rdata[12] = \<const0> ;
assign s_axi4_rdata[11] = \<const0> ;
assign s_axi4_rdata[10] = \<const0> ;
assign s_axi4_rdata[9:0] = \^s_axi4_rdata [9:0];
assign s_axi4_rid[0] = \<const0> ;
assign s_axi4_rresp[1] = \^s_axi4_rresp [1];
assign s_axi4_rresp[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign ss_1_o = \<const0> ;
assign ss_1_t = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi_top \NO_DUAL_QUAD_MODE.QSPI_NORMAL
(.ext_spi_clk(ext_spi_clk),
.io0_i(io0_i),
.io0_t(io0_t),
.io1_i(io1_i),
.io1_o(io1_o),
.io1_t(io1_t),
.ip2intc_irpt(ip2intc_irpt),
.s_axi4_aclk(s_axi4_aclk),
.s_axi4_araddr(s_axi4_araddr[6:2]),
.s_axi4_aresetn(s_axi4_aresetn),
.s_axi4_arlen(s_axi4_arlen),
.s_axi4_arready(s_axi4_arready),
.s_axi4_arvalid(s_axi4_arvalid),
.s_axi4_awaddr(s_axi4_awaddr[6:2]),
.s_axi4_awlen(s_axi4_awlen),
.s_axi4_awready(s_axi4_awready),
.s_axi4_awvalid(s_axi4_awvalid),
.s_axi4_bready(s_axi4_bready),
.s_axi4_bresp(\^s_axi4_bresp ),
.s_axi4_bvalid(s_axi4_bvalid),
.s_axi4_rdata({\^s_axi4_rdata [31],\^s_axi4_rdata [9:0]}),
.s_axi4_rlast(s_axi4_rlast),
.s_axi4_rready(s_axi4_rready),
.s_axi4_rresp(\^s_axi4_rresp ),
.s_axi4_wdata({s_axi4_wdata[31],s_axi4_wdata[9:0]}),
.s_axi4_wready(s_axi4_wready),
.s_axi4_wstrb({s_axi4_wstrb[3],s_axi4_wstrb[0]}),
.s_axi4_wvalid(s_axi4_wvalid),
.s_axi_rvalid_i_reg(s_axi4_rvalid),
.sck_o(sck_o),
.sck_t(sck_t),
.ss_o(ss_o),
.ss_t(ss_t));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi_top
(s_axi4_rlast,
sck_t,
io0_t,
ss_t,
io1_t,
sck_o,
s_axi_rvalid_i_reg,
s_axi4_awready,
s_axi4_bresp,
s_axi4_arready,
s_axi4_rdata,
s_axi4_rresp,
s_axi4_wready,
ip2intc_irpt,
io1_o,
s_axi4_bvalid,
ss_o,
s_axi4_araddr,
s_axi4_arvalid,
s_axi4_awaddr,
s_axi4_rready,
s_axi4_aclk,
ext_spi_clk,
s_axi4_wdata,
io0_i,
io1_i,
s_axi4_bready,
s_axi4_awvalid,
s_axi4_wvalid,
s_axi4_arlen,
s_axi4_awlen,
s_axi4_aresetn,
s_axi4_wstrb);
output s_axi4_rlast;
output sck_t;
output io0_t;
output ss_t;
output io1_t;
output sck_o;
output s_axi_rvalid_i_reg;
output s_axi4_awready;
output [0:0]s_axi4_bresp;
output s_axi4_arready;
output [10:0]s_axi4_rdata;
output [0:0]s_axi4_rresp;
output s_axi4_wready;
output ip2intc_irpt;
output io1_o;
output s_axi4_bvalid;
output [0:0]ss_o;
input [4:0]s_axi4_araddr;
input s_axi4_arvalid;
input [4:0]s_axi4_awaddr;
input s_axi4_rready;
input s_axi4_aclk;
input ext_spi_clk;
input [10:0]s_axi4_wdata;
input io0_i;
input io1_i;
input s_axi4_bready;
input s_axi4_awvalid;
input s_axi4_wvalid;
input [7:0]s_axi4_arlen;
input [7:0]s_axi4_awlen;
input s_axi4_aresetn;
input [1:0]s_axi4_wstrb;
wire \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0 ;
wire \INTERRUPT_CONTROL_I/interrupt_wrce_strb ;
wire \INTERRUPT_CONTROL_I/intr2bus_rdack0 ;
wire \INTERRUPT_CONTROL_I/irpt_rdack ;
wire \INTERRUPT_CONTROL_I/irpt_rdack_d1 ;
wire \INTERRUPT_CONTROL_I/irpt_wrack ;
wire \INTERRUPT_CONTROL_I/irpt_wrack_d1 ;
wire [31:31]\INTERRUPT_CONTROL_I/p_0_in ;
wire \INTERRUPT_CONTROL_I/p_0_in0_in ;
wire \INTERRUPT_CONTROL_I/p_0_in11_in ;
wire \INTERRUPT_CONTROL_I/p_0_in14_in ;
wire \INTERRUPT_CONTROL_I/p_0_in17_in ;
wire \INTERRUPT_CONTROL_I/p_0_in20_in ;
wire \INTERRUPT_CONTROL_I/p_0_in2_in ;
wire \INTERRUPT_CONTROL_I/p_0_in5_in ;
wire \INTERRUPT_CONTROL_I/p_0_in8_in ;
wire \INTERRUPT_CONTROL_I/p_1_in13_in ;
wire \INTERRUPT_CONTROL_I/p_1_in16_in ;
wire \INTERRUPT_CONTROL_I/p_1_in19_in ;
wire \INTERRUPT_CONTROL_I/p_1_in22_in ;
wire \INTERRUPT_CONTROL_I/p_1_in25_in ;
wire \INTERRUPT_CONTROL_I/p_1_in28_in ;
wire \INTERRUPT_CONTROL_I/p_1_in31_in ;
wire \INTERRUPT_CONTROL_I/p_1_in34_in ;
wire IP2Bus_WrAck_transmit_enable;
wire \I_DECODER/Bus_RNW_reg ;
wire \I_DECODER/p_1_in ;
wire \I_DECODER/p_2_in ;
wire \I_DECODER/p_4_in ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_23 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_38 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_46 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_48 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_57 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_68 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_12 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_13 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_14 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_15 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_21 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_22 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_29 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_31 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_35 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_36 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_37 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_38 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_39 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_40 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_41 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_44 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_45 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_46 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_47 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_50 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_51 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_52 ;
wire \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_53 ;
wire Rx_FIFO_Empty;
wire Rx_FIFO_Full_Fifo_d1_synced;
wire \SOFT_RESET_I/reset_trig0 ;
wire \SOFT_RESET_I/sw_rst_cond ;
wire \SOFT_RESET_I/sw_rst_cond_d1 ;
wire SPISSR_frm_axi_clk;
wire TX_Fifo_full_indication;
wire Tx_FIFO_Empty_SPISR_to_axi_clk;
wire Tx_FIFO_Full_int;
wire burst_tr_int;
wire bus2ip_reset_ipif_inverted;
wire [7:7]bus2ip_wrce_int;
wire data_valid;
wire ext_spi_clk;
wire intr_controller_rd_ce_or_reduce;
wire io0_i;
wire io0_i_sync;
wire io0_t;
wire io1_i;
wire io1_i_sync;
wire io1_o;
wire io1_t;
wire ip2Bus_RdAck_core_reg;
wire ip2Bus_RdAck_intr_reg_hole0;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_core_reg;
wire ip2Bus_WrAck_core_reg0;
wire ip2Bus_WrAck_core_reg_d1;
wire ip2Bus_WrAck_intr_reg_hole0;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [7:0]ip2bus_data_int;
wire ip2bus_error_int;
wire ip2intc_irpt;
wire rd_ce_or_reduce_core_cmb;
wire rd_en;
wire receive_ip2bus_error;
wire reset2ip_reset_int;
wire rx_fifo_empty_i;
wire s_axi4_aclk;
wire [4:0]s_axi4_araddr;
wire s_axi4_aresetn;
wire [7:0]s_axi4_arlen;
wire s_axi4_arready;
wire s_axi4_arvalid;
wire [4:0]s_axi4_awaddr;
wire [7:0]s_axi4_awlen;
wire s_axi4_awready;
wire s_axi4_awvalid;
wire s_axi4_bready;
wire [0:0]s_axi4_bresp;
wire s_axi4_bvalid;
wire [10:0]s_axi4_rdata;
wire s_axi4_rlast;
wire s_axi4_rready;
wire [0:0]s_axi4_rresp;
wire s_axi4_rresp_i0;
wire [10:0]s_axi4_wdata;
wire s_axi4_wready;
wire [1:0]s_axi4_wstrb;
wire s_axi4_wvalid;
wire s_axi_rvalid_i_reg;
wire sck_o;
wire sck_t;
wire spicr_0_loop_frm_axi_clk;
wire spicr_1_spe_frm_axi_clk;
wire spicr_2_mst_n_slv_frm_axi_clk;
wire spicr_3_cpol_frm_axi_clk;
wire spicr_4_cpha_frm_axi_clk;
wire spicr_5_txfifo_rst_frm_axi_clk;
wire spicr_6_rxfifo_rst_frm_axi_clk;
wire spicr_7_ss_frm_axi_clk;
wire spicr_8_tr_inhibit_frm_axi_clk;
wire spicr_9_lsb_frm_axi_clk;
wire spisel_d1_reg_to_axi_clk;
wire [0:0]ss_o;
wire ss_t;
wire transmit_ip2bus_error;
wire wr_ce_or_reduce_core_cmb;
(* XILINX_LEGACY_PRIM = "FD" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
IO0_I_REG
(.C(ext_spi_clk),
.CE(1'b1),
.D(io0_i),
.Q(io0_i_sync),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "FD" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
IO1_I_REG
(.C(ext_spi_clk),
.CE(1'b1),
.D(io1_i),
.Q(io1_i_sync),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_core_interface \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I
(.Bus_RNW_reg(\I_DECODER/Bus_RNW_reg ),
.\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_52 ),
.\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_53 ),
.\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_12 ),
.D(ip2bus_data_int),
.E(s_axi4_rresp_i0),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_23 ),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_46 ),
.\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_45 ),
.\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_44 ),
.\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_47 ),
.IP2Bus_WrAck_transmit_enable(IP2Bus_WrAck_transmit_enable),
.Q(\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_21 ),
.\RESET_FLOPS[15].RST_FLOPS (\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_38 ),
.\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_50 ),
.SPISSR_frm_axi_clk(SPISSR_frm_axi_clk),
.Transmit_ip2bus_error0(\FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0 ),
.Tx_FIFO_Empty_SPISR_to_axi_clk(Tx_FIFO_Empty_SPISR_to_axi_clk),
.Tx_FIFO_Full_int(Tx_FIFO_Full_int),
.almost_full(TX_Fifo_full_indication),
.burst_tr_int(burst_tr_int),
.bus2ip_reset_ipif_inverted(bus2ip_reset_ipif_inverted),
.bus2ip_wrce_int(bus2ip_wrce_int),
.data_valid(data_valid),
.empty(Rx_FIFO_Empty),
.ext_spi_clk(ext_spi_clk),
.\gen_fwft.gdvld_fwft.data_valid_fwft_reg (\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_48 ),
.interrupt_wrce_strb(\INTERRUPT_CONTROL_I/interrupt_wrce_strb ),
.intr2bus_rdack0(\INTERRUPT_CONTROL_I/intr2bus_rdack0 ),
.intr2bus_rdack_reg(\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_57 ),
.intr2bus_wrack_reg(\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_46 ),
.intr_controller_rd_ce_or_reduce(intr_controller_rd_ce_or_reduce),
.io0_i_sync(io0_i_sync),
.io0_t(io0_t),
.io1_i_sync(io1_i_sync),
.io1_o(io1_o),
.io1_t(io1_t),
.ip2Bus_RdAck_core_reg(ip2Bus_RdAck_core_reg),
.ip2Bus_RdAck_intr_reg_hole0(ip2Bus_RdAck_intr_reg_hole0),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_core_reg(ip2Bus_WrAck_core_reg),
.ip2Bus_WrAck_core_reg0(ip2Bus_WrAck_core_reg0),
.ip2Bus_WrAck_core_reg_d1(ip2Bus_WrAck_core_reg_d1),
.ip2Bus_WrAck_intr_reg_hole0(ip2Bus_WrAck_intr_reg_hole0),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1_reg_0(\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_14 ),
.ip2bus_error_int(ip2bus_error_int),
.ip2intc_irpt(ip2intc_irpt),
.\ip_irpt_enable_reg_reg[8] ({\INTERRUPT_CONTROL_I/p_0_in20_in ,\INTERRUPT_CONTROL_I/p_0_in17_in ,\INTERRUPT_CONTROL_I/p_0_in14_in ,\INTERRUPT_CONTROL_I/p_0_in11_in ,\INTERRUPT_CONTROL_I/p_0_in8_in ,\INTERRUPT_CONTROL_I/p_0_in5_in ,\INTERRUPT_CONTROL_I/p_0_in2_in ,\INTERRUPT_CONTROL_I/p_0_in0_in ,\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_68 }),
.\ip_irpt_enable_reg_reg[8]_0 (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_13 ),
.ipif_glbl_irpt_enable_reg_reg(\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_51 ),
.irpt_rdack(\INTERRUPT_CONTROL_I/irpt_rdack ),
.irpt_rdack_d1(\INTERRUPT_CONTROL_I/irpt_rdack_d1 ),
.irpt_wrack(\INTERRUPT_CONTROL_I/irpt_wrack ),
.irpt_wrack_d1(\INTERRUPT_CONTROL_I/irpt_wrack_d1 ),
.p_0_in(\INTERRUPT_CONTROL_I/p_0_in ),
.p_1_in(\I_DECODER/p_1_in ),
.p_1_in13_in(\INTERRUPT_CONTROL_I/p_1_in13_in ),
.p_1_in16_in(\INTERRUPT_CONTROL_I/p_1_in16_in ),
.p_1_in19_in(\INTERRUPT_CONTROL_I/p_1_in19_in ),
.p_1_in22_in(\INTERRUPT_CONTROL_I/p_1_in22_in ),
.p_1_in25_in(\INTERRUPT_CONTROL_I/p_1_in25_in ),
.p_1_in28_in(\INTERRUPT_CONTROL_I/p_1_in28_in ),
.p_1_in31_in(\INTERRUPT_CONTROL_I/p_1_in31_in ),
.p_1_in34_in(\INTERRUPT_CONTROL_I/p_1_in34_in ),
.p_2_in(\I_DECODER/p_2_in ),
.p_4_in(\I_DECODER/p_4_in ),
.rd_ce_or_reduce_core_cmb(rd_ce_or_reduce_core_cmb),
.rd_en(rd_en),
.receive_ip2bus_error(receive_ip2bus_error),
.reset2ip_reset_int(reset2ip_reset_int),
.reset_trig0(\SOFT_RESET_I/reset_trig0 ),
.rx_fifo_empty_i(rx_fifo_empty_i),
.s_axi4_aclk(s_axi4_aclk),
.\s_axi4_rdata_i_reg[0] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_31 ),
.\s_axi4_rdata_i_reg[1] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_35 ),
.\s_axi4_rdata_i_reg[2] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_36 ),
.\s_axi4_rdata_i_reg[31] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_22 ),
.\s_axi4_rdata_i_reg[3] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_37 ),
.\s_axi4_rdata_i_reg[4] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_38 ),
.\s_axi4_rdata_i_reg[5] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_39 ),
.\s_axi4_rdata_i_reg[5]_0 (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_15 ),
.\s_axi4_rdata_i_reg[6] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_40 ),
.\s_axi4_rdata_i_reg[7] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_29 ),
.\s_axi4_rdata_i_reg[7]_0 (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_41 ),
.s_axi4_rready(s_axi4_rready),
.s_axi4_wdata(s_axi4_wdata[9:0]),
.sck_o(sck_o),
.sck_t(sck_t),
.scndry_out(Rx_FIFO_Full_Fifo_d1_synced),
.spicr_0_loop_frm_axi_clk(spicr_0_loop_frm_axi_clk),
.spicr_1_spe_frm_axi_clk(spicr_1_spe_frm_axi_clk),
.spicr_2_mst_n_slv_frm_axi_clk(spicr_2_mst_n_slv_frm_axi_clk),
.spicr_3_cpol_frm_axi_clk(spicr_3_cpol_frm_axi_clk),
.spicr_4_cpha_frm_axi_clk(spicr_4_cpha_frm_axi_clk),
.spicr_5_txfifo_rst_frm_axi_clk(spicr_5_txfifo_rst_frm_axi_clk),
.spicr_6_rxfifo_rst_frm_axi_clk(spicr_6_rxfifo_rst_frm_axi_clk),
.spicr_7_ss_frm_axi_clk(spicr_7_ss_frm_axi_clk),
.spicr_8_tr_inhibit_frm_axi_clk(spicr_8_tr_inhibit_frm_axi_clk),
.spicr_9_lsb_frm_axi_clk(spicr_9_lsb_frm_axi_clk),
.spisel_d1_reg_to_axi_clk(spisel_d1_reg_to_axi_clk),
.ss_o(ss_o),
.ss_t(ss_t),
.sw_rst_cond(\SOFT_RESET_I/sw_rst_cond ),
.sw_rst_cond_d1(\SOFT_RESET_I/sw_rst_cond_d1 ),
.transmit_ip2bus_error(transmit_ip2bus_error),
.wr_ce_or_reduce_core_cmb(wr_ce_or_reduce_core_cmb));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_qspi_enhanced_mode \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I
(.Bus_RNW_reg(\I_DECODER/Bus_RNW_reg ),
.Bus_RNW_reg_reg(\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_12 ),
.Bus_RNW_reg_reg_0(\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_13 ),
.Bus_RNW_reg_reg_1(\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_14 ),
.\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_52 ),
.\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_53 ),
.D(ip2bus_data_int),
.E(s_axi4_rresp_i0),
.\FSM_onehot_axi_full_sm_ps_reg[2]_0 (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_22 ),
.\FSM_onehot_axi_full_sm_ps_reg[3]_0 (\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_57 ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_46 ),
.\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_29 ),
.\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_15 ),
.\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_31 ),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_46 ),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_23 ),
.\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_45 ),
.\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_44 ),
.IP2Bus_WrAck_transmit_enable(IP2Bus_WrAck_transmit_enable),
.Q(\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_21 ),
.\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] (\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_38 ),
.SPISSR_frm_axi_clk(SPISSR_frm_axi_clk),
.SR(bus2ip_reset_ipif_inverted),
.Transmit_ip2bus_error0(\FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0 ),
.Tx_FIFO_Empty_SPISR_to_axi_clk(Tx_FIFO_Empty_SPISR_to_axi_clk),
.Tx_FIFO_Full_int(Tx_FIFO_Full_int),
.almost_full(TX_Fifo_full_indication),
.burst_tr_int(burst_tr_int),
.\bus2ip_BE_reg_reg[3]_0 (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_47 ),
.bus2ip_wrce_int(bus2ip_wrce_int),
.data_valid(data_valid),
.empty(Rx_FIFO_Empty),
.interrupt_wrce_strb(\INTERRUPT_CONTROL_I/interrupt_wrce_strb ),
.intr2bus_rdack0(\INTERRUPT_CONTROL_I/intr2bus_rdack0 ),
.intr_controller_rd_ce_or_reduce(intr_controller_rd_ce_or_reduce),
.ip2Bus_RdAck_core_reg(ip2Bus_RdAck_core_reg),
.ip2Bus_RdAck_intr_reg_hole0(ip2Bus_RdAck_intr_reg_hole0),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_core_reg(ip2Bus_WrAck_core_reg),
.ip2Bus_WrAck_core_reg0(ip2Bus_WrAck_core_reg0),
.ip2Bus_WrAck_core_reg_d1(ip2Bus_WrAck_core_reg_d1),
.ip2Bus_WrAck_intr_reg_hole0(ip2Bus_WrAck_intr_reg_hole0),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_error_int(ip2bus_error_int),
.\ip_irpt_enable_reg_reg[1] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_35 ),
.\ip_irpt_enable_reg_reg[2] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_36 ),
.\ip_irpt_enable_reg_reg[3] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_37 ),
.\ip_irpt_enable_reg_reg[4] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_38 ),
.\ip_irpt_enable_reg_reg[5] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_39 ),
.\ip_irpt_enable_reg_reg[6] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_40 ),
.\ip_irpt_enable_reg_reg[7] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_41 ),
.irpt_rdack(\INTERRUPT_CONTROL_I/irpt_rdack ),
.irpt_rdack_d1(\INTERRUPT_CONTROL_I/irpt_rdack_d1 ),
.irpt_wrack(\INTERRUPT_CONTROL_I/irpt_wrack ),
.irpt_wrack_d1(\INTERRUPT_CONTROL_I/irpt_wrack_d1 ),
.p_0_in(\INTERRUPT_CONTROL_I/p_0_in ),
.p_1_in(\I_DECODER/p_1_in ),
.p_1_in13_in(\INTERRUPT_CONTROL_I/p_1_in13_in ),
.p_1_in16_in(\INTERRUPT_CONTROL_I/p_1_in16_in ),
.p_1_in19_in(\INTERRUPT_CONTROL_I/p_1_in19_in ),
.p_1_in22_in(\INTERRUPT_CONTROL_I/p_1_in22_in ),
.p_1_in25_in(\INTERRUPT_CONTROL_I/p_1_in25_in ),
.p_1_in28_in(\INTERRUPT_CONTROL_I/p_1_in28_in ),
.p_1_in31_in(\INTERRUPT_CONTROL_I/p_1_in31_in ),
.p_1_in34_in(\INTERRUPT_CONTROL_I/p_1_in34_in ),
.p_2_in(\I_DECODER/p_2_in ),
.p_4_in(\I_DECODER/p_4_in ),
.rd_ce_or_reduce_core_cmb(rd_ce_or_reduce_core_cmb),
.rd_en(rd_en),
.receive_ip2bus_error(receive_ip2bus_error),
.reset2ip_reset_int(reset2ip_reset_int),
.reset_trig0(\SOFT_RESET_I/reset_trig0 ),
.rx_fifo_empty_i(rx_fifo_empty_i),
.s_axi4_aclk(s_axi4_aclk),
.s_axi4_araddr(s_axi4_araddr),
.s_axi4_aresetn(s_axi4_aresetn),
.s_axi4_arlen(s_axi4_arlen),
.s_axi4_arready(s_axi4_arready),
.s_axi4_arvalid(s_axi4_arvalid),
.s_axi4_awaddr(s_axi4_awaddr),
.s_axi4_awlen(s_axi4_awlen),
.s_axi4_awready(s_axi4_awready),
.s_axi4_awvalid(s_axi4_awvalid),
.s_axi4_bready(s_axi4_bready),
.s_axi4_bresp(s_axi4_bresp),
.s_axi4_bvalid(s_axi4_bvalid),
.s_axi4_rdata(s_axi4_rdata),
.\s_axi4_rdata_i_reg[8]_0 ({\INTERRUPT_CONTROL_I/p_0_in20_in ,\INTERRUPT_CONTROL_I/p_0_in17_in ,\INTERRUPT_CONTROL_I/p_0_in14_in ,\INTERRUPT_CONTROL_I/p_0_in11_in ,\INTERRUPT_CONTROL_I/p_0_in8_in ,\INTERRUPT_CONTROL_I/p_0_in5_in ,\INTERRUPT_CONTROL_I/p_0_in2_in ,\INTERRUPT_CONTROL_I/p_0_in0_in ,\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_68 }),
.s_axi4_rlast(s_axi4_rlast),
.s_axi4_rready(s_axi4_rready),
.s_axi4_rresp(s_axi4_rresp),
.s_axi4_wdata({s_axi4_wdata[10],s_axi4_wdata[6:5],s_axi4_wdata[3:0]}),
.\s_axi4_wdata[31] (\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_51 ),
.s_axi4_wdata_0_sp_1(\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_50 ),
.s_axi4_wready(s_axi4_wready),
.s_axi4_wstrb(s_axi4_wstrb),
.s_axi4_wvalid(s_axi4_wvalid),
.s_axi_rvalid_i_reg_0(s_axi_rvalid_i_reg),
.s_axi_rvalid_i_reg_1(\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_48 ),
.scndry_out(Rx_FIFO_Full_Fifo_d1_synced),
.spicr_0_loop_frm_axi_clk(spicr_0_loop_frm_axi_clk),
.spicr_1_spe_frm_axi_clk(spicr_1_spe_frm_axi_clk),
.spicr_2_mst_n_slv_frm_axi_clk(spicr_2_mst_n_slv_frm_axi_clk),
.spicr_3_cpol_frm_axi_clk(spicr_3_cpol_frm_axi_clk),
.spicr_4_cpha_frm_axi_clk(spicr_4_cpha_frm_axi_clk),
.spicr_5_txfifo_rst_frm_axi_clk(spicr_5_txfifo_rst_frm_axi_clk),
.spicr_6_rxfifo_rst_frm_axi_clk(spicr_6_rxfifo_rst_frm_axi_clk),
.spicr_7_ss_frm_axi_clk(spicr_7_ss_frm_axi_clk),
.spicr_8_tr_inhibit_frm_axi_clk(spicr_8_tr_inhibit_frm_axi_clk),
.spicr_9_lsb_frm_axi_clk(spicr_9_lsb_frm_axi_clk),
.spisel_d1_reg_to_axi_clk(spisel_d1_reg_to_axi_clk),
.sw_rst_cond(\SOFT_RESET_I/sw_rst_cond ),
.sw_rst_cond_d1(\SOFT_RESET_I/sw_rst_cond_d1 ),
.transmit_ip2bus_error(transmit_ip2bus_error),
.wr_ce_or_reduce_core_cmb(wr_ce_or_reduce_core_cmb));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(Rx_FIFO_Full_Fifo,
scndry_out,
almost_full,
prmry_in,
ext_spi_clk);
output Rx_FIFO_Full_Fifo;
output scndry_out;
input almost_full;
input prmry_in;
input ext_spi_clk;
wire Rx_FIFO_Full_Fifo;
wire almost_full;
wire ext_spi_clk;
wire prmry_in;
wire s_level_out_d1_cdc_to;
wire scndry_out;
LUT2 #(
.INIT(4'h2))
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_i_1
(.I0(almost_full),
.I1(scndry_out),
.O(Rx_FIFO_Full_Fifo));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(ext_spi_clk),
.CE(1'b1),
.D(prmry_in),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(ext_spi_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(scndry_out),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(Rx_FIFO_Full_Fifo_d1_synced_i,
scndry_out,
empty,
prmry_in,
s_axi4_aclk);
output Rx_FIFO_Full_Fifo_d1_synced_i;
output scndry_out;
input empty;
input prmry_in;
input s_axi4_aclk;
wire Rx_FIFO_Full_Fifo_d1_synced_i;
wire empty;
wire prmry_in;
wire s_axi4_aclk;
wire s_level_out_d1_cdc_to;
wire scndry_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi4_aclk),
.CE(1'b1),
.D(prmry_in),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi4_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(scndry_out),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
rc_FIFO_Full_d1_i_1
(.I0(scndry_out),
.I1(empty),
.O(Rx_FIFO_Full_Fifo_d1_synced_i));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f
(tx_fifo_count,
\icount_out_reg[3]_0 ,
\icount_out_reg[2]_0 ,
\icount_out_reg[1]_0 ,
\icount_out_reg[5]_0 ,
\icount_out_reg[4]_0 ,
\icount_out_reg[6]_0 ,
tx_occ_msb_1,
TX_one_less_than_full,
S,
IP2Bus_WrAck_transmit_enable,
bus2ip_reset_ipif_inverted,
\icount_out_reg[7]_0 ,
\icount_out_reg[7]_1 ,
\icount_out_reg[0]_0 ,
s_axi4_aclk);
output [0:0]tx_fifo_count;
output \icount_out_reg[3]_0 ;
output \icount_out_reg[2]_0 ;
output \icount_out_reg[1]_0 ;
output \icount_out_reg[5]_0 ;
output \icount_out_reg[4]_0 ;
output \icount_out_reg[6]_0 ;
output tx_occ_msb_1;
output TX_one_less_than_full;
input [0:0]S;
input IP2Bus_WrAck_transmit_enable;
input bus2ip_reset_ipif_inverted;
input \icount_out_reg[7]_0 ;
input \icount_out_reg[7]_1 ;
input \icount_out_reg[0]_0 ;
input s_axi4_aclk;
wire \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_3_n_0 ;
wire IP2Bus_WrAck_transmit_enable;
wire [0:0]S;
wire TX_one_less_than_full;
wire bus2ip_reset_ipif_inverted;
wire icount_out0_carry__0_i_1_n_0;
wire icount_out0_carry__0_i_2_n_0;
wire icount_out0_carry__0_i_3_n_0;
wire icount_out0_carry__0_n_2;
wire icount_out0_carry__0_n_3;
wire icount_out0_carry__0_n_5;
wire icount_out0_carry__0_n_6;
wire icount_out0_carry__0_n_7;
wire icount_out0_carry_i_1_n_0;
wire icount_out0_carry_i_2_n_0;
wire icount_out0_carry_i_3_n_0;
wire icount_out0_carry_i_4_n_0;
wire icount_out0_carry_n_0;
wire icount_out0_carry_n_1;
wire icount_out0_carry_n_2;
wire icount_out0_carry_n_3;
wire icount_out0_carry_n_4;
wire icount_out0_carry_n_5;
wire icount_out0_carry_n_6;
wire icount_out0_carry_n_7;
wire \icount_out[0]_i_1_n_0 ;
wire \icount_out[1]_i_1_n_0 ;
wire \icount_out[2]_i_1_n_0 ;
wire \icount_out[3]_i_1_n_0 ;
wire \icount_out[4]_i_1_n_0 ;
wire \icount_out[5]_i_1_n_0 ;
wire \icount_out[6]_i_1_n_0 ;
wire \icount_out[7]_i_2_n_0 ;
wire \icount_out_reg[0]_0 ;
wire \icount_out_reg[1]_0 ;
wire \icount_out_reg[2]_0 ;
wire \icount_out_reg[3]_0 ;
wire \icount_out_reg[4]_0 ;
wire \icount_out_reg[5]_0 ;
wire \icount_out_reg[6]_0 ;
wire \icount_out_reg[7]_0 ;
wire \icount_out_reg[7]_1 ;
wire s_axi4_aclk;
wire [0:0]tx_fifo_count;
wire tx_occ_msb_1;
wire [3:2]NLW_icount_out0_carry__0_CO_UNCONNECTED;
wire [3:3]NLW_icount_out0_carry__0_O_UNCONNECTED;
LUT6 #(
.INIT(64'h2000000000000000))
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_2
(.I0(IP2Bus_WrAck_transmit_enable),
.I1(\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_3_n_0 ),
.I2(\icount_out_reg[3]_0 ),
.I3(\icount_out_reg[1]_0 ),
.I4(\icount_out_reg[5]_0 ),
.I5(\icount_out_reg[2]_0 ),
.O(TX_one_less_than_full));
LUT4 #(
.INIT(16'hDFFF))
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_3
(.I0(\icount_out_reg[6]_0 ),
.I1(tx_fifo_count),
.I2(tx_occ_msb_1),
.I3(\icount_out_reg[4]_0 ),
.O(\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_3_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry
(.CI(1'b0),
.CO({icount_out0_carry_n_0,icount_out0_carry_n_1,icount_out0_carry_n_2,icount_out0_carry_n_3}),
.CYINIT(tx_fifo_count),
.DI({\icount_out_reg[3]_0 ,\icount_out_reg[2]_0 ,\icount_out_reg[1]_0 ,icount_out0_carry_i_1_n_0}),
.O({icount_out0_carry_n_4,icount_out0_carry_n_5,icount_out0_carry_n_6,icount_out0_carry_n_7}),
.S({icount_out0_carry_i_2_n_0,icount_out0_carry_i_3_n_0,icount_out0_carry_i_4_n_0,S}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__0
(.CI(icount_out0_carry_n_0),
.CO({NLW_icount_out0_carry__0_CO_UNCONNECTED[3:2],icount_out0_carry__0_n_2,icount_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\icount_out_reg[5]_0 ,\icount_out_reg[4]_0 }),
.O({NLW_icount_out0_carry__0_O_UNCONNECTED[3],icount_out0_carry__0_n_5,icount_out0_carry__0_n_6,icount_out0_carry__0_n_7}),
.S({1'b0,icount_out0_carry__0_i_1_n_0,icount_out0_carry__0_i_2_n_0,icount_out0_carry__0_i_3_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_1
(.I0(\icount_out_reg[6]_0 ),
.I1(tx_occ_msb_1),
.O(icount_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_2
(.I0(\icount_out_reg[5]_0 ),
.I1(\icount_out_reg[6]_0 ),
.O(icount_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_3
(.I0(\icount_out_reg[4]_0 ),
.I1(\icount_out_reg[5]_0 ),
.O(icount_out0_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h1))
icount_out0_carry_i_1
(.I0(\icount_out_reg[1]_0 ),
.O(icount_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_2
(.I0(\icount_out_reg[3]_0 ),
.I1(\icount_out_reg[4]_0 ),
.O(icount_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_3
(.I0(\icount_out_reg[2]_0 ),
.I1(\icount_out_reg[3]_0 ),
.O(icount_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_4
(.I0(\icount_out_reg[1]_0 ),
.I1(\icount_out_reg[2]_0 ),
.O(icount_out0_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT4 #(
.INIT(16'hFFFD))
\icount_out[0]_i_1
(.I0(tx_fifo_count),
.I1(bus2ip_reset_ipif_inverted),
.I2(\icount_out_reg[7]_0 ),
.I3(\icount_out_reg[7]_1 ),
.O(\icount_out[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT4 #(
.INIT(16'hFFFE))
\icount_out[1]_i_1
(.I0(icount_out0_carry_n_7),
.I1(bus2ip_reset_ipif_inverted),
.I2(\icount_out_reg[7]_0 ),
.I3(\icount_out_reg[7]_1 ),
.O(\icount_out[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT4 #(
.INIT(16'hFFFE))
\icount_out[2]_i_1
(.I0(icount_out0_carry_n_6),
.I1(bus2ip_reset_ipif_inverted),
.I2(\icount_out_reg[7]_0 ),
.I3(\icount_out_reg[7]_1 ),
.O(\icount_out[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT4 #(
.INIT(16'hFFFE))
\icount_out[3]_i_1
(.I0(icount_out0_carry_n_5),
.I1(bus2ip_reset_ipif_inverted),
.I2(\icount_out_reg[7]_0 ),
.I3(\icount_out_reg[7]_1 ),
.O(\icount_out[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'hFFFE))
\icount_out[4]_i_1
(.I0(icount_out0_carry_n_4),
.I1(bus2ip_reset_ipif_inverted),
.I2(\icount_out_reg[7]_0 ),
.I3(\icount_out_reg[7]_1 ),
.O(\icount_out[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'hFFFE))
\icount_out[5]_i_1
(.I0(icount_out0_carry__0_n_7),
.I1(bus2ip_reset_ipif_inverted),
.I2(\icount_out_reg[7]_0 ),
.I3(\icount_out_reg[7]_1 ),
.O(\icount_out[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'hFFFE))
\icount_out[6]_i_1
(.I0(icount_out0_carry__0_n_6),
.I1(bus2ip_reset_ipif_inverted),
.I2(\icount_out_reg[7]_0 ),
.I3(\icount_out_reg[7]_1 ),
.O(\icount_out[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'hFFFE))
\icount_out[7]_i_2
(.I0(icount_out0_carry__0_n_5),
.I1(bus2ip_reset_ipif_inverted),
.I2(\icount_out_reg[7]_0 ),
.I3(\icount_out_reg[7]_1 ),
.O(\icount_out[7]_i_2_n_0 ));
FDRE \icount_out_reg[0]
(.C(s_axi4_aclk),
.CE(\icount_out_reg[0]_0 ),
.D(\icount_out[0]_i_1_n_0 ),
.Q(tx_fifo_count),
.R(1'b0));
FDRE \icount_out_reg[1]
(.C(s_axi4_aclk),
.CE(\icount_out_reg[0]_0 ),
.D(\icount_out[1]_i_1_n_0 ),
.Q(\icount_out_reg[1]_0 ),
.R(1'b0));
FDRE \icount_out_reg[2]
(.C(s_axi4_aclk),
.CE(\icount_out_reg[0]_0 ),
.D(\icount_out[2]_i_1_n_0 ),
.Q(\icount_out_reg[2]_0 ),
.R(1'b0));
FDRE \icount_out_reg[3]
(.C(s_axi4_aclk),
.CE(\icount_out_reg[0]_0 ),
.D(\icount_out[3]_i_1_n_0 ),
.Q(\icount_out_reg[3]_0 ),
.R(1'b0));
FDRE \icount_out_reg[4]
(.C(s_axi4_aclk),
.CE(\icount_out_reg[0]_0 ),
.D(\icount_out[4]_i_1_n_0 ),
.Q(\icount_out_reg[4]_0 ),
.R(1'b0));
FDRE \icount_out_reg[5]
(.C(s_axi4_aclk),
.CE(\icount_out_reg[0]_0 ),
.D(\icount_out[5]_i_1_n_0 ),
.Q(\icount_out_reg[5]_0 ),
.R(1'b0));
FDRE \icount_out_reg[6]
(.C(s_axi4_aclk),
.CE(\icount_out_reg[0]_0 ),
.D(\icount_out[6]_i_1_n_0 ),
.Q(\icount_out_reg[6]_0 ),
.R(1'b0));
FDRE \icount_out_reg[7]
(.C(s_axi4_aclk),
.CE(\icount_out_reg[0]_0 ),
.D(\icount_out[7]_i_2_n_0 ),
.Q(tx_occ_msb_1),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cross_clk_sync_fifo_1
(spisel_d1_reg_to_axi_clk,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0 ,
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0 ,
spicr_0_loop_to_spi_clk,
SPICR_2_MST_N_SLV_to_spi_clk,
spicr_3_cpol_to_spi_clk,
spicr_4_cpha_to_spi_clk,
spicr_9_lsb_to_spi_clk,
register_Data_slvsel_int,
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0 ,
S,
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0 ,
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_1 ,
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_2 ,
spiXfer_done_to_axi_1,
Tx_FIFO_Empty_intr,
tx_occ_msb,
\s_axi4_wdata[7] ,
\s_axi4_wdata[5] ,
R,
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_0 ,
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_1 ,
D_0,
rst,
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2_0 ,
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0 ,
D,
reset2ip_reset_int,
s_axi4_aclk,
empty,
Rst_to_spi,
ext_spi_clk,
spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk,
spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk,
spicr_bits_7_8_frm_axi_clk,
SPISSR_frm_axi_clk,
D01_out,
D0,
icount_out0_carry,
IP2Bus_WrAck_transmit_enable,
bus2ip_reset_ipif_inverted,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg ,
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg ,
spicr_6_rxfifo_rst_frm_axi_clk,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0 ,
Tx_FIFO_Full_i,
Tx_FIFO_Full_int,
tx_fifo_count_d2,
spiXfer_done_to_axi_d1,
tx_occ_msb_4,
s_axi4_wdata,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ,
p_1_in16_in,
p_1_in22_in,
Count_trigger,
Ratio_Count,
transfer_start_d1,
\SS_O_reg[0] ,
transfer_start_reg,
serial_dout_int,
io1_i_sync,
io0_i_sync);
output spisel_d1_reg_to_axi_clk;
output \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0 ;
output \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0 ;
output spicr_0_loop_to_spi_clk;
output SPICR_2_MST_N_SLV_to_spi_clk;
output spicr_3_cpol_to_spi_clk;
output spicr_4_cpha_to_spi_clk;
output spicr_9_lsb_to_spi_clk;
output register_Data_slvsel_int;
output \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0 ;
output [0:0]S;
output \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0 ;
output \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_1 ;
output \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_2 ;
output spiXfer_done_to_axi_1;
output Tx_FIFO_Empty_intr;
output tx_occ_msb;
output \s_axi4_wdata[7] ;
output \s_axi4_wdata[5] ;
output R;
output \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_0 ;
output \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_1 ;
output D_0;
output rst;
output \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2_0 ;
output \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0 ;
output [0:0]D;
input reset2ip_reset_int;
input s_axi4_aclk;
input empty;
input Rst_to_spi;
input ext_spi_clk;
input spicr_0_loop_frm_axi_clk;
input spicr_1_spe_frm_axi_clk;
input spicr_2_mst_n_slv_frm_axi_clk;
input spicr_3_cpol_frm_axi_clk;
input spicr_4_cpha_frm_axi_clk;
input spicr_7_ss_frm_axi_clk;
input spicr_8_tr_inhibit_frm_axi_clk;
input spicr_9_lsb_frm_axi_clk;
input [1:0]spicr_bits_7_8_frm_axi_clk;
input SPISSR_frm_axi_clk;
input D01_out;
input D0;
input icount_out0_carry;
input IP2Bus_WrAck_transmit_enable;
input bus2ip_reset_ipif_inverted;
input \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg ;
input \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg ;
input spicr_6_rxfifo_rst_frm_axi_clk;
input \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0 ;
input Tx_FIFO_Full_i;
input Tx_FIFO_Full_int;
input [7:0]tx_fifo_count_d2;
input spiXfer_done_to_axi_d1;
input tx_occ_msb_4;
input [1:0]s_axi4_wdata;
input \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ;
input p_1_in16_in;
input p_1_in22_in;
input Count_trigger;
input Ratio_Count;
input transfer_start_d1;
input \SS_O_reg[0] ;
input transfer_start_reg;
input serial_dout_int;
input io1_i_sync;
input io0_i_sync;
wire Count_trigger;
wire [0:0]D;
wire D0;
wire D01_out;
wire D_0;
wire \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg ;
wire \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0 ;
wire \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg ;
wire \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ;
wire IP2Bus_WrAck_transmit_enable;
wire \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0 ;
wire \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_0 ;
wire \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_1 ;
wire \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2_0 ;
wire \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0 ;
wire \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0 ;
wire \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0 ;
wire \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_1 ;
wire \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_2 ;
wire \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0 ;
wire \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0 ;
wire \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0 ;
wire R;
wire Ratio_Count;
wire Rst_to_spi;
wire [0:0]S;
wire SPICR_0_LOOP_cdc_from_axi_d1;
wire SPICR_1_SPE_cdc_from_axi_d1;
wire SPICR_2_MST_N_SLV_cdc_from_axi_d1;
wire SPICR_2_MST_N_SLV_to_spi_clk;
wire SPICR_3_CPOL_cdc_from_axi_d1;
wire SPICR_4_CPHA_cdc_from_axi_d1;
wire SPICR_7_SS_cdc_from_axi_d1;
wire SPICR_8_TR_INHIBIT_cdc_from_axi_d1;
wire SPICR_9_LSB_cdc_from_axi_d1;
wire SPICR_bits_7_8_cdc_from_axi_d1_0;
wire SPICR_bits_7_8_cdc_from_axi_d1_1;
wire SPISSR_cdc_from_axi_d1;
wire SPISSR_frm_axi_clk;
wire \SS_O_reg[0] ;
wire Tx_FIFO_Empty_SPISR_cdc_from_spi_d1;
wire Tx_FIFO_Empty_intr;
wire Tx_FIFO_Full_i;
wire Tx_FIFO_Full_int;
wire bus2ip_reset_ipif_inverted;
wire drr_Overrun_int_cdc_from_spi_d1;
wire drr_Overrun_int_cdc_from_spi_d2;
wire drr_Overrun_int_cdc_from_spi_d3;
wire empty;
wire ext_spi_clk;
wire icount_out0_carry;
wire io0_i_sync;
wire io1_i_sync;
wire p_1_in16_in;
wire p_1_in22_in;
wire register_Data_slvsel_int;
wire reset2ip_reset_int;
wire reset_RcFIFO_ptr_cdc_from_axi_d1;
wire reset_RcFIFO_ptr_cdc_from_axi_d2;
wire rst;
wire s_axi4_aclk;
wire [1:0]s_axi4_wdata;
wire \s_axi4_wdata[5] ;
wire \s_axi4_wdata[7] ;
wire serial_dout_int;
wire spiXfer_done_d1;
wire spiXfer_done_d2;
wire spiXfer_done_d3;
wire spiXfer_done_to_axi_1;
wire spiXfer_done_to_axi_d1;
wire spicr_0_loop_frm_axi_clk;
wire spicr_0_loop_to_spi_clk;
wire spicr_1_spe_frm_axi_clk;
wire spicr_1_spe_to_spi_clk;
wire spicr_2_mst_n_slv_frm_axi_clk;
wire spicr_3_cpol_frm_axi_clk;
wire spicr_3_cpol_to_spi_clk;
wire spicr_4_cpha_frm_axi_clk;
wire spicr_4_cpha_to_spi_clk;
wire spicr_6_rxfifo_rst_frm_axi_clk;
wire spicr_7_ss_frm_axi_clk;
wire spicr_7_ss_to_spi_clk;
wire spicr_8_tr_inhibit_frm_axi_clk;
wire spicr_8_tr_inhibit_to_spi_clk;
wire spicr_9_lsb_frm_axi_clk;
wire spicr_9_lsb_to_spi_clk;
wire [1:0]spicr_bits_7_8_frm_axi_clk;
wire [0:1]spicr_bits_7_8_to_spi_clk;
wire spisel_d1_reg_cdc_from_spi_d1;
wire spisel_d1_reg_to_axi_clk;
wire spisel_pulse_cdc_from_spi_d1;
wire spisel_pulse_cdc_from_spi_d2;
wire spisel_pulse_cdc_from_spi_d3;
wire transfer_start_d1;
wire transfer_start_i_2_n_0;
wire transfer_start_reg;
wire tx_FIFO_Empty_d1_i_2_n_0;
wire [7:0]tx_fifo_count_d2;
wire tx_occ_msb;
wire tx_occ_msb_4;
LUT3 #(
.INIT(8'hBE))
\FIFO_EXISTS.RX_FIFO_II_i_1
(.I0(Rst_to_spi),
.I1(reset_RcFIFO_ptr_cdc_from_axi_d2),
.I2(reset_RcFIFO_ptr_cdc_from_axi_d1),
.O(rst));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFF90))
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_i_1
(.I0(spiXfer_done_d3),
.I1(spiXfer_done_d2),
.I2(\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0 ),
.I3(bus2ip_reset_ipif_inverted),
.I4(\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg ),
.I5(spicr_6_rxfifo_rst_frm_axi_clk),
.O(\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_1 ));
LUT6 #(
.INIT(64'h00090009000F0000))
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_i_1
(.I0(spiXfer_done_d3),
.I1(spiXfer_done_d2),
.I2(\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg ),
.I3(reset2ip_reset_int),
.I4(Tx_FIFO_Full_i),
.I5(Tx_FIFO_Full_int),
.O(\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_2 ));
LUT2 #(
.INIT(4'h6))
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.spiXfer_done_to_axi_d1_i_1
(.I0(spiXfer_done_d3),
.I1(spiXfer_done_d2),
.O(spiXfer_done_to_axi_1));
LUT5 #(
.INIT(32'h78FFFF78))
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1
(.I0(s_axi4_wdata[0]),
.I1(\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ),
.I2(p_1_in22_in),
.I3(drr_Overrun_int_cdc_from_spi_d3),
.I4(drr_Overrun_int_cdc_from_spi_d2),
.O(\s_axi4_wdata[5] ));
LUT5 #(
.INIT(32'h78FFFF78))
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1
(.I0(s_axi4_wdata[1]),
.I1(\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] ),
.I2(p_1_in16_in),
.I3(spisel_pulse_cdc_from_spi_d3),
.I4(spisel_pulse_cdc_from_spi_d2),
.O(\s_axi4_wdata[7] ));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0 ),
.Q(drr_Overrun_int_cdc_from_spi_d1),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2
(.C(s_axi4_aclk),
.CE(1'b1),
.D(drr_Overrun_int_cdc_from_spi_d1),
.Q(drr_Overrun_int_cdc_from_spi_d2),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3
(.C(s_axi4_aclk),
.CE(1'b1),
.D(drr_Overrun_int_cdc_from_spi_d2),
.Q(drr_Overrun_int_cdc_from_spi_d3),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0 ),
.Q(reset_RcFIFO_ptr_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(reset_RcFIFO_ptr_cdc_from_axi_d1),
.Q(reset_RcFIFO_ptr_cdc_from_axi_d2),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_0_loop_frm_axi_clk),
.Q(SPICR_0_LOOP_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_0_LOOP_cdc_from_axi_d1),
.Q(spicr_0_loop_to_spi_clk),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_1_spe_frm_axi_clk),
.Q(SPICR_1_SPE_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_1_SPE_cdc_from_axi_d1),
.Q(spicr_1_spe_to_spi_clk),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_2_mst_n_slv_frm_axi_clk),
.Q(SPICR_2_MST_N_SLV_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_2_MST_N_SLV_cdc_from_axi_d1),
.Q(SPICR_2_MST_N_SLV_to_spi_clk),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_3_cpol_frm_axi_clk),
.Q(SPICR_3_CPOL_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_3_CPOL_cdc_from_axi_d1),
.Q(spicr_3_cpol_to_spi_clk),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_4_cpha_frm_axi_clk),
.Q(SPICR_4_CPHA_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_4_CPHA_cdc_from_axi_d1),
.Q(spicr_4_cpha_to_spi_clk),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_7_ss_frm_axi_clk),
.Q(SPICR_7_SS_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_7_SS_cdc_from_axi_d1),
.Q(spicr_7_ss_to_spi_clk),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_8_tr_inhibit_frm_axi_clk),
.Q(SPICR_8_TR_INHIBIT_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_8_TR_INHIBIT_cdc_from_axi_d1),
.Q(spicr_8_tr_inhibit_to_spi_clk),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_9_lsb_frm_axi_clk),
.Q(SPICR_9_LSB_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_9_LSB_cdc_from_axi_d1),
.Q(spicr_9_lsb_to_spi_clk),
.R(Rst_to_spi));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_bits_7_8_frm_axi_clk[0]),
.Q(SPICR_bits_7_8_cdc_from_axi_d1_0),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_bits_7_8_cdc_from_axi_d1_0),
.Q(spicr_bits_7_8_to_spi_clk[1]),
.R(Rst_to_spi));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(spicr_bits_7_8_frm_axi_clk[1]),
.Q(SPICR_bits_7_8_cdc_from_axi_d1_1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPICR_bits_7_8_cdc_from_axi_d1_1),
.Q(spicr_bits_7_8_to_spi_clk[0]),
.R(Rst_to_spi));
LUT2 #(
.INIT(4'h6))
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1
(.I0(\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0 ),
.I1(spicr_6_rxfifo_rst_frm_axi_clk),
.O(\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0 ));
FDRE \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0 ),
.Q(\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0 ),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC
(.C(s_axi4_aclk),
.CE(1'b1),
.D(1'b1),
.Q(spisel_d1_reg_cdc_from_spi_d1),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2
(.C(s_axi4_aclk),
.CE(1'b1),
.D(spisel_d1_reg_cdc_from_spi_d1),
.Q(spisel_d1_reg_to_axi_clk),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC
(.C(s_axi4_aclk),
.CE(1'b1),
.D(1'b0),
.Q(spisel_pulse_cdc_from_spi_d1),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2
(.C(s_axi4_aclk),
.CE(1'b1),
.D(spisel_pulse_cdc_from_spi_d1),
.Q(spisel_pulse_cdc_from_spi_d2),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3
(.C(s_axi4_aclk),
.CE(1'b1),
.D(spisel_pulse_cdc_from_spi_d2),
.Q(spisel_pulse_cdc_from_spi_d3),
.R(reset2ip_reset_int));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPISSR_frm_axi_clk),
.Q(SPISSR_cdc_from_axi_d1),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPISSR_cdc_from_axi_d1),
.Q(register_Data_slvsel_int),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0 ),
.Q(spiXfer_done_d1),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2
(.C(s_axi4_aclk),
.CE(1'b1),
.D(spiXfer_done_d1),
.Q(spiXfer_done_d2),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3
(.C(s_axi4_aclk),
.CE(1'b1),
.D(spiXfer_done_d2),
.Q(spiXfer_done_d3),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC
(.C(s_axi4_aclk),
.CE(1'b1),
.D(empty),
.Q(Tx_FIFO_Empty_SPISR_cdc_from_spi_d1),
.R(reset2ip_reset_int));
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2
(.C(s_axi4_aclk),
.CE(1'b1),
.D(Tx_FIFO_Empty_SPISR_cdc_from_spi_d1),
.Q(\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0 ),
.R(reset2ip_reset_int));
FDRE \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(D0),
.Q(\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0 ),
.R(Rst_to_spi));
FDRE \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(D01_out),
.Q(\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0 ),
.R(Rst_to_spi));
LUT1 #(
.INIT(2'h1))
\RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST_i_1
(.I0(SPICR_2_MST_N_SLV_to_spi_clk),
.O(R));
LUT5 #(
.INIT(32'hB8FFB800))
\RISING_EDGE_CLK_RATIO_4_GEN.Serial_Din_i_1
(.I0(serial_dout_int),
.I1(spicr_0_loop_to_spi_clk),
.I2(io1_i_sync),
.I3(SPICR_2_MST_N_SLV_to_spi_clk),
.I4(io0_i_sync),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT5 #(
.INIT(32'h0000F600))
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_3
(.I0(spicr_3_cpol_to_spi_clk),
.I1(spicr_4_cpha_to_spi_clk),
.I2(Count_trigger),
.I3(SPICR_2_MST_N_SLV_to_spi_clk),
.I4(Ratio_Count),
.O(\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT2 #(
.INIT(4'h6))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_3
(.I0(spicr_3_cpol_to_spi_clk),
.I1(spicr_4_cpha_to_spi_clk),
.O(\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_1 ));
LUT3 #(
.INIT(8'hDF))
SPI_TRISTATE_CONTROL_III_i_1
(.I0(spicr_bits_7_8_to_spi_clk[0]),
.I1(spicr_0_loop_to_spi_clk),
.I2(spicr_bits_7_8_to_spi_clk[1]),
.O(D_0));
LUT5 #(
.INIT(32'hFFFFFF15))
\SS_O[0]_i_1
(.I0(spicr_7_ss_to_spi_clk),
.I1(transfer_start_d1),
.I2(\SS_O_reg[0] ),
.I3(register_Data_slvsel_int),
.I4(Rst_to_spi),
.O(\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2_0 ));
LUT4 #(
.INIT(16'hAA96))
icount_out0_carry_i_5
(.I0(icount_out0_carry),
.I1(spiXfer_done_d3),
.I2(spiXfer_done_d2),
.I3(IP2Bus_WrAck_transmit_enable),
.O(S));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFF96))
\icount_out[7]_i_1
(.I0(IP2Bus_WrAck_transmit_enable),
.I1(spiXfer_done_d3),
.I2(spiXfer_done_d2),
.I3(bus2ip_reset_ipif_inverted),
.I4(\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg ),
.I5(\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg ),
.O(\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0 ));
LUT5 #(
.INIT(32'h00002F20))
transfer_start_i_1
(.I0(\SS_O_reg[0] ),
.I1(transfer_start_i_2_n_0),
.I2(SPICR_2_MST_N_SLV_to_spi_clk),
.I3(spicr_1_spe_to_spi_clk),
.I4(Rst_to_spi),
.O(\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0 ));
LUT4 #(
.INIT(16'hFF8F))
transfer_start_i_2
(.I0(transfer_start_reg),
.I1(empty),
.I2(spicr_1_spe_to_spi_clk),
.I3(spicr_8_tr_inhibit_to_spi_clk),
.O(transfer_start_i_2_n_0));
LUT5 #(
.INIT(32'h00000001))
tx_FIFO_Empty_d1_i_1
(.I0(tx_fifo_count_d2[1]),
.I1(tx_fifo_count_d2[2]),
.I2(tx_fifo_count_d2[0]),
.I3(tx_fifo_count_d2[4]),
.I4(tx_FIFO_Empty_d1_i_2_n_0),
.O(Tx_FIFO_Empty_intr));
LUT6 #(
.INIT(64'hFFFFFEFFFFFFFFFF))
tx_FIFO_Empty_d1_i_2
(.I0(tx_fifo_count_d2[6]),
.I1(tx_fifo_count_d2[3]),
.I2(tx_fifo_count_d2[7]),
.I3(\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0 ),
.I4(tx_fifo_count_d2[5]),
.I5(spiXfer_done_to_axi_d1),
.O(tx_FIFO_Empty_d1_i_2_n_0));
LUT2 #(
.INIT(4'h2))
tx_FIFO_Occpncy_MSB_d1_i_1
(.I0(tx_occ_msb_4),
.I1(\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0 ),
.O(tx_occ_msb));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control
(irpt_wrack_d1,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
p_1_in34_in,
p_1_in31_in,
p_1_in28_in,
p_1_in25_in,
p_1_in22_in,
p_1_in19_in,
p_1_in16_in,
p_1_in13_in,
irpt_rdack_d1,
p_0_in,
intr2bus_wrack_reg_0,
E,
\gen_fwft.gdvld_fwft.data_valid_fwft_reg ,
intr2bus_rdack_reg_0,
ip2intc_irpt,
\ip_irpt_enable_reg_reg[8]_0 ,
reset2ip_reset_int,
irpt_wrack,
s_axi4_aclk,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1 ,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0 ,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0 ,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0 ,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0 ,
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 ,
interrupt_wrce_strb,
irpt_rdack,
intr2bus_rdack0,
ipif_glbl_irpt_enable_reg_reg_0,
ip2bus_error_int,
wrack,
ip2Bus_WrAck_intr_reg_hole,
ip2Bus_WrAck_core_reg,
burst_tr_int,
s_axi4_rready,
Q,
\s_axi4_rdata_i_reg[31] ,
data_valid,
ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole,
s_axi4_wdata,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0 ,
rc_FIFO_Full_d1,
scndry_out,
empty,
tx_FIFO_Empty_d1,
Tx_FIFO_Empty_intr,
tx_occ_msb_4,
Tx_FIFO_Empty_SPISR_to_axi_clk,
tx_FIFO_Occpncy_MSB_d1,
\ip_irpt_enable_reg_reg[8]_1 ,
D);
output irpt_wrack_d1;
output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
output p_1_in34_in;
output p_1_in31_in;
output p_1_in28_in;
output p_1_in25_in;
output p_1_in22_in;
output p_1_in19_in;
output p_1_in16_in;
output p_1_in13_in;
output irpt_rdack_d1;
output [0:0]p_0_in;
output intr2bus_wrack_reg_0;
output [0:0]E;
output \gen_fwft.gdvld_fwft.data_valid_fwft_reg ;
output intr2bus_rdack_reg_0;
output ip2intc_irpt;
output [8:0]\ip_irpt_enable_reg_reg[8]_0 ;
input reset2ip_reset_int;
input irpt_wrack;
input s_axi4_aclk;
input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1 ;
input \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0 ;
input \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0 ;
input \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0 ;
input \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0 ;
input \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 ;
input interrupt_wrce_strb;
input irpt_rdack;
input intr2bus_rdack0;
input ipif_glbl_irpt_enable_reg_reg_0;
input ip2bus_error_int;
input wrack;
input ip2Bus_WrAck_intr_reg_hole;
input ip2Bus_WrAck_core_reg;
input burst_tr_int;
input s_axi4_rready;
input [0:0]Q;
input \s_axi4_rdata_i_reg[31] ;
input data_valid;
input ip2Bus_RdAck_core_reg;
input ip2Bus_RdAck_intr_reg_hole;
input [7:0]s_axi4_wdata;
input \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0 ;
input rc_FIFO_Full_d1;
input scndry_out;
input empty;
input tx_FIFO_Empty_d1;
input Tx_FIFO_Empty_intr;
input tx_occ_msb_4;
input Tx_FIFO_Empty_SPISR_to_axi_clk;
input tx_FIFO_Occpncy_MSB_d1;
input [0:0]\ip_irpt_enable_reg_reg[8]_1 ;
input [0:0]D;
wire [0:0]D;
wire [0:0]E;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1 ;
wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 ;
wire [0:0]Q;
wire Tx_FIFO_Empty_SPISR_to_axi_clk;
wire Tx_FIFO_Empty_intr;
wire burst_tr_int;
wire data_valid;
wire empty;
wire \gen_fwft.gdvld_fwft.data_valid_fwft_reg ;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr2bus_rdack_reg_0;
wire intr2bus_wrack_reg_0;
wire intr_ip2bus_rdack;
wire intr_ip2bus_wrack;
wire ip2Bus_RdAck_core_reg;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_WrAck_core_reg;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2bus_error_int;
wire ip2intc_irpt;
wire ip2intc_irpt_INST_0_i_1_n_0;
wire ip2intc_irpt_INST_0_i_2_n_0;
wire ip2intc_irpt_INST_0_i_3_n_0;
wire ip2intc_irpt_INST_0_i_4_n_0;
wire [8:0]\ip_irpt_enable_reg_reg[8]_0 ;
wire [0:0]\ip_irpt_enable_reg_reg[8]_1 ;
wire ipif_glbl_irpt_enable_reg_reg_0;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire p_1_in13_in;
wire p_1_in16_in;
wire p_1_in19_in;
wire p_1_in22_in;
wire p_1_in25_in;
wire p_1_in28_in;
wire p_1_in31_in;
wire p_1_in34_in;
wire rc_FIFO_Full_d1;
wire reset2ip_reset_int;
wire s_axi4_aclk;
wire \s_axi4_rdata_i_reg[31] ;
wire s_axi4_rready;
wire [7:0]s_axi4_wdata;
wire scndry_out;
wire tx_FIFO_Empty_d1;
wire tx_FIFO_Occpncy_MSB_d1;
wire tx_occ_msb_4;
wire wrack;
LUT3 #(
.INIT(8'hFE))
\FSM_onehot_axi_full_sm_ps[3]_i_3
(.I0(intr_ip2bus_rdack),
.I1(ip2Bus_RdAck_core_reg),
.I2(ip2Bus_RdAck_intr_reg_hole),
.O(intr2bus_rdack_reg_0));
FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1 ),
.Q(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.R(reset2ip_reset_int));
FDRE \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0 ),
.Q(p_1_in34_in),
.R(reset2ip_reset_int));
LUT5 #(
.INIT(32'h78FF7878))
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1
(.I0(s_axi4_wdata[2]),
.I1(\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0 ),
.I2(p_1_in31_in),
.I3(tx_FIFO_Empty_d1),
.I4(Tx_FIFO_Empty_intr),
.O(\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0 ));
FDRE \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0 ),
.Q(p_1_in31_in),
.R(reset2ip_reset_int));
FDRE \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0 ),
.Q(p_1_in28_in),
.R(reset2ip_reset_int));
LUT6 #(
.INIT(64'h7878787878FF7878))
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1
(.I0(s_axi4_wdata[4]),
.I1(\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0 ),
.I2(p_1_in25_in),
.I3(rc_FIFO_Full_d1),
.I4(scndry_out),
.I5(empty),
.O(\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0 ));
FDRE \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0 ),
.Q(p_1_in25_in),
.R(reset2ip_reset_int));
FDRE \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0 ),
.Q(p_1_in22_in),
.R(reset2ip_reset_int));
LUT6 #(
.INIT(64'hFFFF78FF78787878))
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1
(.I0(s_axi4_wdata[6]),
.I1(\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0 ),
.I2(p_1_in19_in),
.I3(tx_occ_msb_4),
.I4(Tx_FIFO_Empty_SPISR_to_axi_clk),
.I5(tx_FIFO_Occpncy_MSB_d1),
.O(\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0 ));
FDRE \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0 ),
.Q(p_1_in19_in),
.R(reset2ip_reset_int));
FDRE \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0 ),
.Q(p_1_in16_in),
.R(reset2ip_reset_int));
FDRE \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 ),
.Q(p_1_in13_in),
.R(reset2ip_reset_int));
LUT6 #(
.INIT(64'hFFFEFFFEFFFFFFFE))
awready_i_i_2
(.I0(ip2bus_error_int),
.I1(intr_ip2bus_wrack),
.I2(wrack),
.I3(ip2Bus_WrAck_intr_reg_hole),
.I4(ip2Bus_WrAck_core_reg),
.I5(burst_tr_int),
.O(intr2bus_wrack_reg_0));
FDRE intr2bus_rdack_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(intr2bus_rdack0),
.Q(intr_ip2bus_rdack),
.R(reset2ip_reset_int));
FDRE intr2bus_wrack_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(interrupt_wrce_strb),
.Q(intr_ip2bus_wrack),
.R(reset2ip_reset_int));
LUT5 #(
.INIT(32'hAAA8AAAA))
ip2intc_irpt_INST_0
(.I0(p_0_in),
.I1(ip2intc_irpt_INST_0_i_1_n_0),
.I2(ip2intc_irpt_INST_0_i_2_n_0),
.I3(ip2intc_irpt_INST_0_i_3_n_0),
.I4(ip2intc_irpt_INST_0_i_4_n_0),
.O(ip2intc_irpt));
LUT4 #(
.INIT(16'hF888))
ip2intc_irpt_INST_0_i_1
(.I0(\ip_irpt_enable_reg_reg[8]_0 [2]),
.I1(p_1_in31_in),
.I2(\ip_irpt_enable_reg_reg[8]_0 [0]),
.I3(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.O(ip2intc_irpt_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'hF888))
ip2intc_irpt_INST_0_i_2
(.I0(\ip_irpt_enable_reg_reg[8]_0 [8]),
.I1(p_1_in13_in),
.I2(\ip_irpt_enable_reg_reg[8]_0 [1]),
.I3(p_1_in34_in),
.O(ip2intc_irpt_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'hF888))
ip2intc_irpt_INST_0_i_3
(.I0(\ip_irpt_enable_reg_reg[8]_0 [4]),
.I1(p_1_in25_in),
.I2(\ip_irpt_enable_reg_reg[8]_0 [5]),
.I3(p_1_in22_in),
.O(ip2intc_irpt_INST_0_i_3_n_0));
LUT6 #(
.INIT(64'h0000077707770777))
ip2intc_irpt_INST_0_i_4
(.I0(\ip_irpt_enable_reg_reg[8]_0 [3]),
.I1(p_1_in28_in),
.I2(p_1_in19_in),
.I3(\ip_irpt_enable_reg_reg[8]_0 [6]),
.I4(p_1_in16_in),
.I5(\ip_irpt_enable_reg_reg[8]_0 [7]),
.O(ip2intc_irpt_INST_0_i_4_n_0));
FDRE \ip_irpt_enable_reg_reg[0]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(s_axi4_wdata[0]),
.Q(\ip_irpt_enable_reg_reg[8]_0 [0]),
.R(reset2ip_reset_int));
FDRE \ip_irpt_enable_reg_reg[1]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(s_axi4_wdata[1]),
.Q(\ip_irpt_enable_reg_reg[8]_0 [1]),
.R(reset2ip_reset_int));
FDRE \ip_irpt_enable_reg_reg[2]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(s_axi4_wdata[2]),
.Q(\ip_irpt_enable_reg_reg[8]_0 [2]),
.R(reset2ip_reset_int));
FDRE \ip_irpt_enable_reg_reg[3]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(s_axi4_wdata[3]),
.Q(\ip_irpt_enable_reg_reg[8]_0 [3]),
.R(reset2ip_reset_int));
FDRE \ip_irpt_enable_reg_reg[4]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(s_axi4_wdata[4]),
.Q(\ip_irpt_enable_reg_reg[8]_0 [4]),
.R(reset2ip_reset_int));
FDRE \ip_irpt_enable_reg_reg[5]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(s_axi4_wdata[5]),
.Q(\ip_irpt_enable_reg_reg[8]_0 [5]),
.R(reset2ip_reset_int));
FDRE \ip_irpt_enable_reg_reg[6]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(s_axi4_wdata[6]),
.Q(\ip_irpt_enable_reg_reg[8]_0 [6]),
.R(reset2ip_reset_int));
FDRE \ip_irpt_enable_reg_reg[7]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(s_axi4_wdata[7]),
.Q(\ip_irpt_enable_reg_reg[8]_0 [7]),
.R(reset2ip_reset_int));
FDRE \ip_irpt_enable_reg_reg[8]
(.C(s_axi4_aclk),
.CE(\ip_irpt_enable_reg_reg[8]_1 ),
.D(D),
.Q(\ip_irpt_enable_reg_reg[8]_0 [8]),
.R(reset2ip_reset_int));
FDRE ipif_glbl_irpt_enable_reg_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(ipif_glbl_irpt_enable_reg_reg_0),
.Q(p_0_in),
.R(reset2ip_reset_int));
FDRE irpt_rdack_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(irpt_rdack),
.Q(irpt_rdack_d1),
.R(reset2ip_reset_int));
FDRE irpt_wrack_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(irpt_wrack),
.Q(irpt_wrack_d1),
.R(reset2ip_reset_int));
LUT3 #(
.INIT(8'hBA))
\s_axi4_rdata_i[31]_i_2
(.I0(s_axi4_rready),
.I1(\gen_fwft.gdvld_fwft.data_valid_fwft_reg ),
.I2(Q),
.O(E));
LUT6 #(
.INIT(64'h0000000000000007))
\s_axi4_rdata_i[31]_i_4
(.I0(\s_axi4_rdata_i_reg[31] ),
.I1(data_valid),
.I2(intr_ip2bus_rdack),
.I3(ip2Bus_RdAck_core_reg),
.I4(ip2Bus_RdAck_intr_reg_hole),
.I5(ip2bus_error_int),
.O(\gen_fwft.gdvld_fwft.data_valid_fwft_reg ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_address_decoder
(start,
p_1_in,
p_2_in,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 ,
Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3,
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]_0 ,
ip2Bus_WrAck_core_reg0,
wr_ce_or_reduce_core_cmb,
ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole0,
\FSM_onehot_axi_full_sm_ps_reg[0] ,
D,
s_axi4_wvalid_0,
Bus_RNW_reg_reg_4,
reset_trig0,
sw_rst_cond,
Transmit_ip2bus_error0,
IP2Bus_WrAck_transmit_enable,
\length_cntr_reg[6] ,
rd_en,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_1 ,
\length_cntr_reg[2] ,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ,
bus2ip_wrce_int,
irpt_wrack,
interrupt_wrce_strb,
\ip_irpt_enable_reg_reg[1] ,
\ip_irpt_enable_reg_reg[2] ,
\ip_irpt_enable_reg_reg[3] ,
\ip_irpt_enable_reg_reg[4] ,
\ip_irpt_enable_reg_reg[5] ,
\ip_irpt_enable_reg_reg[6] ,
\ip_irpt_enable_reg_reg[7] ,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1 ,
irpt_rdack,
intr2bus_rdack0,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
\bus2ip_BE_reg_reg[3] ,
rd_ce_or_reduce_core_cmb,
intr_controller_rd_ce_or_reduce,
s_axi4_wdata_0_sp_1,
\s_axi4_wdata[31] ,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ,
s_axi4_aclk,
s_axi4_araddr,
s_axi4_arvalid,
s_axi4_awaddr,
ip2Bus_WrAck_core_reg,
Q,
empty,
ip2Bus_WrAck_core_reg_d1,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
last_data_acked_reg,
last_data_acked_reg_0,
last_data_acked_reg_1,
last_data_acked_reg_2,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
s_axi4_awvalid,
s_axi4_wvalid,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ,
\FSM_onehot_axi_full_sm_ps_reg[3] ,
data_valid,
\FSM_onehot_axi_full_sm_ps_reg[3]_0 ,
\FSM_onehot_axi_full_sm_ps_reg[3]_1 ,
\s_axi4_rresp_i_reg[1] ,
transmit_ip2bus_error,
receive_ip2bus_error,
sw_rst_cond_d1,
Tx_FIFO_Full_int,
almost_full,
s_axi_wready_i,
\gwack.wr_ack_i_reg ,
\gwack.wr_ack_i_reg_0 ,
s_axi4_rready,
\guf.underflow_i_reg ,
ip2Bus_RdAck_core_reg,
s_axi4_aresetn,
\FSM_onehot_axi_full_sm_ps_reg[1] ,
\s_axi4_rdata_i_reg[8] ,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
SPISSR_frm_axi_clk,
rx_fifo_empty_i,
spicr_0_loop_frm_axi_clk,
irpt_wrack_d1,
p_1_in34_in,
p_1_in31_in,
p_1_in28_in,
spicr_4_cpha_frm_axi_clk,
p_1_in25_in,
p_1_in22_in,
spicr_6_rxfifo_rst_frm_axi_clk,
p_1_in19_in,
p_1_in16_in,
spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk,
p_1_in13_in,
p_0_in,
irpt_rdack_d1,
s_axi4_wdata,
scndry_out,
spicr_1_spe_frm_axi_clk,
Tx_FIFO_Empty_SPISR_to_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk,
spisel_d1_reg_to_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk,
spicr_9_lsb_frm_axi_clk,
reset2ip_reset_int);
output start;
output p_1_in;
output p_2_in;
output \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 ;
output Bus_RNW_reg_reg_0;
output Bus_RNW_reg_reg_1;
output [0:0]Bus_RNW_reg_reg_2;
output Bus_RNW_reg_reg_3;
output \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]_0 ;
output ip2Bus_WrAck_core_reg0;
output wr_ce_or_reduce_core_cmb;
output ip2Bus_RdAck_intr_reg_hole0;
output ip2Bus_WrAck_intr_reg_hole0;
output \FSM_onehot_axi_full_sm_ps_reg[0] ;
output [0:0]D;
output s_axi4_wvalid_0;
output Bus_RNW_reg_reg_4;
output reset_trig0;
output sw_rst_cond;
output Transmit_ip2bus_error0;
output IP2Bus_WrAck_transmit_enable;
output \length_cntr_reg[6] ;
output rd_en;
output \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_1 ;
output \length_cntr_reg[2] ;
output \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ;
output [0:0]bus2ip_wrce_int;
output irpt_wrack;
output interrupt_wrce_strb;
output \ip_irpt_enable_reg_reg[1] ;
output \ip_irpt_enable_reg_reg[2] ;
output \ip_irpt_enable_reg_reg[3] ;
output \ip_irpt_enable_reg_reg[4] ;
output \ip_irpt_enable_reg_reg[5] ;
output \ip_irpt_enable_reg_reg[6] ;
output \ip_irpt_enable_reg_reg[7] ;
output [2:0]\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1 ;
output irpt_rdack;
output intr2bus_rdack0;
output \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
output \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
output \bus2ip_BE_reg_reg[3] ;
output rd_ce_or_reduce_core_cmb;
output intr_controller_rd_ce_or_reduce;
output s_axi4_wdata_0_sp_1;
output \s_axi4_wdata[31] ;
output \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ;
output \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ;
input s_axi4_aclk;
input [4:0]s_axi4_araddr;
input s_axi4_arvalid;
input [4:0]s_axi4_awaddr;
input ip2Bus_WrAck_core_reg;
input [0:0]Q;
input empty;
input ip2Bus_WrAck_core_reg_d1;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input last_data_acked_reg;
input last_data_acked_reg_0;
input last_data_acked_reg_1;
input last_data_acked_reg_2;
input [5:0]\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
input s_axi4_awvalid;
input s_axi4_wvalid;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ;
input \FSM_onehot_axi_full_sm_ps_reg[3] ;
input data_valid;
input \FSM_onehot_axi_full_sm_ps_reg[3]_0 ;
input \FSM_onehot_axi_full_sm_ps_reg[3]_1 ;
input \s_axi4_rresp_i_reg[1] ;
input transmit_ip2bus_error;
input receive_ip2bus_error;
input sw_rst_cond_d1;
input Tx_FIFO_Full_int;
input almost_full;
input s_axi_wready_i;
input \gwack.wr_ack_i_reg ;
input \gwack.wr_ack_i_reg_0 ;
input s_axi4_rready;
input \guf.underflow_i_reg ;
input ip2Bus_RdAck_core_reg;
input s_axi4_aresetn;
input [7:0]\FSM_onehot_axi_full_sm_ps_reg[1] ;
input [8:0]\s_axi4_rdata_i_reg[8] ;
input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
input SPISSR_frm_axi_clk;
input rx_fifo_empty_i;
input spicr_0_loop_frm_axi_clk;
input irpt_wrack_d1;
input p_1_in34_in;
input p_1_in31_in;
input p_1_in28_in;
input spicr_4_cpha_frm_axi_clk;
input p_1_in25_in;
input p_1_in22_in;
input spicr_6_rxfifo_rst_frm_axi_clk;
input p_1_in19_in;
input p_1_in16_in;
input spicr_7_ss_frm_axi_clk;
input spicr_8_tr_inhibit_frm_axi_clk;
input p_1_in13_in;
input [0:0]p_0_in;
input irpt_rdack_d1;
input [5:0]s_axi4_wdata;
input scndry_out;
input spicr_1_spe_frm_axi_clk;
input Tx_FIFO_Empty_SPISR_to_axi_clk;
input spicr_2_mst_n_slv_frm_axi_clk;
input spicr_3_cpol_frm_axi_clk;
input spisel_d1_reg_to_axi_clk;
input spicr_5_txfifo_rst_frm_axi_clk;
input spicr_9_lsb_frm_axi_clk;
input reset2ip_reset_int;
wire Bus_RNW_reg_i_1_n_0;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire [0:0]Bus_RNW_reg_reg_2;
wire Bus_RNW_reg_reg_3;
wire Bus_RNW_reg_reg_4;
wire \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ;
wire \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ;
wire [0:0]D;
wire \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0 ;
wire \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0 ;
wire \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0 ;
wire \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2_n_0 ;
wire \FSM_onehot_axi_full_sm_ps_reg[0] ;
wire [7:0]\FSM_onehot_axi_full_sm_ps_reg[1] ;
wire \FSM_onehot_axi_full_sm_ps_reg[3] ;
wire \FSM_onehot_axi_full_sm_ps_reg[3]_0 ;
wire \FSM_onehot_axi_full_sm_ps_reg[3]_1 ;
wire [5:0]\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ;
wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 ;
wire \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_1 ;
wire \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]_0 ;
wire \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_5_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ;
wire [2:0]\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1 ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
wire \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
wire IP2Bus_WrAck_transmit_enable;
wire [0:0]Q;
wire SPISSR_frm_axi_clk;
wire Transmit_ip2bus_error0;
wire Tx_FIFO_Empty_SPISR_to_axi_clk;
wire Tx_FIFO_Full_int;
wire almost_full;
wire \bus2ip_BE_reg_reg[3] ;
wire [0:0]bus2ip_wrce_int;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_10;
wire ce_expnd_i_11;
wire ce_expnd_i_12;
wire ce_expnd_i_13;
wire ce_expnd_i_14;
wire ce_expnd_i_15;
wire ce_expnd_i_16;
wire ce_expnd_i_17;
wire ce_expnd_i_18;
wire ce_expnd_i_19;
wire ce_expnd_i_2;
wire ce_expnd_i_20;
wire ce_expnd_i_21;
wire ce_expnd_i_22;
wire ce_expnd_i_23;
wire ce_expnd_i_24;
wire ce_expnd_i_25;
wire ce_expnd_i_26;
wire ce_expnd_i_28;
wire ce_expnd_i_29;
wire ce_expnd_i_3;
wire ce_expnd_i_31;
wire ce_expnd_i_4;
wire ce_expnd_i_5;
wire ce_expnd_i_6;
wire ce_expnd_i_7;
wire ce_expnd_i_8;
wire ce_expnd_i_9;
wire cs_ce_clr;
wire data_valid;
wire empty;
wire \guf.underflow_i_reg ;
wire \gwack.wr_ack_i_reg ;
wire \gwack.wr_ack_i_reg_0 ;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_controller_rd_ce_or_reduce;
wire ip2Bus_RdAck_core_reg;
wire ip2Bus_RdAck_intr_reg_hole0;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_core_reg;
wire ip2Bus_WrAck_core_reg0;
wire ip2Bus_WrAck_core_reg_d1;
wire ip2Bus_WrAck_intr_reg_hole0;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0;
wire ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0;
wire ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0;
wire \ip_irpt_enable_reg_reg[1] ;
wire \ip_irpt_enable_reg_reg[2] ;
wire \ip_irpt_enable_reg_reg[3] ;
wire \ip_irpt_enable_reg_reg[4] ;
wire \ip_irpt_enable_reg_reg[5] ;
wire \ip_irpt_enable_reg_reg[6] ;
wire \ip_irpt_enable_reg_reg[7] ;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire last_data_acked_reg;
wire last_data_acked_reg_0;
wire last_data_acked_reg_1;
wire last_data_acked_reg_2;
wire \length_cntr_reg[2] ;
wire \length_cntr_reg[6] ;
wire [0:0]p_0_in;
wire p_10_in;
wire p_11_in;
wire p_12_in;
wire p_13_in;
wire p_14_in;
wire p_15_in;
wire p_16_in;
wire p_17_in;
wire p_18_in;
wire p_19_in;
wire p_1_in;
wire p_1_in13_in;
wire p_1_in16_in;
wire p_1_in19_in;
wire p_1_in22_in;
wire p_1_in25_in;
wire p_1_in28_in;
wire p_1_in31_in;
wire p_1_in34_in;
wire p_20_in;
wire p_21_in;
wire p_22_in;
wire p_23_in;
wire p_24_in;
wire p_25_in;
wire p_26_in;
wire p_27_in;
wire p_28_in;
wire p_29_in;
wire p_2_in;
wire p_30_in;
wire p_31_in;
wire p_3_in;
wire p_5_in;
wire p_6_in;
wire p_7_in;
wire p_8_in;
wire p_9_in;
wire rd_ce_or_reduce_core_cmb;
wire rd_en;
wire receive_ip2bus_error;
wire reset2ip_reset_int;
wire reset_trig0;
wire rx_fifo_empty_i;
wire s_axi4_aclk;
wire [4:0]s_axi4_araddr;
wire s_axi4_aresetn;
wire s_axi4_arvalid;
wire [4:0]s_axi4_awaddr;
wire s_axi4_awvalid;
wire \s_axi4_rdata_i[0]_i_4_n_0 ;
wire \s_axi4_rdata_i[0]_i_5_n_0 ;
wire \s_axi4_rdata_i[1]_i_5_n_0 ;
wire \s_axi4_rdata_i[2]_i_5_n_0 ;
wire \s_axi4_rdata_i[3]_i_5_n_0 ;
wire \s_axi4_rdata_i[5]_i_5_n_0 ;
wire \s_axi4_rdata_i[8]_i_2_n_0 ;
wire \s_axi4_rdata_i[8]_i_3_n_0 ;
wire \s_axi4_rdata_i[8]_i_4_n_0 ;
wire [8:0]\s_axi4_rdata_i_reg[8] ;
wire s_axi4_rready;
wire \s_axi4_rresp_i_reg[1] ;
wire [5:0]s_axi4_wdata;
wire \s_axi4_wdata[31] ;
wire s_axi4_wdata_0_sn_1;
wire s_axi4_wvalid;
wire s_axi4_wvalid_0;
wire s_axi_wready_i;
wire scndry_out;
wire spicr_0_loop_frm_axi_clk;
wire spicr_1_spe_frm_axi_clk;
wire spicr_2_mst_n_slv_frm_axi_clk;
wire spicr_3_cpol_frm_axi_clk;
wire spicr_4_cpha_frm_axi_clk;
wire spicr_5_txfifo_rst_frm_axi_clk;
wire spicr_6_rxfifo_rst_frm_axi_clk;
wire spicr_7_ss_frm_axi_clk;
wire spicr_8_tr_inhibit_frm_axi_clk;
wire spicr_9_lsb_frm_axi_clk;
wire spisel_d1_reg_to_axi_clk;
wire start;
wire sw_rst_cond;
wire sw_rst_cond_d1;
wire transmit_ip2bus_error;
wire wr_ce_or_reduce_core_cmb;
assign s_axi4_wdata_0_sp_1 = s_axi4_wdata_0_sn_1;
LUT5 #(
.INIT(32'hFF7FAA00))
Bus_RNW_reg_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [0]),
.I1(s_axi4_awvalid),
.I2(s_axi4_wvalid),
.I3(s_axi4_arvalid),
.I4(Bus_RNW_reg_reg_0),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(Bus_RNW_reg_reg_0),
.R(1'b0));
LUT6 #(
.INIT(64'h000000000000E200))
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int[3]_i_1
(.I0(spicr_6_rxfifo_rst_frm_axi_clk),
.I1(ip2Bus_WrAck_core_reg),
.I2(s_axi4_wdata[4]),
.I3(p_7_in),
.I4(Bus_RNW_reg_reg_0),
.I5(reset2ip_reset_int),
.O(\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ));
LUT6 #(
.INIT(64'h000000000000E200))
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int[4]_i_1
(.I0(spicr_5_txfifo_rst_frm_axi_clk),
.I1(ip2Bus_WrAck_core_reg),
.I2(s_axi4_wdata[3]),
.I3(p_7_in),
.I4(Bus_RNW_reg_reg_0),
.I5(reset2ip_reset_int),
.O(\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'h40))
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int[9]_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(p_7_in),
.I2(ip2Bus_WrAck_core_reg),
.O(Bus_RNW_reg_reg_1));
LUT5 #(
.INIT(32'hFFFF00FD))
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_1
(.I0(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0 ),
.I1(p_6_in),
.I2(\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 ),
.I3(Bus_RNW_reg_reg_0),
.I4(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0 ),
.O(wr_ce_or_reduce_core_cmb));
LUT5 #(
.INIT(32'h00000001))
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2
(.I0(p_12_in),
.I1(p_14_in),
.I2(\GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31] ),
.I3(p_8_in),
.I4(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0 ),
.O(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0 ));
LUT5 #(
.INIT(32'h00FF00F2))
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3
(.I0(p_5_in),
.I1(almost_full),
.I2(p_3_in),
.I3(Bus_RNW_reg_reg_0),
.I4(p_7_in),
.O(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4
(.I0(p_2_in),
.I1(p_10_in),
.I2(p_11_in),
.I3(p_9_in),
.I4(p_1_in),
.I5(p_13_in),
.O(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFF00FD))
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_i_1
(.I0(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0 ),
.I1(p_6_in),
.I2(\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 ),
.I3(Bus_RNW_reg_reg_0),
.I4(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0 ),
.I5(ip2Bus_WrAck_core_reg_d1),
.O(ip2Bus_WrAck_core_reg0));
LUT5 #(
.INIT(32'hFFFFFD00))
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_1
(.I0(\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0 ),
.I1(p_5_in),
.I2(p_15_in),
.I3(Bus_RNW_reg_reg_0),
.I4(\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2_n_0 ),
.O(rd_ce_or_reduce_core_cmb));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT4 #(
.INIT(16'hCCC8))
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2
(.I0(p_7_in),
.I1(Bus_RNW_reg_reg_0),
.I2(p_3_in),
.I3(p_6_in),
.O(\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000000F2000000))
\FIFO_EXISTS.RX_FIFO_II_i_2
(.I0(s_axi4_rready),
.I1(\guf.underflow_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [2]),
.I3(Bus_RNW_reg_reg_0),
.I4(\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 ),
.I5(empty),
.O(rd_en));
LUT5 #(
.INIT(32'hFFFFFFFE))
\FSM_onehot_axi_full_sm_ps[1]_i_2
(.I0(\length_cntr_reg[2] ),
.I1(\FSM_onehot_axi_full_sm_ps_reg[1] [6]),
.I2(\FSM_onehot_axi_full_sm_ps_reg[1] [5]),
.I3(\FSM_onehot_axi_full_sm_ps_reg[1] [7]),
.I4(\FSM_onehot_axi_full_sm_ps_reg[1] [4]),
.O(\length_cntr_reg[6] ));
LUT6 #(
.INIT(64'hFFFFFFFFFFF80000))
\FSM_onehot_axi_full_sm_ps[3]_i_1
(.I0(\FSM_onehot_axi_full_sm_ps_reg[3] ),
.I1(data_valid),
.I2(\FSM_onehot_axi_full_sm_ps_reg[3]_0 ),
.I3(Bus_RNW_reg_reg_4),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [2]),
.I5(\FSM_onehot_axi_full_sm_ps_reg[3]_1 ),
.O(D));
LUT5 #(
.INIT(32'hFFBBBFBF))
\FSM_onehot_axi_full_sm_ps[6]_i_2
(.I0(\length_cntr_reg[6] ),
.I1(s_axi4_wvalid),
.I2(s_axi_wready_i),
.I3(almost_full),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [4]),
.O(s_axi4_wvalid_0));
LUT6 #(
.INIT(64'h0044034700000000))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(s_axi4_araddr[0]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[0]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0 ),
.O(ce_expnd_i_31));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_31),
.Q(p_31_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000088808))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ),
.I2(s_axi4_awaddr[2]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.O(ce_expnd_i_21));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_21),
.Q(p_21_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0008880800000000))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.I2(s_axi4_awaddr[2]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ),
.O(ce_expnd_i_20));
FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_20),
.Q(p_20_in),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h00088808))
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I2(s_axi4_awaddr[4]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[4]),
.O(ce_expnd_i_19));
FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_19),
.Q(p_19_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h202A000A20200000))
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I1(s_axi4_araddr[1]),
.I2(s_axi4_arvalid),
.I3(s_axi4_awaddr[1]),
.I4(s_axi4_araddr[2]),
.I5(s_axi4_awaddr[2]),
.O(ce_expnd_i_18));
FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_18),
.Q(p_18_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000A80800000000))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I1(s_axi4_awaddr[2]),
.I2(s_axi4_arvalid),
.I3(s_axi4_araddr[2]),
.I4(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.I5(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ),
.O(ce_expnd_i_17));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2
(.I0(s_axi4_araddr[0]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[0]),
.O(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'h5050300000003000))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3
(.I0(s_axi4_araddr[4]),
.I1(s_axi4_awaddr[4]),
.I2(start),
.I3(s_axi4_awaddr[1]),
.I4(s_axi4_arvalid),
.I5(s_axi4_araddr[1]),
.O(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_17),
.Q(p_17_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hC000A0A0C0000000))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1
(.I0(s_axi4_awaddr[1]),
.I1(s_axi4_araddr[1]),
.I2(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_arvalid),
.I5(s_axi4_awaddr[2]),
.O(ce_expnd_i_16));
LUT6 #(
.INIT(64'h0000008080800080))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I2(start),
.I3(s_axi4_awaddr[4]),
.I4(s_axi4_arvalid),
.I5(s_axi4_araddr[4]),
.O(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_16),
.Q(p_16_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT5 #(
.INIT(32'h22200020))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I2(s_axi4_awaddr[4]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[4]),
.O(ce_expnd_i_15));
FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_15),
.Q(p_15_in),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h80888000))
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0 ),
.I2(s_axi4_araddr[0]),
.I3(s_axi4_arvalid),
.I4(s_axi4_awaddr[0]),
.O(ce_expnd_i_14));
FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_14),
.Q(p_14_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000440347))
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1
(.I0(s_axi4_araddr[0]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[0]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0 ),
.O(ce_expnd_i_13));
FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_13),
.Q(p_13_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000047034400))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1
(.I0(s_axi4_araddr[2]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[2]),
.I3(s_axi4_araddr[0]),
.I4(s_axi4_awaddr[0]),
.I5(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0 ),
.O(ce_expnd_i_12));
FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_12),
.Q(p_12_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h202A000A20200000))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0 ),
.I1(s_axi4_araddr[2]),
.I2(s_axi4_arvalid),
.I3(s_axi4_awaddr[2]),
.I4(s_axi4_araddr[0]),
.I5(s_axi4_awaddr[0]),
.O(\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi4_aclk),
.CE(start),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0 ),
.Q(p_30_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT5 #(
.INIT(32'h22200020))
\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I2(s_axi4_awaddr[4]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[4]),
.O(ce_expnd_i_11));
FDRE \GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_11),
.Q(p_11_in),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h80888000))
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0 ),
.I2(s_axi4_araddr[0]),
.I3(s_axi4_arvalid),
.I4(s_axi4_awaddr[0]),
.O(ce_expnd_i_10));
LUT6 #(
.INIT(64'h000000C0A0A000C0))
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2
(.I0(s_axi4_araddr[4]),
.I1(s_axi4_awaddr[4]),
.I2(start),
.I3(s_axi4_awaddr[3]),
.I4(s_axi4_arvalid),
.I5(s_axi4_araddr[3]),
.O(\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_10),
.Q(p_10_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000047034400))
\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1
(.I0(s_axi4_araddr[0]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[0]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0 ),
.O(ce_expnd_i_9));
FDRE \GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_9),
.Q(p_9_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h00000000B8308800))
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1
(.I0(s_axi4_araddr[0]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[0]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0 ),
.O(ce_expnd_i_8));
LUT6 #(
.INIT(64'hDFDFDFFFFFFFDFFF))
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I2(start),
.I3(s_axi4_awaddr[4]),
.I4(s_axi4_arvalid),
.I5(s_axi4_araddr[4]),
.O(\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_8),
.Q(p_8_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT5 #(
.INIT(32'hA8080000))
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0 ),
.I1(s_axi4_awaddr[4]),
.I2(s_axi4_arvalid),
.I3(s_axi4_araddr[4]),
.I4(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.O(ce_expnd_i_7));
LUT6 #(
.INIT(64'h0000000000440347))
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2
(.I0(s_axi4_araddr[1]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[1]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_7),
.Q(p_7_in),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h80888000))
\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3_n_0 ),
.I2(s_axi4_araddr[0]),
.I3(s_axi4_arvalid),
.I4(s_axi4_awaddr[0]),
.O(ce_expnd_i_6));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT5 #(
.INIT(32'h00053305))
\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2
(.I0(s_axi4_awaddr[2]),
.I1(s_axi4_araddr[2]),
.I2(s_axi4_awaddr[1]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[1]),
.O(\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[25].ce_out_i_reg[25]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_6),
.Q(p_6_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000440347))
\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1
(.I0(s_axi4_araddr[0]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[0]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0 ),
.O(ce_expnd_i_5));
FDRE \GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_5),
.Q(p_5_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000047034400))
\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1
(.I0(s_axi4_araddr[2]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[2]),
.I3(s_axi4_araddr[0]),
.I4(s_axi4_awaddr[0]),
.I5(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0 ),
.O(ce_expnd_i_4));
FDRE \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_4),
.Q(\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT5 #(
.INIT(32'hA8080000))
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0 ),
.I1(s_axi4_awaddr[4]),
.I2(s_axi4_arvalid),
.I3(s_axi4_araddr[4]),
.I4(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.O(ce_expnd_i_3));
LUT6 #(
.INIT(64'h0000000047034400))
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2
(.I0(s_axi4_araddr[1]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[1]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hB8))
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3
(.I0(s_axi4_araddr[3]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[3]),
.O(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_3),
.Q(p_3_in),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT5 #(
.INIT(32'h80888000))
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3_n_0 ),
.I2(s_axi4_araddr[0]),
.I3(s_axi4_arvalid),
.I4(s_axi4_awaddr[0]),
.O(ce_expnd_i_2));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT5 #(
.INIT(32'h000ACC0A))
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2
(.I0(s_axi4_awaddr[2]),
.I1(s_axi4_araddr[2]),
.I2(s_axi4_awaddr[1]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[1]),
.O(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'hC0AAC00000000000))
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3
(.I0(s_axi4_awaddr[3]),
.I1(s_axi4_araddr[3]),
.I2(s_axi4_araddr[4]),
.I3(s_axi4_arvalid),
.I4(s_axi4_awaddr[4]),
.I5(start),
.O(\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[29].ce_out_i_reg[29]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_2),
.Q(p_2_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h00000000000002A2))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ),
.I1(s_axi4_awaddr[2]),
.I2(s_axi4_arvalid),
.I3(s_axi4_araddr[2]),
.I4(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.I5(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.O(ce_expnd_i_29));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_29),
.Q(p_29_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000047034400))
\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1
(.I0(s_axi4_araddr[0]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[0]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0 ),
.O(ce_expnd_i_1));
FDRE \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_1),
.Q(p_1_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFFFFFFFFFFBABABA))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_4_n_0 ),
.I1(s_axi4_wvalid_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [4]),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1 ),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [5]),
.I5(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_5_n_0 ),
.O(cs_ce_clr));
LUT4 #(
.INIT(16'hAA80))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [0]),
.I1(s_axi4_awvalid),
.I2(s_axi4_wvalid),
.I3(s_axi4_arvalid),
.O(start));
LUT6 #(
.INIT(64'h00000000B8308800))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_3
(.I0(s_axi4_araddr[0]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[0]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0 ),
.O(ce_expnd_i_0));
LUT4 #(
.INIT(16'hFE00))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_4
(.I0(Bus_RNW_reg_reg_4),
.I1(\FSM_onehot_axi_full_sm_ps_reg[3]_0 ),
.I2(data_valid),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [2]),
.O(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_4_n_0 ));
LUT5 #(
.INIT(32'h4F4FFF4F))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_5
(.I0(\length_cntr_reg[6] ),
.I1(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [1]),
.I2(s_axi4_aresetn),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [3]),
.I4(s_axi4_rready),
.O(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_5_n_0 ));
LUT6 #(
.INIT(64'h777FFF7FFFFFFFFF))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6
(.I0(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0 ),
.I1(start),
.I2(s_axi4_awaddr[4]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[4]),
.I5(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'hB8))
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7
(.I0(s_axi4_araddr[1]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[1]),
.O(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg[31]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31] ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000002A20000))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.I1(s_axi4_awaddr[2]),
.I2(s_axi4_arvalid),
.I3(s_axi4_araddr[2]),
.I4(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ),
.I5(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.O(ce_expnd_i_28));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_28),
.Q(p_28_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h202A000A20200000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0 ),
.I1(s_axi4_araddr[0]),
.I2(s_axi4_arvalid),
.I3(s_axi4_awaddr[0]),
.I4(s_axi4_araddr[2]),
.I5(s_axi4_awaddr[2]),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi4_aclk),
.CE(start),
.D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
.Q(p_27_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h8A800A0080800000))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0 ),
.I1(s_axi4_araddr[0]),
.I2(s_axi4_arvalid),
.I3(s_axi4_awaddr[0]),
.I4(s_axi4_araddr[2]),
.I5(s_axi4_awaddr[2]),
.O(ce_expnd_i_26));
LUT6 #(
.INIT(64'h0000000000004700))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2
(.I0(s_axi4_araddr[4]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[4]),
.I3(start),
.I4(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I5(\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_26),
.Q(p_26_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0000000000E20000))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1
(.I0(s_axi4_awaddr[2]),
.I1(s_axi4_arvalid),
.I2(s_axi4_araddr[2]),
.I3(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.I4(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ),
.I5(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.O(ce_expnd_i_25));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_25),
.Q(p_25_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h00000000A8080000))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0 ),
.I1(s_axi4_awaddr[2]),
.I2(s_axi4_arvalid),
.I3(s_axi4_araddr[2]),
.I4(\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0 ),
.I5(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.O(ce_expnd_i_24));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_24),
.Q(p_24_in),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h00088808))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0 ),
.I2(s_axi4_awaddr[4]),
.I3(s_axi4_arvalid),
.I4(s_axi4_araddr[4]),
.O(ce_expnd_i_23));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_23),
.Q(p_23_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h0044034700000000))
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1
(.I0(s_axi4_araddr[1]),
.I1(s_axi4_arvalid),
.I2(s_axi4_awaddr[1]),
.I3(s_axi4_araddr[2]),
.I4(s_axi4_awaddr[2]),
.I5(\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0 ),
.O(ce_expnd_i_22));
FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]
(.C(s_axi4_aclk),
.CE(start),
.D(ce_expnd_i_22),
.Q(p_22_in),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hAAAAAA6AAAAAAAAA))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1
(.I0(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.I1(Q),
.I2(p_23_in),
.I3(Bus_RNW_reg_reg_0),
.I4(irpt_wrack_d1),
.I5(s_axi4_wdata[0]),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ));
LUT6 #(
.INIT(64'hAAAAAA6AAAAAAAAA))
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1
(.I0(p_1_in34_in),
.I1(Q),
.I2(p_23_in),
.I3(Bus_RNW_reg_reg_0),
.I4(irpt_wrack_d1),
.I5(s_axi4_wdata[1]),
.O(\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT4 #(
.INIT(16'h0008))
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_2
(.I0(Q),
.I1(p_23_in),
.I2(Bus_RNW_reg_reg_0),
.I3(irpt_wrack_d1),
.O(\bus2ip_BE_reg_reg[3] ));
LUT6 #(
.INIT(64'hAAAAAA6AAAAAAAAA))
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1
(.I0(p_1_in28_in),
.I1(Q),
.I2(p_23_in),
.I3(Bus_RNW_reg_reg_0),
.I4(irpt_wrack_d1),
.I5(s_axi4_wdata[2]),
.O(\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT2 #(
.INIT(4'h2))
\SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I_i_1
(.I0(p_7_in),
.I1(Bus_RNW_reg_reg_0),
.O(bus2ip_wrce_int));
LUT5 #(
.INIT(32'hEFFF2000))
\SPISSR_WR_GEN[0].SPISSR_Data_reg[0]_i_1
(.I0(s_axi4_wdata[0]),
.I1(Bus_RNW_reg_reg_0),
.I2(p_3_in),
.I3(ip2Bus_WrAck_core_reg),
.I4(SPISSR_frm_axi_clk),
.O(s_axi4_wdata_0_sn_1));
LUT6 #(
.INIT(64'h0040404000004000))
Transmit_ip2bus_error_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(p_5_in),
.I2(Tx_FIFO_Full_int),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [4]),
.I4(almost_full),
.I5(s_axi_wready_i),
.O(Transmit_ip2bus_error0));
LUT6 #(
.INIT(64'h4400440044004000))
intr2bus_rdack_i_1
(.I0(irpt_rdack_d1),
.I1(Bus_RNW_reg_reg_0),
.I2(p_24_in),
.I3(Q),
.I4(p_21_in),
.I5(p_23_in),
.O(intr2bus_rdack0));
LUT6 #(
.INIT(64'h0000505000005040))
intr2bus_wrack_i_1
(.I0(irpt_wrack_d1),
.I1(p_21_in),
.I2(Q),
.I3(p_23_in),
.I4(Bus_RNW_reg_reg_0),
.I5(p_24_in),
.O(interrupt_wrce_strb));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT2 #(
.INIT(4'h2))
ip2Bus_RdAck_intr_reg_hole_d1_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0),
.O(intr_controller_rd_ce_or_reduce));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'h02))
ip2Bus_RdAck_intr_reg_hole_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0),
.I2(ip2Bus_RdAck_intr_reg_hole_d1),
.O(ip2Bus_RdAck_intr_reg_hole0));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT2 #(
.INIT(4'h1))
ip2Bus_WrAck_intr_reg_hole_d1_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0),
.O(Bus_RNW_reg_reg_3));
LUT5 #(
.INIT(32'h00000002))
ip2Bus_WrAck_intr_reg_hole_d1_i_2
(.I0(ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0),
.I1(ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0),
.I2(p_17_in),
.I3(p_25_in),
.I4(p_20_in),
.O(ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
ip2Bus_WrAck_intr_reg_hole_d1_i_3
(.I0(p_16_in),
.I1(p_31_in),
.I2(p_28_in),
.I3(p_19_in),
.I4(p_29_in),
.I5(p_30_in),
.O(ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0));
LUT4 #(
.INIT(16'hFFFE))
ip2Bus_WrAck_intr_reg_hole_d1_i_4
(.I0(p_26_in),
.I1(p_18_in),
.I2(p_27_in),
.I3(p_22_in),
.O(ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT3 #(
.INIT(8'h01))
ip2Bus_WrAck_intr_reg_hole_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0),
.I2(ip2Bus_WrAck_intr_reg_hole_d1),
.O(ip2Bus_WrAck_intr_reg_hole0));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'h40))
\ip_irpt_enable_reg[8]_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(Q),
.I2(p_21_in),
.O(Bus_RNW_reg_reg_2));
LUT5 #(
.INIT(32'hEFFF2000))
ipif_glbl_irpt_enable_reg_i_1
(.I0(s_axi4_wdata[5]),
.I1(Bus_RNW_reg_reg_0),
.I2(p_24_in),
.I3(Q),
.I4(p_0_in),
.O(\s_axi4_wdata[31] ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT5 #(
.INIT(32'hA0A0A080))
irpt_rdack_d1_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(p_24_in),
.I2(Q),
.I3(p_21_in),
.I4(p_23_in),
.O(irpt_rdack));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT5 #(
.INIT(32'h00CC00C8))
irpt_wrack_d1_i_1
(.I0(p_21_in),
.I1(Q),
.I2(p_23_in),
.I3(Bus_RNW_reg_reg_0),
.I4(p_24_in),
.O(irpt_wrack));
LUT6 #(
.INIT(64'h00000000AAAA88A8))
last_data_acked_i_1
(.I0(last_data_acked_reg),
.I1(last_data_acked_reg_0),
.I2(D),
.I3(last_data_acked_reg_1),
.I4(last_data_acked_reg_2),
.I5(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [0]),
.O(\FSM_onehot_axi_full_sm_ps_reg[0] ));
LUT4 #(
.INIT(16'hFFFE))
\length_cntr[4]_i_2
(.I0(\FSM_onehot_axi_full_sm_ps_reg[1] [2]),
.I1(\FSM_onehot_axi_full_sm_ps_reg[1] [3]),
.I2(\FSM_onehot_axi_full_sm_ps_reg[1] [0]),
.I3(\FSM_onehot_axi_full_sm_ps_reg[1] [1]),
.O(\length_cntr_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT4 #(
.INIT(16'h0004))
reset_trig_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(p_15_in),
.I2(\s_axi4_rresp_i_reg[1] ),
.I3(sw_rst_cond_d1),
.O(reset_trig0));
LUT6 #(
.INIT(64'hFFFFFFFF40000000))
\s_axi4_rdata_i[0]_i_2
(.I0(p_23_in),
.I1(p_21_in),
.I2(Q),
.I3(Bus_RNW_reg_reg_0),
.I4(\s_axi4_rdata_i_reg[8] [0]),
.I5(\s_axi4_rdata_i[0]_i_4_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0 ));
LUT6 #(
.INIT(64'hFFF8F8F8F8F8F8F8))
\s_axi4_rdata_i[0]_i_4
(.I0(\s_axi4_rdata_i[8]_i_4_n_0 ),
.I1(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.I2(\s_axi4_rdata_i[0]_i_5_n_0 ),
.I3(SPISSR_frm_axi_clk),
.I4(p_3_in),
.I5(Bus_RNW_reg_reg_0),
.O(\s_axi4_rdata_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFF00A800A800A800))
\s_axi4_rdata_i[0]_i_5
(.I0(p_6_in),
.I1(empty),
.I2(rx_fifo_empty_i),
.I3(Bus_RNW_reg_reg_0),
.I4(p_7_in),
.I5(spicr_0_loop_frm_axi_clk),
.O(\s_axi4_rdata_i[0]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFF4F4F4))
\s_axi4_rdata_i[1]_i_3
(.I0(\s_axi4_rdata_i[8]_i_2_n_0 ),
.I1(\s_axi4_rdata_i_reg[8] [1]),
.I2(\s_axi4_rdata_i[1]_i_5_n_0 ),
.I3(p_1_in34_in),
.I4(\s_axi4_rdata_i[8]_i_4_n_0 ),
.O(\ip_irpt_enable_reg_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT5 #(
.INIT(32'hF0808080))
\s_axi4_rdata_i[1]_i_5
(.I0(p_6_in),
.I1(scndry_out),
.I2(Bus_RNW_reg_reg_0),
.I3(p_7_in),
.I4(spicr_1_spe_frm_axi_clk),
.O(\s_axi4_rdata_i[1]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFFF4F4F4))
\s_axi4_rdata_i[2]_i_3
(.I0(\s_axi4_rdata_i[8]_i_2_n_0 ),
.I1(\s_axi4_rdata_i_reg[8] [2]),
.I2(\s_axi4_rdata_i[2]_i_5_n_0 ),
.I3(p_1_in31_in),
.I4(\s_axi4_rdata_i[8]_i_4_n_0 ),
.O(\ip_irpt_enable_reg_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT5 #(
.INIT(32'hF0808080))
\s_axi4_rdata_i[2]_i_5
(.I0(p_6_in),
.I1(Tx_FIFO_Empty_SPISR_to_axi_clk),
.I2(Bus_RNW_reg_reg_0),
.I3(p_7_in),
.I4(spicr_2_mst_n_slv_frm_axi_clk),
.O(\s_axi4_rdata_i[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'h1000000000000000))
\s_axi4_rdata_i[31]_i_3
(.I0(p_23_in),
.I1(p_21_in),
.I2(Bus_RNW_reg_reg_0),
.I3(p_24_in),
.I4(Q),
.I5(p_0_in),
.O(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1 [2]));
LUT5 #(
.INIT(32'hFFF4F4F4))
\s_axi4_rdata_i[3]_i_3
(.I0(\s_axi4_rdata_i[8]_i_2_n_0 ),
.I1(\s_axi4_rdata_i_reg[8] [3]),
.I2(\s_axi4_rdata_i[3]_i_5_n_0 ),
.I3(p_1_in28_in),
.I4(\s_axi4_rdata_i[8]_i_4_n_0 ),
.O(\ip_irpt_enable_reg_reg[3] ));
LUT5 #(
.INIT(32'hF0808080))
\s_axi4_rdata_i[3]_i_5
(.I0(p_6_in),
.I1(Tx_FIFO_Full_int),
.I2(Bus_RNW_reg_reg_0),
.I3(p_7_in),
.I4(spicr_3_cpol_frm_axi_clk),
.O(\s_axi4_rdata_i[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFF44F444F444F4))
\s_axi4_rdata_i[4]_i_2
(.I0(\s_axi4_rdata_i[8]_i_2_n_0 ),
.I1(\s_axi4_rdata_i_reg[8] [4]),
.I2(spicr_4_cpha_frm_axi_clk),
.I3(\s_axi4_rdata_i[8]_i_3_n_0 ),
.I4(p_1_in25_in),
.I5(\s_axi4_rdata_i[8]_i_4_n_0 ),
.O(\ip_irpt_enable_reg_reg[4] ));
LUT5 #(
.INIT(32'hFFF4F4F4))
\s_axi4_rdata_i[5]_i_3
(.I0(\s_axi4_rdata_i[8]_i_2_n_0 ),
.I1(\s_axi4_rdata_i_reg[8] [5]),
.I2(\s_axi4_rdata_i[5]_i_5_n_0 ),
.I3(p_1_in22_in),
.I4(\s_axi4_rdata_i[8]_i_4_n_0 ),
.O(\ip_irpt_enable_reg_reg[5] ));
LUT5 #(
.INIT(32'hF0808080))
\s_axi4_rdata_i[5]_i_5
(.I0(p_6_in),
.I1(spisel_d1_reg_to_axi_clk),
.I2(Bus_RNW_reg_reg_0),
.I3(p_7_in),
.I4(spicr_5_txfifo_rst_frm_axi_clk),
.O(\s_axi4_rdata_i[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFF44F444F444F4))
\s_axi4_rdata_i[6]_i_2
(.I0(\s_axi4_rdata_i[8]_i_2_n_0 ),
.I1(\s_axi4_rdata_i_reg[8] [6]),
.I2(spicr_6_rxfifo_rst_frm_axi_clk),
.I3(\s_axi4_rdata_i[8]_i_3_n_0 ),
.I4(p_1_in19_in),
.I5(\s_axi4_rdata_i[8]_i_4_n_0 ),
.O(\ip_irpt_enable_reg_reg[6] ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT3 #(
.INIT(8'hDF))
\s_axi4_rdata_i[6]_i_6
(.I0(p_1_in),
.I1(empty),
.I2(Bus_RNW_reg_reg_0),
.O(\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]_0 ));
LUT6 #(
.INIT(64'h777777777F777F7F))
\s_axi4_rdata_i[7]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0 ),
.I1(Bus_RNW_reg_reg_0),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 [2]),
.I3(\guf.underflow_i_reg ),
.I4(s_axi4_rready),
.I5(ip2Bus_RdAck_core_reg),
.O(\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_1 ));
LUT6 #(
.INIT(64'hF444F444FFFFF444))
\s_axi4_rdata_i[7]_i_5
(.I0(\s_axi4_rdata_i[8]_i_2_n_0 ),
.I1(\s_axi4_rdata_i_reg[8] [7]),
.I2(p_1_in16_in),
.I3(\s_axi4_rdata_i[8]_i_4_n_0 ),
.I4(spicr_7_ss_frm_axi_clk),
.I5(\s_axi4_rdata_i[8]_i_3_n_0 ),
.O(\ip_irpt_enable_reg_reg[7] ));
LUT6 #(
.INIT(64'hFFFF44F444F444F4))
\s_axi4_rdata_i[8]_i_1
(.I0(\s_axi4_rdata_i[8]_i_2_n_0 ),
.I1(\s_axi4_rdata_i_reg[8] [8]),
.I2(spicr_8_tr_inhibit_frm_axi_clk),
.I3(\s_axi4_rdata_i[8]_i_3_n_0 ),
.I4(p_1_in13_in),
.I5(\s_axi4_rdata_i[8]_i_4_n_0 ),
.O(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1 [0]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT4 #(
.INIT(16'hBFFF))
\s_axi4_rdata_i[8]_i_2
(.I0(p_23_in),
.I1(p_21_in),
.I2(Q),
.I3(Bus_RNW_reg_reg_0),
.O(\s_axi4_rdata_i[8]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT2 #(
.INIT(4'h7))
\s_axi4_rdata_i[8]_i_3
(.I0(Bus_RNW_reg_reg_0),
.I1(p_7_in),
.O(\s_axi4_rdata_i[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'h80))
\s_axi4_rdata_i[8]_i_4
(.I0(Bus_RNW_reg_reg_0),
.I1(p_23_in),
.I2(Q),
.O(\s_axi4_rdata_i[8]_i_4_n_0 ));
LUT3 #(
.INIT(8'h80))
\s_axi4_rdata_i[9]_i_1
(.I0(spicr_9_lsb_frm_axi_clk),
.I1(p_7_in),
.I2(Bus_RNW_reg_reg_0),
.O(\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1 [1]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT5 #(
.INIT(32'hFFFFFF40))
\s_axi4_rresp_i[1]_i_1
(.I0(Bus_RNW_reg_reg_0),
.I1(p_15_in),
.I2(\s_axi4_rresp_i_reg[1] ),
.I3(transmit_ip2bus_error),
.I4(receive_ip2bus_error),
.O(Bus_RNW_reg_reg_4));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'h04))
sw_rst_cond_d1_i_1
(.I0(\s_axi4_rresp_i_reg[1] ),
.I1(p_15_in),
.I2(Bus_RNW_reg_reg_0),
.O(sw_rst_cond));
LUT6 #(
.INIT(64'h0000040004040400))
\xpm_fifo_instance.xpm_fifo_async_inst_i_2
(.I0(Bus_RNW_reg_reg_0),
.I1(p_5_in),
.I2(almost_full),
.I3(ip2Bus_WrAck_core_reg),
.I4(\gwack.wr_ack_i_reg ),
.I5(\gwack.wr_ack_i_reg_0 ),
.O(IP2Bus_WrAck_transmit_enable));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_cntrl_reg
(spicr_bits_7_8_frm_axi_clk,
spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk,
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0 ,
spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk,
spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0 ,
spicr_6_rxfifo_rst_frm_axi_clk,
\s_axi4_wdata[8] ,
D,
reset2ip_reset_int,
bus2ip_wrce_int,
s_axi4_wdata,
s_axi4_aclk,
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_1 ,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0 ,
\ip_irpt_enable_reg_reg[8] ,
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8] ,
p_1_in13_in,
data_Exists_RcFIFO_int_d1,
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 );
output [1:0]spicr_bits_7_8_frm_axi_clk;
output spicr_0_loop_frm_axi_clk;
output spicr_1_spe_frm_axi_clk;
output \CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0 ;
output spicr_3_cpol_frm_axi_clk;
output spicr_4_cpha_frm_axi_clk;
output spicr_7_ss_frm_axi_clk;
output spicr_8_tr_inhibit_frm_axi_clk;
output spicr_9_lsb_frm_axi_clk;
output \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0 ;
output spicr_6_rxfifo_rst_frm_axi_clk;
output \s_axi4_wdata[8] ;
output [0:0]D;
input reset2ip_reset_int;
input [0:0]bus2ip_wrce_int;
input [7:0]s_axi4_wdata;
input s_axi4_aclk;
input \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ;
input \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_1 ;
input \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0 ;
input \ip_irpt_enable_reg_reg[8] ;
input \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8] ;
input p_1_in13_in;
input data_Exists_RcFIFO_int_d1;
input \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 ;
wire \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0 ;
wire \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0 ;
wire \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_1 ;
wire \CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0 ;
wire \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ;
wire [0:0]D;
wire \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8] ;
wire \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 ;
wire [0:0]bus2ip_wrce_int;
wire data_Exists_RcFIFO_int_d1;
wire \ip_irpt_enable_reg_reg[8] ;
wire p_1_in13_in;
wire reset2ip_reset_int;
wire s_axi4_aclk;
wire [7:0]s_axi4_wdata;
wire \s_axi4_wdata[8] ;
wire spicr_0_loop_frm_axi_clk;
wire spicr_1_spe_frm_axi_clk;
wire spicr_3_cpol_frm_axi_clk;
wire spicr_4_cpha_frm_axi_clk;
wire spicr_6_rxfifo_rst_frm_axi_clk;
wire spicr_7_ss_frm_axi_clk;
wire spicr_8_tr_inhibit_frm_axi_clk;
wire spicr_9_lsb_frm_axi_clk;
wire [1:0]spicr_bits_7_8_frm_axi_clk;
FDSE \CONTROL_REG_1_2_GENERATE[1].SPICR_data_int_reg[1]
(.C(s_axi4_aclk),
.CE(\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ),
.D(s_axi4_wdata[6]),
.Q(spicr_8_tr_inhibit_frm_axi_clk),
.S(reset2ip_reset_int));
FDSE \CONTROL_REG_1_2_GENERATE[2].SPICR_data_int_reg[2]
(.C(s_axi4_aclk),
.CE(\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ),
.D(s_axi4_wdata[5]),
.Q(spicr_7_ss_frm_axi_clk),
.S(reset2ip_reset_int));
FDRE \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0 ),
.Q(spicr_6_rxfifo_rst_frm_axi_clk),
.R(1'b0));
FDRE \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_1 ),
.Q(\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0 ),
.R(1'b0));
FDRE \CONTROL_REG_5_9_GENERATE[5].SPICR_data_int_reg[5]
(.C(s_axi4_aclk),
.CE(\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ),
.D(s_axi4_wdata[4]),
.Q(spicr_4_cpha_frm_axi_clk),
.R(reset2ip_reset_int));
FDRE \CONTROL_REG_5_9_GENERATE[6].SPICR_data_int_reg[6]
(.C(s_axi4_aclk),
.CE(\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ),
.D(s_axi4_wdata[3]),
.Q(spicr_3_cpol_frm_axi_clk),
.R(reset2ip_reset_int));
FDRE \CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]
(.C(s_axi4_aclk),
.CE(\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ),
.D(s_axi4_wdata[2]),
.Q(\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0 ),
.R(reset2ip_reset_int));
FDRE \CONTROL_REG_5_9_GENERATE[8].SPICR_data_int_reg[8]
(.C(s_axi4_aclk),
.CE(\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ),
.D(s_axi4_wdata[1]),
.Q(spicr_1_spe_frm_axi_clk),
.R(reset2ip_reset_int));
FDRE \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]
(.C(s_axi4_aclk),
.CE(\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ),
.D(s_axi4_wdata[0]),
.Q(spicr_0_loop_frm_axi_clk),
.R(reset2ip_reset_int));
LUT6 #(
.INIT(64'hFFFFFFFFD5FF2A00))
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1
(.I0(s_axi4_wdata[6]),
.I1(\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0 ),
.I2(\ip_irpt_enable_reg_reg[8] ),
.I3(\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8] ),
.I4(p_1_in13_in),
.I5(\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0 ),
.O(\s_axi4_wdata[8] ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT4 #(
.INIT(16'h0111))
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2
(.I0(data_Exists_RcFIFO_int_d1),
.I1(\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 ),
.I2(\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0 ),
.I3(\ip_irpt_enable_reg_reg[8] ),
.O(\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0 ));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I
(.C(s_axi4_aclk),
.CE(bus2ip_wrce_int),
.D(s_axi4_wdata[2]),
.Q(spicr_bits_7_8_frm_axi_clk[1]),
.R(reset2ip_reset_int));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\SPICR_REG_78_GENERATE[8].SPI_TRISTATE_CONTROL_I
(.C(s_axi4_aclk),
.CE(bus2ip_wrce_int),
.D(s_axi4_wdata[1]),
.Q(spicr_bits_7_8_frm_axi_clk[0]),
.R(reset2ip_reset_int));
FDRE \SPICR_data_int_reg[0]
(.C(s_axi4_aclk),
.CE(\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 ),
.D(s_axi4_wdata[7]),
.Q(spicr_9_lsb_frm_axi_clk),
.R(reset2ip_reset_int));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'h2A))
\ip_irpt_enable_reg[8]_i_2
(.I0(s_axi4_wdata[6]),
.I1(\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0 ),
.I2(\ip_irpt_enable_reg_reg[8] ),
.O(D));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_core_interface
(spisel_d1_reg_to_axi_clk,
Tx_FIFO_Empty_SPISR_to_axi_clk,
spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk,
spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk,
SPISSR_frm_axi_clk,
empty,
data_valid,
almost_full,
sck_t,
io0_t,
ss_t,
io1_t,
sck_o,
receive_ip2bus_error,
transmit_ip2bus_error,
sw_rst_cond_d1,
irpt_wrack_d1,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ,
p_1_in34_in,
p_1_in31_in,
p_1_in28_in,
p_1_in25_in,
p_1_in22_in,
p_1_in19_in,
p_1_in16_in,
p_1_in13_in,
irpt_rdack_d1,
ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_core_reg,
ip2Bus_WrAck_intr_reg_hole_d1,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_RdAck_core_reg,
\RESET_FLOPS[15].RST_FLOPS ,
io1_o,
ss_o,
spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk,
p_0_in,
Tx_FIFO_Full_int,
rx_fifo_empty_i,
intr2bus_wrack_reg,
E,
\gen_fwft.gdvld_fwft.data_valid_fwft_reg ,
D,
intr2bus_rdack_reg,
scndry_out,
ip2intc_irpt,
\ip_irpt_enable_reg_reg[8] ,
reset2ip_reset_int,
s_axi4_aclk,
ext_spi_clk,
rd_en,
IP2Bus_WrAck_transmit_enable,
s_axi4_wdata,
bus2ip_wrce_int,
Transmit_ip2bus_error0,
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9] ,
bus2ip_reset_ipif_inverted,
sw_rst_cond,
reset_trig0,
irpt_wrack,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ,
interrupt_wrce_strb,
irpt_rdack,
intr2bus_rdack0,
wr_ce_or_reduce_core_cmb,
ip2Bus_WrAck_core_reg0,
ip2Bus_WrAck_intr_reg_hole_d1_reg_0,
ip2Bus_WrAck_intr_reg_hole0,
intr_controller_rd_ce_or_reduce,
ip2Bus_RdAck_intr_reg_hole0,
rd_ce_or_reduce_core_cmb,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] ,
ipif_glbl_irpt_enable_reg_reg,
ip2bus_error_int,
burst_tr_int,
s_axi4_rready,
Q,
\s_axi4_rdata_i_reg[31] ,
\s_axi4_rdata_i_reg[0] ,
\s_axi4_rdata_i_reg[7] ,
\s_axi4_rdata_i_reg[1] ,
\s_axi4_rdata_i_reg[2] ,
\s_axi4_rdata_i_reg[3] ,
\s_axi4_rdata_i_reg[4] ,
\s_axi4_rdata_i_reg[5] ,
\s_axi4_rdata_i_reg[6] ,
\s_axi4_rdata_i_reg[7]_0 ,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ,
p_4_in,
Bus_RNW_reg,
p_2_in,
p_1_in,
\s_axi4_rdata_i_reg[5]_0 ,
\ip_irpt_enable_reg_reg[8]_0 ,
io1_i_sync,
io0_i_sync);
output spisel_d1_reg_to_axi_clk;
output Tx_FIFO_Empty_SPISR_to_axi_clk;
output spicr_0_loop_frm_axi_clk;
output spicr_1_spe_frm_axi_clk;
output spicr_2_mst_n_slv_frm_axi_clk;
output spicr_3_cpol_frm_axi_clk;
output spicr_4_cpha_frm_axi_clk;
output spicr_7_ss_frm_axi_clk;
output spicr_8_tr_inhibit_frm_axi_clk;
output spicr_9_lsb_frm_axi_clk;
output SPISSR_frm_axi_clk;
output empty;
output data_valid;
output almost_full;
output sck_t;
output io0_t;
output ss_t;
output io1_t;
output sck_o;
output receive_ip2bus_error;
output transmit_ip2bus_error;
output sw_rst_cond_d1;
output irpt_wrack_d1;
output \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
output p_1_in34_in;
output p_1_in31_in;
output p_1_in28_in;
output p_1_in25_in;
output p_1_in22_in;
output p_1_in19_in;
output p_1_in16_in;
output p_1_in13_in;
output irpt_rdack_d1;
output ip2Bus_WrAck_core_reg_d1;
output ip2Bus_WrAck_core_reg;
output ip2Bus_WrAck_intr_reg_hole_d1;
output ip2Bus_RdAck_intr_reg_hole_d1;
output ip2Bus_RdAck_core_reg;
output \RESET_FLOPS[15].RST_FLOPS ;
output io1_o;
output [0:0]ss_o;
output spicr_5_txfifo_rst_frm_axi_clk;
output spicr_6_rxfifo_rst_frm_axi_clk;
output [0:0]p_0_in;
output Tx_FIFO_Full_int;
output rx_fifo_empty_i;
output intr2bus_wrack_reg;
output [0:0]E;
output \gen_fwft.gdvld_fwft.data_valid_fwft_reg ;
output [7:0]D;
output intr2bus_rdack_reg;
output scndry_out;
output ip2intc_irpt;
output [8:0]\ip_irpt_enable_reg_reg[8] ;
input reset2ip_reset_int;
input s_axi4_aclk;
input ext_spi_clk;
input rd_en;
input IP2Bus_WrAck_transmit_enable;
input [9:0]s_axi4_wdata;
input [0:0]bus2ip_wrce_int;
input Transmit_ip2bus_error0;
input \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9] ;
input bus2ip_reset_ipif_inverted;
input sw_rst_cond;
input reset_trig0;
input irpt_wrack;
input \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
input \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
input \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
input interrupt_wrce_strb;
input irpt_rdack;
input intr2bus_rdack0;
input wr_ce_or_reduce_core_cmb;
input ip2Bus_WrAck_core_reg0;
input ip2Bus_WrAck_intr_reg_hole_d1_reg_0;
input ip2Bus_WrAck_intr_reg_hole0;
input intr_controller_rd_ce_or_reduce;
input ip2Bus_RdAck_intr_reg_hole0;
input rd_ce_or_reduce_core_cmb;
input \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ;
input \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ;
input \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] ;
input ipif_glbl_irpt_enable_reg_reg;
input ip2bus_error_int;
input burst_tr_int;
input s_axi4_rready;
input [0:0]Q;
input \s_axi4_rdata_i_reg[31] ;
input \s_axi4_rdata_i_reg[0] ;
input \s_axi4_rdata_i_reg[7] ;
input \s_axi4_rdata_i_reg[1] ;
input \s_axi4_rdata_i_reg[2] ;
input \s_axi4_rdata_i_reg[3] ;
input \s_axi4_rdata_i_reg[4] ;
input \s_axi4_rdata_i_reg[5] ;
input \s_axi4_rdata_i_reg[6] ;
input \s_axi4_rdata_i_reg[7]_0 ;
input \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ;
input p_4_in;
input Bus_RNW_reg;
input p_2_in;
input p_1_in;
input \s_axi4_rdata_i_reg[5]_0 ;
input [0:0]\ip_irpt_enable_reg_reg[8]_0 ;
input io1_i_sync;
input io0_i_sync;
wire Bus_RNW_reg;
wire \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ;
wire \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ;
wire \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9] ;
wire CONTROL_REG_I_n_12;
wire Count_trigger;
wire [7:0]D;
wire D0;
wire D01_out;
wire D_0;
wire [0:0]E;
wire \FIFO_EXISTS.CLK_CROSS_I_n_10 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_11 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_12 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_13 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_17 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_18 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_2 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_20 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_21 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_24 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_25 ;
wire \FIFO_EXISTS.CLK_CROSS_I_n_9 ;
wire \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_1 ;
wire \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_2 ;
wire \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3 ;
wire \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4 ;
wire \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5 ;
wire \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6 ;
wire \FIFO_EXISTS.TX_FIFO_II_n_18 ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ;
wire \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ;
wire \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ;
wire \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ;
wire IP2Bus_WrAck_transmit_enable;
wire \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_15 ;
wire \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_16 ;
wire \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_6 ;
wire [0:0]Q;
wire R;
wire \RESET_FLOPS[15].RST_FLOPS ;
wire Ratio_Count;
wire Rx_FIFO_Empty_Synced_in_SPI_domain;
wire Rx_FIFO_Full_Fifo;
wire Rx_FIFO_Full_Fifo_d1;
wire Rx_FIFO_Full_Fifo_d1_synced_i;
wire [8:0]Rx_FIFO_occ_Reversed;
wire SOFT_RESET_I_n_3;
wire SPICR_2_MST_N_SLV_to_spi_clk;
wire \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] ;
wire SPISSR_frm_axi_clk;
wire TX_one_less_than_full;
wire Transmit_ip2bus_error0;
wire Tx_FIFO_Empty_SPISR_to_axi_clk;
wire Tx_FIFO_Empty_intr;
wire Tx_FIFO_Full_i;
wire Tx_FIFO_Full_int;
wire almost_full;
wire almost_full_0;
wire burst_tr_int;
wire [23:23]bus2IP_Data_for_interrupt_core;
wire bus2ip_reset_ipif_inverted;
wire [0:0]bus2ip_wrce_int;
wire data_Exists_RcFIFO_int_d1;
wire data_Exists_RcFIFO_int_d10;
wire [0:7]data_from_rx_fifo;
wire [0:7]data_from_txfifo;
wire data_in;
wire [0:7]data_to_rx_fifo;
wire data_valid;
wire empty;
wire ext_spi_clk;
wire \gen_fwft.gdvld_fwft.data_valid_fwft_reg ;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr2bus_rdack_reg;
wire intr2bus_wrack_reg;
wire intr_controller_rd_ce_or_reduce;
wire io0_i_sync;
wire io0_t;
wire io1_i_sync;
wire io1_o;
wire io1_t;
wire ip2Bus_RdAck_core_reg;
wire ip2Bus_RdAck_core_reg0;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_RdAck_intr_reg_hole0;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_core_reg;
wire ip2Bus_WrAck_core_reg0;
wire ip2Bus_WrAck_core_reg_d1;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole0;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1_reg_0;
wire ip2bus_error_int;
wire ip2intc_irpt;
wire [8:0]\ip_irpt_enable_reg_reg[8] ;
wire [0:0]\ip_irpt_enable_reg_reg[8]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire p_1_in;
wire p_1_in13_in;
wire p_1_in16_in;
wire p_1_in19_in;
wire p_1_in22_in;
wire p_1_in25_in;
wire p_1_in28_in;
wire p_1_in31_in;
wire p_1_in34_in;
wire p_2_in;
wire p_4_in;
wire rc_FIFO_Full_d1;
wire rd_ce_or_reduce_core_cmb;
wire rd_en;
wire read_ack_delay_1;
wire read_ack_delay_2;
wire read_ack_delay_3;
wire read_ack_delay_4;
wire read_ack_delay_5;
wire read_ack_delay_6;
wire read_ack_delay_7;
wire receive_ip2bus_error;
wire register_Data_slvsel_int;
wire reset2ip_reset_int;
wire reset_TxFIFO_ptr_int;
wire reset_trig0;
wire rst;
wire rst_to_spi_int;
wire rx_fifo_empty_i;
wire s_axi4_aclk;
wire \s_axi4_rdata_i[0]_i_3_n_0 ;
wire \s_axi4_rdata_i[1]_i_4_n_0 ;
wire \s_axi4_rdata_i[2]_i_4_n_0 ;
wire \s_axi4_rdata_i[2]_i_6_n_0 ;
wire \s_axi4_rdata_i[3]_i_4_n_0 ;
wire \s_axi4_rdata_i[3]_i_6_n_0 ;
wire \s_axi4_rdata_i[4]_i_3_n_0 ;
wire \s_axi4_rdata_i[4]_i_5_n_0 ;
wire \s_axi4_rdata_i[4]_i_6_n_0 ;
wire \s_axi4_rdata_i[5]_i_4_n_0 ;
wire \s_axi4_rdata_i[5]_i_6_n_0 ;
wire \s_axi4_rdata_i[6]_i_3_n_0 ;
wire \s_axi4_rdata_i[7]_i_3_n_0 ;
wire \s_axi4_rdata_i[7]_i_4_n_0 ;
wire \s_axi4_rdata_i[7]_i_7_n_0 ;
wire \s_axi4_rdata_i[7]_i_8_n_0 ;
wire \s_axi4_rdata_i_reg[0] ;
wire \s_axi4_rdata_i_reg[1] ;
wire \s_axi4_rdata_i_reg[2] ;
wire \s_axi4_rdata_i_reg[31] ;
wire \s_axi4_rdata_i_reg[3] ;
wire \s_axi4_rdata_i_reg[4] ;
wire \s_axi4_rdata_i_reg[5] ;
wire \s_axi4_rdata_i_reg[5]_0 ;
wire \s_axi4_rdata_i_reg[6] ;
wire \s_axi4_rdata_i_reg[7] ;
wire \s_axi4_rdata_i_reg[7]_0 ;
wire s_axi4_rready;
wire [9:0]s_axi4_wdata;
wire sck_o;
wire sck_t;
wire scndry_out;
wire serial_dout_int;
wire spiXfer_done_int;
wire spiXfer_done_to_axi_1;
wire spiXfer_done_to_axi_d1;
wire spicr_0_loop_frm_axi_clk;
wire spicr_0_loop_to_spi_clk;
wire spicr_1_spe_frm_axi_clk;
wire spicr_2_mst_n_slv_frm_axi_clk;
wire spicr_3_cpol_frm_axi_clk;
wire spicr_3_cpol_to_spi_clk;
wire spicr_4_cpha_frm_axi_clk;
wire spicr_4_cpha_to_spi_clk;
wire spicr_5_txfifo_rst_frm_axi_clk;
wire spicr_6_rxfifo_rst_frm_axi_clk;
wire spicr_7_ss_frm_axi_clk;
wire spicr_8_tr_inhibit_frm_axi_clk;
wire spicr_9_lsb_frm_axi_clk;
wire spicr_9_lsb_to_spi_clk;
wire [1:0]spicr_bits_7_8_frm_axi_clk;
wire spisel_d1_reg_to_axi_clk;
wire [0:0]ss_o;
wire ss_t;
wire sw_rst_cond;
wire sw_rst_cond_d1;
wire transfer_start_d1;
wire transmit_ip2bus_error;
wire tx_FIFO_Empty_d1;
wire tx_FIFO_Occpncy_MSB_d1;
wire [0:0]tx_fifo_count;
wire [7:0]tx_fifo_count_d1;
wire [7:0]tx_fifo_count_d2;
wire tx_fifo_empty;
wire tx_occ_msb;
wire tx_occ_msb_1;
wire tx_occ_msb_4;
wire wr_ce_or_reduce_core_cmb;
wire wrack;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_almost_empty_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_dbiterr_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_full_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_overflow_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_prog_empty_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_prog_full_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_rd_rst_busy_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_sbiterr_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_underflow_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_wr_ack_UNCONNECTED ;
wire \NLW_FIFO_EXISTS.RX_FIFO_II_wr_rst_busy_UNCONNECTED ;
wire [8:0]\NLW_FIFO_EXISTS.RX_FIFO_II_wr_data_count_UNCONNECTED ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_cntrl_reg CONTROL_REG_I
(.\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0 (\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3] ),
.\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0 (spicr_5_txfifo_rst_frm_axi_clk),
.\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_1 (\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4] ),
.\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0 (spicr_2_mst_n_slv_frm_axi_clk),
.\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0 (\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9] ),
.D(bus2IP_Data_for_interrupt_core),
.\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8] (\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ),
.\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 (rx_fifo_empty_i),
.bus2ip_wrce_int(bus2ip_wrce_int),
.data_Exists_RcFIFO_int_d1(data_Exists_RcFIFO_int_d1),
.\ip_irpt_enable_reg_reg[8] (spisel_d1_reg_to_axi_clk),
.p_1_in13_in(p_1_in13_in),
.reset2ip_reset_int(reset2ip_reset_int),
.s_axi4_aclk(s_axi4_aclk),
.s_axi4_wdata({s_axi4_wdata[9:7],s_axi4_wdata[4:0]}),
.\s_axi4_wdata[8] (CONTROL_REG_I_n_12),
.spicr_0_loop_frm_axi_clk(spicr_0_loop_frm_axi_clk),
.spicr_1_spe_frm_axi_clk(spicr_1_spe_frm_axi_clk),
.spicr_3_cpol_frm_axi_clk(spicr_3_cpol_frm_axi_clk),
.spicr_4_cpha_frm_axi_clk(spicr_4_cpha_frm_axi_clk),
.spicr_6_rxfifo_rst_frm_axi_clk(spicr_6_rxfifo_rst_frm_axi_clk),
.spicr_7_ss_frm_axi_clk(spicr_7_ss_frm_axi_clk),
.spicr_8_tr_inhibit_frm_axi_clk(spicr_8_tr_inhibit_frm_axi_clk),
.spicr_9_lsb_frm_axi_clk(spicr_9_lsb_frm_axi_clk),
.spicr_bits_7_8_frm_axi_clk(spicr_bits_7_8_frm_axi_clk));
LUT2 #(
.INIT(4'h2))
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1
(.I0(read_ack_delay_6),
.I1(read_ack_delay_7),
.O(ip2Bus_RdAck_core_reg0));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(ip2Bus_RdAck_core_reg0),
.Q(ip2Bus_RdAck_core_reg),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(wr_ce_or_reduce_core_cmb),
.Q(ip2Bus_WrAck_core_reg_d1),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(ip2Bus_WrAck_core_reg0),
.Q(ip2Bus_WrAck_core_reg),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(rd_ce_or_reduce_core_cmb),
.Q(read_ack_delay_1),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(read_ack_delay_1),
.Q(read_ack_delay_2),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(read_ack_delay_2),
.Q(read_ack_delay_3),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(read_ack_delay_3),
.Q(read_ack_delay_4),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(read_ack_delay_4),
.Q(read_ack_delay_5),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_6_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(read_ack_delay_5),
.Q(read_ack_delay_6),
.R(reset2ip_reset_int));
FDRE \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_7_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(read_ack_delay_6),
.Q(read_ack_delay_7),
.R(reset2ip_reset_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cross_clk_sync_fifo_1 \FIFO_EXISTS.CLK_CROSS_I
(.Count_trigger(Count_trigger),
.D(data_in),
.D0(D0),
.D01_out(D01_out),
.D_0(D_0),
.\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg (\RESET_FLOPS[15].RST_FLOPS ),
.\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0 (rx_fifo_empty_i),
.\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg (spicr_5_txfifo_rst_frm_axi_clk),
.\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5] (\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ),
.IP2Bus_WrAck_transmit_enable(IP2Bus_WrAck_transmit_enable),
.\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0 (\FIFO_EXISTS.CLK_CROSS_I_n_25 ),
.\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_0 (\FIFO_EXISTS.CLK_CROSS_I_n_20 ),
.\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_1 (\FIFO_EXISTS.CLK_CROSS_I_n_21 ),
.\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2_0 (\FIFO_EXISTS.CLK_CROSS_I_n_24 ),
.\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0 (\FIFO_EXISTS.CLK_CROSS_I_n_11 ),
.\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_1 (\FIFO_EXISTS.CLK_CROSS_I_n_12 ),
.\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_2 (\FIFO_EXISTS.CLK_CROSS_I_n_13 ),
.\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0 (Tx_FIFO_Empty_SPISR_to_axi_clk),
.\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0 (\FIFO_EXISTS.CLK_CROSS_I_n_9 ),
.\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0 (\FIFO_EXISTS.CLK_CROSS_I_n_2 ),
.R(R),
.Ratio_Count(Ratio_Count),
.Rst_to_spi(rst_to_spi_int),
.S(\FIFO_EXISTS.CLK_CROSS_I_n_10 ),
.SPICR_2_MST_N_SLV_to_spi_clk(SPICR_2_MST_N_SLV_to_spi_clk),
.SPISSR_frm_axi_clk(SPISSR_frm_axi_clk),
.\SS_O_reg[0] (\LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_16 ),
.Tx_FIFO_Empty_intr(Tx_FIFO_Empty_intr),
.Tx_FIFO_Full_i(Tx_FIFO_Full_i),
.Tx_FIFO_Full_int(Tx_FIFO_Full_int),
.bus2ip_reset_ipif_inverted(bus2ip_reset_ipif_inverted),
.empty(tx_fifo_empty),
.ext_spi_clk(ext_spi_clk),
.icount_out0_carry(\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3 ),
.io0_i_sync(io0_i_sync),
.io1_i_sync(io1_i_sync),
.p_1_in16_in(p_1_in16_in),
.p_1_in22_in(p_1_in22_in),
.register_Data_slvsel_int(register_Data_slvsel_int),
.reset2ip_reset_int(reset2ip_reset_int),
.rst(rst),
.s_axi4_aclk(s_axi4_aclk),
.s_axi4_wdata({s_axi4_wdata[7],s_axi4_wdata[5]}),
.\s_axi4_wdata[5] (\FIFO_EXISTS.CLK_CROSS_I_n_18 ),
.\s_axi4_wdata[7] (\FIFO_EXISTS.CLK_CROSS_I_n_17 ),
.serial_dout_int(serial_dout_int),
.spiXfer_done_to_axi_1(spiXfer_done_to_axi_1),
.spiXfer_done_to_axi_d1(spiXfer_done_to_axi_d1),
.spicr_0_loop_frm_axi_clk(spicr_0_loop_frm_axi_clk),
.spicr_0_loop_to_spi_clk(spicr_0_loop_to_spi_clk),
.spicr_1_spe_frm_axi_clk(spicr_1_spe_frm_axi_clk),
.spicr_2_mst_n_slv_frm_axi_clk(spicr_2_mst_n_slv_frm_axi_clk),
.spicr_3_cpol_frm_axi_clk(spicr_3_cpol_frm_axi_clk),
.spicr_3_cpol_to_spi_clk(spicr_3_cpol_to_spi_clk),
.spicr_4_cpha_frm_axi_clk(spicr_4_cpha_frm_axi_clk),
.spicr_4_cpha_to_spi_clk(spicr_4_cpha_to_spi_clk),
.spicr_6_rxfifo_rst_frm_axi_clk(spicr_6_rxfifo_rst_frm_axi_clk),
.spicr_7_ss_frm_axi_clk(spicr_7_ss_frm_axi_clk),
.spicr_8_tr_inhibit_frm_axi_clk(spicr_8_tr_inhibit_frm_axi_clk),
.spicr_9_lsb_frm_axi_clk(spicr_9_lsb_frm_axi_clk),
.spicr_9_lsb_to_spi_clk(spicr_9_lsb_to_spi_clk),
.spicr_bits_7_8_frm_axi_clk(spicr_bits_7_8_frm_axi_clk),
.spisel_d1_reg_to_axi_clk(spisel_d1_reg_to_axi_clk),
.transfer_start_d1(transfer_start_d1),
.transfer_start_reg(\LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_6 ),
.tx_fifo_count_d2(tx_fifo_count_d2),
.tx_occ_msb(tx_occ_msb),
.tx_occ_msb_4(tx_occ_msb_4));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_fifo_ifmodule \FIFO_EXISTS.FIFO_IF_MODULE_I
(.Bus_RNW_reg(Bus_RNW_reg),
.Receive_ip2bus_error_reg_0(rx_fifo_empty_i),
.Rx_FIFO_Full_Fifo_d1_synced_i(Rx_FIFO_Full_Fifo_d1_synced_i),
.Transmit_ip2bus_error0(Transmit_ip2bus_error0),
.Tx_FIFO_Empty_intr(Tx_FIFO_Empty_intr),
.p_4_in(p_4_in),
.prmry_in(empty),
.rc_FIFO_Full_d1(rc_FIFO_Full_d1),
.receive_ip2bus_error(receive_ip2bus_error),
.reset2ip_reset_int(reset2ip_reset_int),
.s_axi4_aclk(s_axi4_aclk),
.transmit_ip2bus_error(transmit_ip2bus_error),
.tx_FIFO_Empty_d1(tx_FIFO_Empty_d1),
.tx_FIFO_Occpncy_MSB_d1(tx_FIFO_Occpncy_MSB_d1),
.tx_occ_msb(tx_occ_msb));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC
(.Rx_FIFO_Full_Fifo(Rx_FIFO_Full_Fifo),
.almost_full(almost_full_0),
.ext_spi_clk(ext_spi_clk),
.prmry_in(empty),
.scndry_out(Rx_FIFO_Empty_Synced_in_SPI_domain));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC
(.Rx_FIFO_Full_Fifo_d1_synced_i(Rx_FIFO_Full_Fifo_d1_synced_i),
.empty(empty),
.prmry_in(Rx_FIFO_Full_Fifo_d1),
.s_axi4_aclk(s_axi4_aclk),
.scndry_out(scndry_out));
(* CASCADE_HEIGHT = "0" *)
(* CDC_SYNC_STAGES = "2" *)
(* DOUT_RESET_VALUE = "0" *)
(* ECC_MODE = "no_ecc" *)
(* EN_ADV_FEATURE_ASYNC = "16'b0001111100011111" *)
(* FIFO_MEMORY_TYPE = "auto" *)
(* FIFO_READ_LATENCY = "0" *)
(* FIFO_WRITE_DEPTH = "256" *)
(* FULL_RESET_VALUE = "0" *)
(* PROG_EMPTY_THRESH = "10" *)
(* PROG_FULL_THRESH = "10" *)
(* P_COMMON_CLOCK = "0" *)
(* P_ECC_MODE = "0" *)
(* P_FIFO_MEMORY_TYPE = "0" *)
(* P_READ_MODE = "1" *)
(* P_WAKEUP_TIME = "2" *)
(* RD_DATA_COUNT_WIDTH = "9" *)
(* READ_DATA_WIDTH = "8" *)
(* READ_MODE = "fwft" *)
(* RELATED_CLOCKS = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* USE_ADV_FEATURES = "1f1f" *)
(* WAKEUP_TIME = "0" *)
(* WRITE_DATA_WIDTH = "8" *)
(* WR_DATA_COUNT_WIDTH = "9" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async \FIFO_EXISTS.RX_FIFO_II
(.almost_empty(\NLW_FIFO_EXISTS.RX_FIFO_II_almost_empty_UNCONNECTED ),
.almost_full(almost_full_0),
.data_valid(data_valid),
.dbiterr(\NLW_FIFO_EXISTS.RX_FIFO_II_dbiterr_UNCONNECTED ),
.din({data_to_rx_fifo[0],data_to_rx_fifo[1],data_to_rx_fifo[2],data_to_rx_fifo[3],data_to_rx_fifo[4],data_to_rx_fifo[5],data_to_rx_fifo[6],data_to_rx_fifo[7]}),
.dout({data_from_rx_fifo[0],data_from_rx_fifo[1],data_from_rx_fifo[2],data_from_rx_fifo[3],data_from_rx_fifo[4],data_from_rx_fifo[5],data_from_rx_fifo[6],data_from_rx_fifo[7]}),
.empty(empty),
.full(\NLW_FIFO_EXISTS.RX_FIFO_II_full_UNCONNECTED ),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.overflow(\NLW_FIFO_EXISTS.RX_FIFO_II_overflow_UNCONNECTED ),
.prog_empty(\NLW_FIFO_EXISTS.RX_FIFO_II_prog_empty_UNCONNECTED ),
.prog_full(\NLW_FIFO_EXISTS.RX_FIFO_II_prog_full_UNCONNECTED ),
.rd_clk(s_axi4_aclk),
.rd_data_count(Rx_FIFO_occ_Reversed),
.rd_en(rd_en),
.rd_rst_busy(\NLW_FIFO_EXISTS.RX_FIFO_II_rd_rst_busy_UNCONNECTED ),
.rst(rst),
.sbiterr(\NLW_FIFO_EXISTS.RX_FIFO_II_sbiterr_UNCONNECTED ),
.sleep(1'b0),
.underflow(\NLW_FIFO_EXISTS.RX_FIFO_II_underflow_UNCONNECTED ),
.wr_ack(\NLW_FIFO_EXISTS.RX_FIFO_II_wr_ack_UNCONNECTED ),
.wr_clk(ext_spi_clk),
.wr_data_count(\NLW_FIFO_EXISTS.RX_FIFO_II_wr_data_count_UNCONNECTED [8:0]),
.wr_en(spiXfer_done_int),
.wr_rst_busy(\NLW_FIFO_EXISTS.RX_FIFO_II_wr_rst_busy_UNCONNECTED ));
FDRE \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FIFO_EXISTS.CLK_CROSS_I_n_12 ),
.Q(rx_fifo_empty_i),
.R(1'b0));
FDRE \FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(Rx_FIFO_Full_Fifo),
.Q(Rx_FIFO_Full_Fifo_d1),
.R(rst_to_spi_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I
(.IP2Bus_WrAck_transmit_enable(IP2Bus_WrAck_transmit_enable),
.S(\FIFO_EXISTS.CLK_CROSS_I_n_10 ),
.TX_one_less_than_full(TX_one_less_than_full),
.bus2ip_reset_ipif_inverted(bus2ip_reset_ipif_inverted),
.\icount_out_reg[0]_0 (\FIFO_EXISTS.CLK_CROSS_I_n_11 ),
.\icount_out_reg[1]_0 (\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3 ),
.\icount_out_reg[2]_0 (\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_2 ),
.\icount_out_reg[3]_0 (\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_1 ),
.\icount_out_reg[4]_0 (\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5 ),
.\icount_out_reg[5]_0 (\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4 ),
.\icount_out_reg[6]_0 (\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6 ),
.\icount_out_reg[7]_0 (\RESET_FLOPS[15].RST_FLOPS ),
.\icount_out_reg[7]_1 (spicr_5_txfifo_rst_frm_axi_clk),
.s_axi4_aclk(s_axi4_aclk),
.tx_fifo_count(tx_fifo_count),
.tx_occ_msb_1(tx_occ_msb_1));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_async_fifo_fg \FIFO_EXISTS.TX_FIFO_II
(.Bus_RNW_reg(Bus_RNW_reg),
.D(D),
.IP2Bus_WrAck_transmit_enable(IP2Bus_WrAck_transmit_enable),
.almost_full(almost_full),
.dout({data_from_txfifo[0],data_from_txfifo[1],data_from_txfifo[2],data_from_txfifo[3],data_from_txfifo[4],data_from_txfifo[5],data_from_txfifo[6],data_from_txfifo[7]}),
.empty(tx_fifo_empty),
.ext_spi_clk(ext_spi_clk),
.\gen_wr_a.gen_word_narrow.mem_reg (\FIFO_EXISTS.TX_FIFO_II_n_18 ),
.p_2_in(p_2_in),
.rd_en(\LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_15 ),
.rst(reset_TxFIFO_ptr_int),
.s_axi4_aclk(s_axi4_aclk),
.\s_axi4_rdata_i_reg[0] (\s_axi4_rdata_i_reg[0] ),
.\s_axi4_rdata_i_reg[0]_0 (\s_axi4_rdata_i[0]_i_3_n_0 ),
.\s_axi4_rdata_i_reg[1] (\s_axi4_rdata_i_reg[1] ),
.\s_axi4_rdata_i_reg[1]_0 (\s_axi4_rdata_i[1]_i_4_n_0 ),
.\s_axi4_rdata_i_reg[2] (\s_axi4_rdata_i_reg[2] ),
.\s_axi4_rdata_i_reg[2]_0 (\s_axi4_rdata_i[2]_i_4_n_0 ),
.\s_axi4_rdata_i_reg[3] (\s_axi4_rdata_i_reg[3] ),
.\s_axi4_rdata_i_reg[3]_0 (\s_axi4_rdata_i[3]_i_4_n_0 ),
.\s_axi4_rdata_i_reg[4] (\s_axi4_rdata_i_reg[4] ),
.\s_axi4_rdata_i_reg[4]_0 (\s_axi4_rdata_i[4]_i_3_n_0 ),
.\s_axi4_rdata_i_reg[5] (\s_axi4_rdata_i_reg[5] ),
.\s_axi4_rdata_i_reg[5]_0 (\s_axi4_rdata_i[5]_i_4_n_0 ),
.\s_axi4_rdata_i_reg[6] (\s_axi4_rdata_i_reg[6] ),
.\s_axi4_rdata_i_reg[6]_0 (\s_axi4_rdata_i[6]_i_3_n_0 ),
.\s_axi4_rdata_i_reg[6]_1 (Tx_FIFO_Empty_SPISR_to_axi_clk),
.\s_axi4_rdata_i_reg[7] ({data_from_rx_fifo[0],data_from_rx_fifo[1],data_from_rx_fifo[2],data_from_rx_fifo[3],data_from_rx_fifo[4],data_from_rx_fifo[5],data_from_rx_fifo[6],data_from_rx_fifo[7]}),
.\s_axi4_rdata_i_reg[7]_0 (\s_axi4_rdata_i_reg[7] ),
.\s_axi4_rdata_i_reg[7]_1 (\s_axi4_rdata_i[7]_i_3_n_0 ),
.\s_axi4_rdata_i_reg[7]_2 (\s_axi4_rdata_i[7]_i_4_n_0 ),
.\s_axi4_rdata_i_reg[7]_3 (\s_axi4_rdata_i_reg[7]_0 ),
.s_axi4_wdata(s_axi4_wdata[7:0]),
.spicr_9_lsb_to_spi_clk(spicr_9_lsb_to_spi_clk));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(SOFT_RESET_I_n_3),
.Q(Tx_FIFO_Full_i),
.R(1'b0));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FIFO_EXISTS.CLK_CROSS_I_n_13 ),
.Q(Tx_FIFO_Full_int),
.R(1'b0));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.spiXfer_done_to_axi_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(spiXfer_done_to_axi_1),
.Q(spiXfer_done_to_axi_d1),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[0]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count),
.Q(tx_fifo_count_d1[0]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[1]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3 ),
.Q(tx_fifo_count_d1[1]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[2]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_2 ),
.Q(tx_fifo_count_d1[2]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_1 ),
.Q(tx_fifo_count_d1[3]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[4]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5 ),
.Q(tx_fifo_count_d1[4]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[5]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4 ),
.Q(tx_fifo_count_d1[5]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[6]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6 ),
.Q(tx_fifo_count_d1[6]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[7]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_occ_msb_1),
.Q(tx_fifo_count_d1[7]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[0]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d1[0]),
.Q(tx_fifo_count_d2[0]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[1]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d1[1]),
.Q(tx_fifo_count_d2[1]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[2]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d1[2]),
.Q(tx_fifo_count_d2[2]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[3]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d1[3]),
.Q(tx_fifo_count_d2[3]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[4]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d1[4]),
.Q(tx_fifo_count_d2[4]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[5]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d1[5]),
.Q(tx_fifo_count_d2[5]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[6]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d1[6]),
.Q(tx_fifo_count_d2[6]),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[7]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d1[7]),
.Q(tx_fifo_count_d2[7]),
.R(reset2ip_reset_int));
LUT1 #(
.INIT(2'h1))
\FIFO_EXISTS.data_Exists_RcFIFO_int_d1_i_1
(.I0(rx_fifo_empty_i),
.O(data_Exists_RcFIFO_int_d10));
FDRE \FIFO_EXISTS.data_Exists_RcFIFO_int_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(data_Exists_RcFIFO_int_d10),
.Q(data_Exists_RcFIFO_int_d1),
.R(reset2ip_reset_int));
FDRE \FIFO_EXISTS.tx_occ_msb_4_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_fifo_count_d2[7]),
.Q(tx_occ_msb_4),
.R(reset2ip_reset_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control INTERRUPT_CONTROL_I
(.D(bus2IP_Data_for_interrupt_core),
.E(E),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0] ),
.\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1 (\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0 ),
.\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0 (\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1] ),
.\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0 (\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3] ),
.\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0 (\FIFO_EXISTS.CLK_CROSS_I_n_18 ),
.\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0 (\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6] ),
.\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0 (\FIFO_EXISTS.CLK_CROSS_I_n_17 ),
.\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0 (CONTROL_REG_I_n_12),
.Q(Q),
.Tx_FIFO_Empty_SPISR_to_axi_clk(Tx_FIFO_Empty_SPISR_to_axi_clk),
.Tx_FIFO_Empty_intr(Tx_FIFO_Empty_intr),
.burst_tr_int(burst_tr_int),
.data_valid(data_valid),
.empty(empty),
.\gen_fwft.gdvld_fwft.data_valid_fwft_reg (\gen_fwft.gdvld_fwft.data_valid_fwft_reg ),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr2bus_rdack_reg_0(intr2bus_rdack_reg),
.intr2bus_wrack_reg_0(intr2bus_wrack_reg),
.ip2Bus_RdAck_core_reg(ip2Bus_RdAck_core_reg),
.ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole),
.ip2Bus_WrAck_core_reg(ip2Bus_WrAck_core_reg),
.ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole),
.ip2bus_error_int(ip2bus_error_int),
.ip2intc_irpt(ip2intc_irpt),
.\ip_irpt_enable_reg_reg[8]_0 (\ip_irpt_enable_reg_reg[8] ),
.\ip_irpt_enable_reg_reg[8]_1 (\ip_irpt_enable_reg_reg[8]_0 ),
.ipif_glbl_irpt_enable_reg_reg_0(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in13_in(p_1_in13_in),
.p_1_in16_in(p_1_in16_in),
.p_1_in19_in(p_1_in19_in),
.p_1_in22_in(p_1_in22_in),
.p_1_in25_in(p_1_in25_in),
.p_1_in28_in(p_1_in28_in),
.p_1_in31_in(p_1_in31_in),
.p_1_in34_in(p_1_in34_in),
.rc_FIFO_Full_d1(rc_FIFO_Full_d1),
.reset2ip_reset_int(reset2ip_reset_int),
.s_axi4_aclk(s_axi4_aclk),
.\s_axi4_rdata_i_reg[31] (\s_axi4_rdata_i_reg[31] ),
.s_axi4_rready(s_axi4_rready),
.s_axi4_wdata(s_axi4_wdata[7:0]),
.scndry_out(scndry_out),
.tx_FIFO_Empty_d1(tx_FIFO_Empty_d1),
.tx_FIFO_Occpncy_MSB_d1(tx_FIFO_Occpncy_MSB_d1),
.tx_occ_msb_4(tx_occ_msb_4),
.wrack(wrack));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_mode_0_module \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I
(.Count_trigger(Count_trigger),
.D(data_in),
.D0(D0),
.D01_out(D01_out),
.D_0(D_0),
.\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2 (\LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_16 ),
.\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg (\FIFO_EXISTS.CLK_CROSS_I_n_9 ),
.\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg (\FIFO_EXISTS.CLK_CROSS_I_n_2 ),
.\OTHER_RATIO_GENERATE.Serial_Dout_reg_0 (\FIFO_EXISTS.TX_FIFO_II_n_18 ),
.\OTHER_RATIO_GENERATE.sck_o_int_reg_0 (\FIFO_EXISTS.CLK_CROSS_I_n_21 ),
.R(R),
.\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 (\LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_6 ),
.\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_1 (\FIFO_EXISTS.CLK_CROSS_I_n_20 ),
.Ratio_Count(Ratio_Count),
.Rst_to_spi(rst_to_spi_int),
.SPICR_2_MST_N_SLV_to_spi_clk(SPICR_2_MST_N_SLV_to_spi_clk),
.\SS_O_reg[0]_0 (\FIFO_EXISTS.CLK_CROSS_I_n_24 ),
.almost_full(almost_full_0),
.din({data_to_rx_fifo[0],data_to_rx_fifo[1],data_to_rx_fifo[2],data_to_rx_fifo[3],data_to_rx_fifo[4],data_to_rx_fifo[5],data_to_rx_fifo[6],data_to_rx_fifo[7]}),
.dout({data_from_txfifo[0],data_from_txfifo[1],data_from_txfifo[2],data_from_txfifo[3],data_from_txfifo[4],data_from_txfifo[5],data_from_txfifo[6],data_from_txfifo[7]}),
.empty(tx_fifo_empty),
.ext_spi_clk(ext_spi_clk),
.io0_t(io0_t),
.io1_o(io1_o),
.io1_t(io1_t),
.rd_en(\LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_15 ),
.register_Data_slvsel_int(register_Data_slvsel_int),
.sck_o(sck_o),
.sck_t(sck_t),
.scndry_out(Rx_FIFO_Empty_Synced_in_SPI_domain),
.serial_dout_int(serial_dout_int),
.spiXfer_done_int(spiXfer_done_int),
.spicr_0_loop_to_spi_clk(spicr_0_loop_to_spi_clk),
.spicr_3_cpol_to_spi_clk(spicr_3_cpol_to_spi_clk),
.spicr_4_cpha_to_spi_clk(spicr_4_cpha_to_spi_clk),
.spicr_9_lsb_to_spi_clk(spicr_9_lsb_to_spi_clk),
.ss_o(ss_o),
.ss_t(ss_t),
.transfer_start_d1(transfer_start_d1),
.transfer_start_reg_0(\FIFO_EXISTS.CLK_CROSS_I_n_25 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_module RESET_SYNC_AXI_SPI_CLK_INST
(.Rst_to_spi(rst_to_spi_int),
.ext_spi_clk(ext_spi_clk),
.reset2ip_reset_int(reset2ip_reset_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_soft_reset SOFT_RESET_I
(.Bus2IP_Reset_i_reg(SOFT_RESET_I_n_3),
.\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg (spicr_5_txfifo_rst_frm_axi_clk),
.\RESET_FLOPS[15].RST_FLOPS_0 (\RESET_FLOPS[15].RST_FLOPS ),
.TX_one_less_than_full(TX_one_less_than_full),
.Tx_FIFO_Full_i(Tx_FIFO_Full_i),
.Tx_FIFO_Full_int(Tx_FIFO_Full_int),
.bus2ip_reset_ipif_inverted(bus2ip_reset_ipif_inverted),
.reset_trig0(reset_trig0),
.rst(reset_TxFIFO_ptr_int),
.s_axi4_aclk(s_axi4_aclk),
.sw_rst_cond(sw_rst_cond),
.sw_rst_cond_d1(sw_rst_cond_d1),
.wrack(wrack));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_status_slave_sel_reg \STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I
(.\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]_0 (\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0] ),
.SPISSR_frm_axi_clk(SPISSR_frm_axi_clk),
.reset2ip_reset_int(reset2ip_reset_int),
.s_axi4_aclk(s_axi4_aclk));
FDRE ip2Bus_RdAck_intr_reg_hole_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(intr_controller_rd_ce_or_reduce),
.Q(ip2Bus_RdAck_intr_reg_hole_d1),
.R(reset2ip_reset_int));
FDRE ip2Bus_RdAck_intr_reg_hole_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(ip2Bus_RdAck_intr_reg_hole0),
.Q(ip2Bus_RdAck_intr_reg_hole),
.R(reset2ip_reset_int));
FDRE ip2Bus_WrAck_intr_reg_hole_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(ip2Bus_WrAck_intr_reg_hole_d1_reg_0),
.Q(ip2Bus_WrAck_intr_reg_hole_d1),
.R(reset2ip_reset_int));
FDRE ip2Bus_WrAck_intr_reg_hole_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(ip2Bus_WrAck_intr_reg_hole0),
.Q(ip2Bus_WrAck_intr_reg_hole),
.R(reset2ip_reset_int));
LUT6 #(
.INIT(64'h0000000055555554))
\s_axi4_rdata_i[0]_i_3
(.I0(\s_axi4_rdata_i_reg[5]_0 ),
.I1(Rx_FIFO_occ_Reversed[8]),
.I2(Rx_FIFO_occ_Reversed[6]),
.I3(\s_axi4_rdata_i[7]_i_8_n_0 ),
.I4(Rx_FIFO_occ_Reversed[7]),
.I5(Rx_FIFO_occ_Reversed[0]),
.O(\s_axi4_rdata_i[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h2000000000002000))
\s_axi4_rdata_i[1]_i_4
(.I0(p_1_in),
.I1(empty),
.I2(Bus_RNW_reg),
.I3(\s_axi4_rdata_i[4]_i_5_n_0 ),
.I4(Rx_FIFO_occ_Reversed[1]),
.I5(Rx_FIFO_occ_Reversed[0]),
.O(\s_axi4_rdata_i[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h2000000000002000))
\s_axi4_rdata_i[2]_i_4
(.I0(p_1_in),
.I1(empty),
.I2(Bus_RNW_reg),
.I3(\s_axi4_rdata_i[4]_i_5_n_0 ),
.I4(\s_axi4_rdata_i[2]_i_6_n_0 ),
.I5(Rx_FIFO_occ_Reversed[2]),
.O(\s_axi4_rdata_i[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT2 #(
.INIT(4'hE))
\s_axi4_rdata_i[2]_i_6
(.I0(Rx_FIFO_occ_Reversed[0]),
.I1(Rx_FIFO_occ_Reversed[1]),
.O(\s_axi4_rdata_i[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'h2000000000002000))
\s_axi4_rdata_i[3]_i_4
(.I0(p_1_in),
.I1(empty),
.I2(Bus_RNW_reg),
.I3(\s_axi4_rdata_i[4]_i_5_n_0 ),
.I4(\s_axi4_rdata_i[3]_i_6_n_0 ),
.I5(Rx_FIFO_occ_Reversed[3]),
.O(\s_axi4_rdata_i[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hFE))
\s_axi4_rdata_i[3]_i_6
(.I0(Rx_FIFO_occ_Reversed[2]),
.I1(Rx_FIFO_occ_Reversed[1]),
.I2(Rx_FIFO_occ_Reversed[0]),
.O(\s_axi4_rdata_i[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h2000000000002000))
\s_axi4_rdata_i[4]_i_3
(.I0(p_1_in),
.I1(empty),
.I2(Bus_RNW_reg),
.I3(\s_axi4_rdata_i[4]_i_5_n_0 ),
.I4(\s_axi4_rdata_i[4]_i_6_n_0 ),
.I5(Rx_FIFO_occ_Reversed[4]),
.O(\s_axi4_rdata_i[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT4 #(
.INIT(16'hFFFE))
\s_axi4_rdata_i[4]_i_5
(.I0(Rx_FIFO_occ_Reversed[8]),
.I1(Rx_FIFO_occ_Reversed[6]),
.I2(\s_axi4_rdata_i[7]_i_8_n_0 ),
.I3(Rx_FIFO_occ_Reversed[7]),
.O(\s_axi4_rdata_i[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'hFFFE))
\s_axi4_rdata_i[4]_i_6
(.I0(Rx_FIFO_occ_Reversed[3]),
.I1(Rx_FIFO_occ_Reversed[0]),
.I2(Rx_FIFO_occ_Reversed[1]),
.I3(Rx_FIFO_occ_Reversed[2]),
.O(\s_axi4_rdata_i[4]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5555000000005554))
\s_axi4_rdata_i[5]_i_4
(.I0(\s_axi4_rdata_i_reg[5]_0 ),
.I1(Rx_FIFO_occ_Reversed[8]),
.I2(Rx_FIFO_occ_Reversed[6]),
.I3(Rx_FIFO_occ_Reversed[7]),
.I4(\s_axi4_rdata_i[5]_i_6_n_0 ),
.I5(Rx_FIFO_occ_Reversed[5]),
.O(\s_axi4_rdata_i[5]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\s_axi4_rdata_i[5]_i_6
(.I0(Rx_FIFO_occ_Reversed[4]),
.I1(Rx_FIFO_occ_Reversed[2]),
.I2(Rx_FIFO_occ_Reversed[1]),
.I3(Rx_FIFO_occ_Reversed[0]),
.I4(Rx_FIFO_occ_Reversed[3]),
.O(\s_axi4_rdata_i[5]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h55000054))
\s_axi4_rdata_i[6]_i_3
(.I0(\s_axi4_rdata_i_reg[5]_0 ),
.I1(Rx_FIFO_occ_Reversed[8]),
.I2(Rx_FIFO_occ_Reversed[7]),
.I3(\s_axi4_rdata_i[7]_i_8_n_0 ),
.I4(Rx_FIFO_occ_Reversed[6]),
.O(\s_axi4_rdata_i[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000FB0000000000))
\s_axi4_rdata_i[7]_i_3
(.I0(Rx_FIFO_occ_Reversed[7]),
.I1(\s_axi4_rdata_i[7]_i_7_n_0 ),
.I2(Rx_FIFO_occ_Reversed[8]),
.I3(Bus_RNW_reg),
.I4(empty),
.I5(p_1_in),
.O(\s_axi4_rdata_i[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'h56))
\s_axi4_rdata_i[7]_i_4
(.I0(Rx_FIFO_occ_Reversed[7]),
.I1(\s_axi4_rdata_i[7]_i_8_n_0 ),
.I2(Rx_FIFO_occ_Reversed[6]),
.O(\s_axi4_rdata_i[7]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT2 #(
.INIT(4'h1))
\s_axi4_rdata_i[7]_i_7
(.I0(Rx_FIFO_occ_Reversed[6]),
.I1(\s_axi4_rdata_i[7]_i_8_n_0 ),
.O(\s_axi4_rdata_i[7]_i_7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\s_axi4_rdata_i[7]_i_8
(.I0(Rx_FIFO_occ_Reversed[5]),
.I1(Rx_FIFO_occ_Reversed[3]),
.I2(Rx_FIFO_occ_Reversed[0]),
.I3(Rx_FIFO_occ_Reversed[1]),
.I4(Rx_FIFO_occ_Reversed[2]),
.I5(Rx_FIFO_occ_Reversed[4]),
.O(\s_axi4_rdata_i[7]_i_8_n_0 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_fifo_ifmodule
(rc_FIFO_Full_d1,
tx_FIFO_Empty_d1,
receive_ip2bus_error,
transmit_ip2bus_error,
tx_FIFO_Occpncy_MSB_d1,
reset2ip_reset_int,
Rx_FIFO_Full_Fifo_d1_synced_i,
s_axi4_aclk,
Tx_FIFO_Empty_intr,
Transmit_ip2bus_error0,
tx_occ_msb,
Receive_ip2bus_error_reg_0,
prmry_in,
p_4_in,
Bus_RNW_reg);
output rc_FIFO_Full_d1;
output tx_FIFO_Empty_d1;
output receive_ip2bus_error;
output transmit_ip2bus_error;
output tx_FIFO_Occpncy_MSB_d1;
input reset2ip_reset_int;
input Rx_FIFO_Full_Fifo_d1_synced_i;
input s_axi4_aclk;
input Tx_FIFO_Empty_intr;
input Transmit_ip2bus_error0;
input tx_occ_msb;
input Receive_ip2bus_error_reg_0;
input prmry_in;
input p_4_in;
input Bus_RNW_reg;
wire Bus_RNW_reg;
wire Receive_ip2bus_error0;
wire Receive_ip2bus_error_reg_0;
wire Rx_FIFO_Full_Fifo_d1_synced_i;
wire Transmit_ip2bus_error0;
wire Tx_FIFO_Empty_intr;
wire p_4_in;
wire prmry_in;
wire rc_FIFO_Full_d1;
wire receive_ip2bus_error;
wire reset2ip_reset_int;
wire s_axi4_aclk;
wire transmit_ip2bus_error;
wire tx_FIFO_Empty_d1;
wire tx_FIFO_Occpncy_MSB_d1;
wire tx_occ_msb;
LUT4 #(
.INIT(16'hE000))
Receive_ip2bus_error_i_1
(.I0(Receive_ip2bus_error_reg_0),
.I1(prmry_in),
.I2(p_4_in),
.I3(Bus_RNW_reg),
.O(Receive_ip2bus_error0));
FDRE Receive_ip2bus_error_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(Receive_ip2bus_error0),
.Q(receive_ip2bus_error),
.R(reset2ip_reset_int));
FDRE Transmit_ip2bus_error_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(Transmit_ip2bus_error0),
.Q(transmit_ip2bus_error),
.R(reset2ip_reset_int));
FDRE rc_FIFO_Full_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(Rx_FIFO_Full_Fifo_d1_synced_i),
.Q(rc_FIFO_Full_d1),
.R(reset2ip_reset_int));
FDSE tx_FIFO_Empty_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(Tx_FIFO_Empty_intr),
.Q(tx_FIFO_Empty_d1),
.S(reset2ip_reset_int));
FDRE tx_FIFO_Occpncy_MSB_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(tx_occ_msb),
.Q(tx_FIFO_Occpncy_MSB_d1),
.R(reset2ip_reset_int));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_mode_0_module
(sck_t,
io0_t,
ss_t,
io1_t,
sck_o,
transfer_start_d1,
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ,
spiXfer_done_int,
Ratio_Count,
Count_trigger,
io1_o,
serial_dout_int,
ss_o,
D01_out,
D0,
rd_en,
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2 ,
din,
D_0,
ext_spi_clk,
R,
Rst_to_spi,
empty,
D,
transfer_start_reg_0,
\SS_O_reg[0]_0 ,
SPICR_2_MST_N_SLV_to_spi_clk,
\OTHER_RATIO_GENERATE.Serial_Dout_reg_0 ,
\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ,
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg ,
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg ,
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_1 ,
spicr_9_lsb_to_spi_clk,
spicr_4_cpha_to_spi_clk,
spicr_3_cpol_to_spi_clk,
dout,
scndry_out,
almost_full,
spicr_0_loop_to_spi_clk,
register_Data_slvsel_int);
output sck_t;
output io0_t;
output ss_t;
output io1_t;
output sck_o;
output transfer_start_d1;
output \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ;
output spiXfer_done_int;
output Ratio_Count;
output Count_trigger;
output io1_o;
output serial_dout_int;
output [0:0]ss_o;
output D01_out;
output D0;
output rd_en;
output \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2 ;
output [7:0]din;
input D_0;
input ext_spi_clk;
input R;
input Rst_to_spi;
input empty;
input [0:0]D;
input transfer_start_reg_0;
input \SS_O_reg[0]_0 ;
input SPICR_2_MST_N_SLV_to_spi_clk;
input \OTHER_RATIO_GENERATE.Serial_Dout_reg_0 ;
input \OTHER_RATIO_GENERATE.sck_o_int_reg_0 ;
input \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg ;
input \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg ;
input \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_1 ;
input spicr_9_lsb_to_spi_clk;
input spicr_4_cpha_to_spi_clk;
input spicr_3_cpol_to_spi_clk;
input [7:0]dout;
input scndry_out;
input almost_full;
input spicr_0_loop_to_spi_clk;
input register_Data_slvsel_int;
wire [1:0]Count;
wire Count_trigger;
wire Count_trigger_d1;
wire [0:0]D;
wire D0;
wire D01_out;
wire DRR_Overrun_reg_int0;
wire D_0;
wire \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0 ;
wire \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0 ;
wire \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0 ;
wire \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0 ;
wire \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2 ;
wire \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg ;
wire \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg ;
wire \OTHER_RATIO_GENERATE.Count[2]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Count[3]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 ;
wire \OTHER_RATIO_GENERATE.Count[4]_i_3_n_0 ;
wire \OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ;
wire \OTHER_RATIO_GENERATE.Count_reg_n_0_[1] ;
wire \OTHER_RATIO_GENERATE.Count_reg_n_0_[2] ;
wire \OTHER_RATIO_GENERATE.Count_reg_n_0_[3] ;
wire \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ;
wire \OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0 ;
wire \OTHER_RATIO_GENERATE.Serial_Dout_i_5_n_0 ;
wire \OTHER_RATIO_GENERATE.Serial_Dout_reg_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0 ;
wire \OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0 ;
wire \OTHER_RATIO_GENERATE.sck_o_int_reg_0 ;
wire \OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0 ;
wire R;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_1 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0 ;
wire \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0 ;
wire Ratio_Count;
wire Rst_to_spi;
wire SCK_O_1;
wire SPICR_2_MST_N_SLV_to_spi_clk;
wire SPIXfer_done_int_d1;
wire SPIXfer_done_int_pulse_d1;
wire SR_5_Tx_Empty_d1;
wire SR_5_Tx_comeplete_Empty;
wire SR_5_Tx_comeplete_Empty_i_1_n_0;
wire \SS_O[0]_i_3_n_0 ;
wire \SS_O[0]_i_4_n_0 ;
wire \SS_O_reg[0]_0 ;
wire Sync_Set;
wire almost_full;
wire [7:0]din;
wire [7:0]dout;
wire drr_Overrun_int;
wire empty;
wire ext_spi_clk;
wire io0_t;
wire io1_o;
wire io1_t;
wire load;
wire p_19_in;
wire [7:0]p_2_in__0;
wire p_3_in;
wire rd_en;
wire register_Data_slvsel_int;
wire [0:7]rx_shft_reg_mode_0011;
wire rx_shft_reg_mode_00110;
wire [0:7]rx_shft_reg_mode_0110;
wire rx_shft_reg_mode_01100;
wire sck_d1;
wire sck_d2;
wire sck_o;
wire sck_o_int;
wire sck_t;
wire scndry_out;
wire serial_dout_int;
wire spiXfer_done_int;
wire [1:0]spi_cntrl_ps;
wire spicr_0_loop_to_spi_clk;
wire spicr_3_cpol_to_spi_clk;
wire spicr_4_cpha_to_spi_clk;
wire spicr_9_lsb_to_spi_clk;
wire [0:0]ss_o;
wire ss_t;
wire stop_clock;
wire stop_clock_reg;
wire transfer_start_d1;
wire transfer_start_reg_0;
wire transfer_start_reg_n_0;
LUT6 #(
.INIT(64'h000F0008000FFF08))
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1
(.I0(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0 ),
.I1(SPICR_2_MST_N_SLV_to_spi_clk),
.I2(empty),
.I3(spi_cntrl_ps[1]),
.I4(spi_cntrl_ps[0]),
.I5(SR_5_Tx_comeplete_Empty),
.O(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h2))
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2
(.I0(transfer_start_reg_n_0),
.I1(transfer_start_d1),
.O(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT4 #(
.INIT(16'hAA8A))
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1
(.I0(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0 ),
.I1(spiXfer_done_int),
.I2(register_Data_slvsel_int),
.I3(spi_cntrl_ps[0]),
.O(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000022AA0CCC0000))
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2
(.I0(empty),
.I1(SR_5_Tx_comeplete_Empty),
.I2(spicr_0_loop_to_spi_clk),
.I3(spiXfer_done_int),
.I4(spi_cntrl_ps[1]),
.I5(spi_cntrl_ps[0]),
.O(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0 ));
(* FSM_ENCODED_STATES = "transfer_okay:01,temp_transfer_okay:10,idle:00" *)
FDRE \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg[0]
(.C(ext_spi_clk),
.CE(1'b1),
.D(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0 ),
.Q(spi_cntrl_ps[0]),
.R(Rst_to_spi));
(* FSM_ENCODED_STATES = "transfer_okay:01,temp_transfer_okay:10,idle:00" *)
FDRE \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg[1]
(.C(ext_spi_clk),
.CE(1'b1),
.D(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0 ),
.Q(spi_cntrl_ps[1]),
.R(Rst_to_spi));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT4 #(
.INIT(16'h0040))
\LOCAL_TX_EMPTY_FIFO_12_GEN.DRR_Overrun_reg_int_i_1
(.I0(scndry_out),
.I1(almost_full),
.I2(spiXfer_done_int),
.I3(drr_Overrun_int),
.O(DRR_Overrun_reg_int0));
FDRE \LOCAL_TX_EMPTY_FIFO_12_GEN.DRR_Overrun_reg_int_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(DRR_Overrun_reg_int0),
.Q(drr_Overrun_int),
.R(Rst_to_spi));
LUT1 #(
.INIT(2'h1))
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_1
(.I0(\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2 ),
.O(stop_clock));
FDRE \LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(stop_clock),
.Q(stop_clock_reg),
.R(Rst_to_spi));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h6))
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_i_1
(.I0(drr_Overrun_int),
.I1(\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg ),
.O(D0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'h6))
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_i_1
(.I0(spiXfer_done_int),
.I1(\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg ),
.O(D01_out));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT1 #(
.INIT(2'h1))
\OTHER_RATIO_GENERATE.Count[0]_i_1
(.I0(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.O(Count[0]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h6))
\OTHER_RATIO_GENERATE.Count[1]_i_1
(.I0(\OTHER_RATIO_GENERATE.Count_reg_n_0_[1] ),
.I1(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.O(Count[1]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'h78))
\OTHER_RATIO_GENERATE.Count[2]_i_1
(.I0(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.I1(\OTHER_RATIO_GENERATE.Count_reg_n_0_[1] ),
.I2(\OTHER_RATIO_GENERATE.Count_reg_n_0_[2] ),
.O(\OTHER_RATIO_GENERATE.Count[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT4 #(
.INIT(16'h7F80))
\OTHER_RATIO_GENERATE.Count[3]_i_1
(.I0(\OTHER_RATIO_GENERATE.Count_reg_n_0_[1] ),
.I1(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.I2(\OTHER_RATIO_GENERATE.Count_reg_n_0_[2] ),
.I3(\OTHER_RATIO_GENERATE.Count_reg_n_0_[3] ),
.O(\OTHER_RATIO_GENERATE.Count[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFFF7))
\OTHER_RATIO_GENERATE.Count[4]_i_1
(.I0(SPICR_2_MST_N_SLV_to_spi_clk),
.I1(transfer_start_reg_n_0),
.I2(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.I3(Rst_to_spi),
.O(\OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'h14))
\OTHER_RATIO_GENERATE.Count[4]_i_2
(.I0(load),
.I1(Count_trigger_d1),
.I2(Count_trigger),
.O(\OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT4 #(
.INIT(16'h8000))
\OTHER_RATIO_GENERATE.Count[4]_i_3
(.I0(\OTHER_RATIO_GENERATE.Count_reg_n_0_[3] ),
.I1(\OTHER_RATIO_GENERATE.Count_reg_n_0_[1] ),
.I2(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.I3(\OTHER_RATIO_GENERATE.Count_reg_n_0_[2] ),
.O(\OTHER_RATIO_GENERATE.Count[4]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.Count_reg[0]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 ),
.D(Count[0]),
.Q(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.R(\OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.Count_reg[1]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 ),
.D(Count[1]),
.Q(\OTHER_RATIO_GENERATE.Count_reg_n_0_[1] ),
.R(\OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.Count_reg[2]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 ),
.D(\OTHER_RATIO_GENERATE.Count[2]_i_1_n_0 ),
.Q(\OTHER_RATIO_GENERATE.Count_reg_n_0_[2] ),
.R(\OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.Count_reg[3]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 ),
.D(\OTHER_RATIO_GENERATE.Count[3]_i_1_n_0 ),
.Q(\OTHER_RATIO_GENERATE.Count_reg_n_0_[3] ),
.R(\OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.Count_reg[4]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Count[4]_i_2_n_0 ),
.D(\OTHER_RATIO_GENERATE.Count[4]_i_3_n_0 ),
.Q(load),
.R(\OTHER_RATIO_GENERATE.Count[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'h08))
\OTHER_RATIO_GENERATE.Count_trigger_d1_i_1
(.I0(Count_trigger),
.I1(transfer_start_reg_n_0),
.I2(Rst_to_spi),
.O(\OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0 ));
FDRE \OTHER_RATIO_GENERATE.Count_trigger_d1_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(\OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0 ),
.Q(Count_trigger_d1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT4 #(
.INIT(16'h0090))
\OTHER_RATIO_GENERATE.Count_trigger_i_1
(.I0(Count_trigger),
.I1(Ratio_Count),
.I2(transfer_start_reg_n_0),
.I3(Rst_to_spi),
.O(\OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0 ));
FDRE \OTHER_RATIO_GENERATE.Count_trigger_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(\OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0 ),
.Q(Count_trigger),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hDF))
\OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1
(.I0(transfer_start_reg_n_0),
.I1(Rst_to_spi),
.I2(Ratio_Count),
.O(\OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0 ));
FDRE \OTHER_RATIO_GENERATE.Ratio_Count_reg[0]
(.C(ext_spi_clk),
.CE(1'b1),
.D(\OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0 ),
.Q(Ratio_Count),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\OTHER_RATIO_GENERATE.Serial_Dout_i_1
(.I0(p_3_in),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(\OTHER_RATIO_GENERATE.Serial_Dout_reg_0 ),
.I3(\OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0 ),
.I4(io1_o),
.O(\OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000454500FF4545))
\OTHER_RATIO_GENERATE.Serial_Dout_i_2
(.I0(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.I1(empty),
.I2(SR_5_Tx_Empty_d1),
.I3(SPIXfer_done_int_d1),
.I4(SPICR_2_MST_N_SLV_to_spi_clk),
.I5(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0 ),
.O(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF7F0000FF7FFF5F))
\OTHER_RATIO_GENERATE.Serial_Dout_i_4
(.I0(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.I1(transfer_start_d1),
.I2(SPICR_2_MST_N_SLV_to_spi_clk),
.I3(SPIXfer_done_int_d1),
.I4(transfer_start_reg_n_0),
.I5(\OTHER_RATIO_GENERATE.Serial_Dout_i_5_n_0 ),
.O(\OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT4 #(
.INIT(16'h000D))
\OTHER_RATIO_GENERATE.Serial_Dout_i_5
(.I0(SR_5_Tx_Empty_d1),
.I1(empty),
.I2(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.I3(SPICR_2_MST_N_SLV_to_spi_clk),
.O(\OTHER_RATIO_GENERATE.Serial_Dout_i_5_n_0 ));
FDSE \OTHER_RATIO_GENERATE.Serial_Dout_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(\OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0 ),
.Q(io1_o),
.S(Rst_to_spi));
LUT5 #(
.INIT(32'h2800FFFF))
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1
(.I0(SPICR_2_MST_N_SLV_to_spi_clk),
.I1(Count_trigger),
.I2(Count_trigger_d1),
.I3(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.I4(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2
(.I0(p_2_in__0[7]),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(dout[0]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(dout[7]),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1
(.I0(p_2_in__0[6]),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(dout[1]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(dout[6]),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1
(.I0(p_2_in__0[5]),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(dout[2]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(dout[5]),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1
(.I0(p_2_in__0[4]),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(dout[3]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(dout[4]),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1
(.I0(p_2_in__0[3]),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(dout[4]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(dout[3]),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1
(.I0(p_2_in__0[2]),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(dout[5]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(dout[2]),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1
(.I0(p_2_in__0[1]),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(dout[6]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(dout[1]),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1
(.I0(p_2_in__0[0]),
.I1(\OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0 ),
.I2(dout[7]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(dout[0]),
.O(\OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1_n_0 ));
FDRE \OTHER_RATIO_GENERATE.Shift_Reg_reg[0]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ),
.D(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0 ),
.Q(p_3_in),
.R(Rst_to_spi));
FDSE \OTHER_RATIO_GENERATE.Shift_Reg_reg[1]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ),
.D(\OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0 ),
.Q(p_2_in__0[7]),
.S(Rst_to_spi));
FDRE \OTHER_RATIO_GENERATE.Shift_Reg_reg[2]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ),
.D(\OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0 ),
.Q(p_2_in__0[6]),
.R(Rst_to_spi));
FDRE \OTHER_RATIO_GENERATE.Shift_Reg_reg[3]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ),
.D(\OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0 ),
.Q(p_2_in__0[5]),
.R(Rst_to_spi));
FDRE \OTHER_RATIO_GENERATE.Shift_Reg_reg[4]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ),
.D(\OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0 ),
.Q(p_2_in__0[4]),
.R(Rst_to_spi));
FDRE \OTHER_RATIO_GENERATE.Shift_Reg_reg[5]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ),
.D(\OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0 ),
.Q(p_2_in__0[3]),
.R(Rst_to_spi));
FDRE \OTHER_RATIO_GENERATE.Shift_Reg_reg[6]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ),
.D(\OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0 ),
.Q(p_2_in__0[2]),
.R(Rst_to_spi));
FDRE \OTHER_RATIO_GENERATE.Shift_Reg_reg[7]
(.C(ext_spi_clk),
.CE(\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0 ),
.D(\OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1_n_0 ),
.Q(p_2_in__0[1]),
.R(Rst_to_spi));
LUT3 #(
.INIT(8'h08))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011[0]_i_1
(.I0(sck_d1),
.I1(transfer_start_reg_n_0),
.I2(sck_d2),
.O(rx_shft_reg_mode_00110));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[0]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_00110),
.D(rx_shft_reg_mode_0011[1]),
.Q(rx_shft_reg_mode_0011[0]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[1]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_00110),
.D(rx_shft_reg_mode_0011[2]),
.Q(rx_shft_reg_mode_0011[1]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[2]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_00110),
.D(rx_shft_reg_mode_0011[3]),
.Q(rx_shft_reg_mode_0011[2]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[3]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_00110),
.D(rx_shft_reg_mode_0011[4]),
.Q(rx_shft_reg_mode_0011[3]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[4]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_00110),
.D(rx_shft_reg_mode_0011[5]),
.Q(rx_shft_reg_mode_0011[4]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[5]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_00110),
.D(rx_shft_reg_mode_0011[6]),
.Q(rx_shft_reg_mode_0011[5]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[6]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_00110),
.D(rx_shft_reg_mode_0011[7]),
.Q(rx_shft_reg_mode_0011[6]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[7]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_00110),
.D(D),
.Q(rx_shft_reg_mode_0011[7]),
.R(Rst_to_spi));
LUT3 #(
.INIT(8'h08))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110[0]_i_1
(.I0(sck_d2),
.I1(transfer_start_reg_n_0),
.I2(sck_d1),
.O(rx_shft_reg_mode_01100));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[0]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_01100),
.D(rx_shft_reg_mode_0110[1]),
.Q(rx_shft_reg_mode_0110[0]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[1]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_01100),
.D(rx_shft_reg_mode_0110[2]),
.Q(rx_shft_reg_mode_0110[1]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[2]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_01100),
.D(rx_shft_reg_mode_0110[3]),
.Q(rx_shft_reg_mode_0110[2]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[3]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_01100),
.D(rx_shft_reg_mode_0110[4]),
.Q(rx_shft_reg_mode_0110[3]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[4]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_01100),
.D(rx_shft_reg_mode_0110[5]),
.Q(rx_shft_reg_mode_0110[4]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[5]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_01100),
.D(rx_shft_reg_mode_0110[6]),
.Q(rx_shft_reg_mode_0110[5]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[6]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_01100),
.D(rx_shft_reg_mode_0110[7]),
.Q(rx_shft_reg_mode_0110[6]),
.R(Rst_to_spi));
FDRE #(
.INIT(1'b0))
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[7]
(.C(ext_spi_clk),
.CE(rx_shft_reg_mode_01100),
.D(D),
.Q(rx_shft_reg_mode_0110[7]),
.R(Rst_to_spi));
FDRE \OTHER_RATIO_GENERATE.sck_d1_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(sck_o_int),
.Q(sck_d1),
.R(Rst_to_spi));
FDRE \OTHER_RATIO_GENERATE.sck_d2_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(sck_d1),
.Q(sck_d2),
.R(Rst_to_spi));
LUT6 #(
.INIT(64'h0000F10000000000))
\OTHER_RATIO_GENERATE.sck_o_int_i_1
(.I0(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.I1(\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0 ),
.I2(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I3(SPICR_2_MST_N_SLV_to_spi_clk),
.I4(Rst_to_spi),
.I5(\OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0 ),
.O(\OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0 ));
LUT5 #(
.INIT(32'hFF9FFF60))
\OTHER_RATIO_GENERATE.sck_o_int_i_2
(.I0(Count_trigger_d1),
.I1(Count_trigger),
.I2(transfer_start_reg_n_0),
.I3(Sync_Set),
.I4(sck_o_int),
.O(\OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'h66660060))
\OTHER_RATIO_GENERATE.sck_o_int_i_3
(.I0(spicr_4_cpha_to_spi_clk),
.I1(spicr_3_cpol_to_spi_clk),
.I2(transfer_start_reg_n_0),
.I3(transfer_start_d1),
.I4(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.O(Sync_Set));
FDRE \OTHER_RATIO_GENERATE.sck_o_int_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(\OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0 ),
.Q(sck_o_int),
.R(1'b0));
LUT3 #(
.INIT(8'h08))
\OTHER_RATIO_GENERATE.serial_dout_int_i_1
(.I0(io1_o),
.I1(spicr_0_loop_to_spi_clk),
.I2(Rst_to_spi),
.O(\OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0 ));
FDRE \OTHER_RATIO_GENERATE.serial_dout_int_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(\OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0 ),
.Q(serial_dout_int),
.R(1'b0));
(* IOB = "TRUE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST
(.C(ext_spi_clk),
.CE(1'b1),
.D(SCK_O_1),
.Q(sck_o),
.R(R));
LUT6 #(
.INIT(64'hCCCC8CCC00008000))
\RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST_i_2
(.I0(sck_o_int),
.I1(SPICR_2_MST_N_SLV_to_spi_clk),
.I2(transfer_start_reg_n_0),
.I3(transfer_start_d1),
.I4(load),
.I5(spicr_3_cpol_to_spi_clk),
.O(SCK_O_1));
FDRE \RISING_EDGE_CLK_RATIO_4_GEN.Serial_Din_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(D),
.Q(p_2_in__0[0]),
.R(Rst_to_spi));
LUT6 #(
.INIT(64'h0010001000000010))
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1
(.I0(Rst_to_spi),
.I1(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0 ),
.I2(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_1 ),
.I3(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.I4(transfer_start_reg_n_0),
.I5(transfer_start_d1),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT4 #(
.INIT(16'h7FFF))
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2
(.I0(\OTHER_RATIO_GENERATE.Count_reg_n_0_[2] ),
.I1(\OTHER_RATIO_GENERATE.Count_reg_n_0_[0] ),
.I2(\OTHER_RATIO_GENERATE.Count_reg_n_0_[1] ),
.I3(\OTHER_RATIO_GENERATE.Count_reg_n_0_[3] ),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0 ));
FDRE \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0 ),
.Q(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1
(.I0(SPIXfer_done_int_pulse_d1),
.I1(SPICR_2_MST_N_SLV_to_spi_clk),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFE2CCE233E200E2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2
(.I0(rx_shft_reg_mode_0011[0]),
.I1(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I2(rx_shft_reg_mode_0110[0]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(rx_shft_reg_mode_0011[7]),
.I5(rx_shft_reg_mode_0110[7]),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFE2CCE233E200E2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1
(.I0(rx_shft_reg_mode_0011[1]),
.I1(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I2(rx_shft_reg_mode_0110[1]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(rx_shft_reg_mode_0011[6]),
.I5(rx_shft_reg_mode_0110[6]),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFE2CCE233E200E2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1
(.I0(rx_shft_reg_mode_0011[2]),
.I1(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I2(rx_shft_reg_mode_0110[2]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(rx_shft_reg_mode_0011[5]),
.I5(rx_shft_reg_mode_0110[5]),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFE2CCE233E200E2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1
(.I0(rx_shft_reg_mode_0011[3]),
.I1(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I2(rx_shft_reg_mode_0110[3]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(rx_shft_reg_mode_0011[4]),
.I5(rx_shft_reg_mode_0110[4]),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFE2CCE233E200E2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1
(.I0(rx_shft_reg_mode_0011[4]),
.I1(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I2(rx_shft_reg_mode_0110[4]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(rx_shft_reg_mode_0011[3]),
.I5(rx_shft_reg_mode_0110[3]),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFE2CCE233E200E2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1
(.I0(rx_shft_reg_mode_0011[5]),
.I1(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I2(rx_shft_reg_mode_0110[5]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(rx_shft_reg_mode_0011[2]),
.I5(rx_shft_reg_mode_0110[2]),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFE2CCE233E200E2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1
(.I0(rx_shft_reg_mode_0011[6]),
.I1(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I2(rx_shft_reg_mode_0110[6]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(rx_shft_reg_mode_0011[1]),
.I5(rx_shft_reg_mode_0110[1]),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFE2CCE233E200E2))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1
(.I0(rx_shft_reg_mode_0011[7]),
.I1(\OTHER_RATIO_GENERATE.sck_o_int_reg_0 ),
.I2(rx_shft_reg_mode_0110[7]),
.I3(spicr_9_lsb_to_spi_clk),
.I4(rx_shft_reg_mode_0011[0]),
.I5(rx_shft_reg_mode_0110[0]),
.O(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[0]
(.C(ext_spi_clk),
.CE(SPIXfer_done_int_pulse_d1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0 ),
.Q(din[7]),
.R(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[1]
(.C(ext_spi_clk),
.CE(SPIXfer_done_int_pulse_d1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0 ),
.Q(din[6]),
.R(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[2]
(.C(ext_spi_clk),
.CE(SPIXfer_done_int_pulse_d1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0 ),
.Q(din[5]),
.R(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[3]
(.C(ext_spi_clk),
.CE(SPIXfer_done_int_pulse_d1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0 ),
.Q(din[4]),
.R(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[4]
(.C(ext_spi_clk),
.CE(SPIXfer_done_int_pulse_d1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0 ),
.Q(din[3]),
.R(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[5]
(.C(ext_spi_clk),
.CE(SPIXfer_done_int_pulse_d1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0 ),
.Q(din[2]),
.R(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[6]
(.C(ext_spi_clk),
.CE(SPIXfer_done_int_pulse_d1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0 ),
.Q(din[1]),
.R(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[7]
(.C(ext_spi_clk),
.CE(SPIXfer_done_int_pulse_d1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0 ),
.Q(din[0]),
.R(\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0 ));
FDRE SPIXfer_done_int_d1_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.Q(SPIXfer_done_int_d1),
.R(Rst_to_spi));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'h2))
SPIXfer_done_int_pulse_d1_i_1
(.I0(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.I1(SPIXfer_done_int_d1),
.O(p_19_in));
FDRE SPIXfer_done_int_pulse_d1_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(p_19_in),
.Q(SPIXfer_done_int_pulse_d1),
.R(Rst_to_spi));
FDRE SPIXfer_done_int_pulse_d2_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(SPIXfer_done_int_pulse_d1),
.Q(spiXfer_done_int),
.R(Rst_to_spi));
(* XILINX_LEGACY_PRIM = "FD" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
SPI_TRISTATE_CONTROL_II
(.C(ext_spi_clk),
.CE(1'b1),
.D(D_0),
.Q(sck_t),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "FD" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
SPI_TRISTATE_CONTROL_III
(.C(ext_spi_clk),
.CE(1'b1),
.D(D_0),
.Q(io0_t),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "FD" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
SPI_TRISTATE_CONTROL_IV
(.C(ext_spi_clk),
.CE(1'b1),
.D(D_0),
.Q(ss_t),
.R(1'b0));
(* DONT_TOUCH *)
(* XILINX_LEGACY_PRIM = "FD" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE GND:R" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1))
SPI_TRISTATE_CONTROL_V
(.C(ext_spi_clk),
.CE(1'b1),
.D(1'b1),
.Q(io1_t),
.R(1'b0));
FDRE SR_5_Tx_Empty_d1_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(empty),
.Q(SR_5_Tx_Empty_d1),
.R(Rst_to_spi));
LUT4 #(
.INIT(16'h88C8))
SR_5_Tx_comeplete_Empty_i_1
(.I0(SR_5_Tx_comeplete_Empty),
.I1(empty),
.I2(\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0 ),
.I3(SPIXfer_done_int_d1),
.O(SR_5_Tx_comeplete_Empty_i_1_n_0));
FDRE SR_5_Tx_comeplete_Empty_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(SR_5_Tx_comeplete_Empty_i_1_n_0),
.Q(SR_5_Tx_comeplete_Empty),
.R(1'b0));
LUT6 #(
.INIT(64'hFF55FF750F00FFFF))
\SS_O[0]_i_2
(.I0(\SS_O[0]_i_3_n_0 ),
.I1(spicr_0_loop_to_spi_clk),
.I2(\SS_O[0]_i_4_n_0 ),
.I3(spi_cntrl_ps[0]),
.I4(empty),
.I5(spi_cntrl_ps[1]),
.O(\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT4 #(
.INIT(16'hFFC8))
\SS_O[0]_i_3
(.I0(spiXfer_done_int),
.I1(SR_5_Tx_comeplete_Empty),
.I2(register_Data_slvsel_int),
.I3(stop_clock_reg),
.O(\SS_O[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'h8))
\SS_O[0]_i_4
(.I0(spiXfer_done_int),
.I1(SR_5_Tx_comeplete_Empty),
.O(\SS_O[0]_i_4_n_0 ));
FDRE \SS_O_reg[0]
(.C(ext_spi_clk),
.CE(1'b1),
.D(\SS_O_reg[0]_0 ),
.Q(ss_o),
.R(1'b0));
FDRE transfer_start_d1_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(transfer_start_reg_n_0),
.Q(transfer_start_d1),
.R(Rst_to_spi));
FDRE transfer_start_reg
(.C(ext_spi_clk),
.CE(1'b1),
.D(transfer_start_reg_0),
.Q(transfer_start_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hBA))
\xpm_fifo_instance.xpm_fifo_async_inst_i_3
(.I0(spiXfer_done_int),
.I1(transfer_start_d1),
.I2(transfer_start_reg_n_0),
.O(rd_en));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_status_slave_sel_reg
(SPISSR_frm_axi_clk,
reset2ip_reset_int,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]_0 ,
s_axi4_aclk);
output SPISSR_frm_axi_clk;
input reset2ip_reset_int;
input \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]_0 ;
input s_axi4_aclk;
wire \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]_0 ;
wire SPISSR_frm_axi_clk;
wire reset2ip_reset_int;
wire s_axi4_aclk;
FDSE \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]_0 ),
.Q(SPISSR_frm_axi_clk),
.S(reset2ip_reset_int));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_module
(Rst_to_spi,
reset2ip_reset_int,
ext_spi_clk);
output Rst_to_spi;
input reset2ip_reset_int;
input ext_spi_clk;
wire Rst_to_spi;
wire Soft_Reset_frm_axi_d1;
wire ext_spi_clk;
wire reset2ip_reset_int;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
RESET_SYNC_AX2S_1
(.C(ext_spi_clk),
.CE(1'b1),
.D(reset2ip_reset_int),
.Q(Soft_Reset_frm_axi_d1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* XILINX_TRANSFORM_PINMAP = "VCC:CE" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
RESET_SYNC_AX2S_2
(.C(ext_spi_clk),
.CE(1'b1),
.D(Soft_Reset_frm_axi_d1),
.Q(Rst_to_spi),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_soft_reset
(sw_rst_cond_d1,
wrack,
\RESET_FLOPS[15].RST_FLOPS_0 ,
Bus2IP_Reset_i_reg,
rst,
bus2ip_reset_ipif_inverted,
sw_rst_cond,
s_axi4_aclk,
reset_trig0,
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg ,
TX_one_less_than_full,
Tx_FIFO_Full_i,
Tx_FIFO_Full_int);
output sw_rst_cond_d1;
output wrack;
output \RESET_FLOPS[15].RST_FLOPS_0 ;
output Bus2IP_Reset_i_reg;
output rst;
input bus2ip_reset_ipif_inverted;
input sw_rst_cond;
input s_axi4_aclk;
input reset_trig0;
input \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg ;
input TX_one_less_than_full;
input Tx_FIFO_Full_i;
input Tx_FIFO_Full_int;
wire Bus2IP_Reset_i_reg;
wire FF_WRACK_i_1_n_0;
wire \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg ;
wire \RESET_FLOPS[10].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[11].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[12].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[13].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[14].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[15].RST_FLOPS_0 ;
wire \RESET_FLOPS[15].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[4].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[5].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[6].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[7].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[8].RST_FLOPS_i_1_n_0 ;
wire \RESET_FLOPS[9].RST_FLOPS_i_1_n_0 ;
wire S;
wire TX_one_less_than_full;
wire Tx_FIFO_Full_i;
wire Tx_FIFO_Full_int;
wire bus2ip_reset_ipif_inverted;
wire flop_q_chain_1;
wire flop_q_chain_10;
wire flop_q_chain_11;
wire flop_q_chain_12;
wire flop_q_chain_13;
wire flop_q_chain_14;
wire flop_q_chain_15;
wire flop_q_chain_2;
wire flop_q_chain_3;
wire flop_q_chain_4;
wire flop_q_chain_5;
wire flop_q_chain_6;
wire flop_q_chain_7;
wire flop_q_chain_8;
wire flop_q_chain_9;
wire reset_trig0;
wire rst;
wire s_axi4_aclk;
wire sw_rst_cond;
wire sw_rst_cond_d1;
wire wrack;
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
FF_WRACK
(.C(s_axi4_aclk),
.CE(1'b1),
.D(FF_WRACK_i_1_n_0),
.Q(wrack),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h2))
FF_WRACK_i_1
(.I0(\RESET_FLOPS[15].RST_FLOPS_0 ),
.I1(flop_q_chain_1),
.O(FF_WRACK_i_1_n_0));
LUT6 #(
.INIT(64'h0000000001010100))
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_1
(.I0(bus2ip_reset_ipif_inverted),
.I1(\RESET_FLOPS[15].RST_FLOPS_0 ),
.I2(\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg ),
.I3(TX_one_less_than_full),
.I4(Tx_FIFO_Full_i),
.I5(Tx_FIFO_Full_int),
.O(Bus2IP_Reset_i_reg));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[0].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(S),
.Q(flop_q_chain_15),
.R(bus2ip_reset_ipif_inverted));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[10].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[10].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_5),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[10].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_6),
.O(\RESET_FLOPS[10].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[11].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[11].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_4),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[11].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_5),
.O(\RESET_FLOPS[11].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[12].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[12].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_3),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[12].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_4),
.O(\RESET_FLOPS[12].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[13].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[13].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_2),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[13].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_3),
.O(\RESET_FLOPS[13].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[14].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[14].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_1),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[14].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_2),
.O(\RESET_FLOPS[14].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[15].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[15].RST_FLOPS_i_1_n_0 ),
.Q(\RESET_FLOPS[15].RST_FLOPS_0 ),
.R(bus2ip_reset_ipif_inverted));
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[15].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_1),
.O(\RESET_FLOPS[15].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[1].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_14),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[1].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_15),
.O(\RESET_FLOPS[1].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[2].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_13),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[2].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_14),
.O(\RESET_FLOPS[2].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[3].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_12),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[3].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_13),
.O(\RESET_FLOPS[3].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[4].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[4].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_11),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[4].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_12),
.O(\RESET_FLOPS[4].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[5].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[5].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_10),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[5].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_11),
.O(\RESET_FLOPS[5].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[6].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[6].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_9),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[6].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_10),
.O(\RESET_FLOPS[6].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[7].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[7].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_8),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[7].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_9),
.O(\RESET_FLOPS[7].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[8].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[8].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_7),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[8].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_8),
.O(\RESET_FLOPS[8].RST_FLOPS_i_1_n_0 ));
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\RESET_FLOPS[9].RST_FLOPS
(.C(s_axi4_aclk),
.CE(1'b1),
.D(\RESET_FLOPS[9].RST_FLOPS_i_1_n_0 ),
.Q(flop_q_chain_6),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'hE))
\RESET_FLOPS[9].RST_FLOPS_i_1
(.I0(S),
.I1(flop_q_chain_7),
.O(\RESET_FLOPS[9].RST_FLOPS_i_1_n_0 ));
FDRE reset_trig_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(reset_trig0),
.Q(S),
.R(bus2ip_reset_ipif_inverted));
FDRE sw_rst_cond_d1_reg
(.C(s_axi4_aclk),
.CE(1'b1),
.D(sw_rst_cond),
.Q(sw_rst_cond_d1),
.R(bus2ip_reset_ipif_inverted));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hFE))
\xpm_fifo_instance.xpm_fifo_async_inst_i_1
(.I0(bus2ip_reset_ipif_inverted),
.I1(\RESET_FLOPS[15].RST_FLOPS_0 ),
.I2(\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg ),
.O(rst));
endmodule
(* CHECK_LICENSE_TYPE = "xlnx_axi_quad_spi,axi_quad_spi,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_quad_spi,Vivado 2021.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(ext_spi_clk,
s_axi4_aclk,
s_axi4_aresetn,
s_axi4_awaddr,
s_axi4_awlen,
s_axi4_awsize,
s_axi4_awburst,
s_axi4_awlock,
s_axi4_awcache,
s_axi4_awprot,
s_axi4_awvalid,
s_axi4_awready,
s_axi4_wdata,
s_axi4_wstrb,
s_axi4_wlast,
s_axi4_wvalid,
s_axi4_wready,
s_axi4_bresp,
s_axi4_bvalid,
s_axi4_bready,
s_axi4_araddr,
s_axi4_arlen,
s_axi4_arsize,
s_axi4_arburst,
s_axi4_arlock,
s_axi4_arcache,
s_axi4_arprot,
s_axi4_arvalid,
s_axi4_arready,
s_axi4_rdata,
s_axi4_rresp,
s_axi4_rlast,
s_axi4_rvalid,
s_axi4_rready,
io0_i,
io0_o,
io0_t,
io1_i,
io1_o,
io1_t,
sck_i,
sck_o,
sck_t,
ss_i,
ss_o,
ss_t,
ip2intc_irpt);
(* x_interface_info = "xilinx.com:signal:clock:1.0 spi_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME spi_clk, ASSOCIATED_BUSIF SPI_0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input ext_spi_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 full_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME full_clk, ASSOCIATED_BUSIF AXI_FULL, ASSOCIATED_RESET s_axi4_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) input s_axi4_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 full_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME full_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input s_axi4_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME AXI_FULL, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 24, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) input [23:0]s_axi4_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWLEN" *) input [7:0]s_axi4_awlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWSIZE" *) input [2:0]s_axi4_awsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWBURST" *) input [1:0]s_axi4_awburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWLOCK" *) input s_axi4_awlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWCACHE" *) input [3:0]s_axi4_awcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWPROT" *) input [2:0]s_axi4_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWVALID" *) input s_axi4_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL AWREADY" *) output s_axi4_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL WDATA" *) input [31:0]s_axi4_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL WSTRB" *) input [3:0]s_axi4_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL WLAST" *) input s_axi4_wlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL WVALID" *) input s_axi4_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL WREADY" *) output s_axi4_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL BRESP" *) output [1:0]s_axi4_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL BVALID" *) output s_axi4_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL BREADY" *) input s_axi4_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARADDR" *) input [23:0]s_axi4_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARLEN" *) input [7:0]s_axi4_arlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARSIZE" *) input [2:0]s_axi4_arsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARBURST" *) input [1:0]s_axi4_arburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARLOCK" *) input s_axi4_arlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARCACHE" *) input [3:0]s_axi4_arcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARPROT" *) input [2:0]s_axi4_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARVALID" *) input s_axi4_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL ARREADY" *) output s_axi4_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL RDATA" *) output [31:0]s_axi4_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL RRESP" *) output [1:0]s_axi4_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL RLAST" *) output s_axi4_rlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL RVALID" *) output s_axi4_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 AXI_FULL RREADY" *) input s_axi4_rready;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 IO0_I" *) (* x_interface_parameter = "XIL_INTERFACENAME SPI_0, BOARD.ASSOCIATED_PARAM QSPI_BOARD_INTERFACE" *) input io0_i;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 IO0_O" *) output io0_o;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 IO0_T" *) output io0_t;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 IO1_I" *) input io1_i;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 IO1_O" *) output io1_o;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 IO1_T" *) output io1_t;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 SCK_I" *) input sck_i;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 SCK_O" *) output sck_o;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 SCK_T" *) output sck_t;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 SS_I" *) input [0:0]ss_i;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 SS_O" *) output [0:0]ss_o;
(* x_interface_info = "xilinx.com:interface:spi:1.0 SPI_0 SS_T" *) output ss_t;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME interrupt, SENSITIVITY EDGE_RISING, PortWidth 1" *) output ip2intc_irpt;
wire \<const0> ;
wire ext_spi_clk;
wire io0_i;
wire io0_o;
wire io0_t;
wire io1_i;
wire io1_o;
wire io1_t;
wire ip2intc_irpt;
wire s_axi4_aclk;
wire [23:0]s_axi4_araddr;
wire s_axi4_aresetn;
wire [7:0]s_axi4_arlen;
wire s_axi4_arready;
wire s_axi4_arvalid;
wire [23:0]s_axi4_awaddr;
wire [7:0]s_axi4_awlen;
wire s_axi4_awready;
wire s_axi4_awvalid;
wire s_axi4_bready;
wire [1:1]\^s_axi4_bresp ;
wire s_axi4_bvalid;
wire [31:0]\^s_axi4_rdata ;
wire s_axi4_rlast;
wire s_axi4_rready;
wire [1:1]\^s_axi4_rresp ;
wire s_axi4_rvalid;
wire [31:0]s_axi4_wdata;
wire s_axi4_wready;
wire [3:0]s_axi4_wstrb;
wire s_axi4_wvalid;
wire sck_o;
wire sck_t;
wire [0:0]ss_o;
wire ss_t;
wire NLW_U0_cfgclk_UNCONNECTED;
wire NLW_U0_cfgmclk_UNCONNECTED;
wire NLW_U0_eos_UNCONNECTED;
wire NLW_U0_io0_1_o_UNCONNECTED;
wire NLW_U0_io0_1_t_UNCONNECTED;
wire NLW_U0_io1_1_o_UNCONNECTED;
wire NLW_U0_io1_1_t_UNCONNECTED;
wire NLW_U0_io2_1_o_UNCONNECTED;
wire NLW_U0_io2_1_t_UNCONNECTED;
wire NLW_U0_io2_o_UNCONNECTED;
wire NLW_U0_io2_t_UNCONNECTED;
wire NLW_U0_io3_1_o_UNCONNECTED;
wire NLW_U0_io3_1_t_UNCONNECTED;
wire NLW_U0_io3_o_UNCONNECTED;
wire NLW_U0_io3_t_UNCONNECTED;
wire NLW_U0_preq_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_ss_1_o_UNCONNECTED;
wire NLW_U0_ss_1_t_UNCONNECTED;
wire [0:0]NLW_U0_s_axi4_bid_UNCONNECTED;
wire [0:0]NLW_U0_s_axi4_bresp_UNCONNECTED;
wire [30:10]NLW_U0_s_axi4_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi4_rid_UNCONNECTED;
wire [0:0]NLW_U0_s_axi4_rresp_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
assign s_axi4_bresp[1] = \^s_axi4_bresp [1];
assign s_axi4_bresp[0] = \<const0> ;
assign s_axi4_rdata[31] = \^s_axi4_rdata [31];
assign s_axi4_rdata[30] = \<const0> ;
assign s_axi4_rdata[29] = \<const0> ;
assign s_axi4_rdata[28] = \<const0> ;
assign s_axi4_rdata[27] = \<const0> ;
assign s_axi4_rdata[26] = \<const0> ;
assign s_axi4_rdata[25] = \<const0> ;
assign s_axi4_rdata[24] = \<const0> ;
assign s_axi4_rdata[23] = \<const0> ;
assign s_axi4_rdata[22] = \<const0> ;
assign s_axi4_rdata[21] = \<const0> ;
assign s_axi4_rdata[20] = \<const0> ;
assign s_axi4_rdata[19] = \<const0> ;
assign s_axi4_rdata[18] = \<const0> ;
assign s_axi4_rdata[17] = \<const0> ;
assign s_axi4_rdata[16] = \<const0> ;
assign s_axi4_rdata[15] = \<const0> ;
assign s_axi4_rdata[14] = \<const0> ;
assign s_axi4_rdata[13] = \<const0> ;
assign s_axi4_rdata[12] = \<const0> ;
assign s_axi4_rdata[11] = \<const0> ;
assign s_axi4_rdata[10] = \<const0> ;
assign s_axi4_rdata[9:0] = \^s_axi4_rdata [9:0];
assign s_axi4_rresp[1] = \^s_axi4_rresp [1];
assign s_axi4_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* Async_Clk = "0" *)
(* C_BYTE_LEVEL_INTERRUPT_EN = "0" *)
(* C_DUAL_QUAD_MODE = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FIFO_DEPTH = "256" *)
(* C_INSTANCE = "axi_quad_spi_inst" *)
(* C_LSB_STUP = "0" *)
(* C_NEW_SEQ_EN = "1" *)
(* C_NUM_SS_BITS = "1" *)
(* C_NUM_TRANSFER_BITS = "8" *)
(* C_SCK_RATIO = "4" *)
(* C_SELECT_XPM = "0" *)
(* C_SHARED_STARTUP = "0" *)
(* C_SPI_MEMORY = "1" *)
(* C_SPI_MEM_ADDR_BITS = "24" *)
(* C_SPI_MODE = "0" *)
(* C_SUB_FAMILY = "kintex7" *)
(* C_S_AXI4_ADDR_WIDTH = "24" *)
(* C_S_AXI4_BASEADDR = "-1" *)
(* C_S_AXI4_DATA_WIDTH = "32" *)
(* C_S_AXI4_HIGHADDR = "0" *)
(* C_S_AXI4_ID_WIDTH = "1" *)
(* C_S_AXI_ADDR_WIDTH = "7" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TYPE_OF_AXI4_INTERFACE = "1" *)
(* C_UC_FAMILY = "0" *)
(* C_USE_STARTUP = "0" *)
(* C_USE_STARTUP_EXT = "0" *)
(* C_XIP_MODE = "0" *)
(* C_XIP_PERF_MODE = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi U0
(.cfgclk(NLW_U0_cfgclk_UNCONNECTED),
.cfgmclk(NLW_U0_cfgmclk_UNCONNECTED),
.clk(1'b0),
.eos(NLW_U0_eos_UNCONNECTED),
.ext_spi_clk(ext_spi_clk),
.gsr(1'b0),
.gts(1'b0),
.io0_1_i(1'b0),
.io0_1_o(NLW_U0_io0_1_o_UNCONNECTED),
.io0_1_t(NLW_U0_io0_1_t_UNCONNECTED),
.io0_i(io0_i),
.io0_o(io0_o),
.io0_t(io0_t),
.io1_1_i(1'b0),
.io1_1_o(NLW_U0_io1_1_o_UNCONNECTED),
.io1_1_t(NLW_U0_io1_1_t_UNCONNECTED),
.io1_i(io1_i),
.io1_o(io1_o),
.io1_t(io1_t),
.io2_1_i(1'b0),
.io2_1_o(NLW_U0_io2_1_o_UNCONNECTED),
.io2_1_t(NLW_U0_io2_1_t_UNCONNECTED),
.io2_i(1'b0),
.io2_o(NLW_U0_io2_o_UNCONNECTED),
.io2_t(NLW_U0_io2_t_UNCONNECTED),
.io3_1_i(1'b0),
.io3_1_o(NLW_U0_io3_1_o_UNCONNECTED),
.io3_1_t(NLW_U0_io3_1_t_UNCONNECTED),
.io3_i(1'b0),
.io3_o(NLW_U0_io3_o_UNCONNECTED),
.io3_t(NLW_U0_io3_t_UNCONNECTED),
.ip2intc_irpt(ip2intc_irpt),
.keyclearb(1'b0),
.pack(1'b0),
.preq(NLW_U0_preq_UNCONNECTED),
.s_axi4_aclk(s_axi4_aclk),
.s_axi4_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axi4_araddr[6:2],1'b0,1'b0}),
.s_axi4_arburst({1'b0,1'b0}),
.s_axi4_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi4_aresetn(s_axi4_aresetn),
.s_axi4_arid(1'b0),
.s_axi4_arlen(s_axi4_arlen),
.s_axi4_arlock(1'b0),
.s_axi4_arprot({1'b0,1'b0,1'b0}),
.s_axi4_arready(s_axi4_arready),
.s_axi4_arsize({1'b0,1'b0,1'b0}),
.s_axi4_arvalid(s_axi4_arvalid),
.s_axi4_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axi4_awaddr[6:2],1'b0,1'b0}),
.s_axi4_awburst({1'b0,1'b0}),
.s_axi4_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi4_awid(1'b0),
.s_axi4_awlen(s_axi4_awlen),
.s_axi4_awlock(1'b0),
.s_axi4_awprot({1'b0,1'b0,1'b0}),
.s_axi4_awready(s_axi4_awready),
.s_axi4_awsize({1'b0,1'b0,1'b0}),
.s_axi4_awvalid(s_axi4_awvalid),
.s_axi4_bid(NLW_U0_s_axi4_bid_UNCONNECTED[0]),
.s_axi4_bready(s_axi4_bready),
.s_axi4_bresp({\^s_axi4_bresp ,NLW_U0_s_axi4_bresp_UNCONNECTED[0]}),
.s_axi4_bvalid(s_axi4_bvalid),
.s_axi4_rdata(\^s_axi4_rdata ),
.s_axi4_rid(NLW_U0_s_axi4_rid_UNCONNECTED[0]),
.s_axi4_rlast(s_axi4_rlast),
.s_axi4_rready(s_axi4_rready),
.s_axi4_rresp({\^s_axi4_rresp ,NLW_U0_s_axi4_rresp_UNCONNECTED[0]}),
.s_axi4_rvalid(s_axi4_rvalid),
.s_axi4_wdata({s_axi4_wdata[31],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axi4_wdata[9:0]}),
.s_axi4_wlast(1'b0),
.s_axi4_wready(s_axi4_wready),
.s_axi4_wstrb({s_axi4_wstrb[3],1'b0,1'b0,s_axi4_wstrb[0]}),
.s_axi4_wvalid(s_axi4_wvalid),
.s_axi_aclk(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_aresetn(1'b0),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awvalid(1'b0),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wvalid(1'b0),
.sck_i(1'b0),
.sck_o(sck_o),
.sck_t(sck_t),
.spisel(1'b1),
.ss_1_i(1'b0),
.ss_1_o(NLW_U0_ss_1_o_UNCONNECTED),
.ss_1_t(NLW_U0_ss_1_t_UNCONNECTED),
.ss_i(1'b0),
.ss_o(ss_o),
.ss_t(ss_t),
.usrcclkts(1'b0),
.usrdoneo(1'b1),
.usrdonets(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *)
(* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *)
(* xpm_cdc = "GRAY" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray
(src_clk,
src_in_bin,
dest_clk,
dest_out_bin);
input src_clk;
input [7:0]src_in_bin;
input dest_clk;
output [7:0]dest_out_bin;
wire [7:0]async_path;
wire dest_clk;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ;
wire [6:0]\^dest_out_bin ;
wire [6:0]gray_enc;
wire src_clk;
wire [7:0]src_in_bin;
assign dest_out_bin[7] = \dest_graysync_ff[1] [7];
assign dest_out_bin[6:0] = \^dest_out_bin [6:0];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][0]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[0]),
.Q(\dest_graysync_ff[0] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][1]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[1]),
.Q(\dest_graysync_ff[0] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][2]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[2]),
.Q(\dest_graysync_ff[0] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][3]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[3]),
.Q(\dest_graysync_ff[0] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][4]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[4]),
.Q(\dest_graysync_ff[0] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][5]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[5]),
.Q(\dest_graysync_ff[0] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][6]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[6]),
.Q(\dest_graysync_ff[0] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][7]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[7]),
.Q(\dest_graysync_ff[0] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [0]),
.Q(\dest_graysync_ff[1] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [1]),
.Q(\dest_graysync_ff[1] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [2]),
.Q(\dest_graysync_ff[1] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [3]),
.Q(\dest_graysync_ff[1] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [4]),
.Q(\dest_graysync_ff[1] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [5]),
.Q(\dest_graysync_ff[1] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [6]),
.Q(\dest_graysync_ff[1] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [7]),
.Q(\dest_graysync_ff[1] [7]),
.R(1'b0));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[0]_INST_0
(.I0(\dest_graysync_ff[1] [0]),
.I1(\^dest_out_bin [2]),
.I2(\dest_graysync_ff[1] [1]),
.O(\^dest_out_bin [0]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[1]_INST_0
(.I0(\dest_graysync_ff[1] [1]),
.I1(\^dest_out_bin [2]),
.O(\^dest_out_bin [1]));
LUT6 #(
.INIT(64'h6996966996696996))
\dest_out_bin[2]_INST_0
(.I0(\dest_graysync_ff[1] [2]),
.I1(\dest_graysync_ff[1] [4]),
.I2(\dest_graysync_ff[1] [6]),
.I3(\dest_graysync_ff[1] [7]),
.I4(\dest_graysync_ff[1] [5]),
.I5(\dest_graysync_ff[1] [3]),
.O(\^dest_out_bin [2]));
LUT5 #(
.INIT(32'h96696996))
\dest_out_bin[3]_INST_0
(.I0(\dest_graysync_ff[1] [3]),
.I1(\dest_graysync_ff[1] [5]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [6]),
.I4(\dest_graysync_ff[1] [4]),
.O(\^dest_out_bin [3]));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[4]_INST_0
(.I0(\dest_graysync_ff[1] [4]),
.I1(\dest_graysync_ff[1] [6]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [5]),
.O(\^dest_out_bin [4]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[5]_INST_0
(.I0(\dest_graysync_ff[1] [5]),
.I1(\dest_graysync_ff[1] [7]),
.I2(\dest_graysync_ff[1] [6]),
.O(\^dest_out_bin [5]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[6]_INST_0
(.I0(\dest_graysync_ff[1] [6]),
.I1(\dest_graysync_ff[1] [7]),
.O(\^dest_out_bin [6]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[0]_i_1
(.I0(src_in_bin[1]),
.I1(src_in_bin[0]),
.O(gray_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[1]_i_1
(.I0(src_in_bin[2]),
.I1(src_in_bin[1]),
.O(gray_enc[1]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[2]_i_1
(.I0(src_in_bin[3]),
.I1(src_in_bin[2]),
.O(gray_enc[2]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[3]_i_1
(.I0(src_in_bin[4]),
.I1(src_in_bin[3]),
.O(gray_enc[3]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[4]_i_1
(.I0(src_in_bin[5]),
.I1(src_in_bin[4]),
.O(gray_enc[4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[5]_i_1
(.I0(src_in_bin[6]),
.I1(src_in_bin[5]),
.O(gray_enc[5]));
LUT2 #(
.INIT(4'h6))
\src_gray_ff[6]_i_1
(.I0(src_in_bin[7]),
.I1(src_in_bin[6]),
.O(gray_enc[6]));
FDRE \src_gray_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[0]),
.Q(async_path[0]),
.R(1'b0));
FDRE \src_gray_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[1]),
.Q(async_path[1]),
.R(1'b0));
FDRE \src_gray_ff_reg[2]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[2]),
.Q(async_path[2]),
.R(1'b0));
FDRE \src_gray_ff_reg[3]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[3]),
.Q(async_path[3]),
.R(1'b0));
FDRE \src_gray_ff_reg[4]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[4]),
.Q(async_path[4]),
.R(1'b0));
FDRE \src_gray_ff_reg[5]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[5]),
.Q(async_path[5]),
.R(1'b0));
FDRE \src_gray_ff_reg[6]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[6]),
.Q(async_path[6]),
.R(1'b0));
FDRE \src_gray_ff_reg[7]
(.C(src_clk),
.CE(1'b1),
.D(src_in_bin[7]),
.Q(async_path[7]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *)
(* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *)
(* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1
(src_clk,
src_in_bin,
dest_clk,
dest_out_bin);
input src_clk;
input [7:0]src_in_bin;
input dest_clk;
output [7:0]dest_out_bin;
wire [7:0]async_path;
wire dest_clk;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ;
wire [6:0]\^dest_out_bin ;
wire [6:0]gray_enc;
wire src_clk;
wire [7:0]src_in_bin;
assign dest_out_bin[7] = \dest_graysync_ff[1] [7];
assign dest_out_bin[6:0] = \^dest_out_bin [6:0];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][0]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[0]),
.Q(\dest_graysync_ff[0] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][1]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[1]),
.Q(\dest_graysync_ff[0] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][2]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[2]),
.Q(\dest_graysync_ff[0] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][3]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[3]),
.Q(\dest_graysync_ff[0] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][4]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[4]),
.Q(\dest_graysync_ff[0] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][5]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[5]),
.Q(\dest_graysync_ff[0] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][6]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[6]),
.Q(\dest_graysync_ff[0] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][7]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[7]),
.Q(\dest_graysync_ff[0] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [0]),
.Q(\dest_graysync_ff[1] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [1]),
.Q(\dest_graysync_ff[1] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [2]),
.Q(\dest_graysync_ff[1] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [3]),
.Q(\dest_graysync_ff[1] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [4]),
.Q(\dest_graysync_ff[1] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [5]),
.Q(\dest_graysync_ff[1] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [6]),
.Q(\dest_graysync_ff[1] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [7]),
.Q(\dest_graysync_ff[1] [7]),
.R(1'b0));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[0]_INST_0
(.I0(\dest_graysync_ff[1] [0]),
.I1(\^dest_out_bin [2]),
.I2(\dest_graysync_ff[1] [1]),
.O(\^dest_out_bin [0]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[1]_INST_0
(.I0(\dest_graysync_ff[1] [1]),
.I1(\^dest_out_bin [2]),
.O(\^dest_out_bin [1]));
LUT6 #(
.INIT(64'h6996966996696996))
\dest_out_bin[2]_INST_0
(.I0(\dest_graysync_ff[1] [2]),
.I1(\dest_graysync_ff[1] [4]),
.I2(\dest_graysync_ff[1] [6]),
.I3(\dest_graysync_ff[1] [7]),
.I4(\dest_graysync_ff[1] [5]),
.I5(\dest_graysync_ff[1] [3]),
.O(\^dest_out_bin [2]));
LUT5 #(
.INIT(32'h96696996))
\dest_out_bin[3]_INST_0
(.I0(\dest_graysync_ff[1] [3]),
.I1(\dest_graysync_ff[1] [5]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [6]),
.I4(\dest_graysync_ff[1] [4]),
.O(\^dest_out_bin [3]));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[4]_INST_0
(.I0(\dest_graysync_ff[1] [4]),
.I1(\dest_graysync_ff[1] [6]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [5]),
.O(\^dest_out_bin [4]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[5]_INST_0
(.I0(\dest_graysync_ff[1] [5]),
.I1(\dest_graysync_ff[1] [7]),
.I2(\dest_graysync_ff[1] [6]),
.O(\^dest_out_bin [5]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[6]_INST_0
(.I0(\dest_graysync_ff[1] [6]),
.I1(\dest_graysync_ff[1] [7]),
.O(\^dest_out_bin [6]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[0]_i_1
(.I0(src_in_bin[1]),
.I1(src_in_bin[0]),
.O(gray_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[1]_i_1
(.I0(src_in_bin[2]),
.I1(src_in_bin[1]),
.O(gray_enc[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[2]_i_1
(.I0(src_in_bin[3]),
.I1(src_in_bin[2]),
.O(gray_enc[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[3]_i_1
(.I0(src_in_bin[4]),
.I1(src_in_bin[3]),
.O(gray_enc[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[4]_i_1
(.I0(src_in_bin[5]),
.I1(src_in_bin[4]),
.O(gray_enc[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[5]_i_1
(.I0(src_in_bin[6]),
.I1(src_in_bin[5]),
.O(gray_enc[5]));
LUT2 #(
.INIT(4'h6))
\src_gray_ff[6]_i_1
(.I0(src_in_bin[7]),
.I1(src_in_bin[6]),
.O(gray_enc[6]));
FDRE \src_gray_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[0]),
.Q(async_path[0]),
.R(1'b0));
FDRE \src_gray_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[1]),
.Q(async_path[1]),
.R(1'b0));
FDRE \src_gray_ff_reg[2]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[2]),
.Q(async_path[2]),
.R(1'b0));
FDRE \src_gray_ff_reg[3]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[3]),
.Q(async_path[3]),
.R(1'b0));
FDRE \src_gray_ff_reg[4]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[4]),
.Q(async_path[4]),
.R(1'b0));
FDRE \src_gray_ff_reg[5]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[5]),
.Q(async_path[5]),
.R(1'b0));
FDRE \src_gray_ff_reg[6]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[6]),
.Q(async_path[6]),
.R(1'b0));
FDRE \src_gray_ff_reg[7]
(.C(src_clk),
.CE(1'b1),
.D(src_in_bin[7]),
.Q(async_path[7]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *)
(* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *)
(* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2
(src_clk,
src_in_bin,
dest_clk,
dest_out_bin);
input src_clk;
input [7:0]src_in_bin;
input dest_clk;
output [7:0]dest_out_bin;
wire [7:0]async_path;
wire dest_clk;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ;
wire [6:0]\^dest_out_bin ;
wire [6:0]gray_enc;
wire src_clk;
wire [7:0]src_in_bin;
assign dest_out_bin[7] = \dest_graysync_ff[1] [7];
assign dest_out_bin[6:0] = \^dest_out_bin [6:0];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][0]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[0]),
.Q(\dest_graysync_ff[0] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][1]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[1]),
.Q(\dest_graysync_ff[0] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][2]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[2]),
.Q(\dest_graysync_ff[0] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][3]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[3]),
.Q(\dest_graysync_ff[0] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][4]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[4]),
.Q(\dest_graysync_ff[0] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][5]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[5]),
.Q(\dest_graysync_ff[0] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][6]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[6]),
.Q(\dest_graysync_ff[0] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][7]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[7]),
.Q(\dest_graysync_ff[0] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [0]),
.Q(\dest_graysync_ff[1] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [1]),
.Q(\dest_graysync_ff[1] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [2]),
.Q(\dest_graysync_ff[1] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [3]),
.Q(\dest_graysync_ff[1] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [4]),
.Q(\dest_graysync_ff[1] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [5]),
.Q(\dest_graysync_ff[1] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [6]),
.Q(\dest_graysync_ff[1] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [7]),
.Q(\dest_graysync_ff[1] [7]),
.R(1'b0));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[0]_INST_0
(.I0(\dest_graysync_ff[1] [0]),
.I1(\^dest_out_bin [2]),
.I2(\dest_graysync_ff[1] [1]),
.O(\^dest_out_bin [0]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[1]_INST_0
(.I0(\dest_graysync_ff[1] [1]),
.I1(\^dest_out_bin [2]),
.O(\^dest_out_bin [1]));
LUT6 #(
.INIT(64'h6996966996696996))
\dest_out_bin[2]_INST_0
(.I0(\dest_graysync_ff[1] [2]),
.I1(\dest_graysync_ff[1] [4]),
.I2(\dest_graysync_ff[1] [6]),
.I3(\dest_graysync_ff[1] [7]),
.I4(\dest_graysync_ff[1] [5]),
.I5(\dest_graysync_ff[1] [3]),
.O(\^dest_out_bin [2]));
LUT5 #(
.INIT(32'h96696996))
\dest_out_bin[3]_INST_0
(.I0(\dest_graysync_ff[1] [3]),
.I1(\dest_graysync_ff[1] [5]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [6]),
.I4(\dest_graysync_ff[1] [4]),
.O(\^dest_out_bin [3]));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[4]_INST_0
(.I0(\dest_graysync_ff[1] [4]),
.I1(\dest_graysync_ff[1] [6]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [5]),
.O(\^dest_out_bin [4]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[5]_INST_0
(.I0(\dest_graysync_ff[1] [5]),
.I1(\dest_graysync_ff[1] [7]),
.I2(\dest_graysync_ff[1] [6]),
.O(\^dest_out_bin [5]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[6]_INST_0
(.I0(\dest_graysync_ff[1] [6]),
.I1(\dest_graysync_ff[1] [7]),
.O(\^dest_out_bin [6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[0]_i_1
(.I0(src_in_bin[1]),
.I1(src_in_bin[0]),
.O(gray_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[1]_i_1
(.I0(src_in_bin[2]),
.I1(src_in_bin[1]),
.O(gray_enc[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[2]_i_1
(.I0(src_in_bin[3]),
.I1(src_in_bin[2]),
.O(gray_enc[2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[3]_i_1
(.I0(src_in_bin[4]),
.I1(src_in_bin[3]),
.O(gray_enc[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[4]_i_1
(.I0(src_in_bin[5]),
.I1(src_in_bin[4]),
.O(gray_enc[4]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[5]_i_1
(.I0(src_in_bin[6]),
.I1(src_in_bin[5]),
.O(gray_enc[5]));
LUT2 #(
.INIT(4'h6))
\src_gray_ff[6]_i_1
(.I0(src_in_bin[7]),
.I1(src_in_bin[6]),
.O(gray_enc[6]));
FDRE \src_gray_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[0]),
.Q(async_path[0]),
.R(1'b0));
FDRE \src_gray_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[1]),
.Q(async_path[1]),
.R(1'b0));
FDRE \src_gray_ff_reg[2]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[2]),
.Q(async_path[2]),
.R(1'b0));
FDRE \src_gray_ff_reg[3]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[3]),
.Q(async_path[3]),
.R(1'b0));
FDRE \src_gray_ff_reg[4]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[4]),
.Q(async_path[4]),
.R(1'b0));
FDRE \src_gray_ff_reg[5]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[5]),
.Q(async_path[5]),
.R(1'b0));
FDRE \src_gray_ff_reg[6]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[6]),
.Q(async_path[6]),
.R(1'b0));
FDRE \src_gray_ff_reg[7]
(.C(src_clk),
.CE(1'b1),
.D(src_in_bin[7]),
.Q(async_path[7]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *)
(* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *)
(* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3
(src_clk,
src_in_bin,
dest_clk,
dest_out_bin);
input src_clk;
input [7:0]src_in_bin;
input dest_clk;
output [7:0]dest_out_bin;
wire [7:0]async_path;
wire dest_clk;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ;
wire [6:0]\^dest_out_bin ;
wire [6:0]gray_enc;
wire src_clk;
wire [7:0]src_in_bin;
assign dest_out_bin[7] = \dest_graysync_ff[1] [7];
assign dest_out_bin[6:0] = \^dest_out_bin [6:0];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][0]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[0]),
.Q(\dest_graysync_ff[0] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][1]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[1]),
.Q(\dest_graysync_ff[0] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][2]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[2]),
.Q(\dest_graysync_ff[0] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][3]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[3]),
.Q(\dest_graysync_ff[0] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][4]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[4]),
.Q(\dest_graysync_ff[0] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][5]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[5]),
.Q(\dest_graysync_ff[0] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][6]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[6]),
.Q(\dest_graysync_ff[0] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][7]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[7]),
.Q(\dest_graysync_ff[0] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [0]),
.Q(\dest_graysync_ff[1] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [1]),
.Q(\dest_graysync_ff[1] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [2]),
.Q(\dest_graysync_ff[1] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [3]),
.Q(\dest_graysync_ff[1] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [4]),
.Q(\dest_graysync_ff[1] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [5]),
.Q(\dest_graysync_ff[1] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [6]),
.Q(\dest_graysync_ff[1] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [7]),
.Q(\dest_graysync_ff[1] [7]),
.R(1'b0));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[0]_INST_0
(.I0(\dest_graysync_ff[1] [0]),
.I1(\^dest_out_bin [2]),
.I2(\dest_graysync_ff[1] [1]),
.O(\^dest_out_bin [0]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[1]_INST_0
(.I0(\dest_graysync_ff[1] [1]),
.I1(\^dest_out_bin [2]),
.O(\^dest_out_bin [1]));
LUT6 #(
.INIT(64'h6996966996696996))
\dest_out_bin[2]_INST_0
(.I0(\dest_graysync_ff[1] [2]),
.I1(\dest_graysync_ff[1] [4]),
.I2(\dest_graysync_ff[1] [6]),
.I3(\dest_graysync_ff[1] [7]),
.I4(\dest_graysync_ff[1] [5]),
.I5(\dest_graysync_ff[1] [3]),
.O(\^dest_out_bin [2]));
LUT5 #(
.INIT(32'h96696996))
\dest_out_bin[3]_INST_0
(.I0(\dest_graysync_ff[1] [3]),
.I1(\dest_graysync_ff[1] [5]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [6]),
.I4(\dest_graysync_ff[1] [4]),
.O(\^dest_out_bin [3]));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[4]_INST_0
(.I0(\dest_graysync_ff[1] [4]),
.I1(\dest_graysync_ff[1] [6]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [5]),
.O(\^dest_out_bin [4]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[5]_INST_0
(.I0(\dest_graysync_ff[1] [5]),
.I1(\dest_graysync_ff[1] [7]),
.I2(\dest_graysync_ff[1] [6]),
.O(\^dest_out_bin [5]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[6]_INST_0
(.I0(\dest_graysync_ff[1] [6]),
.I1(\dest_graysync_ff[1] [7]),
.O(\^dest_out_bin [6]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[0]_i_1
(.I0(src_in_bin[1]),
.I1(src_in_bin[0]),
.O(gray_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[1]_i_1
(.I0(src_in_bin[2]),
.I1(src_in_bin[1]),
.O(gray_enc[1]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[2]_i_1
(.I0(src_in_bin[3]),
.I1(src_in_bin[2]),
.O(gray_enc[2]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[3]_i_1
(.I0(src_in_bin[4]),
.I1(src_in_bin[3]),
.O(gray_enc[3]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[4]_i_1
(.I0(src_in_bin[5]),
.I1(src_in_bin[4]),
.O(gray_enc[4]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[5]_i_1
(.I0(src_in_bin[6]),
.I1(src_in_bin[5]),
.O(gray_enc[5]));
LUT2 #(
.INIT(4'h6))
\src_gray_ff[6]_i_1
(.I0(src_in_bin[7]),
.I1(src_in_bin[6]),
.O(gray_enc[6]));
FDRE \src_gray_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[0]),
.Q(async_path[0]),
.R(1'b0));
FDRE \src_gray_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[1]),
.Q(async_path[1]),
.R(1'b0));
FDRE \src_gray_ff_reg[2]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[2]),
.Q(async_path[2]),
.R(1'b0));
FDRE \src_gray_ff_reg[3]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[3]),
.Q(async_path[3]),
.R(1'b0));
FDRE \src_gray_ff_reg[4]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[4]),
.Q(async_path[4]),
.R(1'b0));
FDRE \src_gray_ff_reg[5]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[5]),
.Q(async_path[5]),
.R(1'b0));
FDRE \src_gray_ff_reg[6]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[6]),
.Q(async_path[6]),
.R(1'b0));
FDRE \src_gray_ff_reg[7]
(.C(src_clk),
.CE(1'b1),
.D(src_in_bin[7]),
.Q(async_path[7]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *)
(* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *)
(* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0
(src_clk,
src_in_bin,
dest_clk,
dest_out_bin);
input src_clk;
input [8:0]src_in_bin;
input dest_clk;
output [8:0]dest_out_bin;
wire [8:0]async_path;
wire dest_clk;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[3] ;
wire [7:0]\^dest_out_bin ;
wire [7:0]gray_enc;
wire src_clk;
wire [8:0]src_in_bin;
assign dest_out_bin[8] = \dest_graysync_ff[3] [8];
assign dest_out_bin[7:0] = \^dest_out_bin [7:0];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][0]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[0]),
.Q(\dest_graysync_ff[0] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][1]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[1]),
.Q(\dest_graysync_ff[0] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][2]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[2]),
.Q(\dest_graysync_ff[0] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][3]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[3]),
.Q(\dest_graysync_ff[0] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][4]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[4]),
.Q(\dest_graysync_ff[0] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][5]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[5]),
.Q(\dest_graysync_ff[0] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][6]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[6]),
.Q(\dest_graysync_ff[0] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][7]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[7]),
.Q(\dest_graysync_ff[0] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][8]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[8]),
.Q(\dest_graysync_ff[0] [8]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [0]),
.Q(\dest_graysync_ff[1] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [1]),
.Q(\dest_graysync_ff[1] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [2]),
.Q(\dest_graysync_ff[1] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [3]),
.Q(\dest_graysync_ff[1] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [4]),
.Q(\dest_graysync_ff[1] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [5]),
.Q(\dest_graysync_ff[1] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [6]),
.Q(\dest_graysync_ff[1] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [7]),
.Q(\dest_graysync_ff[1] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][8]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [8]),
.Q(\dest_graysync_ff[1] [8]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [0]),
.Q(\dest_graysync_ff[2] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [1]),
.Q(\dest_graysync_ff[2] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [2]),
.Q(\dest_graysync_ff[2] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [3]),
.Q(\dest_graysync_ff[2] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [4]),
.Q(\dest_graysync_ff[2] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [5]),
.Q(\dest_graysync_ff[2] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [6]),
.Q(\dest_graysync_ff[2] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [7]),
.Q(\dest_graysync_ff[2] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][8]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [8]),
.Q(\dest_graysync_ff[2] [8]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [0]),
.Q(\dest_graysync_ff[3] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [1]),
.Q(\dest_graysync_ff[3] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [2]),
.Q(\dest_graysync_ff[3] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [3]),
.Q(\dest_graysync_ff[3] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [4]),
.Q(\dest_graysync_ff[3] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [5]),
.Q(\dest_graysync_ff[3] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [6]),
.Q(\dest_graysync_ff[3] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [7]),
.Q(\dest_graysync_ff[3] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][8]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [8]),
.Q(\dest_graysync_ff[3] [8]),
.R(1'b0));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[0]_INST_0
(.I0(\dest_graysync_ff[3] [0]),
.I1(\dest_graysync_ff[3] [2]),
.I2(\^dest_out_bin [3]),
.I3(\dest_graysync_ff[3] [1]),
.O(\^dest_out_bin [0]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[1]_INST_0
(.I0(\dest_graysync_ff[3] [1]),
.I1(\^dest_out_bin [3]),
.I2(\dest_graysync_ff[3] [2]),
.O(\^dest_out_bin [1]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[2]_INST_0
(.I0(\dest_graysync_ff[3] [2]),
.I1(\^dest_out_bin [3]),
.O(\^dest_out_bin [2]));
LUT6 #(
.INIT(64'h6996966996696996))
\dest_out_bin[3]_INST_0
(.I0(\dest_graysync_ff[3] [3]),
.I1(\dest_graysync_ff[3] [5]),
.I2(\dest_graysync_ff[3] [7]),
.I3(\dest_graysync_ff[3] [8]),
.I4(\dest_graysync_ff[3] [6]),
.I5(\dest_graysync_ff[3] [4]),
.O(\^dest_out_bin [3]));
LUT5 #(
.INIT(32'h96696996))
\dest_out_bin[4]_INST_0
(.I0(\dest_graysync_ff[3] [4]),
.I1(\dest_graysync_ff[3] [6]),
.I2(\dest_graysync_ff[3] [8]),
.I3(\dest_graysync_ff[3] [7]),
.I4(\dest_graysync_ff[3] [5]),
.O(\^dest_out_bin [4]));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[5]_INST_0
(.I0(\dest_graysync_ff[3] [5]),
.I1(\dest_graysync_ff[3] [7]),
.I2(\dest_graysync_ff[3] [8]),
.I3(\dest_graysync_ff[3] [6]),
.O(\^dest_out_bin [5]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[6]_INST_0
(.I0(\dest_graysync_ff[3] [6]),
.I1(\dest_graysync_ff[3] [8]),
.I2(\dest_graysync_ff[3] [7]),
.O(\^dest_out_bin [6]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[7]_INST_0
(.I0(\dest_graysync_ff[3] [7]),
.I1(\dest_graysync_ff[3] [8]),
.O(\^dest_out_bin [7]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[0]_i_1
(.I0(src_in_bin[1]),
.I1(src_in_bin[0]),
.O(gray_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[1]_i_1
(.I0(src_in_bin[2]),
.I1(src_in_bin[1]),
.O(gray_enc[1]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[2]_i_1
(.I0(src_in_bin[3]),
.I1(src_in_bin[2]),
.O(gray_enc[2]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[3]_i_1
(.I0(src_in_bin[4]),
.I1(src_in_bin[3]),
.O(gray_enc[3]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[4]_i_1
(.I0(src_in_bin[5]),
.I1(src_in_bin[4]),
.O(gray_enc[4]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[5]_i_1
(.I0(src_in_bin[6]),
.I1(src_in_bin[5]),
.O(gray_enc[5]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[6]_i_1
(.I0(src_in_bin[7]),
.I1(src_in_bin[6]),
.O(gray_enc[6]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[7]_i_1
(.I0(src_in_bin[8]),
.I1(src_in_bin[7]),
.O(gray_enc[7]));
FDRE \src_gray_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[0]),
.Q(async_path[0]),
.R(1'b0));
FDRE \src_gray_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[1]),
.Q(async_path[1]),
.R(1'b0));
FDRE \src_gray_ff_reg[2]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[2]),
.Q(async_path[2]),
.R(1'b0));
FDRE \src_gray_ff_reg[3]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[3]),
.Q(async_path[3]),
.R(1'b0));
FDRE \src_gray_ff_reg[4]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[4]),
.Q(async_path[4]),
.R(1'b0));
FDRE \src_gray_ff_reg[5]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[5]),
.Q(async_path[5]),
.R(1'b0));
FDRE \src_gray_ff_reg[6]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[6]),
.Q(async_path[6]),
.R(1'b0));
FDRE \src_gray_ff_reg[7]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[7]),
.Q(async_path[7]),
.R(1'b0));
FDRE \src_gray_ff_reg[8]
(.C(src_clk),
.CE(1'b1),
.D(src_in_bin[8]),
.Q(async_path[8]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "4" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *)
(* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *)
(* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1
(src_clk,
src_in_bin,
dest_clk,
dest_out_bin);
input src_clk;
input [8:0]src_in_bin;
input dest_clk;
output [8:0]dest_out_bin;
wire [8:0]async_path;
wire dest_clk;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[3] ;
wire [7:0]\^dest_out_bin ;
wire [7:0]gray_enc;
wire src_clk;
wire [8:0]src_in_bin;
assign dest_out_bin[8] = \dest_graysync_ff[3] [8];
assign dest_out_bin[7:0] = \^dest_out_bin [7:0];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][0]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[0]),
.Q(\dest_graysync_ff[0] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][1]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[1]),
.Q(\dest_graysync_ff[0] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][2]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[2]),
.Q(\dest_graysync_ff[0] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][3]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[3]),
.Q(\dest_graysync_ff[0] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][4]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[4]),
.Q(\dest_graysync_ff[0] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][5]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[5]),
.Q(\dest_graysync_ff[0] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][6]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[6]),
.Q(\dest_graysync_ff[0] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][7]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[7]),
.Q(\dest_graysync_ff[0] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][8]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[8]),
.Q(\dest_graysync_ff[0] [8]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [0]),
.Q(\dest_graysync_ff[1] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [1]),
.Q(\dest_graysync_ff[1] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [2]),
.Q(\dest_graysync_ff[1] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [3]),
.Q(\dest_graysync_ff[1] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [4]),
.Q(\dest_graysync_ff[1] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [5]),
.Q(\dest_graysync_ff[1] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [6]),
.Q(\dest_graysync_ff[1] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [7]),
.Q(\dest_graysync_ff[1] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][8]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [8]),
.Q(\dest_graysync_ff[1] [8]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [0]),
.Q(\dest_graysync_ff[2] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [1]),
.Q(\dest_graysync_ff[2] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [2]),
.Q(\dest_graysync_ff[2] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [3]),
.Q(\dest_graysync_ff[2] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [4]),
.Q(\dest_graysync_ff[2] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [5]),
.Q(\dest_graysync_ff[2] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [6]),
.Q(\dest_graysync_ff[2] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [7]),
.Q(\dest_graysync_ff[2] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[2][8]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[1] [8]),
.Q(\dest_graysync_ff[2] [8]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [0]),
.Q(\dest_graysync_ff[3] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [1]),
.Q(\dest_graysync_ff[3] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [2]),
.Q(\dest_graysync_ff[3] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [3]),
.Q(\dest_graysync_ff[3] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [4]),
.Q(\dest_graysync_ff[3] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [5]),
.Q(\dest_graysync_ff[3] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [6]),
.Q(\dest_graysync_ff[3] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [7]),
.Q(\dest_graysync_ff[3] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[3][8]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[2] [8]),
.Q(\dest_graysync_ff[3] [8]),
.R(1'b0));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[0]_INST_0
(.I0(\dest_graysync_ff[3] [0]),
.I1(\dest_graysync_ff[3] [2]),
.I2(\^dest_out_bin [3]),
.I3(\dest_graysync_ff[3] [1]),
.O(\^dest_out_bin [0]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[1]_INST_0
(.I0(\dest_graysync_ff[3] [1]),
.I1(\^dest_out_bin [3]),
.I2(\dest_graysync_ff[3] [2]),
.O(\^dest_out_bin [1]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[2]_INST_0
(.I0(\dest_graysync_ff[3] [2]),
.I1(\^dest_out_bin [3]),
.O(\^dest_out_bin [2]));
LUT6 #(
.INIT(64'h6996966996696996))
\dest_out_bin[3]_INST_0
(.I0(\dest_graysync_ff[3] [3]),
.I1(\dest_graysync_ff[3] [5]),
.I2(\dest_graysync_ff[3] [7]),
.I3(\dest_graysync_ff[3] [8]),
.I4(\dest_graysync_ff[3] [6]),
.I5(\dest_graysync_ff[3] [4]),
.O(\^dest_out_bin [3]));
LUT5 #(
.INIT(32'h96696996))
\dest_out_bin[4]_INST_0
(.I0(\dest_graysync_ff[3] [4]),
.I1(\dest_graysync_ff[3] [6]),
.I2(\dest_graysync_ff[3] [8]),
.I3(\dest_graysync_ff[3] [7]),
.I4(\dest_graysync_ff[3] [5]),
.O(\^dest_out_bin [4]));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[5]_INST_0
(.I0(\dest_graysync_ff[3] [5]),
.I1(\dest_graysync_ff[3] [7]),
.I2(\dest_graysync_ff[3] [8]),
.I3(\dest_graysync_ff[3] [6]),
.O(\^dest_out_bin [5]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[6]_INST_0
(.I0(\dest_graysync_ff[3] [6]),
.I1(\dest_graysync_ff[3] [8]),
.I2(\dest_graysync_ff[3] [7]),
.O(\^dest_out_bin [6]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[7]_INST_0
(.I0(\dest_graysync_ff[3] [7]),
.I1(\dest_graysync_ff[3] [8]),
.O(\^dest_out_bin [7]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[0]_i_1
(.I0(src_in_bin[1]),
.I1(src_in_bin[0]),
.O(gray_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[1]_i_1
(.I0(src_in_bin[2]),
.I1(src_in_bin[1]),
.O(gray_enc[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[2]_i_1
(.I0(src_in_bin[3]),
.I1(src_in_bin[2]),
.O(gray_enc[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[3]_i_1
(.I0(src_in_bin[4]),
.I1(src_in_bin[3]),
.O(gray_enc[3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[4]_i_1
(.I0(src_in_bin[5]),
.I1(src_in_bin[4]),
.O(gray_enc[4]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[5]_i_1
(.I0(src_in_bin[6]),
.I1(src_in_bin[5]),
.O(gray_enc[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[6]_i_1
(.I0(src_in_bin[7]),
.I1(src_in_bin[6]),
.O(gray_enc[6]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[7]_i_1
(.I0(src_in_bin[8]),
.I1(src_in_bin[7]),
.O(gray_enc[7]));
FDRE \src_gray_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[0]),
.Q(async_path[0]),
.R(1'b0));
FDRE \src_gray_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[1]),
.Q(async_path[1]),
.R(1'b0));
FDRE \src_gray_ff_reg[2]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[2]),
.Q(async_path[2]),
.R(1'b0));
FDRE \src_gray_ff_reg[3]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[3]),
.Q(async_path[3]),
.R(1'b0));
FDRE \src_gray_ff_reg[4]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[4]),
.Q(async_path[4]),
.R(1'b0));
FDRE \src_gray_ff_reg[5]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[5]),
.Q(async_path[5]),
.R(1'b0));
FDRE \src_gray_ff_reg[6]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[6]),
.Q(async_path[6]),
.R(1'b0));
FDRE \src_gray_ff_reg[7]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[7]),
.Q(async_path[7]),
.R(1'b0));
FDRE \src_gray_ff_reg[8]
(.C(src_clk),
.CE(1'b1),
.D(src_in_bin[8]),
.Q(async_path[8]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *)
(* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *)
(* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1
(src_clk,
src_in_bin,
dest_clk,
dest_out_bin);
input src_clk;
input [8:0]src_in_bin;
input dest_clk;
output [8:0]dest_out_bin;
wire [8:0]async_path;
wire dest_clk;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ;
wire [7:0]\^dest_out_bin ;
wire [7:0]gray_enc;
wire src_clk;
wire [8:0]src_in_bin;
assign dest_out_bin[8] = \dest_graysync_ff[1] [8];
assign dest_out_bin[7:0] = \^dest_out_bin [7:0];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][0]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[0]),
.Q(\dest_graysync_ff[0] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][1]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[1]),
.Q(\dest_graysync_ff[0] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][2]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[2]),
.Q(\dest_graysync_ff[0] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][3]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[3]),
.Q(\dest_graysync_ff[0] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][4]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[4]),
.Q(\dest_graysync_ff[0] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][5]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[5]),
.Q(\dest_graysync_ff[0] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][6]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[6]),
.Q(\dest_graysync_ff[0] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][7]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[7]),
.Q(\dest_graysync_ff[0] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][8]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[8]),
.Q(\dest_graysync_ff[0] [8]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [0]),
.Q(\dest_graysync_ff[1] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [1]),
.Q(\dest_graysync_ff[1] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [2]),
.Q(\dest_graysync_ff[1] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [3]),
.Q(\dest_graysync_ff[1] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [4]),
.Q(\dest_graysync_ff[1] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [5]),
.Q(\dest_graysync_ff[1] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [6]),
.Q(\dest_graysync_ff[1] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [7]),
.Q(\dest_graysync_ff[1] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][8]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [8]),
.Q(\dest_graysync_ff[1] [8]),
.R(1'b0));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[0]_INST_0
(.I0(\dest_graysync_ff[1] [0]),
.I1(\dest_graysync_ff[1] [2]),
.I2(\^dest_out_bin [3]),
.I3(\dest_graysync_ff[1] [1]),
.O(\^dest_out_bin [0]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[1]_INST_0
(.I0(\dest_graysync_ff[1] [1]),
.I1(\^dest_out_bin [3]),
.I2(\dest_graysync_ff[1] [2]),
.O(\^dest_out_bin [1]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[2]_INST_0
(.I0(\dest_graysync_ff[1] [2]),
.I1(\^dest_out_bin [3]),
.O(\^dest_out_bin [2]));
LUT6 #(
.INIT(64'h6996966996696996))
\dest_out_bin[3]_INST_0
(.I0(\dest_graysync_ff[1] [3]),
.I1(\dest_graysync_ff[1] [5]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [8]),
.I4(\dest_graysync_ff[1] [6]),
.I5(\dest_graysync_ff[1] [4]),
.O(\^dest_out_bin [3]));
LUT5 #(
.INIT(32'h96696996))
\dest_out_bin[4]_INST_0
(.I0(\dest_graysync_ff[1] [4]),
.I1(\dest_graysync_ff[1] [6]),
.I2(\dest_graysync_ff[1] [8]),
.I3(\dest_graysync_ff[1] [7]),
.I4(\dest_graysync_ff[1] [5]),
.O(\^dest_out_bin [4]));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[5]_INST_0
(.I0(\dest_graysync_ff[1] [5]),
.I1(\dest_graysync_ff[1] [7]),
.I2(\dest_graysync_ff[1] [8]),
.I3(\dest_graysync_ff[1] [6]),
.O(\^dest_out_bin [5]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[6]_INST_0
(.I0(\dest_graysync_ff[1] [6]),
.I1(\dest_graysync_ff[1] [8]),
.I2(\dest_graysync_ff[1] [7]),
.O(\^dest_out_bin [6]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[7]_INST_0
(.I0(\dest_graysync_ff[1] [7]),
.I1(\dest_graysync_ff[1] [8]),
.O(\^dest_out_bin [7]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[0]_i_1
(.I0(src_in_bin[1]),
.I1(src_in_bin[0]),
.O(gray_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[1]_i_1
(.I0(src_in_bin[2]),
.I1(src_in_bin[1]),
.O(gray_enc[1]));
LUT2 #(
.INIT(4'h6))
\src_gray_ff[2]_i_1
(.I0(src_in_bin[3]),
.I1(src_in_bin[2]),
.O(gray_enc[2]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[3]_i_1
(.I0(src_in_bin[4]),
.I1(src_in_bin[3]),
.O(gray_enc[3]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[4]_i_1
(.I0(src_in_bin[5]),
.I1(src_in_bin[4]),
.O(gray_enc[4]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[5]_i_1
(.I0(src_in_bin[6]),
.I1(src_in_bin[5]),
.O(gray_enc[5]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[6]_i_1
(.I0(src_in_bin[7]),
.I1(src_in_bin[6]),
.O(gray_enc[6]));
LUT2 #(
.INIT(4'h6))
\src_gray_ff[7]_i_1
(.I0(src_in_bin[8]),
.I1(src_in_bin[7]),
.O(gray_enc[7]));
FDRE \src_gray_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[0]),
.Q(async_path[0]),
.R(1'b0));
FDRE \src_gray_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[1]),
.Q(async_path[1]),
.R(1'b0));
FDRE \src_gray_ff_reg[2]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[2]),
.Q(async_path[2]),
.R(1'b0));
FDRE \src_gray_ff_reg[3]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[3]),
.Q(async_path[3]),
.R(1'b0));
FDRE \src_gray_ff_reg[4]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[4]),
.Q(async_path[4]),
.R(1'b0));
FDRE \src_gray_ff_reg[5]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[5]),
.Q(async_path[5]),
.R(1'b0));
FDRE \src_gray_ff_reg[6]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[6]),
.Q(async_path[6]),
.R(1'b0));
FDRE \src_gray_ff_reg[7]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[7]),
.Q(async_path[7]),
.R(1'b0));
FDRE \src_gray_ff_reg[8]
(.C(src_clk),
.CE(1'b1),
.D(src_in_bin[8]),
.Q(async_path[8]),
.R(1'b0));
endmodule
(* DEST_SYNC_FF = "2" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *)
(* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *)
(* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1
(src_clk,
src_in_bin,
dest_clk,
dest_out_bin);
input src_clk;
input [8:0]src_in_bin;
input dest_clk;
output [8:0]dest_out_bin;
wire [8:0]async_path;
wire dest_clk;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ;
wire [7:0]\^dest_out_bin ;
wire [7:0]gray_enc;
wire src_clk;
wire [8:0]src_in_bin;
assign dest_out_bin[8] = \dest_graysync_ff[1] [8];
assign dest_out_bin[7:0] = \^dest_out_bin [7:0];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][0]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[0]),
.Q(\dest_graysync_ff[0] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][1]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[1]),
.Q(\dest_graysync_ff[0] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][2]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[2]),
.Q(\dest_graysync_ff[0] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][3]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[3]),
.Q(\dest_graysync_ff[0] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][4]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[4]),
.Q(\dest_graysync_ff[0] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][5]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[5]),
.Q(\dest_graysync_ff[0] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][6]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[6]),
.Q(\dest_graysync_ff[0] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][7]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[7]),
.Q(\dest_graysync_ff[0] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[0][8]
(.C(dest_clk),
.CE(1'b1),
.D(async_path[8]),
.Q(\dest_graysync_ff[0] [8]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][0]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [0]),
.Q(\dest_graysync_ff[1] [0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][1]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [1]),
.Q(\dest_graysync_ff[1] [1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][2]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [2]),
.Q(\dest_graysync_ff[1] [2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][3]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [3]),
.Q(\dest_graysync_ff[1] [3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][4]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [4]),
.Q(\dest_graysync_ff[1] [4]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][5]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [5]),
.Q(\dest_graysync_ff[1] [5]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][6]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [6]),
.Q(\dest_graysync_ff[1] [6]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][7]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [7]),
.Q(\dest_graysync_ff[1] [7]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "GRAY" *)
FDRE \dest_graysync_ff_reg[1][8]
(.C(dest_clk),
.CE(1'b1),
.D(\dest_graysync_ff[0] [8]),
.Q(\dest_graysync_ff[1] [8]),
.R(1'b0));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[0]_INST_0
(.I0(\dest_graysync_ff[1] [0]),
.I1(\dest_graysync_ff[1] [2]),
.I2(\^dest_out_bin [3]),
.I3(\dest_graysync_ff[1] [1]),
.O(\^dest_out_bin [0]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[1]_INST_0
(.I0(\dest_graysync_ff[1] [1]),
.I1(\^dest_out_bin [3]),
.I2(\dest_graysync_ff[1] [2]),
.O(\^dest_out_bin [1]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[2]_INST_0
(.I0(\dest_graysync_ff[1] [2]),
.I1(\^dest_out_bin [3]),
.O(\^dest_out_bin [2]));
LUT6 #(
.INIT(64'h6996966996696996))
\dest_out_bin[3]_INST_0
(.I0(\dest_graysync_ff[1] [3]),
.I1(\dest_graysync_ff[1] [5]),
.I2(\dest_graysync_ff[1] [7]),
.I3(\dest_graysync_ff[1] [8]),
.I4(\dest_graysync_ff[1] [6]),
.I5(\dest_graysync_ff[1] [4]),
.O(\^dest_out_bin [3]));
LUT5 #(
.INIT(32'h96696996))
\dest_out_bin[4]_INST_0
(.I0(\dest_graysync_ff[1] [4]),
.I1(\dest_graysync_ff[1] [6]),
.I2(\dest_graysync_ff[1] [8]),
.I3(\dest_graysync_ff[1] [7]),
.I4(\dest_graysync_ff[1] [5]),
.O(\^dest_out_bin [4]));
LUT4 #(
.INIT(16'h6996))
\dest_out_bin[5]_INST_0
(.I0(\dest_graysync_ff[1] [5]),
.I1(\dest_graysync_ff[1] [7]),
.I2(\dest_graysync_ff[1] [8]),
.I3(\dest_graysync_ff[1] [6]),
.O(\^dest_out_bin [5]));
LUT3 #(
.INIT(8'h96))
\dest_out_bin[6]_INST_0
(.I0(\dest_graysync_ff[1] [6]),
.I1(\dest_graysync_ff[1] [8]),
.I2(\dest_graysync_ff[1] [7]),
.O(\^dest_out_bin [6]));
LUT2 #(
.INIT(4'h6))
\dest_out_bin[7]_INST_0
(.I0(\dest_graysync_ff[1] [7]),
.I1(\dest_graysync_ff[1] [8]),
.O(\^dest_out_bin [7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[0]_i_1
(.I0(src_in_bin[1]),
.I1(src_in_bin[0]),
.O(gray_enc[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[1]_i_1
(.I0(src_in_bin[2]),
.I1(src_in_bin[1]),
.O(gray_enc[1]));
LUT2 #(
.INIT(4'h6))
\src_gray_ff[2]_i_1
(.I0(src_in_bin[3]),
.I1(src_in_bin[2]),
.O(gray_enc[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[3]_i_1
(.I0(src_in_bin[4]),
.I1(src_in_bin[3]),
.O(gray_enc[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[4]_i_1
(.I0(src_in_bin[5]),
.I1(src_in_bin[4]),
.O(gray_enc[4]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[5]_i_1
(.I0(src_in_bin[6]),
.I1(src_in_bin[5]),
.O(gray_enc[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\src_gray_ff[6]_i_1
(.I0(src_in_bin[7]),
.I1(src_in_bin[6]),
.O(gray_enc[6]));
LUT2 #(
.INIT(4'h6))
\src_gray_ff[7]_i_1
(.I0(src_in_bin[8]),
.I1(src_in_bin[7]),
.O(gray_enc[7]));
FDRE \src_gray_ff_reg[0]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[0]),
.Q(async_path[0]),
.R(1'b0));
FDRE \src_gray_ff_reg[1]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[1]),
.Q(async_path[1]),
.R(1'b0));
FDRE \src_gray_ff_reg[2]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[2]),
.Q(async_path[2]),
.R(1'b0));
FDRE \src_gray_ff_reg[3]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[3]),
.Q(async_path[3]),
.R(1'b0));
FDRE \src_gray_ff_reg[4]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[4]),
.Q(async_path[4]),
.R(1'b0));
FDRE \src_gray_ff_reg[5]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[5]),
.Q(async_path[5]),
.R(1'b0));
FDRE \src_gray_ff_reg[6]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[6]),
.Q(async_path[6]),
.R(1'b0));
FDRE \src_gray_ff_reg[7]
(.C(src_clk),
.CE(1'b1),
.D(gray_enc[7]),
.Q(async_path[7]),
.R(1'b0));
FDRE \src_gray_ff_reg[8]
(.C(src_clk),
.CE(1'b1),
.D(src_in_bin[8]),
.Q(async_path[8]),
.R(1'b0));
endmodule
(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT = "0" *)
(* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *)
(* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst
(src_rst,
dest_clk,
dest_rst);
input src_rst;
input dest_clk;
output dest_rst;
wire dest_clk;
wire src_rst;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [1:0]syncstages_ff;
assign dest_rst = syncstages_ff[1];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "SYNC_RST" *)
FDRE #(
.INIT(1'b0))
\syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_rst),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "SYNC_RST" *)
FDRE #(
.INIT(1'b0))
\syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT = "0" *)
(* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *)
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *)
(* xpm_cdc = "SYNC_RST" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4
(src_rst,
dest_clk,
dest_rst);
input src_rst;
input dest_clk;
output dest_rst;
wire dest_clk;
wire src_rst;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [1:0]syncstages_ff;
assign dest_rst = syncstages_ff[1];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "SYNC_RST" *)
FDRE #(
.INIT(1'b0))
\syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_rst),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "SYNC_RST" *)
FDRE #(
.INIT(1'b0))
\syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT = "0" *)
(* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *)
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *)
(* xpm_cdc = "SYNC_RST" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5
(src_rst,
dest_clk,
dest_rst);
input src_rst;
input dest_clk;
output dest_rst;
wire dest_clk;
wire src_rst;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [1:0]syncstages_ff;
assign dest_rst = syncstages_ff[1];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "SYNC_RST" *)
FDRE #(
.INIT(1'b0))
\syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_rst),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "SYNC_RST" *)
FDRE #(
.INIT(1'b0))
\syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
(* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "2" *) (* INIT = "0" *)
(* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *)
(* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *)
(* xpm_cdc = "SYNC_RST" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6
(src_rst,
dest_clk,
dest_rst);
input src_rst;
input dest_clk;
output dest_rst;
wire dest_clk;
wire src_rst;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [1:0]syncstages_ff;
assign dest_rst = syncstages_ff[1];
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "SYNC_RST" *)
FDRE #(
.INIT(1'b0))
\syncstages_ff_reg[0]
(.C(dest_clk),
.CE(1'b1),
.D(src_rst),
.Q(syncstages_ff[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "true" *)
(* XPM_CDC = "SYNC_RST" *)
FDRE #(
.INIT(1'b0))
\syncstages_ff_reg[1]
(.C(dest_clk),
.CE(1'b1),
.D(syncstages_ff[0]),
.Q(syncstages_ff[1]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn
(Q,
wr_pntr_plus1_pf_carry,
wr_en,
\count_value_i_reg[6]_0 ,
wrst_busy,
rst_d1,
wr_clk);
output [7:0]Q;
input wr_pntr_plus1_pf_carry;
input wr_en;
input \count_value_i_reg[6]_0 ;
input wrst_busy;
input rst_d1;
input wr_clk;
wire [7:0]Q;
wire \count_value_i[0]_i_1__2_n_0 ;
wire \count_value_i[1]_i_1__2_n_0 ;
wire \count_value_i[2]_i_1__2_n_0 ;
wire \count_value_i[3]_i_1__2_n_0 ;
wire \count_value_i[4]_i_1__2_n_0 ;
wire \count_value_i[5]_i_1__2_n_0 ;
wire \count_value_i[6]_i_1__2_n_0 ;
wire \count_value_i[6]_i_2__2_n_0 ;
wire \count_value_i[7]_i_1__2_n_0 ;
wire \count_value_i[7]_i_2__1_n_0 ;
wire \count_value_i_reg[6]_0 ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT1 #(
.INIT(2'h1))
\count_value_i[0]_i_1__2
(.I0(Q[0]),
.O(\count_value_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'h6))
\count_value_i[1]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.O(\count_value_i[1]_i_1__2_n_0 ));
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1__2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1__2
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1__2
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2__2_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1__2
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2__2_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000800000000))
\count_value_i[6]_i_2__2
(.I0(Q[1]),
.I1(wr_en),
.I2(\count_value_i_reg[6]_0 ),
.I3(wrst_busy),
.I4(rst_d1),
.I5(Q[0]),
.O(\count_value_i[6]_i_2__2_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1__2
(.I0(Q[5]),
.I1(\count_value_i[7]_i_2__1_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[7]_i_2__1
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(wr_pntr_plus1_pf_carry),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[7]_i_2__1_n_0 ));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[0]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[0]_i_1__2_n_0 ),
.Q(Q[0]),
.S(wrst_busy));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[1]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[1]_i_1__2_n_0 ),
.Q(Q[1]),
.S(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[2]_i_1__2_n_0 ),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[3]_i_1__2_n_0 ),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[4]_i_1__2_n_0 ),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[5]_i_1__2_n_0 ),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[6]_i_1__2_n_0 ),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[7]_i_1__2_n_0 ),
.Q(Q[7]),
.R(wrst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_5
(Q,
wr_pntr_plus1_pf_carry,
wr_en,
\count_value_i_reg[6]_0 ,
wrst_busy,
rst_d1,
wr_clk);
output [7:0]Q;
input wr_pntr_plus1_pf_carry;
input wr_en;
input \count_value_i_reg[6]_0 ;
input wrst_busy;
input rst_d1;
input wr_clk;
wire [7:0]Q;
wire \count_value_i[0]_i_1__2_n_0 ;
wire \count_value_i[1]_i_1__2_n_0 ;
wire \count_value_i[2]_i_1__2_n_0 ;
wire \count_value_i[3]_i_1__2_n_0 ;
wire \count_value_i[4]_i_1__2_n_0 ;
wire \count_value_i[5]_i_1__2_n_0 ;
wire \count_value_i[6]_i_1__2_n_0 ;
wire \count_value_i[6]_i_2__2_n_0 ;
wire \count_value_i[7]_i_1__2_n_0 ;
wire \count_value_i[7]_i_2__1_n_0 ;
wire \count_value_i_reg[6]_0 ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT1 #(
.INIT(2'h1))
\count_value_i[0]_i_1__2
(.I0(Q[0]),
.O(\count_value_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\count_value_i[1]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.O(\count_value_i[1]_i_1__2_n_0 ));
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1__2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1__2
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1__2
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2__2_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1__2
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2__2_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000800000000))
\count_value_i[6]_i_2__2
(.I0(Q[1]),
.I1(wr_en),
.I2(\count_value_i_reg[6]_0 ),
.I3(wrst_busy),
.I4(rst_d1),
.I5(Q[0]),
.O(\count_value_i[6]_i_2__2_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1__2
(.I0(Q[5]),
.I1(\count_value_i[7]_i_2__1_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[7]_i_2__1
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(wr_pntr_plus1_pf_carry),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[7]_i_2__1_n_0 ));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[0]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[0]_i_1__2_n_0 ),
.Q(Q[0]),
.S(wrst_busy));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[1]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[1]_i_1__2_n_0 ),
.Q(Q[1]),
.S(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[2]_i_1__2_n_0 ),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[3]_i_1__2_n_0 ),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[4]_i_1__2_n_0 ),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[5]_i_1__2_n_0 ),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[6]_i_1__2_n_0 ),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[7]_i_1__2_n_0 ),
.Q(Q[7]),
.R(wrst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0
(Q,
wr_pntr_plus1_pf_carry,
wr_en,
\count_value_i_reg[6]_0 ,
wrst_busy,
rst_d1,
wr_clk);
output [7:0]Q;
input wr_pntr_plus1_pf_carry;
input wr_en;
input \count_value_i_reg[6]_0 ;
input wrst_busy;
input rst_d1;
input wr_clk;
wire [7:0]Q;
wire \count_value_i[0]_i_1_n_0 ;
wire \count_value_i[1]_i_1_n_0 ;
wire \count_value_i[2]_i_1_n_0 ;
wire \count_value_i[3]_i_1_n_0 ;
wire \count_value_i[4]_i_1_n_0 ;
wire \count_value_i[5]_i_1_n_0 ;
wire \count_value_i[6]_i_1_n_0 ;
wire \count_value_i[6]_i_2_n_0 ;
wire \count_value_i[7]_i_1_n_0 ;
wire \count_value_i[7]_i_2_n_0 ;
wire \count_value_i_reg[6]_0 ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT1 #(
.INIT(2'h1))
\count_value_i[0]_i_1
(.I0(Q[0]),
.O(\count_value_i[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\count_value_i[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\count_value_i[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000800000000))
\count_value_i[6]_i_2
(.I0(Q[1]),
.I1(wr_en),
.I2(\count_value_i_reg[6]_0 ),
.I3(wrst_busy),
.I4(rst_d1),
.I5(Q[0]),
.O(\count_value_i[6]_i_2_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1
(.I0(Q[5]),
.I1(\count_value_i[7]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[7]_i_2
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(wr_pntr_plus1_pf_carry),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[7]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[0]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[0]_i_1_n_0 ),
.Q(Q[0]),
.R(wrst_busy));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[1]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[1]_i_1_n_0 ),
.Q(Q[1]),
.S(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[2]_i_1_n_0 ),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[3]_i_1_n_0 ),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[4]_i_1_n_0 ),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[5]_i_1_n_0 ),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[6]_i_1_n_0 ),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[7]_i_1_n_0 ),
.Q(Q[7]),
.R(wrst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_16
(Q,
wr_pntr_plus1_pf_carry,
wr_en,
\count_value_i_reg[6]_0 ,
wrst_busy,
rst_d1,
wr_clk);
output [7:0]Q;
input wr_pntr_plus1_pf_carry;
input wr_en;
input \count_value_i_reg[6]_0 ;
input wrst_busy;
input rst_d1;
input wr_clk;
wire [7:0]Q;
wire \count_value_i[0]_i_1_n_0 ;
wire \count_value_i[1]_i_1_n_0 ;
wire \count_value_i[2]_i_1_n_0 ;
wire \count_value_i[3]_i_1_n_0 ;
wire \count_value_i[4]_i_1_n_0 ;
wire \count_value_i[5]_i_1_n_0 ;
wire \count_value_i[6]_i_1_n_0 ;
wire \count_value_i[6]_i_2_n_0 ;
wire \count_value_i[7]_i_1_n_0 ;
wire \count_value_i[7]_i_2_n_0 ;
wire \count_value_i_reg[6]_0 ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT1 #(
.INIT(2'h1))
\count_value_i[0]_i_1
(.I0(Q[0]),
.O(\count_value_i[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\count_value_i[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\count_value_i[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000800000000))
\count_value_i[6]_i_2
(.I0(Q[1]),
.I1(wr_en),
.I2(\count_value_i_reg[6]_0 ),
.I3(wrst_busy),
.I4(rst_d1),
.I5(Q[0]),
.O(\count_value_i[6]_i_2_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1
(.I0(Q[5]),
.I1(\count_value_i[7]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[7]_i_2
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(wr_pntr_plus1_pf_carry),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[7]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[0]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[0]_i_1_n_0 ),
.Q(Q[0]),
.R(wrst_busy));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[1]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[1]_i_1_n_0 ),
.Q(Q[1]),
.S(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[2]_i_1_n_0 ),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[3]_i_1_n_0 ),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[4]_i_1_n_0 ),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[5]_i_1_n_0 ),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[6]_i_1_n_0 ),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[7]_i_1_n_0 ),
.Q(Q[7]),
.R(wrst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1
(src_in_bin,
\count_value_i_reg[0]_0 ,
\count_value_i_reg[1]_0 ,
S,
DI,
Q,
\grdc.rd_data_count_i_reg[3] ,
\count_value_i_reg[1]_1 ,
rd_en,
ram_empty_i,
\count_value_i_reg[1]_2 ,
rd_clk);
output [0:0]src_in_bin;
output \count_value_i_reg[0]_0 ;
output \count_value_i_reg[1]_0 ;
output [1:0]S;
output [0:0]DI;
input [1:0]Q;
input [1:0]\grdc.rd_data_count_i_reg[3] ;
input [1:0]\count_value_i_reg[1]_1 ;
input rd_en;
input ram_empty_i;
input \count_value_i_reg[1]_2 ;
input rd_clk;
wire [0:0]DI;
wire [1:0]Q;
wire [1:0]S;
wire \count_value_i[0]_i_1_n_0 ;
wire \count_value_i[1]_i_1_n_0 ;
wire \count_value_i[1]_i_2_n_0 ;
wire \count_value_i_reg[0]_0 ;
wire \count_value_i_reg[1]_0 ;
wire [1:0]\count_value_i_reg[1]_1 ;
wire \count_value_i_reg[1]_2 ;
wire [1:0]\grdc.rd_data_count_i_reg[3] ;
wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire [0:0]src_in_bin;
LUT6 #(
.INIT(64'h000000005A88A655))
\count_value_i[0]_i_1
(.I0(\count_value_i_reg[0]_0 ),
.I1(\count_value_i_reg[1]_1 [0]),
.I2(rd_en),
.I3(\count_value_i_reg[1]_1 [1]),
.I4(ram_empty_i),
.I5(\count_value_i_reg[1]_2 ),
.O(\count_value_i[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000000AA88AAAA))
\count_value_i[1]_i_1
(.I0(\count_value_i[1]_i_2_n_0 ),
.I1(\count_value_i_reg[1]_1 [0]),
.I2(rd_en),
.I3(\count_value_i_reg[1]_1 [1]),
.I4(ram_empty_i),
.I5(\count_value_i_reg[1]_2 ),
.O(\count_value_i[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFFFF755500008AA))
\count_value_i[1]_i_2
(.I0(\count_value_i_reg[0]_0 ),
.I1(\count_value_i_reg[1]_1 [0]),
.I2(rd_en),
.I3(\count_value_i_reg[1]_1 [1]),
.I4(ram_empty_i),
.I5(\count_value_i_reg[1]_0 ),
.O(\count_value_i[1]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(\count_value_i[0]_i_1_n_0 ),
.Q(\count_value_i_reg[0]_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(\count_value_i[1]_i_1_n_0 ),
.Q(\count_value_i_reg[1]_0 ),
.R(1'b0));
LUT4 #(
.INIT(16'h2DD2))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8
(.I0(\count_value_i_reg[0]_0 ),
.I1(Q[0]),
.I2(\count_value_i_reg[1]_0 ),
.I3(Q[1]),
.O(src_in_bin));
(* HLUTNM = "lutpair1" *)
LUT2 #(
.INIT(4'hB))
\grdc.rd_data_count_i[3]_i_4
(.I0(\count_value_i_reg[0]_0 ),
.I1(Q[0]),
.O(DI));
LUT4 #(
.INIT(16'h9669))
\grdc.rd_data_count_i[3]_i_7
(.I0(DI),
.I1(\count_value_i_reg[1]_0 ),
.I2(Q[1]),
.I3(\grdc.rd_data_count_i_reg[3] [1]),
.O(S[1]));
(* HLUTNM = "lutpair1" *)
LUT3 #(
.INIT(8'h96))
\grdc.rd_data_count_i[3]_i_8
(.I0(\count_value_i_reg[0]_0 ),
.I1(Q[0]),
.I2(\grdc.rd_data_count_i_reg[3] [0]),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_10
(S,
DI,
\count_value_i_reg[1]_0 ,
\count_value_i_reg[0]_0 ,
Q,
\grdc.rd_data_count_i_reg[3] ,
ram_empty_i,
\count_value_i_reg[1]_1 ,
\count_value_i_reg[1]_2 ,
rd_en,
rd_clk);
output [1:0]S;
output [0:0]DI;
output \count_value_i_reg[1]_0 ;
output \count_value_i_reg[0]_0 ;
input [1:0]Q;
input [1:0]\grdc.rd_data_count_i_reg[3] ;
input ram_empty_i;
input \count_value_i_reg[1]_1 ;
input [1:0]\count_value_i_reg[1]_2 ;
input rd_en;
input rd_clk;
wire [0:0]DI;
wire [1:0]Q;
wire [1:0]S;
wire \count_value_i[0]_i_1_n_0 ;
wire \count_value_i[1]_i_1_n_0 ;
wire \count_value_i[1]_i_2_n_0 ;
wire \count_value_i_reg[0]_0 ;
wire \count_value_i_reg[1]_0 ;
wire \count_value_i_reg[1]_1 ;
wire [1:0]\count_value_i_reg[1]_2 ;
wire [1:0]\grdc.rd_data_count_i_reg[3] ;
wire ram_empty_i;
wire rd_clk;
wire rd_en;
LUT6 #(
.INIT(64'h006900A5006A0005))
\count_value_i[0]_i_1
(.I0(\count_value_i_reg[0]_0 ),
.I1(rd_en),
.I2(ram_empty_i),
.I3(\count_value_i_reg[1]_1 ),
.I4(\count_value_i_reg[1]_2 [1]),
.I5(\count_value_i_reg[1]_2 [0]),
.O(\count_value_i[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0A0A0A02))
\count_value_i[1]_i_1
(.I0(\count_value_i[1]_i_2_n_0 ),
.I1(ram_empty_i),
.I2(\count_value_i_reg[1]_1 ),
.I3(\count_value_i_reg[1]_2 [1]),
.I4(\count_value_i_reg[1]_2 [0]),
.O(\count_value_i[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hBBDFDDDD44202222))
\count_value_i[1]_i_2
(.I0(\count_value_i_reg[0]_0 ),
.I1(ram_empty_i),
.I2(\count_value_i_reg[1]_2 [0]),
.I3(rd_en),
.I4(\count_value_i_reg[1]_2 [1]),
.I5(\count_value_i_reg[1]_0 ),
.O(\count_value_i[1]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(\count_value_i[0]_i_1_n_0 ),
.Q(\count_value_i_reg[0]_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(\count_value_i[1]_i_1_n_0 ),
.Q(\count_value_i_reg[1]_0 ),
.R(1'b0));
(* HLUTNM = "lutpair0" *)
LUT2 #(
.INIT(4'hB))
\grdc.rd_data_count_i[3]_i_4
(.I0(\count_value_i_reg[0]_0 ),
.I1(Q[0]),
.O(DI));
LUT4 #(
.INIT(16'h9669))
\grdc.rd_data_count_i[3]_i_7
(.I0(DI),
.I1(Q[1]),
.I2(\count_value_i_reg[1]_0 ),
.I3(\grdc.rd_data_count_i_reg[3] [1]),
.O(S[1]));
(* HLUTNM = "lutpair0" *)
LUT3 #(
.INIT(8'h96))
\grdc.rd_data_count_i[3]_i_8
(.I0(\count_value_i_reg[0]_0 ),
.I1(Q[0]),
.I2(\grdc.rd_data_count_i_reg[3] [0]),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2
(Q,
enb,
DI,
\count_value_i_reg[7]_0 ,
D,
S,
\count_value_i_reg[6]_0 ,
src_in_bin,
\count_value_i_reg[0]_0 ,
rd_en,
ram_empty_i,
\grdc.rd_data_count_i_reg[3] ,
\grdc.rd_data_count_i_reg[8] ,
\src_gray_ff_reg[2] ,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ,
\count_value_i_reg[8]_0 ,
rd_clk);
output [7:0]Q;
output enb;
output [0:0]DI;
output [0:0]\count_value_i_reg[7]_0 ;
output [7:0]D;
output [0:0]S;
output [3:0]\count_value_i_reg[6]_0 ;
output [7:0]src_in_bin;
input [1:0]\count_value_i_reg[0]_0 ;
input rd_en;
input ram_empty_i;
input \grdc.rd_data_count_i_reg[3] ;
input [7:0]\grdc.rd_data_count_i_reg[8] ;
input \src_gray_ff_reg[2] ;
input [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ;
input \count_value_i_reg[8]_0 ;
input rd_clk;
wire [7:0]D;
wire [0:0]DI;
wire [7:0]Q;
wire [0:0]S;
wire \count_value_i[0]_i_1__4_n_0 ;
wire \count_value_i[1]_i_1__4_n_0 ;
wire \count_value_i[2]_i_1__4_n_0 ;
wire \count_value_i[3]_i_1__4_n_0 ;
wire \count_value_i[4]_i_1__4_n_0 ;
wire \count_value_i[5]_i_1__3_n_0 ;
wire \count_value_i[6]_i_1__3_n_0 ;
wire \count_value_i[6]_i_2__3_n_0 ;
wire \count_value_i[7]_i_1__3_n_0 ;
wire \count_value_i[8]_i_1__0_n_0 ;
wire \count_value_i[8]_i_2__0_n_0 ;
wire [1:0]\count_value_i_reg[0]_0 ;
wire [3:0]\count_value_i_reg[6]_0 ;
wire [0:0]\count_value_i_reg[7]_0 ;
wire \count_value_i_reg[8]_0 ;
wire \count_value_i_reg_n_0_[8] ;
wire enb;
wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ;
wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_1 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_2 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_3 ;
wire [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ;
wire \grdc.rd_data_count_i_reg[3] ;
wire [7:0]\grdc.rd_data_count_i_reg[8] ;
wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire \src_gray_ff_reg[2] ;
wire [7:0]src_in_bin;
wire [3:3]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED ;
LUT5 #(
.INIT(32'hABAA5455))
\count_value_i[0]_i_1__4
(.I0(ram_empty_i),
.I1(rd_en),
.I2(\count_value_i_reg[0]_0 [0]),
.I3(\count_value_i_reg[0]_0 [1]),
.I4(Q[0]),
.O(\count_value_i[0]_i_1__4_n_0 ));
LUT5 #(
.INIT(32'h02FFFD00))
\count_value_i[1]_i_1__4
(.I0(\count_value_i_reg[0]_0 [1]),
.I1(\count_value_i_reg[0]_0 [0]),
.I2(rd_en),
.I3(Q[0]),
.I4(Q[1]),
.O(\count_value_i[1]_i_1__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1__4
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1__4
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1__4
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1__4_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1__3
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2__3_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1__3
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2__3_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000AAA200000000))
\count_value_i[6]_i_2__3
(.I0(Q[1]),
.I1(\count_value_i_reg[0]_0 [1]),
.I2(\count_value_i_reg[0]_0 [0]),
.I3(rd_en),
.I4(ram_empty_i),
.I5(Q[0]),
.O(\count_value_i[6]_i_2__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1__3
(.I0(Q[5]),
.I1(\count_value_i[8]_i_2__0_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[8]_i_1__0
(.I0(Q[6]),
.I1(\count_value_i[8]_i_2__0_n_0 ),
.I2(Q[5]),
.I3(Q[7]),
.I4(\count_value_i_reg_n_0_[8] ),
.O(\count_value_i[8]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[8]_i_2__0
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(enb),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[8]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[0]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[0]_i_1__4_n_0 ),
.Q(Q[0]),
.R(\count_value_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[1]_i_1__4_n_0 ),
.Q(Q[1]),
.R(\count_value_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[2]_i_1__4_n_0 ),
.Q(Q[2]),
.R(\count_value_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[3]_i_1__4_n_0 ),
.Q(Q[3]),
.R(\count_value_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[4]_i_1__4_n_0 ),
.Q(Q[4]),
.R(\count_value_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[5]_i_1__3_n_0 ),
.Q(Q[5]),
.R(\count_value_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[6]_i_1__3_n_0 ),
.Q(Q[6]),
.R(\count_value_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[7]_i_1__3_n_0 ),
.Q(Q[7]),
.R(\count_value_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[8]
(.C(rd_clk),
.CE(enb),
.D(\count_value_i[8]_i_1__0_n_0 ),
.Q(\count_value_i_reg_n_0_[8] ),
.R(\count_value_i_reg[8]_0 ));
LUT6 #(
.INIT(64'hFFFFFFFE00000001))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.I3(Q[4]),
.I4(Q[6]),
.I5(\count_value_i_reg_n_0_[8] ),
.O(src_in_bin[7]));
LUT6 #(
.INIT(64'hFFFFFFFFFBFBBAFB))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10
(.I0(Q[2]),
.I1(\grdc.rd_data_count_i_reg[3] ),
.I2(Q[1]),
.I3(\src_gray_ff_reg[2] ),
.I4(Q[0]),
.I5(Q[3]),
.O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'hB))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11
(.I0(Q[0]),
.I1(\src_gray_ff_reg[2] ),
.O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT5 #(
.INIT(32'hFFFE0001))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.I3(Q[5]),
.I4(Q[7]),
.O(src_in_bin[6]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'hFE01))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3
(.I0(Q[5]),
.I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.I2(Q[4]),
.I3(Q[6]),
.O(src_in_bin[5]));
LUT3 #(
.INIT(8'hE1))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4
(.I0(Q[4]),
.I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.I2(Q[5]),
.O(src_in_bin[4]));
LUT6 #(
.INIT(64'hFFFFEAFE00001501))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5
(.I0(Q[3]),
.I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ),
.I2(Q[1]),
.I3(\grdc.rd_data_count_i_reg[3] ),
.I4(Q[2]),
.I5(Q[4]),
.O(src_in_bin[3]));
LUT6 #(
.INIT(64'hFBFBBAFB04044504))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6
(.I0(Q[2]),
.I1(\grdc.rd_data_count_i_reg[3] ),
.I2(Q[1]),
.I3(\src_gray_ff_reg[2] ),
.I4(Q[0]),
.I5(Q[3]),
.O(src_in_bin[2]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'hB0FB4F04))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7
(.I0(Q[0]),
.I1(\src_gray_ff_reg[2] ),
.I2(Q[1]),
.I3(\grdc.rd_data_count_i_reg[3] ),
.I4(Q[2]),
.O(src_in_bin[1]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h6))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9
(.I0(Q[0]),
.I1(\src_gray_ff_reg[2] ),
.O(src_in_bin[0]));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2
(.I0(Q[3]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3
(.I0(Q[2]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4
(.I0(Q[1]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5
(.I0(Q[0]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6
(.I0(Q[3]),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [3]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7
(.I0(Q[2]),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [2]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8
(.I0(Q[1]),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [1]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8_n_0 ));
LUT5 #(
.INIT(32'hABAA5455))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9
(.I0(ram_empty_i),
.I1(rd_en),
.I2(\count_value_i_reg[0]_0 [0]),
.I3(\count_value_i_reg[0]_0 [1]),
.I4(Q[0]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2
(.I0(Q[6]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3
(.I0(Q[5]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4
(.I0(Q[4]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5
(.I0(Q[7]),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [7]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6
(.I0(Q[6]),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [6]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7
(.I0(Q[5]),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [5]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8
(.I0(Q[4]),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [4]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 ));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1
(.CI(1'b0),
.CO({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_3 }),
.CYINIT(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [0]),
.DI({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0 }),
.O(D[3:0]),
.S({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0 }));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1
(.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0 ),
.CO({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED [3],\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 }),
.O(D[7:4]),
.S({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 }));
LUT4 #(
.INIT(16'h00FD))
\gen_sdpram.xpm_memory_base_inst_i_2
(.I0(\count_value_i_reg[0]_0 [1]),
.I1(\count_value_i_reg[0]_0 [0]),
.I2(rd_en),
.I3(ram_empty_i),
.O(enb));
LUT3 #(
.INIT(8'hD4))
\grdc.rd_data_count_i[3]_i_3
(.I0(Q[1]),
.I1(\grdc.rd_data_count_i_reg[3] ),
.I2(\grdc.rd_data_count_i_reg[8] [0]),
.O(DI));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[3]_i_5
(.I0(Q[2]),
.I1(\grdc.rd_data_count_i_reg[8] [1]),
.I2(Q[3]),
.I3(\grdc.rd_data_count_i_reg[8] [2]),
.O(S));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[7]_i_6
(.I0(Q[6]),
.I1(\grdc.rd_data_count_i_reg[8] [5]),
.I2(Q[7]),
.I3(\grdc.rd_data_count_i_reg[8] [6]),
.O(\count_value_i_reg[6]_0 [3]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[7]_i_7
(.I0(Q[5]),
.I1(\grdc.rd_data_count_i_reg[8] [4]),
.I2(Q[6]),
.I3(\grdc.rd_data_count_i_reg[8] [5]),
.O(\count_value_i_reg[6]_0 [2]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[7]_i_8
(.I0(Q[4]),
.I1(\grdc.rd_data_count_i_reg[8] [3]),
.I2(Q[5]),
.I3(\grdc.rd_data_count_i_reg[8] [4]),
.O(\count_value_i_reg[6]_0 [1]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[7]_i_9
(.I0(Q[3]),
.I1(\grdc.rd_data_count_i_reg[8] [2]),
.I2(Q[4]),
.I3(\grdc.rd_data_count_i_reg[8] [3]),
.O(\count_value_i_reg[6]_0 [0]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[8]_i_3
(.I0(Q[7]),
.I1(\grdc.rd_data_count_i_reg[8] [6]),
.I2(\count_value_i_reg_n_0_[8] ),
.I3(\grdc.rd_data_count_i_reg[8] [7]),
.O(\count_value_i_reg[7]_0 ));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_11
(Q,
E,
src_in_bin,
\count_value_i_reg[7]_0 ,
D,
\count_value_i_reg[2]_0 ,
\count_value_i_reg[6]_0 ,
rd_en,
\count_value_i_reg[8]_0 ,
ram_empty_i,
\src_gray_ff_reg[0] ,
\grdc.rd_data_count_i_reg[3] ,
\grdc.rd_data_count_i_reg[8] ,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] ,
S,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ,
\count_value_i_reg[4]_0 ,
\count_value_i_reg[8]_1 ,
rd_clk);
output [7:0]Q;
output [0:0]E;
output [8:0]src_in_bin;
output [0:0]\count_value_i_reg[7]_0 ;
output [7:0]D;
output [1:0]\count_value_i_reg[2]_0 ;
output [3:0]\count_value_i_reg[6]_0 ;
input rd_en;
input [1:0]\count_value_i_reg[8]_0 ;
input ram_empty_i;
input \src_gray_ff_reg[0] ;
input \grdc.rd_data_count_i_reg[3] ;
input [7:0]\grdc.rd_data_count_i_reg[8] ;
input [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] ;
input [2:0]S;
input [3:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ;
input \count_value_i_reg[4]_0 ;
input \count_value_i_reg[8]_1 ;
input rd_clk;
wire [7:0]D;
wire [0:0]E;
wire [7:0]Q;
wire [2:0]S;
wire \count_value_i[0]_i_1__4_n_0 ;
wire \count_value_i[1]_i_1__4_n_0 ;
wire \count_value_i[2]_i_1__4_n_0 ;
wire \count_value_i[3]_i_1__4_n_0 ;
wire \count_value_i[4]_i_1__4_n_0 ;
wire \count_value_i[5]_i_1__4_n_0 ;
wire \count_value_i[6]_i_1__4_n_0 ;
wire \count_value_i[6]_i_2__4_n_0 ;
wire \count_value_i[7]_i_1__3_n_0 ;
wire \count_value_i[8]_i_1__0_n_0 ;
wire \count_value_i[8]_i_2__0_n_0 ;
wire [1:0]\count_value_i_reg[2]_0 ;
wire \count_value_i_reg[4]_0 ;
wire [3:0]\count_value_i_reg[6]_0 ;
wire [0:0]\count_value_i_reg[7]_0 ;
wire [1:0]\count_value_i_reg[8]_0 ;
wire \count_value_i_reg[8]_1 ;
wire \count_value_i_reg_n_0_[8] ;
wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ;
wire [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_1 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_2 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_3 ;
wire [3:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ;
wire \grdc.rd_data_count_i_reg[3] ;
wire [7:0]\grdc.rd_data_count_i_reg[8] ;
wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire \src_gray_ff_reg[0] ;
wire [8:0]src_in_bin;
wire [3:3]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h5565))
\count_value_i[0]_i_1__4
(.I0(Q[0]),
.I1(rd_en),
.I2(\count_value_i_reg[8]_0 [1]),
.I3(\count_value_i_reg[8]_0 [0]),
.O(\count_value_i[0]_i_1__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'h66666A66))
\count_value_i[1]_i_1__4
(.I0(Q[1]),
.I1(Q[0]),
.I2(\count_value_i_reg[8]_0 [0]),
.I3(\count_value_i_reg[8]_0 [1]),
.I4(rd_en),
.O(\count_value_i[1]_i_1__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hA6AA))
\count_value_i[2]_i_1__4
(.I0(Q[2]),
.I1(Q[1]),
.I2(\count_value_i_reg[4]_0 ),
.I3(Q[0]),
.O(\count_value_i[2]_i_1__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hAA6AAAAA))
\count_value_i[3]_i_1__4
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(\count_value_i_reg[4]_0 ),
.I4(Q[1]),
.O(\count_value_i[3]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\count_value_i[4]_i_1__4
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[1]),
.I3(\count_value_i_reg[4]_0 ),
.I4(Q[0]),
.I5(Q[2]),
.O(\count_value_i[4]_i_1__4_n_0 ));
LUT5 #(
.INIT(32'hAA6AAAAA))
\count_value_i[5]_i_1__4
(.I0(Q[5]),
.I1(Q[4]),
.I2(Q[2]),
.I3(\count_value_i[6]_i_2__4_n_0 ),
.I4(Q[3]),
.O(\count_value_i[5]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\count_value_i[6]_i_1__4
(.I0(Q[6]),
.I1(Q[5]),
.I2(Q[3]),
.I3(\count_value_i[6]_i_2__4_n_0 ),
.I4(Q[2]),
.I5(Q[4]),
.O(\count_value_i[6]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'hDDDDDFDDFFFFFFFF))
\count_value_i[6]_i_2__4
(.I0(Q[0]),
.I1(ram_empty_i),
.I2(\count_value_i_reg[8]_0 [0]),
.I3(\count_value_i_reg[8]_0 [1]),
.I4(rd_en),
.I5(Q[1]),
.O(\count_value_i[6]_i_2__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h9AAA))
\count_value_i[7]_i_1__3
(.I0(Q[7]),
.I1(\count_value_i[8]_i_2__0_n_0 ),
.I2(Q[5]),
.I3(Q[6]),
.O(\count_value_i[7]_i_1__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hAAAA6AAA))
\count_value_i[8]_i_1__0
(.I0(\count_value_i_reg_n_0_[8] ),
.I1(Q[7]),
.I2(Q[6]),
.I3(Q[5]),
.I4(\count_value_i[8]_i_2__0_n_0 ),
.O(\count_value_i[8]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF7FFFFFFFFFFFFFF))
\count_value_i[8]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(\count_value_i_reg[4]_0 ),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\count_value_i[8]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[0]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[0]_i_1__4_n_0 ),
.Q(Q[0]),
.R(\count_value_i_reg[8]_1 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[1]_i_1__4_n_0 ),
.Q(Q[1]),
.R(\count_value_i_reg[8]_1 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[2]_i_1__4_n_0 ),
.Q(Q[2]),
.R(\count_value_i_reg[8]_1 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[3]_i_1__4_n_0 ),
.Q(Q[3]),
.R(\count_value_i_reg[8]_1 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[4]_i_1__4_n_0 ),
.Q(Q[4]),
.R(\count_value_i_reg[8]_1 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[5]_i_1__4_n_0 ),
.Q(Q[5]),
.R(\count_value_i_reg[8]_1 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[6]_i_1__4_n_0 ),
.Q(Q[6]),
.R(\count_value_i_reg[8]_1 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[7]_i_1__3_n_0 ),
.Q(Q[7]),
.R(\count_value_i_reg[8]_1 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[8]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[8]_i_1__0_n_0 ),
.Q(\count_value_i_reg_n_0_[8] ),
.R(\count_value_i_reg[8]_1 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1
(.I0(\count_value_i_reg_n_0_[8] ),
.I1(Q[7]),
.I2(Q[6]),
.I3(Q[4]),
.I4(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.I5(Q[5]),
.O(src_in_bin[8]));
LUT6 #(
.INIT(64'hFFFFFFFFEFEFAEEF))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10
(.I0(Q[3]),
.I1(Q[1]),
.I2(\grdc.rd_data_count_i_reg[3] ),
.I3(\src_gray_ff_reg[0] ),
.I4(Q[0]),
.I5(Q[2]),
.O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2
(.I0(Q[7]),
.I1(Q[5]),
.I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.I3(Q[4]),
.I4(Q[6]),
.O(src_in_bin[7]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'hAAA9))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3
(.I0(Q[6]),
.I1(Q[4]),
.I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.I3(Q[5]),
.O(src_in_bin[6]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hA9))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4
(.I0(Q[5]),
.I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.I2(Q[4]),
.O(src_in_bin[5]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h9))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5
(.I0(Q[4]),
.I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ),
.O(src_in_bin[4]));
LUT6 #(
.INIT(64'hAAAAAAAA9A9A599A))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6
(.I0(Q[3]),
.I1(Q[1]),
.I2(\grdc.rd_data_count_i_reg[3] ),
.I3(\src_gray_ff_reg[0] ),
.I4(Q[0]),
.I5(Q[2]),
.O(src_in_bin[3]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h9AAA559A))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7
(.I0(Q[2]),
.I1(Q[0]),
.I2(\src_gray_ff_reg[0] ),
.I3(\grdc.rd_data_count_i_reg[3] ),
.I4(Q[1]),
.O(src_in_bin[2]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h4BB4))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8
(.I0(Q[0]),
.I1(\src_gray_ff_reg[0] ),
.I2(\grdc.rd_data_count_i_reg[3] ),
.I3(Q[1]),
.O(src_in_bin[1]));
LUT2 #(
.INIT(4'h6))
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9
(.I0(Q[0]),
.I1(\src_gray_ff_reg[0] ),
.O(src_in_bin[0]));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2
(.I0(Q[3]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3
(.I0(Q[2]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4
(.I0(Q[1]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5
(.I0(Q[0]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0 ));
LUT5 #(
.INIT(32'hFF0400FB))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9
(.I0(rd_en),
.I1(\count_value_i_reg[8]_0 [1]),
.I2(\count_value_i_reg[8]_0 [0]),
.I3(ram_empty_i),
.I4(Q[0]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2
(.I0(Q[6]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3
(.I0(Q[5]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4
(.I0(Q[4]),
.O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1
(.CI(1'b0),
.CO({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_3 }),
.CYINIT(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] ),
.DI({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0 }),
.O(D[3:0]),
.S({S,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0 }));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1
(.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0 ),
.CO({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED [3],\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 }),
.O(D[7:4]),
.S(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ));
LUT4 #(
.INIT(16'h00FB))
\gen_sdpram.xpm_memory_base_inst_i_2
(.I0(rd_en),
.I1(\count_value_i_reg[8]_0 [1]),
.I2(\count_value_i_reg[8]_0 [0]),
.I3(ram_empty_i),
.O(E));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[3]_i_5
(.I0(Q[2]),
.I1(\grdc.rd_data_count_i_reg[8] [1]),
.I2(\grdc.rd_data_count_i_reg[8] [2]),
.I3(Q[3]),
.O(\count_value_i_reg[2]_0 [1]));
LUT5 #(
.INIT(32'h2BD4D42B))
\grdc.rd_data_count_i[3]_i_6
(.I0(Q[1]),
.I1(\grdc.rd_data_count_i_reg[3] ),
.I2(\grdc.rd_data_count_i_reg[8] [0]),
.I3(\grdc.rd_data_count_i_reg[8] [1]),
.I4(Q[2]),
.O(\count_value_i_reg[2]_0 [0]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[7]_i_6
(.I0(Q[6]),
.I1(\grdc.rd_data_count_i_reg[8] [5]),
.I2(\grdc.rd_data_count_i_reg[8] [6]),
.I3(Q[7]),
.O(\count_value_i_reg[6]_0 [3]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[7]_i_7
(.I0(Q[5]),
.I1(\grdc.rd_data_count_i_reg[8] [4]),
.I2(\grdc.rd_data_count_i_reg[8] [5]),
.I3(Q[6]),
.O(\count_value_i_reg[6]_0 [2]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[7]_i_8
(.I0(Q[4]),
.I1(\grdc.rd_data_count_i_reg[8] [3]),
.I2(\grdc.rd_data_count_i_reg[8] [4]),
.I3(Q[5]),
.O(\count_value_i_reg[6]_0 [1]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[7]_i_9
(.I0(Q[3]),
.I1(\grdc.rd_data_count_i_reg[8] [2]),
.I2(\grdc.rd_data_count_i_reg[8] [3]),
.I3(Q[4]),
.O(\count_value_i_reg[6]_0 [0]));
LUT4 #(
.INIT(16'hB44B))
\grdc.rd_data_count_i[8]_i_3
(.I0(Q[7]),
.I1(\grdc.rd_data_count_i_reg[8] [6]),
.I2(\grdc.rd_data_count_i_reg[8] [7]),
.I3(\count_value_i_reg_n_0_[8] ),
.O(\count_value_i_reg[7]_0 ));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_14
(Q,
D,
wr_pntr_plus1_pf_carry,
wr_en,
\count_value_i_reg[6]_0 ,
wrst_busy,
rst_d1,
\gwdc.wr_data_count_i_reg[8] ,
wr_clk);
output [8:0]Q;
output [8:0]D;
input wr_pntr_plus1_pf_carry;
input wr_en;
input \count_value_i_reg[6]_0 ;
input wrst_busy;
input rst_d1;
input [8:0]\gwdc.wr_data_count_i_reg[8] ;
input wr_clk;
wire [8:0]D;
wire [8:0]Q;
wire \count_value_i[0]_i_1__1_n_0 ;
wire \count_value_i[1]_i_1__1_n_0 ;
wire \count_value_i[2]_i_1__1_n_0 ;
wire \count_value_i[3]_i_1__1_n_0 ;
wire \count_value_i[4]_i_1__1_n_0 ;
wire \count_value_i[5]_i_1__1_n_0 ;
wire \count_value_i[6]_i_1__1_n_0 ;
wire \count_value_i[6]_i_2__1_n_0 ;
wire \count_value_i[7]_i_1__1_n_0 ;
wire \count_value_i[8]_i_1_n_0 ;
wire \count_value_i[8]_i_2_n_0 ;
wire \count_value_i_reg[6]_0 ;
wire \gwdc.wr_data_count_i[3]_i_2_n_0 ;
wire \gwdc.wr_data_count_i[3]_i_3_n_0 ;
wire \gwdc.wr_data_count_i[3]_i_4_n_0 ;
wire \gwdc.wr_data_count_i[3]_i_5_n_0 ;
wire \gwdc.wr_data_count_i[7]_i_2_n_0 ;
wire \gwdc.wr_data_count_i[7]_i_3_n_0 ;
wire \gwdc.wr_data_count_i[7]_i_4_n_0 ;
wire \gwdc.wr_data_count_i[7]_i_5_n_0 ;
wire \gwdc.wr_data_count_i[8]_i_2_n_0 ;
wire \gwdc.wr_data_count_i_reg[3]_i_1_n_0 ;
wire \gwdc.wr_data_count_i_reg[3]_i_1_n_1 ;
wire \gwdc.wr_data_count_i_reg[3]_i_1_n_2 ;
wire \gwdc.wr_data_count_i_reg[3]_i_1_n_3 ;
wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ;
wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ;
wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ;
wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ;
wire [8:0]\gwdc.wr_data_count_i_reg[8] ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
wire [3:0]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ;
wire [3:1]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\count_value_i[0]_i_1__1
(.I0(Q[0]),
.O(\count_value_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h6))
\count_value_i[1]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.O(\count_value_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1__1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1__1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1__1
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2__1_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1__1
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2__1_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000800000000))
\count_value_i[6]_i_2__1
(.I0(Q[1]),
.I1(wr_en),
.I2(\count_value_i_reg[6]_0 ),
.I3(wrst_busy),
.I4(rst_d1),
.I5(Q[0]),
.O(\count_value_i[6]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1__1
(.I0(Q[5]),
.I1(\count_value_i[8]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[8]_i_1
(.I0(Q[6]),
.I1(\count_value_i[8]_i_2_n_0 ),
.I2(Q[5]),
.I3(Q[7]),
.I4(Q[8]),
.O(\count_value_i[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[8]_i_2
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(wr_pntr_plus1_pf_carry),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[8]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[0]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[0]_i_1__1_n_0 ),
.Q(Q[0]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[1]_i_1__1_n_0 ),
.Q(Q[1]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[2]_i_1__1_n_0 ),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[3]_i_1__1_n_0 ),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[4]_i_1__1_n_0 ),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[5]_i_1__1_n_0 ),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[6]_i_1__1_n_0 ),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[7]_i_1__1_n_0 ),
.Q(Q[7]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[8]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[8]_i_1_n_0 ),
.Q(Q[8]),
.R(wrst_busy));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[3]_i_2
(.I0(Q[3]),
.I1(\gwdc.wr_data_count_i_reg[8] [3]),
.O(\gwdc.wr_data_count_i[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[3]_i_3
(.I0(Q[2]),
.I1(\gwdc.wr_data_count_i_reg[8] [2]),
.O(\gwdc.wr_data_count_i[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[3]_i_4
(.I0(Q[1]),
.I1(\gwdc.wr_data_count_i_reg[8] [1]),
.O(\gwdc.wr_data_count_i[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[3]_i_5
(.I0(Q[0]),
.I1(\gwdc.wr_data_count_i_reg[8] [0]),
.O(\gwdc.wr_data_count_i[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[7]_i_2
(.I0(Q[7]),
.I1(\gwdc.wr_data_count_i_reg[8] [7]),
.O(\gwdc.wr_data_count_i[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[7]_i_3
(.I0(Q[6]),
.I1(\gwdc.wr_data_count_i_reg[8] [6]),
.O(\gwdc.wr_data_count_i[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[7]_i_4
(.I0(Q[5]),
.I1(\gwdc.wr_data_count_i_reg[8] [5]),
.O(\gwdc.wr_data_count_i[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[7]_i_5
(.I0(Q[4]),
.I1(\gwdc.wr_data_count_i_reg[8] [4]),
.O(\gwdc.wr_data_count_i[7]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[8]_i_2
(.I0(Q[8]),
.I1(\gwdc.wr_data_count_i_reg[8] [8]),
.O(\gwdc.wr_data_count_i[8]_i_2_n_0 ));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gwdc.wr_data_count_i_reg[3]_i_1
(.CI(1'b0),
.CO({\gwdc.wr_data_count_i_reg[3]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O(D[3:0]),
.S({\gwdc.wr_data_count_i[3]_i_2_n_0 ,\gwdc.wr_data_count_i[3]_i_3_n_0 ,\gwdc.wr_data_count_i[3]_i_4_n_0 ,\gwdc.wr_data_count_i[3]_i_5_n_0 }));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gwdc.wr_data_count_i_reg[7]_i_1
(.CI(\gwdc.wr_data_count_i_reg[3]_i_1_n_0 ),
.CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O(D[7:4]),
.S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 }));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gwdc.wr_data_count_i_reg[8]_i_1
(.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ),
.CO(\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [3:1],D[8]}),
.S({1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[8]_i_2_n_0 }));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_3
(Q,
D,
wr_pntr_plus1_pf_carry,
wr_en,
\count_value_i_reg[6]_0 ,
wrst_busy,
rst_d1,
\gwdc.wr_data_count_i_reg[8] ,
wr_clk);
output [8:0]Q;
output [8:0]D;
input wr_pntr_plus1_pf_carry;
input wr_en;
input \count_value_i_reg[6]_0 ;
input wrst_busy;
input rst_d1;
input [8:0]\gwdc.wr_data_count_i_reg[8] ;
input wr_clk;
wire [8:0]D;
wire [8:0]Q;
wire \count_value_i[0]_i_1__1_n_0 ;
wire \count_value_i[1]_i_1__1_n_0 ;
wire \count_value_i[2]_i_1__1_n_0 ;
wire \count_value_i[3]_i_1__1_n_0 ;
wire \count_value_i[4]_i_1__1_n_0 ;
wire \count_value_i[5]_i_1__1_n_0 ;
wire \count_value_i[6]_i_1__1_n_0 ;
wire \count_value_i[6]_i_2__1_n_0 ;
wire \count_value_i[7]_i_1__1_n_0 ;
wire \count_value_i[8]_i_1_n_0 ;
wire \count_value_i[8]_i_2_n_0 ;
wire \count_value_i_reg[6]_0 ;
wire \gwdc.wr_data_count_i[3]_i_2_n_0 ;
wire \gwdc.wr_data_count_i[3]_i_3_n_0 ;
wire \gwdc.wr_data_count_i[3]_i_4_n_0 ;
wire \gwdc.wr_data_count_i[3]_i_5_n_0 ;
wire \gwdc.wr_data_count_i[7]_i_2_n_0 ;
wire \gwdc.wr_data_count_i[7]_i_3_n_0 ;
wire \gwdc.wr_data_count_i[7]_i_4_n_0 ;
wire \gwdc.wr_data_count_i[7]_i_5_n_0 ;
wire \gwdc.wr_data_count_i[8]_i_2_n_0 ;
wire \gwdc.wr_data_count_i_reg[3]_i_1_n_0 ;
wire \gwdc.wr_data_count_i_reg[3]_i_1_n_1 ;
wire \gwdc.wr_data_count_i_reg[3]_i_1_n_2 ;
wire \gwdc.wr_data_count_i_reg[3]_i_1_n_3 ;
wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ;
wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ;
wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ;
wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ;
wire [8:0]\gwdc.wr_data_count_i_reg[8] ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
wire [3:0]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ;
wire [3:1]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\count_value_i[0]_i_1__1
(.I0(Q[0]),
.O(\count_value_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT2 #(
.INIT(4'h6))
\count_value_i[1]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.O(\count_value_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1__1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1__1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1__1
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2__1_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1__1
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2__1_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000800000000))
\count_value_i[6]_i_2__1
(.I0(Q[1]),
.I1(wr_en),
.I2(\count_value_i_reg[6]_0 ),
.I3(wrst_busy),
.I4(rst_d1),
.I5(Q[0]),
.O(\count_value_i[6]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1__1
(.I0(Q[5]),
.I1(\count_value_i[8]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[8]_i_1
(.I0(Q[6]),
.I1(\count_value_i[8]_i_2_n_0 ),
.I2(Q[5]),
.I3(Q[7]),
.I4(Q[8]),
.O(\count_value_i[8]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[8]_i_2
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(wr_pntr_plus1_pf_carry),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[8]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[0]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[0]_i_1__1_n_0 ),
.Q(Q[0]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[1]_i_1__1_n_0 ),
.Q(Q[1]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[2]_i_1__1_n_0 ),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[3]_i_1__1_n_0 ),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[4]_i_1__1_n_0 ),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[5]_i_1__1_n_0 ),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[6]_i_1__1_n_0 ),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[7]_i_1__1_n_0 ),
.Q(Q[7]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[8]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[8]_i_1_n_0 ),
.Q(Q[8]),
.R(wrst_busy));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[3]_i_2
(.I0(Q[3]),
.I1(\gwdc.wr_data_count_i_reg[8] [3]),
.O(\gwdc.wr_data_count_i[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[3]_i_3
(.I0(Q[2]),
.I1(\gwdc.wr_data_count_i_reg[8] [2]),
.O(\gwdc.wr_data_count_i[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[3]_i_4
(.I0(Q[1]),
.I1(\gwdc.wr_data_count_i_reg[8] [1]),
.O(\gwdc.wr_data_count_i[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[3]_i_5
(.I0(Q[0]),
.I1(\gwdc.wr_data_count_i_reg[8] [0]),
.O(\gwdc.wr_data_count_i[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[7]_i_2
(.I0(Q[7]),
.I1(\gwdc.wr_data_count_i_reg[8] [7]),
.O(\gwdc.wr_data_count_i[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[7]_i_3
(.I0(Q[6]),
.I1(\gwdc.wr_data_count_i_reg[8] [6]),
.O(\gwdc.wr_data_count_i[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[7]_i_4
(.I0(Q[5]),
.I1(\gwdc.wr_data_count_i_reg[8] [5]),
.O(\gwdc.wr_data_count_i[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[7]_i_5
(.I0(Q[4]),
.I1(\gwdc.wr_data_count_i_reg[8] [4]),
.O(\gwdc.wr_data_count_i[7]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gwdc.wr_data_count_i[8]_i_2
(.I0(Q[8]),
.I1(\gwdc.wr_data_count_i_reg[8] [8]),
.O(\gwdc.wr_data_count_i[8]_i_2_n_0 ));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gwdc.wr_data_count_i_reg[3]_i_1
(.CI(1'b0),
.CO({\gwdc.wr_data_count_i_reg[3]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[3]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O(D[3:0]),
.S({\gwdc.wr_data_count_i[3]_i_2_n_0 ,\gwdc.wr_data_count_i[3]_i_3_n_0 ,\gwdc.wr_data_count_i[3]_i_4_n_0 ,\gwdc.wr_data_count_i[3]_i_5_n_0 }));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gwdc.wr_data_count_i_reg[7]_i_1
(.CI(\gwdc.wr_data_count_i_reg[3]_i_1_n_0 ),
.CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O(D[7:4]),
.S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 }));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gwdc.wr_data_count_i_reg[8]_i_1
(.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ),
.CO(\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [3:1],D[8]}),
.S({1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[8]_i_2_n_0 }));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3
(Q,
E,
\count_value_i_reg[1]_0 ,
rd_en,
ram_empty_i,
\count_value_i_reg[0]_0 ,
rd_clk);
output [7:0]Q;
input [0:0]E;
input [1:0]\count_value_i_reg[1]_0 ;
input rd_en;
input ram_empty_i;
input \count_value_i_reg[0]_0 ;
input rd_clk;
wire [0:0]E;
wire [7:0]Q;
wire \count_value_i[0]_i_1__3_n_0 ;
wire \count_value_i[1]_i_1__3_n_0 ;
wire \count_value_i[2]_i_1__3_n_0 ;
wire \count_value_i[3]_i_1__3_n_0 ;
wire \count_value_i[4]_i_1__3_n_0 ;
wire \count_value_i[5]_i_1__4_n_0 ;
wire \count_value_i[6]_i_1__4_n_0 ;
wire \count_value_i[6]_i_2__4_n_0 ;
wire \count_value_i[7]_i_1__4_n_0 ;
wire \count_value_i[7]_i_2__2_n_0 ;
wire \count_value_i_reg[0]_0 ;
wire [1:0]\count_value_i_reg[1]_0 ;
wire ram_empty_i;
wire rd_clk;
wire rd_en;
LUT4 #(
.INIT(16'h10EF))
\count_value_i[0]_i_1__3
(.I0(rd_en),
.I1(\count_value_i_reg[1]_0 [0]),
.I2(\count_value_i_reg[1]_0 [1]),
.I3(Q[0]),
.O(\count_value_i[0]_i_1__3_n_0 ));
LUT5 #(
.INIT(32'h02FFFD00))
\count_value_i[1]_i_1__3
(.I0(\count_value_i_reg[1]_0 [1]),
.I1(\count_value_i_reg[1]_0 [0]),
.I2(rd_en),
.I3(Q[0]),
.I4(Q[1]),
.O(\count_value_i[1]_i_1__3_n_0 ));
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1__3
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1__3
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1__3
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1__3_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1__4
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2__4_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1__4
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2__4_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000AAA200000000))
\count_value_i[6]_i_2__4
(.I0(Q[1]),
.I1(\count_value_i_reg[1]_0 [1]),
.I2(\count_value_i_reg[1]_0 [0]),
.I3(rd_en),
.I4(ram_empty_i),
.I5(Q[0]),
.O(\count_value_i[6]_i_2__4_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1__4
(.I0(Q[5]),
.I1(\count_value_i[7]_i_2__2_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[7]_i_2__2
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(E),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[7]_i_2__2_n_0 ));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[0]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[0]_i_1__3_n_0 ),
.Q(Q[0]),
.S(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[1]_i_1__3_n_0 ),
.Q(Q[1]),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[2]_i_1__3_n_0 ),
.Q(Q[2]),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[3]_i_1__3_n_0 ),
.Q(Q[3]),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[4]_i_1__3_n_0 ),
.Q(Q[4]),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[5]_i_1__4_n_0 ),
.Q(Q[5]),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[6]_i_1__4_n_0 ),
.Q(Q[6]),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[7]_i_1__4_n_0 ),
.Q(Q[7]),
.R(\count_value_i_reg[0]_0 ));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12
(ram_empty_i0,
\gen_pf_ic_rc.ram_empty_i_reg ,
ram_empty_i,
Q,
rd_en,
\gen_pf_ic_rc.ram_empty_i_reg_0 ,
\gen_pf_ic_rc.ram_empty_i_reg_1 ,
\count_value_i_reg[0]_0 ,
E,
rd_clk);
output ram_empty_i0;
output \gen_pf_ic_rc.ram_empty_i_reg ;
input ram_empty_i;
input [1:0]Q;
input rd_en;
input \gen_pf_ic_rc.ram_empty_i_reg_0 ;
input [7:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ;
input \count_value_i_reg[0]_0 ;
input [0:0]E;
input rd_clk;
wire [0:0]E;
wire [1:0]Q;
wire \count_value_i[0]_i_1__3_n_0 ;
wire \count_value_i[1]_i_1__3_n_0 ;
wire \count_value_i[2]_i_1__3_n_0 ;
wire \count_value_i[3]_i_1__3_n_0 ;
wire \count_value_i[4]_i_1__3_n_0 ;
wire \count_value_i[5]_i_1__3_n_0 ;
wire \count_value_i[6]_i_1__3_n_0 ;
wire \count_value_i[6]_i_2__3_n_0 ;
wire \count_value_i[7]_i_1__4_n_0 ;
wire \count_value_i[7]_i_2__2_n_0 ;
wire \count_value_i_reg[0]_0 ;
wire \count_value_i_reg_n_0_[0] ;
wire \count_value_i_reg_n_0_[1] ;
wire \count_value_i_reg_n_0_[2] ;
wire \count_value_i_reg_n_0_[3] ;
wire \count_value_i_reg_n_0_[4] ;
wire \count_value_i_reg_n_0_[5] ;
wire \count_value_i_reg_n_0_[6] ;
wire \count_value_i_reg_n_0_[7] ;
wire \gen_pf_ic_rc.ram_empty_i_i_2_n_0 ;
wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ;
wire \gen_pf_ic_rc.ram_empty_i_i_5_n_0 ;
wire \gen_pf_ic_rc.ram_empty_i_reg ;
wire \gen_pf_ic_rc.ram_empty_i_reg_0 ;
wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ;
wire ram_empty_i;
wire ram_empty_i0;
wire rd_clk;
wire rd_en;
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h5565))
\count_value_i[0]_i_1__3
(.I0(\count_value_i_reg_n_0_[0] ),
.I1(rd_en),
.I2(Q[1]),
.I3(Q[0]),
.O(\count_value_i[0]_i_1__3_n_0 ));
LUT5 #(
.INIT(32'h5565AAAA))
\count_value_i[1]_i_1__3
(.I0(\count_value_i_reg_n_0_[1] ),
.I1(rd_en),
.I2(Q[1]),
.I3(Q[0]),
.I4(\count_value_i_reg_n_0_[0] ),
.O(\count_value_i[1]_i_1__3_n_0 ));
LUT4 #(
.INIT(16'hA6AA))
\count_value_i[2]_i_1__3
(.I0(\count_value_i_reg_n_0_[2] ),
.I1(\count_value_i_reg_n_0_[0] ),
.I2(\gen_pf_ic_rc.ram_empty_i_reg ),
.I3(\count_value_i_reg_n_0_[1] ),
.O(\count_value_i[2]_i_1__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'hDFFF2000))
\count_value_i[3]_i_1__3
(.I0(\count_value_i_reg_n_0_[1] ),
.I1(\gen_pf_ic_rc.ram_empty_i_reg ),
.I2(\count_value_i_reg_n_0_[0] ),
.I3(\count_value_i_reg_n_0_[2] ),
.I4(\count_value_i_reg_n_0_[3] ),
.O(\count_value_i[3]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'hA6AAAAAAAAAAAAAA))
\count_value_i[4]_i_1__3
(.I0(\count_value_i_reg_n_0_[4] ),
.I1(\count_value_i_reg_n_0_[1] ),
.I2(\gen_pf_ic_rc.ram_empty_i_reg ),
.I3(\count_value_i_reg_n_0_[0] ),
.I4(\count_value_i_reg_n_0_[2] ),
.I5(\count_value_i_reg_n_0_[3] ),
.O(\count_value_i[4]_i_1__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hAABA))
\count_value_i[4]_i_2
(.I0(ram_empty_i),
.I1(Q[0]),
.I2(Q[1]),
.I3(rd_en),
.O(\gen_pf_ic_rc.ram_empty_i_reg ));
LUT5 #(
.INIT(32'hAA6AAAAA))
\count_value_i[5]_i_1__3
(.I0(\count_value_i_reg_n_0_[5] ),
.I1(\count_value_i_reg_n_0_[3] ),
.I2(\count_value_i_reg_n_0_[2] ),
.I3(\count_value_i[6]_i_2__3_n_0 ),
.I4(\count_value_i_reg_n_0_[4] ),
.O(\count_value_i[5]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'hA6AAAAAAAAAAAAAA))
\count_value_i[6]_i_1__3
(.I0(\count_value_i_reg_n_0_[6] ),
.I1(\count_value_i_reg_n_0_[4] ),
.I2(\count_value_i[6]_i_2__3_n_0 ),
.I3(\count_value_i_reg_n_0_[2] ),
.I4(\count_value_i_reg_n_0_[3] ),
.I5(\count_value_i_reg_n_0_[5] ),
.O(\count_value_i[6]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'hDDDDDFDDFFFFFFFF))
\count_value_i[6]_i_2__3
(.I0(\count_value_i_reg_n_0_[0] ),
.I1(ram_empty_i),
.I2(Q[0]),
.I3(Q[1]),
.I4(rd_en),
.I5(\count_value_i_reg_n_0_[1] ),
.O(\count_value_i[6]_i_2__3_n_0 ));
LUT5 #(
.INIT(32'h6AAAAAAA))
\count_value_i[7]_i_1__4
(.I0(\count_value_i_reg_n_0_[7] ),
.I1(\count_value_i_reg_n_0_[5] ),
.I2(\count_value_i[7]_i_2__2_n_0 ),
.I3(\count_value_i_reg_n_0_[4] ),
.I4(\count_value_i_reg_n_0_[6] ),
.O(\count_value_i[7]_i_1__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h00800000))
\count_value_i[7]_i_2__2
(.I0(\count_value_i_reg_n_0_[3] ),
.I1(\count_value_i_reg_n_0_[2] ),
.I2(\count_value_i_reg_n_0_[0] ),
.I3(\gen_pf_ic_rc.ram_empty_i_reg ),
.I4(\count_value_i_reg_n_0_[1] ),
.O(\count_value_i[7]_i_2__2_n_0 ));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[0]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[0]_i_1__3_n_0 ),
.Q(\count_value_i_reg_n_0_[0] ),
.S(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[1]_i_1__3_n_0 ),
.Q(\count_value_i_reg_n_0_[1] ),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[2]_i_1__3_n_0 ),
.Q(\count_value_i_reg_n_0_[2] ),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[3]_i_1__3_n_0 ),
.Q(\count_value_i_reg_n_0_[3] ),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[4]_i_1__3_n_0 ),
.Q(\count_value_i_reg_n_0_[4] ),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[5]_i_1__3_n_0 ),
.Q(\count_value_i_reg_n_0_[5] ),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[6]_i_1__3_n_0 ),
.Q(\count_value_i_reg_n_0_[6] ),
.R(\count_value_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(rd_clk),
.CE(E),
.D(\count_value_i[7]_i_1__4_n_0 ),
.Q(\count_value_i_reg_n_0_[7] ),
.R(\count_value_i_reg[0]_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF11111011))
\gen_pf_ic_rc.ram_empty_i_i_1
(.I0(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 ),
.I1(ram_empty_i),
.I2(Q[0]),
.I3(Q[1]),
.I4(rd_en),
.I5(\gen_pf_ic_rc.ram_empty_i_reg_0 ),
.O(ram_empty_i0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF6FF6))
\gen_pf_ic_rc.ram_empty_i_i_2
(.I0(\gen_pf_ic_rc.ram_empty_i_reg_1 [6]),
.I1(\count_value_i_reg_n_0_[6] ),
.I2(\gen_pf_ic_rc.ram_empty_i_reg_1 [7]),
.I3(\count_value_i_reg_n_0_[7] ),
.I4(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ),
.I5(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ),
.O(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\gen_pf_ic_rc.ram_empty_i_i_4
(.I0(\count_value_i_reg_n_0_[0] ),
.I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [0]),
.I2(\gen_pf_ic_rc.ram_empty_i_reg_1 [2]),
.I3(\count_value_i_reg_n_0_[2] ),
.I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [1]),
.I5(\count_value_i_reg_n_0_[1] ),
.O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\gen_pf_ic_rc.ram_empty_i_i_5
(.I0(\count_value_i_reg_n_0_[3] ),
.I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [3]),
.I2(\gen_pf_ic_rc.ram_empty_i_reg_1 [5]),
.I3(\count_value_i_reg_n_0_[5] ),
.I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [4]),
.I5(\count_value_i_reg_n_0_[4] ),
.O(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_15
(Q,
D,
wr_pntr_plus1_pf_carry,
wr_en,
\count_value_i_reg[6]_0 ,
wrst_busy,
rst_d1,
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ,
wr_clk);
output [7:0]Q;
output [4:0]D;
input wr_pntr_plus1_pf_carry;
input wr_en;
input \count_value_i_reg[6]_0 ;
input wrst_busy;
input rst_d1;
input [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ;
input wr_clk;
wire [4:0]D;
wire [7:0]Q;
wire \count_value_i[0]_i_1__0_n_0 ;
wire \count_value_i[1]_i_1__0_n_0 ;
wire \count_value_i[2]_i_1__0_n_0 ;
wire \count_value_i[3]_i_1__0_n_0 ;
wire \count_value_i[4]_i_1__0_n_0 ;
wire \count_value_i[5]_i_1__0_n_0 ;
wire \count_value_i[6]_i_1__0_n_0 ;
wire \count_value_i[6]_i_2__0_n_0 ;
wire \count_value_i[7]_i_1__0_n_0 ;
wire \count_value_i[7]_i_2__0_n_0 ;
wire \count_value_i_reg[6]_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_1 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_2 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_3 ;
wire [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
wire [2:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_O_UNCONNECTED ;
wire [3:3]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\count_value_i[0]_i_1__0
(.I0(Q[0]),
.O(\count_value_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h6))
\count_value_i[1]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.O(\count_value_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1__0
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1__0
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2__0_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1__0
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2__0_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0000000800000000))
\count_value_i[6]_i_2__0
(.I0(Q[1]),
.I1(wr_en),
.I2(\count_value_i_reg[6]_0 ),
.I3(wrst_busy),
.I4(rst_d1),
.I5(Q[0]),
.O(\count_value_i[6]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1__0
(.I0(Q[5]),
.I1(\count_value_i[7]_i_2__0_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[7]_i_2__0
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(wr_pntr_plus1_pf_carry),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[7]_i_2__0_n_0 ));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[0]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.S(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(wrst_busy));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2
(.I0(Q[3]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [3]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3
(.I0(Q[2]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [2]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4
(.I0(Q[1]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [1]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5
(.I0(Q[0]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [0]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2
(.I0(Q[7]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [7]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3
(.I0(Q[6]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [6]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4
(.I0(Q[5]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [5]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5
(.I0(Q[4]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [4]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1
(.CI(1'b0),
.CO({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_3 }),
.CYINIT(wr_pntr_plus1_pf_carry),
.DI(Q[3:0]),
.O({D[0],\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_O_UNCONNECTED [2:0]}),
.S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0 }));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1
(.CI(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0 ),
.CO({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED [3],\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,Q[6:4]}),
.O(D[4:1]),
.S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 }));
endmodule
(* ORIG_REF_NAME = "xpm_counter_updn" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_4
(Q,
D,
wr_pntr_plus1_pf_carry,
wr_en,
\count_value_i_reg[6]_0 ,
wrst_busy,
rst_d1,
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ,
wr_clk);
output [7:0]Q;
output [4:0]D;
input wr_pntr_plus1_pf_carry;
input wr_en;
input \count_value_i_reg[6]_0 ;
input wrst_busy;
input rst_d1;
input [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ;
input wr_clk;
wire [4:0]D;
wire [7:0]Q;
wire \count_value_i[0]_i_1__0_n_0 ;
wire \count_value_i[1]_i_1__0_n_0 ;
wire \count_value_i[2]_i_1__0_n_0 ;
wire \count_value_i[3]_i_1__0_n_0 ;
wire \count_value_i[4]_i_1__0_n_0 ;
wire \count_value_i[5]_i_1__0_n_0 ;
wire \count_value_i[6]_i_1__0_n_0 ;
wire \count_value_i[6]_i_2__0_n_0 ;
wire \count_value_i[7]_i_1__0_n_0 ;
wire \count_value_i[7]_i_2__0_n_0 ;
wire \count_value_i_reg[6]_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_1 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_2 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_3 ;
wire [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ;
wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
wire [2:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_O_UNCONNECTED ;
wire [3:3]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\count_value_i[0]_i_1__0
(.I0(Q[0]),
.O(\count_value_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT2 #(
.INIT(4'h6))
\count_value_i[1]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.O(\count_value_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'h78))
\count_value_i[2]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(\count_value_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'h7F80))
\count_value_i[3]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(\count_value_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[4]_i_1__0
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(\count_value_i[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h7FFF8000))
\count_value_i[5]_i_1__0
(.I0(Q[3]),
.I1(\count_value_i[6]_i_2__0_n_0 ),
.I2(Q[2]),
.I3(Q[4]),
.I4(Q[5]),
.O(\count_value_i[5]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\count_value_i[6]_i_1__0
(.I0(Q[4]),
.I1(Q[2]),
.I2(\count_value_i[6]_i_2__0_n_0 ),
.I3(Q[3]),
.I4(Q[5]),
.I5(Q[6]),
.O(\count_value_i[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0000000800000000))
\count_value_i[6]_i_2__0
(.I0(Q[1]),
.I1(wr_en),
.I2(\count_value_i_reg[6]_0 ),
.I3(wrst_busy),
.I4(rst_d1),
.I5(Q[0]),
.O(\count_value_i[6]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h7F80))
\count_value_i[7]_i_1__0
(.I0(Q[5]),
.I1(\count_value_i[7]_i_2__0_n_0 ),
.I2(Q[6]),
.I3(Q[7]),
.O(\count_value_i[7]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\count_value_i[7]_i_2__0
(.I0(Q[4]),
.I1(Q[2]),
.I2(Q[0]),
.I3(wr_pntr_plus1_pf_carry),
.I4(Q[1]),
.I5(Q[3]),
.O(\count_value_i[7]_i_2__0_n_0 ));
FDSE #(
.INIT(1'b1))
\count_value_i_reg[0]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.S(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[1]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[2]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[3]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[4]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[5]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[6]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\count_value_i_reg[7]
(.C(wr_clk),
.CE(wr_pntr_plus1_pf_carry),
.D(\count_value_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(wrst_busy));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2
(.I0(Q[3]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [3]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3
(.I0(Q[2]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [2]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4
(.I0(Q[1]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [1]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5
(.I0(Q[0]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [0]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2
(.I0(Q[7]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [7]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3
(.I0(Q[6]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [6]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4
(.I0(Q[5]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [5]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5
(.I0(Q[4]),
.I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [4]),
.O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1
(.CI(1'b0),
.CO({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_3 }),
.CYINIT(wr_pntr_plus1_pf_carry),
.DI(Q[3:0]),
.O({D[0],\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_O_UNCONNECTED [2:0]}),
.S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0 }));
(* ADDER_THRESHOLD = "35" *)
CARRY4 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1
(.CI(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0 ),
.CO({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED [3],\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,Q[6:4]}),
.O(D[4:1]),
.S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 }));
endmodule
(* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "2" *) (* DOUT_RESET_VALUE = "0" *)
(* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0001111100011111" *) (* FIFO_MEMORY_TYPE = "auto" *)
(* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "0" *)
(* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "10" *) (* P_COMMON_CLOCK = "0" *)
(* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "0" *) (* P_READ_MODE = "1" *)
(* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* READ_DATA_WIDTH = "8" *)
(* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *)
(* USE_ADV_FEATURES = "1f1f" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "8" *)
(* WR_DATA_COUNT_WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async
(sleep,
rst,
wr_clk,
wr_en,
din,
full,
prog_full,
wr_data_count,
overflow,
wr_rst_busy,
almost_full,
wr_ack,
rd_clk,
rd_en,
dout,
empty,
prog_empty,
rd_data_count,
underflow,
rd_rst_busy,
almost_empty,
data_valid,
injectsbiterr,
injectdbiterr,
sbiterr,
dbiterr);
input sleep;
input rst;
input wr_clk;
input wr_en;
input [7:0]din;
output full;
output prog_full;
output [8:0]wr_data_count;
output overflow;
output wr_rst_busy;
output almost_full;
output wr_ack;
input rd_clk;
input rd_en;
output [7:0]dout;
output empty;
output prog_empty;
output [8:0]rd_data_count;
output underflow;
output rd_rst_busy;
output almost_empty;
output data_valid;
input injectsbiterr;
input injectdbiterr;
output sbiterr;
output dbiterr;
wire \<const0> ;
wire almost_empty;
wire almost_full;
wire data_valid;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire overflow;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rd_rst_busy;
wire rst;
wire sleep;
wire underflow;
wire wr_ack;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ;
wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ;
wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ;
assign dbiterr = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
(* CASCADE_HEIGHT = "0" *)
(* CDC_DEST_SYNC_FF = "2" *)
(* COMMON_CLOCK = "0" *)
(* DOUT_RESET_VALUE = "0" *)
(* ECC_MODE = "0" *)
(* ENABLE_ECC = "0" *)
(* EN_ADV_FEATURE = "16'b0001111100011111" *)
(* EN_AE = "1'b1" *)
(* EN_AF = "1'b1" *)
(* EN_DVLD = "1'b1" *)
(* EN_OF = "1'b1" *)
(* EN_PE = "1'b1" *)
(* EN_PF = "1'b1" *)
(* EN_RDC = "1'b1" *)
(* EN_UF = "1'b1" *)
(* EN_WACK = "1'b1" *)
(* EN_WDC = "1'b1" *)
(* FG_EQ_ASYM_DOUT = "1'b0" *)
(* FIFO_MEMORY_TYPE = "0" *)
(* FIFO_MEM_TYPE = "0" *)
(* FIFO_READ_DEPTH = "256" *)
(* FIFO_READ_LATENCY = "0" *)
(* FIFO_SIZE = "2048" *)
(* FIFO_WRITE_DEPTH = "256" *)
(* FULL_RESET_VALUE = "0" *)
(* FULL_RST_VAL = "1'b0" *)
(* KEEP_HIERARCHY = "soft" *)
(* PE_THRESH_ADJ = "8" *)
(* PE_THRESH_MAX = "251" *)
(* PE_THRESH_MIN = "5" *)
(* PF_THRESH_ADJ = "8" *)
(* PF_THRESH_MAX = "251" *)
(* PF_THRESH_MIN = "7" *)
(* PROG_EMPTY_THRESH = "10" *)
(* PROG_FULL_THRESH = "10" *)
(* RD_DATA_COUNT_WIDTH = "9" *)
(* RD_DC_WIDTH_EXT = "9" *)
(* RD_LATENCY = "2" *)
(* RD_MODE = "1" *)
(* RD_PNTR_WIDTH = "8" *)
(* READ_DATA_WIDTH = "8" *)
(* READ_MODE = "1" *)
(* READ_MODE_LL = "1" *)
(* RELATED_CLOCKS = "0" *)
(* REMOVE_WR_RD_PROT_LOGIC = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* USE_ADV_FEATURES = "1f1f" *)
(* VERSION = "0" *)
(* WAKEUP_TIME = "0" *)
(* WIDTH_RATIO = "1" *)
(* WRITE_DATA_WIDTH = "8" *)
(* WR_DATA_COUNT_WIDTH = "9" *)
(* WR_DC_WIDTH_EXT = "9" *)
(* WR_DEPTH_LOG = "8" *)
(* WR_PNTR_WIDTH = "8" *)
(* WR_RD_RATIO = "0" *)
(* WR_WIDTH_LOG = "3" *)
(* XPM_MODULE = "TRUE" *)
(* both_stages_valid = "3" *)
(* invalid = "0" *)
(* stage1_valid = "2" *)
(* stage2_valid = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base \gnuram_async_fifo.xpm_fifo_base_inst
(.almost_empty(almost_empty),
.almost_full(almost_full),
.data_valid(data_valid),
.dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.overflow(overflow),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rd_rst_busy(rd_rst_busy),
.rst(rst),
.sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ),
.sleep(sleep),
.underflow(underflow),
.wr_ack(wr_ack),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "2" *) (* DOUT_RESET_VALUE = "0" *)
(* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0001111100011111" *) (* FIFO_MEMORY_TYPE = "auto" *)
(* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *)
(* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "10" *)
(* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "0" *)
(* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "9" *)
(* READ_DATA_WIDTH = "8" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *)
(* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "1F1F" *) (* WAKEUP_TIME = "0" *)
(* WRITE_DATA_WIDTH = "8" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* XPM_MODULE = "TRUE" *)
(* dont_touch = "true" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1
(sleep,
rst,
wr_clk,
wr_en,
din,
full,
prog_full,
wr_data_count,
overflow,
wr_rst_busy,
almost_full,
wr_ack,
rd_clk,
rd_en,
dout,
empty,
prog_empty,
rd_data_count,
underflow,
rd_rst_busy,
almost_empty,
data_valid,
injectsbiterr,
injectdbiterr,
sbiterr,
dbiterr);
input sleep;
input rst;
input wr_clk;
input wr_en;
input [7:0]din;
output full;
output prog_full;
output [8:0]wr_data_count;
output overflow;
output wr_rst_busy;
output almost_full;
output wr_ack;
input rd_clk;
input rd_en;
output [7:0]dout;
output empty;
output prog_empty;
output [8:0]rd_data_count;
output underflow;
output rd_rst_busy;
output almost_empty;
output data_valid;
input injectsbiterr;
input injectdbiterr;
output sbiterr;
output dbiterr;
wire \<const0> ;
wire almost_empty;
wire almost_full;
wire data_valid;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire overflow;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire rd_rst_busy;
wire rst;
wire sleep;
wire underflow;
wire wr_ack;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ;
wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ;
wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ;
assign dbiterr = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
(* CASCADE_HEIGHT = "0" *)
(* CDC_DEST_SYNC_FF = "2" *)
(* COMMON_CLOCK = "0" *)
(* DOUT_RESET_VALUE = "0" *)
(* ECC_MODE = "0" *)
(* ENABLE_ECC = "0" *)
(* EN_ADV_FEATURE = "16'b0001111100011111" *)
(* EN_AE = "1'b1" *)
(* EN_AF = "1'b1" *)
(* EN_DVLD = "1'b1" *)
(* EN_OF = "1'b1" *)
(* EN_PE = "1'b1" *)
(* EN_PF = "1'b1" *)
(* EN_RDC = "1'b1" *)
(* EN_UF = "1'b1" *)
(* EN_WACK = "1'b1" *)
(* EN_WDC = "1'b1" *)
(* FG_EQ_ASYM_DOUT = "1'b0" *)
(* FIFO_MEMORY_TYPE = "0" *)
(* FIFO_MEM_TYPE = "0" *)
(* FIFO_READ_DEPTH = "256" *)
(* FIFO_READ_LATENCY = "0" *)
(* FIFO_SIZE = "2048" *)
(* FIFO_WRITE_DEPTH = "256" *)
(* FULL_RESET_VALUE = "1" *)
(* FULL_RST_VAL = "1'b1" *)
(* KEEP_HIERARCHY = "soft" *)
(* PE_THRESH_ADJ = "8" *)
(* PE_THRESH_MAX = "251" *)
(* PE_THRESH_MIN = "5" *)
(* PF_THRESH_ADJ = "8" *)
(* PF_THRESH_MAX = "251" *)
(* PF_THRESH_MIN = "7" *)
(* PROG_EMPTY_THRESH = "10" *)
(* PROG_FULL_THRESH = "10" *)
(* RD_DATA_COUNT_WIDTH = "9" *)
(* RD_DC_WIDTH_EXT = "9" *)
(* RD_LATENCY = "2" *)
(* RD_MODE = "1" *)
(* RD_PNTR_WIDTH = "8" *)
(* READ_DATA_WIDTH = "8" *)
(* READ_MODE = "1" *)
(* READ_MODE_LL = "1" *)
(* RELATED_CLOCKS = "0" *)
(* REMOVE_WR_RD_PROT_LOGIC = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* USE_ADV_FEATURES = "1F1F" *)
(* VERSION = "0" *)
(* WAKEUP_TIME = "0" *)
(* WIDTH_RATIO = "1" *)
(* WRITE_DATA_WIDTH = "8" *)
(* WR_DATA_COUNT_WIDTH = "9" *)
(* WR_DC_WIDTH_EXT = "9" *)
(* WR_DEPTH_LOG = "8" *)
(* WR_PNTR_WIDTH = "8" *)
(* WR_RD_RATIO = "0" *)
(* WR_WIDTH_LOG = "3" *)
(* XPM_MODULE = "TRUE" *)
(* both_stages_valid = "3" *)
(* invalid = "0" *)
(* stage1_valid = "2" *)
(* stage2_valid = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0 \gnuram_async_fifo.xpm_fifo_base_inst
(.almost_empty(almost_empty),
.almost_full(almost_full),
.data_valid(data_valid),
.dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.overflow(overflow),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rd_rst_busy(rd_rst_busy),
.rst(rst),
.sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ),
.sleep(sleep),
.underflow(underflow),
.wr_ack(wr_ack),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "2" *) (* COMMON_CLOCK = "0" *)
(* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *)
(* EN_ADV_FEATURE = "16'b0001111100011111" *) (* EN_AE = "1'b1" *) (* EN_AF = "1'b1" *)
(* EN_DVLD = "1'b1" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *)
(* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *)
(* EN_WACK = "1'b1" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *)
(* FIFO_MEMORY_TYPE = "0" *) (* FIFO_MEM_TYPE = "0" *) (* FIFO_READ_DEPTH = "256" *)
(* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "2048" *) (* FIFO_WRITE_DEPTH = "256" *)
(* FULL_RESET_VALUE = "0" *) (* FULL_RST_VAL = "1'b0" *) (* PE_THRESH_ADJ = "8" *)
(* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "8" *)
(* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "7" *) (* PROG_EMPTY_THRESH = "10" *)
(* PROG_FULL_THRESH = "10" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "9" *)
(* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *)
(* READ_DATA_WIDTH = "8" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *)
(* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *)
(* USE_ADV_FEATURES = "1f1f" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *)
(* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "8" *) (* WR_DATA_COUNT_WIDTH = "9" *)
(* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *)
(* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "3" *) (* XPM_MODULE = "TRUE" *)
(* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *)
(* stage1_valid = "2" *) (* stage2_valid = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base
(sleep,
rst,
wr_clk,
wr_en,
din,
full,
full_n,
prog_full,
wr_data_count,
overflow,
wr_rst_busy,
almost_full,
wr_ack,
rd_clk,
rd_en,
dout,
empty,
prog_empty,
rd_data_count,
underflow,
rd_rst_busy,
almost_empty,
data_valid,
injectsbiterr,
injectdbiterr,
sbiterr,
dbiterr);
input sleep;
input rst;
input wr_clk;
input wr_en;
input [7:0]din;
output full;
output full_n;
output prog_full;
output [8:0]wr_data_count;
output overflow;
output wr_rst_busy;
output almost_full;
output wr_ack;
input rd_clk;
input rd_en;
output [7:0]dout;
output empty;
output prog_empty;
output [8:0]rd_data_count;
output underflow;
output rd_rst_busy;
output almost_empty;
output data_valid;
input injectsbiterr;
input injectdbiterr;
output sbiterr;
output dbiterr;
wire \<const0> ;
wire aempty_fwft_i0;
wire almost_empty;
wire almost_full;
wire [7:0]count_value_i;
wire [1:0]curr_fwft_state;
wire data_valid;
wire data_valid_fwft1;
wire [7:0]diff_pntr_pe;
wire [8:4]diff_pntr_pf_q;
wire [8:4]diff_pntr_pf_q0;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ;
wire \gen_cdc_pntr.rpw_gray_reg_n_0 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_0 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_1 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_2 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_3 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_4 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_5 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_6 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_7 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_0 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_1 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_10 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_11 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_12 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_13 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_14 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_15 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_2 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_3 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_4 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_5 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_6 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_7 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_8 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_9 ;
wire \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0 ;
wire \gen_fwft.ram_regout_en ;
wire \gen_fwft.rdpp1_inst_n_0 ;
wire \gen_fwft.rdpp1_inst_n_1 ;
wire \gen_fwft.rdpp1_inst_n_2 ;
wire \gen_fwft.rdpp1_inst_n_3 ;
wire \gen_fwft.rdpp1_inst_n_4 ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ;
wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ;
wire [8:0]\grdc.diff_wr_rd_pntr_rdc ;
wire \grdc.rd_data_count_i0 ;
wire [8:0]\gwdc.diff_wr_rd_pntr1_out ;
wire [1:0]next_fwft_state__0;
wire overflow;
wire overflow_i0;
wire p_1_in;
wire prog_empty;
wire prog_full;
wire ram_empty_i;
wire ram_empty_i0;
wire ram_full_i0;
wire ram_rd_en_i;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire [7:0]rd_pntr_ext;
wire [7:0]rd_pntr_wr;
wire [7:0]rd_pntr_wr_cdc;
wire [8:0]rd_pntr_wr_cdc_dc;
wire rd_rst_busy;
wire rdp_inst_n_11;
wire rdp_inst_n_12;
wire rdp_inst_n_13;
wire rdp_inst_n_14;
wire rdp_inst_n_15;
wire rdp_inst_n_18;
wire rdp_inst_n_27;
wire rdp_inst_n_28;
wire rdp_inst_n_29;
wire rdp_inst_n_30;
wire rdp_inst_n_31;
wire rdp_inst_n_32;
wire rdpp1_inst_n_1;
wire rst;
wire rst_d1;
wire rst_d1_inst_n_1;
wire rst_d1_inst_n_3;
wire sleep;
wire [8:0]src_in_bin00_out;
wire underflow;
wire underflow_i0;
wire wr_ack;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire [8:0]wr_pntr_ext;
wire [8:1]wr_pntr_plus1_pf;
wire wr_pntr_plus1_pf_carry;
wire [7:0]wr_pntr_rd_cdc;
wire [8:0]wr_pntr_rd_cdc_dc;
wire wr_rst_busy;
wire wrpp2_inst_n_0;
wire wrpp2_inst_n_1;
wire wrpp2_inst_n_2;
wire wrpp2_inst_n_3;
wire wrpp2_inst_n_4;
wire wrpp2_inst_n_5;
wire wrpp2_inst_n_6;
wire wrpp2_inst_n_7;
wire wrst_busy;
wire xpm_fifo_rst_inst_n_2;
wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ;
wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ;
wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ;
wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ;
wire [7:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ;
assign dbiterr = \<const0> ;
assign full_n = \<const0> ;
assign sbiterr = \<const0> ;
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'h6899))
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1
(.I0(ram_empty_i),
.I1(curr_fwft_state[0]),
.I2(rd_en),
.I3(curr_fwft_state[1]),
.O(next_fwft_state__0[0]));
LUT3 #(
.INIT(8'h7A))
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1
(.I0(curr_fwft_state[0]),
.I1(rd_en),
.I2(curr_fwft_state[1]),
.O(next_fwft_state__0[1]));
(* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(next_fwft_state__0[0]),
.Q(curr_fwft_state[0]),
.R(rd_rst_busy));
(* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(next_fwft_state__0[1]),
.Q(curr_fwft_state[1]),
.R(rd_rst_busy));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_5 \gaf_wptr_p3.wrpp3_inst
(.Q(count_value_i),
.\count_value_i_reg[6]_0 (full),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
(* DEST_SYNC_FF = "2" *)
(* INIT_SYNC_FF = "1" *)
(* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *)
(* WIDTH = "9" *)
(* XPM_CDC = "GRAY" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1 \gen_cdc_pntr.rd_pntr_cdc_dc_inst
(.dest_clk(wr_clk),
.dest_out_bin(rd_pntr_wr_cdc_dc),
.src_clk(rd_clk),
.src_in_bin({src_in_bin00_out[8:7],rdp_inst_n_11,rdp_inst_n_12,rdp_inst_n_13,rdp_inst_n_14,rdp_inst_n_15,src_in_bin00_out[1:0]}));
(* DEST_SYNC_FF = "2" *)
(* INIT_SYNC_FF = "1" *)
(* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *)
(* WIDTH = "8" *)
(* XPM_CDC = "GRAY" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2 \gen_cdc_pntr.rd_pntr_cdc_inst
(.dest_clk(wr_clk),
.dest_out_bin(rd_pntr_wr_cdc),
.src_clk(rd_clk),
.src_in_bin(rd_pntr_ext));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_6 \gen_cdc_pntr.rpw_gray_reg
(.D(rd_pntr_wr_cdc),
.Q(wr_pntr_plus1_pf),
.almost_full(almost_full),
.\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg (\gen_cdc_pntr.rpw_gray_reg_n_0 ),
.\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_0 (\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_n_0 ),
.\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_1 (rst_d1_inst_n_3),
.\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 (count_value_i),
.\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}),
.\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0 (full),
.ram_full_i0(ram_full_i0),
.\reg_out_i_reg[7]_0 (rd_pntr_wr),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_7 \gen_cdc_pntr.rpw_gray_reg_dc
(.D(rd_pntr_wr_cdc_dc),
.Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }),
.wr_clk(wr_clk),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_8 \gen_cdc_pntr.wpr_gray_reg
(.D(wr_pntr_rd_cdc),
.Q(rd_pntr_ext),
.S({\gen_cdc_pntr.wpr_gray_reg_n_9 ,\gen_cdc_pntr.wpr_gray_reg_n_10 ,\gen_cdc_pntr.wpr_gray_reg_n_11 }),
.\count_value_i_reg[7] (\gen_cdc_pntr.wpr_gray_reg_n_0 ),
.rd_clk(rd_clk),
.\reg_out_i_reg[0]_0 (rd_rst_busy),
.\reg_out_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }),
.\reg_out_i_reg[7]_1 ({\gen_cdc_pntr.wpr_gray_reg_n_12 ,\gen_cdc_pntr.wpr_gray_reg_n_13 ,\gen_cdc_pntr.wpr_gray_reg_n_14 ,\gen_cdc_pntr.wpr_gray_reg_n_15 }));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_9 \gen_cdc_pntr.wpr_gray_reg_dc
(.D(\grdc.diff_wr_rd_pntr_rdc ),
.DI(\gen_fwft.rdpp1_inst_n_2 ),
.Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 }),
.S({rdp_inst_n_27,rdp_inst_n_28,\gen_fwft.rdpp1_inst_n_0 ,\gen_fwft.rdpp1_inst_n_1 }),
.\grdc.rd_data_count_i_reg[3] (\gen_fwft.rdpp1_inst_n_3 ),
.\grdc.rd_data_count_i_reg[7] (rd_pntr_ext[6:1]),
.\grdc.rd_data_count_i_reg[7]_0 ({rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31,rdp_inst_n_32}),
.\grdc.rd_data_count_i_reg[8] (rdp_inst_n_18),
.rd_clk(rd_clk),
.\reg_out_i_reg[8]_0 (rd_rst_busy),
.\reg_out_i_reg[8]_1 (wr_pntr_rd_cdc_dc));
(* DEST_SYNC_FF = "4" *)
(* INIT_SYNC_FF = "1" *)
(* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *)
(* WIDTH = "9" *)
(* XPM_CDC = "GRAY" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1 \gen_cdc_pntr.wr_pntr_cdc_dc_inst
(.dest_clk(rd_clk),
.dest_out_bin(wr_pntr_rd_cdc_dc),
.src_clk(wr_clk),
.src_in_bin(wr_pntr_ext));
(* DEST_SYNC_FF = "2" *)
(* INIT_SYNC_FF = "1" *)
(* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *)
(* WIDTH = "8" *)
(* XPM_CDC = "GRAY" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1 \gen_cdc_pntr.wr_pntr_cdc_inst
(.dest_clk(rd_clk),
.dest_out_bin(wr_pntr_rd_cdc),
.src_clk(wr_clk),
.src_in_bin(wr_pntr_ext[7:0]));
LUT4 #(
.INIT(16'hBB80))
\gen_fwft.empty_fwft_i_i_1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(rd_en),
.I3(empty),
.O(data_valid_fwft1));
FDSE #(
.INIT(1'b1))
\gen_fwft.empty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(data_valid_fwft1),
.Q(empty),
.S(rd_rst_busy));
LUT5 #(
.INIT(32'hFBBB2000))
\gen_fwft.gae_fwft.aempty_fwft_i_i_1
(.I0(ram_empty_i),
.I1(curr_fwft_state[0]),
.I2(rd_en),
.I3(curr_fwft_state[1]),
.I4(almost_empty),
.O(aempty_fwft_i0));
FDSE #(
.INIT(1'b1))
\gen_fwft.gae_fwft.aempty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(aempty_fwft_i0),
.Q(almost_empty),
.S(rd_rst_busy));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'h15F5))
\gen_fwft.gdvld_fwft.data_valid_fwft_i_1
(.I0(empty),
.I1(rd_en),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.O(\gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_fwft.gdvld_fwft.data_valid_fwft_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0 ),
.Q(data_valid),
.R(rd_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_10 \gen_fwft.rdpp1_inst
(.DI(\gen_fwft.rdpp1_inst_n_2 ),
.Q(rd_pntr_ext[1:0]),
.S({\gen_fwft.rdpp1_inst_n_0 ,\gen_fwft.rdpp1_inst_n_1 }),
.\count_value_i_reg[0]_0 (\gen_fwft.rdpp1_inst_n_4 ),
.\count_value_i_reg[1]_0 (\gen_fwft.rdpp1_inst_n_3 ),
.\count_value_i_reg[1]_1 (rd_rst_busy),
.\count_value_i_reg[1]_2 (curr_fwft_state),
.\grdc.rd_data_count_i_reg[3] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 }),
.ram_empty_i(ram_empty_i),
.rd_clk(rd_clk),
.rd_en(rd_en));
LUT2 #(
.INIT(4'h1))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2
(.I0(rst),
.I1(full),
.O(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_cdc_pntr.rpw_gray_reg_n_0 ),
.Q(almost_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[0]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[1]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[2]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[3]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[4]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[5]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[6]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[7]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ),
.R(rd_rst_busy));
LUT4 #(
.INIT(16'h88B8))
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1
(.I0(prog_empty),
.I1(empty),
.I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ),
.I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ),
.O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ));
LUT4 #(
.INIT(16'h01FF))
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2
(.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ),
.I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ),
.I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ),
.O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3
(.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ),
.I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ),
.I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ),
.O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ));
FDSE #(
.INIT(1'b1))
\gen_pf_ic_rc.gpe_ic.prog_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ),
.Q(prog_empty),
.S(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[4]),
.Q(diff_pntr_pf_q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[5]),
.Q(diff_pntr_pf_q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[6]),
.Q(diff_pntr_pf_q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[7]),
.Q(diff_pntr_pf_q[7]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[8]),
.Q(diff_pntr_pf_q[8]),
.R(wrst_busy));
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2
(.I0(diff_pntr_pf_q[5]),
.I1(diff_pntr_pf_q[8]),
.I2(diff_pntr_pf_q[4]),
.I3(diff_pntr_pf_q[6]),
.I4(diff_pntr_pf_q[7]),
.O(p_1_in));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1_inst_n_1),
.Q(prog_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i0),
.Q(full),
.R(wrst_busy));
FDSE #(
.INIT(1'b1))
\gen_pf_ic_rc.ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(ram_empty_i0),
.Q(ram_empty_i),
.S(rd_rst_busy));
(* ADDR_WIDTH_A = "8" *)
(* ADDR_WIDTH_B = "8" *)
(* AUTO_SLEEP_TIME = "0" *)
(* BYTE_WRITE_WIDTH_A = "8" *)
(* BYTE_WRITE_WIDTH_B = "8" *)
(* CASCADE_HEIGHT = "0" *)
(* CLOCKING_MODE = "1" *)
(* ECC_MODE = "0" *)
(* IGNORE_INIT_SYNTH = "0" *)
(* KEEP_HIERARCHY = "soft" *)
(* MAX_NUM_CHAR = "0" *)
(* \MEM.ADDRESS_SPACE *)
(* \MEM.ADDRESS_SPACE_BEGIN = "0" *)
(* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *)
(* \MEM.ADDRESS_SPACE_DATA_MSB = "7" *)
(* \MEM.ADDRESS_SPACE_END = "1023" *)
(* \MEM.CORE_MEMORY_WIDTH = "8" *)
(* MEMORY_INIT_FILE = "none" *)
(* MEMORY_INIT_PARAM = "" *)
(* MEMORY_OPTIMIZATION = "true" *)
(* MEMORY_PRIMITIVE = "0" *)
(* MEMORY_SIZE = "2048" *)
(* MEMORY_TYPE = "1" *)
(* MESSAGE_CONTROL = "0" *)
(* NUM_CHAR_LOC = "0" *)
(* P_ECC_MODE = "no_ecc" *)
(* P_ENABLE_BYTE_WRITE_A = "0" *)
(* P_ENABLE_BYTE_WRITE_B = "0" *)
(* P_MAX_DEPTH_DATA = "256" *)
(* P_MEMORY_OPT = "yes" *)
(* P_MEMORY_PRIMITIVE = "auto" *)
(* P_MIN_WIDTH_DATA = "8" *)
(* P_MIN_WIDTH_DATA_A = "8" *)
(* P_MIN_WIDTH_DATA_B = "8" *)
(* P_MIN_WIDTH_DATA_ECC = "8" *)
(* P_MIN_WIDTH_DATA_LDW = "4" *)
(* P_MIN_WIDTH_DATA_SHFT = "8" *)
(* P_NUM_COLS_WRITE_A = "1" *)
(* P_NUM_COLS_WRITE_B = "1" *)
(* P_NUM_ROWS_READ_A = "1" *)
(* P_NUM_ROWS_READ_B = "1" *)
(* P_NUM_ROWS_WRITE_A = "1" *)
(* P_NUM_ROWS_WRITE_B = "1" *)
(* P_SDP_WRITE_MODE = "yes" *)
(* P_WIDTH_ADDR_LSB_READ_A = "0" *)
(* P_WIDTH_ADDR_LSB_READ_B = "0" *)
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *)
(* P_WIDTH_ADDR_LSB_WRITE_B = "0" *)
(* P_WIDTH_ADDR_READ_A = "8" *)
(* P_WIDTH_ADDR_READ_B = "8" *)
(* P_WIDTH_ADDR_WRITE_A = "8" *)
(* P_WIDTH_ADDR_WRITE_B = "8" *)
(* P_WIDTH_COL_WRITE_A = "8" *)
(* P_WIDTH_COL_WRITE_B = "8" *)
(* READ_DATA_WIDTH_A = "8" *)
(* READ_DATA_WIDTH_B = "8" *)
(* READ_LATENCY_A = "2" *)
(* READ_LATENCY_B = "2" *)
(* READ_RESET_VALUE_A = "0" *)
(* READ_RESET_VALUE_B = "0" *)
(* RST_MODE_A = "SYNC" *)
(* RST_MODE_B = "SYNC" *)
(* SIM_ASSERT_CHK = "0" *)
(* USE_EMBEDDED_CONSTRAINT = "0" *)
(* USE_MEM_INIT = "0" *)
(* USE_MEM_INIT_MMI = "0" *)
(* VERSION = "0" *)
(* WAKEUP_TIME = "0" *)
(* WRITE_DATA_WIDTH_A = "8" *)
(* WRITE_DATA_WIDTH_B = "8" *)
(* WRITE_MODE_A = "2" *)
(* WRITE_MODE_B = "2" *)
(* WRITE_PROTECT = "1" *)
(* XPM_MODULE = "TRUE" *)
(* rsta_loop_iter = "8" *)
(* rstb_loop_iter = "8" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1 \gen_sdpram.xpm_memory_base_inst
(.addra(wr_pntr_ext[7:0]),
.addrb(rd_pntr_ext),
.clka(wr_clk),
.clkb(rd_clk),
.dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ),
.dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ),
.dina(din),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [7:0]),
.doutb(dout),
.ena(wr_pntr_plus1_pf_carry),
.enb(ram_rd_en_i),
.injectdbiterra(1'b0),
.injectdbiterrb(1'b0),
.injectsbiterra(1'b0),
.injectsbiterrb(1'b0),
.regcea(1'b0),
.regceb(\gen_fwft.ram_regout_en ),
.rsta(1'b0),
.rstb(rd_rst_busy),
.sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ),
.sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ),
.sleep(sleep),
.wea(1'b0),
.web(1'b0));
LUT3 #(
.INIT(8'h62))
\gen_sdpram.xpm_memory_base_inst_i_3
(.I0(curr_fwft_state[0]),
.I1(curr_fwft_state[1]),
.I2(rd_en),
.O(\gen_fwft.ram_regout_en ));
FDRE #(
.INIT(1'b0))
\gof.overflow_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(overflow_i0),
.Q(overflow),
.R(1'b0));
FDRE \grdc.rd_data_count_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [0]),
.Q(rd_data_count[0]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [1]),
.Q(rd_data_count[1]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [2]),
.Q(rd_data_count[2]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [3]),
.Q(rd_data_count[3]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [4]),
.Q(rd_data_count[4]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [5]),
.Q(rd_data_count[5]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [6]),
.Q(rd_data_count[6]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [7]),
.Q(rd_data_count[7]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [8]),
.Q(rd_data_count[8]),
.R(\grdc.rd_data_count_i0 ));
FDRE #(
.INIT(1'b0))
\guf.underflow_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(underflow_i0),
.Q(underflow),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gwack.wr_ack_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(xpm_fifo_rst_inst_n_2),
.Q(wr_ack),
.R(1'b0));
FDRE \gwdc.wr_data_count_i_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [0]),
.Q(wr_data_count[0]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [1]),
.Q(wr_data_count[1]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [2]),
.Q(wr_data_count[2]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [3]),
.Q(wr_data_count[3]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [4]),
.Q(wr_data_count[4]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [5]),
.Q(wr_data_count[5]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [6]),
.Q(wr_data_count[6]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [7]),
.Q(wr_data_count[7]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [8]),
.Q(wr_data_count[8]),
.R(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_11 rdp_inst
(.D(diff_pntr_pe),
.E(ram_rd_en_i),
.Q(rd_pntr_ext),
.S({\gen_cdc_pntr.wpr_gray_reg_n_9 ,\gen_cdc_pntr.wpr_gray_reg_n_10 ,\gen_cdc_pntr.wpr_gray_reg_n_11 }),
.\count_value_i_reg[2]_0 ({rdp_inst_n_27,rdp_inst_n_28}),
.\count_value_i_reg[4]_0 (rdpp1_inst_n_1),
.\count_value_i_reg[6]_0 ({rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31,rdp_inst_n_32}),
.\count_value_i_reg[7]_0 (rdp_inst_n_18),
.\count_value_i_reg[8]_0 (curr_fwft_state),
.\count_value_i_reg[8]_1 (rd_rst_busy),
.\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (\gen_cdc_pntr.wpr_gray_reg_n_8 ),
.\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ({\gen_cdc_pntr.wpr_gray_reg_n_12 ,\gen_cdc_pntr.wpr_gray_reg_n_13 ,\gen_cdc_pntr.wpr_gray_reg_n_14 ,\gen_cdc_pntr.wpr_gray_reg_n_15 }),
.\grdc.rd_data_count_i_reg[3] (\gen_fwft.rdpp1_inst_n_3 ),
.\grdc.rd_data_count_i_reg[8] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 }),
.ram_empty_i(ram_empty_i),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\src_gray_ff_reg[0] (\gen_fwft.rdpp1_inst_n_4 ),
.src_in_bin({src_in_bin00_out[8:7],rdp_inst_n_11,rdp_inst_n_12,rdp_inst_n_13,rdp_inst_n_14,rdp_inst_n_15,src_in_bin00_out[1:0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12 rdpp1_inst
(.E(ram_rd_en_i),
.Q(curr_fwft_state),
.\count_value_i_reg[0]_0 (rd_rst_busy),
.\gen_pf_ic_rc.ram_empty_i_reg (rdpp1_inst_n_1),
.\gen_pf_ic_rc.ram_empty_i_reg_0 (\gen_cdc_pntr.wpr_gray_reg_n_0 ),
.\gen_pf_ic_rc.ram_empty_i_reg_1 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }),
.ram_empty_i(ram_empty_i),
.ram_empty_i0(ram_empty_i0),
.rd_clk(rd_clk),
.rd_en(rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_13 rst_d1_inst
(.d_out_reg_0(rst_d1_inst_n_3),
.\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (full),
.\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg (rst_d1_inst_n_1),
.overflow_i0(overflow_i0),
.p_1_in(p_1_in),
.prog_full(prog_full),
.rst(rst),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_14 wrp_inst
(.D(\gwdc.diff_wr_rd_pntr1_out ),
.Q(wr_pntr_ext),
.\count_value_i_reg[6]_0 (full),
.\gwdc.wr_data_count_i_reg[8] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_15 wrpp1_inst
(.D(diff_pntr_pf_q0),
.Q(wr_pntr_plus1_pf),
.\count_value_i_reg[6]_0 (full),
.\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rd_pntr_wr),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_16 wrpp2_inst
(.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}),
.\count_value_i_reg[6]_0 (full),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1 xpm_fifo_rst_inst
(.Q(curr_fwft_state),
.SR(\grdc.rd_data_count_i0 ),
.d_out_reg(xpm_fifo_rst_inst_n_2),
.\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy),
.\guf.underflow_i_reg (empty),
.\gwack.wr_ack_i_reg (full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.rst_d1(rst_d1),
.underflow_i0(underflow_i0),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wr_rst_busy(wr_rst_busy),
.wrst_busy(wrst_busy));
endmodule
(* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "2" *) (* COMMON_CLOCK = "0" *)
(* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *)
(* EN_ADV_FEATURE = "16'b0001111100011111" *) (* EN_AE = "1'b1" *) (* EN_AF = "1'b1" *)
(* EN_DVLD = "1'b1" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *)
(* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *)
(* EN_WACK = "1'b1" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *)
(* FIFO_MEMORY_TYPE = "0" *) (* FIFO_MEM_TYPE = "0" *) (* FIFO_READ_DEPTH = "256" *)
(* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "2048" *) (* FIFO_WRITE_DEPTH = "256" *)
(* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *)
(* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *)
(* PF_THRESH_ADJ = "8" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "7" *)
(* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "10" *) (* RD_DATA_COUNT_WIDTH = "9" *)
(* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *)
(* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "8" *) (* READ_MODE = "1" *)
(* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *)
(* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "1F1F" *) (* VERSION = "0" *)
(* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "8" *)
(* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *)
(* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "3" *)
(* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *)
(* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0
(sleep,
rst,
wr_clk,
wr_en,
din,
full,
full_n,
prog_full,
wr_data_count,
overflow,
wr_rst_busy,
almost_full,
wr_ack,
rd_clk,
rd_en,
dout,
empty,
prog_empty,
rd_data_count,
underflow,
rd_rst_busy,
almost_empty,
data_valid,
injectsbiterr,
injectdbiterr,
sbiterr,
dbiterr);
input sleep;
input rst;
input wr_clk;
input wr_en;
input [7:0]din;
output full;
output full_n;
output prog_full;
output [8:0]wr_data_count;
output overflow;
output wr_rst_busy;
output almost_full;
output wr_ack;
input rd_clk;
input rd_en;
output [7:0]dout;
output empty;
output prog_empty;
output [8:0]rd_data_count;
output underflow;
output rd_rst_busy;
output almost_empty;
output data_valid;
input injectsbiterr;
input injectdbiterr;
output sbiterr;
output dbiterr;
wire \<const0> ;
wire aempty_fwft_i0;
wire almost_empty;
wire almost_full;
wire clr_full;
wire [7:0]count_value_i;
wire [1:0]curr_fwft_state;
wire data_valid;
wire data_valid_fwft1;
wire [7:0]diff_pntr_pe;
wire [8:4]diff_pntr_pf_q;
wire [8:4]diff_pntr_pf_q0;
wire [7:0]din;
wire [7:0]dout;
wire empty;
wire full;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ;
wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ;
wire \gen_cdc_pntr.rpw_gray_reg_n_0 ;
wire \gen_cdc_pntr.rpw_gray_reg_n_9 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_17 ;
wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_1 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_2 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_3 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_4 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_5 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_6 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_7 ;
wire \gen_cdc_pntr.wpr_gray_reg_n_8 ;
wire \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0 ;
wire \gen_fwft.ram_regout_en ;
wire \gen_fwft.rdpp1_inst_n_1 ;
wire \gen_fwft.rdpp1_inst_n_2 ;
wire \gen_fwft.rdpp1_inst_n_3 ;
wire \gen_fwft.rdpp1_inst_n_4 ;
wire \gen_fwft.rdpp1_inst_n_5 ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ;
wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ;
wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ;
wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ;
wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ;
wire [8:0]\grdc.diff_wr_rd_pntr_rdc ;
wire \grdc.rd_data_count_i0 ;
wire [8:0]\gwdc.diff_wr_rd_pntr1_out ;
wire [1:0]next_fwft_state__0;
wire overflow;
wire overflow_i0;
wire prog_empty;
wire prog_full;
wire ram_empty_i;
wire ram_empty_i0;
wire rd_clk;
wire [8:0]rd_data_count;
wire rd_en;
wire [7:0]rd_pntr_ext;
wire [7:0]rd_pntr_wr;
wire [7:0]rd_pntr_wr_cdc;
wire [8:0]rd_pntr_wr_cdc_dc;
wire rd_rst_busy;
wire rdp_inst_n_10;
wire rdp_inst_n_19;
wire rdp_inst_n_20;
wire rdp_inst_n_21;
wire rdp_inst_n_22;
wire rdp_inst_n_23;
wire rdp_inst_n_24;
wire rdp_inst_n_25;
wire rdp_inst_n_26;
wire rdp_inst_n_27;
wire rdp_inst_n_28;
wire rdp_inst_n_29;
wire rdp_inst_n_30;
wire rdp_inst_n_31;
wire rdp_inst_n_8;
wire rdp_inst_n_9;
wire rdpp1_inst_n_0;
wire rdpp1_inst_n_1;
wire rdpp1_inst_n_2;
wire rdpp1_inst_n_3;
wire rdpp1_inst_n_4;
wire rdpp1_inst_n_5;
wire rdpp1_inst_n_6;
wire rdpp1_inst_n_7;
wire rst;
wire rst_d1;
wire rst_d1_inst_n_1;
wire sleep;
wire [1:1]src_in_bin00_out;
wire underflow;
wire underflow_i0;
wire wr_ack;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire [8:0]wr_pntr_ext;
wire [8:1]wr_pntr_plus1_pf;
wire wr_pntr_plus1_pf_carry;
wire [7:0]wr_pntr_rd_cdc;
wire [8:0]wr_pntr_rd_cdc_dc;
wire wr_rst_busy;
wire wrpp2_inst_n_0;
wire wrpp2_inst_n_1;
wire wrpp2_inst_n_2;
wire wrpp2_inst_n_3;
wire wrpp2_inst_n_4;
wire wrpp2_inst_n_5;
wire wrpp2_inst_n_6;
wire wrpp2_inst_n_7;
wire wrst_busy;
wire xpm_fifo_rst_inst_n_2;
wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ;
wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ;
wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ;
wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ;
wire [7:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ;
assign dbiterr = \<const0> ;
assign full_n = \<const0> ;
assign sbiterr = \<const0> ;
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h6A85))
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1
(.I0(curr_fwft_state[0]),
.I1(rd_en),
.I2(curr_fwft_state[1]),
.I3(ram_empty_i),
.O(next_fwft_state__0[0]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h3FF0))
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1
(.I0(ram_empty_i),
.I1(rd_en),
.I2(curr_fwft_state[1]),
.I3(curr_fwft_state[0]),
.O(next_fwft_state__0[1]));
(* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(next_fwft_state__0[0]),
.Q(curr_fwft_state[0]),
.R(rd_rst_busy));
(* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(next_fwft_state__0[1]),
.Q(curr_fwft_state[1]),
.R(rd_rst_busy));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn \gaf_wptr_p3.wrpp3_inst
(.Q(count_value_i),
.\count_value_i_reg[6]_0 (full),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
(* DEST_SYNC_FF = "2" *)
(* INIT_SYNC_FF = "1" *)
(* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *)
(* WIDTH = "9" *)
(* XPM_CDC = "GRAY" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1 \gen_cdc_pntr.rd_pntr_cdc_dc_inst
(.dest_clk(wr_clk),
.dest_out_bin(rd_pntr_wr_cdc_dc),
.src_clk(rd_clk),
.src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,src_in_bin00_out,rdp_inst_n_31}));
(* DEST_SYNC_FF = "2" *)
(* INIT_SYNC_FF = "1" *)
(* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *)
(* WIDTH = "8" *)
(* XPM_CDC = "GRAY" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray \gen_cdc_pntr.rd_pntr_cdc_inst
(.dest_clk(wr_clk),
.dest_out_bin(rd_pntr_wr_cdc),
.src_clk(rd_clk),
.src_in_bin(rd_pntr_ext));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec \gen_cdc_pntr.rpw_gray_reg
(.D(rd_pntr_wr_cdc),
.Q(wr_pntr_plus1_pf),
.almost_full(almost_full),
.clr_full(clr_full),
.d_out_reg(\gen_cdc_pntr.rpw_gray_reg_n_9 ),
.\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 (count_value_i),
.\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg (full),
.\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (\gen_cdc_pntr.rpw_gray_reg_n_0 ),
.\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}),
.\reg_out_i_reg[7]_0 (rd_pntr_wr),
.rst(rst),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0 \gen_cdc_pntr.rpw_gray_reg_dc
(.D(rd_pntr_wr_cdc_dc),
.Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }),
.wr_clk(wr_clk),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_1 \gen_cdc_pntr.wpr_gray_reg
(.D(wr_pntr_rd_cdc),
.Q(curr_fwft_state),
.\gen_pf_ic_rc.ram_empty_i_reg (rd_pntr_ext),
.\gen_pf_ic_rc.ram_empty_i_reg_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}),
.ram_empty_i(ram_empty_i),
.ram_empty_i0(ram_empty_i0),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\reg_out_i_reg[0]_0 (rd_rst_busy),
.\reg_out_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_2 \gen_cdc_pntr.wpr_gray_reg_dc
(.D(\grdc.diff_wr_rd_pntr_rdc ),
.DI({rdp_inst_n_9,\gen_fwft.rdpp1_inst_n_5 }),
.Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_17 }),
.S({rdp_inst_n_19,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }),
.\grdc.rd_data_count_i_reg[3] (\gen_fwft.rdpp1_inst_n_2 ),
.\grdc.rd_data_count_i_reg[7] ({rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23}),
.\grdc.rd_data_count_i_reg[7]_0 (rd_pntr_ext[6:1]),
.\grdc.rd_data_count_i_reg[8] (rdp_inst_n_10),
.rd_clk(rd_clk),
.\reg_out_i_reg[8]_0 (rd_rst_busy),
.\reg_out_i_reg[8]_1 (wr_pntr_rd_cdc_dc));
(* DEST_SYNC_FF = "4" *)
(* INIT_SYNC_FF = "1" *)
(* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *)
(* WIDTH = "9" *)
(* XPM_CDC = "GRAY" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0 \gen_cdc_pntr.wr_pntr_cdc_dc_inst
(.dest_clk(rd_clk),
.dest_out_bin(wr_pntr_rd_cdc_dc),
.src_clk(wr_clk),
.src_in_bin(wr_pntr_ext));
(* DEST_SYNC_FF = "2" *)
(* INIT_SYNC_FF = "1" *)
(* REG_OUTPUT = "0" *)
(* SIM_ASSERT_CHK = "0" *)
(* SIM_LOSSLESS_GRAY_CHK = "0" *)
(* VERSION = "0" *)
(* WIDTH = "8" *)
(* XPM_CDC = "GRAY" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3 \gen_cdc_pntr.wr_pntr_cdc_inst
(.dest_clk(rd_clk),
.dest_out_bin(wr_pntr_rd_cdc),
.src_clk(wr_clk),
.src_in_bin(wr_pntr_ext[7:0]));
LUT4 #(
.INIT(16'hF380))
\gen_fwft.empty_fwft_i_i_1
(.I0(rd_en),
.I1(curr_fwft_state[0]),
.I2(curr_fwft_state[1]),
.I3(empty),
.O(data_valid_fwft1));
FDSE #(
.INIT(1'b1))
\gen_fwft.empty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(data_valid_fwft1),
.Q(empty),
.S(rd_rst_busy));
LUT5 #(
.INIT(32'hFDDD4000))
\gen_fwft.gae_fwft.aempty_fwft_i_i_1
(.I0(curr_fwft_state[0]),
.I1(ram_empty_i),
.I2(curr_fwft_state[1]),
.I3(rd_en),
.I4(almost_empty),
.O(aempty_fwft_i0));
FDSE #(
.INIT(1'b1))
\gen_fwft.gae_fwft.aempty_fwft_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(aempty_fwft_i0),
.Q(almost_empty),
.S(rd_rst_busy));
LUT4 #(
.INIT(16'h3575))
\gen_fwft.gdvld_fwft.data_valid_fwft_i_1
(.I0(empty),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(rd_en),
.O(\gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_fwft.gdvld_fwft.data_valid_fwft_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0 ),
.Q(data_valid),
.R(rd_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1 \gen_fwft.rdpp1_inst
(.DI(\gen_fwft.rdpp1_inst_n_5 ),
.Q(rd_pntr_ext[1:0]),
.S({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }),
.\count_value_i_reg[0]_0 (\gen_fwft.rdpp1_inst_n_1 ),
.\count_value_i_reg[1]_0 (\gen_fwft.rdpp1_inst_n_2 ),
.\count_value_i_reg[1]_1 (curr_fwft_state),
.\count_value_i_reg[1]_2 (rd_rst_busy),
.\grdc.rd_data_count_i_reg[3] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_17 }),
.ram_empty_i(ram_empty_i),
.rd_clk(rd_clk),
.rd_en(rd_en),
.src_in_bin(src_in_bin00_out));
FDSE #(
.INIT(1'b1))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_cdc_pntr.rpw_gray_reg_n_0 ),
.Q(almost_full),
.S(wrst_busy));
FDSE #(
.INIT(1'b1))
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_cdc_pntr.rpw_gray_reg_n_9 ),
.Q(full),
.S(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[0]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[1]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[2]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[3]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[4]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[5]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[6]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ),
.R(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]
(.C(rd_clk),
.CE(1'b1),
.D(diff_pntr_pe[7]),
.Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ),
.R(rd_rst_busy));
LUT4 #(
.INIT(16'h88B8))
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1
(.I0(prog_empty),
.I1(empty),
.I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ),
.I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ),
.O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ));
LUT4 #(
.INIT(16'h01FF))
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2
(.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ),
.I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ),
.I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ),
.O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3
(.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ),
.I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ),
.I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ),
.I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ),
.O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ));
FDSE #(
.INIT(1'b1))
\gen_pf_ic_rc.gpe_ic.prog_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ),
.Q(prog_empty),
.S(rd_rst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[4]),
.Q(diff_pntr_pf_q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[5]),
.Q(diff_pntr_pf_q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[6]),
.Q(diff_pntr_pf_q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[7]),
.Q(diff_pntr_pf_q[7]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]
(.C(wr_clk),
.CE(1'b1),
.D(diff_pntr_pf_q0[8]),
.Q(diff_pntr_pf_q[8]),
.R(wrst_busy));
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2
(.I0(diff_pntr_pf_q[5]),
.I1(diff_pntr_pf_q[8]),
.I2(diff_pntr_pf_q[4]),
.I3(diff_pntr_pf_q[6]),
.I4(diff_pntr_pf_q[7]),
.O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ));
FDSE #(
.INIT(1'b1))
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1_inst_n_1),
.Q(prog_full),
.S(wrst_busy));
FDSE #(
.INIT(1'b1))
\gen_pf_ic_rc.ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(ram_empty_i0),
.Q(ram_empty_i),
.S(rd_rst_busy));
(* ADDR_WIDTH_A = "8" *)
(* ADDR_WIDTH_B = "8" *)
(* AUTO_SLEEP_TIME = "0" *)
(* BYTE_WRITE_WIDTH_A = "8" *)
(* BYTE_WRITE_WIDTH_B = "8" *)
(* CASCADE_HEIGHT = "0" *)
(* CLOCKING_MODE = "1" *)
(* ECC_MODE = "0" *)
(* IGNORE_INIT_SYNTH = "0" *)
(* KEEP_HIERARCHY = "soft" *)
(* MAX_NUM_CHAR = "0" *)
(* \MEM.ADDRESS_SPACE *)
(* \MEM.ADDRESS_SPACE_BEGIN = "0" *)
(* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *)
(* \MEM.ADDRESS_SPACE_DATA_MSB = "7" *)
(* \MEM.ADDRESS_SPACE_END = "1023" *)
(* \MEM.CORE_MEMORY_WIDTH = "8" *)
(* MEMORY_INIT_FILE = "none" *)
(* MEMORY_INIT_PARAM = "" *)
(* MEMORY_OPTIMIZATION = "true" *)
(* MEMORY_PRIMITIVE = "0" *)
(* MEMORY_SIZE = "2048" *)
(* MEMORY_TYPE = "1" *)
(* MESSAGE_CONTROL = "0" *)
(* NUM_CHAR_LOC = "0" *)
(* P_ECC_MODE = "no_ecc" *)
(* P_ENABLE_BYTE_WRITE_A = "0" *)
(* P_ENABLE_BYTE_WRITE_B = "0" *)
(* P_MAX_DEPTH_DATA = "256" *)
(* P_MEMORY_OPT = "yes" *)
(* P_MEMORY_PRIMITIVE = "auto" *)
(* P_MIN_WIDTH_DATA = "8" *)
(* P_MIN_WIDTH_DATA_A = "8" *)
(* P_MIN_WIDTH_DATA_B = "8" *)
(* P_MIN_WIDTH_DATA_ECC = "8" *)
(* P_MIN_WIDTH_DATA_LDW = "4" *)
(* P_MIN_WIDTH_DATA_SHFT = "8" *)
(* P_NUM_COLS_WRITE_A = "1" *)
(* P_NUM_COLS_WRITE_B = "1" *)
(* P_NUM_ROWS_READ_A = "1" *)
(* P_NUM_ROWS_READ_B = "1" *)
(* P_NUM_ROWS_WRITE_A = "1" *)
(* P_NUM_ROWS_WRITE_B = "1" *)
(* P_SDP_WRITE_MODE = "yes" *)
(* P_WIDTH_ADDR_LSB_READ_A = "0" *)
(* P_WIDTH_ADDR_LSB_READ_B = "0" *)
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *)
(* P_WIDTH_ADDR_LSB_WRITE_B = "0" *)
(* P_WIDTH_ADDR_READ_A = "8" *)
(* P_WIDTH_ADDR_READ_B = "8" *)
(* P_WIDTH_ADDR_WRITE_A = "8" *)
(* P_WIDTH_ADDR_WRITE_B = "8" *)
(* P_WIDTH_COL_WRITE_A = "8" *)
(* P_WIDTH_COL_WRITE_B = "8" *)
(* READ_DATA_WIDTH_A = "8" *)
(* READ_DATA_WIDTH_B = "8" *)
(* READ_LATENCY_A = "2" *)
(* READ_LATENCY_B = "2" *)
(* READ_RESET_VALUE_A = "0" *)
(* READ_RESET_VALUE_B = "0" *)
(* RST_MODE_A = "SYNC" *)
(* RST_MODE_B = "SYNC" *)
(* SIM_ASSERT_CHK = "0" *)
(* USE_EMBEDDED_CONSTRAINT = "0" *)
(* USE_MEM_INIT = "0" *)
(* USE_MEM_INIT_MMI = "0" *)
(* VERSION = "0" *)
(* WAKEUP_TIME = "0" *)
(* WRITE_DATA_WIDTH_A = "8" *)
(* WRITE_DATA_WIDTH_B = "8" *)
(* WRITE_MODE_A = "2" *)
(* WRITE_MODE_B = "2" *)
(* WRITE_PROTECT = "1" *)
(* XPM_MODULE = "TRUE" *)
(* rsta_loop_iter = "8" *)
(* rstb_loop_iter = "8" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base \gen_sdpram.xpm_memory_base_inst
(.addra(wr_pntr_ext[7:0]),
.addrb(rd_pntr_ext),
.clka(wr_clk),
.clkb(rd_clk),
.dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ),
.dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ),
.dina(din),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [7:0]),
.doutb(dout),
.ena(wr_pntr_plus1_pf_carry),
.enb(rdp_inst_n_8),
.injectdbiterra(1'b0),
.injectdbiterrb(1'b0),
.injectsbiterra(1'b0),
.injectsbiterrb(1'b0),
.regcea(1'b0),
.regceb(\gen_fwft.ram_regout_en ),
.rsta(1'b0),
.rstb(rd_rst_busy),
.sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ),
.sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ),
.sleep(sleep),
.wea(1'b0),
.web(1'b0));
LUT3 #(
.INIT(8'h62))
\gen_sdpram.xpm_memory_base_inst_i_3
(.I0(curr_fwft_state[0]),
.I1(curr_fwft_state[1]),
.I2(rd_en),
.O(\gen_fwft.ram_regout_en ));
FDRE #(
.INIT(1'b0))
\gof.overflow_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(overflow_i0),
.Q(overflow),
.R(1'b0));
FDRE \grdc.rd_data_count_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [0]),
.Q(rd_data_count[0]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [1]),
.Q(rd_data_count[1]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [2]),
.Q(rd_data_count[2]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [3]),
.Q(rd_data_count[3]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [4]),
.Q(rd_data_count[4]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [5]),
.Q(rd_data_count[5]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [6]),
.Q(rd_data_count[6]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [7]),
.Q(rd_data_count[7]),
.R(\grdc.rd_data_count_i0 ));
FDRE \grdc.rd_data_count_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.D(\grdc.diff_wr_rd_pntr_rdc [8]),
.Q(rd_data_count[8]),
.R(\grdc.rd_data_count_i0 ));
FDRE #(
.INIT(1'b0))
\guf.underflow_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(underflow_i0),
.Q(underflow),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gwack.wr_ack_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(xpm_fifo_rst_inst_n_2),
.Q(wr_ack),
.R(1'b0));
FDRE \gwdc.wr_data_count_i_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [0]),
.Q(wr_data_count[0]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [1]),
.Q(wr_data_count[1]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [2]),
.Q(wr_data_count[2]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [3]),
.Q(wr_data_count[3]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [4]),
.Q(wr_data_count[4]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [5]),
.Q(wr_data_count[5]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [6]),
.Q(wr_data_count[6]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [7]),
.Q(wr_data_count[7]),
.R(wrst_busy));
FDRE \gwdc.wr_data_count_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.D(\gwdc.diff_wr_rd_pntr1_out [8]),
.Q(wr_data_count[8]),
.R(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2 rdp_inst
(.D(diff_pntr_pe),
.DI(rdp_inst_n_9),
.Q(rd_pntr_ext),
.S(rdp_inst_n_19),
.\count_value_i_reg[0]_0 (curr_fwft_state),
.\count_value_i_reg[6]_0 ({rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23}),
.\count_value_i_reg[7]_0 (rdp_inst_n_10),
.\count_value_i_reg[8]_0 (rd_rst_busy),
.enb(rdp_inst_n_8),
.\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }),
.\grdc.rd_data_count_i_reg[3] (\gen_fwft.rdpp1_inst_n_2 ),
.\grdc.rd_data_count_i_reg[8] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }),
.ram_empty_i(ram_empty_i),
.rd_clk(rd_clk),
.rd_en(rd_en),
.\src_gray_ff_reg[2] (\gen_fwft.rdpp1_inst_n_1 ),
.src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3 rdpp1_inst
(.E(rdp_inst_n_8),
.Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}),
.\count_value_i_reg[0]_0 (rd_rst_busy),
.\count_value_i_reg[1]_0 (curr_fwft_state),
.ram_empty_i(ram_empty_i),
.rd_clk(rd_clk),
.rd_en(rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit rst_d1_inst
(.clr_full(clr_full),
.d_out_reg_0(rst_d1_inst_n_1),
.\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ),
.\gof.overflow_i_reg (full),
.overflow_i0(overflow_i0),
.prog_full(prog_full),
.rst(rst),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_3 wrp_inst
(.D(\gwdc.diff_wr_rd_pntr1_out ),
.Q(wr_pntr_ext),
.\count_value_i_reg[6]_0 (full),
.\gwdc.wr_data_count_i_reg[8] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_4 wrpp1_inst
(.D(diff_pntr_pf_q0),
.Q(wr_pntr_plus1_pf),
.\count_value_i_reg[6]_0 (full),
.\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rd_pntr_wr),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0 wrpp2_inst
(.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}),
.\count_value_i_reg[6]_0 (full),
.rst_d1(rst_d1),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wrst_busy(wrst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst xpm_fifo_rst_inst
(.Q(curr_fwft_state),
.SR(\grdc.rd_data_count_i0 ),
.d_out_reg(xpm_fifo_rst_inst_n_2),
.\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy),
.\guf.underflow_i_reg (empty),
.\gwack.wr_ack_i_reg (full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.rst_d1(rst_d1),
.underflow_i0(underflow_i0),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry),
.wr_rst_busy(wr_rst_busy),
.wrst_busy(wrst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit
(rst_d1,
d_out_reg_0,
overflow_i0,
clr_full,
wrst_busy,
wr_clk,
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ,
rst,
\gof.overflow_i_reg ,
prog_full,
wr_en);
output rst_d1;
output d_out_reg_0;
output overflow_i0;
output clr_full;
input wrst_busy;
input wr_clk;
input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ;
input rst;
input \gof.overflow_i_reg ;
input prog_full;
input wr_en;
wire clr_full;
wire d_out_reg_0;
wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ;
wire \gof.overflow_i_reg ;
wire overflow_i0;
wire prog_full;
wire rst;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wrst_busy;
FDRE #(
.INIT(1'b0))
d_out_reg
(.C(wr_clk),
.CE(1'b1),
.D(wrst_busy),
.Q(rst_d1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'h04))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_3
(.I0(rst),
.I1(rst_d1),
.I2(wrst_busy),
.O(clr_full));
LUT5 #(
.INIT(32'hF3A200A2))
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_1
(.I0(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ),
.I1(rst_d1),
.I2(rst),
.I3(\gof.overflow_i_reg ),
.I4(prog_full),
.O(d_out_reg_0));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT4 #(
.INIT(16'hFE00))
\gof.overflow_i_i_1
(.I0(rst_d1),
.I1(wrst_busy),
.I2(\gof.overflow_i_reg ),
.I3(wr_en),
.O(overflow_i0));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_reg_bit" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_13
(rst_d1,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg ,
overflow_i0,
d_out_reg_0,
wrst_busy,
wr_clk,
p_1_in,
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ,
prog_full,
rst,
wr_en);
output rst_d1;
output \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg ;
output overflow_i0;
output d_out_reg_0;
input wrst_busy;
input wr_clk;
input p_1_in;
input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ;
input prog_full;
input rst;
input wr_en;
wire d_out_reg_0;
wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ;
wire \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg ;
wire overflow_i0;
wire p_1_in;
wire prog_full;
wire rst;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wrst_busy;
FDRE #(
.INIT(1'b0))
d_out_reg
(.C(wr_clk),
.CE(1'b1),
.D(wrst_busy),
.Q(rst_d1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hF4))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4
(.I0(rst),
.I1(rst_d1),
.I2(wrst_busy),
.O(d_out_reg_0));
LUT6 #(
.INIT(64'h00000000E200E2E2))
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_1
(.I0(p_1_in),
.I1(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ),
.I2(prog_full),
.I3(rst),
.I4(rst_d1),
.I5(wrst_busy),
.O(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'hFE00))
\gof.overflow_i_i_1
(.I0(rst_d1),
.I1(wrst_busy),
.I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ),
.I3(wr_en),
.O(overflow_i0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec
(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ,
\reg_out_i_reg[7]_0 ,
d_out_reg,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg ,
rst,
clr_full,
almost_full,
wr_pntr_plus1_pf_carry,
Q,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 ,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 ,
rst_d1,
wrst_busy,
D,
wr_clk);
output \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ;
output [7:0]\reg_out_i_reg[7]_0 ;
output d_out_reg;
input \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg ;
input rst;
input clr_full;
input almost_full;
input wr_pntr_plus1_pf_carry;
input [7:0]Q;
input [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 ;
input [7:0]\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 ;
input rst_d1;
input wrst_busy;
input [7:0]D;
input wr_clk;
wire [7:0]D;
wire [7:0]Q;
wire almost_full;
wire clr_full;
wire d_out_reg;
wire [7:0]\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4_n_0 ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0 ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0 ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg ;
wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ;
wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ;
wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ;
wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ;
wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ;
wire [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 ;
wire going_afull;
wire leaving_afull;
wire leaving_full;
wire [7:0]\reg_out_i_reg[7]_0 ;
wire rst;
wire rst_d1;
wire wr_clk;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
LUT6 #(
.INIT(64'hFF00FFFE0000000E))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_1
(.I0(leaving_afull),
.I1(going_afull),
.I2(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg ),
.I3(rst),
.I4(clr_full),
.I5(almost_full),
.O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ));
LUT4 #(
.INIT(16'h0800))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2
(.I0(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4_n_0 ),
.I1(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0 ),
.I2(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0 ),
.I3(wr_pntr_plus1_pf_carry),
.O(going_afull));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 [0]),
.I2(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 [2]),
.I3(\reg_out_i_reg[7]_0 [2]),
.I4(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 [1]),
.I5(\reg_out_i_reg[7]_0 [1]),
.O(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 [3]),
.I2(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 [5]),
.I3(\reg_out_i_reg[7]_0 [5]),
.I4(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 [4]),
.I5(\reg_out_i_reg[7]_0 [4]),
.O(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0 ));
LUT4 #(
.INIT(16'h6FF6))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6
(.I0(\reg_out_i_reg[7]_0 [6]),
.I1(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 [6]),
.I2(\reg_out_i_reg[7]_0 [7]),
.I3(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0 [7]),
.O(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0 ));
LUT5 #(
.INIT(32'hEAEA00EA))
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1
(.I0(leaving_full),
.I1(leaving_afull),
.I2(wr_pntr_plus1_pf_carry),
.I3(rst_d1),
.I4(rst),
.O(d_out_reg));
LUT6 #(
.INIT(64'h9009000000000000))
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2
(.I0(Q[7]),
.I1(\reg_out_i_reg[7]_0 [7]),
.I2(Q[6]),
.I3(\reg_out_i_reg[7]_0 [6]),
.I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ),
.I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ),
.O(leaving_full));
LUT6 #(
.INIT(64'h9009000000000000))
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3
(.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 [7]),
.I1(\reg_out_i_reg[7]_0 [7]),
.I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 [6]),
.I3(\reg_out_i_reg[7]_0 [6]),
.I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ),
.I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ),
.O(leaving_afull));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(Q[3]),
.I2(Q[5]),
.I3(\reg_out_i_reg[7]_0 [5]),
.I4(Q[4]),
.I5(\reg_out_i_reg[7]_0 [4]),
.O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(Q[0]),
.I2(Q[2]),
.I3(\reg_out_i_reg[7]_0 [2]),
.I4(Q[1]),
.I5(\reg_out_i_reg[7]_0 [1]),
.O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 [3]),
.I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 [5]),
.I3(\reg_out_i_reg[7]_0 [5]),
.I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 [4]),
.I5(\reg_out_i_reg[7]_0 [4]),
.O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 [0]),
.I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 [2]),
.I3(\reg_out_i_reg[7]_0 [2]),
.I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0 [1]),
.I5(\reg_out_i_reg[7]_0 [1]),
.O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(D[0]),
.Q(\reg_out_i_reg[7]_0 [0]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(D[1]),
.Q(\reg_out_i_reg[7]_0 [1]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(D[2]),
.Q(\reg_out_i_reg[7]_0 [2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.D(D[3]),
.Q(\reg_out_i_reg[7]_0 [3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(D[4]),
.Q(\reg_out_i_reg[7]_0 [4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.D(D[5]),
.Q(\reg_out_i_reg[7]_0 [5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.D(D[6]),
.Q(\reg_out_i_reg[7]_0 [6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.D(D[7]),
.Q(\reg_out_i_reg[7]_0 [7]),
.R(wrst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_reg_vec" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_1
(ram_empty_i0,
\reg_out_i_reg[7]_0 ,
Q,
rd_en,
ram_empty_i,
\gen_pf_ic_rc.ram_empty_i_reg ,
\gen_pf_ic_rc.ram_empty_i_reg_0 ,
\reg_out_i_reg[0]_0 ,
D,
rd_clk);
output ram_empty_i0;
output [7:0]\reg_out_i_reg[7]_0 ;
input [1:0]Q;
input rd_en;
input ram_empty_i;
input [7:0]\gen_pf_ic_rc.ram_empty_i_reg ;
input [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ;
input \reg_out_i_reg[0]_0 ;
input [7:0]D;
input rd_clk;
wire [7:0]D;
wire [1:0]Q;
wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ;
wire \gen_pf_ic_rc.ram_empty_i_i_5_n_0 ;
wire \gen_pf_ic_rc.ram_empty_i_i_6_n_0 ;
wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ;
wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg ;
wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ;
wire going_empty0;
wire leaving_empty;
wire ram_empty_i;
wire ram_empty_i0;
wire rd_clk;
wire rd_en;
wire \reg_out_i_reg[0]_0 ;
wire [7:0]\reg_out_i_reg[7]_0 ;
LUT6 #(
.INIT(64'hFFFFFFFF00FD0000))
\gen_pf_ic_rc.ram_empty_i_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(rd_en),
.I3(ram_empty_i),
.I4(going_empty0),
.I5(leaving_empty),
.O(ram_empty_i0));
LUT6 #(
.INIT(64'h9009000000000000))
\gen_pf_ic_rc.ram_empty_i_i_2
(.I0(\gen_pf_ic_rc.ram_empty_i_reg_0 [7]),
.I1(\reg_out_i_reg[7]_0 [7]),
.I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [6]),
.I3(\reg_out_i_reg[7]_0 [6]),
.I4(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ),
.I5(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ),
.O(going_empty0));
LUT6 #(
.INIT(64'h9009000000000000))
\gen_pf_ic_rc.ram_empty_i_i_3
(.I0(\gen_pf_ic_rc.ram_empty_i_reg [7]),
.I1(\reg_out_i_reg[7]_0 [7]),
.I2(\gen_pf_ic_rc.ram_empty_i_reg [6]),
.I3(\reg_out_i_reg[7]_0 [6]),
.I4(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ),
.I5(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ),
.O(leaving_empty));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.ram_empty_i_i_4
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [3]),
.I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [5]),
.I3(\reg_out_i_reg[7]_0 [5]),
.I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [4]),
.I5(\reg_out_i_reg[7]_0 [4]),
.O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.ram_empty_i_i_5
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [0]),
.I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [2]),
.I3(\reg_out_i_reg[7]_0 [2]),
.I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [1]),
.I5(\reg_out_i_reg[7]_0 [1]),
.O(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.ram_empty_i_i_6
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(\gen_pf_ic_rc.ram_empty_i_reg [3]),
.I2(\gen_pf_ic_rc.ram_empty_i_reg [5]),
.I3(\reg_out_i_reg[7]_0 [5]),
.I4(\gen_pf_ic_rc.ram_empty_i_reg [4]),
.I5(\reg_out_i_reg[7]_0 [4]),
.O(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.ram_empty_i_i_7
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(\gen_pf_ic_rc.ram_empty_i_reg [0]),
.I2(\gen_pf_ic_rc.ram_empty_i_reg [2]),
.I3(\reg_out_i_reg[7]_0 [2]),
.I4(\gen_pf_ic_rc.ram_empty_i_reg [1]),
.I5(\reg_out_i_reg[7]_0 [1]),
.O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(D[0]),
.Q(\reg_out_i_reg[7]_0 [0]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(D[1]),
.Q(\reg_out_i_reg[7]_0 [1]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(D[2]),
.Q(\reg_out_i_reg[7]_0 [2]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.D(D[3]),
.Q(\reg_out_i_reg[7]_0 [3]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.D(D[4]),
.Q(\reg_out_i_reg[7]_0 [4]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.D(D[5]),
.Q(\reg_out_i_reg[7]_0 [5]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.D(D[6]),
.Q(\reg_out_i_reg[7]_0 [6]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.D(D[7]),
.Q(\reg_out_i_reg[7]_0 [7]),
.R(\reg_out_i_reg[0]_0 ));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_reg_vec" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_6
(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg ,
\reg_out_i_reg[7]_0 ,
ram_full_i0,
almost_full,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_0 ,
wr_pntr_plus1_pf_carry,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_1 ,
Q,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg ,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 ,
wr_en,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0 ,
rst_d1,
wrst_busy,
D,
wr_clk);
output \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg ;
output [7:0]\reg_out_i_reg[7]_0 ;
output ram_full_i0;
input almost_full;
input \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_0 ;
input wr_pntr_plus1_pf_carry;
input \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_1 ;
input [7:0]Q;
input [7:0]\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg ;
input [7:0]\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 ;
input wr_en;
input \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0 ;
input rst_d1;
input wrst_busy;
input [7:0]D;
input wr_clk;
wire [7:0]D;
wire [7:0]Q;
wire almost_full;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0 ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0 ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_0 ;
wire \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_1 ;
wire [7:0]\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 ;
wire \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4_n_0 ;
wire \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0 ;
wire \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_6_n_0 ;
wire \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_7_n_0 ;
wire [7:0]\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg ;
wire \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0 ;
wire going_afull0;
wire leaving_afull;
wire leaving_full;
wire ram_full_i0;
wire [7:0]\reg_out_i_reg[7]_0 ;
wire rst_d1;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wrst_busy;
LUT6 #(
.INIT(64'h00000000EEE2E2E2))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_1
(.I0(almost_full),
.I1(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_0 ),
.I2(leaving_afull),
.I3(going_afull0),
.I4(wr_pntr_plus1_pf_carry),
.I5(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_1 ),
.O(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg ));
LUT6 #(
.INIT(64'h9009000000000000))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_3
(.I0(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 [7]),
.I1(\reg_out_i_reg[7]_0 [7]),
.I2(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 [6]),
.I3(\reg_out_i_reg[7]_0 [6]),
.I4(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0 ),
.I5(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0 ),
.O(going_afull0));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 [3]),
.I2(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 [5]),
.I3(\reg_out_i_reg[7]_0 [5]),
.I4(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 [4]),
.I5(\reg_out_i_reg[7]_0 [4]),
.O(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 [0]),
.I2(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 [2]),
.I3(\reg_out_i_reg[7]_0 [2]),
.I4(\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2 [1]),
.I5(\reg_out_i_reg[7]_0 [1]),
.O(\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0 ));
LUT5 #(
.INIT(32'hFFFF0200))
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_1
(.I0(wr_en),
.I1(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0 ),
.I2(rst_d1),
.I3(leaving_afull),
.I4(leaving_full),
.O(ram_full_i0));
LUT6 #(
.INIT(64'h9009000000000000))
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2
(.I0(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg [7]),
.I1(\reg_out_i_reg[7]_0 [7]),
.I2(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg [6]),
.I3(\reg_out_i_reg[7]_0 [6]),
.I4(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4_n_0 ),
.I5(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0 ),
.O(leaving_afull));
LUT6 #(
.INIT(64'h9009000000000000))
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_3
(.I0(Q[7]),
.I1(\reg_out_i_reg[7]_0 [7]),
.I2(Q[6]),
.I3(\reg_out_i_reg[7]_0 [6]),
.I4(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_6_n_0 ),
.I5(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_7_n_0 ),
.O(leaving_full));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg [3]),
.I2(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg [5]),
.I3(\reg_out_i_reg[7]_0 [5]),
.I4(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg [4]),
.I5(\reg_out_i_reg[7]_0 [4]),
.O(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg [0]),
.I2(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg [2]),
.I3(\reg_out_i_reg[7]_0 [2]),
.I4(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg [1]),
.I5(\reg_out_i_reg[7]_0 [1]),
.O(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_6
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(Q[3]),
.I2(Q[5]),
.I3(\reg_out_i_reg[7]_0 [5]),
.I4(Q[4]),
.I5(\reg_out_i_reg[7]_0 [4]),
.O(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_6_n_0 ));
LUT6 #(
.INIT(64'h9009000000009009))
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_7
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(Q[0]),
.I2(Q[2]),
.I3(\reg_out_i_reg[7]_0 [2]),
.I4(Q[1]),
.I5(\reg_out_i_reg[7]_0 [1]),
.O(\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_7_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(D[0]),
.Q(\reg_out_i_reg[7]_0 [0]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(D[1]),
.Q(\reg_out_i_reg[7]_0 [1]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(D[2]),
.Q(\reg_out_i_reg[7]_0 [2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.D(D[3]),
.Q(\reg_out_i_reg[7]_0 [3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(D[4]),
.Q(\reg_out_i_reg[7]_0 [4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.D(D[5]),
.Q(\reg_out_i_reg[7]_0 [5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.D(D[6]),
.Q(\reg_out_i_reg[7]_0 [6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.D(D[7]),
.Q(\reg_out_i_reg[7]_0 [7]),
.R(wrst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_reg_vec" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_8
(\count_value_i_reg[7] ,
\reg_out_i_reg[7]_0 ,
S,
\reg_out_i_reg[7]_1 ,
Q,
\reg_out_i_reg[0]_0 ,
D,
rd_clk);
output \count_value_i_reg[7] ;
output [7:0]\reg_out_i_reg[7]_0 ;
output [2:0]S;
output [3:0]\reg_out_i_reg[7]_1 ;
input [7:0]Q;
input \reg_out_i_reg[0]_0 ;
input [7:0]D;
input rd_clk;
wire [7:0]D;
wire [7:0]Q;
wire [2:0]S;
wire \count_value_i_reg[7] ;
wire \gen_pf_ic_rc.ram_empty_i_i_6_n_0 ;
wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ;
wire rd_clk;
wire \reg_out_i_reg[0]_0 ;
wire [7:0]\reg_out_i_reg[7]_0 ;
wire [3:0]\reg_out_i_reg[7]_1 ;
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(Q[3]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7
(.I0(\reg_out_i_reg[7]_0 [2]),
.I1(Q[2]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8
(.I0(\reg_out_i_reg[7]_0 [1]),
.I1(Q[1]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5
(.I0(\reg_out_i_reg[7]_0 [7]),
.I1(Q[7]),
.O(\reg_out_i_reg[7]_1 [3]));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6
(.I0(\reg_out_i_reg[7]_0 [6]),
.I1(Q[6]),
.O(\reg_out_i_reg[7]_1 [2]));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7
(.I0(\reg_out_i_reg[7]_0 [5]),
.I1(Q[5]),
.O(\reg_out_i_reg[7]_1 [1]));
LUT2 #(
.INIT(4'h9))
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8
(.I0(\reg_out_i_reg[7]_0 [4]),
.I1(Q[4]),
.O(\reg_out_i_reg[7]_1 [0]));
LUT6 #(
.INIT(64'h0000000000009009))
\gen_pf_ic_rc.ram_empty_i_i_3
(.I0(Q[7]),
.I1(\reg_out_i_reg[7]_0 [7]),
.I2(Q[6]),
.I3(\reg_out_i_reg[7]_0 [6]),
.I4(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ),
.I5(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ),
.O(\count_value_i_reg[7] ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\gen_pf_ic_rc.ram_empty_i_i_6
(.I0(\reg_out_i_reg[7]_0 [0]),
.I1(Q[0]),
.I2(Q[1]),
.I3(\reg_out_i_reg[7]_0 [1]),
.I4(Q[2]),
.I5(\reg_out_i_reg[7]_0 [2]),
.O(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\gen_pf_ic_rc.ram_empty_i_i_7
(.I0(\reg_out_i_reg[7]_0 [3]),
.I1(Q[3]),
.I2(Q[4]),
.I3(\reg_out_i_reg[7]_0 [4]),
.I4(Q[5]),
.I5(\reg_out_i_reg[7]_0 [5]),
.O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(D[0]),
.Q(\reg_out_i_reg[7]_0 [0]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(D[1]),
.Q(\reg_out_i_reg[7]_0 [1]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(D[2]),
.Q(\reg_out_i_reg[7]_0 [2]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.D(D[3]),
.Q(\reg_out_i_reg[7]_0 [3]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.D(D[4]),
.Q(\reg_out_i_reg[7]_0 [4]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.D(D[5]),
.Q(\reg_out_i_reg[7]_0 [5]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.D(D[6]),
.Q(\reg_out_i_reg[7]_0 [6]),
.R(\reg_out_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.D(D[7]),
.Q(\reg_out_i_reg[7]_0 [7]),
.R(\reg_out_i_reg[0]_0 ));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_reg_vec" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0
(Q,
wrst_busy,
D,
wr_clk);
output [8:0]Q;
input wrst_busy;
input [8:0]D;
input wr_clk;
wire [8:0]D;
wire [8:0]Q;
wire wr_clk;
wire wrst_busy;
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(D[0]),
.Q(Q[0]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(D[1]),
.Q(Q[1]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(D[2]),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.D(D[3]),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(D[4]),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.D(D[5]),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.D(D[6]),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.D(D[7]),
.Q(Q[7]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.D(D[8]),
.Q(Q[8]),
.R(wrst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_reg_vec" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_2
(D,
Q,
DI,
S,
\grdc.rd_data_count_i_reg[7] ,
\grdc.rd_data_count_i_reg[8] ,
\grdc.rd_data_count_i_reg[3] ,
\grdc.rd_data_count_i_reg[7]_0 ,
\reg_out_i_reg[8]_0 ,
\reg_out_i_reg[8]_1 ,
rd_clk);
output [8:0]D;
output [8:0]Q;
input [1:0]DI;
input [2:0]S;
input [3:0]\grdc.rd_data_count_i_reg[7] ;
input [0:0]\grdc.rd_data_count_i_reg[8] ;
input \grdc.rd_data_count_i_reg[3] ;
input [5:0]\grdc.rd_data_count_i_reg[7]_0 ;
input \reg_out_i_reg[8]_0 ;
input [8:0]\reg_out_i_reg[8]_1 ;
input rd_clk;
wire [8:0]D;
wire [1:0]DI;
wire [8:0]Q;
wire [2:0]S;
wire \grdc.rd_data_count_i[3]_i_2_n_0 ;
wire \grdc.rd_data_count_i[3]_i_6_n_0 ;
wire \grdc.rd_data_count_i[7]_i_2_n_0 ;
wire \grdc.rd_data_count_i[7]_i_3_n_0 ;
wire \grdc.rd_data_count_i[7]_i_4_n_0 ;
wire \grdc.rd_data_count_i[7]_i_5_n_0 ;
wire \grdc.rd_data_count_i_reg[3] ;
wire \grdc.rd_data_count_i_reg[3]_i_1_n_0 ;
wire \grdc.rd_data_count_i_reg[3]_i_1_n_1 ;
wire \grdc.rd_data_count_i_reg[3]_i_1_n_2 ;
wire \grdc.rd_data_count_i_reg[3]_i_1_n_3 ;
wire [3:0]\grdc.rd_data_count_i_reg[7] ;
wire [5:0]\grdc.rd_data_count_i_reg[7]_0 ;
wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ;
wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ;
wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ;
wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ;
wire [0:0]\grdc.rd_data_count_i_reg[8] ;
wire rd_clk;
wire \reg_out_i_reg[8]_0 ;
wire [8:0]\reg_out_i_reg[8]_1 ;
wire [3:0]\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED ;
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[3]_i_2
(.I0(Q[2]),
.I1(\grdc.rd_data_count_i_reg[7]_0 [1]),
.O(\grdc.rd_data_count_i[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h718E8E71))
\grdc.rd_data_count_i[3]_i_6
(.I0(Q[1]),
.I1(\grdc.rd_data_count_i_reg[3] ),
.I2(\grdc.rd_data_count_i_reg[7]_0 [0]),
.I3(\grdc.rd_data_count_i_reg[7]_0 [1]),
.I4(Q[2]),
.O(\grdc.rd_data_count_i[3]_i_6_n_0 ));
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[7]_i_2
(.I0(Q[6]),
.I1(\grdc.rd_data_count_i_reg[7]_0 [5]),
.O(\grdc.rd_data_count_i[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[7]_i_3
(.I0(Q[5]),
.I1(\grdc.rd_data_count_i_reg[7]_0 [4]),
.O(\grdc.rd_data_count_i[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[7]_i_4
(.I0(Q[4]),
.I1(\grdc.rd_data_count_i_reg[7]_0 [3]),
.O(\grdc.rd_data_count_i[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[7]_i_5
(.I0(Q[3]),
.I1(\grdc.rd_data_count_i_reg[7]_0 [2]),
.O(\grdc.rd_data_count_i[7]_i_5_n_0 ));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \grdc.rd_data_count_i_reg[3]_i_1
(.CI(1'b0),
.CO({\grdc.rd_data_count_i_reg[3]_i_1_n_0 ,\grdc.rd_data_count_i_reg[3]_i_1_n_1 ,\grdc.rd_data_count_i_reg[3]_i_1_n_2 ,\grdc.rd_data_count_i_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({\grdc.rd_data_count_i[3]_i_2_n_0 ,DI,Q[0]}),
.O(D[3:0]),
.S({S[2],\grdc.rd_data_count_i[3]_i_6_n_0 ,S[1:0]}));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \grdc.rd_data_count_i_reg[7]_i_1
(.CI(\grdc.rd_data_count_i_reg[3]_i_1_n_0 ),
.CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({\grdc.rd_data_count_i[7]_i_2_n_0 ,\grdc.rd_data_count_i[7]_i_3_n_0 ,\grdc.rd_data_count_i[7]_i_4_n_0 ,\grdc.rd_data_count_i[7]_i_5_n_0 }),
.O(D[7:4]),
.S(\grdc.rd_data_count_i_reg[7] ));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \grdc.rd_data_count_i_reg[8]_i_2
(.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ),
.CO(\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED [3:1],D[8]}),
.S({1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[8] }));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [0]),
.Q(Q[0]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [1]),
.Q(Q[1]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [2]),
.Q(Q[2]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [3]),
.Q(Q[3]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [4]),
.Q(Q[4]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [5]),
.Q(Q[5]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [6]),
.Q(Q[6]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [7]),
.Q(Q[7]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [8]),
.Q(Q[8]),
.R(\reg_out_i_reg[8]_0 ));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_reg_vec" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_7
(Q,
wrst_busy,
D,
wr_clk);
output [8:0]Q;
input wrst_busy;
input [8:0]D;
input wr_clk;
wire [8:0]D;
wire [8:0]Q;
wire wr_clk;
wire wrst_busy;
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(D[0]),
.Q(Q[0]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(D[1]),
.Q(Q[1]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(D[2]),
.Q(Q[2]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.D(D[3]),
.Q(Q[3]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(D[4]),
.Q(Q[4]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.D(D[5]),
.Q(Q[5]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.D(D[6]),
.Q(Q[6]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.D(D[7]),
.Q(Q[7]),
.R(wrst_busy));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.D(D[8]),
.Q(Q[8]),
.R(wrst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_reg_vec" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_9
(Q,
D,
\grdc.rd_data_count_i_reg[7] ,
\grdc.rd_data_count_i_reg[3] ,
DI,
S,
\grdc.rd_data_count_i_reg[7]_0 ,
\grdc.rd_data_count_i_reg[8] ,
\reg_out_i_reg[8]_0 ,
\reg_out_i_reg[8]_1 ,
rd_clk);
output [8:0]Q;
output [8:0]D;
input [5:0]\grdc.rd_data_count_i_reg[7] ;
input \grdc.rd_data_count_i_reg[3] ;
input [0:0]DI;
input [3:0]S;
input [3:0]\grdc.rd_data_count_i_reg[7]_0 ;
input [0:0]\grdc.rd_data_count_i_reg[8] ;
input \reg_out_i_reg[8]_0 ;
input [8:0]\reg_out_i_reg[8]_1 ;
input rd_clk;
wire [8:0]D;
wire [0:0]DI;
wire [8:0]Q;
wire [3:0]S;
wire \grdc.rd_data_count_i[3]_i_2_n_0 ;
wire \grdc.rd_data_count_i[3]_i_3_n_0 ;
wire \grdc.rd_data_count_i[7]_i_2_n_0 ;
wire \grdc.rd_data_count_i[7]_i_3_n_0 ;
wire \grdc.rd_data_count_i[7]_i_4_n_0 ;
wire \grdc.rd_data_count_i[7]_i_5_n_0 ;
wire \grdc.rd_data_count_i_reg[3] ;
wire \grdc.rd_data_count_i_reg[3]_i_1_n_0 ;
wire \grdc.rd_data_count_i_reg[3]_i_1_n_1 ;
wire \grdc.rd_data_count_i_reg[3]_i_1_n_2 ;
wire \grdc.rd_data_count_i_reg[3]_i_1_n_3 ;
wire [5:0]\grdc.rd_data_count_i_reg[7] ;
wire [3:0]\grdc.rd_data_count_i_reg[7]_0 ;
wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ;
wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ;
wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ;
wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ;
wire [0:0]\grdc.rd_data_count_i_reg[8] ;
wire rd_clk;
wire \reg_out_i_reg[8]_0 ;
wire [8:0]\reg_out_i_reg[8]_1 ;
wire [3:0]\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED ;
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[3]_i_2
(.I0(Q[2]),
.I1(\grdc.rd_data_count_i_reg[7] [1]),
.O(\grdc.rd_data_count_i[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'h8E))
\grdc.rd_data_count_i[3]_i_3
(.I0(Q[1]),
.I1(\grdc.rd_data_count_i_reg[3] ),
.I2(\grdc.rd_data_count_i_reg[7] [0]),
.O(\grdc.rd_data_count_i[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[7]_i_2
(.I0(Q[6]),
.I1(\grdc.rd_data_count_i_reg[7] [5]),
.O(\grdc.rd_data_count_i[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[7]_i_3
(.I0(Q[5]),
.I1(\grdc.rd_data_count_i_reg[7] [4]),
.O(\grdc.rd_data_count_i[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[7]_i_4
(.I0(Q[4]),
.I1(\grdc.rd_data_count_i_reg[7] [3]),
.O(\grdc.rd_data_count_i[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\grdc.rd_data_count_i[7]_i_5
(.I0(Q[3]),
.I1(\grdc.rd_data_count_i_reg[7] [2]),
.O(\grdc.rd_data_count_i[7]_i_5_n_0 ));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \grdc.rd_data_count_i_reg[3]_i_1
(.CI(1'b0),
.CO({\grdc.rd_data_count_i_reg[3]_i_1_n_0 ,\grdc.rd_data_count_i_reg[3]_i_1_n_1 ,\grdc.rd_data_count_i_reg[3]_i_1_n_2 ,\grdc.rd_data_count_i_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({\grdc.rd_data_count_i[3]_i_2_n_0 ,\grdc.rd_data_count_i[3]_i_3_n_0 ,DI,Q[0]}),
.O(D[3:0]),
.S(S));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \grdc.rd_data_count_i_reg[7]_i_1
(.CI(\grdc.rd_data_count_i_reg[3]_i_1_n_0 ),
.CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({\grdc.rd_data_count_i[7]_i_2_n_0 ,\grdc.rd_data_count_i[7]_i_3_n_0 ,\grdc.rd_data_count_i[7]_i_4_n_0 ,\grdc.rd_data_count_i[7]_i_5_n_0 }),
.O(D[7:4]),
.S(\grdc.rd_data_count_i_reg[7]_0 ));
(* ADDER_THRESHOLD = "35" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \grdc.rd_data_count_i_reg[8]_i_2
(.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ),
.CO(\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED [3:1],D[8]}),
.S({1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[8] }));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [0]),
.Q(Q[0]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [1]),
.Q(Q[1]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [2]),
.Q(Q[2]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [3]),
.Q(Q[3]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [4]),
.Q(Q[4]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [5]),
.Q(Q[5]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [6]),
.Q(Q[6]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [7]),
.Q(Q[7]),
.R(\reg_out_i_reg[8]_0 ));
FDRE #(
.INIT(1'b0))
\reg_out_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.D(\reg_out_i_reg[8]_1 [8]),
.Q(Q[8]),
.R(\reg_out_i_reg[8]_0 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst
(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ,
wrst_busy,
d_out_reg,
wr_pntr_plus1_pf_carry,
wr_rst_busy,
SR,
underflow_i0,
rd_clk,
wr_clk,
rst,
rst_d1,
\gwack.wr_ack_i_reg ,
wr_en,
Q,
\guf.underflow_i_reg ,
rd_en);
output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ;
output wrst_busy;
output d_out_reg;
output wr_pntr_plus1_pf_carry;
output wr_rst_busy;
output [0:0]SR;
output underflow_i0;
input rd_clk;
input wr_clk;
input rst;
input rst_d1;
input \gwack.wr_ack_i_reg ;
input wr_en;
input [1:0]Q;
input \guf.underflow_i_reg ;
input rd_en;
wire \/i__n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ;
wire [1:0]Q;
wire [0:0]SR;
wire d_out_reg;
(* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ;
wire \gen_rst_ic.fifo_rd_rst_i ;
wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ;
wire \gen_rst_ic.fifo_rd_rst_wr_i ;
wire \gen_rst_ic.fifo_wr_rst_ic ;
wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ;
wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ;
wire \gen_rst_ic.fifo_wr_rst_rd ;
wire [1:0]\gen_rst_ic.next_rrst_state ;
wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ;
wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ;
wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ;
wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ;
wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ;
wire \guf.underflow_i_reg ;
wire \gwack.wr_ack_i_reg ;
wire p_0_in;
wire \power_on_rst_reg_n_0_[0] ;
wire rd_clk;
wire rd_en;
wire rst;
wire rst_d1;
wire rst_i__0;
wire underflow_i0;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wr_rst_busy;
wire wrst_busy;
LUT5 #(
.INIT(32'h00010116))
\/i_
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h03030200FFFFFFFF))
\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I1(p_0_in),
.I2(rst),
.I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I5(\/i__n_0 ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFEFEFEEE))
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I3(rst),
.I4(p_0_in),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFF0EEE0FFFFEEE0))
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I2(rst),
.I3(p_0_in),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I5(\gen_rst_ic.fifo_rd_rst_wr_i ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h000C0008))
\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I1(\gen_rst_ic.fifo_rd_rst_wr_i ),
.I2(rst),
.I3(p_0_in),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000004400000044))
\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1
(.I0(\gen_rst_ic.fifo_rd_rst_wr_i ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I2(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.I3(rst),
.I4(p_0_in),
.I5(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1
(.I0(\/i__n_0 ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I1(p_0_in),
.I2(rst),
.I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b1))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.R(1'b0));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1
(.I0(\gen_rst_ic.curr_rrst_state [0]),
.I1(\gen_rst_ic.curr_rrst_state [1]),
.O(\gen_rst_ic.next_rrst_state [1]));
(* FSM_ENCODED_STATES = "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(\gen_rst_ic.next_rrst_state [0]),
.Q(\gen_rst_ic.curr_rrst_state [0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(\gen_rst_ic.next_rrst_state [1]),
.Q(\gen_rst_ic.curr_rrst_state [1]),
.R(1'b0));
LUT3 #(
.INIT(8'h06))
\__0/i_
(.I0(\gen_rst_ic.fifo_wr_rst_rd ),
.I1(\gen_rst_ic.curr_rrst_state [1]),
.I2(\gen_rst_ic.curr_rrst_state [0]),
.O(\gen_rst_ic.next_rrst_state [0]));
LUT3 #(
.INIT(8'h3E))
\gen_rst_ic.fifo_rd_rst_ic_i_1
(.I0(\gen_rst_ic.fifo_wr_rst_rd ),
.I1(\gen_rst_ic.curr_rrst_state [1]),
.I2(\gen_rst_ic.curr_rrst_state [0]),
.O(\gen_rst_ic.fifo_rd_rst_i ));
FDRE #(
.INIT(1'b0))
\gen_rst_ic.fifo_rd_rst_ic_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gen_rst_ic.fifo_rd_rst_i ),
.Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFEAFFFFFFEA0000))
\gen_rst_ic.fifo_wr_rst_ic_i_1
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I2(rst_i__0),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ),
.I5(\gen_rst_ic.fifo_wr_rst_ic ),
.O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT2 #(
.INIT(4'hE))
\gen_rst_ic.fifo_wr_rst_ic_i_2
(.I0(p_0_in),
.I1(rst),
.O(rst_i__0));
LUT5 #(
.INIT(32'h00010116))
\gen_rst_ic.fifo_wr_rst_ic_i_3
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_rst_ic.fifo_wr_rst_ic_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ),
.Q(\gen_rst_ic.fifo_wr_rst_ic ),
.R(1'b0));
(* DEF_VAL = "1'b0" *)
(* DEST_SYNC_FF = "2" *)
(* INIT = "0" *)
(* INIT_SYNC_FF = "1" *)
(* SIM_ASSERT_CHK = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SYNC_RST" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst \gen_rst_ic.rrst_wr_inst
(.dest_clk(wr_clk),
.dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ),
.src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'h02))
\gen_rst_ic.rst_seq_reentered_i_1
(.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ),
.I1(rst),
.I2(p_0_in),
.O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00010000))
\gen_rst_ic.rst_seq_reentered_i_2
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_rst_ic.rst_seq_reentered_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ),
.Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.R(1'b0));
LUT5 #(
.INIT(32'hEFFFEF00))
\gen_rst_ic.wr_rst_busy_ic_i_1
(.I0(rst),
.I1(p_0_in),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ),
.I4(wrst_busy),
.O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000116))
\gen_rst_ic.wr_rst_busy_ic_i_2
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_rst_ic.wr_rst_busy_ic_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ),
.Q(wrst_busy),
.R(1'b0));
(* DEF_VAL = "1'b0" *)
(* DEST_SYNC_FF = "2" *)
(* INIT = "0" *)
(* INIT_SYNC_FF = "1" *)
(* SIM_ASSERT_CHK = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SYNC_RST" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6 \gen_rst_ic.wrst_rd_inst
(.dest_clk(rd_clk),
.dest_rst(\gen_rst_ic.fifo_wr_rst_rd ),
.src_rst(\gen_rst_ic.fifo_wr_rst_ic ));
LUT4 #(
.INIT(16'h0002))
\gen_sdpram.xpm_memory_base_inst_i_1
(.I0(wr_en),
.I1(\gwack.wr_ack_i_reg ),
.I2(wrst_busy),
.I3(rst_d1),
.O(wr_pntr_plus1_pf_carry));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hAB))
\grdc.rd_data_count_i[8]_i_1
(.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ),
.I1(Q[0]),
.I2(Q[1]),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hE0))
\guf.underflow_i_i_1
(.I0(\guf.underflow_i_reg ),
.I1(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ),
.I2(rd_en),
.O(underflow_i0));
LUT6 #(
.INIT(64'h0000000000000010))
\gwack.wr_ack_i_i_1
(.I0(rst_d1),
.I1(\gwack.wr_ack_i_reg ),
.I2(wr_en),
.I3(wrst_busy),
.I4(\gen_rst_ic.fifo_wr_rst_ic ),
.I5(rst),
.O(d_out_reg));
FDRE #(
.INIT(1'b1))
\power_on_rst_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.Q(\power_on_rst_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\power_on_rst_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(\power_on_rst_reg_n_0_[0] ),
.Q(p_0_in),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
wr_rst_busy_INST_0
(.I0(wrst_busy),
.I1(rst_d1),
.O(wr_rst_busy));
endmodule
(* ORIG_REF_NAME = "xpm_fifo_rst" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1
(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ,
wrst_busy,
d_out_reg,
wr_pntr_plus1_pf_carry,
wr_rst_busy,
SR,
underflow_i0,
rd_clk,
wr_clk,
rst,
rst_d1,
\gwack.wr_ack_i_reg ,
wr_en,
Q,
rd_en,
\guf.underflow_i_reg );
output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ;
output wrst_busy;
output d_out_reg;
output wr_pntr_plus1_pf_carry;
output wr_rst_busy;
output [0:0]SR;
output underflow_i0;
input rd_clk;
input wr_clk;
input rst;
input rst_d1;
input \gwack.wr_ack_i_reg ;
input wr_en;
input [1:0]Q;
input rd_en;
input \guf.underflow_i_reg ;
wire \/i__n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ;
wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ;
wire [1:0]Q;
wire [0:0]SR;
wire d_out_reg;
(* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ;
wire \gen_rst_ic.fifo_rd_rst_i ;
wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ;
wire \gen_rst_ic.fifo_rd_rst_wr_i ;
wire \gen_rst_ic.fifo_wr_rst_ic ;
wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ;
wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ;
wire \gen_rst_ic.fifo_wr_rst_rd ;
wire [1:0]\gen_rst_ic.next_rrst_state ;
wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ;
wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ;
wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ;
wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ;
wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ;
wire \guf.underflow_i_reg ;
wire \gwack.wr_ack_i_reg ;
wire p_0_in;
wire \power_on_rst_reg_n_0_[0] ;
wire rd_clk;
wire rd_en;
wire rst;
wire rst_d1;
wire rst_i__0;
wire underflow_i0;
wire wr_clk;
wire wr_en;
wire wr_pntr_plus1_pf_carry;
wire wr_rst_busy;
wire wrst_busy;
LUT5 #(
.INIT(32'h00010116))
\/i_
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h03030200FFFFFFFF))
\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I1(p_0_in),
.I2(rst),
.I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I5(\/i__n_0 ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFEFEFEEE))
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I3(rst),
.I4(p_0_in),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFF0EEE0FFFFEEE0))
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I2(rst),
.I3(p_0_in),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I5(\gen_rst_ic.fifo_rd_rst_wr_i ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h000C0008))
\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I1(\gen_rst_ic.fifo_rd_rst_wr_i ),
.I2(rst),
.I3(p_0_in),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000004400000044))
\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1
(.I0(\gen_rst_ic.fifo_rd_rst_wr_i ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I2(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.I3(rst),
.I4(p_0_in),
.I5(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1
(.I0(\/i__n_0 ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I1(p_0_in),
.I2(rst),
.I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b1))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.R(1'b0));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
(* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]
(.C(wr_clk),
.CE(1'b1),
.D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ),
.Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1
(.I0(\gen_rst_ic.curr_rrst_state [0]),
.I1(\gen_rst_ic.curr_rrst_state [1]),
.O(\gen_rst_ic.next_rrst_state [1]));
(* FSM_ENCODED_STATES = "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(\gen_rst_ic.next_rrst_state [0]),
.Q(\gen_rst_ic.curr_rrst_state [0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(\gen_rst_ic.next_rrst_state [1]),
.Q(\gen_rst_ic.curr_rrst_state [1]),
.R(1'b0));
LUT3 #(
.INIT(8'h06))
\__0/i_
(.I0(\gen_rst_ic.fifo_wr_rst_rd ),
.I1(\gen_rst_ic.curr_rrst_state [1]),
.I2(\gen_rst_ic.curr_rrst_state [0]),
.O(\gen_rst_ic.next_rrst_state [0]));
LUT3 #(
.INIT(8'h3E))
\gen_rst_ic.fifo_rd_rst_ic_i_1
(.I0(\gen_rst_ic.fifo_wr_rst_rd ),
.I1(\gen_rst_ic.curr_rrst_state [1]),
.I2(\gen_rst_ic.curr_rrst_state [0]),
.O(\gen_rst_ic.fifo_rd_rst_i ));
FDRE #(
.INIT(1'b0))
\gen_rst_ic.fifo_rd_rst_ic_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gen_rst_ic.fifo_rd_rst_i ),
.Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFEAFFFFFFEA0000))
\gen_rst_ic.fifo_wr_rst_ic_i_1
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I2(rst_i__0),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ),
.I5(\gen_rst_ic.fifo_wr_rst_ic ),
.O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'hE))
\gen_rst_ic.fifo_wr_rst_ic_i_2
(.I0(p_0_in),
.I1(rst),
.O(rst_i__0));
LUT5 #(
.INIT(32'h00010116))
\gen_rst_ic.fifo_wr_rst_ic_i_3
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_rst_ic.fifo_wr_rst_ic_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ),
.Q(\gen_rst_ic.fifo_wr_rst_ic ),
.R(1'b0));
(* DEF_VAL = "1'b0" *)
(* DEST_SYNC_FF = "2" *)
(* INIT = "0" *)
(* INIT_SYNC_FF = "1" *)
(* SIM_ASSERT_CHK = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SYNC_RST" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5 \gen_rst_ic.rrst_wr_inst
(.dest_clk(wr_clk),
.dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ),
.src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h02))
\gen_rst_ic.rst_seq_reentered_i_1
(.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ),
.I1(rst),
.I2(p_0_in),
.O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00010000))
\gen_rst_ic.rst_seq_reentered_i_2
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_rst_ic.rst_seq_reentered_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ),
.Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ),
.R(1'b0));
LUT5 #(
.INIT(32'hEFFFEF00))
\gen_rst_ic.wr_rst_busy_ic_i_1
(.I0(rst),
.I1(p_0_in),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ),
.I4(wrst_busy),
.O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000116))
\gen_rst_ic.wr_rst_busy_ic_i_2
(.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ),
.I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ),
.I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ),
.I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ),
.I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ),
.O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_rst_ic.wr_rst_busy_ic_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ),
.Q(wrst_busy),
.R(1'b0));
(* DEF_VAL = "1'b0" *)
(* DEST_SYNC_FF = "2" *)
(* INIT = "0" *)
(* INIT_SYNC_FF = "1" *)
(* SIM_ASSERT_CHK = "0" *)
(* VERSION = "0" *)
(* XPM_CDC = "SYNC_RST" *)
(* XPM_MODULE = "TRUE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4 \gen_rst_ic.wrst_rd_inst
(.dest_clk(rd_clk),
.dest_rst(\gen_rst_ic.fifo_wr_rst_rd ),
.src_rst(\gen_rst_ic.fifo_wr_rst_ic ));
LUT4 #(
.INIT(16'h0002))
\gen_sdpram.xpm_memory_base_inst_i_1
(.I0(wr_en),
.I1(\gwack.wr_ack_i_reg ),
.I2(wrst_busy),
.I3(rst_d1),
.O(wr_pntr_plus1_pf_carry));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hAB))
\grdc.rd_data_count_i[8]_i_1
(.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ),
.I1(Q[1]),
.I2(Q[0]),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hA8))
\guf.underflow_i_i_1
(.I0(rd_en),
.I1(\guf.underflow_i_reg ),
.I2(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ),
.O(underflow_i0));
LUT6 #(
.INIT(64'h0000000000000010))
\gwack.wr_ack_i_i_1
(.I0(rst_d1),
.I1(\gwack.wr_ack_i_reg ),
.I2(wr_en),
.I3(wrst_busy),
.I4(\gen_rst_ic.fifo_wr_rst_ic ),
.I5(rst),
.O(d_out_reg));
FDRE #(
.INIT(1'b1))
\power_on_rst_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.Q(\power_on_rst_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\power_on_rst_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(\power_on_rst_reg_n_0_[0] ),
.Q(p_0_in),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
wr_rst_busy_INST_0
(.I0(wrst_busy),
.I1(rst_d1),
.O(wr_rst_busy));
endmodule
(* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *)
(* BYTE_WRITE_WIDTH_A = "8" *) (* BYTE_WRITE_WIDTH_B = "8" *) (* CASCADE_HEIGHT = "0" *)
(* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* IGNORE_INIT_SYNTH = "0" *)
(* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *)
(* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "0" *) (* MEMORY_SIZE = "2048" *)
(* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *)
(* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *)
(* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "auto" *)
(* P_MIN_WIDTH_DATA = "8" *) (* P_MIN_WIDTH_DATA_A = "8" *) (* P_MIN_WIDTH_DATA_B = "8" *)
(* P_MIN_WIDTH_DATA_ECC = "8" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "8" *)
(* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *)
(* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *)
(* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *)
(* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *)
(* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *)
(* P_WIDTH_COL_WRITE_A = "8" *) (* P_WIDTH_COL_WRITE_B = "8" *) (* READ_DATA_WIDTH_A = "8" *)
(* READ_DATA_WIDTH_B = "8" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *)
(* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *)
(* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *)
(* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *)
(* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "8" *) (* WRITE_DATA_WIDTH_B = "8" *)
(* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *)
(* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "8" *)
(* rstb_loop_iter = "8" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base
(sleep,
clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
injectsbiterra,
injectdbiterra,
douta,
sbiterra,
dbiterra,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
injectsbiterrb,
injectdbiterrb,
doutb,
sbiterrb,
dbiterrb);
input sleep;
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [7:0]addra;
input [7:0]dina;
input injectsbiterra;
input injectdbiterra;
output [7:0]douta;
output sbiterra;
output dbiterra;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [7:0]addrb;
input [7:0]dinb;
input injectsbiterrb;
input injectdbiterrb;
output [7:0]doutb;
output sbiterrb;
output dbiterrb;
wire \<const0> ;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]doutb;
wire ena;
wire enb;
wire regceb;
wire rstb;
wire sleep;
wire [15:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOADO_UNCONNECTED ;
wire [15:8]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED ;
assign dbiterra = \<const0> ;
assign dbiterrb = \<const0> ;
assign douta[7] = \<const0> ;
assign douta[6] = \<const0> ;
assign douta[5] = \<const0> ;
assign douta[4] = \<const0> ;
assign douta[3] = \<const0> ;
assign douta[2] = \<const0> ;
assign douta[1] = \<const0> ;
assign douta[0] = \<const0> ;
assign sbiterra = \<const0> ;
assign sbiterrb = \<const0> ;
GND GND
(.G(\<const0> ));
(* \MEM.PORTA.ADDRESS_BEGIN = "0" *)
(* \MEM.PORTA.ADDRESS_END = "1023" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d8" *)
(* \MEM.PORTA.DATA_LSB = "0" *)
(* \MEM.PORTA.DATA_MSB = "7" *)
(* \MEM.PORTB.ADDRESS_BEGIN = "0" *)
(* \MEM.PORTB.ADDRESS_END = "1023" *)
(* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d8" *)
(* \MEM.PORTB.DATA_LSB = "0" *)
(* \MEM.PORTB.DATA_MSB = "7" *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* RTL_RAM_BITS = "2048" *)
(* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *)
(* RTL_RAM_TYPE = "RAM_SDP" *)
(* ram_addr_begin = "0" *)
(* ram_addr_end = "1023" *)
(* ram_offset = "0" *)
(* ram_slice_begin = "0" *)
(* ram_slice_end = "7" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\gen_wr_a.gen_word_narrow.mem_reg
(.ADDRARDADDR({1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,addrb,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED [15:8],doutb}),
.DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.REGCEAREGCE(1'b0),
.REGCEB(regceb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(rstb),
.WEA({ena,ena}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *)
(* BYTE_WRITE_WIDTH_A = "8" *) (* BYTE_WRITE_WIDTH_B = "8" *) (* CASCADE_HEIGHT = "0" *)
(* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* IGNORE_INIT_SYNTH = "0" *)
(* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *)
(* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "0" *) (* MEMORY_SIZE = "2048" *)
(* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *)
(* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *)
(* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *)
(* P_MEMORY_PRIMITIVE = "auto" *) (* P_MIN_WIDTH_DATA = "8" *) (* P_MIN_WIDTH_DATA_A = "8" *)
(* P_MIN_WIDTH_DATA_B = "8" *) (* P_MIN_WIDTH_DATA_ECC = "8" *) (* P_MIN_WIDTH_DATA_LDW = "4" *)
(* P_MIN_WIDTH_DATA_SHFT = "8" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *)
(* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *)
(* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *)
(* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *)
(* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *)
(* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "8" *) (* P_WIDTH_COL_WRITE_B = "8" *)
(* READ_DATA_WIDTH_A = "8" *) (* READ_DATA_WIDTH_B = "8" *) (* READ_LATENCY_A = "2" *)
(* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *)
(* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *)
(* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *)
(* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "8" *)
(* WRITE_DATA_WIDTH_B = "8" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *)
(* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *)
(* rsta_loop_iter = "8" *) (* rstb_loop_iter = "8" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1
(sleep,
clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
injectsbiterra,
injectdbiterra,
douta,
sbiterra,
dbiterra,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
injectsbiterrb,
injectdbiterrb,
doutb,
sbiterrb,
dbiterrb);
input sleep;
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [7:0]addra;
input [7:0]dina;
input injectsbiterra;
input injectdbiterra;
output [7:0]douta;
output sbiterra;
output dbiterra;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [7:0]addrb;
input [7:0]dinb;
input injectsbiterrb;
input injectdbiterrb;
output [7:0]doutb;
output sbiterrb;
output dbiterrb;
wire \<const0> ;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]doutb;
wire ena;
wire enb;
wire regceb;
wire rstb;
wire sleep;
wire [15:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOADO_UNCONNECTED ;
wire [15:8]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED ;
assign dbiterra = \<const0> ;
assign dbiterrb = \<const0> ;
assign douta[7] = \<const0> ;
assign douta[6] = \<const0> ;
assign douta[5] = \<const0> ;
assign douta[4] = \<const0> ;
assign douta[3] = \<const0> ;
assign douta[2] = \<const0> ;
assign douta[1] = \<const0> ;
assign douta[0] = \<const0> ;
assign sbiterra = \<const0> ;
assign sbiterrb = \<const0> ;
GND GND
(.G(\<const0> ));
(* \MEM.PORTA.ADDRESS_BEGIN = "0" *)
(* \MEM.PORTA.ADDRESS_END = "1023" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d8" *)
(* \MEM.PORTA.DATA_LSB = "0" *)
(* \MEM.PORTA.DATA_MSB = "7" *)
(* \MEM.PORTB.ADDRESS_BEGIN = "0" *)
(* \MEM.PORTB.ADDRESS_END = "1023" *)
(* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d8" *)
(* \MEM.PORTB.DATA_LSB = "0" *)
(* \MEM.PORTB.DATA_MSB = "7" *)
(* METHODOLOGY_DRC_VIOS = "" *)
(* RTL_RAM_BITS = "2048" *)
(* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *)
(* RTL_RAM_TYPE = "RAM_SDP" *)
(* ram_addr_begin = "0" *)
(* ram_addr_end = "1023" *)
(* ram_offset = "0" *)
(* ram_slice_begin = "0" *)
(* ram_slice_end = "7" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\gen_wr_a.gen_word_narrow.mem_reg
(.ADDRARDADDR({1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,addrb,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOADO_UNCONNECTED [15:0]),
.DOBDO({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED [15:8],doutb}),
.DOPADOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.REGCEAREGCE(1'b0),
.REGCEB(regceb),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(rstb),
.WEA({ena,ena}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Tue Sep 20 00:10:15 2022
-- Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_quad_spi_sim_netlist.vhdl
-- Design : xlnx_axi_quad_spi
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k325tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
Rx_FIFO_Full_Fifo : out STD_LOGIC;
scndry_out : out STD_LOGIC;
almost_full : in STD_LOGIC;
prmry_in : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => almost_full,
I1 => \^scndry_out\,
O => Rx_FIFO_Full_Fifo
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => \^scndry_out\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
Rx_FIFO_Full_Fifo_d1_synced_i : out STD_LOGIC;
scndry_out : out STD_LOGIC;
empty : in STD_LOGIC;
prmry_in : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "VCC:CE";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "VCC:CE";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => \^scndry_out\,
R => '0'
);
rc_FIFO_Full_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^scndry_out\,
I1 => empty,
O => Rx_FIFO_Full_Fifo_d1_synced_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f is
port (
tx_fifo_count : out STD_LOGIC_VECTOR ( 0 to 0 );
\icount_out_reg[3]_0\ : out STD_LOGIC;
\icount_out_reg[2]_0\ : out STD_LOGIC;
\icount_out_reg[1]_0\ : out STD_LOGIC;
\icount_out_reg[5]_0\ : out STD_LOGIC;
\icount_out_reg[4]_0\ : out STD_LOGIC;
\icount_out_reg[6]_0\ : out STD_LOGIC;
tx_occ_msb_1 : out STD_LOGIC;
TX_one_less_than_full : out STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
IP2Bus_WrAck_transmit_enable : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\icount_out_reg[7]_0\ : in STD_LOGIC;
\icount_out_reg[7]_1\ : in STD_LOGIC;
\icount_out_reg[0]_0\ : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f is
signal \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal icount_out0_carry_i_1_n_0 : STD_LOGIC;
signal icount_out0_carry_i_2_n_0 : STD_LOGIC;
signal icount_out0_carry_i_3_n_0 : STD_LOGIC;
signal icount_out0_carry_i_4_n_0 : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal \icount_out[0]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[1]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[2]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[3]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[4]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[5]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[6]_i_1_n_0\ : STD_LOGIC;
signal \icount_out[7]_i_2_n_0\ : STD_LOGIC;
signal \^icount_out_reg[1]_0\ : STD_LOGIC;
signal \^icount_out_reg[2]_0\ : STD_LOGIC;
signal \^icount_out_reg[3]_0\ : STD_LOGIC;
signal \^icount_out_reg[4]_0\ : STD_LOGIC;
signal \^icount_out_reg[5]_0\ : STD_LOGIC;
signal \^icount_out_reg[6]_0\ : STD_LOGIC;
signal \^tx_fifo_count\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^tx_occ_msb_1\ : STD_LOGIC;
signal \NLW_icount_out0_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_icount_out0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \icount_out[0]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \icount_out[1]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \icount_out[2]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \icount_out[3]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \icount_out[4]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \icount_out[5]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \icount_out[6]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \icount_out[7]_i_2\ : label is "soft_lutpair36";
begin
\icount_out_reg[1]_0\ <= \^icount_out_reg[1]_0\;
\icount_out_reg[2]_0\ <= \^icount_out_reg[2]_0\;
\icount_out_reg[3]_0\ <= \^icount_out_reg[3]_0\;
\icount_out_reg[4]_0\ <= \^icount_out_reg[4]_0\;
\icount_out_reg[5]_0\ <= \^icount_out_reg[5]_0\;
\icount_out_reg[6]_0\ <= \^icount_out_reg[6]_0\;
tx_fifo_count(0) <= \^tx_fifo_count\(0);
tx_occ_msb_1 <= \^tx_occ_msb_1\;
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => IP2Bus_WrAck_transmit_enable,
I1 => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_3_n_0\,
I2 => \^icount_out_reg[3]_0\,
I3 => \^icount_out_reg[1]_0\,
I4 => \^icount_out_reg[5]_0\,
I5 => \^icount_out_reg[2]_0\,
O => TX_one_less_than_full
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \^icount_out_reg[6]_0\,
I1 => \^tx_fifo_count\(0),
I2 => \^tx_occ_msb_1\,
I3 => \^icount_out_reg[4]_0\,
O => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_3_n_0\
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^tx_fifo_count\(0),
DI(3) => \^icount_out_reg[3]_0\,
DI(2) => \^icount_out_reg[2]_0\,
DI(1) => \^icount_out_reg[1]_0\,
DI(0) => icount_out0_carry_i_1_n_0,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => icount_out0_carry_i_2_n_0,
S(2) => icount_out0_carry_i_3_n_0,
S(1) => icount_out0_carry_i_4_n_0,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3 downto 2) => \NLW_icount_out0_carry__0_CO_UNCONNECTED\(3 downto 2),
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \^icount_out_reg[5]_0\,
DI(0) => \^icount_out_reg[4]_0\,
O(3) => \NLW_icount_out0_carry__0_O_UNCONNECTED\(3),
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => '0',
S(2) => \icount_out0_carry__0_i_1_n_0\,
S(1) => \icount_out0_carry__0_i_2_n_0\,
S(0) => \icount_out0_carry__0_i_3_n_0\
);
\icount_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^icount_out_reg[6]_0\,
I1 => \^tx_occ_msb_1\,
O => \icount_out0_carry__0_i_1_n_0\
);
\icount_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^icount_out_reg[5]_0\,
I1 => \^icount_out_reg[6]_0\,
O => \icount_out0_carry__0_i_2_n_0\
);
\icount_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^icount_out_reg[4]_0\,
I1 => \^icount_out_reg[5]_0\,
O => \icount_out0_carry__0_i_3_n_0\
);
icount_out0_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^icount_out_reg[1]_0\,
O => icount_out0_carry_i_1_n_0
);
icount_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^icount_out_reg[3]_0\,
I1 => \^icount_out_reg[4]_0\,
O => icount_out0_carry_i_2_n_0
);
icount_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^icount_out_reg[2]_0\,
I1 => \^icount_out_reg[3]_0\,
O => icount_out0_carry_i_3_n_0
);
icount_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^icount_out_reg[1]_0\,
I1 => \^icount_out_reg[2]_0\,
O => icount_out0_carry_i_4_n_0
);
\icount_out[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => \^tx_fifo_count\(0),
I1 => bus2ip_reset_ipif_inverted,
I2 => \icount_out_reg[7]_0\,
I3 => \icount_out_reg[7]_1\,
O => \icount_out[0]_i_1_n_0\
);
\icount_out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => icount_out0_carry_n_7,
I1 => bus2ip_reset_ipif_inverted,
I2 => \icount_out_reg[7]_0\,
I3 => \icount_out_reg[7]_1\,
O => \icount_out[1]_i_1_n_0\
);
\icount_out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => icount_out0_carry_n_6,
I1 => bus2ip_reset_ipif_inverted,
I2 => \icount_out_reg[7]_0\,
I3 => \icount_out_reg[7]_1\,
O => \icount_out[2]_i_1_n_0\
);
\icount_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => icount_out0_carry_n_5,
I1 => bus2ip_reset_ipif_inverted,
I2 => \icount_out_reg[7]_0\,
I3 => \icount_out_reg[7]_1\,
O => \icount_out[3]_i_1_n_0\
);
\icount_out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => icount_out0_carry_n_4,
I1 => bus2ip_reset_ipif_inverted,
I2 => \icount_out_reg[7]_0\,
I3 => \icount_out_reg[7]_1\,
O => \icount_out[4]_i_1_n_0\
);
\icount_out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \icount_out0_carry__0_n_7\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \icount_out_reg[7]_0\,
I3 => \icount_out_reg[7]_1\,
O => \icount_out[5]_i_1_n_0\
);
\icount_out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \icount_out0_carry__0_n_6\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \icount_out_reg[7]_0\,
I3 => \icount_out_reg[7]_1\,
O => \icount_out[6]_i_1_n_0\
);
\icount_out[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \icount_out0_carry__0_n_5\,
I1 => bus2ip_reset_ipif_inverted,
I2 => \icount_out_reg[7]_0\,
I3 => \icount_out_reg[7]_1\,
O => \icount_out[7]_i_2_n_0\
);
\icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \icount_out_reg[0]_0\,
D => \icount_out[0]_i_1_n_0\,
Q => \^tx_fifo_count\(0),
R => '0'
);
\icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \icount_out_reg[0]_0\,
D => \icount_out[1]_i_1_n_0\,
Q => \^icount_out_reg[1]_0\,
R => '0'
);
\icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \icount_out_reg[0]_0\,
D => \icount_out[2]_i_1_n_0\,
Q => \^icount_out_reg[2]_0\,
R => '0'
);
\icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \icount_out_reg[0]_0\,
D => \icount_out[3]_i_1_n_0\,
Q => \^icount_out_reg[3]_0\,
R => '0'
);
\icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \icount_out_reg[0]_0\,
D => \icount_out[4]_i_1_n_0\,
Q => \^icount_out_reg[4]_0\,
R => '0'
);
\icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \icount_out_reg[0]_0\,
D => \icount_out[5]_i_1_n_0\,
Q => \^icount_out_reg[5]_0\,
R => '0'
);
\icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \icount_out_reg[0]_0\,
D => \icount_out[6]_i_1_n_0\,
Q => \^icount_out_reg[6]_0\,
R => '0'
);
\icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \icount_out_reg[0]_0\,
D => \icount_out[7]_i_2_n_0\,
Q => \^tx_occ_msb_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cross_clk_sync_fifo_1 is
port (
spisel_d1_reg_to_axi_clk : out STD_LOGIC;
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0\ : out STD_LOGIC;
spicr_0_loop_to_spi_clk : out STD_LOGIC;
SPICR_2_MST_N_SLV_to_spi_clk : out STD_LOGIC;
spicr_3_cpol_to_spi_clk : out STD_LOGIC;
spicr_4_cpha_to_spi_clk : out STD_LOGIC;
spicr_9_lsb_to_spi_clk : out STD_LOGIC;
register_Data_slvsel_int : out STD_LOGIC;
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_1\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_2\ : out STD_LOGIC;
spiXfer_done_to_axi_1 : out STD_LOGIC;
Tx_FIFO_Empty_intr : out STD_LOGIC;
tx_occ_msb : out STD_LOGIC;
\s_axi4_wdata[7]\ : out STD_LOGIC;
\s_axi4_wdata[5]\ : out STD_LOGIC;
R : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_0\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_1\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
rst : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2_0\ : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
reset2ip_reset_int : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
empty : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
spicr_0_loop_frm_axi_clk : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
spicr_9_lsb_frm_axi_clk : in STD_LOGIC;
spicr_bits_7_8_frm_axi_clk : in STD_LOGIC_VECTOR ( 1 downto 0 );
SPISSR_frm_axi_clk : in STD_LOGIC;
D01_out : in STD_LOGIC;
D0 : in STD_LOGIC;
icount_out0_carry : in STD_LOGIC;
IP2Bus_WrAck_transmit_enable : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ : in STD_LOGIC;
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\ : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0\ : in STD_LOGIC;
Tx_FIFO_Full_i : in STD_LOGIC;
Tx_FIFO_Full_int : in STD_LOGIC;
tx_fifo_count_d2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
spiXfer_done_to_axi_d1 : in STD_LOGIC;
tx_occ_msb_4 : in STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ : in STD_LOGIC;
p_1_in16_in : in STD_LOGIC;
p_1_in22_in : in STD_LOGIC;
Count_trigger : in STD_LOGIC;
Ratio_Count : in STD_LOGIC;
transfer_start_d1 : in STD_LOGIC;
\SS_O_reg[0]\ : in STD_LOGIC;
transfer_start_reg : in STD_LOGIC;
serial_dout_int : in STD_LOGIC;
io1_i_sync : in STD_LOGIC;
io0_i_sync : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cross_clk_sync_fifo_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cross_clk_sync_fifo_1 is
signal \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0\ : STD_LOGIC;
signal \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0\ : STD_LOGIC;
signal \^logic_generation_fdr.tx_empt_4_spisr_s2ax_2_0\ : STD_LOGIC;
signal \^logic_generation_fdr.drr_overrun_int_cdc_from_spi_int_2_reg_0\ : STD_LOGIC;
signal \^logic_generation_fdr.spixfer_done_cdc_from_spi_int_2_reg_0\ : STD_LOGIC;
signal SPICR_0_LOOP_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_1_SPE_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : STD_LOGIC;
signal \^spicr_2_mst_n_slv_to_spi_clk\ : STD_LOGIC;
signal SPICR_3_CPOL_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_4_CPHA_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_7_SS_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_9_LSB_cdc_from_axi_d1 : STD_LOGIC;
signal SPICR_bits_7_8_cdc_from_axi_d1_0 : STD_LOGIC;
signal SPICR_bits_7_8_cdc_from_axi_d1_1 : STD_LOGIC;
signal SPISSR_cdc_from_axi_d1 : STD_LOGIC;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d1 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d2 : STD_LOGIC;
signal drr_Overrun_int_cdc_from_spi_d3 : STD_LOGIC;
signal \^register_data_slvsel_int\ : STD_LOGIC;
signal reset_RcFIFO_ptr_cdc_from_axi_d1 : STD_LOGIC;
signal reset_RcFIFO_ptr_cdc_from_axi_d2 : STD_LOGIC;
signal spiXfer_done_d1 : STD_LOGIC;
signal spiXfer_done_d2 : STD_LOGIC;
signal spiXfer_done_d3 : STD_LOGIC;
signal \^spicr_0_loop_to_spi_clk\ : STD_LOGIC;
signal spicr_1_spe_to_spi_clk : STD_LOGIC;
signal \^spicr_3_cpol_to_spi_clk\ : STD_LOGIC;
signal \^spicr_4_cpha_to_spi_clk\ : STD_LOGIC;
signal spicr_7_ss_to_spi_clk : STD_LOGIC;
signal spicr_8_tr_inhibit_to_spi_clk : STD_LOGIC;
signal spicr_bits_7_8_to_spi_clk : STD_LOGIC_VECTOR ( 0 to 1 );
signal spisel_d1_reg_cdc_from_spi_d1 : STD_LOGIC;
signal spisel_pulse_cdc_from_spi_d1 : STD_LOGIC;
signal spisel_pulse_cdc_from_spi_d2 : STD_LOGIC;
signal spisel_pulse_cdc_from_spi_d3 : STD_LOGIC;
signal transfer_start_i_2_n_0 : STD_LOGIC;
signal tx_FIFO_Empty_d1_i_2_n_0 : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\ : label is "VCC:CE";
attribute box_type : string;
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_2\ : label is "PRIMITIVE";
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : label is "VCC:CE";
attribute box_type of \LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_3\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_3\ : label is "soft_lutpair35";
begin
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ <= \^logic_generation_fdr.tx_empt_4_spisr_s2ax_2_0\;
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0\ <= \^logic_generation_fdr.drr_overrun_int_cdc_from_spi_int_2_reg_0\;
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0\ <= \^logic_generation_fdr.spixfer_done_cdc_from_spi_int_2_reg_0\;
SPICR_2_MST_N_SLV_to_spi_clk <= \^spicr_2_mst_n_slv_to_spi_clk\;
register_Data_slvsel_int <= \^register_data_slvsel_int\;
spicr_0_loop_to_spi_clk <= \^spicr_0_loop_to_spi_clk\;
spicr_3_cpol_to_spi_clk <= \^spicr_3_cpol_to_spi_clk\;
spicr_4_cpha_to_spi_clk <= \^spicr_4_cpha_to_spi_clk\;
\FIFO_EXISTS.RX_FIFO_II_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BE"
)
port map (
I0 => Rst_to_spi,
I1 => reset_RcFIFO_ptr_cdc_from_axi_d2,
I2 => reset_RcFIFO_ptr_cdc_from_axi_d1,
O => rst
);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF90"
)
port map (
I0 => spiXfer_done_d3,
I1 => spiXfer_done_d2,
I2 => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0\,
I3 => bus2ip_reset_ipif_inverted,
I4 => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
I5 => spicr_6_rxfifo_rst_frm_axi_clk,
O => \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_1\
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00090009000F0000"
)
port map (
I0 => spiXfer_done_d3,
I1 => spiXfer_done_d2,
I2 => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\,
I3 => reset2ip_reset_int,
I4 => Tx_FIFO_Full_i,
I5 => Tx_FIFO_Full_int,
O => \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_2\
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.spiXfer_done_to_axi_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => spiXfer_done_d3,
I1 => spiXfer_done_d2,
O => spiXfer_done_to_axi_1
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"78FFFF78"
)
port map (
I0 => s_axi4_wdata(0),
I1 => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\,
I2 => p_1_in22_in,
I3 => drr_Overrun_int_cdc_from_spi_d3,
I4 => drr_Overrun_int_cdc_from_spi_d2,
O => \s_axi4_wdata[5]\
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"78FFFF78"
)
port map (
I0 => s_axi4_wdata(1),
I1 => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\,
I2 => p_1_in16_in,
I3 => spisel_pulse_cdc_from_spi_d3,
I4 => spisel_pulse_cdc_from_spi_d2,
O => \s_axi4_wdata[7]\
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \^logic_generation_fdr.drr_overrun_int_cdc_from_spi_int_2_reg_0\,
Q => drr_Overrun_int_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => drr_Overrun_int_cdc_from_spi_d1,
Q => drr_Overrun_int_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.DRR_OVERRUN_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => drr_Overrun_int_cdc_from_spi_d2,
Q => drr_Overrun_int_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0\,
Q => reset_RcFIFO_ptr_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.RX_FIFO_RST_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => reset_RcFIFO_ptr_cdc_from_axi_d1,
Q => reset_RcFIFO_ptr_cdc_from_axi_d2,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_0_loop_frm_axi_clk,
Q => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_0_LOOP_cdc_from_axi_d1,
Q => \^spicr_0_loop_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_1_spe_frm_axi_clk,
Q => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_1_SPE_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_1_SPE_cdc_from_axi_d1,
Q => spicr_1_spe_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_2_mst_n_slv_frm_axi_clk,
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
Q => \^spicr_2_mst_n_slv_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_3_cpol_frm_axi_clk,
Q => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_3_CPOL_cdc_from_axi_d1,
Q => \^spicr_3_cpol_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_4_cpha_frm_axi_clk,
Q => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_4_CPHA_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_4_CPHA_cdc_from_axi_d1,
Q => \^spicr_4_cpha_to_spi_clk\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_7_ss_frm_axi_clk,
Q => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_7_SS_cdc_from_axi_d1,
Q => spicr_7_ss_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_8_tr_inhibit_frm_axi_clk,
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_8_TR_INHIBIT_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
Q => spicr_8_tr_inhibit_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_9_lsb_frm_axi_clk,
Q => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_9_LSB_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_9_LSB_cdc_from_axi_d1,
Q => spicr_9_lsb_to_spi_clk,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_bits_7_8_frm_axi_clk(0),
Q => SPICR_bits_7_8_cdc_from_axi_d1_0,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[0].SPICR_BITS_7_8_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_bits_7_8_cdc_from_axi_d1_0,
Q => spicr_bits_7_8_to_spi_clk(1),
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => spicr_bits_7_8_frm_axi_clk(1),
Q => SPICR_bits_7_8_cdc_from_axi_d1_1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_BITS_7_8_SYNC_GEN[1].SPICR_BITS_7_8_AX2S_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPICR_bits_7_8_cdc_from_axi_d1_1,
Q => spicr_bits_7_8_to_spi_clk(0),
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0\,
I1 => spicr_6_rxfifo_rst_frm_axi_clk,
O => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0\
);
\LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_i_1_n_0\,
Q => \LOGIC_GENERATION_FDR.SPICR_RX_FIFO_Rst_en_d1_reg_n_0\,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => '1',
Q => spisel_d1_reg_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_D1_REG_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => spisel_d1_reg_cdc_from_spi_d1,
Q => spisel_d1_reg_to_axi_clk,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => '0',
Q => spisel_pulse_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => spisel_pulse_cdc_from_spi_d1,
Q => spisel_pulse_cdc_from_spi_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISEL_PULSE_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => spisel_pulse_cdc_from_spi_d2,
Q => spisel_pulse_cdc_from_spi_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_AX2S_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPISSR_frm_axi_clk,
Q => SPISSR_cdc_from_axi_d1,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SPISSR_SYNC_GEN[0].SPISSR_SYNC_AXI_2_SPI_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SPISSR_cdc_from_axi_d1,
Q => \^register_data_slvsel_int\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \^logic_generation_fdr.spixfer_done_cdc_from_spi_int_2_reg_0\,
Q => spiXfer_done_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => spiXfer_done_d1,
Q => spiXfer_done_d2,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => spiXfer_done_d2,
Q => spiXfer_done_d3,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_1_CDC\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => empty,
Q => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => Tx_FIFO_Empty_SPISR_cdc_from_spi_d1,
Q => \^logic_generation_fdr.tx_empt_4_spisr_s2ax_2_0\,
R => reset2ip_reset_int
);
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => D0,
Q => \^logic_generation_fdr.drr_overrun_int_cdc_from_spi_int_2_reg_0\,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => D01_out,
Q => \^logic_generation_fdr.spixfer_done_cdc_from_spi_int_2_reg_0\,
R => Rst_to_spi
);
\RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^spicr_2_mst_n_slv_to_spi_clk\,
O => R
);
\RISING_EDGE_CLK_RATIO_4_GEN.Serial_Din_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => serial_dout_int,
I1 => \^spicr_0_loop_to_spi_clk\,
I2 => io1_i_sync,
I3 => \^spicr_2_mst_n_slv_to_spi_clk\,
I4 => io0_i_sync,
O => D(0)
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000F600"
)
port map (
I0 => \^spicr_3_cpol_to_spi_clk\,
I1 => \^spicr_4_cpha_to_spi_clk\,
I2 => Count_trigger,
I3 => \^spicr_2_mst_n_slv_to_spi_clk\,
I4 => Ratio_Count,
O => \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^spicr_3_cpol_to_spi_clk\,
I1 => \^spicr_4_cpha_to_spi_clk\,
O => \LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_1\
);
SPI_TRISTATE_CONTROL_III_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => spicr_bits_7_8_to_spi_clk(0),
I1 => \^spicr_0_loop_to_spi_clk\,
I2 => spicr_bits_7_8_to_spi_clk(1),
O => D_0
);
\SS_O[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF15"
)
port map (
I0 => spicr_7_ss_to_spi_clk,
I1 => transfer_start_d1,
I2 => \SS_O_reg[0]\,
I3 => \^register_data_slvsel_int\,
I4 => Rst_to_spi,
O => \LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2_0\
);
icount_out0_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"AA96"
)
port map (
I0 => icount_out0_carry,
I1 => spiXfer_done_d3,
I2 => spiXfer_done_d2,
I3 => IP2Bus_WrAck_transmit_enable,
O => S(0)
);
\icount_out[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFF96"
)
port map (
I0 => IP2Bus_WrAck_transmit_enable,
I1 => spiXfer_done_d3,
I2 => spiXfer_done_d2,
I3 => bus2ip_reset_ipif_inverted,
I4 => \FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\,
I5 => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\,
O => \LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0\
);
transfer_start_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00002F20"
)
port map (
I0 => \SS_O_reg[0]\,
I1 => transfer_start_i_2_n_0,
I2 => \^spicr_2_mst_n_slv_to_spi_clk\,
I3 => spicr_1_spe_to_spi_clk,
I4 => Rst_to_spi,
O => \LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0\
);
transfer_start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FF8F"
)
port map (
I0 => transfer_start_reg,
I1 => empty,
I2 => spicr_1_spe_to_spi_clk,
I3 => spicr_8_tr_inhibit_to_spi_clk,
O => transfer_start_i_2_n_0
);
tx_FIFO_Empty_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => tx_fifo_count_d2(1),
I1 => tx_fifo_count_d2(2),
I2 => tx_fifo_count_d2(0),
I3 => tx_fifo_count_d2(4),
I4 => tx_FIFO_Empty_d1_i_2_n_0,
O => Tx_FIFO_Empty_intr
);
tx_FIFO_Empty_d1_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEFFFFFFFFFF"
)
port map (
I0 => tx_fifo_count_d2(6),
I1 => tx_fifo_count_d2(3),
I2 => tx_fifo_count_d2(7),
I3 => \^logic_generation_fdr.tx_empt_4_spisr_s2ax_2_0\,
I4 => tx_fifo_count_d2(5),
I5 => spiXfer_done_to_axi_d1,
O => tx_FIFO_Empty_d1_i_2_n_0
);
tx_FIFO_Occpncy_MSB_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => tx_occ_msb_4,
I1 => \^logic_generation_fdr.tx_empt_4_spisr_s2ax_2_0\,
O => tx_occ_msb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control is
port (
irpt_wrack_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : out STD_LOGIC;
p_1_in34_in : out STD_LOGIC;
p_1_in31_in : out STD_LOGIC;
p_1_in28_in : out STD_LOGIC;
p_1_in25_in : out STD_LOGIC;
p_1_in22_in : out STD_LOGIC;
p_1_in19_in : out STD_LOGIC;
p_1_in16_in : out STD_LOGIC;
p_1_in13_in : out STD_LOGIC;
irpt_rdack_d1 : out STD_LOGIC;
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
intr2bus_wrack_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_fwft.gdvld_fwft.data_valid_fwft_reg\ : out STD_LOGIC;
intr2bus_rdack_reg_0 : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
\ip_irpt_enable_reg_reg[8]_0\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
reset2ip_reset_int : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0\ : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg_0 : in STD_LOGIC;
ip2bus_error_int : in STD_LOGIC;
wrack : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole : in STD_LOGIC;
ip2Bus_WrAck_core_reg : in STD_LOGIC;
burst_tr_int : in STD_LOGIC;
s_axi4_rready : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi4_rdata_i_reg[31]\ : in STD_LOGIC;
data_valid : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole : in STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0\ : in STD_LOGIC;
rc_FIFO_Full_d1 : in STD_LOGIC;
scndry_out : in STD_LOGIC;
empty : in STD_LOGIC;
tx_FIFO_Empty_d1 : in STD_LOGIC;
Tx_FIFO_Empty_intr : in STD_LOGIC;
tx_occ_msb_4 : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
tx_FIFO_Occpncy_MSB_d1 : in STD_LOGIC;
\ip_irpt_enable_reg_reg[8]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control is
signal \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \^gen_fwft.gdvld_fwft.data_valid_fwft_reg\ : STD_LOGIC;
signal intr_ip2bus_rdack : STD_LOGIC;
signal intr_ip2bus_wrack : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_1_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_2_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_3_n_0 : STD_LOGIC;
signal ip2intc_irpt_INST_0_i_4_n_0 : STD_LOGIC;
signal \^ip_irpt_enable_reg_reg[8]_0\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_1_in13_in\ : STD_LOGIC;
signal \^p_1_in16_in\ : STD_LOGIC;
signal \^p_1_in19_in\ : STD_LOGIC;
signal \^p_1_in22_in\ : STD_LOGIC;
signal \^p_1_in25_in\ : STD_LOGIC;
signal \^p_1_in28_in\ : STD_LOGIC;
signal \^p_1_in31_in\ : STD_LOGIC;
signal \^p_1_in34_in\ : STD_LOGIC;
begin
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ <= \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\;
\gen_fwft.gdvld_fwft.data_valid_fwft_reg\ <= \^gen_fwft.gdvld_fwft.data_valid_fwft_reg\;
\ip_irpt_enable_reg_reg[8]_0\(8 downto 0) <= \^ip_irpt_enable_reg_reg[8]_0\(8 downto 0);
p_0_in(0) <= \^p_0_in\(0);
p_1_in13_in <= \^p_1_in13_in\;
p_1_in16_in <= \^p_1_in16_in\;
p_1_in19_in <= \^p_1_in19_in\;
p_1_in22_in <= \^p_1_in22_in\;
p_1_in25_in <= \^p_1_in25_in\;
p_1_in28_in <= \^p_1_in28_in\;
p_1_in31_in <= \^p_1_in31_in\;
p_1_in34_in <= \^p_1_in34_in\;
\FSM_onehot_axi_full_sm_ps[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => intr_ip2bus_rdack,
I1 => ip2Bus_RdAck_core_reg,
I2 => ip2Bus_RdAck_intr_reg_hole,
O => intr2bus_rdack_reg_0
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1\,
Q => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0\,
Q => \^p_1_in34_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"78FF7878"
)
port map (
I0 => s_axi4_wdata(2),
I1 => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0\,
I2 => \^p_1_in31_in\,
I3 => tx_FIFO_Empty_d1,
I4 => Tx_FIFO_Empty_intr,
O => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_1_n_0\,
Q => \^p_1_in31_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0\,
Q => \^p_1_in28_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7878787878FF7878"
)
port map (
I0 => s_axi4_wdata(4),
I1 => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0\,
I2 => \^p_1_in25_in\,
I3 => rc_FIFO_Full_d1,
I4 => scndry_out,
I5 => empty,
O => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[4].GEN_REG_STATUS.ip_irpt_status_reg[4]_i_1_n_0\,
Q => \^p_1_in25_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0\,
Q => \^p_1_in22_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF78FF78787878"
)
port map (
I0 => s_axi4_wdata(6),
I1 => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0\,
I2 => \^p_1_in19_in\,
I3 => tx_occ_msb_4,
I4 => Tx_FIFO_Empty_SPISR_to_axi_clk,
I5 => tx_FIFO_Occpncy_MSB_d1,
O => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\
);
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg[6]_i_1_n_0\,
Q => \^p_1_in19_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0\,
Q => \^p_1_in16_in\,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0\,
Q => \^p_1_in13_in\,
R => reset2ip_reset_int
);
awready_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFEFFFFFFFE"
)
port map (
I0 => ip2bus_error_int,
I1 => intr_ip2bus_wrack,
I2 => wrack,
I3 => ip2Bus_WrAck_intr_reg_hole,
I4 => ip2Bus_WrAck_core_reg,
I5 => burst_tr_int,
O => intr2bus_wrack_reg_0
);
intr2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => intr2bus_rdack0,
Q => intr_ip2bus_rdack,
R => reset2ip_reset_int
);
intr2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => interrupt_wrce_strb,
Q => intr_ip2bus_wrack,
R => reset2ip_reset_int
);
ip2intc_irpt_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA8AAAA"
)
port map (
I0 => \^p_0_in\(0),
I1 => ip2intc_irpt_INST_0_i_1_n_0,
I2 => ip2intc_irpt_INST_0_i_2_n_0,
I3 => ip2intc_irpt_INST_0_i_3_n_0,
I4 => ip2intc_irpt_INST_0_i_4_n_0,
O => ip2intc_irpt
);
ip2intc_irpt_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[8]_0\(2),
I1 => \^p_1_in31_in\,
I2 => \^ip_irpt_enable_reg_reg[8]_0\(0),
I3 => \^gen_ip_irpt_status_reg[0].gen_reg_status.ip_irpt_status_reg_reg[0]_0\,
O => ip2intc_irpt_INST_0_i_1_n_0
);
ip2intc_irpt_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[8]_0\(8),
I1 => \^p_1_in13_in\,
I2 => \^ip_irpt_enable_reg_reg[8]_0\(1),
I3 => \^p_1_in34_in\,
O => ip2intc_irpt_INST_0_i_2_n_0
);
ip2intc_irpt_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[8]_0\(4),
I1 => \^p_1_in25_in\,
I2 => \^ip_irpt_enable_reg_reg[8]_0\(5),
I3 => \^p_1_in22_in\,
O => ip2intc_irpt_INST_0_i_3_n_0
);
ip2intc_irpt_INST_0_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^ip_irpt_enable_reg_reg[8]_0\(3),
I1 => \^p_1_in28_in\,
I2 => \^p_1_in19_in\,
I3 => \^ip_irpt_enable_reg_reg[8]_0\(6),
I4 => \^p_1_in16_in\,
I5 => \^ip_irpt_enable_reg_reg[8]_0\(7),
O => ip2intc_irpt_INST_0_i_4_n_0
);
\ip_irpt_enable_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => s_axi4_wdata(0),
Q => \^ip_irpt_enable_reg_reg[8]_0\(0),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => s_axi4_wdata(1),
Q => \^ip_irpt_enable_reg_reg[8]_0\(1),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => s_axi4_wdata(2),
Q => \^ip_irpt_enable_reg_reg[8]_0\(2),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => s_axi4_wdata(3),
Q => \^ip_irpt_enable_reg_reg[8]_0\(3),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => s_axi4_wdata(4),
Q => \^ip_irpt_enable_reg_reg[8]_0\(4),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => s_axi4_wdata(5),
Q => \^ip_irpt_enable_reg_reg[8]_0\(5),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => s_axi4_wdata(6),
Q => \^ip_irpt_enable_reg_reg[8]_0\(6),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => s_axi4_wdata(7),
Q => \^ip_irpt_enable_reg_reg[8]_0\(7),
R => reset2ip_reset_int
);
\ip_irpt_enable_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \ip_irpt_enable_reg_reg[8]_1\(0),
D => D(0),
Q => \^ip_irpt_enable_reg_reg[8]_0\(8),
R => reset2ip_reset_int
);
ipif_glbl_irpt_enable_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => ipif_glbl_irpt_enable_reg_reg_0,
Q => \^p_0_in\(0),
R => reset2ip_reset_int
);
irpt_rdack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => irpt_rdack,
Q => irpt_rdack_d1,
R => reset2ip_reset_int
);
irpt_wrack_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => irpt_wrack,
Q => irpt_wrack_d1,
R => reset2ip_reset_int
);
\s_axi4_rdata_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi4_rready,
I1 => \^gen_fwft.gdvld_fwft.data_valid_fwft_reg\,
I2 => Q(0),
O => E(0)
);
\s_axi4_rdata_i[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => \s_axi4_rdata_i_reg[31]\,
I1 => data_valid,
I2 => intr_ip2bus_rdack,
I3 => ip2Bus_RdAck_core_reg,
I4 => ip2Bus_RdAck_intr_reg_hole,
I5 => ip2bus_error_int,
O => \^gen_fwft.gdvld_fwft.data_valid_fwft_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_address_decoder is
port (
start : out STD_LOGIC;
p_1_in : out STD_LOGIC;
p_2_in : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0\ : out STD_LOGIC;
Bus_RNW_reg_reg_0 : out STD_LOGIC;
Bus_RNW_reg_reg_1 : out STD_LOGIC;
Bus_RNW_reg_reg_2 : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg_reg_3 : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]_0\ : out STD_LOGIC;
ip2Bus_WrAck_core_reg0 : out STD_LOGIC;
wr_ce_or_reduce_core_cmb : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : out STD_LOGIC;
\FSM_onehot_axi_full_sm_ps_reg[0]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_wvalid_0 : out STD_LOGIC;
Bus_RNW_reg_reg_4 : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
Transmit_ip2bus_error0 : out STD_LOGIC;
IP2Bus_WrAck_transmit_enable : out STD_LOGIC;
\length_cntr_reg[6]\ : out STD_LOGIC;
rd_en : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_1\ : out STD_LOGIC;
\length_cntr_reg[2]\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0\ : out STD_LOGIC;
bus2ip_wrce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
\ip_irpt_enable_reg_reg[1]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[2]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[3]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[4]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[5]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[6]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[7]\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
irpt_rdack : out STD_LOGIC;
intr2bus_rdack0 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
\bus2ip_BE_reg_reg[3]\ : out STD_LOGIC;
rd_ce_or_reduce_core_cmb : out STD_LOGIC;
intr_controller_rd_ce_or_reduce : out STD_LOGIC;
s_axi4_wdata_0_sp_1 : out STD_LOGIC;
\s_axi4_wdata[31]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : out STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
s_axi4_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi4_arvalid : in STD_LOGIC;
s_axi4_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
ip2Bus_WrAck_core_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
empty : in STD_LOGIC;
ip2Bus_WrAck_core_reg_d1 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
last_data_acked_reg : in STD_LOGIC;
last_data_acked_reg_0 : in STD_LOGIC;
last_data_acked_reg_1 : in STD_LOGIC;
last_data_acked_reg_2 : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi4_awvalid : in STD_LOGIC;
s_axi4_wvalid : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1\ : in STD_LOGIC;
\FSM_onehot_axi_full_sm_ps_reg[3]\ : in STD_LOGIC;
data_valid : in STD_LOGIC;
\FSM_onehot_axi_full_sm_ps_reg[3]_0\ : in STD_LOGIC;
\FSM_onehot_axi_full_sm_ps_reg[3]_1\ : in STD_LOGIC;
\s_axi4_rresp_i_reg[1]\ : in STD_LOGIC;
transmit_ip2bus_error : in STD_LOGIC;
receive_ip2bus_error : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
Tx_FIFO_Full_int : in STD_LOGIC;
almost_full : in STD_LOGIC;
s_axi_wready_i : in STD_LOGIC;
\gwack.wr_ack_i_reg\ : in STD_LOGIC;
\gwack.wr_ack_i_reg_0\ : in STD_LOGIC;
s_axi4_rready : in STD_LOGIC;
\guf.underflow_i_reg\ : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
\FSM_onehot_axi_full_sm_ps_reg[1]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\s_axi4_rdata_i_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
rx_fifo_empty_i : in STD_LOGIC;
spicr_0_loop_frm_axi_clk : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
p_1_in34_in : in STD_LOGIC;
p_1_in31_in : in STD_LOGIC;
p_1_in28_in : in STD_LOGIC;
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
p_1_in25_in : in STD_LOGIC;
p_1_in22_in : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
p_1_in19_in : in STD_LOGIC;
p_1_in16_in : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
p_1_in13_in : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 5 downto 0 );
scndry_out : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
spisel_d1_reg_to_axi_clk : in STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : in STD_LOGIC;
spicr_9_lsb_frm_axi_clk : in STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \^bus_rnw_reg_reg_0\ : STD_LOGIC;
signal \^bus_rnw_reg_reg_4\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\ : STD_LOGIC;
signal \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\ : STD_LOGIC;
signal \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\ : STD_LOGIC;
signal \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2_n_0\ : STD_LOGIC;
signal \^gen_bkend_ce_registers[27].ce_out_i_reg[27]_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_4_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_5_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_10 : STD_LOGIC;
signal ce_expnd_i_11 : STD_LOGIC;
signal ce_expnd_i_12 : STD_LOGIC;
signal ce_expnd_i_13 : STD_LOGIC;
signal ce_expnd_i_14 : STD_LOGIC;
signal ce_expnd_i_15 : STD_LOGIC;
signal ce_expnd_i_16 : STD_LOGIC;
signal ce_expnd_i_17 : STD_LOGIC;
signal ce_expnd_i_18 : STD_LOGIC;
signal ce_expnd_i_19 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_20 : STD_LOGIC;
signal ce_expnd_i_21 : STD_LOGIC;
signal ce_expnd_i_22 : STD_LOGIC;
signal ce_expnd_i_23 : STD_LOGIC;
signal ce_expnd_i_24 : STD_LOGIC;
signal ce_expnd_i_25 : STD_LOGIC;
signal ce_expnd_i_26 : STD_LOGIC;
signal ce_expnd_i_28 : STD_LOGIC;
signal ce_expnd_i_29 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_31 : STD_LOGIC;
signal ce_expnd_i_4 : STD_LOGIC;
signal ce_expnd_i_5 : STD_LOGIC;
signal ce_expnd_i_6 : STD_LOGIC;
signal ce_expnd_i_7 : STD_LOGIC;
signal ce_expnd_i_8 : STD_LOGIC;
signal ce_expnd_i_9 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 : STD_LOGIC;
signal \^length_cntr_reg[2]\ : STD_LOGIC;
signal \^length_cntr_reg[6]\ : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_18_in : STD_LOGIC;
signal p_19_in : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
signal p_20_in : STD_LOGIC;
signal p_21_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_24_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_26_in : STD_LOGIC;
signal p_27_in : STD_LOGIC;
signal p_28_in : STD_LOGIC;
signal p_29_in : STD_LOGIC;
signal \^p_2_in\ : STD_LOGIC;
signal p_30_in : STD_LOGIC;
signal p_31_in : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal \s_axi4_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[0]_i_5_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[1]_i_5_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[2]_i_5_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[3]_i_5_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[5]_i_5_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[8]_i_2_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[8]_i_3_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[8]_i_4_n_0\ : STD_LOGIC;
signal s_axi4_wdata_0_sn_1 : STD_LOGIC;
signal \^s_axi4_wvalid_0\ : STD_LOGIC;
signal \^start\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int[9]_i_1\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of ip2Bus_RdAck_intr_reg_hole_d1_i_1 : label is "soft_lutpair110";
attribute SOFT_HLUTNM of ip2Bus_RdAck_intr_reg_hole_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of ip2Bus_WrAck_intr_reg_hole_d1_i_1 : label is "soft_lutpair106";
attribute SOFT_HLUTNM of ip2Bus_WrAck_intr_reg_hole_i_1 : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \ip_irpt_enable_reg[8]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of irpt_rdack_d1_i_1 : label is "soft_lutpair101";
attribute SOFT_HLUTNM of irpt_wrack_d1_i_1 : label is "soft_lutpair101";
attribute SOFT_HLUTNM of reset_trig_i_1 : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[1]_i_5\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[2]_i_5\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[6]_i_6\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[8]_i_2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[8]_i_3\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[8]_i_4\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \s_axi4_rresp_i[1]_i_1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of sw_rst_cond_d1_i_1 : label is "soft_lutpair97";
begin
Bus_RNW_reg_reg_0 <= \^bus_rnw_reg_reg_0\;
Bus_RNW_reg_reg_4 <= \^bus_rnw_reg_reg_4\;
D(0) <= \^d\(0);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0\ <= \^gen_bkend_ce_registers[27].ce_out_i_reg[27]_0\;
\length_cntr_reg[2]\ <= \^length_cntr_reg[2]\;
\length_cntr_reg[6]\ <= \^length_cntr_reg[6]\;
p_1_in <= \^p_1_in\;
p_2_in <= \^p_2_in\;
s_axi4_wdata_0_sp_1 <= s_axi4_wdata_0_sn_1;
s_axi4_wvalid_0 <= \^s_axi4_wvalid_0\;
start <= \^start\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FF7FAA00"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(0),
I1 => s_axi4_awvalid,
I2 => s_axi4_wvalid,
I3 => s_axi4_arvalid,
I4 => \^bus_rnw_reg_reg_0\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^bus_rnw_reg_reg_0\,
R => '0'
);
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000E200"
)
port map (
I0 => spicr_6_rxfifo_rst_frm_axi_clk,
I1 => ip2Bus_WrAck_core_reg,
I2 => s_axi4_wdata(4),
I3 => p_7_in,
I4 => \^bus_rnw_reg_reg_0\,
I5 => reset2ip_reset_int,
O => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\
);
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000E200"
)
port map (
I0 => spicr_5_txfifo_rst_frm_axi_clk,
I1 => ip2Bus_WrAck_core_reg,
I2 => s_axi4_wdata(3),
I3 => p_7_in,
I4 => \^bus_rnw_reg_reg_0\,
I5 => reset2ip_reset_int,
O => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\
);
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => p_7_in,
I2 => ip2Bus_WrAck_core_reg,
O => Bus_RNW_reg_reg_1
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF00FD"
)
port map (
I0 => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\,
I1 => p_6_in,
I2 => \^gen_bkend_ce_registers[27].ce_out_i_reg[27]_0\,
I3 => \^bus_rnw_reg_reg_0\,
I4 => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\,
O => wr_ce_or_reduce_core_cmb
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => p_12_in,
I1 => p_14_in,
I2 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\,
I3 => p_8_in,
I4 => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\,
O => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF00F2"
)
port map (
I0 => p_5_in,
I1 => almost_full,
I2 => p_3_in,
I3 => \^bus_rnw_reg_reg_0\,
I4 => p_7_in,
O => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^p_2_in\,
I1 => p_10_in,
I2 => p_11_in,
I3 => p_9_in,
I4 => \^p_1_in\,
I5 => p_13_in,
O => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_4_n_0\
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF00FD"
)
port map (
I0 => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\,
I1 => p_6_in,
I2 => \^gen_bkend_ce_registers[27].ce_out_i_reg[27]_0\,
I3 => \^bus_rnw_reg_reg_0\,
I4 => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_3_n_0\,
I5 => ip2Bus_WrAck_core_reg_d1,
O => ip2Bus_WrAck_core_reg0
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFD00"
)
port map (
I0 => \ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_i_2_n_0\,
I1 => p_5_in,
I2 => p_15_in,
I3 => \^bus_rnw_reg_reg_0\,
I4 => \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2_n_0\,
O => rd_ce_or_reduce_core_cmb
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCC8"
)
port map (
I0 => p_7_in,
I1 => \^bus_rnw_reg_reg_0\,
I2 => p_3_in,
I3 => p_6_in,
O => \ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_i_2_n_0\
);
\FIFO_EXISTS.RX_FIFO_II_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F2000000"
)
port map (
I0 => s_axi4_rready,
I1 => \guf.underflow_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(2),
I3 => \^bus_rnw_reg_reg_0\,
I4 => \^gen_bkend_ce_registers[27].ce_out_i_reg[27]_0\,
I5 => empty,
O => rd_en
);
\FSM_onehot_axi_full_sm_ps[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^length_cntr_reg[2]\,
I1 => \FSM_onehot_axi_full_sm_ps_reg[1]\(6),
I2 => \FSM_onehot_axi_full_sm_ps_reg[1]\(5),
I3 => \FSM_onehot_axi_full_sm_ps_reg[1]\(7),
I4 => \FSM_onehot_axi_full_sm_ps_reg[1]\(4),
O => \^length_cntr_reg[6]\
);
\FSM_onehot_axi_full_sm_ps[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF80000"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg[3]\,
I1 => data_valid,
I2 => \FSM_onehot_axi_full_sm_ps_reg[3]_0\,
I3 => \^bus_rnw_reg_reg_4\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(2),
I5 => \FSM_onehot_axi_full_sm_ps_reg[3]_1\,
O => \^d\(0)
);
\FSM_onehot_axi_full_sm_ps[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFBBBFBF"
)
port map (
I0 => \^length_cntr_reg[6]\,
I1 => s_axi4_wvalid,
I2 => s_axi_wready_i,
I3 => almost_full,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(4),
O => \^s_axi4_wvalid_0\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0044034700000000"
)
port map (
I0 => s_axi4_araddr(0),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(0),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0\,
O => ce_expnd_i_31
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_31,
Q => p_31_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000088808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\,
I2 => s_axi4_awaddr(2),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
O => ce_expnd_i_21
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_21,
Q => p_21_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008880800000000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
I2 => s_axi4_awaddr(2),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\,
O => ce_expnd_i_20
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_20,
Q => p_20_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00088808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I2 => s_axi4_awaddr(4),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(4),
O => ce_expnd_i_19
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_19,
Q => p_19_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"202A000A20200000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
I1 => s_axi4_araddr(1),
I2 => s_axi4_arvalid,
I3 => s_axi4_awaddr(1),
I4 => s_axi4_araddr(2),
I5 => s_axi4_awaddr(2),
O => ce_expnd_i_18
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_18,
Q => p_18_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A80800000000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I1 => s_axi4_awaddr(2),
I2 => s_axi4_arvalid,
I3 => s_axi4_araddr(2),
I4 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
I5 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\,
O => ce_expnd_i_17
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi4_araddr(0),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(0),
O => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"5050300000003000"
)
port map (
I0 => s_axi4_araddr(4),
I1 => s_axi4_awaddr(4),
I2 => \^start\,
I3 => s_axi4_awaddr(1),
I4 => s_axi4_arvalid,
I5 => s_axi4_araddr(1),
O => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_17,
Q => p_17_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C000A0A0C0000000"
)
port map (
I0 => s_axi4_awaddr(1),
I1 => s_axi4_araddr(1),
I2 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
I3 => s_axi4_araddr(2),
I4 => s_axi4_arvalid,
I5 => s_axi4_awaddr(2),
O => ce_expnd_i_16
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000008080800080"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I2 => \^start\,
I3 => s_axi4_awaddr(4),
I4 => s_axi4_arvalid,
I5 => s_axi4_araddr(4),
O => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_16,
Q => p_16_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"22200020"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I2 => s_axi4_awaddr(4),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(4),
O => ce_expnd_i_15
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_15,
Q => p_15_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"80888000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\,
I2 => s_axi4_araddr(0),
I3 => s_axi4_arvalid,
I4 => s_axi4_awaddr(0),
O => ce_expnd_i_14
);
\GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_14,
Q => p_14_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000440347"
)
port map (
I0 => s_axi4_araddr(0),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(0),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\,
O => ce_expnd_i_13
);
\GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_13,
Q => p_13_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi4_araddr(2),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(2),
I3 => s_axi4_araddr(0),
I4 => s_axi4_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\,
O => ce_expnd_i_12
);
\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_12,
Q => p_12_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"202A000A20200000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0\,
I1 => s_axi4_araddr(2),
I2 => s_axi4_arvalid,
I3 => s_axi4_awaddr(2),
I4 => s_axi4_araddr(0),
I5 => s_axi4_awaddr(0),
O => \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1_n_0\,
Q => p_30_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"22200020"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I2 => s_axi4_awaddr(4),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(4),
O => ce_expnd_i_11
);
\GEN_BKEND_CE_REGISTERS[20].ce_out_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_11,
Q => p_11_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"80888000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\,
I2 => s_axi4_araddr(0),
I3 => s_axi4_arvalid,
I4 => s_axi4_awaddr(0),
O => ce_expnd_i_10
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000C0A0A000C0"
)
port map (
I0 => s_axi4_araddr(4),
I1 => s_axi4_awaddr(4),
I2 => \^start\,
I3 => s_axi4_awaddr(3),
I4 => s_axi4_arvalid,
I5 => s_axi4_araddr(3),
O => \GEN_BKEND_CE_REGISTERS[21].ce_out_i[21]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[21].ce_out_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_10,
Q => p_10_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[22].ce_out_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi4_araddr(0),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(0),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\,
O => ce_expnd_i_9
);
\GEN_BKEND_CE_REGISTERS[22].ce_out_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_9,
Q => p_9_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000B8308800"
)
port map (
I0 => s_axi4_araddr(0),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(0),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\,
O => ce_expnd_i_8
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFFFFFFFDFFF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I2 => \^start\,
I3 => s_axi4_awaddr(4),
I4 => s_axi4_arvalid,
I5 => s_axi4_araddr(4),
O => \GEN_BKEND_CE_REGISTERS[23].ce_out_i[23]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[23].ce_out_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_8,
Q => p_8_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8080000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0\,
I1 => s_axi4_awaddr(4),
I2 => s_axi4_arvalid,
I3 => s_axi4_araddr(4),
I4 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
O => ce_expnd_i_7
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000440347"
)
port map (
I0 => s_axi4_araddr(1),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(1),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[24].ce_out_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_7,
Q => p_7_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"80888000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3_n_0\,
I2 => s_axi4_araddr(0),
I3 => s_axi4_arvalid,
I4 => s_axi4_awaddr(0),
O => ce_expnd_i_6
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi4_awaddr(2),
I1 => s_axi4_araddr(2),
I2 => s_axi4_awaddr(1),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(1),
O => \GEN_BKEND_CE_REGISTERS[25].ce_out_i[25]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[25].ce_out_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_6,
Q => p_6_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[26].ce_out_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000440347"
)
port map (
I0 => s_axi4_araddr(0),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(0),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0\,
O => ce_expnd_i_5
);
\GEN_BKEND_CE_REGISTERS[26].ce_out_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_5,
Q => p_5_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi4_araddr(2),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(2),
I3 => s_axi4_araddr(0),
I4 => s_axi4_awaddr(0),
I5 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0\,
O => ce_expnd_i_4
);
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_4,
Q => \^gen_bkend_ce_registers[27].ce_out_i_reg[27]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A8080000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0\,
I1 => s_axi4_awaddr(4),
I2 => s_axi4_arvalid,
I3 => s_axi4_araddr(4),
I4 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi4_araddr(1),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(1),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
O => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi4_araddr(3),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(3),
O => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[28].ce_out_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_3,
Q => p_3_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"80888000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3_n_0\,
I2 => s_axi4_araddr(0),
I3 => s_axi4_arvalid,
I4 => s_axi4_awaddr(0),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi4_awaddr(2),
I1 => s_axi4_araddr(2),
I2 => s_axi4_awaddr(1),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(1),
O => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0AAC00000000000"
)
port map (
I0 => s_axi4_awaddr(3),
I1 => s_axi4_araddr(3),
I2 => s_axi4_araddr(4),
I3 => s_axi4_arvalid,
I4 => s_axi4_awaddr(4),
I5 => \^start\,
O => \GEN_BKEND_CE_REGISTERS[29].ce_out_i[29]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[29].ce_out_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_2,
Q => \^p_2_in\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000002A2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\,
I1 => s_axi4_awaddr(2),
I2 => s_axi4_arvalid,
I3 => s_axi4_araddr(2),
I4 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
I5 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
O => ce_expnd_i_29
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_29,
Q => p_29_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[30].ce_out_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => s_axi4_araddr(0),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(0),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0\,
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_1,
Q => \^p_1_in\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBABABA"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_4_n_0\,
I1 => \^s_axi4_wvalid_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(4),
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(5),
I5 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_5_n_0\,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(0),
I1 => s_axi4_awvalid,
I2 => s_axi4_wvalid,
I3 => s_axi4_arvalid,
O => \^start\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000B8308800"
)
port map (
I0 => s_axi4_araddr(0),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(0),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0\,
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \^bus_rnw_reg_reg_4\,
I1 => \FSM_onehot_axi_full_sm_ps_reg[3]_0\,
I2 => data_valid,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(2),
O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_4_n_0\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"4F4FFF4F"
)
port map (
I0 => \^length_cntr_reg[6]\,
I1 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(1),
I2 => s_axi4_aresetn,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(3),
I4 => s_axi4_rready,
O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_5_n_0\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"777FFF7FFFFFFFFF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0\,
I1 => \^start\,
I2 => s_axi4_awaddr(4),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(4),
I5 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_6_n_0\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi4_araddr(1),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(1),
O => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0\
);
\GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[31].ce_out_i_reg_n_0_[31]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000002A20000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
I1 => s_axi4_awaddr(2),
I2 => s_axi4_arvalid,
I3 => s_axi4_araddr(2),
I4 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\,
I5 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
O => ce_expnd_i_28
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_28,
Q => p_28_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"202A000A20200000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0\,
I1 => s_axi4_araddr(0),
I2 => s_axi4_arvalid,
I3 => s_axi4_awaddr(0),
I4 => s_axi4_araddr(2),
I5 => s_axi4_awaddr(2),
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0\,
Q => p_27_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A800A0080800000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0\,
I1 => s_axi4_araddr(0),
I2 => s_axi4_arvalid,
I3 => s_axi4_awaddr(0),
I4 => s_axi4_araddr(2),
I5 => s_axi4_awaddr(2),
O => ce_expnd_i_26
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004700"
)
port map (
I0 => s_axi4_araddr(4),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(4),
I3 => \^start\,
I4 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I5 => \GEN_BKEND_CE_REGISTERS[31].ce_out_i[31]_i_7_n_0\,
O => \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_26,
Q => p_26_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000E20000"
)
port map (
I0 => s_axi4_awaddr(2),
I1 => s_axi4_arvalid,
I2 => s_axi4_araddr(2),
I3 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
I4 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\,
I5 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
O => ce_expnd_i_25
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_25,
Q => p_25_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A8080000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_3_n_0\,
I1 => s_axi4_awaddr(2),
I2 => s_axi4_arvalid,
I3 => s_axi4_araddr(2),
I4 => \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_2_n_0\,
I5 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
O => ce_expnd_i_24
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_24,
Q => p_24_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00088808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[24].ce_out_i[24]_i_2_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[28].ce_out_i[28]_i_3_n_0\,
I2 => s_axi4_awaddr(4),
I3 => s_axi4_arvalid,
I4 => s_axi4_araddr(4),
O => ce_expnd_i_23
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_23,
Q => p_23_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0044034700000000"
)
port map (
I0 => s_axi4_araddr(1),
I1 => s_axi4_arvalid,
I2 => s_axi4_awaddr(1),
I3 => s_axi4_araddr(2),
I4 => s_axi4_awaddr(2),
I5 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => ce_expnd_i_22
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \^start\,
D => ce_expnd_i_22,
Q => p_22_in,
R => cs_ce_clr
);
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA6AAAAAAAAA"
)
port map (
I0 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
I1 => Q(0),
I2 => p_23_in,
I3 => \^bus_rnw_reg_reg_0\,
I4 => irpt_wrack_d1,
I5 => s_axi4_wdata(0),
O => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\
);
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA6AAAAAAAAA"
)
port map (
I0 => p_1_in34_in,
I1 => Q(0),
I2 => p_23_in,
I3 => \^bus_rnw_reg_reg_0\,
I4 => irpt_wrack_d1,
I5 => s_axi4_wdata(1),
O => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\
);
\GEN_IP_IRPT_STATUS_REG[2].GEN_REG_STATUS.ip_irpt_status_reg[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => Q(0),
I1 => p_23_in,
I2 => \^bus_rnw_reg_reg_0\,
I3 => irpt_wrack_d1,
O => \bus2ip_BE_reg_reg[3]\
);
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAA6AAAAAAAAA"
)
port map (
I0 => p_1_in28_in,
I1 => Q(0),
I2 => p_23_in,
I3 => \^bus_rnw_reg_reg_0\,
I4 => irpt_wrack_d1,
I5 => s_axi4_wdata(2),
O => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\
);
\SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_7_in,
I1 => \^bus_rnw_reg_reg_0\,
O => bus2ip_wrce_int(0)
);
\SPISSR_WR_GEN[0].SPISSR_Data_reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFF2000"
)
port map (
I0 => s_axi4_wdata(0),
I1 => \^bus_rnw_reg_reg_0\,
I2 => p_3_in,
I3 => ip2Bus_WrAck_core_reg,
I4 => SPISSR_frm_axi_clk,
O => s_axi4_wdata_0_sn_1
);
Transmit_ip2bus_error_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404000004000"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => p_5_in,
I2 => Tx_FIFO_Full_int,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(4),
I4 => almost_full,
I5 => s_axi_wready_i,
O => Transmit_ip2bus_error0
);
intr2bus_rdack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"4400440044004000"
)
port map (
I0 => irpt_rdack_d1,
I1 => \^bus_rnw_reg_reg_0\,
I2 => p_24_in,
I3 => Q(0),
I4 => p_21_in,
I5 => p_23_in,
O => intr2bus_rdack0
);
intr2bus_wrack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000505000005040"
)
port map (
I0 => irpt_wrack_d1,
I1 => p_21_in,
I2 => Q(0),
I3 => p_23_in,
I4 => \^bus_rnw_reg_reg_0\,
I5 => p_24_in,
O => interrupt_wrce_strb
);
ip2Bus_RdAck_intr_reg_hole_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
O => intr_controller_rd_ce_or_reduce
);
ip2Bus_RdAck_intr_reg_hole_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
I2 => ip2Bus_RdAck_intr_reg_hole_d1,
O => ip2Bus_RdAck_intr_reg_hole0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
O => Bus_RNW_reg_reg_3
);
ip2Bus_WrAck_intr_reg_hole_d1_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0,
I1 => ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0,
I2 => p_17_in,
I3 => p_25_in,
I4 => p_20_in,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => p_16_in,
I1 => p_31_in,
I2 => p_28_in,
I3 => p_19_in,
I4 => p_29_in,
I5 => p_30_in,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0
);
ip2Bus_WrAck_intr_reg_hole_d1_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_26_in,
I1 => p_18_in,
I2 => p_27_in,
I3 => p_22_in,
O => ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0
);
ip2Bus_WrAck_intr_reg_hole_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0,
I2 => ip2Bus_WrAck_intr_reg_hole_d1,
O => ip2Bus_WrAck_intr_reg_hole0
);
\ip_irpt_enable_reg[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => Q(0),
I2 => p_21_in,
O => Bus_RNW_reg_reg_2(0)
);
ipif_glbl_irpt_enable_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFF2000"
)
port map (
I0 => s_axi4_wdata(5),
I1 => \^bus_rnw_reg_reg_0\,
I2 => p_24_in,
I3 => Q(0),
I4 => p_0_in(0),
O => \s_axi4_wdata[31]\
);
irpt_rdack_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"A0A0A080"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => p_24_in,
I2 => Q(0),
I3 => p_21_in,
I4 => p_23_in,
O => irpt_rdack
);
irpt_wrack_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00CC00C8"
)
port map (
I0 => p_21_in,
I1 => Q(0),
I2 => p_23_in,
I3 => \^bus_rnw_reg_reg_0\,
I4 => p_24_in,
O => irpt_wrack
);
last_data_acked_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAA88A8"
)
port map (
I0 => last_data_acked_reg,
I1 => last_data_acked_reg_0,
I2 => \^d\(0),
I3 => last_data_acked_reg_1,
I4 => last_data_acked_reg_2,
I5 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(0),
O => \FSM_onehot_axi_full_sm_ps_reg[0]\
);
\length_cntr[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg[1]\(2),
I1 => \FSM_onehot_axi_full_sm_ps_reg[1]\(3),
I2 => \FSM_onehot_axi_full_sm_ps_reg[1]\(0),
I3 => \FSM_onehot_axi_full_sm_ps_reg[1]\(1),
O => \^length_cntr_reg[2]\
);
reset_trig_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => p_15_in,
I2 => \s_axi4_rresp_i_reg[1]\,
I3 => sw_rst_cond_d1,
O => reset_trig0
);
\s_axi4_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF40000000"
)
port map (
I0 => p_23_in,
I1 => p_21_in,
I2 => Q(0),
I3 => \^bus_rnw_reg_reg_0\,
I4 => \s_axi4_rdata_i_reg[8]\(0),
I5 => \s_axi4_rdata_i[0]_i_4_n_0\,
O => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0\
);
\s_axi4_rdata_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF8F8F8F8F8F8F8"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_4_n_0\,
I1 => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
I2 => \s_axi4_rdata_i[0]_i_5_n_0\,
I3 => SPISSR_frm_axi_clk,
I4 => p_3_in,
I5 => \^bus_rnw_reg_reg_0\,
O => \s_axi4_rdata_i[0]_i_4_n_0\
);
\s_axi4_rdata_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00A800A800A800"
)
port map (
I0 => p_6_in,
I1 => empty,
I2 => rx_fifo_empty_i,
I3 => \^bus_rnw_reg_reg_0\,
I4 => p_7_in,
I5 => spicr_0_loop_frm_axi_clk,
O => \s_axi4_rdata_i[0]_i_5_n_0\
);
\s_axi4_rdata_i[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF4F4F4"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_2_n_0\,
I1 => \s_axi4_rdata_i_reg[8]\(1),
I2 => \s_axi4_rdata_i[1]_i_5_n_0\,
I3 => p_1_in34_in,
I4 => \s_axi4_rdata_i[8]_i_4_n_0\,
O => \ip_irpt_enable_reg_reg[1]\
);
\s_axi4_rdata_i[1]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => p_6_in,
I1 => scndry_out,
I2 => \^bus_rnw_reg_reg_0\,
I3 => p_7_in,
I4 => spicr_1_spe_frm_axi_clk,
O => \s_axi4_rdata_i[1]_i_5_n_0\
);
\s_axi4_rdata_i[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF4F4F4"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_2_n_0\,
I1 => \s_axi4_rdata_i_reg[8]\(2),
I2 => \s_axi4_rdata_i[2]_i_5_n_0\,
I3 => p_1_in31_in,
I4 => \s_axi4_rdata_i[8]_i_4_n_0\,
O => \ip_irpt_enable_reg_reg[2]\
);
\s_axi4_rdata_i[2]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => p_6_in,
I1 => Tx_FIFO_Empty_SPISR_to_axi_clk,
I2 => \^bus_rnw_reg_reg_0\,
I3 => p_7_in,
I4 => spicr_2_mst_n_slv_frm_axi_clk,
O => \s_axi4_rdata_i[2]_i_5_n_0\
);
\s_axi4_rdata_i[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"1000000000000000"
)
port map (
I0 => p_23_in,
I1 => p_21_in,
I2 => \^bus_rnw_reg_reg_0\,
I3 => p_24_in,
I4 => Q(0),
I5 => p_0_in(0),
O => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1\(2)
);
\s_axi4_rdata_i[3]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF4F4F4"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_2_n_0\,
I1 => \s_axi4_rdata_i_reg[8]\(3),
I2 => \s_axi4_rdata_i[3]_i_5_n_0\,
I3 => p_1_in28_in,
I4 => \s_axi4_rdata_i[8]_i_4_n_0\,
O => \ip_irpt_enable_reg_reg[3]\
);
\s_axi4_rdata_i[3]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => p_6_in,
I1 => Tx_FIFO_Full_int,
I2 => \^bus_rnw_reg_reg_0\,
I3 => p_7_in,
I4 => spicr_3_cpol_frm_axi_clk,
O => \s_axi4_rdata_i[3]_i_5_n_0\
);
\s_axi4_rdata_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF44F444F444F4"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_2_n_0\,
I1 => \s_axi4_rdata_i_reg[8]\(4),
I2 => spicr_4_cpha_frm_axi_clk,
I3 => \s_axi4_rdata_i[8]_i_3_n_0\,
I4 => p_1_in25_in,
I5 => \s_axi4_rdata_i[8]_i_4_n_0\,
O => \ip_irpt_enable_reg_reg[4]\
);
\s_axi4_rdata_i[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF4F4F4"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_2_n_0\,
I1 => \s_axi4_rdata_i_reg[8]\(5),
I2 => \s_axi4_rdata_i[5]_i_5_n_0\,
I3 => p_1_in22_in,
I4 => \s_axi4_rdata_i[8]_i_4_n_0\,
O => \ip_irpt_enable_reg_reg[5]\
);
\s_axi4_rdata_i[5]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => p_6_in,
I1 => spisel_d1_reg_to_axi_clk,
I2 => \^bus_rnw_reg_reg_0\,
I3 => p_7_in,
I4 => spicr_5_txfifo_rst_frm_axi_clk,
O => \s_axi4_rdata_i[5]_i_5_n_0\
);
\s_axi4_rdata_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF44F444F444F4"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_2_n_0\,
I1 => \s_axi4_rdata_i_reg[8]\(6),
I2 => spicr_6_rxfifo_rst_frm_axi_clk,
I3 => \s_axi4_rdata_i[8]_i_3_n_0\,
I4 => p_1_in19_in,
I5 => \s_axi4_rdata_i[8]_i_4_n_0\,
O => \ip_irpt_enable_reg_reg[6]\
);
\s_axi4_rdata_i[6]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^p_1_in\,
I1 => empty,
I2 => \^bus_rnw_reg_reg_0\,
O => \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]_0\
);
\s_axi4_rdata_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"777777777F777F7F"
)
port map (
I0 => \^gen_bkend_ce_registers[27].ce_out_i_reg[27]_0\,
I1 => \^bus_rnw_reg_reg_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(2),
I3 => \guf.underflow_i_reg\,
I4 => s_axi4_rready,
I5 => ip2Bus_RdAck_core_reg,
O => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_1\
);
\s_axi4_rdata_i[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"F444F444FFFFF444"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_2_n_0\,
I1 => \s_axi4_rdata_i_reg[8]\(7),
I2 => p_1_in16_in,
I3 => \s_axi4_rdata_i[8]_i_4_n_0\,
I4 => spicr_7_ss_frm_axi_clk,
I5 => \s_axi4_rdata_i[8]_i_3_n_0\,
O => \ip_irpt_enable_reg_reg[7]\
);
\s_axi4_rdata_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF44F444F444F4"
)
port map (
I0 => \s_axi4_rdata_i[8]_i_2_n_0\,
I1 => \s_axi4_rdata_i_reg[8]\(8),
I2 => spicr_8_tr_inhibit_frm_axi_clk,
I3 => \s_axi4_rdata_i[8]_i_3_n_0\,
I4 => p_1_in13_in,
I5 => \s_axi4_rdata_i[8]_i_4_n_0\,
O => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1\(0)
);
\s_axi4_rdata_i[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BFFF"
)
port map (
I0 => p_23_in,
I1 => p_21_in,
I2 => Q(0),
I3 => \^bus_rnw_reg_reg_0\,
O => \s_axi4_rdata_i[8]_i_2_n_0\
);
\s_axi4_rdata_i[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => p_7_in,
O => \s_axi4_rdata_i[8]_i_3_n_0\
);
\s_axi4_rdata_i[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => p_23_in,
I2 => Q(0),
O => \s_axi4_rdata_i[8]_i_4_n_0\
);
\s_axi4_rdata_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => spicr_9_lsb_frm_axi_clk,
I1 => p_7_in,
I2 => \^bus_rnw_reg_reg_0\,
O => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1\(1)
);
\s_axi4_rresp_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF40"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => p_15_in,
I2 => \s_axi4_rresp_i_reg[1]\,
I3 => transmit_ip2bus_error,
I4 => receive_ip2bus_error,
O => \^bus_rnw_reg_reg_4\
);
sw_rst_cond_d1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \s_axi4_rresp_i_reg[1]\,
I1 => p_15_in,
I2 => \^bus_rnw_reg_reg_0\,
O => sw_rst_cond
);
\xpm_fifo_instance.xpm_fifo_async_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000040004040400"
)
port map (
I0 => \^bus_rnw_reg_reg_0\,
I1 => p_5_in,
I2 => almost_full,
I3 => ip2Bus_WrAck_core_reg,
I4 => \gwack.wr_ack_i_reg\,
I5 => \gwack.wr_ack_i_reg_0\,
O => IP2Bus_WrAck_transmit_enable
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_cntrl_reg is
port (
spicr_bits_7_8_frm_axi_clk : out STD_LOGIC_VECTOR ( 1 downto 0 );
spicr_0_loop_frm_axi_clk : out STD_LOGIC;
spicr_1_spe_frm_axi_clk : out STD_LOGIC;
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0\ : out STD_LOGIC;
spicr_3_cpol_frm_axi_clk : out STD_LOGIC;
spicr_4_cpha_frm_axi_clk : out STD_LOGIC;
spicr_7_ss_frm_axi_clk : out STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : out STD_LOGIC;
spicr_9_lsb_frm_axi_clk : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\ : out STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : out STD_LOGIC;
\s_axi4_wdata[8]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
reset2ip_reset_int : in STD_LOGIC;
bus2ip_wrce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_aclk : in STD_LOGIC;
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\ : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_1\ : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ : in STD_LOGIC;
\ip_irpt_enable_reg_reg[8]\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\ : in STD_LOGIC;
p_1_in13_in : in STD_LOGIC;
data_Exists_RcFIFO_int_d1 : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_cntrl_reg;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_cntrl_reg is
signal \^control_reg_5_9_generate[7].spicr_data_int_reg[7]_0\ : STD_LOGIC;
signal \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2\ : label is "soft_lutpair34";
attribute box_type : string;
attribute box_type of \SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I\ : label is "PRIMITIVE";
attribute box_type of \SPICR_REG_78_GENERATE[8].SPI_TRISTATE_CONTROL_I\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \ip_irpt_enable_reg[8]_i_2\ : label is "soft_lutpair34";
begin
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0\ <= \^control_reg_5_9_generate[7].spicr_data_int_reg[7]_0\;
\CONTROL_REG_1_2_GENERATE[1].SPICR_data_int_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi4_aclk,
CE => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\,
D => s_axi4_wdata(6),
Q => spicr_8_tr_inhibit_frm_axi_clk,
S => reset2ip_reset_int
);
\CONTROL_REG_1_2_GENERATE[2].SPICR_data_int_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi4_aclk,
CE => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\,
D => s_axi4_wdata(5),
Q => spicr_7_ss_frm_axi_clk,
S => reset2ip_reset_int
);
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\,
Q => spicr_6_rxfifo_rst_frm_axi_clk,
R => '0'
);
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_1\,
Q => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\,
R => '0'
);
\CONTROL_REG_5_9_GENERATE[5].SPICR_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\,
D => s_axi4_wdata(4),
Q => spicr_4_cpha_frm_axi_clk,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[6].SPICR_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\,
D => s_axi4_wdata(3),
Q => spicr_3_cpol_frm_axi_clk,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\,
D => s_axi4_wdata(2),
Q => \^control_reg_5_9_generate[7].spicr_data_int_reg[7]_0\,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[8].SPICR_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\,
D => s_axi4_wdata(1),
Q => spicr_1_spe_frm_axi_clk,
R => reset2ip_reset_int
);
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\,
D => s_axi4_wdata(0),
Q => spicr_0_loop_frm_axi_clk,
R => reset2ip_reset_int
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFD5FF2A00"
)
port map (
I0 => s_axi4_wdata(6),
I1 => \^control_reg_5_9_generate[7].spicr_data_int_reg[7]_0\,
I2 => \ip_irpt_enable_reg_reg[8]\,
I3 => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\,
I4 => p_1_in13_in,
I5 => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0\,
O => \s_axi4_wdata[8]\
);
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0111"
)
port map (
I0 => data_Exists_RcFIFO_int_d1,
I1 => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0\,
I2 => \^control_reg_5_9_generate[7].spicr_data_int_reg[7]_0\,
I3 => \ip_irpt_enable_reg_reg[8]\,
O => \GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg[8]_i_2_n_0\
);
\SPICR_REG_78_GENERATE[7].SPI_TRISTATE_CONTROL_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => bus2ip_wrce_int(0),
D => s_axi4_wdata(2),
Q => spicr_bits_7_8_frm_axi_clk(1),
R => reset2ip_reset_int
);
\SPICR_REG_78_GENERATE[8].SPI_TRISTATE_CONTROL_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => bus2ip_wrce_int(0),
D => s_axi4_wdata(1),
Q => spicr_bits_7_8_frm_axi_clk(0),
R => reset2ip_reset_int
);
\SPICR_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\,
D => s_axi4_wdata(7),
Q => spicr_9_lsb_frm_axi_clk,
R => reset2ip_reset_int
);
\ip_irpt_enable_reg[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => s_axi4_wdata(6),
I1 => \^control_reg_5_9_generate[7].spicr_data_int_reg[7]_0\,
I2 => \ip_irpt_enable_reg_reg[8]\,
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_fifo_ifmodule is
port (
rc_FIFO_Full_d1 : out STD_LOGIC;
tx_FIFO_Empty_d1 : out STD_LOGIC;
receive_ip2bus_error : out STD_LOGIC;
transmit_ip2bus_error : out STD_LOGIC;
tx_FIFO_Occpncy_MSB_d1 : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
Rx_FIFO_Full_Fifo_d1_synced_i : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
Tx_FIFO_Empty_intr : in STD_LOGIC;
Transmit_ip2bus_error0 : in STD_LOGIC;
tx_occ_msb : in STD_LOGIC;
Receive_ip2bus_error_reg_0 : in STD_LOGIC;
prmry_in : in STD_LOGIC;
p_4_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_fifo_ifmodule;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_fifo_ifmodule is
signal Receive_ip2bus_error0 : STD_LOGIC;
begin
Receive_ip2bus_error_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"E000"
)
port map (
I0 => Receive_ip2bus_error_reg_0,
I1 => prmry_in,
I2 => p_4_in,
I3 => Bus_RNW_reg,
O => Receive_ip2bus_error0
);
Receive_ip2bus_error_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => Receive_ip2bus_error0,
Q => receive_ip2bus_error,
R => reset2ip_reset_int
);
Transmit_ip2bus_error_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => Transmit_ip2bus_error0,
Q => transmit_ip2bus_error,
R => reset2ip_reset_int
);
rc_FIFO_Full_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => Rx_FIFO_Full_Fifo_d1_synced_i,
Q => rc_FIFO_Full_d1,
R => reset2ip_reset_int
);
tx_FIFO_Empty_d1_reg: unisim.vcomponents.FDSE
port map (
C => s_axi4_aclk,
CE => '1',
D => Tx_FIFO_Empty_intr,
Q => tx_FIFO_Empty_d1,
S => reset2ip_reset_int
);
tx_FIFO_Occpncy_MSB_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_occ_msb,
Q => tx_FIFO_Occpncy_MSB_d1,
R => reset2ip_reset_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_mode_0_module is
port (
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
ss_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_o : out STD_LOGIC;
transfer_start_d1 : out STD_LOGIC;
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0\ : out STD_LOGIC;
spiXfer_done_int : out STD_LOGIC;
Ratio_Count : out STD_LOGIC;
Count_trigger : out STD_LOGIC;
io1_o : out STD_LOGIC;
serial_dout_int : out STD_LOGIC;
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
D01_out : out STD_LOGIC;
D0 : out STD_LOGIC;
rd_en : out STD_LOGIC;
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ : out STD_LOGIC;
din : out STD_LOGIC_VECTOR ( 7 downto 0 );
D_0 : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
R : in STD_LOGIC;
Rst_to_spi : in STD_LOGIC;
empty : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
transfer_start_reg_0 : in STD_LOGIC;
\SS_O_reg[0]_0\ : in STD_LOGIC;
SPICR_2_MST_N_SLV_to_spi_clk : in STD_LOGIC;
\OTHER_RATIO_GENERATE.Serial_Dout_reg_0\ : in STD_LOGIC;
\OTHER_RATIO_GENERATE.sck_o_int_reg_0\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\ : in STD_LOGIC;
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\ : in STD_LOGIC;
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_1\ : in STD_LOGIC;
spicr_9_lsb_to_spi_clk : in STD_LOGIC;
spicr_4_cpha_to_spi_clk : in STD_LOGIC;
spicr_3_cpol_to_spi_clk : in STD_LOGIC;
dout : in STD_LOGIC_VECTOR ( 7 downto 0 );
scndry_out : in STD_LOGIC;
almost_full : in STD_LOGIC;
spicr_0_loop_to_spi_clk : in STD_LOGIC;
register_Data_slvsel_int : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_mode_0_module;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_mode_0_module is
signal Count : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^count_trigger\ : STD_LOGIC;
signal Count_trigger_d1 : STD_LOGIC;
signal DRR_Overrun_reg_int0 : STD_LOGIC;
signal \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0\ : STD_LOGIC;
signal \^logic_generation_fdr.spicr_0_loop_ax2s_2\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[2]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[3]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count[4]_i_3_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Serial_Dout_i_5_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0\ : STD_LOGIC;
signal \OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0\ : STD_LOGIC;
signal \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0\ : STD_LOGIC;
signal \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0\ : STD_LOGIC;
signal \^ratio_count\ : STD_LOGIC;
signal SCK_O_1 : STD_LOGIC;
signal SPIXfer_done_int_d1 : STD_LOGIC;
signal SPIXfer_done_int_pulse_d1 : STD_LOGIC;
signal SR_5_Tx_Empty_d1 : STD_LOGIC;
signal SR_5_Tx_comeplete_Empty : STD_LOGIC;
signal SR_5_Tx_comeplete_Empty_i_1_n_0 : STD_LOGIC;
signal \SS_O[0]_i_3_n_0\ : STD_LOGIC;
signal \SS_O[0]_i_4_n_0\ : STD_LOGIC;
signal Sync_Set : STD_LOGIC;
signal drr_Overrun_int : STD_LOGIC;
signal \^io1_o\ : STD_LOGIC;
signal load : STD_LOGIC;
signal p_19_in : STD_LOGIC;
signal \p_2_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_3_in : STD_LOGIC;
signal rx_shft_reg_mode_0011 : STD_LOGIC_VECTOR ( 0 to 7 );
signal rx_shft_reg_mode_00110 : STD_LOGIC;
signal rx_shft_reg_mode_0110 : STD_LOGIC_VECTOR ( 0 to 7 );
signal rx_shft_reg_mode_01100 : STD_LOGIC;
signal sck_d1 : STD_LOGIC;
signal sck_d2 : STD_LOGIC;
signal sck_o_int : STD_LOGIC;
signal \^spixfer_done_int\ : STD_LOGIC;
signal spi_cntrl_ps : STD_LOGIC_VECTOR ( 1 downto 0 );
signal stop_clock : STD_LOGIC;
signal stop_clock_reg : STD_LOGIC;
signal \^transfer_start_d1\ : STD_LOGIC;
signal transfer_start_reg_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1\ : label is "soft_lutpair79";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg[0]\ : label is "transfer_okay:01,temp_transfer_okay:10,idle:00";
attribute FSM_ENCODED_STATES of \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg[1]\ : label is "transfer_okay:01,temp_transfer_okay:10,idle:00";
attribute SOFT_HLUTNM of \LOCAL_TX_EMPTY_FIFO_12_GEN.DRR_Overrun_reg_int_i_1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_i_1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[0]_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[1]_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[2]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[3]_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count[4]_i_3\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Count_trigger_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.Serial_Dout_i_5\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \OTHER_RATIO_GENERATE.sck_o_int_i_3\ : label is "soft_lutpair75";
attribute IOB : string;
attribute IOB of \RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST\ : label is "TRUE";
attribute box_type : string;
attribute box_type of \RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of SPIXfer_done_int_pulse_d1_i_1 : label is "soft_lutpair77";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of SPI_TRISTATE_CONTROL_II : label is "FD";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of SPI_TRISTATE_CONTROL_II : label is "VCC:CE GND:R";
attribute box_type of SPI_TRISTATE_CONTROL_II : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of SPI_TRISTATE_CONTROL_III : label is "FD";
attribute XILINX_TRANSFORM_PINMAP of SPI_TRISTATE_CONTROL_III : label is "VCC:CE GND:R";
attribute box_type of SPI_TRISTATE_CONTROL_III : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of SPI_TRISTATE_CONTROL_IV : label is "FD";
attribute XILINX_TRANSFORM_PINMAP of SPI_TRISTATE_CONTROL_IV : label is "VCC:CE GND:R";
attribute box_type of SPI_TRISTATE_CONTROL_IV : label is "PRIMITIVE";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of SPI_TRISTATE_CONTROL_V : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of SPI_TRISTATE_CONTROL_V : label is "FD";
attribute XILINX_TRANSFORM_PINMAP of SPI_TRISTATE_CONTROL_V : label is "VCC:CE GND:R";
attribute box_type of SPI_TRISTATE_CONTROL_V : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \SS_O[0]_i_3\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \SS_O[0]_i_4\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \xpm_fifo_instance.xpm_fifo_async_inst_i_3\ : label is "soft_lutpair83";
begin
Count_trigger <= \^count_trigger\;
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ <= \^logic_generation_fdr.spicr_0_loop_ax2s_2\;
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0\ <= \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\;
Ratio_Count <= \^ratio_count\;
io1_o <= \^io1_o\;
spiXfer_done_int <= \^spixfer_done_int\;
transfer_start_d1 <= \^transfer_start_d1\;
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0008000FFF08"
)
port map (
I0 => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
I2 => empty,
I3 => spi_cntrl_ps(1),
I4 => spi_cntrl_ps(0),
I5 => SR_5_Tx_comeplete_Empty,
O => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0\
);
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => transfer_start_reg_n_0,
I1 => \^transfer_start_d1\,
O => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\
);
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0\,
I1 => \^spixfer_done_int\,
I2 => register_Data_slvsel_int,
I3 => spi_cntrl_ps(0),
O => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0\
);
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000022AA0CCC0000"
)
port map (
I0 => empty,
I1 => SR_5_Tx_comeplete_Empty,
I2 => spicr_0_loop_to_spi_clk,
I3 => \^spixfer_done_int\,
I4 => spi_cntrl_ps(1),
I5 => spi_cntrl_ps(0),
O => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_2_n_0\
);
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_1_n_0\,
Q => spi_cntrl_ps(0),
R => Rst_to_spi
);
\FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps_reg[1]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[1]_i_1_n_0\,
Q => spi_cntrl_ps(1),
R => Rst_to_spi
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.DRR_Overrun_reg_int_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => scndry_out,
I1 => almost_full,
I2 => \^spixfer_done_int\,
I3 => drr_Overrun_int,
O => DRR_Overrun_reg_int0
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.DRR_Overrun_reg_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => DRR_Overrun_reg_int0,
Q => drr_Overrun_int,
R => Rst_to_spi
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^logic_generation_fdr.spicr_0_loop_ax2s_2\,
O => stop_clock
);
\LOCAL_TX_EMPTY_FIFO_12_GEN.stop_clock_reg_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => stop_clock,
Q => stop_clock_reg,
R => Rst_to_spi
);
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => drr_Overrun_int,
I1 => \LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\,
O => D0
);
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^spixfer_done_int\,
I1 => \LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\,
O => D01_out
);
\OTHER_RATIO_GENERATE.Count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
O => Count(0)
);
\OTHER_RATIO_GENERATE.Count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
O => Count(1)
);
\OTHER_RATIO_GENERATE.Count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
O => \OTHER_RATIO_GENERATE.Count[2]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
O => \OTHER_RATIO_GENERATE.Count[3]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => SPICR_2_MST_N_SLV_to_spi_clk,
I1 => transfer_start_reg_n_0,
I2 => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
I3 => Rst_to_spi,
O => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"14"
)
port map (
I0 => load,
I1 => Count_trigger_d1,
I2 => \^count_trigger\,
O => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\
);
\OTHER_RATIO_GENERATE.Count[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
O => \OTHER_RATIO_GENERATE.Count[4]_i_3_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => Count(0),
Q => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => Count(1),
Q => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => \OTHER_RATIO_GENERATE.Count[2]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => \OTHER_RATIO_GENERATE.Count[3]_i_1_n_0\,
Q => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Count[4]_i_2_n_0\,
D => \OTHER_RATIO_GENERATE.Count[4]_i_3_n_0\,
Q => load,
R => \OTHER_RATIO_GENERATE.Count[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_trigger_d1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^count_trigger\,
I1 => transfer_start_reg_n_0,
I2 => Rst_to_spi,
O => \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_trigger_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Count_trigger_d1_i_1_n_0\,
Q => Count_trigger_d1,
R => '0'
);
\OTHER_RATIO_GENERATE.Count_trigger_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0090"
)
port map (
I0 => \^count_trigger\,
I1 => \^ratio_count\,
I2 => transfer_start_reg_n_0,
I3 => Rst_to_spi,
O => \OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Count_trigger_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Count_trigger_i_1_n_0\,
Q => \^count_trigger\,
R => '0'
);
\OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => transfer_start_reg_n_0,
I1 => Rst_to_spi,
I2 => \^ratio_count\,
O => \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Ratio_Count_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Ratio_Count[0]_i_1_n_0\,
Q => \^ratio_count\,
R => '0'
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_3_in,
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => \OTHER_RATIO_GENERATE.Serial_Dout_reg_0\,
I3 => \OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0\,
I4 => \^io1_o\,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000454500FF4545"
)
port map (
I0 => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
I1 => empty,
I2 => SR_5_Tx_Empty_d1,
I3 => SPIXfer_done_int_d1,
I4 => SPICR_2_MST_N_SLV_to_spi_clk,
I5 => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7F0000FF7FFF5F"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I1 => \^transfer_start_d1\,
I2 => SPICR_2_MST_N_SLV_to_spi_clk,
I3 => SPIXfer_done_int_d1,
I4 => transfer_start_reg_n_0,
I5 => \OTHER_RATIO_GENERATE.Serial_Dout_i_5_n_0\,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_4_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"000D"
)
port map (
I0 => SR_5_Tx_Empty_d1,
I1 => empty,
I2 => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
I3 => SPICR_2_MST_N_SLV_to_spi_clk,
O => \OTHER_RATIO_GENERATE.Serial_Dout_i_5_n_0\
);
\OTHER_RATIO_GENERATE.Serial_Dout_reg\: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.Serial_Dout_i_1_n_0\,
Q => \^io1_o\,
S => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2800FFFF"
)
port map (
I0 => SPICR_2_MST_N_SLV_to_spi_clk,
I1 => \^count_trigger\,
I2 => Count_trigger_d1,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I4 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
O => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \p_2_in__0\(7),
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => dout(0),
I3 => spicr_9_lsb_to_spi_clk,
I4 => dout(7),
O => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \p_2_in__0\(6),
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => dout(1),
I3 => spicr_9_lsb_to_spi_clk,
I4 => dout(6),
O => \OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \p_2_in__0\(5),
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => dout(2),
I3 => spicr_9_lsb_to_spi_clk,
I4 => dout(5),
O => \OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \p_2_in__0\(4),
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => dout(3),
I3 => spicr_9_lsb_to_spi_clk,
I4 => dout(4),
O => \OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \p_2_in__0\(3),
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => dout(4),
I3 => spicr_9_lsb_to_spi_clk,
I4 => dout(3),
O => \OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \p_2_in__0\(2),
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => dout(5),
I3 => spicr_9_lsb_to_spi_clk,
I4 => dout(2),
O => \OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \p_2_in__0\(1),
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => dout(6),
I3 => spicr_9_lsb_to_spi_clk,
I4 => dout(1),
O => \OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \p_2_in__0\(0),
I1 => \OTHER_RATIO_GENERATE.Serial_Dout_i_2_n_0\,
I2 => dout(7),
I3 => spicr_9_lsb_to_spi_clk,
I4 => dout(0),
O => \OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1_n_0\
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_2_n_0\,
Q => p_3_in,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[1]\: unisim.vcomponents.FDSE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[1]_i_1_n_0\,
Q => \p_2_in__0\(7),
S => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[2]_i_1_n_0\,
Q => \p_2_in__0\(6),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[3]_i_1_n_0\,
Q => \p_2_in__0\(5),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[4]_i_1_n_0\,
Q => \p_2_in__0\(4),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[5]_i_1_n_0\,
Q => \p_2_in__0\(3),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[6]_i_1_n_0\,
Q => \p_2_in__0\(2),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.Shift_Reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => \OTHER_RATIO_GENERATE.Shift_Reg[0]_i_1_n_0\,
D => \OTHER_RATIO_GENERATE.Shift_Reg[7]_i_1_n_0\,
Q => \p_2_in__0\(1),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => sck_d1,
I1 => transfer_start_reg_n_0,
I2 => sck_d2,
O => rx_shft_reg_mode_00110
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_00110,
D => rx_shft_reg_mode_0011(1),
Q => rx_shft_reg_mode_0011(0),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_00110,
D => rx_shft_reg_mode_0011(2),
Q => rx_shft_reg_mode_0011(1),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_00110,
D => rx_shft_reg_mode_0011(3),
Q => rx_shft_reg_mode_0011(2),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_00110,
D => rx_shft_reg_mode_0011(4),
Q => rx_shft_reg_mode_0011(3),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_00110,
D => rx_shft_reg_mode_0011(5),
Q => rx_shft_reg_mode_0011(4),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_00110,
D => rx_shft_reg_mode_0011(6),
Q => rx_shft_reg_mode_0011(5),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_00110,
D => rx_shft_reg_mode_0011(7),
Q => rx_shft_reg_mode_0011(6),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0011_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_00110,
D => D(0),
Q => rx_shft_reg_mode_0011(7),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => sck_d2,
I1 => transfer_start_reg_n_0,
I2 => sck_d1,
O => rx_shft_reg_mode_01100
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_01100,
D => rx_shft_reg_mode_0110(1),
Q => rx_shft_reg_mode_0110(0),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_01100,
D => rx_shft_reg_mode_0110(2),
Q => rx_shft_reg_mode_0110(1),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_01100,
D => rx_shft_reg_mode_0110(3),
Q => rx_shft_reg_mode_0110(2),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_01100,
D => rx_shft_reg_mode_0110(4),
Q => rx_shft_reg_mode_0110(3),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_01100,
D => rx_shft_reg_mode_0110(5),
Q => rx_shft_reg_mode_0110(4),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_01100,
D => rx_shft_reg_mode_0110(6),
Q => rx_shft_reg_mode_0110(5),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_01100,
D => rx_shft_reg_mode_0110(7),
Q => rx_shft_reg_mode_0110(6),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.rx_shft_reg_mode_0110_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => rx_shft_reg_mode_01100,
D => D(0),
Q => rx_shft_reg_mode_0110(7),
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.sck_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => sck_o_int,
Q => sck_d1,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.sck_d2_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => sck_d1,
Q => sck_d2,
R => Rst_to_spi
);
\OTHER_RATIO_GENERATE.sck_o_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F10000000000"
)
port map (
I0 => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
I1 => \FSM_sequential_LOCAL_TX_EMPTY_FIFO_12_GEN.spi_cntrl_ps[0]_i_2_n_0\,
I2 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I3 => SPICR_2_MST_N_SLV_to_spi_clk,
I4 => Rst_to_spi,
I5 => \OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0\,
O => \OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0\
);
\OTHER_RATIO_GENERATE.sck_o_int_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF9FFF60"
)
port map (
I0 => Count_trigger_d1,
I1 => \^count_trigger\,
I2 => transfer_start_reg_n_0,
I3 => Sync_Set,
I4 => sck_o_int,
O => \OTHER_RATIO_GENERATE.sck_o_int_i_2_n_0\
);
\OTHER_RATIO_GENERATE.sck_o_int_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"66660060"
)
port map (
I0 => spicr_4_cpha_to_spi_clk,
I1 => spicr_3_cpol_to_spi_clk,
I2 => transfer_start_reg_n_0,
I3 => \^transfer_start_d1\,
I4 => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
O => Sync_Set
);
\OTHER_RATIO_GENERATE.sck_o_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.sck_o_int_i_1_n_0\,
Q => sck_o_int,
R => '0'
);
\OTHER_RATIO_GENERATE.serial_dout_int_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^io1_o\,
I1 => spicr_0_loop_to_spi_clk,
I2 => Rst_to_spi,
O => \OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0\
);
\OTHER_RATIO_GENERATE.serial_dout_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \OTHER_RATIO_GENERATE.serial_dout_int_i_1_n_0\,
Q => serial_dout_int,
R => '0'
);
\RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => SCK_O_1,
Q => sck_o,
R => R
);
\RATIO_OF_4_GENERATE.SCK_O_EQ_4_NO_STARTUP_USED.SCK_O_EQ_4_FDRE_INST_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC8CCC00008000"
)
port map (
I0 => sck_o_int,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
I2 => transfer_start_reg_n_0,
I3 => \^transfer_start_d1\,
I4 => load,
I5 => spicr_3_cpol_to_spi_clk,
O => SCK_O_1
);
\RISING_EDGE_CLK_RATIO_4_GEN.Serial_Din_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => D(0),
Q => \p_2_in__0\(0),
R => Rst_to_spi
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000000010"
)
port map (
I0 => Rst_to_spi,
I1 => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0\,
I2 => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_1\,
I3 => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
I4 => transfer_start_reg_n_0,
I5 => \^transfer_start_d1\,
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[2]\,
I1 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[0]\,
I2 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[1]\,
I3 => \OTHER_RATIO_GENERATE.Count_reg_n_0_[3]\,
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_2_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_i_1_n_0\,
Q => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
R => '0'
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => SPIXfer_done_int_pulse_d1,
I1 => SPICR_2_MST_N_SLV_to_spi_clk,
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE2CCE233E200E2"
)
port map (
I0 => rx_shft_reg_mode_0011(0),
I1 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I2 => rx_shft_reg_mode_0110(0),
I3 => spicr_9_lsb_to_spi_clk,
I4 => rx_shft_reg_mode_0011(7),
I5 => rx_shft_reg_mode_0110(7),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE2CCE233E200E2"
)
port map (
I0 => rx_shft_reg_mode_0011(1),
I1 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I2 => rx_shft_reg_mode_0110(1),
I3 => spicr_9_lsb_to_spi_clk,
I4 => rx_shft_reg_mode_0011(6),
I5 => rx_shft_reg_mode_0110(6),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE2CCE233E200E2"
)
port map (
I0 => rx_shft_reg_mode_0011(2),
I1 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I2 => rx_shft_reg_mode_0110(2),
I3 => spicr_9_lsb_to_spi_clk,
I4 => rx_shft_reg_mode_0011(5),
I5 => rx_shft_reg_mode_0110(5),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE2CCE233E200E2"
)
port map (
I0 => rx_shft_reg_mode_0011(3),
I1 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I2 => rx_shft_reg_mode_0110(3),
I3 => spicr_9_lsb_to_spi_clk,
I4 => rx_shft_reg_mode_0011(4),
I5 => rx_shft_reg_mode_0110(4),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE2CCE233E200E2"
)
port map (
I0 => rx_shft_reg_mode_0011(4),
I1 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I2 => rx_shft_reg_mode_0110(4),
I3 => spicr_9_lsb_to_spi_clk,
I4 => rx_shft_reg_mode_0011(3),
I5 => rx_shft_reg_mode_0110(3),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE2CCE233E200E2"
)
port map (
I0 => rx_shft_reg_mode_0011(5),
I1 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I2 => rx_shft_reg_mode_0110(5),
I3 => spicr_9_lsb_to_spi_clk,
I4 => rx_shft_reg_mode_0011(2),
I5 => rx_shft_reg_mode_0110(2),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE2CCE233E200E2"
)
port map (
I0 => rx_shft_reg_mode_0011(6),
I1 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I2 => rx_shft_reg_mode_0110(6),
I3 => spicr_9_lsb_to_spi_clk,
I4 => rx_shft_reg_mode_0011(1),
I5 => rx_shft_reg_mode_0110(1),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFE2CCE233E200E2"
)
port map (
I0 => rx_shft_reg_mode_0011(7),
I1 => \OTHER_RATIO_GENERATE.sck_o_int_reg_0\,
I2 => rx_shft_reg_mode_0110(7),
I3 => spicr_9_lsb_to_spi_clk,
I4 => rx_shft_reg_mode_0011(0),
I5 => rx_shft_reg_mode_0110(0),
O => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_2_n_0\,
Q => din(7),
R => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[1]_i_1_n_0\,
Q => din(6),
R => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[2]_i_1_n_0\,
Q => din(5),
R => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[3]_i_1_n_0\,
Q => din(4),
R => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[4]_i_1_n_0\,
Q => din(3),
R => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[5]_i_1_n_0\,
Q => din(2),
R => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[6]_i_1_n_0\,
Q => din(1),
R => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
\RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => SPIXfer_done_int_pulse_d1,
D => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[7]_i_1_n_0\,
Q => din(0),
R => \RX_DATA_GEN_OTHER_SCK_RATIOS.receive_Data_int[0]_i_1_n_0\
);
SPIXfer_done_int_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
Q => SPIXfer_done_int_d1,
R => Rst_to_spi
);
SPIXfer_done_int_pulse_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
I1 => SPIXfer_done_int_d1,
O => p_19_in
);
SPIXfer_done_int_pulse_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => p_19_in,
Q => SPIXfer_done_int_pulse_d1,
R => Rst_to_spi
);
SPIXfer_done_int_pulse_d2_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => SPIXfer_done_int_pulse_d1,
Q => \^spixfer_done_int\,
R => Rst_to_spi
);
SPI_TRISTATE_CONTROL_II: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => D_0,
Q => sck_t,
R => '0'
);
SPI_TRISTATE_CONTROL_III: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => D_0,
Q => io0_t,
R => '0'
);
SPI_TRISTATE_CONTROL_IV: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => D_0,
Q => ss_t,
R => '0'
);
SPI_TRISTATE_CONTROL_V: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => ext_spi_clk,
CE => '1',
D => '1',
Q => io1_t,
R => '0'
);
SR_5_Tx_Empty_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => empty,
Q => SR_5_Tx_Empty_d1,
R => Rst_to_spi
);
SR_5_Tx_comeplete_Empty_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88C8"
)
port map (
I0 => SR_5_Tx_comeplete_Empty,
I1 => empty,
I2 => \^rx_data_gen_other_sck_ratios.fifo_present_gen.spixfer_done_int_reg_0\,
I3 => SPIXfer_done_int_d1,
O => SR_5_Tx_comeplete_Empty_i_1_n_0
);
SR_5_Tx_comeplete_Empty_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => SR_5_Tx_comeplete_Empty_i_1_n_0,
Q => SR_5_Tx_comeplete_Empty,
R => '0'
);
\SS_O[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF55FF750F00FFFF"
)
port map (
I0 => \SS_O[0]_i_3_n_0\,
I1 => spicr_0_loop_to_spi_clk,
I2 => \SS_O[0]_i_4_n_0\,
I3 => spi_cntrl_ps(0),
I4 => empty,
I5 => spi_cntrl_ps(1),
O => \^logic_generation_fdr.spicr_0_loop_ax2s_2\
);
\SS_O[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFC8"
)
port map (
I0 => \^spixfer_done_int\,
I1 => SR_5_Tx_comeplete_Empty,
I2 => register_Data_slvsel_int,
I3 => stop_clock_reg,
O => \SS_O[0]_i_3_n_0\
);
\SS_O[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^spixfer_done_int\,
I1 => SR_5_Tx_comeplete_Empty,
O => \SS_O[0]_i_4_n_0\
);
\SS_O_reg[0]\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => \SS_O_reg[0]_0\,
Q => ss_o(0),
R => '0'
);
transfer_start_d1_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => transfer_start_reg_n_0,
Q => \^transfer_start_d1\,
R => Rst_to_spi
);
transfer_start_reg: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => transfer_start_reg_0,
Q => transfer_start_reg_n_0,
R => '0'
);
\xpm_fifo_instance.xpm_fifo_async_inst_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^spixfer_done_int\,
I1 => \^transfer_start_d1\,
I2 => transfer_start_reg_n_0,
O => rd_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_status_slave_sel_reg is
port (
SPISSR_frm_axi_clk : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]_0\ : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_status_slave_sel_reg;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_status_slave_sel_reg is
begin
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi4_aclk,
CE => '1',
D => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]_0\,
Q => SPISSR_frm_axi_clk,
S => reset2ip_reset_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_module is
port (
Rst_to_spi : out STD_LOGIC;
reset2ip_reset_int : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_module;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_module is
signal Soft_Reset_frm_axi_d1 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of RESET_SYNC_AX2S_1 : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of RESET_SYNC_AX2S_1 : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of RESET_SYNC_AX2S_1 : label is "VCC:CE";
attribute box_type : string;
attribute box_type of RESET_SYNC_AX2S_1 : label is "PRIMITIVE";
attribute ASYNC_REG of RESET_SYNC_AX2S_2 : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of RESET_SYNC_AX2S_2 : label is "FDR";
attribute XILINX_TRANSFORM_PINMAP of RESET_SYNC_AX2S_2 : label is "VCC:CE";
attribute box_type of RESET_SYNC_AX2S_2 : label is "PRIMITIVE";
begin
RESET_SYNC_AX2S_1: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => reset2ip_reset_int,
Q => Soft_Reset_frm_axi_d1,
R => '0'
);
RESET_SYNC_AX2S_2: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => Soft_Reset_frm_axi_d1,
Q => Rst_to_spi,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_soft_reset is
port (
sw_rst_cond_d1 : out STD_LOGIC;
wrack : out STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS_0\ : out STD_LOGIC;
Bus2IP_Reset_i_reg : out STD_LOGIC;
rst : out STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
sw_rst_cond : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
reset_trig0 : in STD_LOGIC;
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\ : in STD_LOGIC;
TX_one_less_than_full : in STD_LOGIC;
Tx_FIFO_Full_i : in STD_LOGIC;
Tx_FIFO_Full_int : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_soft_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_soft_reset is
signal FF_WRACK_i_1_n_0 : STD_LOGIC;
signal \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \^reset_flops[15].rst_flops_0\ : STD_LOGIC;
signal \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\ : STD_LOGIC;
signal S : STD_LOGIC;
signal flop_q_chain_1 : STD_LOGIC;
signal flop_q_chain_10 : STD_LOGIC;
signal flop_q_chain_11 : STD_LOGIC;
signal flop_q_chain_12 : STD_LOGIC;
signal flop_q_chain_13 : STD_LOGIC;
signal flop_q_chain_14 : STD_LOGIC;
signal flop_q_chain_15 : STD_LOGIC;
signal flop_q_chain_2 : STD_LOGIC;
signal flop_q_chain_3 : STD_LOGIC;
signal flop_q_chain_4 : STD_LOGIC;
signal flop_q_chain_5 : STD_LOGIC;
signal flop_q_chain_6 : STD_LOGIC;
signal flop_q_chain_7 : STD_LOGIC;
signal flop_q_chain_8 : STD_LOGIC;
signal flop_q_chain_9 : STD_LOGIC;
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of FF_WRACK : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of FF_WRACK : label is "1'b0";
attribute box_type : string;
attribute box_type of FF_WRACK : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of FF_WRACK_i_1 : label is "soft_lutpair85";
attribute IS_CE_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[0].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[0].RST_FLOPS\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \RESET_FLOPS[10].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[10].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[10].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[10].RST_FLOPS_i_1\ : label is "soft_lutpair90";
attribute IS_CE_INVERTED of \RESET_FLOPS[11].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[11].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[11].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[11].RST_FLOPS_i_1\ : label is "soft_lutpair91";
attribute IS_CE_INVERTED of \RESET_FLOPS[12].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[12].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[12].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[12].RST_FLOPS_i_1\ : label is "soft_lutpair91";
attribute IS_CE_INVERTED of \RESET_FLOPS[13].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[13].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[13].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[13].RST_FLOPS_i_1\ : label is "soft_lutpair92";
attribute IS_CE_INVERTED of \RESET_FLOPS[14].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[14].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[14].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[14].RST_FLOPS_i_1\ : label is "soft_lutpair92";
attribute IS_CE_INVERTED of \RESET_FLOPS[15].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[15].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[15].RST_FLOPS\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[1].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[1].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[1].RST_FLOPS_i_1\ : label is "soft_lutpair86";
attribute IS_CE_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[2].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[2].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[2].RST_FLOPS_i_1\ : label is "soft_lutpair86";
attribute IS_CE_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[3].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[3].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[3].RST_FLOPS_i_1\ : label is "soft_lutpair87";
attribute IS_CE_INVERTED of \RESET_FLOPS[4].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[4].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[4].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[4].RST_FLOPS_i_1\ : label is "soft_lutpair87";
attribute IS_CE_INVERTED of \RESET_FLOPS[5].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[5].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[5].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[5].RST_FLOPS_i_1\ : label is "soft_lutpair88";
attribute IS_CE_INVERTED of \RESET_FLOPS[6].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[6].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[6].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[6].RST_FLOPS_i_1\ : label is "soft_lutpair88";
attribute IS_CE_INVERTED of \RESET_FLOPS[7].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[7].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[7].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[7].RST_FLOPS_i_1\ : label is "soft_lutpair89";
attribute IS_CE_INVERTED of \RESET_FLOPS[8].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[8].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[8].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[8].RST_FLOPS_i_1\ : label is "soft_lutpair89";
attribute IS_CE_INVERTED of \RESET_FLOPS[9].RST_FLOPS\ : label is "1'b0";
attribute IS_S_INVERTED of \RESET_FLOPS[9].RST_FLOPS\ : label is "1'b0";
attribute box_type of \RESET_FLOPS[9].RST_FLOPS\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \RESET_FLOPS[9].RST_FLOPS_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \xpm_fifo_instance.xpm_fifo_async_inst_i_1\ : label is "soft_lutpair85";
begin
\RESET_FLOPS[15].RST_FLOPS_0\ <= \^reset_flops[15].rst_flops_0\;
FF_WRACK: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => FF_WRACK_i_1_n_0,
Q => wrack,
R => bus2ip_reset_ipif_inverted
);
FF_WRACK_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^reset_flops[15].rst_flops_0\,
I1 => flop_q_chain_1,
O => FF_WRACK_i_1_n_0
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001010100"
)
port map (
I0 => bus2ip_reset_ipif_inverted,
I1 => \^reset_flops[15].rst_flops_0\,
I2 => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\,
I3 => TX_one_less_than_full,
I4 => Tx_FIFO_Full_i,
I5 => Tx_FIFO_Full_int,
O => Bus2IP_Reset_i_reg
);
\RESET_FLOPS[0].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => S,
Q => flop_q_chain_15,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[10].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_5,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[10].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_6,
O => \RESET_FLOPS[10].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[11].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_4,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[11].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_5,
O => \RESET_FLOPS[11].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[12].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_3,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[12].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_4,
O => \RESET_FLOPS[12].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[13].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_2,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[13].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_3,
O => \RESET_FLOPS[13].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[14].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_1,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[14].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_2,
O => \RESET_FLOPS[14].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[15].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\,
Q => \^reset_flops[15].rst_flops_0\,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[15].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_1,
O => \RESET_FLOPS[15].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[1].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_14,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[1].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_15,
O => \RESET_FLOPS[1].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[2].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_13,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[2].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_14,
O => \RESET_FLOPS[2].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[3].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_12,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[3].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_13,
O => \RESET_FLOPS[3].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[4].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_11,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[4].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_12,
O => \RESET_FLOPS[4].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[5].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_10,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[5].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_11,
O => \RESET_FLOPS[5].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[6].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_9,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[6].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_10,
O => \RESET_FLOPS[6].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[7].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_8,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[7].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_9,
O => \RESET_FLOPS[7].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[8].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_7,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[8].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_8,
O => \RESET_FLOPS[8].RST_FLOPS_i_1_n_0\
);
\RESET_FLOPS[9].RST_FLOPS\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\,
Q => flop_q_chain_6,
R => bus2ip_reset_ipif_inverted
);
\RESET_FLOPS[9].RST_FLOPS_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => S,
I1 => flop_q_chain_7,
O => \RESET_FLOPS[9].RST_FLOPS_i_1_n_0\
);
reset_trig_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => reset_trig0,
Q => S,
R => bus2ip_reset_ipif_inverted
);
sw_rst_cond_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => sw_rst_cond,
Q => sw_rst_cond_d1,
R => bus2ip_reset_ipif_inverted
);
\xpm_fifo_instance.xpm_fifo_async_inst_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bus2ip_reset_ipif_inverted,
I1 => \^reset_flops[15].rst_flops_0\,
I2 => \FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\,
O => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray is
port (
src_clk : in STD_LOGIC;
src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 );
dest_clk : in STD_LOGIC;
dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 1;
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 0;
attribute VERSION : integer;
attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is 8;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray : entity is "GRAY";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray is
signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair49";
begin
dest_out_bin(7) <= \dest_graysync_ff[1]\(7);
dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(0),
Q => \dest_graysync_ff[0]\(0),
R => '0'
);
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(1),
Q => \dest_graysync_ff[0]\(1),
R => '0'
);
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(2),
Q => \dest_graysync_ff[0]\(2),
R => '0'
);
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(3),
Q => \dest_graysync_ff[0]\(3),
R => '0'
);
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(4),
Q => \dest_graysync_ff[0]\(4),
R => '0'
);
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(5),
Q => \dest_graysync_ff[0]\(5),
R => '0'
);
\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(6),
Q => \dest_graysync_ff[0]\(6),
R => '0'
);
\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(7),
Q => \dest_graysync_ff[0]\(7),
R => '0'
);
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(0),
Q => \dest_graysync_ff[1]\(0),
R => '0'
);
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(1),
Q => \dest_graysync_ff[1]\(1),
R => '0'
);
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(2),
Q => \dest_graysync_ff[1]\(2),
R => '0'
);
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(3),
Q => \dest_graysync_ff[1]\(3),
R => '0'
);
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(4),
Q => \dest_graysync_ff[1]\(4),
R => '0'
);
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(5),
Q => \dest_graysync_ff[1]\(5),
R => '0'
);
\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(6),
Q => \dest_graysync_ff[1]\(6),
R => '0'
);
\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(7),
Q => \dest_graysync_ff[1]\(7),
R => '0'
);
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(0),
I1 => \^dest_out_bin\(2),
I2 => \dest_graysync_ff[1]\(1),
O => \^dest_out_bin\(0)
);
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(1),
I1 => \^dest_out_bin\(2),
O => \^dest_out_bin\(1)
);
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \dest_graysync_ff[1]\(2),
I1 => \dest_graysync_ff[1]\(4),
I2 => \dest_graysync_ff[1]\(6),
I3 => \dest_graysync_ff[1]\(7),
I4 => \dest_graysync_ff[1]\(5),
I5 => \dest_graysync_ff[1]\(3),
O => \^dest_out_bin\(2)
);
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \dest_graysync_ff[1]\(3),
I1 => \dest_graysync_ff[1]\(5),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(6),
I4 => \dest_graysync_ff[1]\(4),
O => \^dest_out_bin\(3)
);
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[1]\(4),
I1 => \dest_graysync_ff[1]\(6),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(5),
O => \^dest_out_bin\(4)
);
\dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(5),
I1 => \dest_graysync_ff[1]\(7),
I2 => \dest_graysync_ff[1]\(6),
O => \^dest_out_bin\(5)
);
\dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(6),
I1 => \dest_graysync_ff[1]\(7),
O => \^dest_out_bin\(6)
);
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(1),
I1 => src_in_bin(0),
O => gray_enc(0)
);
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(2),
I1 => src_in_bin(1),
O => gray_enc(1)
);
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(3),
I1 => src_in_bin(2),
O => gray_enc(2)
);
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(4),
I1 => src_in_bin(3),
O => gray_enc(3)
);
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(5),
I1 => src_in_bin(4),
O => gray_enc(4)
);
\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(6),
I1 => src_in_bin(5),
O => gray_enc(5)
);
\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(7),
I1 => src_in_bin(6),
O => gray_enc(6)
);
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(0),
Q => async_path(0),
R => '0'
);
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(1),
Q => async_path(1),
R => '0'
);
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(2),
Q => async_path(2),
R => '0'
);
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(3),
Q => async_path(3),
R => '0'
);
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(4),
Q => async_path(4),
R => '0'
);
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(5),
Q => async_path(5),
R => '0'
);
\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(6),
Q => async_path(6),
R => '0'
);
\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_in_bin(7),
Q => async_path(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ is
port (
src_clk : in STD_LOGIC;
src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 );
dest_clk : in STD_LOGIC;
dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is "xpm_cdc_gray";
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is 8;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ : entity is "GRAY";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\ is
signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair2";
begin
dest_out_bin(7) <= \dest_graysync_ff[1]\(7);
dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(0),
Q => \dest_graysync_ff[0]\(0),
R => '0'
);
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(1),
Q => \dest_graysync_ff[0]\(1),
R => '0'
);
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(2),
Q => \dest_graysync_ff[0]\(2),
R => '0'
);
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(3),
Q => \dest_graysync_ff[0]\(3),
R => '0'
);
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(4),
Q => \dest_graysync_ff[0]\(4),
R => '0'
);
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(5),
Q => \dest_graysync_ff[0]\(5),
R => '0'
);
\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(6),
Q => \dest_graysync_ff[0]\(6),
R => '0'
);
\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(7),
Q => \dest_graysync_ff[0]\(7),
R => '0'
);
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(0),
Q => \dest_graysync_ff[1]\(0),
R => '0'
);
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(1),
Q => \dest_graysync_ff[1]\(1),
R => '0'
);
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(2),
Q => \dest_graysync_ff[1]\(2),
R => '0'
);
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(3),
Q => \dest_graysync_ff[1]\(3),
R => '0'
);
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(4),
Q => \dest_graysync_ff[1]\(4),
R => '0'
);
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(5),
Q => \dest_graysync_ff[1]\(5),
R => '0'
);
\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(6),
Q => \dest_graysync_ff[1]\(6),
R => '0'
);
\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(7),
Q => \dest_graysync_ff[1]\(7),
R => '0'
);
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(0),
I1 => \^dest_out_bin\(2),
I2 => \dest_graysync_ff[1]\(1),
O => \^dest_out_bin\(0)
);
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(1),
I1 => \^dest_out_bin\(2),
O => \^dest_out_bin\(1)
);
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \dest_graysync_ff[1]\(2),
I1 => \dest_graysync_ff[1]\(4),
I2 => \dest_graysync_ff[1]\(6),
I3 => \dest_graysync_ff[1]\(7),
I4 => \dest_graysync_ff[1]\(5),
I5 => \dest_graysync_ff[1]\(3),
O => \^dest_out_bin\(2)
);
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \dest_graysync_ff[1]\(3),
I1 => \dest_graysync_ff[1]\(5),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(6),
I4 => \dest_graysync_ff[1]\(4),
O => \^dest_out_bin\(3)
);
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[1]\(4),
I1 => \dest_graysync_ff[1]\(6),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(5),
O => \^dest_out_bin\(4)
);
\dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(5),
I1 => \dest_graysync_ff[1]\(7),
I2 => \dest_graysync_ff[1]\(6),
O => \^dest_out_bin\(5)
);
\dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(6),
I1 => \dest_graysync_ff[1]\(7),
O => \^dest_out_bin\(6)
);
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(1),
I1 => src_in_bin(0),
O => gray_enc(0)
);
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(2),
I1 => src_in_bin(1),
O => gray_enc(1)
);
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(3),
I1 => src_in_bin(2),
O => gray_enc(2)
);
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(4),
I1 => src_in_bin(3),
O => gray_enc(3)
);
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(5),
I1 => src_in_bin(4),
O => gray_enc(4)
);
\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(6),
I1 => src_in_bin(5),
O => gray_enc(5)
);
\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(7),
I1 => src_in_bin(6),
O => gray_enc(6)
);
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(0),
Q => async_path(0),
R => '0'
);
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(1),
Q => async_path(1),
R => '0'
);
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(2),
Q => async_path(2),
R => '0'
);
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(3),
Q => async_path(3),
R => '0'
);
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(4),
Q => async_path(4),
R => '0'
);
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(5),
Q => async_path(5),
R => '0'
);
\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(6),
Q => async_path(6),
R => '0'
);
\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_in_bin(7),
Q => async_path(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ is
port (
src_clk : in STD_LOGIC;
src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 );
dest_clk : in STD_LOGIC;
dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is "xpm_cdc_gray";
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is 8;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ : entity is "GRAY";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\ is
signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair9";
begin
dest_out_bin(7) <= \dest_graysync_ff[1]\(7);
dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(0),
Q => \dest_graysync_ff[0]\(0),
R => '0'
);
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(1),
Q => \dest_graysync_ff[0]\(1),
R => '0'
);
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(2),
Q => \dest_graysync_ff[0]\(2),
R => '0'
);
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(3),
Q => \dest_graysync_ff[0]\(3),
R => '0'
);
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(4),
Q => \dest_graysync_ff[0]\(4),
R => '0'
);
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(5),
Q => \dest_graysync_ff[0]\(5),
R => '0'
);
\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(6),
Q => \dest_graysync_ff[0]\(6),
R => '0'
);
\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(7),
Q => \dest_graysync_ff[0]\(7),
R => '0'
);
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(0),
Q => \dest_graysync_ff[1]\(0),
R => '0'
);
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(1),
Q => \dest_graysync_ff[1]\(1),
R => '0'
);
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(2),
Q => \dest_graysync_ff[1]\(2),
R => '0'
);
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(3),
Q => \dest_graysync_ff[1]\(3),
R => '0'
);
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(4),
Q => \dest_graysync_ff[1]\(4),
R => '0'
);
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(5),
Q => \dest_graysync_ff[1]\(5),
R => '0'
);
\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(6),
Q => \dest_graysync_ff[1]\(6),
R => '0'
);
\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(7),
Q => \dest_graysync_ff[1]\(7),
R => '0'
);
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(0),
I1 => \^dest_out_bin\(2),
I2 => \dest_graysync_ff[1]\(1),
O => \^dest_out_bin\(0)
);
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(1),
I1 => \^dest_out_bin\(2),
O => \^dest_out_bin\(1)
);
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \dest_graysync_ff[1]\(2),
I1 => \dest_graysync_ff[1]\(4),
I2 => \dest_graysync_ff[1]\(6),
I3 => \dest_graysync_ff[1]\(7),
I4 => \dest_graysync_ff[1]\(5),
I5 => \dest_graysync_ff[1]\(3),
O => \^dest_out_bin\(2)
);
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \dest_graysync_ff[1]\(3),
I1 => \dest_graysync_ff[1]\(5),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(6),
I4 => \dest_graysync_ff[1]\(4),
O => \^dest_out_bin\(3)
);
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[1]\(4),
I1 => \dest_graysync_ff[1]\(6),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(5),
O => \^dest_out_bin\(4)
);
\dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(5),
I1 => \dest_graysync_ff[1]\(7),
I2 => \dest_graysync_ff[1]\(6),
O => \^dest_out_bin\(5)
);
\dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(6),
I1 => \dest_graysync_ff[1]\(7),
O => \^dest_out_bin\(6)
);
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(1),
I1 => src_in_bin(0),
O => gray_enc(0)
);
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(2),
I1 => src_in_bin(1),
O => gray_enc(1)
);
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(3),
I1 => src_in_bin(2),
O => gray_enc(2)
);
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(4),
I1 => src_in_bin(3),
O => gray_enc(3)
);
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(5),
I1 => src_in_bin(4),
O => gray_enc(4)
);
\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(6),
I1 => src_in_bin(5),
O => gray_enc(5)
);
\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(7),
I1 => src_in_bin(6),
O => gray_enc(6)
);
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(0),
Q => async_path(0),
R => '0'
);
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(1),
Q => async_path(1),
R => '0'
);
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(2),
Q => async_path(2),
R => '0'
);
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(3),
Q => async_path(3),
R => '0'
);
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(4),
Q => async_path(4),
R => '0'
);
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(5),
Q => async_path(5),
R => '0'
);
\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(6),
Q => async_path(6),
R => '0'
);
\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_in_bin(7),
Q => async_path(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ is
port (
src_clk : in STD_LOGIC;
src_in_bin : in STD_LOGIC_VECTOR ( 7 downto 0 );
dest_clk : in STD_LOGIC;
dest_out_bin : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is "xpm_cdc_gray";
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is 8;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ : entity is "GRAY";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\ is
signal async_path : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal gray_enc : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair42";
begin
dest_out_bin(7) <= \dest_graysync_ff[1]\(7);
dest_out_bin(6 downto 0) <= \^dest_out_bin\(6 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(0),
Q => \dest_graysync_ff[0]\(0),
R => '0'
);
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(1),
Q => \dest_graysync_ff[0]\(1),
R => '0'
);
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(2),
Q => \dest_graysync_ff[0]\(2),
R => '0'
);
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(3),
Q => \dest_graysync_ff[0]\(3),
R => '0'
);
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(4),
Q => \dest_graysync_ff[0]\(4),
R => '0'
);
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(5),
Q => \dest_graysync_ff[0]\(5),
R => '0'
);
\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(6),
Q => \dest_graysync_ff[0]\(6),
R => '0'
);
\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(7),
Q => \dest_graysync_ff[0]\(7),
R => '0'
);
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(0),
Q => \dest_graysync_ff[1]\(0),
R => '0'
);
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(1),
Q => \dest_graysync_ff[1]\(1),
R => '0'
);
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(2),
Q => \dest_graysync_ff[1]\(2),
R => '0'
);
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(3),
Q => \dest_graysync_ff[1]\(3),
R => '0'
);
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(4),
Q => \dest_graysync_ff[1]\(4),
R => '0'
);
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(5),
Q => \dest_graysync_ff[1]\(5),
R => '0'
);
\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(6),
Q => \dest_graysync_ff[1]\(6),
R => '0'
);
\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(7),
Q => \dest_graysync_ff[1]\(7),
R => '0'
);
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(0),
I1 => \^dest_out_bin\(2),
I2 => \dest_graysync_ff[1]\(1),
O => \^dest_out_bin\(0)
);
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(1),
I1 => \^dest_out_bin\(2),
O => \^dest_out_bin\(1)
);
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \dest_graysync_ff[1]\(2),
I1 => \dest_graysync_ff[1]\(4),
I2 => \dest_graysync_ff[1]\(6),
I3 => \dest_graysync_ff[1]\(7),
I4 => \dest_graysync_ff[1]\(5),
I5 => \dest_graysync_ff[1]\(3),
O => \^dest_out_bin\(2)
);
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \dest_graysync_ff[1]\(3),
I1 => \dest_graysync_ff[1]\(5),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(6),
I4 => \dest_graysync_ff[1]\(4),
O => \^dest_out_bin\(3)
);
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[1]\(4),
I1 => \dest_graysync_ff[1]\(6),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(5),
O => \^dest_out_bin\(4)
);
\dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(5),
I1 => \dest_graysync_ff[1]\(7),
I2 => \dest_graysync_ff[1]\(6),
O => \^dest_out_bin\(5)
);
\dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(6),
I1 => \dest_graysync_ff[1]\(7),
O => \^dest_out_bin\(6)
);
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(1),
I1 => src_in_bin(0),
O => gray_enc(0)
);
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(2),
I1 => src_in_bin(1),
O => gray_enc(1)
);
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(3),
I1 => src_in_bin(2),
O => gray_enc(2)
);
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(4),
I1 => src_in_bin(3),
O => gray_enc(3)
);
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(5),
I1 => src_in_bin(4),
O => gray_enc(4)
);
\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(6),
I1 => src_in_bin(5),
O => gray_enc(5)
);
\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(7),
I1 => src_in_bin(6),
O => gray_enc(6)
);
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(0),
Q => async_path(0),
R => '0'
);
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(1),
Q => async_path(1),
R => '0'
);
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(2),
Q => async_path(2),
R => '0'
);
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(3),
Q => async_path(3),
R => '0'
);
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(4),
Q => async_path(4),
R => '0'
);
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(5),
Q => async_path(5),
R => '0'
);
\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(6),
Q => async_path(6),
R => '0'
);
\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_in_bin(7),
Q => async_path(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ is
port (
src_clk : in STD_LOGIC;
src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 );
dest_clk : in STD_LOGIC;
dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 4;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is "xpm_cdc_gray";
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is 9;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ : entity is "GRAY";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\ is
signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[2]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY";
signal \dest_graysync_ff[3]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[3]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[3]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[3]\ : signal is "GRAY";
signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][8]\ : label is "GRAY";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair46";
begin
dest_out_bin(8) <= \dest_graysync_ff[3]\(8);
dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(0),
Q => \dest_graysync_ff[0]\(0),
R => '0'
);
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(1),
Q => \dest_graysync_ff[0]\(1),
R => '0'
);
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(2),
Q => \dest_graysync_ff[0]\(2),
R => '0'
);
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(3),
Q => \dest_graysync_ff[0]\(3),
R => '0'
);
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(4),
Q => \dest_graysync_ff[0]\(4),
R => '0'
);
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(5),
Q => \dest_graysync_ff[0]\(5),
R => '0'
);
\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(6),
Q => \dest_graysync_ff[0]\(6),
R => '0'
);
\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(7),
Q => \dest_graysync_ff[0]\(7),
R => '0'
);
\dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(8),
Q => \dest_graysync_ff[0]\(8),
R => '0'
);
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(0),
Q => \dest_graysync_ff[1]\(0),
R => '0'
);
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(1),
Q => \dest_graysync_ff[1]\(1),
R => '0'
);
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(2),
Q => \dest_graysync_ff[1]\(2),
R => '0'
);
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(3),
Q => \dest_graysync_ff[1]\(3),
R => '0'
);
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(4),
Q => \dest_graysync_ff[1]\(4),
R => '0'
);
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(5),
Q => \dest_graysync_ff[1]\(5),
R => '0'
);
\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(6),
Q => \dest_graysync_ff[1]\(6),
R => '0'
);
\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(7),
Q => \dest_graysync_ff[1]\(7),
R => '0'
);
\dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(8),
Q => \dest_graysync_ff[1]\(8),
R => '0'
);
\dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(0),
Q => \dest_graysync_ff[2]\(0),
R => '0'
);
\dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(1),
Q => \dest_graysync_ff[2]\(1),
R => '0'
);
\dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(2),
Q => \dest_graysync_ff[2]\(2),
R => '0'
);
\dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(3),
Q => \dest_graysync_ff[2]\(3),
R => '0'
);
\dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(4),
Q => \dest_graysync_ff[2]\(4),
R => '0'
);
\dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(5),
Q => \dest_graysync_ff[2]\(5),
R => '0'
);
\dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(6),
Q => \dest_graysync_ff[2]\(6),
R => '0'
);
\dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(7),
Q => \dest_graysync_ff[2]\(7),
R => '0'
);
\dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(8),
Q => \dest_graysync_ff[2]\(8),
R => '0'
);
\dest_graysync_ff_reg[3][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(0),
Q => \dest_graysync_ff[3]\(0),
R => '0'
);
\dest_graysync_ff_reg[3][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(1),
Q => \dest_graysync_ff[3]\(1),
R => '0'
);
\dest_graysync_ff_reg[3][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(2),
Q => \dest_graysync_ff[3]\(2),
R => '0'
);
\dest_graysync_ff_reg[3][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(3),
Q => \dest_graysync_ff[3]\(3),
R => '0'
);
\dest_graysync_ff_reg[3][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(4),
Q => \dest_graysync_ff[3]\(4),
R => '0'
);
\dest_graysync_ff_reg[3][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(5),
Q => \dest_graysync_ff[3]\(5),
R => '0'
);
\dest_graysync_ff_reg[3][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(6),
Q => \dest_graysync_ff[3]\(6),
R => '0'
);
\dest_graysync_ff_reg[3][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(7),
Q => \dest_graysync_ff[3]\(7),
R => '0'
);
\dest_graysync_ff_reg[3][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(8),
Q => \dest_graysync_ff[3]\(8),
R => '0'
);
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[3]\(0),
I1 => \dest_graysync_ff[3]\(2),
I2 => \^dest_out_bin\(3),
I3 => \dest_graysync_ff[3]\(1),
O => \^dest_out_bin\(0)
);
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[3]\(1),
I1 => \^dest_out_bin\(3),
I2 => \dest_graysync_ff[3]\(2),
O => \^dest_out_bin\(1)
);
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[3]\(2),
I1 => \^dest_out_bin\(3),
O => \^dest_out_bin\(2)
);
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \dest_graysync_ff[3]\(3),
I1 => \dest_graysync_ff[3]\(5),
I2 => \dest_graysync_ff[3]\(7),
I3 => \dest_graysync_ff[3]\(8),
I4 => \dest_graysync_ff[3]\(6),
I5 => \dest_graysync_ff[3]\(4),
O => \^dest_out_bin\(3)
);
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \dest_graysync_ff[3]\(4),
I1 => \dest_graysync_ff[3]\(6),
I2 => \dest_graysync_ff[3]\(8),
I3 => \dest_graysync_ff[3]\(7),
I4 => \dest_graysync_ff[3]\(5),
O => \^dest_out_bin\(4)
);
\dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[3]\(5),
I1 => \dest_graysync_ff[3]\(7),
I2 => \dest_graysync_ff[3]\(8),
I3 => \dest_graysync_ff[3]\(6),
O => \^dest_out_bin\(5)
);
\dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[3]\(6),
I1 => \dest_graysync_ff[3]\(8),
I2 => \dest_graysync_ff[3]\(7),
O => \^dest_out_bin\(6)
);
\dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[3]\(7),
I1 => \dest_graysync_ff[3]\(8),
O => \^dest_out_bin\(7)
);
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(1),
I1 => src_in_bin(0),
O => gray_enc(0)
);
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(2),
I1 => src_in_bin(1),
O => gray_enc(1)
);
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(3),
I1 => src_in_bin(2),
O => gray_enc(2)
);
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(4),
I1 => src_in_bin(3),
O => gray_enc(3)
);
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(5),
I1 => src_in_bin(4),
O => gray_enc(4)
);
\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(6),
I1 => src_in_bin(5),
O => gray_enc(5)
);
\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(7),
I1 => src_in_bin(6),
O => gray_enc(6)
);
\src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(8),
I1 => src_in_bin(7),
O => gray_enc(7)
);
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(0),
Q => async_path(0),
R => '0'
);
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(1),
Q => async_path(1),
R => '0'
);
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(2),
Q => async_path(2),
R => '0'
);
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(3),
Q => async_path(3),
R => '0'
);
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(4),
Q => async_path(4),
R => '0'
);
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(5),
Q => async_path(5),
R => '0'
);
\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(6),
Q => async_path(6),
R => '0'
);
\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(7),
Q => async_path(7),
R => '0'
);
\src_gray_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_in_bin(8),
Q => async_path(8),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ is
port (
src_clk : in STD_LOGIC;
src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 );
dest_clk : in STD_LOGIC;
dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is 4;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is "xpm_cdc_gray";
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is 9;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ : entity is "GRAY";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\ is
signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
signal \dest_graysync_ff[2]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[2]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[2]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[2]\ : signal is "GRAY";
signal \dest_graysync_ff[3]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[3]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[3]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[3]\ : signal is "GRAY";
signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[2][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[2][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[2][8]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[3][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[3][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[3][8]\ : label is "GRAY";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \src_gray_ff[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \src_gray_ff[7]_i_1\ : label is "soft_lutpair6";
begin
dest_out_bin(8) <= \dest_graysync_ff[3]\(8);
dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(0),
Q => \dest_graysync_ff[0]\(0),
R => '0'
);
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(1),
Q => \dest_graysync_ff[0]\(1),
R => '0'
);
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(2),
Q => \dest_graysync_ff[0]\(2),
R => '0'
);
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(3),
Q => \dest_graysync_ff[0]\(3),
R => '0'
);
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(4),
Q => \dest_graysync_ff[0]\(4),
R => '0'
);
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(5),
Q => \dest_graysync_ff[0]\(5),
R => '0'
);
\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(6),
Q => \dest_graysync_ff[0]\(6),
R => '0'
);
\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(7),
Q => \dest_graysync_ff[0]\(7),
R => '0'
);
\dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(8),
Q => \dest_graysync_ff[0]\(8),
R => '0'
);
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(0),
Q => \dest_graysync_ff[1]\(0),
R => '0'
);
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(1),
Q => \dest_graysync_ff[1]\(1),
R => '0'
);
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(2),
Q => \dest_graysync_ff[1]\(2),
R => '0'
);
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(3),
Q => \dest_graysync_ff[1]\(3),
R => '0'
);
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(4),
Q => \dest_graysync_ff[1]\(4),
R => '0'
);
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(5),
Q => \dest_graysync_ff[1]\(5),
R => '0'
);
\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(6),
Q => \dest_graysync_ff[1]\(6),
R => '0'
);
\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(7),
Q => \dest_graysync_ff[1]\(7),
R => '0'
);
\dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(8),
Q => \dest_graysync_ff[1]\(8),
R => '0'
);
\dest_graysync_ff_reg[2][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(0),
Q => \dest_graysync_ff[2]\(0),
R => '0'
);
\dest_graysync_ff_reg[2][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(1),
Q => \dest_graysync_ff[2]\(1),
R => '0'
);
\dest_graysync_ff_reg[2][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(2),
Q => \dest_graysync_ff[2]\(2),
R => '0'
);
\dest_graysync_ff_reg[2][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(3),
Q => \dest_graysync_ff[2]\(3),
R => '0'
);
\dest_graysync_ff_reg[2][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(4),
Q => \dest_graysync_ff[2]\(4),
R => '0'
);
\dest_graysync_ff_reg[2][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(5),
Q => \dest_graysync_ff[2]\(5),
R => '0'
);
\dest_graysync_ff_reg[2][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(6),
Q => \dest_graysync_ff[2]\(6),
R => '0'
);
\dest_graysync_ff_reg[2][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(7),
Q => \dest_graysync_ff[2]\(7),
R => '0'
);
\dest_graysync_ff_reg[2][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[1]\(8),
Q => \dest_graysync_ff[2]\(8),
R => '0'
);
\dest_graysync_ff_reg[3][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(0),
Q => \dest_graysync_ff[3]\(0),
R => '0'
);
\dest_graysync_ff_reg[3][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(1),
Q => \dest_graysync_ff[3]\(1),
R => '0'
);
\dest_graysync_ff_reg[3][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(2),
Q => \dest_graysync_ff[3]\(2),
R => '0'
);
\dest_graysync_ff_reg[3][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(3),
Q => \dest_graysync_ff[3]\(3),
R => '0'
);
\dest_graysync_ff_reg[3][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(4),
Q => \dest_graysync_ff[3]\(4),
R => '0'
);
\dest_graysync_ff_reg[3][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(5),
Q => \dest_graysync_ff[3]\(5),
R => '0'
);
\dest_graysync_ff_reg[3][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(6),
Q => \dest_graysync_ff[3]\(6),
R => '0'
);
\dest_graysync_ff_reg[3][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(7),
Q => \dest_graysync_ff[3]\(7),
R => '0'
);
\dest_graysync_ff_reg[3][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[2]\(8),
Q => \dest_graysync_ff[3]\(8),
R => '0'
);
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[3]\(0),
I1 => \dest_graysync_ff[3]\(2),
I2 => \^dest_out_bin\(3),
I3 => \dest_graysync_ff[3]\(1),
O => \^dest_out_bin\(0)
);
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[3]\(1),
I1 => \^dest_out_bin\(3),
I2 => \dest_graysync_ff[3]\(2),
O => \^dest_out_bin\(1)
);
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[3]\(2),
I1 => \^dest_out_bin\(3),
O => \^dest_out_bin\(2)
);
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \dest_graysync_ff[3]\(3),
I1 => \dest_graysync_ff[3]\(5),
I2 => \dest_graysync_ff[3]\(7),
I3 => \dest_graysync_ff[3]\(8),
I4 => \dest_graysync_ff[3]\(6),
I5 => \dest_graysync_ff[3]\(4),
O => \^dest_out_bin\(3)
);
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \dest_graysync_ff[3]\(4),
I1 => \dest_graysync_ff[3]\(6),
I2 => \dest_graysync_ff[3]\(8),
I3 => \dest_graysync_ff[3]\(7),
I4 => \dest_graysync_ff[3]\(5),
O => \^dest_out_bin\(4)
);
\dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[3]\(5),
I1 => \dest_graysync_ff[3]\(7),
I2 => \dest_graysync_ff[3]\(8),
I3 => \dest_graysync_ff[3]\(6),
O => \^dest_out_bin\(5)
);
\dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[3]\(6),
I1 => \dest_graysync_ff[3]\(8),
I2 => \dest_graysync_ff[3]\(7),
O => \^dest_out_bin\(6)
);
\dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[3]\(7),
I1 => \dest_graysync_ff[3]\(8),
O => \^dest_out_bin\(7)
);
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(1),
I1 => src_in_bin(0),
O => gray_enc(0)
);
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(2),
I1 => src_in_bin(1),
O => gray_enc(1)
);
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(3),
I1 => src_in_bin(2),
O => gray_enc(2)
);
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(4),
I1 => src_in_bin(3),
O => gray_enc(3)
);
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(5),
I1 => src_in_bin(4),
O => gray_enc(4)
);
\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(6),
I1 => src_in_bin(5),
O => gray_enc(5)
);
\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(7),
I1 => src_in_bin(6),
O => gray_enc(6)
);
\src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(8),
I1 => src_in_bin(7),
O => gray_enc(7)
);
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(0),
Q => async_path(0),
R => '0'
);
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(1),
Q => async_path(1),
R => '0'
);
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(2),
Q => async_path(2),
R => '0'
);
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(3),
Q => async_path(3),
R => '0'
);
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(4),
Q => async_path(4),
R => '0'
);
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(5),
Q => async_path(5),
R => '0'
);
\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(6),
Q => async_path(6),
R => '0'
);
\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(7),
Q => async_path(7),
R => '0'
);
\src_gray_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_in_bin(8),
Q => async_path(8),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ is
port (
src_clk : in STD_LOGIC;
src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 );
dest_clk : in STD_LOGIC;
dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is "xpm_cdc_gray";
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is 9;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ : entity is "GRAY";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\ is
signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair51";
begin
dest_out_bin(8) <= \dest_graysync_ff[1]\(8);
dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(0),
Q => \dest_graysync_ff[0]\(0),
R => '0'
);
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(1),
Q => \dest_graysync_ff[0]\(1),
R => '0'
);
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(2),
Q => \dest_graysync_ff[0]\(2),
R => '0'
);
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(3),
Q => \dest_graysync_ff[0]\(3),
R => '0'
);
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(4),
Q => \dest_graysync_ff[0]\(4),
R => '0'
);
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(5),
Q => \dest_graysync_ff[0]\(5),
R => '0'
);
\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(6),
Q => \dest_graysync_ff[0]\(6),
R => '0'
);
\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(7),
Q => \dest_graysync_ff[0]\(7),
R => '0'
);
\dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(8),
Q => \dest_graysync_ff[0]\(8),
R => '0'
);
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(0),
Q => \dest_graysync_ff[1]\(0),
R => '0'
);
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(1),
Q => \dest_graysync_ff[1]\(1),
R => '0'
);
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(2),
Q => \dest_graysync_ff[1]\(2),
R => '0'
);
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(3),
Q => \dest_graysync_ff[1]\(3),
R => '0'
);
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(4),
Q => \dest_graysync_ff[1]\(4),
R => '0'
);
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(5),
Q => \dest_graysync_ff[1]\(5),
R => '0'
);
\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(6),
Q => \dest_graysync_ff[1]\(6),
R => '0'
);
\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(7),
Q => \dest_graysync_ff[1]\(7),
R => '0'
);
\dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(8),
Q => \dest_graysync_ff[1]\(8),
R => '0'
);
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[1]\(0),
I1 => \dest_graysync_ff[1]\(2),
I2 => \^dest_out_bin\(3),
I3 => \dest_graysync_ff[1]\(1),
O => \^dest_out_bin\(0)
);
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(1),
I1 => \^dest_out_bin\(3),
I2 => \dest_graysync_ff[1]\(2),
O => \^dest_out_bin\(1)
);
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(2),
I1 => \^dest_out_bin\(3),
O => \^dest_out_bin\(2)
);
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \dest_graysync_ff[1]\(3),
I1 => \dest_graysync_ff[1]\(5),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(8),
I4 => \dest_graysync_ff[1]\(6),
I5 => \dest_graysync_ff[1]\(4),
O => \^dest_out_bin\(3)
);
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \dest_graysync_ff[1]\(4),
I1 => \dest_graysync_ff[1]\(6),
I2 => \dest_graysync_ff[1]\(8),
I3 => \dest_graysync_ff[1]\(7),
I4 => \dest_graysync_ff[1]\(5),
O => \^dest_out_bin\(4)
);
\dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[1]\(5),
I1 => \dest_graysync_ff[1]\(7),
I2 => \dest_graysync_ff[1]\(8),
I3 => \dest_graysync_ff[1]\(6),
O => \^dest_out_bin\(5)
);
\dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(6),
I1 => \dest_graysync_ff[1]\(8),
I2 => \dest_graysync_ff[1]\(7),
O => \^dest_out_bin\(6)
);
\dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(7),
I1 => \dest_graysync_ff[1]\(8),
O => \^dest_out_bin\(7)
);
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(1),
I1 => src_in_bin(0),
O => gray_enc(0)
);
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(2),
I1 => src_in_bin(1),
O => gray_enc(1)
);
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(3),
I1 => src_in_bin(2),
O => gray_enc(2)
);
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(4),
I1 => src_in_bin(3),
O => gray_enc(3)
);
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(5),
I1 => src_in_bin(4),
O => gray_enc(4)
);
\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(6),
I1 => src_in_bin(5),
O => gray_enc(5)
);
\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(7),
I1 => src_in_bin(6),
O => gray_enc(6)
);
\src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(8),
I1 => src_in_bin(7),
O => gray_enc(7)
);
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(0),
Q => async_path(0),
R => '0'
);
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(1),
Q => async_path(1),
R => '0'
);
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(2),
Q => async_path(2),
R => '0'
);
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(3),
Q => async_path(3),
R => '0'
);
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(4),
Q => async_path(4),
R => '0'
);
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(5),
Q => async_path(5),
R => '0'
);
\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(6),
Q => async_path(6),
R => '0'
);
\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(7),
Q => async_path(7),
R => '0'
);
\src_gray_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_in_bin(8),
Q => async_path(8),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ is
port (
src_clk : in STD_LOGIC;
src_in_bin : in STD_LOGIC_VECTOR ( 8 downto 0 );
dest_clk : in STD_LOGIC;
dest_out_bin : out STD_LOGIC_VECTOR ( 8 downto 0 )
);
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is "xpm_cdc_gray";
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is 0;
attribute WIDTH : integer;
attribute WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is 9;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ : entity is "GRAY";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\ is
signal async_path : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \dest_graysync_ff[0]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \dest_graysync_ff[0]\ : signal is "true";
attribute async_reg : string;
attribute async_reg of \dest_graysync_ff[0]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[0]\ : signal is "GRAY";
signal \dest_graysync_ff[1]\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute RTL_KEEP of \dest_graysync_ff[1]\ : signal is "true";
attribute async_reg of \dest_graysync_ff[1]\ : signal is "true";
attribute xpm_cdc of \dest_graysync_ff[1]\ : signal is "GRAY";
signal \^dest_out_bin\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal gray_enc : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \dest_graysync_ff_reg[0][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[0][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[0][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[0][8]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][0]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][0]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][0]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][1]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][1]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][1]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][2]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][2]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][2]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][3]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][3]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][3]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][4]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][4]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][4]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][5]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][5]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][5]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][6]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][6]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][6]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][7]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][7]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][7]\ : label is "GRAY";
attribute ASYNC_REG_boolean of \dest_graysync_ff_reg[1][8]\ : label is std.standard.true;
attribute KEEP of \dest_graysync_ff_reg[1][8]\ : label is "true";
attribute XPM_CDC of \dest_graysync_ff_reg[1][8]\ : label is "GRAY";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \src_gray_ff[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \src_gray_ff[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \src_gray_ff[3]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \src_gray_ff[4]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \src_gray_ff[5]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \src_gray_ff[6]_i_1\ : label is "soft_lutpair11";
begin
dest_out_bin(8) <= \dest_graysync_ff[1]\(8);
dest_out_bin(7 downto 0) <= \^dest_out_bin\(7 downto 0);
\dest_graysync_ff_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(0),
Q => \dest_graysync_ff[0]\(0),
R => '0'
);
\dest_graysync_ff_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(1),
Q => \dest_graysync_ff[0]\(1),
R => '0'
);
\dest_graysync_ff_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(2),
Q => \dest_graysync_ff[0]\(2),
R => '0'
);
\dest_graysync_ff_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(3),
Q => \dest_graysync_ff[0]\(3),
R => '0'
);
\dest_graysync_ff_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(4),
Q => \dest_graysync_ff[0]\(4),
R => '0'
);
\dest_graysync_ff_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(5),
Q => \dest_graysync_ff[0]\(5),
R => '0'
);
\dest_graysync_ff_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(6),
Q => \dest_graysync_ff[0]\(6),
R => '0'
);
\dest_graysync_ff_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(7),
Q => \dest_graysync_ff[0]\(7),
R => '0'
);
\dest_graysync_ff_reg[0][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => async_path(8),
Q => \dest_graysync_ff[0]\(8),
R => '0'
);
\dest_graysync_ff_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(0),
Q => \dest_graysync_ff[1]\(0),
R => '0'
);
\dest_graysync_ff_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(1),
Q => \dest_graysync_ff[1]\(1),
R => '0'
);
\dest_graysync_ff_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(2),
Q => \dest_graysync_ff[1]\(2),
R => '0'
);
\dest_graysync_ff_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(3),
Q => \dest_graysync_ff[1]\(3),
R => '0'
);
\dest_graysync_ff_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(4),
Q => \dest_graysync_ff[1]\(4),
R => '0'
);
\dest_graysync_ff_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(5),
Q => \dest_graysync_ff[1]\(5),
R => '0'
);
\dest_graysync_ff_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(6),
Q => \dest_graysync_ff[1]\(6),
R => '0'
);
\dest_graysync_ff_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(7),
Q => \dest_graysync_ff[1]\(7),
R => '0'
);
\dest_graysync_ff_reg[1][8]\: unisim.vcomponents.FDRE
port map (
C => dest_clk,
CE => '1',
D => \dest_graysync_ff[0]\(8),
Q => \dest_graysync_ff[1]\(8),
R => '0'
);
\dest_out_bin[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[1]\(0),
I1 => \dest_graysync_ff[1]\(2),
I2 => \^dest_out_bin\(3),
I3 => \dest_graysync_ff[1]\(1),
O => \^dest_out_bin\(0)
);
\dest_out_bin[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(1),
I1 => \^dest_out_bin\(3),
I2 => \dest_graysync_ff[1]\(2),
O => \^dest_out_bin\(1)
);
\dest_out_bin[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(2),
I1 => \^dest_out_bin\(3),
O => \^dest_out_bin\(2)
);
\dest_out_bin[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \dest_graysync_ff[1]\(3),
I1 => \dest_graysync_ff[1]\(5),
I2 => \dest_graysync_ff[1]\(7),
I3 => \dest_graysync_ff[1]\(8),
I4 => \dest_graysync_ff[1]\(6),
I5 => \dest_graysync_ff[1]\(4),
O => \^dest_out_bin\(3)
);
\dest_out_bin[4]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \dest_graysync_ff[1]\(4),
I1 => \dest_graysync_ff[1]\(6),
I2 => \dest_graysync_ff[1]\(8),
I3 => \dest_graysync_ff[1]\(7),
I4 => \dest_graysync_ff[1]\(5),
O => \^dest_out_bin\(4)
);
\dest_out_bin[5]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \dest_graysync_ff[1]\(5),
I1 => \dest_graysync_ff[1]\(7),
I2 => \dest_graysync_ff[1]\(8),
I3 => \dest_graysync_ff[1]\(6),
O => \^dest_out_bin\(5)
);
\dest_out_bin[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \dest_graysync_ff[1]\(6),
I1 => \dest_graysync_ff[1]\(8),
I2 => \dest_graysync_ff[1]\(7),
O => \^dest_out_bin\(6)
);
\dest_out_bin[7]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \dest_graysync_ff[1]\(7),
I1 => \dest_graysync_ff[1]\(8),
O => \^dest_out_bin\(7)
);
\src_gray_ff[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(1),
I1 => src_in_bin(0),
O => gray_enc(0)
);
\src_gray_ff[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(2),
I1 => src_in_bin(1),
O => gray_enc(1)
);
\src_gray_ff[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(3),
I1 => src_in_bin(2),
O => gray_enc(2)
);
\src_gray_ff[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(4),
I1 => src_in_bin(3),
O => gray_enc(3)
);
\src_gray_ff[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(5),
I1 => src_in_bin(4),
O => gray_enc(4)
);
\src_gray_ff[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(6),
I1 => src_in_bin(5),
O => gray_enc(5)
);
\src_gray_ff[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(7),
I1 => src_in_bin(6),
O => gray_enc(6)
);
\src_gray_ff[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => src_in_bin(8),
I1 => src_in_bin(7),
O => gray_enc(7)
);
\src_gray_ff_reg[0]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(0),
Q => async_path(0),
R => '0'
);
\src_gray_ff_reg[1]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(1),
Q => async_path(1),
R => '0'
);
\src_gray_ff_reg[2]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(2),
Q => async_path(2),
R => '0'
);
\src_gray_ff_reg[3]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(3),
Q => async_path(3),
R => '0'
);
\src_gray_ff_reg[4]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(4),
Q => async_path(4),
R => '0'
);
\src_gray_ff_reg[5]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(5),
Q => async_path(5),
R => '0'
);
\src_gray_ff_reg[6]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(6),
Q => async_path(6),
R => '0'
);
\src_gray_ff_reg[7]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => gray_enc(7),
Q => async_path(7),
R => '0'
);
\src_gray_ff_reg[8]\: unisim.vcomponents.FDRE
port map (
C => src_clk,
CE => '1',
D => src_in_bin(8),
Q => async_path(8),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst is
port (
src_rst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_rst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 2;
attribute INIT : string;
attribute INIT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "0";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 1;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 0;
attribute VERSION : integer;
attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst : entity is "SYNC_RST";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
begin
dest_rst <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => src_rst,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ is
port (
src_rst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_rst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is 2;
attribute INIT : string;
attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is "0";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is "xpm_cdc_sync_rst";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ : entity is "SYNC_RST";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
begin
dest_rst <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => src_rst,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ is
port (
src_rst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_rst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is 2;
attribute INIT : string;
attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is "0";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is "xpm_cdc_sync_rst";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ : entity is "SYNC_RST";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
begin
dest_rst <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => src_rst,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ is
port (
src_rst : in STD_LOGIC;
dest_clk : in STD_LOGIC;
dest_rst : out STD_LOGIC
);
attribute DEF_VAL : string;
attribute DEF_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is 2;
attribute INIT : string;
attribute INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is "0";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is "xpm_cdc_sync_rst";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is 0;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is "true";
attribute xpm_cdc : string;
attribute xpm_cdc of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ : entity is "SYNC_RST";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\ is
signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of syncstages_ff : signal is "true";
attribute async_reg : string;
attribute async_reg of syncstages_ff : signal is "true";
attribute xpm_cdc of syncstages_ff : signal is "SYNC_RST";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SYNC_RST";
attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SYNC_RST";
begin
dest_rst <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => src_rst,
Q => syncstages_ff(0),
R => '0'
);
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => dest_clk,
CE => '1',
D => syncstages_ff(0),
Q => syncstages_ff(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_pntr_plus1_pf_carry : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[6]_0\ : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
wr_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__2_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_2__1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[0]_i_1__2\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__2\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair53";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1__2_n_0\
);
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1__2_n_0\
);
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__2_n_0\
);
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__2_n_0\
);
\count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__2_n_0\
);
\count_value_i[5]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2__2_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1__2_n_0\
);
\count_value_i[6]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2__2_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1__2_n_0\
);
\count_value_i[6]_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \count_value_i_reg[6]_0\,
I3 => wrst_busy,
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[6]_i_2__2_n_0\
);
\count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[7]_i_2__1_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1__2_n_0\
);
\count_value_i[7]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => wr_pntr_plus1_pf_carry,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[7]_i_2__1_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[0]_i_1__2_n_0\,
Q => \^q\(0),
S => wrst_busy
);
\count_value_i_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[1]_i_1__2_n_0\,
Q => \^q\(1),
S => wrst_busy
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[2]_i_1__2_n_0\,
Q => \^q\(2),
R => wrst_busy
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[3]_i_1__2_n_0\,
Q => \^q\(3),
R => wrst_busy
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[4]_i_1__2_n_0\,
Q => \^q\(4),
R => wrst_busy
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[5]_i_1__2_n_0\,
Q => \^q\(5),
R => wrst_busy
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[6]_i_1__2_n_0\,
Q => \^q\(6),
R => wrst_busy
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[7]_i_1__2_n_0\,
Q => \^q\(7),
R => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_5 is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_pntr_plus1_pf_carry : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[6]_0\ : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_5 : entity is "xpm_counter_updn";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_5 is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__2_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_2__1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[0]_i_1__2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__2\ : label is "soft_lutpair13";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\count_value_i[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1__2_n_0\
);
\count_value_i[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1__2_n_0\
);
\count_value_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__2_n_0\
);
\count_value_i[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__2_n_0\
);
\count_value_i[4]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__2_n_0\
);
\count_value_i[5]_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2__2_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1__2_n_0\
);
\count_value_i[6]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2__2_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1__2_n_0\
);
\count_value_i[6]_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \count_value_i_reg[6]_0\,
I3 => wrst_busy,
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[6]_i_2__2_n_0\
);
\count_value_i[7]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[7]_i_2__1_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1__2_n_0\
);
\count_value_i[7]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => wr_pntr_plus1_pf_carry,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[7]_i_2__1_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[0]_i_1__2_n_0\,
Q => \^q\(0),
S => wrst_busy
);
\count_value_i_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[1]_i_1__2_n_0\,
Q => \^q\(1),
S => wrst_busy
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[2]_i_1__2_n_0\,
Q => \^q\(2),
R => wrst_busy
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[3]_i_1__2_n_0\,
Q => \^q\(3),
R => wrst_busy
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[4]_i_1__2_n_0\,
Q => \^q\(4),
R => wrst_busy
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[5]_i_1__2_n_0\,
Q => \^q\(5),
R => wrst_busy
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[6]_i_1__2_n_0\,
Q => \^q\(6),
R => wrst_busy
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[7]_i_1__2_n_0\,
Q => \^q\(7),
R => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_pntr_plus1_pf_carry : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[6]_0\ : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair67";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1_n_0\
);
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1_n_0\
);
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1_n_0\
);
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1_n_0\
);
\count_value_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1_n_0\
);
\count_value_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1_n_0\
);
\count_value_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1_n_0\
);
\count_value_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \count_value_i_reg[6]_0\,
I3 => wrst_busy,
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[6]_i_2_n_0\
);
\count_value_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[7]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1_n_0\
);
\count_value_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => wr_pntr_plus1_pf_carry,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[7]_i_2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[0]_i_1_n_0\,
Q => \^q\(0),
R => wrst_busy
);
\count_value_i_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[1]_i_1_n_0\,
Q => \^q\(1),
S => wrst_busy
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[2]_i_1_n_0\,
Q => \^q\(2),
R => wrst_busy
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[3]_i_1_n_0\,
Q => \^q\(3),
R => wrst_busy
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[4]_i_1_n_0\,
Q => \^q\(4),
R => wrst_busy
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[5]_i_1_n_0\,
Q => \^q\(5),
R => wrst_busy
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[6]_i_1_n_0\,
Q => \^q\(6),
R => wrst_busy
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[7]_i_1_n_0\,
Q => \^q\(7),
R => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_16\ is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_pntr_plus1_pf_carry : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[6]_0\ : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_16\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_16\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_16\ is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[0]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1\ : label is "soft_lutpair29";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\count_value_i[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1_n_0\
);
\count_value_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1_n_0\
);
\count_value_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1_n_0\
);
\count_value_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1_n_0\
);
\count_value_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1_n_0\
);
\count_value_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1_n_0\
);
\count_value_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1_n_0\
);
\count_value_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \count_value_i_reg[6]_0\,
I3 => wrst_busy,
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[6]_i_2_n_0\
);
\count_value_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[7]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1_n_0\
);
\count_value_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => wr_pntr_plus1_pf_carry,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[7]_i_2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[0]_i_1_n_0\,
Q => \^q\(0),
R => wrst_busy
);
\count_value_i_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[1]_i_1_n_0\,
Q => \^q\(1),
S => wrst_busy
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[2]_i_1_n_0\,
Q => \^q\(2),
R => wrst_busy
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[3]_i_1_n_0\,
Q => \^q\(3),
R => wrst_busy
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[4]_i_1_n_0\,
Q => \^q\(4),
R => wrst_busy
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[5]_i_1_n_0\,
Q => \^q\(5),
R => wrst_busy
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[6]_i_1_n_0\,
Q => \^q\(6),
R => wrst_busy
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[7]_i_1_n_0\,
Q => \^q\(7),
R => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ is
port (
src_in_bin : out STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[0]_0\ : out STD_LOGIC;
\count_value_i_reg[1]_0\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 1 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\count_value_i_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_i : in STD_LOGIC;
\count_value_i_reg[1]_2\ : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\ is
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_2_n_0\ : STD_LOGIC;
signal \^count_value_i_reg[0]_0\ : STD_LOGIC;
signal \^count_value_i_reg[1]_0\ : STD_LOGIC;
attribute HLUTNM : string;
attribute HLUTNM of \grdc.rd_data_count_i[3]_i_4\ : label is "lutpair1";
attribute HLUTNM of \grdc.rd_data_count_i[3]_i_8\ : label is "lutpair1";
begin
DI(0) <= \^di\(0);
\count_value_i_reg[0]_0\ <= \^count_value_i_reg[0]_0\;
\count_value_i_reg[1]_0\ <= \^count_value_i_reg[1]_0\;
\count_value_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000005A88A655"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => \count_value_i_reg[1]_1\(0),
I2 => rd_en,
I3 => \count_value_i_reg[1]_1\(1),
I4 => ram_empty_i,
I5 => \count_value_i_reg[1]_2\,
O => \count_value_i[0]_i_1_n_0\
);
\count_value_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AA88AAAA"
)
port map (
I0 => \count_value_i[1]_i_2_n_0\,
I1 => \count_value_i_reg[1]_1\(0),
I2 => rd_en,
I3 => \count_value_i_reg[1]_1\(1),
I4 => ram_empty_i,
I5 => \count_value_i_reg[1]_2\,
O => \count_value_i[1]_i_1_n_0\
);
\count_value_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFFF755500008AA"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => \count_value_i_reg[1]_1\(0),
I2 => rd_en,
I3 => \count_value_i_reg[1]_1\(1),
I4 => ram_empty_i,
I5 => \^count_value_i_reg[1]_0\,
O => \count_value_i[1]_i_2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \count_value_i[0]_i_1_n_0\,
Q => \^count_value_i_reg[0]_0\,
R => '0'
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \count_value_i[1]_i_1_n_0\,
Q => \^count_value_i_reg[1]_0\,
R => '0'
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"2DD2"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => Q(0),
I2 => \^count_value_i_reg[1]_0\,
I3 => Q(1),
O => src_in_bin(0)
);
\grdc.rd_data_count_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => Q(0),
O => \^di\(0)
);
\grdc.rd_data_count_i[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \^di\(0),
I1 => \^count_value_i_reg[1]_0\,
I2 => Q(1),
I3 => \grdc.rd_data_count_i_reg[3]\(1),
O => S(1)
);
\grdc.rd_data_count_i[3]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => Q(0),
I2 => \grdc.rd_data_count_i_reg[3]\(0),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_10\ is
port (
S : out STD_LOGIC_VECTOR ( 1 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[1]_0\ : out STD_LOGIC;
\count_value_i_reg[0]_0\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
ram_empty_i : in STD_LOGIC;
\count_value_i_reg[1]_1\ : in STD_LOGIC;
\count_value_i_reg[1]_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_10\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_10\ is
signal \^di\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \count_value_i[0]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_2_n_0\ : STD_LOGIC;
signal \^count_value_i_reg[0]_0\ : STD_LOGIC;
signal \^count_value_i_reg[1]_0\ : STD_LOGIC;
attribute HLUTNM : string;
attribute HLUTNM of \grdc.rd_data_count_i[3]_i_4\ : label is "lutpair0";
attribute HLUTNM of \grdc.rd_data_count_i[3]_i_8\ : label is "lutpair0";
begin
DI(0) <= \^di\(0);
\count_value_i_reg[0]_0\ <= \^count_value_i_reg[0]_0\;
\count_value_i_reg[1]_0\ <= \^count_value_i_reg[1]_0\;
\count_value_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"006900A5006A0005"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => rd_en,
I2 => ram_empty_i,
I3 => \count_value_i_reg[1]_1\,
I4 => \count_value_i_reg[1]_2\(1),
I5 => \count_value_i_reg[1]_2\(0),
O => \count_value_i[0]_i_1_n_0\
);
\count_value_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0A0A0A02"
)
port map (
I0 => \count_value_i[1]_i_2_n_0\,
I1 => ram_empty_i,
I2 => \count_value_i_reg[1]_1\,
I3 => \count_value_i_reg[1]_2\(1),
I4 => \count_value_i_reg[1]_2\(0),
O => \count_value_i[1]_i_1_n_0\
);
\count_value_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBDFDDDD44202222"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => ram_empty_i,
I2 => \count_value_i_reg[1]_2\(0),
I3 => rd_en,
I4 => \count_value_i_reg[1]_2\(1),
I5 => \^count_value_i_reg[1]_0\,
O => \count_value_i[1]_i_2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \count_value_i[0]_i_1_n_0\,
Q => \^count_value_i_reg[0]_0\,
R => '0'
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \count_value_i[1]_i_1_n_0\,
Q => \^count_value_i_reg[1]_0\,
R => '0'
);
\grdc.rd_data_count_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => Q(0),
O => \^di\(0)
);
\grdc.rd_data_count_i[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"9669"
)
port map (
I0 => \^di\(0),
I1 => Q(1),
I2 => \^count_value_i_reg[1]_0\,
I3 => \grdc.rd_data_count_i_reg[3]\(1),
O => S(1)
);
\grdc.rd_data_count_i[3]_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^count_value_i_reg[0]_0\,
I1 => Q(0),
I2 => \grdc.rd_data_count_i_reg[3]\(0),
O => S(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\ is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
enb : out STD_LOGIC;
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[6]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
src_in_bin : out STD_LOGIC_VECTOR ( 7 downto 0 );
\count_value_i_reg[0]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_i : in STD_LOGIC;
\grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC;
\grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\src_gray_ff_reg[2]\ : in STD_LOGIC;
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\count_value_i_reg[8]_0\ : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\ is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__3_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[8]_i_2__0_n_0\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC;
signal \^enb\ : STD_LOGIC;
signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\ : STD_LOGIC;
signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[2]_i_1__4\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__4\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__4\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \count_value_i[7]_i_1__3\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\ : label is "soft_lutpair59";
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1\ : label is 35;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is 35;
attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
enb <= \^enb\;
\count_value_i[0]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAA5455"
)
port map (
I0 => ram_empty_i,
I1 => rd_en,
I2 => \count_value_i_reg[0]_0\(0),
I3 => \count_value_i_reg[0]_0\(1),
I4 => \^q\(0),
O => \count_value_i[0]_i_1__4_n_0\
);
\count_value_i[1]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02FFFD00"
)
port map (
I0 => \count_value_i_reg[0]_0\(1),
I1 => \count_value_i_reg[0]_0\(0),
I2 => rd_en,
I3 => \^q\(0),
I4 => \^q\(1),
O => \count_value_i[1]_i_1__4_n_0\
);
\count_value_i[2]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__4_n_0\
);
\count_value_i[3]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__4_n_0\
);
\count_value_i[4]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__4_n_0\
);
\count_value_i[5]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2__3_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1__3_n_0\
);
\count_value_i[6]_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2__3_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1__3_n_0\
);
\count_value_i[6]_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAA200000000"
)
port map (
I0 => \^q\(1),
I1 => \count_value_i_reg[0]_0\(1),
I2 => \count_value_i_reg[0]_0\(0),
I3 => rd_en,
I4 => ram_empty_i,
I5 => \^q\(0),
O => \count_value_i[6]_i_2__3_n_0\
);
\count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[8]_i_2__0_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1__3_n_0\
);
\count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(6),
I1 => \count_value_i[8]_i_2__0_n_0\,
I2 => \^q\(5),
I3 => \^q\(7),
I4 => \count_value_i_reg_n_0_[8]\,
O => \count_value_i[8]_i_1__0_n_0\
);
\count_value_i[8]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^enb\,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[8]_i_2__0_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[0]_i_1__4_n_0\,
Q => \^q\(0),
R => \count_value_i_reg[8]_0\
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[1]_i_1__4_n_0\,
Q => \^q\(1),
R => \count_value_i_reg[8]_0\
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[2]_i_1__4_n_0\,
Q => \^q\(2),
R => \count_value_i_reg[8]_0\
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[3]_i_1__4_n_0\,
Q => \^q\(3),
R => \count_value_i_reg[8]_0\
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[4]_i_1__4_n_0\,
Q => \^q\(4),
R => \count_value_i_reg[8]_0\
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[5]_i_1__3_n_0\,
Q => \^q\(5),
R => \count_value_i_reg[8]_0\
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[6]_i_1__3_n_0\,
Q => \^q\(6),
R => \count_value_i_reg[8]_0\
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[7]_i_1__3_n_0\,
Q => \^q\(7),
R => \count_value_i_reg[8]_0\
);
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^enb\,
D => \count_value_i[8]_i_1__0_n_0\,
Q => \count_value_i_reg_n_0_[8]\,
R => \count_value_i_reg[8]_0\
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
I3 => \^q\(4),
I4 => \^q\(6),
I5 => \count_value_i_reg_n_0_[8]\,
O => src_in_bin(7)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFBFBBAFB"
)
port map (
I0 => \^q\(2),
I1 => \grdc.rd_data_count_i_reg[3]\,
I2 => \^q\(1),
I3 => \src_gray_ff_reg[2]\,
I4 => \^q\(0),
I5 => \^q\(3),
O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^q\(0),
I1 => \src_gray_ff_reg[2]\,
O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
I3 => \^q\(5),
I4 => \^q\(7),
O => src_in_bin(6)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => \^q\(5),
I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
I2 => \^q\(4),
I3 => \^q\(6),
O => src_in_bin(5)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \^q\(4),
I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
I2 => \^q\(5),
O => src_in_bin(4)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEAFE00001501"
)
port map (
I0 => \^q\(3),
I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0\,
I2 => \^q\(1),
I3 => \grdc.rd_data_count_i_reg[3]\,
I4 => \^q\(2),
I5 => \^q\(4),
O => src_in_bin(3)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBBAFB04044504"
)
port map (
I0 => \^q\(2),
I1 => \grdc.rd_data_count_i_reg[3]\,
I2 => \^q\(1),
I3 => \src_gray_ff_reg[2]\,
I4 => \^q\(0),
I5 => \^q\(3),
O => src_in_bin(2)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0FB4F04"
)
port map (
I0 => \^q\(0),
I1 => \src_gray_ff_reg[2]\,
I2 => \^q\(1),
I3 => \grdc.rd_data_count_i_reg[3]\,
I4 => \^q\(2),
O => src_in_bin(1)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \src_gray_ff_reg[2]\,
O => src_in_bin(0)
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(3),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(2),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(1),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAA5455"
)
port map (
I0 => ram_empty_i,
I1 => rd_en,
I2 => \count_value_i_reg[0]_0\(0),
I3 => \count_value_i_reg[0]_0\(1),
I4 => \^q\(0),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(6),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(5),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(4),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(7),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(6),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(5),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(4),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0\,
CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_1\,
CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_2\,
CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_3\,
CYINIT => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0),
DI(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0\,
DI(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0\,
DI(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0\,
DI(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0\,
O(3 downto 0) => D(3 downto 0),
S(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6_n_0\,
S(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7_n_0\,
S(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8_n_0\,
S(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0\,
CO(3) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\,
CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\,
CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\,
DI(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\,
DI(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\,
O(3 downto 0) => D(7 downto 4),
S(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0\,
S(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0\,
S(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0\,
S(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0\
);
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FD"
)
port map (
I0 => \count_value_i_reg[0]_0\(1),
I1 => \count_value_i_reg[0]_0\(0),
I2 => rd_en,
I3 => ram_empty_i,
O => \^enb\
);
\grdc.rd_data_count_i[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"D4"
)
port map (
I0 => \^q\(1),
I1 => \grdc.rd_data_count_i_reg[3]\,
I2 => \grdc.rd_data_count_i_reg[8]\(0),
O => DI(0)
);
\grdc.rd_data_count_i[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(2),
I1 => \grdc.rd_data_count_i_reg[8]\(1),
I2 => \^q\(3),
I3 => \grdc.rd_data_count_i_reg[8]\(2),
O => S(0)
);
\grdc.rd_data_count_i[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(6),
I1 => \grdc.rd_data_count_i_reg[8]\(5),
I2 => \^q\(7),
I3 => \grdc.rd_data_count_i_reg[8]\(6),
O => \count_value_i_reg[6]_0\(3)
);
\grdc.rd_data_count_i[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(5),
I1 => \grdc.rd_data_count_i_reg[8]\(4),
I2 => \^q\(6),
I3 => \grdc.rd_data_count_i_reg[8]\(5),
O => \count_value_i_reg[6]_0\(2)
);
\grdc.rd_data_count_i[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(4),
I1 => \grdc.rd_data_count_i_reg[8]\(3),
I2 => \^q\(5),
I3 => \grdc.rd_data_count_i_reg[8]\(4),
O => \count_value_i_reg[6]_0\(1)
);
\grdc.rd_data_count_i[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(3),
I1 => \grdc.rd_data_count_i_reg[8]\(2),
I2 => \^q\(4),
I3 => \grdc.rd_data_count_i_reg[8]\(3),
O => \count_value_i_reg[6]_0\(0)
);
\grdc.rd_data_count_i[8]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(7),
I1 => \grdc.rd_data_count_i_reg[8]\(6),
I2 => \count_value_i_reg_n_0_[8]\,
I3 => \grdc.rd_data_count_i_reg[8]\(7),
O => \count_value_i_reg[7]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_11\ is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
src_in_bin : out STD_LOGIC_VECTOR ( 8 downto 0 );
\count_value_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\count_value_i_reg[2]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\count_value_i_reg[6]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
rd_en : in STD_LOGIC;
\count_value_i_reg[8]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
ram_empty_i : in STD_LOGIC;
\src_gray_ff_reg[0]\ : in STD_LOGIC;
\grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC;
\grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\count_value_i_reg[4]_0\ : in STD_LOGIC;
\count_value_i_reg[8]_1\ : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_11\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_11\ is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__4_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[8]_i_2__0_n_0\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[8]\ : STD_LOGIC;
signal \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[0]_i_1__4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1__4\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__4\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \count_value_i[7]_i_1__3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \count_value_i[8]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\ : label is "soft_lutpair19";
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1\ : label is 35;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is 35;
attribute METHODOLOGY_DRC_VIOS of \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
E(0) <= \^e\(0);
Q(7 downto 0) <= \^q\(7 downto 0);
\count_value_i[0]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"5565"
)
port map (
I0 => \^q\(0),
I1 => rd_en,
I2 => \count_value_i_reg[8]_0\(1),
I3 => \count_value_i_reg[8]_0\(0),
O => \count_value_i[0]_i_1__4_n_0\
);
\count_value_i[1]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"66666A66"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_value_i_reg[8]_0\(0),
I3 => \count_value_i_reg[8]_0\(1),
I4 => rd_en,
O => \count_value_i[1]_i_1__4_n_0\
);
\count_value_i[2]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \count_value_i_reg[4]_0\,
I3 => \^q\(0),
O => \count_value_i[2]_i_1__4_n_0\
);
\count_value_i[3]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AAAAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \count_value_i_reg[4]_0\,
I4 => \^q\(1),
O => \count_value_i[3]_i_1__4_n_0\
);
\count_value_i[4]_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \^q\(4),
I1 => \^q\(3),
I2 => \^q\(1),
I3 => \count_value_i_reg[4]_0\,
I4 => \^q\(0),
I5 => \^q\(2),
O => \count_value_i[4]_i_1__4_n_0\
);
\count_value_i[5]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AAAAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(4),
I2 => \^q\(2),
I3 => \count_value_i[6]_i_2__4_n_0\,
I4 => \^q\(3),
O => \count_value_i[5]_i_1__4_n_0\
);
\count_value_i[6]_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(5),
I2 => \^q\(3),
I3 => \count_value_i[6]_i_2__4_n_0\,
I4 => \^q\(2),
I5 => \^q\(4),
O => \count_value_i[6]_i_1__4_n_0\
);
\count_value_i[6]_i_2__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDFDDFFFFFFFF"
)
port map (
I0 => \^q\(0),
I1 => ram_empty_i,
I2 => \count_value_i_reg[8]_0\(0),
I3 => \count_value_i_reg[8]_0\(1),
I4 => rd_en,
I5 => \^q\(1),
O => \count_value_i[6]_i_2__4_n_0\
);
\count_value_i[7]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AAA"
)
port map (
I0 => \^q\(7),
I1 => \count_value_i[8]_i_2__0_n_0\,
I2 => \^q\(5),
I3 => \^q\(6),
O => \count_value_i[7]_i_1__3_n_0\
);
\count_value_i[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA6AAA"
)
port map (
I0 => \count_value_i_reg_n_0_[8]\,
I1 => \^q\(7),
I2 => \^q\(6),
I3 => \^q\(5),
I4 => \count_value_i[8]_i_2__0_n_0\,
O => \count_value_i[8]_i_1__0_n_0\
);
\count_value_i[8]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \count_value_i_reg[4]_0\,
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(4),
O => \count_value_i[8]_i_2__0_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[0]_i_1__4_n_0\,
Q => \^q\(0),
R => \count_value_i_reg[8]_1\
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[1]_i_1__4_n_0\,
Q => \^q\(1),
R => \count_value_i_reg[8]_1\
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[2]_i_1__4_n_0\,
Q => \^q\(2),
R => \count_value_i_reg[8]_1\
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[3]_i_1__4_n_0\,
Q => \^q\(3),
R => \count_value_i_reg[8]_1\
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[4]_i_1__4_n_0\,
Q => \^q\(4),
R => \count_value_i_reg[8]_1\
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[5]_i_1__4_n_0\,
Q => \^q\(5),
R => \count_value_i_reg[8]_1\
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[6]_i_1__4_n_0\,
Q => \^q\(6),
R => \count_value_i_reg[8]_1\
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[7]_i_1__3_n_0\,
Q => \^q\(7),
R => \count_value_i_reg[8]_1\
);
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => \^e\(0),
D => \count_value_i[8]_i_1__0_n_0\,
Q => \count_value_i_reg_n_0_[8]\,
R => \count_value_i_reg[8]_1\
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA9"
)
port map (
I0 => \count_value_i_reg_n_0_[8]\,
I1 => \^q\(7),
I2 => \^q\(6),
I3 => \^q\(4),
I4 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
I5 => \^q\(5),
O => src_in_bin(8)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEFEFAEEF"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \grdc.rd_data_count_i_reg[3]\,
I3 => \src_gray_ff_reg[0]\,
I4 => \^q\(0),
I5 => \^q\(2),
O => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \^q\(7),
I1 => \^q\(5),
I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
I3 => \^q\(4),
I4 => \^q\(6),
O => src_in_bin(7)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
I3 => \^q\(5),
O => src_in_bin(6)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \^q\(5),
I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
I2 => \^q\(4),
O => src_in_bin(5)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0\,
O => src_in_bin(4)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA9A9A599A"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \grdc.rd_data_count_i_reg[3]\,
I3 => \src_gray_ff_reg[0]\,
I4 => \^q\(0),
I5 => \^q\(2),
O => src_in_bin(3)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AAA559A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \src_gray_ff_reg[0]\,
I3 => \grdc.rd_data_count_i_reg[3]\,
I4 => \^q\(1),
O => src_in_bin(2)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"4BB4"
)
port map (
I0 => \^q\(0),
I1 => \src_gray_ff_reg[0]\,
I2 => \grdc.rd_data_count_i_reg[3]\,
I3 => \^q\(1),
O => src_in_bin(1)
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \src_gray_ff_reg[0]\,
O => src_in_bin(0)
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(3),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(2),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(1),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF0400FB"
)
port map (
I0 => rd_en,
I1 => \count_value_i_reg[8]_0\(1),
I2 => \count_value_i_reg[8]_0\(0),
I3 => ram_empty_i,
I4 => \^q\(0),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(6),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(5),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(4),
O => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0\,
CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_1\,
CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_2\,
CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_3\,
CYINIT => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\(0),
DI(3) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_2_n_0\,
DI(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_3_n_0\,
DI(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_4_n_0\,
DI(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_5_n_0\,
O(3 downto 0) => D(3 downto 0),
S(3 downto 1) => S(2 downto 0),
S(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_9_n_0\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]_i_1_n_0\,
CO(3) => \NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1\,
CO(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2\,
CO(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0\,
DI(1) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0\,
DI(0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0\,
O(3 downto 0) => D(7 downto 4),
S(3 downto 0) => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3 downto 0)
);
\gen_sdpram.xpm_memory_base_inst_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => rd_en,
I1 => \count_value_i_reg[8]_0\(1),
I2 => \count_value_i_reg[8]_0\(0),
I3 => ram_empty_i,
O => \^e\(0)
);
\grdc.rd_data_count_i[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(2),
I1 => \grdc.rd_data_count_i_reg[8]\(1),
I2 => \grdc.rd_data_count_i_reg[8]\(2),
I3 => \^q\(3),
O => \count_value_i_reg[2]_0\(1)
);
\grdc.rd_data_count_i[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"2BD4D42B"
)
port map (
I0 => \^q\(1),
I1 => \grdc.rd_data_count_i_reg[3]\,
I2 => \grdc.rd_data_count_i_reg[8]\(0),
I3 => \grdc.rd_data_count_i_reg[8]\(1),
I4 => \^q\(2),
O => \count_value_i_reg[2]_0\(0)
);
\grdc.rd_data_count_i[7]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(6),
I1 => \grdc.rd_data_count_i_reg[8]\(5),
I2 => \grdc.rd_data_count_i_reg[8]\(6),
I3 => \^q\(7),
O => \count_value_i_reg[6]_0\(3)
);
\grdc.rd_data_count_i[7]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(5),
I1 => \grdc.rd_data_count_i_reg[8]\(4),
I2 => \grdc.rd_data_count_i_reg[8]\(5),
I3 => \^q\(6),
O => \count_value_i_reg[6]_0\(2)
);
\grdc.rd_data_count_i[7]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(4),
I1 => \grdc.rd_data_count_i_reg[8]\(3),
I2 => \grdc.rd_data_count_i_reg[8]\(4),
I3 => \^q\(5),
O => \count_value_i_reg[6]_0\(1)
);
\grdc.rd_data_count_i[7]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(3),
I1 => \grdc.rd_data_count_i_reg[8]\(2),
I2 => \grdc.rd_data_count_i_reg[8]\(3),
I3 => \^q\(4),
O => \count_value_i_reg[6]_0\(0)
);
\grdc.rd_data_count_i[8]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B44B"
)
port map (
I0 => \^q\(7),
I1 => \grdc.rd_data_count_i_reg[8]\(6),
I2 => \grdc.rd_data_count_i_reg[8]\(7),
I3 => \count_value_i_reg_n_0_[8]\,
O => \count_value_i_reg[7]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_14\ is
port (
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_pntr_plus1_pf_carry : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[6]_0\ : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
\gwdc.wr_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_14\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_14\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_14\ is
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__1_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[8]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_4_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_5_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[7]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[7]_i_3_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[7]_i_4_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[7]_i_5_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[8]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair24";
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[3]_i_1\ : label is 35;
attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[7]_i_1\ : label is 35;
attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[8]_i_1\ : label is 35;
begin
Q(8 downto 0) <= \^q\(8 downto 0);
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1__1_n_0\
);
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1__1_n_0\
);
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__1_n_0\
);
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__1_n_0\
);
\count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__1_n_0\
);
\count_value_i[5]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2__1_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1__1_n_0\
);
\count_value_i[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2__1_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1__1_n_0\
);
\count_value_i[6]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \count_value_i_reg[6]_0\,
I3 => wrst_busy,
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[6]_i_2__1_n_0\
);
\count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[8]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1__1_n_0\
);
\count_value_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(6),
I1 => \count_value_i[8]_i_2_n_0\,
I2 => \^q\(5),
I3 => \^q\(7),
I4 => \^q\(8),
O => \count_value_i[8]_i_1_n_0\
);
\count_value_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => wr_pntr_plus1_pf_carry,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[8]_i_2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[0]_i_1__1_n_0\,
Q => \^q\(0),
R => wrst_busy
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[1]_i_1__1_n_0\,
Q => \^q\(1),
R => wrst_busy
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[2]_i_1__1_n_0\,
Q => \^q\(2),
R => wrst_busy
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[3]_i_1__1_n_0\,
Q => \^q\(3),
R => wrst_busy
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[4]_i_1__1_n_0\,
Q => \^q\(4),
R => wrst_busy
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[5]_i_1__1_n_0\,
Q => \^q\(5),
R => wrst_busy
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[6]_i_1__1_n_0\,
Q => \^q\(6),
R => wrst_busy
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[7]_i_1__1_n_0\,
Q => \^q\(7),
R => wrst_busy
);
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[8]_i_1_n_0\,
Q => \^q\(8),
R => wrst_busy
);
\gwdc.wr_data_count_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \gwdc.wr_data_count_i_reg[8]\(3),
O => \gwdc.wr_data_count_i[3]_i_2_n_0\
);
\gwdc.wr_data_count_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \gwdc.wr_data_count_i_reg[8]\(2),
O => \gwdc.wr_data_count_i[3]_i_3_n_0\
);
\gwdc.wr_data_count_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \gwdc.wr_data_count_i_reg[8]\(1),
O => \gwdc.wr_data_count_i[3]_i_4_n_0\
);
\gwdc.wr_data_count_i[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => \gwdc.wr_data_count_i_reg[8]\(0),
O => \gwdc.wr_data_count_i[3]_i_5_n_0\
);
\gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \gwdc.wr_data_count_i_reg[8]\(7),
O => \gwdc.wr_data_count_i[7]_i_2_n_0\
);
\gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \gwdc.wr_data_count_i_reg[8]\(6),
O => \gwdc.wr_data_count_i[7]_i_3_n_0\
);
\gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \gwdc.wr_data_count_i_reg[8]\(5),
O => \gwdc.wr_data_count_i[7]_i_4_n_0\
);
\gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \gwdc.wr_data_count_i_reg[8]\(4),
O => \gwdc.wr_data_count_i[7]_i_5_n_0\
);
\gwdc.wr_data_count_i[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \gwdc.wr_data_count_i_reg[8]\(8),
O => \gwdc.wr_data_count_i[8]_i_2_n_0\
);
\gwdc.wr_data_count_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gwdc.wr_data_count_i_reg[3]_i_1_n_0\,
CO(2) => \gwdc.wr_data_count_i_reg[3]_i_1_n_1\,
CO(1) => \gwdc.wr_data_count_i_reg[3]_i_1_n_2\,
CO(0) => \gwdc.wr_data_count_i_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => \^q\(3 downto 0),
O(3 downto 0) => D(3 downto 0),
S(3) => \gwdc.wr_data_count_i[3]_i_2_n_0\,
S(2) => \gwdc.wr_data_count_i[3]_i_3_n_0\,
S(1) => \gwdc.wr_data_count_i[3]_i_4_n_0\,
S(0) => \gwdc.wr_data_count_i[3]_i_5_n_0\
);
\gwdc.wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gwdc.wr_data_count_i_reg[3]_i_1_n_0\,
CO(3) => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\,
CO(2) => \gwdc.wr_data_count_i_reg[7]_i_1_n_1\,
CO(1) => \gwdc.wr_data_count_i_reg[7]_i_1_n_2\,
CO(0) => \gwdc.wr_data_count_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(7 downto 4),
O(3 downto 0) => D(7 downto 4),
S(3) => \gwdc.wr_data_count_i[7]_i_2_n_0\,
S(2) => \gwdc.wr_data_count_i[7]_i_3_n_0\,
S(1) => \gwdc.wr_data_count_i[7]_i_4_n_0\,
S(0) => \gwdc.wr_data_count_i[7]_i_5_n_0\
);
\gwdc.wr_data_count_i_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\,
CO(3 downto 0) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => D(8),
S(3 downto 1) => B"000",
S(0) => \gwdc.wr_data_count_i[8]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_3\ is
port (
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
wr_pntr_plus1_pf_carry : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[6]_0\ : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
\gwdc.wr_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_3\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_3\ is
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \count_value_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__1_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \count_value_i[8]_i_1_n_0\ : STD_LOGIC;
signal \count_value_i[8]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_4_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[3]_i_5_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[7]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[7]_i_3_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[7]_i_4_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[7]_i_5_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i[8]_i_2_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \gwdc.wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1__1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \count_value_i[7]_i_1__1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \count_value_i[8]_i_1\ : label is "soft_lutpair62";
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[3]_i_1\ : label is 35;
attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[7]_i_1\ : label is 35;
attribute ADDER_THRESHOLD of \gwdc.wr_data_count_i_reg[8]_i_1\ : label is 35;
begin
Q(8 downto 0) <= \^q\(8 downto 0);
\count_value_i[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1__1_n_0\
);
\count_value_i[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1__1_n_0\
);
\count_value_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__1_n_0\
);
\count_value_i[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__1_n_0\
);
\count_value_i[4]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__1_n_0\
);
\count_value_i[5]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2__1_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1__1_n_0\
);
\count_value_i[6]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2__1_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1__1_n_0\
);
\count_value_i[6]_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \count_value_i_reg[6]_0\,
I3 => wrst_busy,
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[6]_i_2__1_n_0\
);
\count_value_i[7]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[8]_i_2_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1__1_n_0\
);
\count_value_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(6),
I1 => \count_value_i[8]_i_2_n_0\,
I2 => \^q\(5),
I3 => \^q\(7),
I4 => \^q\(8),
O => \count_value_i[8]_i_1_n_0\
);
\count_value_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => wr_pntr_plus1_pf_carry,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[8]_i_2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[0]_i_1__1_n_0\,
Q => \^q\(0),
R => wrst_busy
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[1]_i_1__1_n_0\,
Q => \^q\(1),
R => wrst_busy
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[2]_i_1__1_n_0\,
Q => \^q\(2),
R => wrst_busy
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[3]_i_1__1_n_0\,
Q => \^q\(3),
R => wrst_busy
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[4]_i_1__1_n_0\,
Q => \^q\(4),
R => wrst_busy
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[5]_i_1__1_n_0\,
Q => \^q\(5),
R => wrst_busy
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[6]_i_1__1_n_0\,
Q => \^q\(6),
R => wrst_busy
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[7]_i_1__1_n_0\,
Q => \^q\(7),
R => wrst_busy
);
\count_value_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[8]_i_1_n_0\,
Q => \^q\(8),
R => wrst_busy
);
\gwdc.wr_data_count_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \gwdc.wr_data_count_i_reg[8]\(3),
O => \gwdc.wr_data_count_i[3]_i_2_n_0\
);
\gwdc.wr_data_count_i[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \gwdc.wr_data_count_i_reg[8]\(2),
O => \gwdc.wr_data_count_i[3]_i_3_n_0\
);
\gwdc.wr_data_count_i[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \gwdc.wr_data_count_i_reg[8]\(1),
O => \gwdc.wr_data_count_i[3]_i_4_n_0\
);
\gwdc.wr_data_count_i[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => \gwdc.wr_data_count_i_reg[8]\(0),
O => \gwdc.wr_data_count_i[3]_i_5_n_0\
);
\gwdc.wr_data_count_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \gwdc.wr_data_count_i_reg[8]\(7),
O => \gwdc.wr_data_count_i[7]_i_2_n_0\
);
\gwdc.wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \gwdc.wr_data_count_i_reg[8]\(6),
O => \gwdc.wr_data_count_i[7]_i_3_n_0\
);
\gwdc.wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \gwdc.wr_data_count_i_reg[8]\(5),
O => \gwdc.wr_data_count_i[7]_i_4_n_0\
);
\gwdc.wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \gwdc.wr_data_count_i_reg[8]\(4),
O => \gwdc.wr_data_count_i[7]_i_5_n_0\
);
\gwdc.wr_data_count_i[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \gwdc.wr_data_count_i_reg[8]\(8),
O => \gwdc.wr_data_count_i[8]_i_2_n_0\
);
\gwdc.wr_data_count_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gwdc.wr_data_count_i_reg[3]_i_1_n_0\,
CO(2) => \gwdc.wr_data_count_i_reg[3]_i_1_n_1\,
CO(1) => \gwdc.wr_data_count_i_reg[3]_i_1_n_2\,
CO(0) => \gwdc.wr_data_count_i_reg[3]_i_1_n_3\,
CYINIT => '1',
DI(3 downto 0) => \^q\(3 downto 0),
O(3 downto 0) => D(3 downto 0),
S(3) => \gwdc.wr_data_count_i[3]_i_2_n_0\,
S(2) => \gwdc.wr_data_count_i[3]_i_3_n_0\,
S(1) => \gwdc.wr_data_count_i[3]_i_4_n_0\,
S(0) => \gwdc.wr_data_count_i[3]_i_5_n_0\
);
\gwdc.wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gwdc.wr_data_count_i_reg[3]_i_1_n_0\,
CO(3) => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\,
CO(2) => \gwdc.wr_data_count_i_reg[7]_i_1_n_1\,
CO(1) => \gwdc.wr_data_count_i_reg[7]_i_1_n_2\,
CO(0) => \gwdc.wr_data_count_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(7 downto 4),
O(3 downto 0) => D(7 downto 4),
S(3) => \gwdc.wr_data_count_i[7]_i_2_n_0\,
S(2) => \gwdc.wr_data_count_i[7]_i_3_n_0\,
S(1) => \gwdc.wr_data_count_i[7]_i_4_n_0\,
S(0) => \gwdc.wr_data_count_i[7]_i_5_n_0\
);
\gwdc.wr_data_count_i_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gwdc.wr_data_count_i_reg[7]_i_1_n_0\,
CO(3 downto 0) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED\(3 downto 1),
O(0) => D(8),
S(3 downto 1) => B"000",
S(0) => \gwdc.wr_data_count_i[8]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\ is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\count_value_i_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_i : in STD_LOGIC;
\count_value_i_reg[0]_0\ : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\ is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__4_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_2__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__3\ : label is "soft_lutpair60";
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\count_value_i[0]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"10EF"
)
port map (
I0 => rd_en,
I1 => \count_value_i_reg[1]_0\(0),
I2 => \count_value_i_reg[1]_0\(1),
I3 => \^q\(0),
O => \count_value_i[0]_i_1__3_n_0\
);
\count_value_i[1]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"02FFFD00"
)
port map (
I0 => \count_value_i_reg[1]_0\(1),
I1 => \count_value_i_reg[1]_0\(0),
I2 => rd_en,
I3 => \^q\(0),
I4 => \^q\(1),
O => \count_value_i[1]_i_1__3_n_0\
);
\count_value_i[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__3_n_0\
);
\count_value_i[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__3_n_0\
);
\count_value_i[4]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__3_n_0\
);
\count_value_i[5]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2__4_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1__4_n_0\
);
\count_value_i[6]_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2__4_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1__4_n_0\
);
\count_value_i[6]_i_2__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAA200000000"
)
port map (
I0 => \^q\(1),
I1 => \count_value_i_reg[1]_0\(1),
I2 => \count_value_i_reg[1]_0\(0),
I3 => rd_en,
I4 => ram_empty_i,
I5 => \^q\(0),
O => \count_value_i[6]_i_2__4_n_0\
);
\count_value_i[7]_i_1__4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[7]_i_2__2_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1__4_n_0\
);
\count_value_i[7]_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => E(0),
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[7]_i_2__2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[0]_i_1__3_n_0\,
Q => \^q\(0),
S => \count_value_i_reg[0]_0\
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[1]_i_1__3_n_0\,
Q => \^q\(1),
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[2]_i_1__3_n_0\,
Q => \^q\(2),
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[3]_i_1__3_n_0\,
Q => \^q\(3),
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[4]_i_1__3_n_0\,
Q => \^q\(4),
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[5]_i_1__4_n_0\,
Q => \^q\(5),
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[6]_i_1__4_n_0\,
Q => \^q\(6),
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[7]_i_1__4_n_0\,
Q => \^q\(7),
R => \count_value_i_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\ is
port (
ram_empty_i0 : out STD_LOGIC;
\gen_pf_ic_rc.ram_empty_i_reg\ : out STD_LOGIC;
ram_empty_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
\gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC;
\gen_pf_ic_rc.ram_empty_i_reg_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\count_value_i_reg[0]_0\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\ is
signal \count_value_i[0]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__3_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__3_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__4_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_2__2_n_0\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[0]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[1]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[2]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[3]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[4]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[5]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[6]\ : STD_LOGIC;
signal \count_value_i_reg_n_0_[7]\ : STD_LOGIC;
signal \gen_pf_ic_rc.ram_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ : STD_LOGIC;
signal \^gen_pf_ic_rc.ram_empty_i_reg\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[0]_i_1__3\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \count_value_i[4]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \count_value_i[7]_i_2__2\ : label is "soft_lutpair21";
begin
\gen_pf_ic_rc.ram_empty_i_reg\ <= \^gen_pf_ic_rc.ram_empty_i_reg\;
\count_value_i[0]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5565"
)
port map (
I0 => \count_value_i_reg_n_0_[0]\,
I1 => rd_en,
I2 => Q(1),
I3 => Q(0),
O => \count_value_i[0]_i_1__3_n_0\
);
\count_value_i[1]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"5565AAAA"
)
port map (
I0 => \count_value_i_reg_n_0_[1]\,
I1 => rd_en,
I2 => Q(1),
I3 => Q(0),
I4 => \count_value_i_reg_n_0_[0]\,
O => \count_value_i[1]_i_1__3_n_0\
);
\count_value_i[2]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \count_value_i_reg_n_0_[2]\,
I1 => \count_value_i_reg_n_0_[0]\,
I2 => \^gen_pf_ic_rc.ram_empty_i_reg\,
I3 => \count_value_i_reg_n_0_[1]\,
O => \count_value_i[2]_i_1__3_n_0\
);
\count_value_i[3]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFFF2000"
)
port map (
I0 => \count_value_i_reg_n_0_[1]\,
I1 => \^gen_pf_ic_rc.ram_empty_i_reg\,
I2 => \count_value_i_reg_n_0_[0]\,
I3 => \count_value_i_reg_n_0_[2]\,
I4 => \count_value_i_reg_n_0_[3]\,
O => \count_value_i[3]_i_1__3_n_0\
);
\count_value_i[4]_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAAAAAAAAAAAAA"
)
port map (
I0 => \count_value_i_reg_n_0_[4]\,
I1 => \count_value_i_reg_n_0_[1]\,
I2 => \^gen_pf_ic_rc.ram_empty_i_reg\,
I3 => \count_value_i_reg_n_0_[0]\,
I4 => \count_value_i_reg_n_0_[2]\,
I5 => \count_value_i_reg_n_0_[3]\,
O => \count_value_i[4]_i_1__3_n_0\
);
\count_value_i[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AABA"
)
port map (
I0 => ram_empty_i,
I1 => Q(0),
I2 => Q(1),
I3 => rd_en,
O => \^gen_pf_ic_rc.ram_empty_i_reg\
);
\count_value_i[5]_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AAAAA"
)
port map (
I0 => \count_value_i_reg_n_0_[5]\,
I1 => \count_value_i_reg_n_0_[3]\,
I2 => \count_value_i_reg_n_0_[2]\,
I3 => \count_value_i[6]_i_2__3_n_0\,
I4 => \count_value_i_reg_n_0_[4]\,
O => \count_value_i[5]_i_1__3_n_0\
);
\count_value_i[6]_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAAAAAAAAAAAAA"
)
port map (
I0 => \count_value_i_reg_n_0_[6]\,
I1 => \count_value_i_reg_n_0_[4]\,
I2 => \count_value_i[6]_i_2__3_n_0\,
I3 => \count_value_i_reg_n_0_[2]\,
I4 => \count_value_i_reg_n_0_[3]\,
I5 => \count_value_i_reg_n_0_[5]\,
O => \count_value_i[6]_i_1__3_n_0\
);
\count_value_i[6]_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDFDDFFFFFFFF"
)
port map (
I0 => \count_value_i_reg_n_0_[0]\,
I1 => ram_empty_i,
I2 => Q(0),
I3 => Q(1),
I4 => rd_en,
I5 => \count_value_i_reg_n_0_[1]\,
O => \count_value_i[6]_i_2__3_n_0\
);
\count_value_i[7]_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \count_value_i_reg_n_0_[7]\,
I1 => \count_value_i_reg_n_0_[5]\,
I2 => \count_value_i[7]_i_2__2_n_0\,
I3 => \count_value_i_reg_n_0_[4]\,
I4 => \count_value_i_reg_n_0_[6]\,
O => \count_value_i[7]_i_1__4_n_0\
);
\count_value_i[7]_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \count_value_i_reg_n_0_[3]\,
I1 => \count_value_i_reg_n_0_[2]\,
I2 => \count_value_i_reg_n_0_[0]\,
I3 => \^gen_pf_ic_rc.ram_empty_i_reg\,
I4 => \count_value_i_reg_n_0_[1]\,
O => \count_value_i[7]_i_2__2_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[0]_i_1__3_n_0\,
Q => \count_value_i_reg_n_0_[0]\,
S => \count_value_i_reg[0]_0\
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[1]_i_1__3_n_0\,
Q => \count_value_i_reg_n_0_[1]\,
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[2]_i_1__3_n_0\,
Q => \count_value_i_reg_n_0_[2]\,
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[3]_i_1__3_n_0\,
Q => \count_value_i_reg_n_0_[3]\,
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[4]_i_1__3_n_0\,
Q => \count_value_i_reg_n_0_[4]\,
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[5]_i_1__3_n_0\,
Q => \count_value_i_reg_n_0_[5]\,
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[6]_i_1__3_n_0\,
Q => \count_value_i_reg_n_0_[6]\,
R => \count_value_i_reg[0]_0\
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
D => \count_value_i[7]_i_1__4_n_0\,
Q => \count_value_i_reg_n_0_[7]\,
R => \count_value_i_reg[0]_0\
);
\gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF11111011"
)
port map (
I0 => \gen_pf_ic_rc.ram_empty_i_i_2_n_0\,
I1 => ram_empty_i,
I2 => Q(0),
I3 => Q(1),
I4 => rd_en,
I5 => \gen_pf_ic_rc.ram_empty_i_reg_0\,
O => ram_empty_i0
);
\gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF6FF6"
)
port map (
I0 => \gen_pf_ic_rc.ram_empty_i_reg_1\(6),
I1 => \count_value_i_reg_n_0_[6]\,
I2 => \gen_pf_ic_rc.ram_empty_i_reg_1\(7),
I3 => \count_value_i_reg_n_0_[7]\,
I4 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\,
I5 => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\,
O => \gen_pf_ic_rc.ram_empty_i_i_2_n_0\
);
\gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \count_value_i_reg_n_0_[0]\,
I1 => \gen_pf_ic_rc.ram_empty_i_reg_1\(0),
I2 => \gen_pf_ic_rc.ram_empty_i_reg_1\(2),
I3 => \count_value_i_reg_n_0_[2]\,
I4 => \gen_pf_ic_rc.ram_empty_i_reg_1\(1),
I5 => \count_value_i_reg_n_0_[1]\,
O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\
);
\gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \count_value_i_reg_n_0_[3]\,
I1 => \gen_pf_ic_rc.ram_empty_i_reg_1\(3),
I2 => \gen_pf_ic_rc.ram_empty_i_reg_1\(5),
I3 => \count_value_i_reg_n_0_[5]\,
I4 => \gen_pf_ic_rc.ram_empty_i_reg_1\(4),
I5 => \count_value_i_reg_n_0_[4]\,
O => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_15\ is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_pntr_plus1_pf_carry : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[6]_0\ : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_15\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_15\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_15\ is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__0_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair27";
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1\ : label is 35;
attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\ : label is 35;
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1__0_n_0\
);
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1__0_n_0\
);
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__0_n_0\
);
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__0_n_0\
);
\count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__0_n_0\
);
\count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2__0_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1__0_n_0\
);
\count_value_i[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2__0_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1__0_n_0\
);
\count_value_i[6]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \count_value_i_reg[6]_0\,
I3 => wrst_busy,
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[6]_i_2__0_n_0\
);
\count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[7]_i_2__0_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1__0_n_0\
);
\count_value_i[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => wr_pntr_plus1_pf_carry,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[7]_i_2__0_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[0]_i_1__0_n_0\,
Q => \^q\(0),
S => wrst_busy
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => wrst_busy
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => wrst_busy
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => wrst_busy
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => wrst_busy
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => wrst_busy
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => wrst_busy
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(3),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(2),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(1),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(0),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(6),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(5),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(4),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0\,
CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_1\,
CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_2\,
CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_3\,
CYINIT => wr_pntr_plus1_pf_carry,
DI(3 downto 0) => \^q\(3 downto 0),
O(3) => D(0),
O(2 downto 0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_O_UNCONNECTED\(2 downto 0),
S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0\,
S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0\,
S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0\,
S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0\,
CO(3) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\,
CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\,
CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^q\(6 downto 4),
O(3 downto 0) => D(4 downto 1),
S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\,
S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\,
S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\,
S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_4\ is
port (
Q : out STD_LOGIC_VECTOR ( 7 downto 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_pntr_plus1_pf_carry : in STD_LOGIC;
wr_en : in STD_LOGIC;
\count_value_i_reg[6]_0\ : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_4\ : entity is "xpm_counter_updn";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_4\ is
signal \^q\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \count_value_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[6]_i_2__0_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \count_value_i[7]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count_value_i[1]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \count_value_i[2]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \count_value_i[3]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \count_value_i[4]_i_1__0\ : label is "soft_lutpair65";
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1\ : label is 35;
attribute ADDER_THRESHOLD of \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\ : label is 35;
begin
Q(7 downto 0) <= \^q\(7 downto 0);
\count_value_i[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \count_value_i[0]_i_1__0_n_0\
);
\count_value_i[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_value_i[1]_i_1__0_n_0\
);
\count_value_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \count_value_i[2]_i_1__0_n_0\
);
\count_value_i[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \count_value_i[3]_i_1__0_n_0\
);
\count_value_i[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => \count_value_i[4]_i_1__0_n_0\
);
\count_value_i[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(3),
I1 => \count_value_i[6]_i_2__0_n_0\,
I2 => \^q\(2),
I3 => \^q\(4),
I4 => \^q\(5),
O => \count_value_i[5]_i_1__0_n_0\
);
\count_value_i[6]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \count_value_i[6]_i_2__0_n_0\,
I3 => \^q\(3),
I4 => \^q\(5),
I5 => \^q\(6),
O => \count_value_i[6]_i_1__0_n_0\
);
\count_value_i[6]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => \^q\(1),
I1 => wr_en,
I2 => \count_value_i_reg[6]_0\,
I3 => wrst_busy,
I4 => rst_d1,
I5 => \^q\(0),
O => \count_value_i[6]_i_2__0_n_0\
);
\count_value_i[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(5),
I1 => \count_value_i[7]_i_2__0_n_0\,
I2 => \^q\(6),
I3 => \^q\(7),
O => \count_value_i[7]_i_1__0_n_0\
);
\count_value_i[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(4),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => wr_pntr_plus1_pf_carry,
I4 => \^q\(1),
I5 => \^q\(3),
O => \count_value_i[7]_i_2__0_n_0\
);
\count_value_i_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[0]_i_1__0_n_0\,
Q => \^q\(0),
S => wrst_busy
);
\count_value_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => wrst_busy
);
\count_value_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => wrst_busy
);
\count_value_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => wrst_busy
);
\count_value_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => wrst_busy
);
\count_value_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => wrst_busy
);
\count_value_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => wrst_busy
);
\count_value_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => wr_pntr_plus1_pf_carry,
D => \count_value_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(3),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(2),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(1),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(0),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(6),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(5),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(4),
O => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0\,
CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_1\,
CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_2\,
CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_3\,
CYINIT => wr_pntr_plus1_pf_carry,
DI(3 downto 0) => \^q\(3 downto 0),
O(3) => D(0),
O(2 downto 0) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_O_UNCONNECTED\(2 downto 0),
S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_2_n_0\,
S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_3_n_0\,
S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_4_n_0\,
S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[4]_i_5_n_0\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]_i_1_n_0\,
CO(3) => \NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1\,
CO(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2\,
CO(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^q\(6 downto 4),
O(3 downto 0) => D(4 downto 1),
S(3) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0\,
S(2) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0\,
S(1) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0\,
S(0) => \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit is
port (
rst_d1 : out STD_LOGIC;
d_out_reg_0 : out STD_LOGIC;
overflow_i0 : out STD_LOGIC;
clr_full : out STD_LOGIC;
wrst_busy : in STD_LOGIC;
wr_clk : in STD_LOGIC;
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC;
rst : in STD_LOGIC;
\gof.overflow_i_reg\ : in STD_LOGIC;
prog_full : in STD_LOGIC;
wr_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit is
signal \^rst_d1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_3\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair61";
begin
rst_d1 <= \^rst_d1\;
d_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wrst_busy,
Q => \^rst_d1\,
R => '0'
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => rst,
I1 => \^rst_d1\,
I2 => wrst_busy,
O => clr_full
);
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F3A200A2"
)
port map (
I0 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\,
I1 => \^rst_d1\,
I2 => rst,
I3 => \gof.overflow_i_reg\,
I4 => prog_full,
O => d_out_reg_0
);
\gof.overflow_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \^rst_d1\,
I1 => wrst_busy,
I2 => \gof.overflow_i_reg\,
I3 => wr_en,
O => overflow_i0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_13 is
port (
rst_d1 : out STD_LOGIC;
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\ : out STD_LOGIC;
overflow_i0 : out STD_LOGIC;
d_out_reg_0 : out STD_LOGIC;
wrst_busy : in STD_LOGIC;
wr_clk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ : in STD_LOGIC;
prog_full : in STD_LOGIC;
rst : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_13 : entity is "xpm_fifo_reg_bit";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_13;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_13 is
signal \^rst_d1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gof.overflow_i_i_1\ : label is "soft_lutpair23";
begin
rst_d1 <= \^rst_d1\;
d_out_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wrst_busy,
Q => \^rst_d1\,
R => '0'
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => rst,
I1 => \^rst_d1\,
I2 => wrst_busy,
O => d_out_reg_0
);
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E200E2E2"
)
port map (
I0 => p_1_in,
I1 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\,
I2 => prog_full,
I3 => rst,
I4 => \^rst_d1\,
I5 => wrst_busy,
O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\
);
\gof.overflow_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => \^rst_d1\,
I1 => wrst_busy,
I2 => \gen_pf_ic_rc.gpf_ic.prog_full_i_reg\,
I3 => wr_en,
O => overflow_i0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec is
port (
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\ : out STD_LOGIC;
\reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
d_out_reg : out STD_LOGIC;
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg\ : in STD_LOGIC;
rst : in STD_LOGIC;
clr_full : in STD_LOGIC;
almost_full : in STD_LOGIC;
wr_pntr_plus1_pf_carry : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_d1 : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec is
signal \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\ : STD_LOGIC;
signal going_afull : STD_LOGIC;
signal leaving_afull : STD_LOGIC;
signal leaving_full : STD_LOGIC;
signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00FFFE0000000E"
)
port map (
I0 => leaving_afull,
I1 => going_afull,
I2 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg\,
I3 => rst,
I4 => clr_full,
I5 => almost_full,
O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4_n_0\,
I1 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0\,
I2 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0\,
I3 => wr_pntr_plus1_pf_carry,
O => going_afull
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(0),
I2 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(2),
I3 => \^reg_out_i_reg[7]_0\(2),
I4 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(1),
I5 => \^reg_out_i_reg[7]_0\(1),
O => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_4_n_0\
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(3),
I2 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(5),
I3 => \^reg_out_i_reg[7]_0\(5),
I4 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(4),
I5 => \^reg_out_i_reg[7]_0\(4),
O => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0\
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(6),
I1 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(6),
I2 => \^reg_out_i_reg[7]_0\(7),
I3 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(7),
O => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0\
);
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EAEA00EA"
)
port map (
I0 => leaving_full,
I1 => leaving_afull,
I2 => wr_pntr_plus1_pf_carry,
I3 => rst_d1,
I4 => rst,
O => d_out_reg
);
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => Q(7),
I1 => \^reg_out_i_reg[7]_0\(7),
I2 => Q(6),
I3 => \^reg_out_i_reg[7]_0\(6),
I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\,
I5 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\,
O => leaving_full
);
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(7),
I1 => \^reg_out_i_reg[7]_0\(7),
I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(6),
I3 => \^reg_out_i_reg[7]_0\(6),
I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\,
I5 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\,
O => leaving_afull
);
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => Q(3),
I2 => Q(5),
I3 => \^reg_out_i_reg[7]_0\(5),
I4 => Q(4),
I5 => \^reg_out_i_reg[7]_0\(4),
O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0\
);
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => Q(0),
I2 => Q(2),
I3 => \^reg_out_i_reg[7]_0\(2),
I4 => Q(1),
I5 => \^reg_out_i_reg[7]_0\(1),
O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0\
);
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(3),
I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(5),
I3 => \^reg_out_i_reg[7]_0\(5),
I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(4),
I5 => \^reg_out_i_reg[7]_0\(4),
O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0\
);
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(0),
I2 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(2),
I3 => \^reg_out_i_reg[7]_0\(2),
I4 => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(1),
I5 => \^reg_out_i_reg[7]_0\(1),
O => \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0\
);
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(0),
Q => \^reg_out_i_reg[7]_0\(0),
R => wrst_busy
);
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(1),
Q => \^reg_out_i_reg[7]_0\(1),
R => wrst_busy
);
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(2),
Q => \^reg_out_i_reg[7]_0\(2),
R => wrst_busy
);
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(3),
Q => \^reg_out_i_reg[7]_0\(3),
R => wrst_busy
);
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(4),
Q => \^reg_out_i_reg[7]_0\(4),
R => wrst_busy
);
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(5),
Q => \^reg_out_i_reg[7]_0\(5),
R => wrst_busy
);
\reg_out_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(6),
Q => \^reg_out_i_reg[7]_0\(6),
R => wrst_busy
);
\reg_out_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(7),
Q => \^reg_out_i_reg[7]_0\(7),
R => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_1 is
port (
ram_empty_i0 : out STD_LOGIC;
\reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
ram_empty_i : in STD_LOGIC;
\gen_pf_ic_rc.ram_empty_i_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_pf_ic_rc.ram_empty_i_reg_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\reg_out_i_reg[0]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_1 : entity is "xpm_fifo_reg_vec";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_1 is
signal \gen_pf_ic_rc.ram_empty_i_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ram_empty_i_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ : STD_LOGIC;
signal going_empty0 : STD_LOGIC;
signal leaving_empty : STD_LOGIC;
signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0);
\gen_pf_ic_rc.ram_empty_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00FD0000"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => rd_en,
I3 => ram_empty_i,
I4 => going_empty0,
I5 => leaving_empty,
O => ram_empty_i0
);
\gen_pf_ic_rc.ram_empty_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \gen_pf_ic_rc.ram_empty_i_reg_0\(7),
I1 => \^reg_out_i_reg[7]_0\(7),
I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(6),
I3 => \^reg_out_i_reg[7]_0\(6),
I4 => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\,
I5 => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\,
O => going_empty0
);
\gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \gen_pf_ic_rc.ram_empty_i_reg\(7),
I1 => \^reg_out_i_reg[7]_0\(7),
I2 => \gen_pf_ic_rc.ram_empty_i_reg\(6),
I3 => \^reg_out_i_reg[7]_0\(6),
I4 => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\,
I5 => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\,
O => leaving_empty
);
\gen_pf_ic_rc.ram_empty_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\(3),
I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(5),
I3 => \^reg_out_i_reg[7]_0\(5),
I4 => \gen_pf_ic_rc.ram_empty_i_reg_0\(4),
I5 => \^reg_out_i_reg[7]_0\(4),
O => \gen_pf_ic_rc.ram_empty_i_i_4_n_0\
);
\gen_pf_ic_rc.ram_empty_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => \gen_pf_ic_rc.ram_empty_i_reg_0\(0),
I2 => \gen_pf_ic_rc.ram_empty_i_reg_0\(2),
I3 => \^reg_out_i_reg[7]_0\(2),
I4 => \gen_pf_ic_rc.ram_empty_i_reg_0\(1),
I5 => \^reg_out_i_reg[7]_0\(1),
O => \gen_pf_ic_rc.ram_empty_i_i_5_n_0\
);
\gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => \gen_pf_ic_rc.ram_empty_i_reg\(3),
I2 => \gen_pf_ic_rc.ram_empty_i_reg\(5),
I3 => \^reg_out_i_reg[7]_0\(5),
I4 => \gen_pf_ic_rc.ram_empty_i_reg\(4),
I5 => \^reg_out_i_reg[7]_0\(4),
O => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\
);
\gen_pf_ic_rc.ram_empty_i_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => \gen_pf_ic_rc.ram_empty_i_reg\(0),
I2 => \gen_pf_ic_rc.ram_empty_i_reg\(2),
I3 => \^reg_out_i_reg[7]_0\(2),
I4 => \gen_pf_ic_rc.ram_empty_i_reg\(1),
I5 => \^reg_out_i_reg[7]_0\(1),
O => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\
);
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(0),
Q => \^reg_out_i_reg[7]_0\(0),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(1),
Q => \^reg_out_i_reg[7]_0\(1),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(2),
Q => \^reg_out_i_reg[7]_0\(2),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(3),
Q => \^reg_out_i_reg[7]_0\(3),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(4),
Q => \^reg_out_i_reg[7]_0\(4),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(5),
Q => \^reg_out_i_reg[7]_0\(5),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(6),
Q => \^reg_out_i_reg[7]_0\(6),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(7),
Q => \^reg_out_i_reg[7]_0\(7),
R => \reg_out_i_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_6 is
port (
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg\ : out STD_LOGIC;
\reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i0 : out STD_LOGIC;
almost_full : in STD_LOGIC;
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_0\ : in STD_LOGIC;
wr_pntr_plus1_pf_carry : in STD_LOGIC;
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\ : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
wrst_busy : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_6 : entity is "xpm_fifo_reg_vec";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_6;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_6 is
signal \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_6_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_7_n_0\ : STD_LOGIC;
signal going_afull0 : STD_LOGIC;
signal leaving_afull : STD_LOGIC;
signal leaving_full : STD_LOGIC;
signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE2E2E2"
)
port map (
I0 => almost_full,
I1 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_0\,
I2 => leaving_afull,
I3 => going_afull0,
I4 => wr_pntr_plus1_pf_carry,
I5 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_1\,
O => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg\
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(7),
I1 => \^reg_out_i_reg[7]_0\(7),
I2 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(6),
I3 => \^reg_out_i_reg[7]_0\(6),
I4 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0\,
I5 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0\,
O => going_afull0
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(3),
I2 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(5),
I3 => \^reg_out_i_reg[7]_0\(5),
I4 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(4),
I5 => \^reg_out_i_reg[7]_0\(4),
O => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_5_n_0\
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(0),
I2 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(2),
I3 => \^reg_out_i_reg[7]_0\(2),
I4 => \gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(1),
I5 => \^reg_out_i_reg[7]_0\(1),
O => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_6_n_0\
);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF0200"
)
port map (
I0 => wr_en,
I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\,
I2 => rst_d1,
I3 => leaving_afull,
I4 => leaving_full,
O => ram_full_i0
);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(7),
I1 => \^reg_out_i_reg[7]_0\(7),
I2 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(6),
I3 => \^reg_out_i_reg[7]_0\(6),
I4 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4_n_0\,
I5 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\,
O => leaving_afull
);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => Q(7),
I1 => \^reg_out_i_reg[7]_0\(7),
I2 => Q(6),
I3 => \^reg_out_i_reg[7]_0\(6),
I4 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_6_n_0\,
I5 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_7_n_0\,
O => leaving_full
);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(3),
I2 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(5),
I3 => \^reg_out_i_reg[7]_0\(5),
I4 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(4),
I5 => \^reg_out_i_reg[7]_0\(4),
O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_4_n_0\
);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(0),
I2 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(2),
I3 => \^reg_out_i_reg[7]_0\(2),
I4 => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(1),
I5 => \^reg_out_i_reg[7]_0\(1),
O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_5_n_0\
);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => Q(3),
I2 => Q(5),
I3 => \^reg_out_i_reg[7]_0\(5),
I4 => Q(4),
I5 => \^reg_out_i_reg[7]_0\(4),
O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_6_n_0\
);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => Q(0),
I2 => Q(2),
I3 => \^reg_out_i_reg[7]_0\(2),
I4 => Q(1),
I5 => \^reg_out_i_reg[7]_0\(1),
O => \gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_i_7_n_0\
);
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(0),
Q => \^reg_out_i_reg[7]_0\(0),
R => wrst_busy
);
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(1),
Q => \^reg_out_i_reg[7]_0\(1),
R => wrst_busy
);
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(2),
Q => \^reg_out_i_reg[7]_0\(2),
R => wrst_busy
);
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(3),
Q => \^reg_out_i_reg[7]_0\(3),
R => wrst_busy
);
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(4),
Q => \^reg_out_i_reg[7]_0\(4),
R => wrst_busy
);
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(5),
Q => \^reg_out_i_reg[7]_0\(5),
R => wrst_busy
);
\reg_out_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(6),
Q => \^reg_out_i_reg[7]_0\(6),
R => wrst_busy
);
\reg_out_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(7),
Q => \^reg_out_i_reg[7]_0\(7),
R => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_8 is
port (
\count_value_i_reg[7]\ : out STD_LOGIC;
\reg_out_i_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
S : out STD_LOGIC_VECTOR ( 2 downto 0 );
\reg_out_i_reg[7]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\reg_out_i_reg[0]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_8 : entity is "xpm_fifo_reg_vec";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_8;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_8 is
signal \gen_pf_ic_rc.ram_empty_i_i_6_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.ram_empty_i_i_7_n_0\ : STD_LOGIC;
signal \^reg_out_i_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
\reg_out_i_reg[7]_0\(7 downto 0) <= \^reg_out_i_reg[7]_0\(7 downto 0);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => Q(3),
O => S(2)
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(2),
I1 => Q(2),
O => S(1)
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[3]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(1),
I1 => Q(1),
O => S(0)
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(7),
I1 => Q(7),
O => \reg_out_i_reg[7]_1\(3)
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(6),
I1 => Q(6),
O => \reg_out_i_reg[7]_1\(2)
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(5),
I1 => Q(5),
O => \reg_out_i_reg[7]_1\(1)
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(4),
I1 => Q(4),
O => \reg_out_i_reg[7]_1\(0)
);
\gen_pf_ic_rc.ram_empty_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000009009"
)
port map (
I0 => Q(7),
I1 => \^reg_out_i_reg[7]_0\(7),
I2 => Q(6),
I3 => \^reg_out_i_reg[7]_0\(6),
I4 => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\,
I5 => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\,
O => \count_value_i_reg[7]\
);
\gen_pf_ic_rc.ram_empty_i_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(0),
I1 => Q(0),
I2 => Q(1),
I3 => \^reg_out_i_reg[7]_0\(1),
I4 => Q(2),
I5 => \^reg_out_i_reg[7]_0\(2),
O => \gen_pf_ic_rc.ram_empty_i_i_6_n_0\
);
\gen_pf_ic_rc.ram_empty_i_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^reg_out_i_reg[7]_0\(3),
I1 => Q(3),
I2 => Q(4),
I3 => \^reg_out_i_reg[7]_0\(4),
I4 => Q(5),
I5 => \^reg_out_i_reg[7]_0\(5),
O => \gen_pf_ic_rc.ram_empty_i_i_7_n_0\
);
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(0),
Q => \^reg_out_i_reg[7]_0\(0),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(1),
Q => \^reg_out_i_reg[7]_0\(1),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(2),
Q => \^reg_out_i_reg[7]_0\(2),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(3),
Q => \^reg_out_i_reg[7]_0\(3),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(4),
Q => \^reg_out_i_reg[7]_0\(4),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(5),
Q => \^reg_out_i_reg[7]_0\(5),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(6),
Q => \^reg_out_i_reg[7]_0\(6),
R => \reg_out_i_reg[0]_0\
);
\reg_out_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => D(7),
Q => \^reg_out_i_reg[7]_0\(7),
R => \reg_out_i_reg[0]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
wrst_busy : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\ : entity is "xpm_fifo_reg_vec";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\ is
begin
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(0),
Q => Q(0),
R => wrst_busy
);
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(1),
Q => Q(1),
R => wrst_busy
);
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(2),
Q => Q(2),
R => wrst_busy
);
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(3),
Q => Q(3),
R => wrst_busy
);
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(4),
Q => Q(4),
R => wrst_busy
);
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(5),
Q => Q(5),
R => wrst_busy
);
\reg_out_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(6),
Q => Q(6),
R => wrst_busy
);
\reg_out_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(7),
Q => Q(7),
R => wrst_busy
);
\reg_out_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(8),
Q => Q(8),
R => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_2\ is
port (
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
DI : in STD_LOGIC_VECTOR ( 1 downto 0 );
S : in STD_LOGIC_VECTOR ( 2 downto 0 );
\grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC;
\grdc.rd_data_count_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\reg_out_i_reg[8]_0\ : in STD_LOGIC;
\reg_out_i_reg[8]_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_2\ : entity is "xpm_fifo_reg_vec";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_2\ is
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \grdc.rd_data_count_i[3]_i_2_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[3]_i_6_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[7]_i_2_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[7]_i_3_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[7]_i_4_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[7]_i_5_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[3]_i_1\ : label is 35;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[7]_i_1\ : label is 35;
attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[8]_i_2\ : label is 35;
attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[8]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
Q(8 downto 0) <= \^q\(8 downto 0);
\grdc.rd_data_count_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(2),
I1 => \grdc.rd_data_count_i_reg[7]_0\(1),
O => \grdc.rd_data_count_i[3]_i_2_n_0\
);
\grdc.rd_data_count_i[3]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"718E8E71"
)
port map (
I0 => \^q\(1),
I1 => \grdc.rd_data_count_i_reg[3]\,
I2 => \grdc.rd_data_count_i_reg[7]_0\(0),
I3 => \grdc.rd_data_count_i_reg[7]_0\(1),
I4 => \^q\(2),
O => \grdc.rd_data_count_i[3]_i_6_n_0\
);
\grdc.rd_data_count_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
I1 => \grdc.rd_data_count_i_reg[7]_0\(5),
O => \grdc.rd_data_count_i[7]_i_2_n_0\
);
\grdc.rd_data_count_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
I1 => \grdc.rd_data_count_i_reg[7]_0\(4),
O => \grdc.rd_data_count_i[7]_i_3_n_0\
);
\grdc.rd_data_count_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
I1 => \grdc.rd_data_count_i_reg[7]_0\(3),
O => \grdc.rd_data_count_i[7]_i_4_n_0\
);
\grdc.rd_data_count_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(3),
I1 => \grdc.rd_data_count_i_reg[7]_0\(2),
O => \grdc.rd_data_count_i[7]_i_5_n_0\
);
\grdc.rd_data_count_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \grdc.rd_data_count_i_reg[3]_i_1_n_0\,
CO(2) => \grdc.rd_data_count_i_reg[3]_i_1_n_1\,
CO(1) => \grdc.rd_data_count_i_reg[3]_i_1_n_2\,
CO(0) => \grdc.rd_data_count_i_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \grdc.rd_data_count_i[3]_i_2_n_0\,
DI(2 downto 1) => DI(1 downto 0),
DI(0) => \^q\(0),
O(3 downto 0) => D(3 downto 0),
S(3) => S(2),
S(2) => \grdc.rd_data_count_i[3]_i_6_n_0\,
S(1 downto 0) => S(1 downto 0)
);
\grdc.rd_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \grdc.rd_data_count_i_reg[3]_i_1_n_0\,
CO(3) => \grdc.rd_data_count_i_reg[7]_i_1_n_0\,
CO(2) => \grdc.rd_data_count_i_reg[7]_i_1_n_1\,
CO(1) => \grdc.rd_data_count_i_reg[7]_i_1_n_2\,
CO(0) => \grdc.rd_data_count_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \grdc.rd_data_count_i[7]_i_2_n_0\,
DI(2) => \grdc.rd_data_count_i[7]_i_3_n_0\,
DI(1) => \grdc.rd_data_count_i[7]_i_4_n_0\,
DI(0) => \grdc.rd_data_count_i[7]_i_5_n_0\,
O(3 downto 0) => D(7 downto 4),
S(3 downto 0) => \grdc.rd_data_count_i_reg[7]\(3 downto 0)
);
\grdc.rd_data_count_i_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \grdc.rd_data_count_i_reg[7]_i_1_n_0\,
CO(3 downto 0) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\(3 downto 1),
O(0) => D(8),
S(3 downto 1) => B"000",
S(0) => \grdc.rd_data_count_i_reg[8]\(0)
);
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(0),
Q => \^q\(0),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(1),
Q => \^q\(1),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(2),
Q => \^q\(2),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(3),
Q => \^q\(3),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(4),
Q => \^q\(4),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(5),
Q => \^q\(5),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(6),
Q => \^q\(6),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(7),
Q => \^q\(7),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(8),
Q => \^q\(8),
R => \reg_out_i_reg[8]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_7\ is
port (
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
wrst_busy : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 8 downto 0 );
wr_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_7\ : entity is "xpm_fifo_reg_vec";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_7\ is
begin
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(0),
Q => Q(0),
R => wrst_busy
);
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(1),
Q => Q(1),
R => wrst_busy
);
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(2),
Q => Q(2),
R => wrst_busy
);
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(3),
Q => Q(3),
R => wrst_busy
);
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(4),
Q => Q(4),
R => wrst_busy
);
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(5),
Q => Q(5),
R => wrst_busy
);
\reg_out_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(6),
Q => Q(6),
R => wrst_busy
);
\reg_out_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(7),
Q => Q(7),
R => wrst_busy
);
\reg_out_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => D(8),
Q => Q(8),
R => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_9\ is
port (
Q : out STD_LOGIC_VECTOR ( 8 downto 0 );
D : out STD_LOGIC_VECTOR ( 8 downto 0 );
\grdc.rd_data_count_i_reg[7]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\grdc.rd_data_count_i_reg[3]\ : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grdc.rd_data_count_i_reg[7]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grdc.rd_data_count_i_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\reg_out_i_reg[8]_0\ : in STD_LOGIC;
\reg_out_i_reg[8]_1\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_9\ : entity is "xpm_fifo_reg_vec";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_9\ is
signal \^q\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \grdc.rd_data_count_i[3]_i_2_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[3]_i_3_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[7]_i_2_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[7]_i_3_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[7]_i_4_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i[7]_i_5_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \grdc.rd_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
attribute ADDER_THRESHOLD : integer;
attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[3]_i_1\ : label is 35;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[3]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[7]_i_1\ : label is 35;
attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[7]_i_1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute ADDER_THRESHOLD of \grdc.rd_data_count_i_reg[8]_i_2\ : label is 35;
attribute METHODOLOGY_DRC_VIOS of \grdc.rd_data_count_i_reg[8]_i_2\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
Q(8 downto 0) <= \^q\(8 downto 0);
\grdc.rd_data_count_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(2),
I1 => \grdc.rd_data_count_i_reg[7]\(1),
O => \grdc.rd_data_count_i[3]_i_2_n_0\
);
\grdc.rd_data_count_i[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"8E"
)
port map (
I0 => \^q\(1),
I1 => \grdc.rd_data_count_i_reg[3]\,
I2 => \grdc.rd_data_count_i_reg[7]\(0),
O => \grdc.rd_data_count_i[3]_i_3_n_0\
);
\grdc.rd_data_count_i[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
I1 => \grdc.rd_data_count_i_reg[7]\(5),
O => \grdc.rd_data_count_i[7]_i_2_n_0\
);
\grdc.rd_data_count_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
I1 => \grdc.rd_data_count_i_reg[7]\(4),
O => \grdc.rd_data_count_i[7]_i_3_n_0\
);
\grdc.rd_data_count_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
I1 => \grdc.rd_data_count_i_reg[7]\(3),
O => \grdc.rd_data_count_i[7]_i_4_n_0\
);
\grdc.rd_data_count_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(3),
I1 => \grdc.rd_data_count_i_reg[7]\(2),
O => \grdc.rd_data_count_i[7]_i_5_n_0\
);
\grdc.rd_data_count_i_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \grdc.rd_data_count_i_reg[3]_i_1_n_0\,
CO(2) => \grdc.rd_data_count_i_reg[3]_i_1_n_1\,
CO(1) => \grdc.rd_data_count_i_reg[3]_i_1_n_2\,
CO(0) => \grdc.rd_data_count_i_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3) => \grdc.rd_data_count_i[3]_i_2_n_0\,
DI(2) => \grdc.rd_data_count_i[3]_i_3_n_0\,
DI(1) => DI(0),
DI(0) => \^q\(0),
O(3 downto 0) => D(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\grdc.rd_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \grdc.rd_data_count_i_reg[3]_i_1_n_0\,
CO(3) => \grdc.rd_data_count_i_reg[7]_i_1_n_0\,
CO(2) => \grdc.rd_data_count_i_reg[7]_i_1_n_1\,
CO(1) => \grdc.rd_data_count_i_reg[7]_i_1_n_2\,
CO(0) => \grdc.rd_data_count_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => \grdc.rd_data_count_i[7]_i_2_n_0\,
DI(2) => \grdc.rd_data_count_i[7]_i_3_n_0\,
DI(1) => \grdc.rd_data_count_i[7]_i_4_n_0\,
DI(0) => \grdc.rd_data_count_i[7]_i_5_n_0\,
O(3 downto 0) => D(7 downto 4),
S(3 downto 0) => \grdc.rd_data_count_i_reg[7]_0\(3 downto 0)
);
\grdc.rd_data_count_i_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \grdc.rd_data_count_i_reg[7]_i_1_n_0\,
CO(3 downto 0) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 1) => \NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED\(3 downto 1),
O(0) => D(8),
S(3 downto 1) => B"000",
S(0) => \grdc.rd_data_count_i_reg[8]\(0)
);
\reg_out_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(0),
Q => \^q\(0),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(1),
Q => \^q\(1),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(2),
Q => \^q\(2),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(3),
Q => \^q\(3),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(4),
Q => \^q\(4),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(5),
Q => \^q\(5),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(6),
Q => \^q\(6),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(7),
Q => \^q\(7),
R => \reg_out_i_reg[8]_0\
);
\reg_out_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \reg_out_i_reg[8]_1\(8),
Q => \^q\(8),
R => \reg_out_i_reg[8]_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute ECC_MODE : integer;
attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute IGNORE_INIT_SYNTH : integer;
attribute IGNORE_INIT_SYNTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "";
attribute MEMORY_OPTIMIZATION : string;
attribute MEMORY_OPTIMIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "true";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2048;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 256;
attribute P_MEMORY_OPT : string;
attribute P_MEMORY_OPT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "yes";
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "auto";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "0";
attribute RST_MODE_A : string;
attribute RST_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "SYNC";
attribute RST_MODE_B : string;
attribute RST_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "SYNC";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute USE_EMBEDDED_CONSTRAINT : integer;
attribute USE_EMBEDDED_CONSTRAINT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute USE_MEM_INIT_MMI : integer;
attribute USE_MEM_INIT_MMI of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute VERSION : integer;
attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 2;
attribute WRITE_PROTECT : integer;
attribute WRITE_PROTECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is "soft";
attribute rsta_loop_iter : integer;
attribute rsta_loop_iter of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
attribute rstb_loop_iter : integer;
attribute rstb_loop_iter of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base : entity is 8;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base is
signal \<const0>\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 1023;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d8";
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 7;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 1023;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d8";
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 7;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 2048;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute RTL_RAM_TYPE : string;
attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "RAM_SDP";
attribute ram_addr_begin : integer;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute ram_addr_end : integer;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 1023;
attribute ram_offset : integer;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute ram_slice_begin : integer;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute ram_slice_end : integer;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 7;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_a.gen_word_narrow.mem_reg\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => addra(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 12) => B"00",
ADDRBWRADDR(11 downto 4) => addrb(7 downto 0),
ADDRBWRADDR(3 downto 0) => B"0000",
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000011111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 8) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED\(15 downto 8),
DOBDO(7 downto 0) => doutb(7 downto 0),
DOPADOP(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => enb,
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
WEA(1) => ena,
WEA(0) => ena,
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute ECC_MODE : integer;
attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute IGNORE_INIT_SYNTH : integer;
attribute IGNORE_INIT_SYNTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "";
attribute MEMORY_OPTIMIZATION : string;
attribute MEMORY_OPTIMIZATION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "true";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 2048;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 256;
attribute P_MEMORY_OPT : string;
attribute P_MEMORY_OPT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "yes";
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "auto";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 2;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 2;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "0";
attribute RST_MODE_A : string;
attribute RST_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "SYNC";
attribute RST_MODE_B : string;
attribute RST_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "SYNC";
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute USE_EMBEDDED_CONSTRAINT : integer;
attribute USE_EMBEDDED_CONSTRAINT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute USE_MEM_INIT_MMI : integer;
attribute USE_MEM_INIT_MMI of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 2;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 2;
attribute WRITE_PROTECT : integer;
attribute WRITE_PROTECT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "TRUE";
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is "soft";
attribute rsta_loop_iter : integer;
attribute rsta_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
attribute rstb_loop_iter : integer;
attribute rstb_loop_iter of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ : entity is 8;
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\ is
signal \<const0>\ : STD_LOGIC;
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 1023;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d8";
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 7;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 1023;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "p0_d8";
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 7;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 2048;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "gen_wr_a.gen_word_narrow.mem";
attribute RTL_RAM_TYPE : string;
attribute RTL_RAM_TYPE of \gen_wr_a.gen_word_narrow.mem_reg\ : label is "RAM_SDP";
attribute ram_addr_begin : integer;
attribute ram_addr_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute ram_addr_end : integer;
attribute ram_addr_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 1023;
attribute ram_offset : integer;
attribute ram_offset of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute ram_slice_begin : integer;
attribute ram_slice_begin of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 0;
attribute ram_slice_end : integer;
attribute ram_slice_end of \gen_wr_a.gen_word_narrow.mem_reg\ : label is 7;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_a.gen_word_narrow.mem_reg\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => addra(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 12) => B"00",
ADDRBWRADDR(11 downto 4) => addrb(7 downto 0),
ADDRBWRADDR(3 downto 0) => B"0000",
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 8) => B"00000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(15 downto 0) => B"0000000011111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 8) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOBDO_UNCONNECTED\(15 downto 8),
DOBDO(7 downto 0) => doutb(7 downto 0),
DOPADOP(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_gen_wr_a.gen_word_narrow.mem_reg_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => enb,
REGCEAREGCE => '0',
REGCEB => regceb,
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => rstb,
WEA(1) => ena,
WEA(0) => ena,
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_qspi_enhanced_mode is
port (
p_1_in : out STD_LOGIC;
p_2_in : out STD_LOGIC;
p_4_in : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_awready : out STD_LOGIC;
s_axi4_arready : out STD_LOGIC;
s_axi4_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2bus_error_int : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
s_axi4_bvalid : out STD_LOGIC;
burst_tr_int : out STD_LOGIC;
s_axi4_rlast : out STD_LOGIC;
Bus_RNW_reg_reg : out STD_LOGIC;
Bus_RNW_reg_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg_reg_1 : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\ : out STD_LOGIC;
ip2Bus_WrAck_core_reg0 : out STD_LOGIC;
wr_ce_or_reduce_core_cmb : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\FSM_onehot_axi_full_sm_ps_reg[2]_0\ : out STD_LOGIC;
reset_trig0 : out STD_LOGIC;
sw_rst_cond : out STD_LOGIC;
Transmit_ip2bus_error0 : out STD_LOGIC;
s_axi4_wready : out STD_LOGIC;
IP2Bus_WrAck_transmit_enable : out STD_LOGIC;
rd_en : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ : out STD_LOGIC;
reset2ip_reset_int : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ : out STD_LOGIC;
bus2ip_wrce_int : out STD_LOGIC_VECTOR ( 0 to 0 );
irpt_wrack : out STD_LOGIC;
interrupt_wrce_strb : out STD_LOGIC;
\ip_irpt_enable_reg_reg[1]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[2]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[3]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[4]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[5]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[6]\ : out STD_LOGIC;
\ip_irpt_enable_reg_reg[7]\ : out STD_LOGIC;
irpt_rdack : out STD_LOGIC;
intr2bus_rdack0 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
\bus2ip_BE_reg_reg[3]_0\ : out STD_LOGIC;
rd_ce_or_reduce_core_cmb : out STD_LOGIC;
intr_controller_rd_ce_or_reduce : out STD_LOGIC;
s_axi4_wdata_0_sp_1 : out STD_LOGIC;
\s_axi4_wdata[31]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : out STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : out STD_LOGIC;
s_axi4_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi4_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi4_arvalid : in STD_LOGIC;
s_axi4_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi4_rready : in STD_LOGIC;
ip2Bus_WrAck_core_reg : in STD_LOGIC;
empty : in STD_LOGIC;
ip2Bus_WrAck_core_reg_d1 : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : in STD_LOGIC;
s_axi4_bready : in STD_LOGIC;
s_axi4_awvalid : in STD_LOGIC;
s_axi4_wvalid : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
s_axi4_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rvalid_i_reg_1 : in STD_LOGIC;
data_valid : in STD_LOGIC;
\FSM_onehot_axi_full_sm_ps_reg[3]_0\ : in STD_LOGIC;
transmit_ip2bus_error : in STD_LOGIC;
receive_ip2bus_error : in STD_LOGIC;
sw_rst_cond_d1 : in STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
Tx_FIFO_Full_int : in STD_LOGIC;
almost_full : in STD_LOGIC;
ip2Bus_RdAck_core_reg : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
s_axi4_wstrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[8]_0\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : in STD_LOGIC;
SPISSR_frm_axi_clk : in STD_LOGIC;
rx_fifo_empty_i : in STD_LOGIC;
spicr_0_loop_frm_axi_clk : in STD_LOGIC;
irpt_wrack_d1 : in STD_LOGIC;
p_1_in34_in : in STD_LOGIC;
p_1_in31_in : in STD_LOGIC;
p_1_in28_in : in STD_LOGIC;
spicr_4_cpha_frm_axi_clk : in STD_LOGIC;
p_1_in25_in : in STD_LOGIC;
p_1_in22_in : in STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : in STD_LOGIC;
p_1_in19_in : in STD_LOGIC;
p_1_in16_in : in STD_LOGIC;
spicr_7_ss_frm_axi_clk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
spicr_8_tr_inhibit_frm_axi_clk : in STD_LOGIC;
p_1_in13_in : in STD_LOGIC;
p_0_in : in STD_LOGIC_VECTOR ( 0 to 0 );
irpt_rdack_d1 : in STD_LOGIC;
scndry_out : in STD_LOGIC;
spicr_1_spe_frm_axi_clk : in STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : in STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : in STD_LOGIC;
spicr_3_cpol_frm_axi_clk : in STD_LOGIC;
spisel_d1_reg_to_axi_clk : in STD_LOGIC;
spicr_5_txfifo_rst_frm_axi_clk : in STD_LOGIC;
spicr_9_lsb_frm_axi_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_qspi_enhanced_mode;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_qspi_enhanced_mode is
signal \FSM_onehot_axi_full_sm_ps[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[3]_i_4_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[4]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[5]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[6]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps[7]_i_1_n_0\ : STD_LOGIC;
signal \^fsm_onehot_axi_full_sm_ps_reg[2]_0\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps_reg_n_0_[3]\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps_reg_n_0_[6]\ : STD_LOGIC;
signal \FSM_onehot_axi_full_sm_ps_reg_n_0_[7]\ : STD_LOGIC;
signal I_DECODER_n_13 : STD_LOGIC;
signal I_DECODER_n_14 : STD_LOGIC;
signal I_DECODER_n_15 : STD_LOGIC;
signal I_DECODER_n_21 : STD_LOGIC;
signal I_DECODER_n_24 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/IP2Bus_SPICR_Data_int\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/intr_ip2bus_data\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \S_AXI4_BRESP_i[1]_i_1_n_0\ : STD_LOGIC;
signal arready_cmb : STD_LOGIC;
signal awready_cmb : STD_LOGIC;
signal awready_i_i_10_n_0 : STD_LOGIC;
signal awready_i_i_3_n_0 : STD_LOGIC;
signal awready_i_i_5_n_0 : STD_LOGIC;
signal awready_i_i_6_n_0 : STD_LOGIC;
signal awready_i_i_7_n_0 : STD_LOGIC;
signal awready_i_i_8_n_0 : STD_LOGIC;
signal awready_i_i_9_n_0 : STD_LOGIC;
signal axi_full_sm_ps_IDLE_cmb : STD_LOGIC;
signal \^burst_tr_int\ : STD_LOGIC;
signal burst_transfer_cmb : STD_LOGIC;
signal burst_transfer_reg_i_1_n_0 : STD_LOGIC;
signal \bus2ip_BE_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_BE_reg[3]_i_1_n_0\ : STD_LOGIC;
signal bus2ip_be_int : STD_LOGIC_VECTOR ( 3 downto 0 );
signal clear : STD_LOGIC;
signal ip2bus_data_int : STD_LOGIC_VECTOR ( 8 to 8 );
signal \^ip2bus_error_int\ : STD_LOGIC;
signal last_data_acked_i_2_n_0 : STD_LOGIC;
signal last_data_acked_i_3_n_0 : STD_LOGIC;
signal last_data_acked_i_4_n_0 : STD_LOGIC;
signal last_data_acked_i_5_n_0 : STD_LOGIC;
signal last_data_acked_i_6_n_0 : STD_LOGIC;
signal last_data_acked_i_7_n_0 : STD_LOGIC;
signal \length_cntr[2]_i_2_n_0\ : STD_LOGIC;
signal \length_cntr[3]_i_2_n_0\ : STD_LOGIC;
signal \length_cntr[6]_i_2_n_0\ : STD_LOGIC;
signal \length_cntr[7]_i_1_n_0\ : STD_LOGIC;
signal \length_cntr[7]_i_3_n_0\ : STD_LOGIC;
signal \length_cntr[7]_i_4_n_0\ : STD_LOGIC;
signal \length_cntr[7]_i_5_n_0\ : STD_LOGIC;
signal length_cntr_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^reset2ip_reset_int\ : STD_LOGIC;
signal rnw_cmb : STD_LOGIC;
signal rnw_reg_i_2_n_0 : STD_LOGIC;
signal rnw_reg_i_3_n_0 : STD_LOGIC;
signal rnw_reg_reg_n_0 : STD_LOGIC;
signal \^s_axi4_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi4_bvalid\ : STD_LOGIC;
signal \^s_axi4_rlast\ : STD_LOGIC;
signal \s_axi4_rresp_i[1]_i_2_n_0\ : STD_LOGIC;
signal s_axi4_wdata_0_sn_1 : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rvalid_i_i_2_n_0 : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC;
signal s_axi_wready_i : STD_LOGIC;
signal s_axi_wready_i_i_1_n_0 : STD_LOGIC;
signal s_axi_wready_i_i_2_n_0 : STD_LOGIC;
signal start : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_i_4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_axi_full_sm_ps[1]_i_1\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \FSM_onehot_axi_full_sm_ps[2]_i_1\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \FSM_onehot_axi_full_sm_ps[4]_i_2\ : label is "soft_lutpair117";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_axi_full_sm_ps_reg[0]\ : label is "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101";
attribute FSM_ENCODED_STATES of \FSM_onehot_axi_full_sm_ps_reg[1]\ : label is "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101";
attribute FSM_ENCODED_STATES of \FSM_onehot_axi_full_sm_ps_reg[2]\ : label is "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101";
attribute FSM_ENCODED_STATES of \FSM_onehot_axi_full_sm_ps_reg[3]\ : label is "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101";
attribute FSM_ENCODED_STATES of \FSM_onehot_axi_full_sm_ps_reg[4]\ : label is "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101";
attribute FSM_ENCODED_STATES of \FSM_onehot_axi_full_sm_ps_reg[5]\ : label is "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101";
attribute FSM_ENCODED_STATES of \FSM_onehot_axi_full_sm_ps_reg[6]\ : label is "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101";
attribute FSM_ENCODED_STATES of \FSM_onehot_axi_full_sm_ps_reg[7]\ : label is "axi_wr:00010000,axi_single_wr:00100000,axi_rd:00000010,error_resp:1100,rd_resp_2:1011,rd_last:00001000,axi_single_rd:00000100,idle:00000001,wr_resp_1:01000000,wr_resp_2:10000000,check_axi_length_error:0101";
attribute SOFT_HLUTNM of arready_i_i_1 : label is "soft_lutpair113";
attribute SOFT_HLUTNM of awready_i_i_10 : label is "soft_lutpair119";
attribute SOFT_HLUTNM of awready_i_i_3 : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \bus2ip_BE_reg[0]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bus2ip_BE_reg[3]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of last_data_acked_i_2 : label is "soft_lutpair118";
attribute SOFT_HLUTNM of last_data_acked_i_7 : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \length_cntr[2]_i_2\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \length_cntr[7]_i_4\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \length_cntr[7]_i_5\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of rnw_reg_i_2 : label is "soft_lutpair114";
attribute SOFT_HLUTNM of rnw_reg_i_3 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axi4_wready_INST_0 : label is "soft_lutpair116";
attribute SOFT_HLUTNM of s_axi_wready_i_i_2 : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \xpm_fifo_instance.xpm_fifo_async_inst_i_4\ : label is "soft_lutpair116";
begin
\FSM_onehot_axi_full_sm_ps_reg[2]_0\ <= \^fsm_onehot_axi_full_sm_ps_reg[2]_0\;
Q(0) <= \^q\(0);
SR(0) <= \^sr\(0);
burst_tr_int <= \^burst_tr_int\;
ip2bus_error_int <= \^ip2bus_error_int\;
reset2ip_reset_int <= \^reset2ip_reset_int\;
s_axi4_bresp(0) <= \^s_axi4_bresp\(0);
s_axi4_bvalid <= \^s_axi4_bvalid\;
s_axi4_rlast <= \^s_axi4_rlast\;
s_axi4_wdata_0_sp_1 <= s_axi4_wdata_0_sn_1;
s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\;
Bus2IP_Reset_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => clear,
Q => \^sr\(0),
R => '0'
);
\FSM_onehot_axi_full_sm_ps[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFBA00"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[3]\,
I1 => I_DECODER_n_21,
I2 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
I3 => s_axi4_rready,
I4 => \FSM_onehot_axi_full_sm_ps[0]_i_2_n_0\,
O => \FSM_onehot_axi_full_sm_ps[0]_i_1_n_0\
);
\FSM_onehot_axi_full_sm_ps[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888888FFF8888"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[7]\,
I1 => s_axi4_bready,
I2 => s_axi4_awvalid,
I3 => s_axi4_wvalid,
I4 => axi_full_sm_ps_IDLE_cmb,
I5 => s_axi4_arvalid,
O => \FSM_onehot_axi_full_sm_ps[0]_i_2_n_0\
);
\FSM_onehot_axi_full_sm_ps[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF808080"
)
port map (
I0 => s_axi4_arvalid,
I1 => axi_full_sm_ps_IDLE_cmb,
I2 => burst_transfer_cmb,
I3 => I_DECODER_n_21,
I4 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
O => \FSM_onehot_axi_full_sm_ps[1]_i_1_n_0\
);
\FSM_onehot_axi_full_sm_ps[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => burst_transfer_cmb,
I1 => s_axi4_arvalid,
I2 => axi_full_sm_ps_IDLE_cmb,
I3 => s_axi_rvalid_i_reg_1,
I4 => \^q\(0),
O => \FSM_onehot_axi_full_sm_ps[2]_i_1_n_0\
);
\FSM_onehot_axi_full_sm_ps[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"EEEAAAAA"
)
port map (
I0 => \^q\(0),
I1 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
I2 => last_data_acked_i_6_n_0,
I3 => I_DECODER_n_24,
I4 => s_axi4_rready,
O => \^fsm_onehot_axi_full_sm_ps_reg[2]_0\
);
\FSM_onehot_axi_full_sm_ps[3]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55550004"
)
port map (
I0 => s_axi4_rready,
I1 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
I2 => last_data_acked_i_6_n_0,
I3 => I_DECODER_n_24,
I4 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[3]\,
O => \FSM_onehot_axi_full_sm_ps[3]_i_4_n_0\
);
\FSM_onehot_axi_full_sm_ps[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAEAAAAAAAAAAAAA"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps[4]_i_2_n_0\,
I1 => s_axi4_wvalid,
I2 => s_axi4_awvalid,
I3 => s_axi4_arvalid,
I4 => axi_full_sm_ps_IDLE_cmb,
I5 => burst_transfer_cmb,
O => \FSM_onehot_axi_full_sm_ps[4]_i_1_n_0\
);
\FSM_onehot_axi_full_sm_ps[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
I1 => almost_full,
I2 => s_axi4_wvalid,
I3 => I_DECODER_n_21,
O => \FSM_onehot_axi_full_sm_ps[4]_i_2_n_0\
);
\FSM_onehot_axi_full_sm_ps[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020FFFF00200020"
)
port map (
I0 => awready_i_i_3_n_0,
I1 => s_axi4_arvalid,
I2 => axi_full_sm_ps_IDLE_cmb,
I3 => burst_transfer_cmb,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I5 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
O => \FSM_onehot_axi_full_sm_ps[5]_i_1_n_0\
);
\FSM_onehot_axi_full_sm_ps[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F444"
)
port map (
I0 => I_DECODER_n_15,
I1 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I3 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
O => \FSM_onehot_axi_full_sm_ps[6]_i_1_n_0\
);
\FSM_onehot_axi_full_sm_ps[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[6]\,
I1 => s_axi4_bready,
I2 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[7]\,
O => \FSM_onehot_axi_full_sm_ps[7]_i_1_n_0\
);
\FSM_onehot_axi_full_sm_ps_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \FSM_onehot_axi_full_sm_ps[0]_i_1_n_0\,
Q => axi_full_sm_ps_IDLE_cmb,
S => \^sr\(0)
);
\FSM_onehot_axi_full_sm_ps_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \FSM_onehot_axi_full_sm_ps[1]_i_1_n_0\,
Q => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
R => \^sr\(0)
);
\FSM_onehot_axi_full_sm_ps_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \FSM_onehot_axi_full_sm_ps[2]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\(0)
);
\FSM_onehot_axi_full_sm_ps_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => I_DECODER_n_14,
Q => \FSM_onehot_axi_full_sm_ps_reg_n_0_[3]\,
R => \^sr\(0)
);
\FSM_onehot_axi_full_sm_ps_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \FSM_onehot_axi_full_sm_ps[4]_i_1_n_0\,
Q => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
R => \^sr\(0)
);
\FSM_onehot_axi_full_sm_ps_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \FSM_onehot_axi_full_sm_ps[5]_i_1_n_0\,
Q => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
R => \^sr\(0)
);
\FSM_onehot_axi_full_sm_ps_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \FSM_onehot_axi_full_sm_ps[6]_i_1_n_0\,
Q => \FSM_onehot_axi_full_sm_ps_reg_n_0_[6]\,
R => \^sr\(0)
);
\FSM_onehot_axi_full_sm_ps_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi4_aclk,
CE => '1',
D => \FSM_onehot_axi_full_sm_ps[7]_i_1_n_0\,
Q => \FSM_onehot_axi_full_sm_ps_reg_n_0_[7]\,
R => \^sr\(0)
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_address_decoder
port map (
Bus_RNW_reg_reg_0 => Bus_RNW_reg,
Bus_RNW_reg_reg_1 => Bus_RNW_reg_reg,
Bus_RNW_reg_reg_2(0) => Bus_RNW_reg_reg_0(0),
Bus_RNW_reg_reg_3 => Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_4 => \^ip2bus_error_int\,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
D(0) => I_DECODER_n_14,
\FSM_onehot_axi_full_sm_ps_reg[0]\ => I_DECODER_n_13,
\FSM_onehot_axi_full_sm_ps_reg[1]\(7 downto 0) => length_cntr_reg(7 downto 0),
\FSM_onehot_axi_full_sm_ps_reg[3]\ => \^fsm_onehot_axi_full_sm_ps_reg[2]_0\,
\FSM_onehot_axi_full_sm_ps_reg[3]_0\ => \FSM_onehot_axi_full_sm_ps_reg[3]_0\,
\FSM_onehot_axi_full_sm_ps_reg[3]_1\ => \FSM_onehot_axi_full_sm_ps[3]_i_4_n_0\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(5) => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(4) => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(3) => \FSM_onehot_axi_full_sm_ps_reg_n_0_[3]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(2) => \^q\(0),
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(1) => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\(0) => axi_full_sm_ps_IDLE_cmb,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_1\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_0\ => p_4_in,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]_1\ => \GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\,
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]_0\ => \GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_0\ => \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1\(2) => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/intr_ip2bus_data\(0),
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1\(1) => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/IP2Bus_SPICR_Data_int\(0),
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]_1\(0) => ip2bus_data_int(8),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\,
IP2Bus_WrAck_transmit_enable => IP2Bus_WrAck_transmit_enable,
Q(0) => bus2ip_be_int(3),
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => Transmit_ip2bus_error0,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_int => Tx_FIFO_Full_int,
almost_full => almost_full,
\bus2ip_BE_reg_reg[3]\ => \bus2ip_BE_reg_reg[3]_0\,
bus2ip_wrce_int(0) => bus2ip_wrce_int(0),
data_valid => data_valid,
empty => empty,
\guf.underflow_i_reg\ => s_axi_rvalid_i_i_2_n_0,
\gwack.wr_ack_i_reg\ => \^burst_tr_int\,
\gwack.wr_ack_i_reg_0\ => \xpm_fifo_instance.xpm_fifo_async_inst_i_4_n_0\,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg => ip2Bus_WrAck_core_reg,
ip2Bus_WrAck_core_reg0 => ip2Bus_WrAck_core_reg0,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
\ip_irpt_enable_reg_reg[1]\ => \ip_irpt_enable_reg_reg[1]\,
\ip_irpt_enable_reg_reg[2]\ => \ip_irpt_enable_reg_reg[2]\,
\ip_irpt_enable_reg_reg[3]\ => \ip_irpt_enable_reg_reg[3]\,
\ip_irpt_enable_reg_reg[4]\ => \ip_irpt_enable_reg_reg[4]\,
\ip_irpt_enable_reg_reg[5]\ => \ip_irpt_enable_reg_reg[5]\,
\ip_irpt_enable_reg_reg[6]\ => \ip_irpt_enable_reg_reg[6]\,
\ip_irpt_enable_reg_reg[7]\ => \ip_irpt_enable_reg_reg[7]\,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
last_data_acked_reg => last_data_acked_i_2_n_0,
last_data_acked_reg_0 => last_data_acked_i_3_n_0,
last_data_acked_reg_1 => last_data_acked_i_4_n_0,
last_data_acked_reg_2 => last_data_acked_i_5_n_0,
\length_cntr_reg[2]\ => I_DECODER_n_24,
\length_cntr_reg[6]\ => I_DECODER_n_21,
p_0_in(0) => p_0_in(0),
p_1_in => p_1_in,
p_1_in13_in => p_1_in13_in,
p_1_in16_in => p_1_in16_in,
p_1_in19_in => p_1_in19_in,
p_1_in22_in => p_1_in22_in,
p_1_in25_in => p_1_in25_in,
p_1_in28_in => p_1_in28_in,
p_1_in31_in => p_1_in31_in,
p_1_in34_in => p_1_in34_in,
p_2_in => p_2_in,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
rd_en => rd_en,
receive_ip2bus_error => receive_ip2bus_error,
reset2ip_reset_int => \^reset2ip_reset_int\,
reset_trig0 => reset_trig0,
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi4_aclk => s_axi4_aclk,
s_axi4_araddr(4 downto 0) => s_axi4_araddr(4 downto 0),
s_axi4_aresetn => s_axi4_aresetn,
s_axi4_arvalid => s_axi4_arvalid,
s_axi4_awaddr(4 downto 0) => s_axi4_awaddr(4 downto 0),
s_axi4_awvalid => s_axi4_awvalid,
\s_axi4_rdata_i_reg[8]\(8 downto 0) => \s_axi4_rdata_i_reg[8]_0\(8 downto 0),
s_axi4_rready => s_axi4_rready,
\s_axi4_rresp_i_reg[1]\ => \s_axi4_rresp_i[1]_i_2_n_0\,
s_axi4_wdata(5 downto 2) => s_axi4_wdata(6 downto 3),
s_axi4_wdata(1 downto 0) => s_axi4_wdata(1 downto 0),
\s_axi4_wdata[31]\ => \s_axi4_wdata[31]\,
s_axi4_wdata_0_sp_1 => s_axi4_wdata_0_sn_1,
s_axi4_wvalid => s_axi4_wvalid,
s_axi4_wvalid_0 => I_DECODER_n_15,
s_axi_wready_i => s_axi_wready_i,
scndry_out => scndry_out,
spicr_0_loop_frm_axi_clk => spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk => spicr_9_lsb_frm_axi_clk,
spisel_d1_reg_to_axi_clk => spisel_d1_reg_to_axi_clk,
start => start,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
transmit_ip2bus_error => transmit_ip2bus_error,
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
RESET_SYNC_AX2S_1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^sr\(0),
I1 => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\,
O => \^reset2ip_reset_int\
);
\S_AXI4_BRESP_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000ABA8"
)
port map (
I0 => \^ip2bus_error_int\,
I1 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
I2 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
I3 => \^s_axi4_bresp\(0),
I4 => axi_full_sm_ps_IDLE_cmb,
O => \S_AXI4_BRESP_i[1]_i_1_n_0\
);
\S_AXI4_BRESP_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \S_AXI4_BRESP_i[1]_i_1_n_0\,
Q => \^s_axi4_bresp\(0),
R => '0'
);
arready_i_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_full_sm_ps_IDLE_cmb,
I1 => s_axi4_arvalid,
O => arready_cmb
);
arready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => arready_cmb,
Q => s_axi4_arready,
R => \^sr\(0)
);
awready_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"88F8888888888888"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I1 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
I2 => awready_i_i_3_n_0,
I3 => s_axi4_arvalid,
I4 => axi_full_sm_ps_IDLE_cmb,
I5 => burst_transfer_cmb,
O => awready_cmb
);
awready_i_i_10: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => s_axi4_awvalid,
I1 => axi_full_sm_ps_IDLE_cmb,
I2 => s_axi4_arvalid,
O => awready_i_i_10_n_0
);
awready_i_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi4_awvalid,
I1 => s_axi4_wvalid,
O => awready_i_i_3_n_0
);
awready_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \length_cntr[3]_i_2_n_0\,
I1 => awready_i_i_5_n_0,
I2 => awready_i_i_6_n_0,
I3 => awready_i_i_7_n_0,
I4 => awready_i_i_8_n_0,
I5 => awready_i_i_9_n_0,
O => burst_transfer_cmb
);
awready_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBABBB8888A888"
)
port map (
I0 => s_axi4_arlen(2),
I1 => \length_cntr[7]_i_5_n_0\,
I2 => s_axi4_arvalid,
I3 => axi_full_sm_ps_IDLE_cmb,
I4 => s_axi4_awvalid,
I5 => s_axi4_awlen(2),
O => awready_i_i_5_n_0
);
awready_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBABBB8888A888"
)
port map (
I0 => s_axi4_arlen(5),
I1 => \length_cntr[7]_i_5_n_0\,
I2 => s_axi4_arvalid,
I3 => axi_full_sm_ps_IDLE_cmb,
I4 => s_axi4_awvalid,
I5 => s_axi4_awlen(5),
O => awready_i_i_6_n_0
);
awready_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBABBB8888A888"
)
port map (
I0 => s_axi4_arlen(0),
I1 => \length_cntr[7]_i_5_n_0\,
I2 => s_axi4_arvalid,
I3 => axi_full_sm_ps_IDLE_cmb,
I4 => s_axi4_awvalid,
I5 => s_axi4_awlen(0),
O => awready_i_i_7_n_0
);
awready_i_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFACCCCCCFA"
)
port map (
I0 => s_axi4_awlen(4),
I1 => s_axi4_arlen(4),
I2 => s_axi4_awlen(1),
I3 => awready_i_i_10_n_0,
I4 => \length_cntr[7]_i_5_n_0\,
I5 => s_axi4_arlen(1),
O => awready_i_i_8_n_0
);
awready_i_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFACCCCCCFA"
)
port map (
I0 => s_axi4_awlen(7),
I1 => s_axi4_arlen(7),
I2 => s_axi4_awlen(6),
I3 => awready_i_i_10_n_0,
I4 => \length_cntr[7]_i_5_n_0\,
I5 => s_axi4_arlen(6),
O => awready_i_i_9_n_0
);
awready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => awready_cmb,
Q => s_axi4_awready,
R => \^sr\(0)
);
burst_transfer_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"E200"
)
port map (
I0 => \^burst_tr_int\,
I1 => start,
I2 => burst_transfer_cmb,
I3 => s_axi4_aresetn,
O => burst_transfer_reg_i_1_n_0
);
burst_transfer_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => burst_transfer_reg_i_1_n_0,
Q => \^burst_tr_int\,
R => '0'
);
\bus2ip_BE_reg[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi4_wstrb(0),
I1 => rnw_cmb,
O => \bus2ip_BE_reg[0]_i_1_n_0\
);
\bus2ip_BE_reg[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_axi4_wstrb(1),
I1 => rnw_cmb,
O => \bus2ip_BE_reg[3]_i_1_n_0\
);
\bus2ip_BE_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \bus2ip_BE_reg[0]_i_1_n_0\,
Q => bus2ip_be_int(0),
R => \^sr\(0)
);
\bus2ip_BE_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \bus2ip_BE_reg[3]_i_1_n_0\,
Q => bus2ip_be_int(3),
R => \^sr\(0)
);
last_data_acked_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi4_rready,
I1 => \^s_axi4_rlast\,
O => last_data_acked_i_2_n_0
);
last_data_acked_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => last_data_acked_i_6_n_0,
I1 => last_data_acked_i_7_n_0,
I2 => length_cntr_reg(0),
I3 => length_cntr_reg(1),
I4 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
I5 => \^burst_tr_int\,
O => last_data_acked_i_3_n_0
);
last_data_acked_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^burst_tr_int\,
I1 => length_cntr_reg(4),
I2 => length_cntr_reg(7),
I3 => length_cntr_reg(5),
I4 => length_cntr_reg(6),
I5 => I_DECODER_n_24,
O => last_data_acked_i_4_n_0
);
last_data_acked_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => s_axi4_rready,
I1 => \^s_axi4_rlast\,
I2 => \^burst_tr_int\,
O => last_data_acked_i_5_n_0
);
last_data_acked_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => length_cntr_reg(4),
I1 => length_cntr_reg(7),
I2 => length_cntr_reg(5),
I3 => length_cntr_reg(6),
O => last_data_acked_i_6_n_0
);
last_data_acked_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"EFFF"
)
port map (
I0 => length_cntr_reg(2),
I1 => length_cntr_reg(3),
I2 => \^s_axi_rvalid_i_reg_0\,
I3 => s_axi4_rready,
O => last_data_acked_i_7_n_0
);
last_data_acked_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => I_DECODER_n_13,
Q => \^s_axi4_rlast\,
R => '0'
);
\length_cntr[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B800B8FF"
)
port map (
I0 => s_axi4_arlen(0),
I1 => rnw_cmb,
I2 => s_axi4_awlen(0),
I3 => start,
I4 => length_cntr_reg(0),
O => \p_0_in__0\(0)
);
\length_cntr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => s_axi4_arlen(1),
I1 => rnw_cmb,
I2 => s_axi4_awlen(1),
I3 => start,
I4 => length_cntr_reg(1),
I5 => length_cntr_reg(0),
O => \p_0_in__0\(1)
);
\length_cntr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => s_axi4_arlen(2),
I1 => rnw_cmb,
I2 => s_axi4_awlen(2),
I3 => start,
I4 => length_cntr_reg(2),
I5 => \length_cntr[2]_i_2_n_0\,
O => \p_0_in__0\(2)
);
\length_cntr[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => length_cntr_reg(1),
I1 => length_cntr_reg(0),
O => \length_cntr[2]_i_2_n_0\
);
\length_cntr[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => \length_cntr[3]_i_2_n_0\,
I1 => start,
I2 => length_cntr_reg(3),
I3 => length_cntr_reg(2),
I4 => length_cntr_reg(1),
I5 => length_cntr_reg(0),
O => \p_0_in__0\(3)
);
\length_cntr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBABBB8888A888"
)
port map (
I0 => s_axi4_arlen(3),
I1 => \length_cntr[7]_i_5_n_0\,
I2 => s_axi4_arvalid,
I3 => axi_full_sm_ps_IDLE_cmb,
I4 => s_axi4_awvalid,
I5 => s_axi4_awlen(3),
O => \length_cntr[3]_i_2_n_0\
);
\length_cntr[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => s_axi4_arlen(4),
I1 => rnw_cmb,
I2 => s_axi4_awlen(4),
I3 => start,
I4 => length_cntr_reg(4),
I5 => I_DECODER_n_24,
O => \p_0_in__0\(4)
);
\length_cntr[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => s_axi4_arlen(5),
I1 => rnw_cmb,
I2 => s_axi4_awlen(5),
I3 => start,
I4 => length_cntr_reg(5),
I5 => \length_cntr[7]_i_4_n_0\,
O => \p_0_in__0\(5)
);
\length_cntr[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => s_axi4_arlen(6),
I1 => rnw_cmb,
I2 => s_axi4_awlen(6),
I3 => start,
I4 => length_cntr_reg(6),
I5 => \length_cntr[6]_i_2_n_0\,
O => \p_0_in__0\(6)
);
\length_cntr[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => length_cntr_reg(2),
I1 => length_cntr_reg(3),
I2 => length_cntr_reg(0),
I3 => length_cntr_reg(1),
I4 => length_cntr_reg(4),
I5 => length_cntr_reg(5),
O => \length_cntr[6]_i_2_n_0\
);
\length_cntr[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => s_axi4_rready,
I1 => \^s_axi_rvalid_i_reg_0\,
I2 => start,
I3 => \xpm_fifo_instance.xpm_fifo_async_inst_i_4_n_0\,
O => \length_cntr[7]_i_1_n_0\
);
\length_cntr[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B88BB8"
)
port map (
I0 => \length_cntr[7]_i_3_n_0\,
I1 => start,
I2 => length_cntr_reg(7),
I3 => \length_cntr[7]_i_4_n_0\,
I4 => length_cntr_reg(6),
I5 => length_cntr_reg(5),
O => \p_0_in__0\(7)
);
\length_cntr[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBABBB8888A888"
)
port map (
I0 => s_axi4_arlen(7),
I1 => \length_cntr[7]_i_5_n_0\,
I2 => s_axi4_arvalid,
I3 => axi_full_sm_ps_IDLE_cmb,
I4 => s_axi4_awvalid,
I5 => s_axi4_awlen(7),
O => \length_cntr[7]_i_3_n_0\
);
\length_cntr[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => length_cntr_reg(4),
I1 => length_cntr_reg(1),
I2 => length_cntr_reg(0),
I3 => length_cntr_reg(3),
I4 => length_cntr_reg(2),
O => \length_cntr[7]_i_4_n_0\
);
\length_cntr[7]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => rnw_reg_reg_n_0,
I1 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
I2 => \^q\(0),
I3 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
I4 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
O => \length_cntr[7]_i_5_n_0\
);
\length_cntr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \length_cntr[7]_i_1_n_0\,
D => \p_0_in__0\(0),
Q => length_cntr_reg(0),
R => clear
);
\length_cntr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \length_cntr[7]_i_1_n_0\,
D => \p_0_in__0\(1),
Q => length_cntr_reg(1),
R => clear
);
\length_cntr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \length_cntr[7]_i_1_n_0\,
D => \p_0_in__0\(2),
Q => length_cntr_reg(2),
R => clear
);
\length_cntr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \length_cntr[7]_i_1_n_0\,
D => \p_0_in__0\(3),
Q => length_cntr_reg(3),
R => clear
);
\length_cntr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \length_cntr[7]_i_1_n_0\,
D => \p_0_in__0\(4),
Q => length_cntr_reg(4),
R => clear
);
\length_cntr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \length_cntr[7]_i_1_n_0\,
D => \p_0_in__0\(5),
Q => length_cntr_reg(5),
R => clear
);
\length_cntr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \length_cntr[7]_i_1_n_0\,
D => \p_0_in__0\(6),
Q => length_cntr_reg(6),
R => clear
);
\length_cntr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => \length_cntr[7]_i_1_n_0\,
D => \p_0_in__0\(7),
Q => length_cntr_reg(7),
R => clear
);
rnw_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FD00FD00FD00FFFF"
)
port map (
I0 => rnw_reg_i_2_n_0,
I1 => \^q\(0),
I2 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
I3 => rnw_reg_reg_n_0,
I4 => rnw_reg_i_3_n_0,
I5 => s_axi4_awvalid,
O => rnw_cmb
);
rnw_reg_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
I1 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
O => rnw_reg_i_2_n_0
);
rnw_reg_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi4_arvalid,
I1 => axi_full_sm_ps_IDLE_cmb,
O => rnw_reg_i_3_n_0
);
rnw_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => rnw_cmb,
Q => rnw_reg_reg_n_0,
R => \^sr\(0)
);
\s_axi4_rdata_i[31]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi4_aresetn,
O => clear
);
\s_axi4_rdata_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => D(0),
Q => s_axi4_rdata(0),
R => clear
);
\s_axi4_rdata_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => D(1),
Q => s_axi4_rdata(1),
R => clear
);
\s_axi4_rdata_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => D(2),
Q => s_axi4_rdata(2),
R => clear
);
\s_axi4_rdata_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/intr_ip2bus_data\(0),
Q => s_axi4_rdata(10),
R => clear
);
\s_axi4_rdata_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => D(3),
Q => s_axi4_rdata(3),
R => clear
);
\s_axi4_rdata_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => D(4),
Q => s_axi4_rdata(4),
R => clear
);
\s_axi4_rdata_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => D(5),
Q => s_axi4_rdata(5),
R => clear
);
\s_axi4_rdata_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => D(6),
Q => s_axi4_rdata(6),
R => clear
);
\s_axi4_rdata_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => D(7),
Q => s_axi4_rdata(7),
R => clear
);
\s_axi4_rdata_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => ip2bus_data_int(8),
Q => s_axi4_rdata(8),
R => clear
);
\s_axi4_rdata_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I/IP2Bus_SPICR_Data_int\(0),
Q => s_axi4_rdata(9),
R => clear
);
\s_axi4_rresp_i[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFDFFF"
)
port map (
I0 => bus2ip_be_int(0),
I1 => s_axi4_wdata(0),
I2 => s_axi4_wdata(3),
I3 => s_axi4_wdata(1),
I4 => s_axi4_wdata(2),
O => \s_axi4_rresp_i[1]_i_2_n_0\
);
\s_axi4_rresp_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => E(0),
D => \^ip2bus_error_int\,
Q => s_axi4_rresp(0),
R => clear
);
s_axi4_wready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"72"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
I1 => almost_full,
I2 => s_axi_wready_i,
O => s_axi4_wready
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F200"
)
port map (
I0 => \^s_axi4_bvalid\,
I1 => s_axi4_bready,
I2 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[6]\,
I3 => s_axi4_aresetn,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi4_bvalid\,
R => '0'
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF222F"
)
port map (
I0 => \^s_axi_rvalid_i_reg_0\,
I1 => s_axi4_rready,
I2 => s_axi_rvalid_i_reg_1,
I3 => s_axi_rvalid_i_i_2_n_0,
I4 => I_DECODER_n_14,
I5 => axi_full_sm_ps_IDLE_cmb,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555557"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[1]\,
I1 => length_cntr_reg(4),
I2 => length_cntr_reg(7),
I3 => length_cntr_reg(5),
I4 => length_cntr_reg(6),
I5 => I_DECODER_n_24,
O => s_axi_rvalid_i_i_2_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid_i_reg_0\,
R => '0'
);
s_axi_wready_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF8F8800000000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I1 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[5]\,
I2 => s_axi_wready_i_i_2_n_0,
I3 => burst_transfer_cmb,
I4 => \FSM_onehot_axi_full_sm_ps[4]_i_2_n_0\,
I5 => s_axi4_aresetn,
O => s_axi_wready_i_i_1_n_0
);
s_axi_wready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F7FF"
)
port map (
I0 => s_axi4_wvalid,
I1 => s_axi4_awvalid,
I2 => s_axi4_arvalid,
I3 => axi_full_sm_ps_IDLE_cmb,
O => s_axi_wready_i_i_2_n_0
);
s_axi_wready_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => s_axi_wready_i_i_1_n_0,
Q => s_axi_wready_i,
R => '0'
);
\xpm_fifo_instance.xpm_fifo_async_inst_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"8DFF"
)
port map (
I0 => \FSM_onehot_axi_full_sm_ps_reg_n_0_[4]\,
I1 => almost_full,
I2 => s_axi_wready_i,
I3 => s_axi4_wvalid,
O => \xpm_fifo_instance.xpm_fifo_async_inst_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst is
port (
\gen_rst_ic.fifo_rd_rst_ic_reg_0\ : out STD_LOGIC;
wrst_busy : out STD_LOGIC;
d_out_reg : out STD_LOGIC;
wr_pntr_plus1_pf_carry : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
underflow_i0 : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
\gwack.wr_ack_i_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\guf.underflow_i_reg\ : in STD_LOGIC;
rd_en : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst is
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes";
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes";
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes";
signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes";
signal \gen_rst_ic.fifo_rd_rst_i\ : STD_LOGIC;
signal \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ : STD_LOGIC;
signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC;
signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC;
signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC;
signal \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ : STD_LOGIC;
signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC;
signal \gen_rst_ic.next_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC;
signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC;
signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC;
signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC;
signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
signal \rst_i__0\ : STD_LOGIC;
signal \^wrst_busy\ : STD_LOGIC;
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11";
attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11";
attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_rst_ic.fifo_wr_rst_ic_i_2\ : label is "soft_lutpair69";
attribute DEF_VAL : string;
attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 2;
attribute INIT : string;
attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0;
attribute VERSION : integer;
attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0;
attribute XPM_CDC : string;
attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST";
attribute XPM_MODULE : string;
attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE";
attribute SOFT_HLUTNM of \gen_rst_ic.rst_seq_reentered_i_1\ : label is "soft_lutpair69";
attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0";
attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 2;
attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0";
attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1;
attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0;
attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0;
attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST";
attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE";
attribute SOFT_HLUTNM of \grdc.rd_data_count_i[8]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \guf.underflow_i_i_1\ : label is "soft_lutpair70";
begin
\gen_rst_ic.fifo_rd_rst_ic_reg_0\ <= \^gen_rst_ic.fifo_rd_rst_ic_reg_0\;
wrst_busy <= \^wrst_busy\;
\/i_\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010116"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
O => \/i__n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"03030200FFFFFFFF"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I1 => p_0_in,
I2 => rst,
I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I5 => \/i__n_0\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEEE"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I3 => rst,
I4 => p_0_in,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0EEE0FFFFEEE0"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I2 => rst,
I3 => p_0_in,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I5 => \gen_rst_ic.fifo_rd_rst_wr_i\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000C0008"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I1 => \gen_rst_ic.fifo_rd_rst_wr_i\,
I2 => rst,
I3 => p_0_in,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004400000044"
)
port map (
I0 => \gen_rst_ic.fifo_rd_rst_wr_i\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I2 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
I3 => rst,
I4 => p_0_in,
I5 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \/i__n_0\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I1 => p_0_in,
I2 => rst,
I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
R => '0'
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gen_rst_ic.curr_rrst_state\(0),
I1 => \gen_rst_ic.curr_rrst_state\(1),
O => \gen_rst_ic.next_rrst_state\(1)
);
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_rst_ic.next_rrst_state\(0),
Q => \gen_rst_ic.curr_rrst_state\(0),
R => '0'
);
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_rst_ic.next_rrst_state\(1),
Q => \gen_rst_ic.curr_rrst_state\(1),
R => '0'
);
\__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => \gen_rst_ic.fifo_wr_rst_rd\,
I1 => \gen_rst_ic.curr_rrst_state\(1),
I2 => \gen_rst_ic.curr_rrst_state\(0),
O => \gen_rst_ic.next_rrst_state\(0)
);
\gen_rst_ic.fifo_rd_rst_ic_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3E"
)
port map (
I0 => \gen_rst_ic.fifo_wr_rst_rd\,
I1 => \gen_rst_ic.curr_rrst_state\(1),
I2 => \gen_rst_ic.curr_rrst_state\(0),
O => \gen_rst_ic.fifo_rd_rst_i\
);
\gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_rst_ic.fifo_rd_rst_i\,
Q => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\,
R => '0'
);
\gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAFFFFFFEA0000"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I2 => \rst_i__0\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I4 => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\,
I5 => \gen_rst_ic.fifo_wr_rst_ic\,
O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\
);
\gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in,
I1 => rst,
O => \rst_i__0\
);
\gen_rst_ic.fifo_wr_rst_ic_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010116"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
O => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\
);
\gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\,
Q => \gen_rst_ic.fifo_wr_rst_ic\,
R => '0'
);
\gen_rst_ic.rrst_wr_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst
port map (
dest_clk => wr_clk,
dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\,
src_rst => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\
);
\gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\,
I1 => rst,
I2 => p_0_in,
O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\
);
\gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00010000"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
I5 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\
);
\gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\,
Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
R => '0'
);
\gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFEF00"
)
port map (
I0 => rst,
I1 => p_0_in,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\,
I4 => \^wrst_busy\,
O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\
);
\gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000116"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\
);
\gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\,
Q => \^wrst_busy\,
R => '0'
);
\gen_rst_ic.wrst_rd_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__6\
port map (
dest_clk => rd_clk,
dest_rst => \gen_rst_ic.fifo_wr_rst_rd\,
src_rst => \gen_rst_ic.fifo_wr_rst_ic\
);
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => wr_en,
I1 => \gwack.wr_ack_i_reg\,
I2 => \^wrst_busy\,
I3 => rst_d1,
O => wr_pntr_plus1_pf_carry
);
\grdc.rd_data_count_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\,
I1 => Q(0),
I2 => Q(1),
O => SR(0)
);
\guf.underflow_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E0"
)
port map (
I0 => \guf.underflow_i_reg\,
I1 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\,
I2 => rd_en,
O => underflow_i0
);
\gwack.wr_ack_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => rst_d1,
I1 => \gwack.wr_ack_i_reg\,
I2 => wr_en,
I3 => \^wrst_busy\,
I4 => \gen_rst_ic.fifo_wr_rst_ic\,
I5 => rst,
O => d_out_reg
);
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
Q => \power_on_rst_reg_n_0_[0]\,
R => '0'
);
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \power_on_rst_reg_n_0_[0]\,
Q => p_0_in,
R => '0'
);
wr_rst_busy_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^wrst_busy\,
I1 => rst_d1,
O => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\ is
port (
\gen_rst_ic.fifo_rd_rst_ic_reg_0\ : out STD_LOGIC;
wrst_busy : out STD_LOGIC;
d_out_reg : out STD_LOGIC;
wr_pntr_plus1_pf_carry : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
underflow_i0 : out STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rst_d1 : in STD_LOGIC;
\gwack.wr_ack_i_reg\ : in STD_LOGIC;
wr_en : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
\guf.underflow_i_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\ : entity is "xpm_fifo_rst";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\ is
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\ : signal is "yes";
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\ : signal is "yes";
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\ : signal is "yes";
signal \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\ : signal is "yes";
signal \gen_rst_ic.curr_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \gen_rst_ic.curr_rrst_state\ : signal is "yes";
signal \gen_rst_ic.fifo_rd_rst_i\ : STD_LOGIC;
signal \^gen_rst_ic.fifo_rd_rst_ic_reg_0\ : STD_LOGIC;
signal \gen_rst_ic.fifo_rd_rst_wr_i\ : STD_LOGIC;
signal \gen_rst_ic.fifo_wr_rst_ic\ : STD_LOGIC;
signal \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\ : STD_LOGIC;
signal \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\ : STD_LOGIC;
signal \gen_rst_ic.fifo_wr_rst_rd\ : STD_LOGIC;
signal \gen_rst_ic.next_rrst_state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \gen_rst_ic.rst_seq_reentered_i_1_n_0\ : STD_LOGIC;
signal \gen_rst_ic.rst_seq_reentered_i_2_n_0\ : STD_LOGIC;
signal \gen_rst_ic.rst_seq_reentered_reg_n_0\ : STD_LOGIC;
signal \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\ : STD_LOGIC;
signal \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal \power_on_rst_reg_n_0_[0]\ : STD_LOGIC;
signal \rst_i__0\ : STD_LOGIC;
signal \^wrst_busy\ : STD_LOGIC;
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001";
attribute KEEP of \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11";
attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "RRST_IDLE:00,RRST_IN:01,RRST_OUT:10,RRST_EXIT:11";
attribute KEEP of \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_rst_ic.fifo_wr_rst_ic_i_2\ : label is "soft_lutpair32";
attribute DEF_VAL : string;
attribute DEF_VAL of \gen_rst_ic.rrst_wr_inst\ : label is "1'b0";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 2;
attribute INIT : string;
attribute INIT of \gen_rst_ic.rrst_wr_inst\ : label is "0";
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \gen_rst_ic.rrst_wr_inst\ : label is 1;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \gen_rst_ic.rrst_wr_inst\ : label is 0;
attribute VERSION : integer;
attribute VERSION of \gen_rst_ic.rrst_wr_inst\ : label is 0;
attribute XPM_CDC : string;
attribute XPM_CDC of \gen_rst_ic.rrst_wr_inst\ : label is "SYNC_RST";
attribute XPM_MODULE : string;
attribute XPM_MODULE of \gen_rst_ic.rrst_wr_inst\ : label is "TRUE";
attribute SOFT_HLUTNM of \gen_rst_ic.rst_seq_reentered_i_1\ : label is "soft_lutpair32";
attribute DEF_VAL of \gen_rst_ic.wrst_rd_inst\ : label is "1'b0";
attribute DEST_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 2;
attribute INIT of \gen_rst_ic.wrst_rd_inst\ : label is "0";
attribute INIT_SYNC_FF of \gen_rst_ic.wrst_rd_inst\ : label is 1;
attribute SIM_ASSERT_CHK of \gen_rst_ic.wrst_rd_inst\ : label is 0;
attribute VERSION of \gen_rst_ic.wrst_rd_inst\ : label is 0;
attribute XPM_CDC of \gen_rst_ic.wrst_rd_inst\ : label is "SYNC_RST";
attribute XPM_MODULE of \gen_rst_ic.wrst_rd_inst\ : label is "TRUE";
attribute SOFT_HLUTNM of \grdc.rd_data_count_i[8]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \guf.underflow_i_i_1\ : label is "soft_lutpair31";
begin
\gen_rst_ic.fifo_rd_rst_ic_reg_0\ <= \^gen_rst_ic.fifo_rd_rst_ic_reg_0\;
wrst_busy <= \^wrst_busy\;
\/i_\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010116"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
O => \/i__n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"03030200FFFFFFFF"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I1 => p_0_in,
I2 => rst,
I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I5 => \/i__n_0\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEEE"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I3 => rst,
I4 => p_0_in,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFF0EEE0FFFFEEE0"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I2 => rst,
I3 => p_0_in,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I5 => \gen_rst_ic.fifo_rd_rst_wr_i\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000C0008"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I1 => \gen_rst_ic.fifo_rd_rst_wr_i\,
I2 => rst,
I3 => p_0_in,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004400000044"
)
port map (
I0 => \gen_rst_ic.fifo_rd_rst_wr_i\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I2 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
I3 => rst,
I4 => p_0_in,
I5 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \/i__n_0\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I1 => p_0_in,
I2 => rst,
I3 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
O => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
R => '0'
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0\,
Q => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
R => \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0\
);
\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gen_rst_ic.curr_rrst_state\(0),
I1 => \gen_rst_ic.curr_rrst_state\(1),
O => \gen_rst_ic.next_rrst_state\(1)
);
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_rst_ic.next_rrst_state\(0),
Q => \gen_rst_ic.curr_rrst_state\(0),
R => '0'
);
\FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_rst_ic.next_rrst_state\(1),
Q => \gen_rst_ic.curr_rrst_state\(1),
R => '0'
);
\__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"06"
)
port map (
I0 => \gen_rst_ic.fifo_wr_rst_rd\,
I1 => \gen_rst_ic.curr_rrst_state\(1),
I2 => \gen_rst_ic.curr_rrst_state\(0),
O => \gen_rst_ic.next_rrst_state\(0)
);
\gen_rst_ic.fifo_rd_rst_ic_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3E"
)
port map (
I0 => \gen_rst_ic.fifo_wr_rst_rd\,
I1 => \gen_rst_ic.curr_rrst_state\(1),
I2 => \gen_rst_ic.curr_rrst_state\(0),
O => \gen_rst_ic.fifo_rd_rst_i\
);
\gen_rst_ic.fifo_rd_rst_ic_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_rst_ic.fifo_rd_rst_i\,
Q => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\,
R => '0'
);
\gen_rst_ic.fifo_wr_rst_ic_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEAFFFFFFEA0000"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I2 => \rst_i__0\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I4 => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\,
I5 => \gen_rst_ic.fifo_wr_rst_ic\,
O => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\
);
\gen_rst_ic.fifo_wr_rst_ic_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => p_0_in,
I1 => rst,
O => \rst_i__0\
);
\gen_rst_ic.fifo_wr_rst_ic_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00010116"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
O => \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0\
);
\gen_rst_ic.fifo_wr_rst_ic_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0\,
Q => \gen_rst_ic.fifo_wr_rst_ic\,
R => '0'
);
\gen_rst_ic.rrst_wr_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__5\
port map (
dest_clk => wr_clk,
dest_rst => \gen_rst_ic.fifo_rd_rst_wr_i\,
src_rst => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\
);
\gen_rst_ic.rst_seq_reentered_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \gen_rst_ic.rst_seq_reentered_i_2_n_0\,
I1 => rst,
I2 => p_0_in,
O => \gen_rst_ic.rst_seq_reentered_i_1_n_0\
);
\gen_rst_ic.rst_seq_reentered_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00010000"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
I5 => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
O => \gen_rst_ic.rst_seq_reentered_i_2_n_0\
);
\gen_rst_ic.rst_seq_reentered_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_ic.rst_seq_reentered_i_1_n_0\,
Q => \gen_rst_ic.rst_seq_reentered_reg_n_0\,
R => '0'
);
\gen_rst_ic.wr_rst_busy_ic_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFFEF00"
)
port map (
I0 => rst,
I1 => p_0_in,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I3 => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\,
I4 => \^wrst_busy\,
O => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\
);
\gen_rst_ic.wr_rst_busy_ic_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000116"
)
port map (
I0 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3]\,
I1 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2]\,
I2 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1]\,
I3 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0]\,
I4 => \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4]\,
O => \gen_rst_ic.wr_rst_busy_ic_i_2_n_0\
);
\gen_rst_ic.wr_rst_busy_ic_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_rst_ic.wr_rst_busy_ic_i_1_n_0\,
Q => \^wrst_busy\,
R => '0'
);
\gen_rst_ic.wrst_rd_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_sync_rst__4\
port map (
dest_clk => rd_clk,
dest_rst => \gen_rst_ic.fifo_wr_rst_rd\,
src_rst => \gen_rst_ic.fifo_wr_rst_ic\
);
\gen_sdpram.xpm_memory_base_inst_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => wr_en,
I1 => \gwack.wr_ack_i_reg\,
I2 => \^wrst_busy\,
I3 => rst_d1,
O => wr_pntr_plus1_pf_carry
);
\grdc.rd_data_count_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\,
I1 => Q(1),
I2 => Q(0),
O => SR(0)
);
\guf.underflow_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => rd_en,
I1 => \guf.underflow_i_reg\,
I2 => \^gen_rst_ic.fifo_rd_rst_ic_reg_0\,
O => underflow_i0
);
\gwack.wr_ack_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => rst_d1,
I1 => \gwack.wr_ack_i_reg\,
I2 => wr_en,
I3 => \^wrst_busy\,
I4 => \gen_rst_ic.fifo_wr_rst_ic\,
I5 => rst,
O => d_out_reg
);
\power_on_rst_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
Q => \power_on_rst_reg_n_0_[0]\,
R => '0'
);
\power_on_rst_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \power_on_rst_reg_n_0_[0]\,
Q => p_0_in,
R => '0'
);
wr_rst_busy_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^wrst_busy\,
I1 => rst_d1,
O => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base is
port (
sleep : in STD_LOGIC;
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
full_n : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
overflow : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
underflow : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
almost_empty : out STD_LOGIC;
data_valid : out STD_LOGIC;
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC
);
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute CDC_DEST_SYNC_FF : integer;
attribute CDC_DEST_SYNC_FF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2;
attribute COMMON_CLOCK : integer;
attribute COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "0";
attribute ECC_MODE : integer;
attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute ENABLE_ECC : integer;
attribute ENABLE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute EN_ADV_FEATURE : string;
attribute EN_ADV_FEATURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "16'b0001111100011111";
attribute EN_AE : string;
attribute EN_AE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_AF : string;
attribute EN_AF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_DVLD : string;
attribute EN_DVLD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_OF : string;
attribute EN_OF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_PE : string;
attribute EN_PE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_PF : string;
attribute EN_PF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_RDC : string;
attribute EN_RDC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_UF : string;
attribute EN_UF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_WACK : string;
attribute EN_WACK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute EN_WDC : string;
attribute EN_WDC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b1";
attribute FG_EQ_ASYM_DOUT : string;
attribute FG_EQ_ASYM_DOUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute FIFO_MEMORY_TYPE : integer;
attribute FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute FIFO_MEM_TYPE : integer;
attribute FIFO_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute FIFO_READ_DEPTH : integer;
attribute FIFO_READ_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 256;
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute FIFO_SIZE : integer;
attribute FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2048;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 256;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute FULL_RST_VAL : string;
attribute FULL_RST_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1'b0";
attribute PE_THRESH_ADJ : integer;
attribute PE_THRESH_ADJ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8;
attribute PE_THRESH_MAX : integer;
attribute PE_THRESH_MAX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 251;
attribute PE_THRESH_MIN : integer;
attribute PE_THRESH_MIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 5;
attribute PF_THRESH_ADJ : integer;
attribute PF_THRESH_ADJ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8;
attribute PF_THRESH_MAX : integer;
attribute PF_THRESH_MAX of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 251;
attribute PF_THRESH_MIN : integer;
attribute PF_THRESH_MIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 7;
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 10;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 9;
attribute RD_DC_WIDTH_EXT : integer;
attribute RD_DC_WIDTH_EXT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 9;
attribute RD_LATENCY : integer;
attribute RD_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2;
attribute RD_MODE : integer;
attribute RD_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute RD_PNTR_WIDTH : integer;
attribute RD_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8;
attribute READ_MODE : integer;
attribute READ_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute READ_MODE_LL : integer;
attribute READ_MODE_LL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute REMOVE_WR_RD_PROT_LOGIC : integer;
attribute REMOVE_WR_RD_PROT_LOGIC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "1f1f";
attribute VERSION : integer;
attribute VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute WIDTH_RATIO : integer;
attribute WIDTH_RATIO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 9;
attribute WR_DC_WIDTH_EXT : integer;
attribute WR_DC_WIDTH_EXT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 9;
attribute WR_DEPTH_LOG : integer;
attribute WR_DEPTH_LOG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8;
attribute WR_PNTR_WIDTH : integer;
attribute WR_PNTR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 8;
attribute WR_RD_RATIO : integer;
attribute WR_RD_RATIO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute WR_WIDTH_LOG : integer;
attribute WR_WIDTH_LOG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 3;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "TRUE";
attribute both_stages_valid : integer;
attribute both_stages_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 3;
attribute invalid : integer;
attribute invalid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 0;
attribute keep_hierarchy : string;
attribute keep_hierarchy of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is "soft";
attribute stage1_valid : integer;
attribute stage1_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 2;
attribute stage2_valid : integer;
attribute stage2_valid of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base is
signal \<const0>\ : STD_LOGIC;
signal aempty_fwft_i0 : STD_LOGIC;
signal \^almost_empty\ : STD_LOGIC;
signal \^almost_full\ : STD_LOGIC;
signal count_value_i : STD_LOGIC_VECTOR ( 7 downto 0 );
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal data_valid_fwft1 : STD_LOGIC;
signal diff_pntr_pe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 8 downto 4 );
signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 8 downto 4 );
signal \^empty\ : STD_LOGIC;
signal \^full\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_6\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_7\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_8\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_n_0\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_0\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_1\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_2\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_3\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_4\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_5\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_6\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_7\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_8\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_0\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_1\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_10\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_11\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_12\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_13\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_14\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_15\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_2\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_3\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_9\ : STD_LOGIC;
signal \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\ : STD_LOGIC;
signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_0\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_1\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_2\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_3\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_4\ : STD_LOGIC;
signal \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ : STD_LOGIC;
signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \grdc.rd_data_count_i0\ : STD_LOGIC;
signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal overflow_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal ram_empty_i : STD_LOGIC;
signal ram_empty_i0 : STD_LOGIC;
signal ram_full_i0 : STD_LOGIC;
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_ext : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_pntr_wr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^rd_rst_busy\ : STD_LOGIC;
signal rdp_inst_n_11 : STD_LOGIC;
signal rdp_inst_n_12 : STD_LOGIC;
signal rdp_inst_n_13 : STD_LOGIC;
signal rdp_inst_n_14 : STD_LOGIC;
signal rdp_inst_n_15 : STD_LOGIC;
signal rdp_inst_n_18 : STD_LOGIC;
signal rdp_inst_n_27 : STD_LOGIC;
signal rdp_inst_n_28 : STD_LOGIC;
signal rdp_inst_n_29 : STD_LOGIC;
signal rdp_inst_n_30 : STD_LOGIC;
signal rdp_inst_n_31 : STD_LOGIC;
signal rdp_inst_n_32 : STD_LOGIC;
signal rdpp1_inst_n_1 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d1_inst_n_1 : STD_LOGIC;
signal rst_d1_inst_n_3 : STD_LOGIC;
signal src_in_bin00_out : STD_LOGIC_VECTOR ( 8 downto 0 );
signal underflow_i0 : STD_LOGIC;
signal wr_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 8 downto 1 );
signal wr_pntr_plus1_pf_carry : STD_LOGIC;
signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wrpp2_inst_n_0 : STD_LOGIC;
signal wrpp2_inst_n_1 : STD_LOGIC;
signal wrpp2_inst_n_2 : STD_LOGIC;
signal wrpp2_inst_n_3 : STD_LOGIC;
signal wrpp2_inst_n_4 : STD_LOGIC;
signal wrpp2_inst_n_5 : STD_LOGIC;
signal wrpp2_inst_n_6 : STD_LOGIC;
signal wrpp2_inst_n_7 : STD_LOGIC;
signal wrst_busy : STD_LOGIC;
signal xpm_fifo_rst_inst_n_2 : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair33";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1;
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
attribute WIDTH : integer;
attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 9;
attribute XPM_CDC : string;
attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY";
attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE";
attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 2;
attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1;
attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 8;
attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY";
attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE";
attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 4;
attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1;
attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 9;
attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY";
attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE";
attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 2;
attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1;
attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 8;
attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY";
attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE";
attribute SOFT_HLUTNM of \gen_fwft.gdvld_fwft.data_valid_fwft_i_1\ : label is "soft_lutpair33";
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute IGNORE_INIT_SYNTH : integer;
attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of \gen_sdpram.xpm_memory_base_inst\ : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 7;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 1023;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
attribute MEMORY_OPTIMIZATION : string;
attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 2048;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 256;
attribute P_MEMORY_OPT : string;
attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
attribute RST_MODE_A : string;
attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
attribute RST_MODE_B : string;
attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_EMBEDDED_CONSTRAINT : integer;
attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_MEM_INIT_MMI : integer;
attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute WRITE_PROTECT : integer;
attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
attribute rsta_loop_iter : integer;
attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute rstb_loop_iter : integer;
attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
begin
almost_empty <= \^almost_empty\;
almost_full <= \^almost_full\;
dbiterr <= \<const0>\;
empty <= \^empty\;
full <= \^full\;
full_n <= \<const0>\;
prog_empty <= \^prog_empty\;
prog_full <= \^prog_full\;
rd_rst_busy <= \^rd_rst_busy\;
sbiterr <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6899"
)
port map (
I0 => ram_empty_i,
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => curr_fwft_state(1),
O => \next_fwft_state__0\(0)
);
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7A"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
O => \next_fwft_state__0\(1)
);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \next_fwft_state__0\(0),
Q => curr_fwft_state(0),
R => \^rd_rst_busy\
);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \next_fwft_state__0\(1),
Q => curr_fwft_state(1),
R => \^rd_rst_busy\
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gaf_wptr_p3.wrpp3_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn_5
port map (
Q(7 downto 0) => count_value_i(7 downto 0),
\count_value_i_reg[6]_0\ => \^full\,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1__1\
port map (
dest_clk => wr_clk,
dest_out_bin(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0),
src_clk => rd_clk,
src_in_bin(8 downto 7) => src_in_bin00_out(8 downto 7),
src_in_bin(6) => rdp_inst_n_11,
src_in_bin(5) => rdp_inst_n_12,
src_in_bin(4) => rdp_inst_n_13,
src_in_bin(3) => rdp_inst_n_14,
src_in_bin(2) => rdp_inst_n_15,
src_in_bin(1 downto 0) => src_in_bin00_out(1 downto 0)
);
\gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__2\
port map (
dest_clk => wr_clk,
dest_out_bin(7 downto 0) => rd_pntr_wr_cdc(7 downto 0),
src_clk => rd_clk,
src_in_bin(7 downto 0) => rd_pntr_ext(7 downto 0)
);
\gen_cdc_pntr.rpw_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_6
port map (
D(7 downto 0) => rd_pntr_wr_cdc(7 downto 0),
Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1),
almost_full => \^almost_full\,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg\ => \gen_cdc_pntr.rpw_gray_reg_n_0\,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_0\ => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_n_0\,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_1\ => rst_d1_inst_n_3,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg_2\(7 downto 0) => count_value_i(7 downto 0),
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(7) => wrpp2_inst_n_0,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(6) => wrpp2_inst_n_1,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(5) => wrpp2_inst_n_2,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(4) => wrpp2_inst_n_3,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(3) => wrpp2_inst_n_4,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(2) => wrpp2_inst_n_5,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(1) => wrpp2_inst_n_6,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\(0) => wrpp2_inst_n_7,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg_0\ => \^full\,
ram_full_i0 => ram_full_i0,
\reg_out_i_reg[7]_0\(7 downto 0) => rd_pntr_wr(7 downto 0),
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
\gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_7\
port map (
D(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0),
Q(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\,
Q(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\,
Q(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\,
Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\,
Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\,
Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\,
Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\,
Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\,
Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\,
wr_clk => wr_clk,
wrst_busy => wrst_busy
);
\gen_cdc_pntr.wpr_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_8
port map (
D(7 downto 0) => wr_pntr_rd_cdc(7 downto 0),
Q(7 downto 0) => rd_pntr_ext(7 downto 0),
S(2) => \gen_cdc_pntr.wpr_gray_reg_n_9\,
S(1) => \gen_cdc_pntr.wpr_gray_reg_n_10\,
S(0) => \gen_cdc_pntr.wpr_gray_reg_n_11\,
\count_value_i_reg[7]\ => \gen_cdc_pntr.wpr_gray_reg_n_0\,
rd_clk => rd_clk,
\reg_out_i_reg[0]_0\ => \^rd_rst_busy\,
\reg_out_i_reg[7]_0\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\,
\reg_out_i_reg[7]_0\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\,
\reg_out_i_reg[7]_0\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\,
\reg_out_i_reg[7]_0\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
\reg_out_i_reg[7]_0\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\,
\reg_out_i_reg[7]_0\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
\reg_out_i_reg[7]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
\reg_out_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
\reg_out_i_reg[7]_1\(3) => \gen_cdc_pntr.wpr_gray_reg_n_12\,
\reg_out_i_reg[7]_1\(2) => \gen_cdc_pntr.wpr_gray_reg_n_13\,
\reg_out_i_reg[7]_1\(1) => \gen_cdc_pntr.wpr_gray_reg_n_14\,
\reg_out_i_reg[7]_1\(0) => \gen_cdc_pntr.wpr_gray_reg_n_15\
);
\gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_9\
port map (
D(8 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(8 downto 0),
DI(0) => \gen_fwft.rdpp1_inst_n_2\,
Q(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_0\,
Q(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_1\,
Q(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_2\,
Q(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_3\,
Q(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_4\,
Q(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_5\,
Q(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_6\,
Q(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_7\,
Q(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\,
S(3) => rdp_inst_n_27,
S(2) => rdp_inst_n_28,
S(1) => \gen_fwft.rdpp1_inst_n_0\,
S(0) => \gen_fwft.rdpp1_inst_n_1\,
\grdc.rd_data_count_i_reg[3]\ => \gen_fwft.rdpp1_inst_n_3\,
\grdc.rd_data_count_i_reg[7]\(5 downto 0) => rd_pntr_ext(6 downto 1),
\grdc.rd_data_count_i_reg[7]_0\(3) => rdp_inst_n_29,
\grdc.rd_data_count_i_reg[7]_0\(2) => rdp_inst_n_30,
\grdc.rd_data_count_i_reg[7]_0\(1) => rdp_inst_n_31,
\grdc.rd_data_count_i_reg[7]_0\(0) => rdp_inst_n_32,
\grdc.rd_data_count_i_reg[8]\(0) => rdp_inst_n_18,
rd_clk => rd_clk,
\reg_out_i_reg[8]_0\ => \^rd_rst_busy\,
\reg_out_i_reg[8]_1\(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0)
);
\gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0__1\
port map (
dest_clk => rd_clk,
dest_out_bin(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0),
src_clk => wr_clk,
src_in_bin(8 downto 0) => wr_pntr_ext(8 downto 0)
);
\gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__1\
port map (
dest_clk => rd_clk,
dest_out_bin(7 downto 0) => wr_pntr_rd_cdc(7 downto 0),
src_clk => wr_clk,
src_in_bin(7 downto 0) => wr_pntr_ext(7 downto 0)
);
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BB80"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => \^empty\,
O => data_valid_fwft1
);
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => data_valid_fwft1,
Q => \^empty\,
S => \^rd_rst_busy\
);
\gen_fwft.gae_fwft.aempty_fwft_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBBB2000"
)
port map (
I0 => ram_empty_i,
I1 => curr_fwft_state(0),
I2 => rd_en,
I3 => curr_fwft_state(1),
I4 => \^almost_empty\,
O => aempty_fwft_i0
);
\gen_fwft.gae_fwft.aempty_fwft_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => aempty_fwft_i0,
Q => \^almost_empty\,
S => \^rd_rst_busy\
);
\gen_fwft.gdvld_fwft.data_valid_fwft_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"15F5"
)
port map (
I0 => \^empty\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
O => \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\
);
\gen_fwft.gdvld_fwft.data_valid_fwft_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\,
Q => data_valid,
R => \^rd_rst_busy\
);
\gen_fwft.rdpp1_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1_10\
port map (
DI(0) => \gen_fwft.rdpp1_inst_n_2\,
Q(1 downto 0) => rd_pntr_ext(1 downto 0),
S(1) => \gen_fwft.rdpp1_inst_n_0\,
S(0) => \gen_fwft.rdpp1_inst_n_1\,
\count_value_i_reg[0]_0\ => \gen_fwft.rdpp1_inst_n_4\,
\count_value_i_reg[1]_0\ => \gen_fwft.rdpp1_inst_n_3\,
\count_value_i_reg[1]_1\ => \^rd_rst_busy\,
\count_value_i_reg[1]_2\(1 downto 0) => curr_fwft_state(1 downto 0),
\grdc.rd_data_count_i_reg[3]\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_7\,
\grdc.rd_data_count_i_reg[3]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_8\,
ram_empty_i => ram_empty_i,
rd_clk => rd_clk,
rd_en => rd_en
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rst,
I1 => \^full\,
O => \gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_n_0\
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_cdc_pntr.rpw_gray_reg_n_0\,
Q => \^almost_full\,
R => '0'
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(0),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(1),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(2),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(3),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(4),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(5),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(6),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(7),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \^prog_empty\,
I1 => \^empty\,
I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\,
I3 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\,
O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\
);
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FF"
)
port map (
I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\,
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\,
I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\,
I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\,
O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\
);
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\,
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\,
I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\,
I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\,
O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\
);
\gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\,
Q => \^prog_empty\,
S => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(4),
Q => diff_pntr_pf_q(4),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(5),
Q => diff_pntr_pf_q(5),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(6),
Q => diff_pntr_pf_q(6),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(7),
Q => diff_pntr_pf_q(7),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(8),
Q => diff_pntr_pf_q(8),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => diff_pntr_pf_q(5),
I1 => diff_pntr_pf_q(8),
I2 => diff_pntr_pf_q(4),
I3 => diff_pntr_pf_q(6),
I4 => diff_pntr_pf_q(7),
O => p_1_in
);
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1_inst_n_1,
Q => \^prog_full\,
R => '0'
);
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i0,
Q => \^full\,
R => wrst_busy
);
\gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => ram_empty_i0,
Q => ram_empty_i,
S => \^rd_rst_busy\
);
\gen_sdpram.xpm_memory_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base__1\
port map (
addra(7 downto 0) => wr_pntr_ext(7 downto 0),
addrb(7 downto 0) => rd_pntr_ext(7 downto 0),
clka => wr_clk,
clkb => rd_clk,
dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
dina(7 downto 0) => din(7 downto 0),
dinb(7 downto 0) => B"00000000",
douta(7 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(7 downto 0),
doutb(7 downto 0) => dout(7 downto 0),
ena => wr_pntr_plus1_pf_carry,
enb => ram_rd_en_i,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '0',
regceb => \gen_fwft.ram_regout_en\,
rsta => '0',
rstb => \^rd_rst_busy\,
sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
sleep => sleep,
wea(0) => '0',
web(0) => '0'
);
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"62"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
O => \gen_fwft.ram_regout_en\
);
\gof.overflow_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => overflow_i0,
Q => overflow,
R => '0'
);
\grdc.rd_data_count_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(0),
Q => rd_data_count(0),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(1),
Q => rd_data_count(1),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(2),
Q => rd_data_count(2),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(3),
Q => rd_data_count(3),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(4),
Q => rd_data_count(4),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(5),
Q => rd_data_count(5),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(6),
Q => rd_data_count(6),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(7),
Q => rd_data_count(7),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(8),
Q => rd_data_count(8),
R => \grdc.rd_data_count_i0\
);
\guf.underflow_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => underflow_i0,
Q => underflow,
R => '0'
);
\gwack.wr_ack_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => xpm_fifo_rst_inst_n_2,
Q => wr_ack,
R => '0'
);
\gwdc.wr_data_count_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(0),
Q => wr_data_count(0),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(1),
Q => wr_data_count(1),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(2),
Q => wr_data_count(2),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(3),
Q => wr_data_count(3),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(4),
Q => wr_data_count(4),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(5),
Q => wr_data_count(5),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(6),
Q => wr_data_count(6),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(7),
Q => wr_data_count(7),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(8),
Q => wr_data_count(8),
R => wrst_busy
);
rdp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_11\
port map (
D(7 downto 0) => diff_pntr_pe(7 downto 0),
E(0) => ram_rd_en_i,
Q(7 downto 0) => rd_pntr_ext(7 downto 0),
S(2) => \gen_cdc_pntr.wpr_gray_reg_n_9\,
S(1) => \gen_cdc_pntr.wpr_gray_reg_n_10\,
S(0) => \gen_cdc_pntr.wpr_gray_reg_n_11\,
\count_value_i_reg[2]_0\(1) => rdp_inst_n_27,
\count_value_i_reg[2]_0\(0) => rdp_inst_n_28,
\count_value_i_reg[4]_0\ => rdpp1_inst_n_1,
\count_value_i_reg[6]_0\(3) => rdp_inst_n_29,
\count_value_i_reg[6]_0\(2) => rdp_inst_n_30,
\count_value_i_reg[6]_0\(1) => rdp_inst_n_31,
\count_value_i_reg[6]_0\(0) => rdp_inst_n_32,
\count_value_i_reg[7]_0\(0) => rdp_inst_n_18,
\count_value_i_reg[8]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
\count_value_i_reg[8]_1\ => \^rd_rst_busy\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3) => \gen_cdc_pntr.wpr_gray_reg_n_12\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2) => \gen_cdc_pntr.wpr_gray_reg_n_13\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1) => \gen_cdc_pntr.wpr_gray_reg_n_14\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0) => \gen_cdc_pntr.wpr_gray_reg_n_15\,
\grdc.rd_data_count_i_reg[3]\ => \gen_fwft.rdpp1_inst_n_3\,
\grdc.rd_data_count_i_reg[8]\(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_0\,
\grdc.rd_data_count_i_reg[8]\(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_1\,
\grdc.rd_data_count_i_reg[8]\(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_2\,
\grdc.rd_data_count_i_reg[8]\(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_3\,
\grdc.rd_data_count_i_reg[8]\(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_4\,
\grdc.rd_data_count_i_reg[8]\(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_5\,
\grdc.rd_data_count_i_reg[8]\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_6\,
\grdc.rd_data_count_i_reg[8]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_7\,
ram_empty_i => ram_empty_i,
rd_clk => rd_clk,
rd_en => rd_en,
\src_gray_ff_reg[0]\ => \gen_fwft.rdpp1_inst_n_4\,
src_in_bin(8 downto 7) => src_in_bin00_out(8 downto 7),
src_in_bin(6) => rdp_inst_n_11,
src_in_bin(5) => rdp_inst_n_12,
src_in_bin(4) => rdp_inst_n_13,
src_in_bin(3) => rdp_inst_n_14,
src_in_bin(2) => rdp_inst_n_15,
src_in_bin(1 downto 0) => src_in_bin00_out(1 downto 0)
);
rdpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_12\
port map (
E(0) => ram_rd_en_i,
Q(1 downto 0) => curr_fwft_state(1 downto 0),
\count_value_i_reg[0]_0\ => \^rd_rst_busy\,
\gen_pf_ic_rc.ram_empty_i_reg\ => rdpp1_inst_n_1,
\gen_pf_ic_rc.ram_empty_i_reg_0\ => \gen_cdc_pntr.wpr_gray_reg_n_0\,
\gen_pf_ic_rc.ram_empty_i_reg_1\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\,
\gen_pf_ic_rc.ram_empty_i_reg_1\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\,
\gen_pf_ic_rc.ram_empty_i_reg_1\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\,
\gen_pf_ic_rc.ram_empty_i_reg_1\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
\gen_pf_ic_rc.ram_empty_i_reg_1\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\,
\gen_pf_ic_rc.ram_empty_i_reg_1\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
\gen_pf_ic_rc.ram_empty_i_reg_1\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
\gen_pf_ic_rc.ram_empty_i_reg_1\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
ram_empty_i => ram_empty_i,
ram_empty_i0 => ram_empty_i0,
rd_clk => rd_clk,
rd_en => rd_en
);
rst_d1_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit_13
port map (
d_out_reg_0 => rst_d1_inst_n_3,
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \^full\,
\gen_pf_ic_rc.ngen_full_rst_val.ram_full_i_reg\ => rst_d1_inst_n_1,
overflow_i0 => overflow_i0,
p_1_in => p_1_in,
prog_full => \^prog_full\,
rst => rst,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wrst_busy => wrst_busy
);
wrp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_14\
port map (
D(8 downto 0) => \gwdc.diff_wr_rd_pntr1_out\(8 downto 0),
Q(8 downto 0) => wr_pntr_ext(8 downto 0),
\count_value_i_reg[6]_0\ => \^full\,
\gwdc.wr_data_count_i_reg[8]\(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\,
\gwdc.wr_data_count_i_reg[8]\(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\,
\gwdc.wr_data_count_i_reg[8]\(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\,
\gwdc.wr_data_count_i_reg[8]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\,
\gwdc.wr_data_count_i_reg[8]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\,
\gwdc.wr_data_count_i_reg[8]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\,
\gwdc.wr_data_count_i_reg[8]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\,
\gwdc.wr_data_count_i_reg[8]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\,
\gwdc.wr_data_count_i_reg[8]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
wrpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_15\
port map (
D(4 downto 0) => diff_pntr_pf_q0(8 downto 4),
Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1),
\count_value_i_reg[6]_0\ => \^full\,
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7 downto 0) => rd_pntr_wr(7 downto 0),
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
wrpp2_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0_16\
port map (
Q(7) => wrpp2_inst_n_0,
Q(6) => wrpp2_inst_n_1,
Q(5) => wrpp2_inst_n_2,
Q(4) => wrpp2_inst_n_3,
Q(3) => wrpp2_inst_n_4,
Q(2) => wrpp2_inst_n_5,
Q(1) => wrpp2_inst_n_6,
Q(0) => wrpp2_inst_n_7,
\count_value_i_reg[6]_0\ => \^full\,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
xpm_fifo_rst_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst__xdcDup__1\
port map (
Q(1 downto 0) => curr_fwft_state(1 downto 0),
SR(0) => \grdc.rd_data_count_i0\,
d_out_reg => xpm_fifo_rst_inst_n_2,
\gen_rst_ic.fifo_rd_rst_ic_reg_0\ => \^rd_rst_busy\,
\guf.underflow_i_reg\ => \^empty\,
\gwack.wr_ack_i_reg\ => \^full\,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
rst_d1 => rst_d1,
underflow_i0 => underflow_i0,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wr_rst_busy => wr_rst_busy,
wrst_busy => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ is
port (
sleep : in STD_LOGIC;
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
full_n : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
overflow : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
underflow : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
almost_empty : out STD_LOGIC;
data_valid : out STD_LOGIC;
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC
);
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute CDC_DEST_SYNC_FF : integer;
attribute CDC_DEST_SYNC_FF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 2;
attribute COMMON_CLOCK : integer;
attribute COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "0";
attribute ECC_MODE : integer;
attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute ENABLE_ECC : integer;
attribute ENABLE_ECC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute EN_ADV_FEATURE : string;
attribute EN_ADV_FEATURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "16'b0001111100011111";
attribute EN_AE : string;
attribute EN_AE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_AF : string;
attribute EN_AF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_DVLD : string;
attribute EN_DVLD of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_OF : string;
attribute EN_OF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_PE : string;
attribute EN_PE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_PF : string;
attribute EN_PF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_RDC : string;
attribute EN_RDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_UF : string;
attribute EN_UF of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_WACK : string;
attribute EN_WACK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute EN_WDC : string;
attribute EN_WDC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute FG_EQ_ASYM_DOUT : string;
attribute FG_EQ_ASYM_DOUT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b0";
attribute FIFO_MEMORY_TYPE : integer;
attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute FIFO_MEM_TYPE : integer;
attribute FIFO_MEM_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute FIFO_READ_DEPTH : integer;
attribute FIFO_READ_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 256;
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute FIFO_SIZE : integer;
attribute FIFO_SIZE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 2048;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 256;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1;
attribute FULL_RST_VAL : string;
attribute FULL_RST_VAL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "xpm_fifo_base";
attribute PE_THRESH_ADJ : integer;
attribute PE_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8;
attribute PE_THRESH_MAX : integer;
attribute PE_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 251;
attribute PE_THRESH_MIN : integer;
attribute PE_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 5;
attribute PF_THRESH_ADJ : integer;
attribute PF_THRESH_ADJ of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8;
attribute PF_THRESH_MAX : integer;
attribute PF_THRESH_MAX of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 251;
attribute PF_THRESH_MIN : integer;
attribute PF_THRESH_MIN of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 7;
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 10;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9;
attribute RD_DC_WIDTH_EXT : integer;
attribute RD_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9;
attribute RD_LATENCY : integer;
attribute RD_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 2;
attribute RD_MODE : integer;
attribute RD_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1;
attribute RD_PNTR_WIDTH : integer;
attribute RD_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8;
attribute READ_MODE : integer;
attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1;
attribute READ_MODE_LL : integer;
attribute READ_MODE_LL of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1;
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute REMOVE_WR_RD_PROT_LOGIC : integer;
attribute REMOVE_WR_RD_PROT_LOGIC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "1F1F";
attribute VERSION : integer;
attribute VERSION of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute WIDTH_RATIO : integer;
attribute WIDTH_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9;
attribute WR_DC_WIDTH_EXT : integer;
attribute WR_DC_WIDTH_EXT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 9;
attribute WR_DEPTH_LOG : integer;
attribute WR_DEPTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8;
attribute WR_PNTR_WIDTH : integer;
attribute WR_PNTR_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 8;
attribute WR_RD_RATIO : integer;
attribute WR_RD_RATIO of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute WR_WIDTH_LOG : integer;
attribute WR_WIDTH_LOG of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 3;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "TRUE";
attribute both_stages_valid : integer;
attribute both_stages_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 3;
attribute invalid : integer;
attribute invalid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 0;
attribute keep_hierarchy : string;
attribute keep_hierarchy of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is "soft";
attribute stage1_valid : integer;
attribute stage1_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 2;
attribute stage2_valid : integer;
attribute stage2_valid of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ : entity is 1;
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal aempty_fwft_i0 : STD_LOGIC;
signal \^almost_empty\ : STD_LOGIC;
signal \^almost_full\ : STD_LOGIC;
signal clr_full : STD_LOGIC;
signal count_value_i : STD_LOGIC_VECTOR ( 7 downto 0 );
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal data_valid_fwft1 : STD_LOGIC;
signal diff_pntr_pe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal diff_pntr_pf_q : STD_LOGIC_VECTOR ( 8 downto 4 );
signal diff_pntr_pf_q0 : STD_LOGIC_VECTOR ( 8 downto 4 );
signal \^empty\ : STD_LOGIC;
signal \^full\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_0\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_1\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_2\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_3\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_4\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_5\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_6\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_7\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_dc_n_8\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_n_0\ : STD_LOGIC;
signal \gen_cdc_pntr.rpw_gray_reg_n_9\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_10\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_11\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_12\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_13\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_14\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_15\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_16\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_17\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_dc_n_9\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_1\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_2\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_3\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_4\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_5\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_6\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_7\ : STD_LOGIC;
signal \gen_cdc_pntr.wpr_gray_reg_n_8\ : STD_LOGIC;
signal \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\ : STD_LOGIC;
signal \gen_fwft.ram_regout_en\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_1\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_2\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_3\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_4\ : STD_LOGIC;
signal \gen_fwft.rdpp1_inst_n_5\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\ : STD_LOGIC;
signal \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\ : STD_LOGIC;
signal \grdc.diff_wr_rd_pntr_rdc\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \grdc.rd_data_count_i0\ : STD_LOGIC;
signal \gwdc.diff_wr_rd_pntr1_out\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \next_fwft_state__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal overflow_i0 : STD_LOGIC;
signal \^prog_empty\ : STD_LOGIC;
signal \^prog_full\ : STD_LOGIC;
signal ram_empty_i : STD_LOGIC;
signal ram_empty_i0 : STD_LOGIC;
signal rd_pntr_ext : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_pntr_wr : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_pntr_wr_cdc : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_pntr_wr_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^rd_rst_busy\ : STD_LOGIC;
signal rdp_inst_n_10 : STD_LOGIC;
signal rdp_inst_n_19 : STD_LOGIC;
signal rdp_inst_n_20 : STD_LOGIC;
signal rdp_inst_n_21 : STD_LOGIC;
signal rdp_inst_n_22 : STD_LOGIC;
signal rdp_inst_n_23 : STD_LOGIC;
signal rdp_inst_n_24 : STD_LOGIC;
signal rdp_inst_n_25 : STD_LOGIC;
signal rdp_inst_n_26 : STD_LOGIC;
signal rdp_inst_n_27 : STD_LOGIC;
signal rdp_inst_n_28 : STD_LOGIC;
signal rdp_inst_n_29 : STD_LOGIC;
signal rdp_inst_n_30 : STD_LOGIC;
signal rdp_inst_n_31 : STD_LOGIC;
signal rdp_inst_n_8 : STD_LOGIC;
signal rdp_inst_n_9 : STD_LOGIC;
signal rdpp1_inst_n_0 : STD_LOGIC;
signal rdpp1_inst_n_1 : STD_LOGIC;
signal rdpp1_inst_n_2 : STD_LOGIC;
signal rdpp1_inst_n_3 : STD_LOGIC;
signal rdpp1_inst_n_4 : STD_LOGIC;
signal rdpp1_inst_n_5 : STD_LOGIC;
signal rdpp1_inst_n_6 : STD_LOGIC;
signal rdpp1_inst_n_7 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d1_inst_n_1 : STD_LOGIC;
signal src_in_bin00_out : STD_LOGIC_VECTOR ( 1 to 1 );
signal underflow_i0 : STD_LOGIC;
signal wr_pntr_ext : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wr_pntr_plus1_pf : STD_LOGIC_VECTOR ( 8 downto 1 );
signal wr_pntr_plus1_pf_carry : STD_LOGIC;
signal wr_pntr_rd_cdc : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wr_pntr_rd_cdc_dc : STD_LOGIC_VECTOR ( 8 downto 0 );
signal wrpp2_inst_n_0 : STD_LOGIC;
signal wrpp2_inst_n_1 : STD_LOGIC;
signal wrpp2_inst_n_2 : STD_LOGIC;
signal wrpp2_inst_n_3 : STD_LOGIC;
signal wrpp2_inst_n_4 : STD_LOGIC;
signal wrpp2_inst_n_5 : STD_LOGIC;
signal wrpp2_inst_n_6 : STD_LOGIC;
signal wrpp2_inst_n_7 : STD_LOGIC;
signal wrst_busy : STD_LOGIC;
signal xpm_fifo_rst_inst_n_2 : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\ : label is "soft_lutpair71";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
attribute FSM_ENCODED_STATES of \FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\ : label is "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11";
attribute DEST_SYNC_FF : integer;
attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 2;
attribute INIT_SYNC_FF : integer;
attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 1;
attribute REG_OUTPUT : integer;
attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
attribute SIM_LOSSLESS_GRAY_CHK : integer;
attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 0;
attribute WIDTH : integer;
attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is 9;
attribute XPM_CDC : string;
attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "GRAY";
attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_dc_inst\ : label is "TRUE";
attribute DEST_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 2;
attribute INIT_SYNC_FF of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 1;
attribute REG_OUTPUT of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
attribute VERSION of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 0;
attribute WIDTH of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is 8;
attribute XPM_CDC of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "GRAY";
attribute XPM_MODULE of \gen_cdc_pntr.rd_pntr_cdc_inst\ : label is "TRUE";
attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 4;
attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 1;
attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 0;
attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is 9;
attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "GRAY";
attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_dc_inst\ : label is "TRUE";
attribute DEST_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 2;
attribute INIT_SYNC_FF of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 1;
attribute REG_OUTPUT of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
attribute SIM_LOSSLESS_GRAY_CHK of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
attribute VERSION of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 0;
attribute WIDTH of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is 8;
attribute XPM_CDC of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "GRAY";
attribute XPM_MODULE of \gen_cdc_pntr.wr_pntr_cdc_inst\ : label is "TRUE";
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute CASCADE_HEIGHT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute IGNORE_INIT_SYNTH : integer;
attribute IGNORE_INIT_SYNTH of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute KEEP_HIERARCHY of \gen_sdpram.xpm_memory_base_inst\ : label is "soft";
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of \gen_sdpram.xpm_memory_base_inst\ : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of \gen_sdpram.xpm_memory_base_inst\ : label is 7;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of \gen_sdpram.xpm_memory_base_inst\ : label is 1023;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \gen_sdpram.xpm_memory_base_inst\ : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \gen_sdpram.xpm_memory_base_inst\ : label is "";
attribute MEMORY_OPTIMIZATION : string;
attribute MEMORY_OPTIMIZATION of \gen_sdpram.xpm_memory_base_inst\ : label is "true";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \gen_sdpram.xpm_memory_base_inst\ : label is 2048;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 256;
attribute P_MEMORY_OPT : string;
attribute P_MEMORY_OPT of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \gen_sdpram.xpm_memory_base_inst\ : label is "auto";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \gen_sdpram.xpm_memory_base_inst\ : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \gen_sdpram.xpm_memory_base_inst\ : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "0";
attribute RST_MODE_A : string;
attribute RST_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
attribute RST_MODE_B : string;
attribute RST_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is "SYNC";
attribute SIM_ASSERT_CHK of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_EMBEDDED_CONSTRAINT : integer;
attribute USE_EMBEDDED_CONSTRAINT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute USE_MEM_INIT_MMI : integer;
attribute USE_MEM_INIT_MMI of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute VERSION of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute WAKEUP_TIME of \gen_sdpram.xpm_memory_base_inst\ : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \gen_sdpram.xpm_memory_base_inst\ : label is 2;
attribute WRITE_PROTECT : integer;
attribute WRITE_PROTECT of \gen_sdpram.xpm_memory_base_inst\ : label is 1;
attribute XPM_MODULE of \gen_sdpram.xpm_memory_base_inst\ : label is "TRUE";
attribute rsta_loop_iter : integer;
attribute rsta_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
attribute rstb_loop_iter : integer;
attribute rstb_loop_iter of \gen_sdpram.xpm_memory_base_inst\ : label is 8;
begin
almost_empty <= \^almost_empty\;
almost_full <= \^almost_full\;
dbiterr <= \<const0>\;
empty <= \^empty\;
full <= \^full\;
full_n <= \<const0>\;
prog_empty <= \^prog_empty\;
prog_full <= \^prog_full\;
rd_rst_busy <= \^rd_rst_busy\;
sbiterr <= \<const0>\;
\FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6A85"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => curr_fwft_state(1),
I3 => ram_empty_i,
O => \next_fwft_state__0\(0)
);
\FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3FF0"
)
port map (
I0 => ram_empty_i,
I1 => rd_en,
I2 => curr_fwft_state(1),
I3 => curr_fwft_state(0),
O => \next_fwft_state__0\(1)
);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \next_fwft_state__0\(0),
Q => curr_fwft_state(0),
R => \^rd_rst_busy\
);
\FSM_sequential_gen_fwft.curr_fwft_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \next_fwft_state__0\(1),
Q => curr_fwft_state(1),
R => \^rd_rst_busy\
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gaf_wptr_p3.wrpp3_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn
port map (
Q(7 downto 0) => count_value_i(7 downto 0),
\count_value_i_reg[6]_0\ => \^full\,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
\gen_cdc_pntr.rd_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized1\
port map (
dest_clk => wr_clk,
dest_out_bin(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0),
src_clk => rd_clk,
src_in_bin(8) => rdp_inst_n_24,
src_in_bin(7) => rdp_inst_n_25,
src_in_bin(6) => rdp_inst_n_26,
src_in_bin(5) => rdp_inst_n_27,
src_in_bin(4) => rdp_inst_n_28,
src_in_bin(3) => rdp_inst_n_29,
src_in_bin(2) => rdp_inst_n_30,
src_in_bin(1) => src_in_bin00_out(1),
src_in_bin(0) => rdp_inst_n_31
);
\gen_cdc_pntr.rd_pntr_cdc_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray
port map (
dest_clk => wr_clk,
dest_out_bin(7 downto 0) => rd_pntr_wr_cdc(7 downto 0),
src_clk => rd_clk,
src_in_bin(7 downto 0) => rd_pntr_ext(7 downto 0)
);
\gen_cdc_pntr.rpw_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec
port map (
D(7 downto 0) => rd_pntr_wr_cdc(7 downto 0),
Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1),
almost_full => \^almost_full\,
clr_full => clr_full,
d_out_reg => \gen_cdc_pntr.rpw_gray_reg_n_9\,
\gen_pf_ic_rc.gaf_ic.ram_afull_i_i_2_0\(7 downto 0) => count_value_i(7 downto 0),
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg\ => \^full\,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\ => \gen_cdc_pntr.rpw_gray_reg_n_0\,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(7) => wrpp2_inst_n_0,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(6) => wrpp2_inst_n_1,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(5) => wrpp2_inst_n_2,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(4) => wrpp2_inst_n_3,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(3) => wrpp2_inst_n_4,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(2) => wrpp2_inst_n_5,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(1) => wrpp2_inst_n_6,
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg_0\(0) => wrpp2_inst_n_7,
\reg_out_i_reg[7]_0\(7 downto 0) => rd_pntr_wr(7 downto 0),
rst => rst,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
\gen_cdc_pntr.rpw_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0\
port map (
D(8 downto 0) => rd_pntr_wr_cdc_dc(8 downto 0),
Q(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\,
Q(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\,
Q(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\,
Q(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\,
Q(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\,
Q(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\,
Q(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\,
Q(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\,
Q(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\,
wr_clk => wr_clk,
wrst_busy => wrst_busy
);
\gen_cdc_pntr.wpr_gray_reg\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec_1
port map (
D(7 downto 0) => wr_pntr_rd_cdc(7 downto 0),
Q(1 downto 0) => curr_fwft_state(1 downto 0),
\gen_pf_ic_rc.ram_empty_i_reg\(7 downto 0) => rd_pntr_ext(7 downto 0),
\gen_pf_ic_rc.ram_empty_i_reg_0\(7) => rdpp1_inst_n_0,
\gen_pf_ic_rc.ram_empty_i_reg_0\(6) => rdpp1_inst_n_1,
\gen_pf_ic_rc.ram_empty_i_reg_0\(5) => rdpp1_inst_n_2,
\gen_pf_ic_rc.ram_empty_i_reg_0\(4) => rdpp1_inst_n_3,
\gen_pf_ic_rc.ram_empty_i_reg_0\(3) => rdpp1_inst_n_4,
\gen_pf_ic_rc.ram_empty_i_reg_0\(2) => rdpp1_inst_n_5,
\gen_pf_ic_rc.ram_empty_i_reg_0\(1) => rdpp1_inst_n_6,
\gen_pf_ic_rc.ram_empty_i_reg_0\(0) => rdpp1_inst_n_7,
ram_empty_i => ram_empty_i,
ram_empty_i0 => ram_empty_i0,
rd_clk => rd_clk,
rd_en => rd_en,
\reg_out_i_reg[0]_0\ => \^rd_rst_busy\,
\reg_out_i_reg[7]_0\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\,
\reg_out_i_reg[7]_0\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\,
\reg_out_i_reg[7]_0\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\,
\reg_out_i_reg[7]_0\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
\reg_out_i_reg[7]_0\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\,
\reg_out_i_reg[7]_0\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
\reg_out_i_reg[7]_0\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
\reg_out_i_reg[7]_0\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\
);
\gen_cdc_pntr.wpr_gray_reg_dc\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_vec__parameterized0_2\
port map (
D(8 downto 0) => \grdc.diff_wr_rd_pntr_rdc\(8 downto 0),
DI(1) => rdp_inst_n_9,
DI(0) => \gen_fwft.rdpp1_inst_n_5\,
Q(8) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\,
Q(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\,
Q(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\,
Q(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\,
Q(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\,
Q(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\,
Q(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\,
Q(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\,
Q(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_17\,
S(2) => rdp_inst_n_19,
S(1) => \gen_fwft.rdpp1_inst_n_3\,
S(0) => \gen_fwft.rdpp1_inst_n_4\,
\grdc.rd_data_count_i_reg[3]\ => \gen_fwft.rdpp1_inst_n_2\,
\grdc.rd_data_count_i_reg[7]\(3) => rdp_inst_n_20,
\grdc.rd_data_count_i_reg[7]\(2) => rdp_inst_n_21,
\grdc.rd_data_count_i_reg[7]\(1) => rdp_inst_n_22,
\grdc.rd_data_count_i_reg[7]\(0) => rdp_inst_n_23,
\grdc.rd_data_count_i_reg[7]_0\(5 downto 0) => rd_pntr_ext(6 downto 1),
\grdc.rd_data_count_i_reg[8]\(0) => rdp_inst_n_10,
rd_clk => rd_clk,
\reg_out_i_reg[8]_0\ => \^rd_rst_busy\,
\reg_out_i_reg[8]_1\(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0)
);
\gen_cdc_pntr.wr_pntr_cdc_dc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__parameterized0\
port map (
dest_clk => rd_clk,
dest_out_bin(8 downto 0) => wr_pntr_rd_cdc_dc(8 downto 0),
src_clk => wr_clk,
src_in_bin(8 downto 0) => wr_pntr_ext(8 downto 0)
);
\gen_cdc_pntr.wr_pntr_cdc_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_cdc_gray__3\
port map (
dest_clk => rd_clk,
dest_out_bin(7 downto 0) => wr_pntr_rd_cdc(7 downto 0),
src_clk => wr_clk,
src_in_bin(7 downto 0) => wr_pntr_ext(7 downto 0)
);
\gen_fwft.empty_fwft_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F380"
)
port map (
I0 => rd_en,
I1 => curr_fwft_state(0),
I2 => curr_fwft_state(1),
I3 => \^empty\,
O => data_valid_fwft1
);
\gen_fwft.empty_fwft_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => data_valid_fwft1,
Q => \^empty\,
S => \^rd_rst_busy\
);
\gen_fwft.gae_fwft.aempty_fwft_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FDDD4000"
)
port map (
I0 => curr_fwft_state(0),
I1 => ram_empty_i,
I2 => curr_fwft_state(1),
I3 => rd_en,
I4 => \^almost_empty\,
O => aempty_fwft_i0
);
\gen_fwft.gae_fwft.aempty_fwft_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => aempty_fwft_i0,
Q => \^almost_empty\,
S => \^rd_rst_busy\
);
\gen_fwft.gdvld_fwft.data_valid_fwft_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3575"
)
port map (
I0 => \^empty\,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => rd_en,
O => \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\
);
\gen_fwft.gdvld_fwft.data_valid_fwft_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_fwft.gdvld_fwft.data_valid_fwft_i_1_n_0\,
Q => data_valid,
R => \^rd_rst_busy\
);
\gen_fwft.rdpp1_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized1\
port map (
DI(0) => \gen_fwft.rdpp1_inst_n_5\,
Q(1 downto 0) => rd_pntr_ext(1 downto 0),
S(1) => \gen_fwft.rdpp1_inst_n_3\,
S(0) => \gen_fwft.rdpp1_inst_n_4\,
\count_value_i_reg[0]_0\ => \gen_fwft.rdpp1_inst_n_1\,
\count_value_i_reg[1]_0\ => \gen_fwft.rdpp1_inst_n_2\,
\count_value_i_reg[1]_1\(1 downto 0) => curr_fwft_state(1 downto 0),
\count_value_i_reg[1]_2\ => \^rd_rst_busy\,
\grdc.rd_data_count_i_reg[3]\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\,
\grdc.rd_data_count_i_reg[3]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_17\,
ram_empty_i => ram_empty_i,
rd_clk => rd_clk,
rd_en => rd_en,
src_in_bin(0) => src_in_bin00_out(1)
);
\gen_pf_ic_rc.gaf_ic.ram_afull_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_cdc_pntr.rpw_gray_reg_n_0\,
Q => \^almost_full\,
S => wrst_busy
);
\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \gen_cdc_pntr.rpw_gray_reg_n_9\,
Q => \^full\,
S => wrst_busy
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(0),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(1),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(2),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(3),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(4),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(5),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(6),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => diff_pntr_pe(7),
Q => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\,
R => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \^prog_empty\,
I1 => \^empty\,
I2 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\,
I3 => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\,
O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\
);
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"01FF"
)
port map (
I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0]\,
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1]\,
I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2]\,
I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3]\,
O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0\
);
\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5]\,
I1 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4]\,
I2 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7]\,
I3 => \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6]\,
O => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0\
);
\gen_pf_ic_rc.gpe_ic.prog_empty_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0\,
Q => \^prog_empty\,
S => \^rd_rst_busy\
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(4),
Q => diff_pntr_pf_q(4),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(5),
Q => diff_pntr_pf_q(5),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(6),
Q => diff_pntr_pf_q(6),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(7),
Q => diff_pntr_pf_q(7),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => diff_pntr_pf_q0(8),
Q => diff_pntr_pf_q(8),
R => wrst_busy
);
\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => diff_pntr_pf_q(5),
I1 => diff_pntr_pf_q(8),
I2 => diff_pntr_pf_q(4),
I3 => diff_pntr_pf_q(6),
I4 => diff_pntr_pf_q(7),
O => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\
);
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1_inst_n_1,
Q => \^prog_full\,
S => wrst_busy
);
\gen_pf_ic_rc.ram_empty_i_reg\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => ram_empty_i0,
Q => ram_empty_i,
S => \^rd_rst_busy\
);
\gen_sdpram.xpm_memory_base_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_memory_base
port map (
addra(7 downto 0) => wr_pntr_ext(7 downto 0),
addrb(7 downto 0) => rd_pntr_ext(7 downto 0),
clka => wr_clk,
clkb => rd_clk,
dbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED\,
dbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED\,
dina(7 downto 0) => din(7 downto 0),
dinb(7 downto 0) => B"00000000",
douta(7 downto 0) => \NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED\(7 downto 0),
doutb(7 downto 0) => dout(7 downto 0),
ena => wr_pntr_plus1_pf_carry,
enb => rdp_inst_n_8,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '0',
regceb => \gen_fwft.ram_regout_en\,
rsta => '0',
rstb => \^rd_rst_busy\,
sbiterra => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED\,
sbiterrb => \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED\,
sleep => sleep,
wea(0) => '0',
web(0) => '0'
);
\gen_sdpram.xpm_memory_base_inst_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"62"
)
port map (
I0 => curr_fwft_state(0),
I1 => curr_fwft_state(1),
I2 => rd_en,
O => \gen_fwft.ram_regout_en\
);
\gof.overflow_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => overflow_i0,
Q => overflow,
R => '0'
);
\grdc.rd_data_count_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(0),
Q => rd_data_count(0),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(1),
Q => rd_data_count(1),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(2),
Q => rd_data_count(2),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(3),
Q => rd_data_count(3),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(4),
Q => rd_data_count(4),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(5),
Q => rd_data_count(5),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(6),
Q => rd_data_count(6),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(7),
Q => rd_data_count(7),
R => \grdc.rd_data_count_i0\
);
\grdc.rd_data_count_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => rd_clk,
CE => '1',
D => \grdc.diff_wr_rd_pntr_rdc\(8),
Q => rd_data_count(8),
R => \grdc.rd_data_count_i0\
);
\guf.underflow_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => underflow_i0,
Q => underflow,
R => '0'
);
\gwack.wr_ack_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => xpm_fifo_rst_inst_n_2,
Q => wr_ack,
R => '0'
);
\gwdc.wr_data_count_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(0),
Q => wr_data_count(0),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(1),
Q => wr_data_count(1),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(2),
Q => wr_data_count(2),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(3),
Q => wr_data_count(3),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(4),
Q => wr_data_count(4),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(5),
Q => wr_data_count(5),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(6),
Q => wr_data_count(6),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(7),
Q => wr_data_count(7),
R => wrst_busy
);
\gwdc.wr_data_count_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => wr_clk,
CE => '1',
D => \gwdc.diff_wr_rd_pntr1_out\(8),
Q => wr_data_count(8),
R => wrst_busy
);
rdp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2\
port map (
D(7 downto 0) => diff_pntr_pe(7 downto 0),
DI(0) => rdp_inst_n_9,
Q(7 downto 0) => rd_pntr_ext(7 downto 0),
S(0) => rdp_inst_n_19,
\count_value_i_reg[0]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
\count_value_i_reg[6]_0\(3) => rdp_inst_n_20,
\count_value_i_reg[6]_0\(2) => rdp_inst_n_21,
\count_value_i_reg[6]_0\(1) => rdp_inst_n_22,
\count_value_i_reg[6]_0\(0) => rdp_inst_n_23,
\count_value_i_reg[7]_0\(0) => rdp_inst_n_10,
\count_value_i_reg[8]_0\ => \^rd_rst_busy\,
enb => rdp_inst_n_8,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(7) => \gen_cdc_pntr.wpr_gray_reg_n_1\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(6) => \gen_cdc_pntr.wpr_gray_reg_n_2\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(5) => \gen_cdc_pntr.wpr_gray_reg_n_3\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(4) => \gen_cdc_pntr.wpr_gray_reg_n_4\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(3) => \gen_cdc_pntr.wpr_gray_reg_n_5\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(2) => \gen_cdc_pntr.wpr_gray_reg_n_6\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(1) => \gen_cdc_pntr.wpr_gray_reg_n_7\,
\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]\(0) => \gen_cdc_pntr.wpr_gray_reg_n_8\,
\grdc.rd_data_count_i_reg[3]\ => \gen_fwft.rdpp1_inst_n_2\,
\grdc.rd_data_count_i_reg[8]\(7) => \gen_cdc_pntr.wpr_gray_reg_dc_n_9\,
\grdc.rd_data_count_i_reg[8]\(6) => \gen_cdc_pntr.wpr_gray_reg_dc_n_10\,
\grdc.rd_data_count_i_reg[8]\(5) => \gen_cdc_pntr.wpr_gray_reg_dc_n_11\,
\grdc.rd_data_count_i_reg[8]\(4) => \gen_cdc_pntr.wpr_gray_reg_dc_n_12\,
\grdc.rd_data_count_i_reg[8]\(3) => \gen_cdc_pntr.wpr_gray_reg_dc_n_13\,
\grdc.rd_data_count_i_reg[8]\(2) => \gen_cdc_pntr.wpr_gray_reg_dc_n_14\,
\grdc.rd_data_count_i_reg[8]\(1) => \gen_cdc_pntr.wpr_gray_reg_dc_n_15\,
\grdc.rd_data_count_i_reg[8]\(0) => \gen_cdc_pntr.wpr_gray_reg_dc_n_16\,
ram_empty_i => ram_empty_i,
rd_clk => rd_clk,
rd_en => rd_en,
\src_gray_ff_reg[2]\ => \gen_fwft.rdpp1_inst_n_1\,
src_in_bin(7) => rdp_inst_n_24,
src_in_bin(6) => rdp_inst_n_25,
src_in_bin(5) => rdp_inst_n_26,
src_in_bin(4) => rdp_inst_n_27,
src_in_bin(3) => rdp_inst_n_28,
src_in_bin(2) => rdp_inst_n_29,
src_in_bin(1) => rdp_inst_n_30,
src_in_bin(0) => rdp_inst_n_31
);
rdpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3\
port map (
E(0) => rdp_inst_n_8,
Q(7) => rdpp1_inst_n_0,
Q(6) => rdpp1_inst_n_1,
Q(5) => rdpp1_inst_n_2,
Q(4) => rdpp1_inst_n_3,
Q(3) => rdpp1_inst_n_4,
Q(2) => rdpp1_inst_n_5,
Q(1) => rdpp1_inst_n_6,
Q(0) => rdpp1_inst_n_7,
\count_value_i_reg[0]_0\ => \^rd_rst_busy\,
\count_value_i_reg[1]_0\(1 downto 0) => curr_fwft_state(1 downto 0),
ram_empty_i => ram_empty_i,
rd_clk => rd_clk,
rd_en => rd_en
);
rst_d1_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_reg_bit
port map (
clr_full => clr_full,
d_out_reg_0 => rst_d1_inst_n_1,
\gen_pf_ic_rc.gpf_ic.prog_full_i_reg\ => \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0\,
\gof.overflow_i_reg\ => \^full\,
overflow_i0 => overflow_i0,
prog_full => \^prog_full\,
rst => rst,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wrst_busy => wrst_busy
);
wrp_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized2_3\
port map (
D(8 downto 0) => \gwdc.diff_wr_rd_pntr1_out\(8 downto 0),
Q(8 downto 0) => wr_pntr_ext(8 downto 0),
\count_value_i_reg[6]_0\ => \^full\,
\gwdc.wr_data_count_i_reg[8]\(8) => \gen_cdc_pntr.rpw_gray_reg_dc_n_0\,
\gwdc.wr_data_count_i_reg[8]\(7) => \gen_cdc_pntr.rpw_gray_reg_dc_n_1\,
\gwdc.wr_data_count_i_reg[8]\(6) => \gen_cdc_pntr.rpw_gray_reg_dc_n_2\,
\gwdc.wr_data_count_i_reg[8]\(5) => \gen_cdc_pntr.rpw_gray_reg_dc_n_3\,
\gwdc.wr_data_count_i_reg[8]\(4) => \gen_cdc_pntr.rpw_gray_reg_dc_n_4\,
\gwdc.wr_data_count_i_reg[8]\(3) => \gen_cdc_pntr.rpw_gray_reg_dc_n_5\,
\gwdc.wr_data_count_i_reg[8]\(2) => \gen_cdc_pntr.rpw_gray_reg_dc_n_6\,
\gwdc.wr_data_count_i_reg[8]\(1) => \gen_cdc_pntr.rpw_gray_reg_dc_n_7\,
\gwdc.wr_data_count_i_reg[8]\(0) => \gen_cdc_pntr.rpw_gray_reg_dc_n_8\,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
wrpp1_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized3_4\
port map (
D(4 downto 0) => diff_pntr_pf_q0(8 downto 4),
Q(7 downto 0) => wr_pntr_plus1_pf(8 downto 1),
\count_value_i_reg[6]_0\ => \^full\,
\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]\(7 downto 0) => rd_pntr_wr(7 downto 0),
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
wrpp2_inst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_counter_updn__parameterized0\
port map (
Q(7) => wrpp2_inst_n_0,
Q(6) => wrpp2_inst_n_1,
Q(5) => wrpp2_inst_n_2,
Q(4) => wrpp2_inst_n_3,
Q(3) => wrpp2_inst_n_4,
Q(2) => wrpp2_inst_n_5,
Q(1) => wrpp2_inst_n_6,
Q(0) => wrpp2_inst_n_7,
\count_value_i_reg[6]_0\ => \^full\,
rst_d1 => rst_d1,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wrst_busy => wrst_busy
);
xpm_fifo_rst_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_rst
port map (
Q(1 downto 0) => curr_fwft_state(1 downto 0),
SR(0) => \grdc.rd_data_count_i0\,
d_out_reg => xpm_fifo_rst_inst_n_2,
\gen_rst_ic.fifo_rd_rst_ic_reg_0\ => \^rd_rst_busy\,
\guf.underflow_i_reg\ => \^empty\,
\gwack.wr_ack_i_reg\ => \^full\,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
rst_d1 => rst_d1,
underflow_i0 => underflow_i0,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pf_carry => wr_pntr_plus1_pf_carry,
wr_rst_busy => wr_rst_busy,
wrst_busy => wrst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async is
port (
sleep : in STD_LOGIC;
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
overflow : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
underflow : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
almost_empty : out STD_LOGIC;
data_valid : out STD_LOGIC;
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC
);
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute CDC_SYNC_STAGES : integer;
attribute CDC_SYNC_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 2;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "0";
attribute ECC_MODE : string;
attribute ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "no_ecc";
attribute EN_ADV_FEATURE_ASYNC : string;
attribute EN_ADV_FEATURE_ASYNC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "16'b0001111100011111";
attribute FIFO_MEMORY_TYPE : string;
attribute FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "auto";
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 256;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 10;
attribute P_COMMON_CLOCK : integer;
attribute P_COMMON_CLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute P_ECC_MODE : integer;
attribute P_ECC_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute P_FIFO_MEMORY_TYPE : integer;
attribute P_FIFO_MEMORY_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute P_READ_MODE : integer;
attribute P_READ_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 1;
attribute P_WAKEUP_TIME : integer;
attribute P_WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 2;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 9;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 8;
attribute READ_MODE : string;
attribute READ_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "fwft";
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "1f1f";
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 0;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 8;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is 9;
attribute XPM_MODULE : string;
attribute XPM_MODULE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "TRUE";
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async is
signal \<const0>\ : STD_LOGIC;
signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC;
attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute CDC_DEST_SYNC_FF : integer;
attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
attribute COMMON_CLOCK : integer;
attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0";
attribute ECC_MODE_integer : integer;
attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute ENABLE_ECC : integer;
attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute EN_ADV_FEATURE : string;
attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0001111100011111";
attribute EN_AE : string;
attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_AF : string;
attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_DVLD : string;
attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_OF : string;
attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_PE : string;
attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_PF : string;
attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_RDC : string;
attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_UF : string;
attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_WACK : string;
attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_WDC : string;
attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute FG_EQ_ASYM_DOUT : string;
attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
attribute FIFO_MEMORY_TYPE_integer : integer;
attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute FIFO_MEM_TYPE : integer;
attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute FIFO_READ_DEPTH : integer;
attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256;
attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute FIFO_SIZE : integer;
attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2048;
attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256;
attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute FULL_RST_VAL : string;
attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft";
attribute PE_THRESH_ADJ : integer;
attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute PE_THRESH_MAX : integer;
attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251;
attribute PE_THRESH_MIN : integer;
attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
attribute PF_THRESH_ADJ : integer;
attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute PF_THRESH_MAX : integer;
attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251;
attribute PF_THRESH_MIN : integer;
attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 7;
attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9;
attribute RD_DC_WIDTH_EXT : integer;
attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9;
attribute RD_LATENCY : integer;
attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
attribute RD_MODE : integer;
attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute RD_PNTR_WIDTH : integer;
attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute READ_MODE_integer : integer;
attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute READ_MODE_LL : integer;
attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute REMOVE_WR_RD_PROT_LOGIC : integer;
attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1f1f";
attribute VERSION : integer;
attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute WIDTH_RATIO : integer;
attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9;
attribute WR_DC_WIDTH_EXT : integer;
attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9;
attribute WR_DEPTH_LOG : integer;
attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute WR_PNTR_WIDTH : integer;
attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute WR_RD_RATIO : integer;
attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute WR_WIDTH_LOG : integer;
attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3;
attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE";
attribute both_stages_valid : integer;
attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3;
attribute invalid : integer;
attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute stage1_valid : integer;
attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
attribute stage2_valid : integer;
attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
begin
dbiterr <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gnuram_async_fifo.xpm_fifo_base_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base
port map (
almost_empty => almost_empty,
almost_full => almost_full,
data_valid => data_valid,
dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
overflow => overflow,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(8 downto 0) => rd_data_count(8 downto 0),
rd_en => rd_en,
rd_rst_busy => rd_rst_busy,
rst => rst,
sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\,
sleep => sleep,
underflow => underflow,
wr_ack => wr_ack,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ is
port (
sleep : in STD_LOGIC;
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_en : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 7 downto 0 );
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
overflow : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
prog_empty : out STD_LOGIC;
rd_data_count : out STD_LOGIC_VECTOR ( 8 downto 0 );
underflow : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
almost_empty : out STD_LOGIC;
data_valid : out STD_LOGIC;
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC
);
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0;
attribute CDC_SYNC_STAGES : integer;
attribute CDC_SYNC_STAGES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 2;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "0";
attribute ECC_MODE : string;
attribute ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "no_ecc";
attribute EN_ADV_FEATURE_ASYNC : string;
attribute EN_ADV_FEATURE_ASYNC of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "16'b0001111100011111";
attribute FIFO_MEMORY_TYPE : string;
attribute FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "auto";
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 256;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "xpm_fifo_async";
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 10;
attribute P_COMMON_CLOCK : integer;
attribute P_COMMON_CLOCK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0;
attribute P_ECC_MODE : integer;
attribute P_ECC_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0;
attribute P_FIFO_MEMORY_TYPE : integer;
attribute P_FIFO_MEMORY_TYPE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0;
attribute P_READ_MODE : integer;
attribute P_READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 1;
attribute P_WAKEUP_TIME : integer;
attribute P_WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 2;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 9;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 8;
attribute READ_MODE : string;
attribute READ_MODE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "fwft";
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "1F1F";
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 0;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 8;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is 9;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "TRUE";
attribute dont_touch : string;
attribute dont_touch of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ : entity is "true";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\ is
signal \<const0>\ : STD_LOGIC;
signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\ : STD_LOGIC;
attribute CASCADE_HEIGHT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute CDC_DEST_SYNC_FF : integer;
attribute CDC_DEST_SYNC_FF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
attribute COMMON_CLOCK : integer;
attribute COMMON_CLOCK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute DOUT_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "0";
attribute ECC_MODE_integer : integer;
attribute ECC_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute ENABLE_ECC : integer;
attribute ENABLE_ECC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute EN_ADV_FEATURE : string;
attribute EN_ADV_FEATURE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "16'b0001111100011111";
attribute EN_AE : string;
attribute EN_AE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_AF : string;
attribute EN_AF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_DVLD : string;
attribute EN_DVLD of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_OF : string;
attribute EN_OF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_PE : string;
attribute EN_PE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_PF : string;
attribute EN_PF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_RDC : string;
attribute EN_RDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_UF : string;
attribute EN_UF of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_WACK : string;
attribute EN_WACK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute EN_WDC : string;
attribute EN_WDC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute FG_EQ_ASYM_DOUT : string;
attribute FG_EQ_ASYM_DOUT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b0";
attribute FIFO_MEMORY_TYPE_integer : integer;
attribute FIFO_MEMORY_TYPE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute FIFO_MEM_TYPE : integer;
attribute FIFO_MEM_TYPE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute FIFO_READ_DEPTH : integer;
attribute FIFO_READ_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256;
attribute FIFO_READ_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute FIFO_SIZE : integer;
attribute FIFO_SIZE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2048;
attribute FIFO_WRITE_DEPTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 256;
attribute FULL_RESET_VALUE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute FULL_RST_VAL : string;
attribute FULL_RST_VAL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1'b1";
attribute KEEP_HIERARCHY : string;
attribute KEEP_HIERARCHY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "soft";
attribute PE_THRESH_ADJ : integer;
attribute PE_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute PE_THRESH_MAX : integer;
attribute PE_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251;
attribute PE_THRESH_MIN : integer;
attribute PE_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 5;
attribute PF_THRESH_ADJ : integer;
attribute PF_THRESH_ADJ of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute PF_THRESH_MAX : integer;
attribute PF_THRESH_MAX of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 251;
attribute PF_THRESH_MIN : integer;
attribute PF_THRESH_MIN of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 7;
attribute PROG_EMPTY_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
attribute PROG_FULL_THRESH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 10;
attribute RD_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9;
attribute RD_DC_WIDTH_EXT : integer;
attribute RD_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9;
attribute RD_LATENCY : integer;
attribute RD_LATENCY of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
attribute RD_MODE : integer;
attribute RD_MODE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute RD_PNTR_WIDTH : integer;
attribute RD_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute READ_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute READ_MODE_integer : integer;
attribute READ_MODE_integer of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute READ_MODE_LL : integer;
attribute READ_MODE_LL of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute RELATED_CLOCKS of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute REMOVE_WR_RD_PROT_LOGIC : integer;
attribute REMOVE_WR_RD_PROT_LOGIC of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute SIM_ASSERT_CHK of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute USE_ADV_FEATURES of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "1F1F";
attribute VERSION : integer;
attribute VERSION of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute WAKEUP_TIME of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute WIDTH_RATIO : integer;
attribute WIDTH_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
attribute WRITE_DATA_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute WR_DATA_COUNT_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9;
attribute WR_DC_WIDTH_EXT : integer;
attribute WR_DC_WIDTH_EXT of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 9;
attribute WR_DEPTH_LOG : integer;
attribute WR_DEPTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute WR_PNTR_WIDTH : integer;
attribute WR_PNTR_WIDTH of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 8;
attribute WR_RD_RATIO : integer;
attribute WR_RD_RATIO of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute WR_WIDTH_LOG : integer;
attribute WR_WIDTH_LOG of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3;
attribute XPM_MODULE of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is "TRUE";
attribute both_stages_valid : integer;
attribute both_stages_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 3;
attribute invalid : integer;
attribute invalid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 0;
attribute stage1_valid : integer;
attribute stage1_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 2;
attribute stage2_valid : integer;
attribute stage2_valid of \gnuram_async_fifo.xpm_fifo_base_inst\ : label is 1;
begin
dbiterr <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gnuram_async_fifo.xpm_fifo_base_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_base__parameterized0\
port map (
almost_empty => almost_empty,
almost_full => almost_full,
data_valid => data_valid,
dbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED\,
din(7 downto 0) => din(7 downto 0),
dout(7 downto 0) => dout(7 downto 0),
empty => empty,
full => full,
full_n => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
overflow => overflow,
prog_empty => prog_empty,
prog_full => prog_full,
rd_clk => rd_clk,
rd_data_count(8 downto 0) => rd_data_count(8 downto 0),
rd_en => rd_en,
rd_rst_busy => rd_rst_busy,
rst => rst,
sbiterr => \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED\,
sleep => sleep,
underflow => underflow,
wr_ack => wr_ack,
wr_clk => wr_clk,
wr_data_count(8 downto 0) => wr_data_count(8 downto 0),
wr_en => wr_en,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_async_fifo_fg is
port (
almost_full : out STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 7 downto 0 );
empty : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gen_wr_a.gen_word_narrow.mem_reg\ : out STD_LOGIC;
rst : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
IP2Bus_WrAck_transmit_enable : in STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
ext_spi_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
\s_axi4_rdata_i_reg[0]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\s_axi4_rdata_i_reg[7]_0\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[0]_0\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[1]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[1]_0\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[2]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[2]_0\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[3]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[3]_0\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[4]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[4]_0\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[5]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[5]_0\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[6]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[6]_0\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[7]_1\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[7]_2\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[7]_3\ : in STD_LOGIC;
p_2_in : in STD_LOGIC;
\s_axi4_rdata_i_reg[6]_1\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
spicr_9_lsb_to_spi_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_async_fifo_fg;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_async_fifo_fg is
signal Tx_FIFO_occ_Reversed : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \^dout\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal full : STD_LOGIC;
signal \s_axi4_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[4]_i_4_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[5]_i_2_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[6]_i_4_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[6]_i_5_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[6]_i_7_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[7]_i_6_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[7]_i_9_n_0\ : STD_LOGIC;
signal wr_rst_busy : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_14\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_25\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_26\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_27\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_28\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_29\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_30\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_31\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_32\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_33\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_36\ : STD_LOGIC;
signal \xpm_fifo_instance.xpm_fifo_async_inst_n_37\ : STD_LOGIC;
signal \NLW_xpm_fifo_instance.xpm_fifo_async_inst_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_xpm_fifo_instance.xpm_fifo_async_inst_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_xpm_fifo_instance.xpm_fifo_async_inst_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_xpm_fifo_instance.xpm_fifo_async_inst_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_xpm_fifo_instance.xpm_fifo_async_inst_rd_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_xpm_fifo_instance.xpm_fifo_async_inst_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_xpm_fifo_instance.xpm_fifo_async_inst_underflow_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axi4_rdata_i[1]_i_2\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[2]_i_2\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[3]_i_2\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[4]_i_4\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[6]_i_5\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[7]_i_9\ : label is "soft_lutpair74";
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 0;
attribute CDC_SYNC_STAGES : integer;
attribute CDC_SYNC_STAGES of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 2;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is "0";
attribute ECC_MODE : string;
attribute ECC_MODE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is "no_ecc";
attribute EN_ADV_FEATURE_ASYNC : string;
attribute EN_ADV_FEATURE_ASYNC of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is "16'b0001111100011111";
attribute FIFO_MEMORY_TYPE : string;
attribute FIFO_MEMORY_TYPE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is "auto";
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 0;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 256;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 1;
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 10;
attribute P_COMMON_CLOCK : integer;
attribute P_COMMON_CLOCK of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 0;
attribute P_ECC_MODE : integer;
attribute P_ECC_MODE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 0;
attribute P_FIFO_MEMORY_TYPE : integer;
attribute P_FIFO_MEMORY_TYPE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 0;
attribute P_READ_MODE : integer;
attribute P_READ_MODE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 1;
attribute P_WAKEUP_TIME : integer;
attribute P_WAKEUP_TIME of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 2;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 9;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 8;
attribute READ_MODE : string;
attribute READ_MODE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is "fwft";
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is "1F1F";
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 0;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 8;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is 9;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \xpm_fifo_instance.xpm_fifo_async_inst\ : label is "TRUE";
begin
dout(7 downto 0) <= \^dout\(7 downto 0);
\OTHER_RATIO_GENERATE.Serial_Dout_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^dout\(0),
I1 => spicr_9_lsb_to_spi_clk,
I2 => \^dout\(7),
O => \gen_wr_a.gen_word_narrow.mem_reg\
);
\s_axi4_rdata_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAEFFAEFFFFFFAE"
)
port map (
I0 => \s_axi4_rdata_i_reg[0]\,
I1 => \s_axi4_rdata_i_reg[7]\(0),
I2 => \s_axi4_rdata_i_reg[7]_0\,
I3 => \s_axi4_rdata_i_reg[0]_0\,
I4 => \s_axi4_rdata_i[6]_i_4_n_0\,
I5 => Tx_FIFO_occ_Reversed(0),
O => D(0)
);
\s_axi4_rdata_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \s_axi4_rdata_i_reg[7]\(1),
I1 => \s_axi4_rdata_i_reg[7]_0\,
I2 => \s_axi4_rdata_i[6]_i_4_n_0\,
I3 => \s_axi4_rdata_i[1]_i_2_n_0\,
I4 => \s_axi4_rdata_i_reg[1]\,
I5 => \s_axi4_rdata_i_reg[1]_0\,
O => D(1)
);
\s_axi4_rdata_i[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Tx_FIFO_occ_Reversed(0),
I1 => Tx_FIFO_occ_Reversed(1),
O => \s_axi4_rdata_i[1]_i_2_n_0\
);
\s_axi4_rdata_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \s_axi4_rdata_i_reg[7]\(2),
I1 => \s_axi4_rdata_i_reg[7]_0\,
I2 => \s_axi4_rdata_i[6]_i_4_n_0\,
I3 => \s_axi4_rdata_i[2]_i_2_n_0\,
I4 => \s_axi4_rdata_i_reg[2]\,
I5 => \s_axi4_rdata_i_reg[2]_0\,
O => D(2)
);
\s_axi4_rdata_i[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => Tx_FIFO_occ_Reversed(2),
I1 => Tx_FIFO_occ_Reversed(1),
I2 => Tx_FIFO_occ_Reversed(0),
O => \s_axi4_rdata_i[2]_i_2_n_0\
);
\s_axi4_rdata_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \s_axi4_rdata_i_reg[7]\(3),
I1 => \s_axi4_rdata_i_reg[7]_0\,
I2 => \s_axi4_rdata_i[6]_i_4_n_0\,
I3 => \s_axi4_rdata_i[3]_i_2_n_0\,
I4 => \s_axi4_rdata_i_reg[3]\,
I5 => \s_axi4_rdata_i_reg[3]_0\,
O => D(3)
);
\s_axi4_rdata_i[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"5556"
)
port map (
I0 => Tx_FIFO_occ_Reversed(3),
I1 => Tx_FIFO_occ_Reversed(0),
I2 => Tx_FIFO_occ_Reversed(1),
I3 => Tx_FIFO_occ_Reversed(2),
O => \s_axi4_rdata_i[3]_i_2_n_0\
);
\s_axi4_rdata_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAEFFAEFFFFFFAE"
)
port map (
I0 => \s_axi4_rdata_i_reg[4]\,
I1 => \s_axi4_rdata_i_reg[7]\(4),
I2 => \s_axi4_rdata_i_reg[7]_0\,
I3 => \s_axi4_rdata_i_reg[4]_0\,
I4 => \s_axi4_rdata_i[6]_i_4_n_0\,
I5 => \s_axi4_rdata_i[4]_i_4_n_0\,
O => D(4)
);
\s_axi4_rdata_i[4]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555556"
)
port map (
I0 => Tx_FIFO_occ_Reversed(4),
I1 => Tx_FIFO_occ_Reversed(2),
I2 => Tx_FIFO_occ_Reversed(1),
I3 => Tx_FIFO_occ_Reversed(0),
I4 => Tx_FIFO_occ_Reversed(3),
O => \s_axi4_rdata_i[4]_i_4_n_0\
);
\s_axi4_rdata_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \s_axi4_rdata_i_reg[7]\(5),
I1 => \s_axi4_rdata_i_reg[7]_0\,
I2 => \s_axi4_rdata_i[6]_i_4_n_0\,
I3 => \s_axi4_rdata_i[5]_i_2_n_0\,
I4 => \s_axi4_rdata_i_reg[5]\,
I5 => \s_axi4_rdata_i_reg[5]_0\,
O => D(5)
);
\s_axi4_rdata_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555556"
)
port map (
I0 => Tx_FIFO_occ_Reversed(5),
I1 => Tx_FIFO_occ_Reversed(3),
I2 => Tx_FIFO_occ_Reversed(0),
I3 => Tx_FIFO_occ_Reversed(1),
I4 => Tx_FIFO_occ_Reversed(2),
I5 => Tx_FIFO_occ_Reversed(4),
O => \s_axi4_rdata_i[5]_i_2_n_0\
);
\s_axi4_rdata_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAEFFAEFFFFFFAE"
)
port map (
I0 => \s_axi4_rdata_i_reg[6]\,
I1 => \s_axi4_rdata_i_reg[7]\(6),
I2 => \s_axi4_rdata_i_reg[7]_0\,
I3 => \s_axi4_rdata_i_reg[6]_0\,
I4 => \s_axi4_rdata_i[6]_i_4_n_0\,
I5 => \s_axi4_rdata_i[6]_i_5_n_0\,
O => D(6)
);
\s_axi4_rdata_i[6]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FB0000000000"
)
port map (
I0 => Tx_FIFO_occ_Reversed(7),
I1 => \s_axi4_rdata_i[7]_i_9_n_0\,
I2 => Tx_FIFO_occ_Reversed(8),
I3 => Bus_RNW_reg,
I4 => \s_axi4_rdata_i_reg[6]_1\,
I5 => p_2_in,
O => \s_axi4_rdata_i[6]_i_4_n_0\
);
\s_axi4_rdata_i[6]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Tx_FIFO_occ_Reversed(6),
I1 => \s_axi4_rdata_i[6]_i_7_n_0\,
O => \s_axi4_rdata_i[6]_i_5_n_0\
);
\s_axi4_rdata_i[6]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => Tx_FIFO_occ_Reversed(5),
I1 => Tx_FIFO_occ_Reversed(3),
I2 => Tx_FIFO_occ_Reversed(0),
I3 => Tx_FIFO_occ_Reversed(1),
I4 => Tx_FIFO_occ_Reversed(2),
I5 => Tx_FIFO_occ_Reversed(4),
O => \s_axi4_rdata_i[6]_i_7_n_0\
);
\s_axi4_rdata_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF22F2"
)
port map (
I0 => \s_axi4_rdata_i_reg[7]\(7),
I1 => \s_axi4_rdata_i_reg[7]_0\,
I2 => \s_axi4_rdata_i_reg[7]_1\,
I3 => \s_axi4_rdata_i_reg[7]_2\,
I4 => \s_axi4_rdata_i_reg[7]_3\,
I5 => \s_axi4_rdata_i[7]_i_6_n_0\,
O => D(7)
);
\s_axi4_rdata_i[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000202020000000"
)
port map (
I0 => p_2_in,
I1 => \s_axi4_rdata_i_reg[6]_1\,
I2 => Bus_RNW_reg,
I3 => Tx_FIFO_occ_Reversed(8),
I4 => \s_axi4_rdata_i[7]_i_9_n_0\,
I5 => Tx_FIFO_occ_Reversed(7),
O => \s_axi4_rdata_i[7]_i_6_n_0\
);
\s_axi4_rdata_i[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => Tx_FIFO_occ_Reversed(6),
I1 => \s_axi4_rdata_i[6]_i_7_n_0\,
O => \s_axi4_rdata_i[7]_i_9_n_0\
);
\xpm_fifo_instance.xpm_fifo_async_inst\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async__parameterized1\
port map (
almost_empty => \xpm_fifo_instance.xpm_fifo_async_inst_n_36\,
almost_full => almost_full,
data_valid => \xpm_fifo_instance.xpm_fifo_async_inst_n_37\,
dbiterr => \NLW_xpm_fifo_instance.xpm_fifo_async_inst_dbiterr_UNCONNECTED\,
din(7 downto 0) => s_axi4_wdata(7 downto 0),
dout(7 downto 0) => \^dout\(7 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
overflow => \NLW_xpm_fifo_instance.xpm_fifo_async_inst_overflow_UNCONNECTED\,
prog_empty => \NLW_xpm_fifo_instance.xpm_fifo_async_inst_prog_empty_UNCONNECTED\,
prog_full => \NLW_xpm_fifo_instance.xpm_fifo_async_inst_prog_full_UNCONNECTED\,
rd_clk => ext_spi_clk,
rd_data_count(8) => \xpm_fifo_instance.xpm_fifo_async_inst_n_25\,
rd_data_count(7) => \xpm_fifo_instance.xpm_fifo_async_inst_n_26\,
rd_data_count(6) => \xpm_fifo_instance.xpm_fifo_async_inst_n_27\,
rd_data_count(5) => \xpm_fifo_instance.xpm_fifo_async_inst_n_28\,
rd_data_count(4) => \xpm_fifo_instance.xpm_fifo_async_inst_n_29\,
rd_data_count(3) => \xpm_fifo_instance.xpm_fifo_async_inst_n_30\,
rd_data_count(2) => \xpm_fifo_instance.xpm_fifo_async_inst_n_31\,
rd_data_count(1) => \xpm_fifo_instance.xpm_fifo_async_inst_n_32\,
rd_data_count(0) => \xpm_fifo_instance.xpm_fifo_async_inst_n_33\,
rd_en => rd_en,
rd_rst_busy => \NLW_xpm_fifo_instance.xpm_fifo_async_inst_rd_rst_busy_UNCONNECTED\,
rst => rst,
sbiterr => \NLW_xpm_fifo_instance.xpm_fifo_async_inst_sbiterr_UNCONNECTED\,
sleep => '0',
underflow => \NLW_xpm_fifo_instance.xpm_fifo_async_inst_underflow_UNCONNECTED\,
wr_ack => \xpm_fifo_instance.xpm_fifo_async_inst_n_14\,
wr_clk => s_axi4_aclk,
wr_data_count(8 downto 0) => Tx_FIFO_occ_Reversed(8 downto 0),
wr_en => IP2Bus_WrAck_transmit_enable,
wr_rst_busy => wr_rst_busy
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_core_interface is
port (
spisel_d1_reg_to_axi_clk : out STD_LOGIC;
Tx_FIFO_Empty_SPISR_to_axi_clk : out STD_LOGIC;
spicr_0_loop_frm_axi_clk : out STD_LOGIC;
spicr_1_spe_frm_axi_clk : out STD_LOGIC;
spicr_2_mst_n_slv_frm_axi_clk : out STD_LOGIC;
spicr_3_cpol_frm_axi_clk : out STD_LOGIC;
spicr_4_cpha_frm_axi_clk : out STD_LOGIC;
spicr_7_ss_frm_axi_clk : out STD_LOGIC;
spicr_8_tr_inhibit_frm_axi_clk : out STD_LOGIC;
spicr_9_lsb_frm_axi_clk : out STD_LOGIC;
SPISSR_frm_axi_clk : out STD_LOGIC;
empty : out STD_LOGIC;
data_valid : out STD_LOGIC;
almost_full : out STD_LOGIC;
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
ss_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_o : out STD_LOGIC;
receive_ip2bus_error : out STD_LOGIC;
transmit_ip2bus_error : out STD_LOGIC;
sw_rst_cond_d1 : out STD_LOGIC;
irpt_wrack_d1 : out STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ : out STD_LOGIC;
p_1_in34_in : out STD_LOGIC;
p_1_in31_in : out STD_LOGIC;
p_1_in28_in : out STD_LOGIC;
p_1_in25_in : out STD_LOGIC;
p_1_in22_in : out STD_LOGIC;
p_1_in19_in : out STD_LOGIC;
p_1_in16_in : out STD_LOGIC;
p_1_in13_in : out STD_LOGIC;
irpt_rdack_d1 : out STD_LOGIC;
ip2Bus_WrAck_core_reg_d1 : out STD_LOGIC;
ip2Bus_WrAck_core_reg : out STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1 : out STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole_d1 : out STD_LOGIC;
ip2Bus_RdAck_core_reg : out STD_LOGIC;
\RESET_FLOPS[15].RST_FLOPS\ : out STD_LOGIC;
io1_o : out STD_LOGIC;
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
spicr_5_txfifo_rst_frm_axi_clk : out STD_LOGIC;
spicr_6_rxfifo_rst_frm_axi_clk : out STD_LOGIC;
p_0_in : out STD_LOGIC_VECTOR ( 0 to 0 );
Tx_FIFO_Full_int : out STD_LOGIC;
rx_fifo_empty_i : out STD_LOGIC;
intr2bus_wrack_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_fwft.gdvld_fwft.data_valid_fwft_reg\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
intr2bus_rdack_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
\ip_irpt_enable_reg_reg[8]\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
reset2ip_reset_int : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
rd_en : in STD_LOGIC;
IP2Bus_WrAck_transmit_enable : in STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
bus2ip_wrce_int : in STD_LOGIC_VECTOR ( 0 to 0 );
Transmit_ip2bus_error0 : in STD_LOGIC;
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]\ : in STD_LOGIC;
bus2ip_reset_ipif_inverted : in STD_LOGIC;
sw_rst_cond : in STD_LOGIC;
reset_trig0 : in STD_LOGIC;
irpt_wrack : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ : in STD_LOGIC;
interrupt_wrce_strb : in STD_LOGIC;
irpt_rdack : in STD_LOGIC;
intr2bus_rdack0 : in STD_LOGIC;
wr_ce_or_reduce_core_cmb : in STD_LOGIC;
ip2Bus_WrAck_core_reg0 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole_d1_reg_0 : in STD_LOGIC;
ip2Bus_WrAck_intr_reg_hole0 : in STD_LOGIC;
intr_controller_rd_ce_or_reduce : in STD_LOGIC;
ip2Bus_RdAck_intr_reg_hole0 : in STD_LOGIC;
rd_ce_or_reduce_core_cmb : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ : in STD_LOGIC;
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ : in STD_LOGIC;
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ : in STD_LOGIC;
ipif_glbl_irpt_enable_reg_reg : in STD_LOGIC;
ip2bus_error_int : in STD_LOGIC;
burst_tr_int : in STD_LOGIC;
s_axi4_rready : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi4_rdata_i_reg[31]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[0]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[7]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[1]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[2]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[3]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[4]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[5]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[6]\ : in STD_LOGIC;
\s_axi4_rdata_i_reg[7]_0\ : in STD_LOGIC;
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ : in STD_LOGIC;
p_4_in : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_2_in : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\s_axi4_rdata_i_reg[5]_0\ : in STD_LOGIC;
\ip_irpt_enable_reg_reg[8]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
io1_i_sync : in STD_LOGIC;
io0_i_sync : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_core_interface;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_core_interface is
signal CONTROL_REG_I_n_12 : STD_LOGIC;
signal Count_trigger : STD_LOGIC;
signal D0 : STD_LOGIC;
signal D01_out : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_10\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_11\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_12\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_13\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_17\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_18\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_2\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_20\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_21\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_24\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_25\ : STD_LOGIC;
signal \FIFO_EXISTS.CLK_CROSS_I_n_9\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_1\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_2\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6\ : STD_LOGIC;
signal \FIFO_EXISTS.TX_FIFO_II_n_18\ : STD_LOGIC;
signal \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_15\ : STD_LOGIC;
signal \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_16\ : STD_LOGIC;
signal \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_6\ : STD_LOGIC;
signal R : STD_LOGIC;
signal \^reset_flops[15].rst_flops\ : STD_LOGIC;
signal Ratio_Count : STD_LOGIC;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : STD_LOGIC;
signal Rx_FIFO_Full_Fifo : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1 : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_synced_i : STD_LOGIC;
signal Rx_FIFO_occ_Reversed : STD_LOGIC_VECTOR ( 8 downto 0 );
signal SOFT_RESET_I_n_3 : STD_LOGIC;
signal SPICR_2_MST_N_SLV_to_spi_clk : STD_LOGIC;
signal \^spissr_frm_axi_clk\ : STD_LOGIC;
signal TX_one_less_than_full : STD_LOGIC;
signal \^tx_fifo_empty_spisr_to_axi_clk\ : STD_LOGIC;
signal Tx_FIFO_Empty_intr : STD_LOGIC;
signal Tx_FIFO_Full_i : STD_LOGIC;
signal \^tx_fifo_full_int\ : STD_LOGIC;
signal almost_full_0 : STD_LOGIC;
signal bus2IP_Data_for_interrupt_core : STD_LOGIC_VECTOR ( 23 to 23 );
signal data_Exists_RcFIFO_int_d1 : STD_LOGIC;
signal data_Exists_RcFIFO_int_d10 : STD_LOGIC;
signal data_from_rx_fifo : STD_LOGIC_VECTOR ( 0 to 7 );
signal data_from_txfifo : STD_LOGIC_VECTOR ( 0 to 7 );
signal data_in : STD_LOGIC;
signal data_to_rx_fifo : STD_LOGIC_VECTOR ( 0 to 7 );
signal \^data_valid\ : STD_LOGIC;
signal \^empty\ : STD_LOGIC;
signal \^ip2bus_rdack_core_reg\ : STD_LOGIC;
signal ip2Bus_RdAck_core_reg0 : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole : STD_LOGIC;
signal \^ip2bus_wrack_core_reg\ : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole : STD_LOGIC;
signal \^p_1_in13_in\ : STD_LOGIC;
signal \^p_1_in16_in\ : STD_LOGIC;
signal \^p_1_in22_in\ : STD_LOGIC;
signal rc_FIFO_Full_d1 : STD_LOGIC;
signal read_ack_delay_1 : STD_LOGIC;
signal read_ack_delay_2 : STD_LOGIC;
signal read_ack_delay_3 : STD_LOGIC;
signal read_ack_delay_4 : STD_LOGIC;
signal read_ack_delay_5 : STD_LOGIC;
signal read_ack_delay_6 : STD_LOGIC;
signal read_ack_delay_7 : STD_LOGIC;
signal register_Data_slvsel_int : STD_LOGIC;
signal reset_TxFIFO_ptr_int : STD_LOGIC;
signal rst : STD_LOGIC;
signal rst_to_spi_int : STD_LOGIC;
signal \^rx_fifo_empty_i\ : STD_LOGIC;
signal \s_axi4_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[1]_i_4_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[2]_i_4_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[2]_i_6_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[3]_i_4_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[3]_i_6_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[4]_i_3_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[4]_i_5_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[4]_i_6_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[5]_i_4_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[5]_i_6_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[6]_i_3_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[7]_i_3_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[7]_i_4_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[7]_i_7_n_0\ : STD_LOGIC;
signal \s_axi4_rdata_i[7]_i_8_n_0\ : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
signal serial_dout_int : STD_LOGIC;
signal spiXfer_done_int : STD_LOGIC;
signal spiXfer_done_to_axi_1 : STD_LOGIC;
signal spiXfer_done_to_axi_d1 : STD_LOGIC;
signal \^spicr_0_loop_frm_axi_clk\ : STD_LOGIC;
signal spicr_0_loop_to_spi_clk : STD_LOGIC;
signal \^spicr_1_spe_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_2_mst_n_slv_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_3_cpol_frm_axi_clk\ : STD_LOGIC;
signal spicr_3_cpol_to_spi_clk : STD_LOGIC;
signal \^spicr_4_cpha_frm_axi_clk\ : STD_LOGIC;
signal spicr_4_cpha_to_spi_clk : STD_LOGIC;
signal \^spicr_5_txfifo_rst_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_6_rxfifo_rst_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_7_ss_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_8_tr_inhibit_frm_axi_clk\ : STD_LOGIC;
signal \^spicr_9_lsb_frm_axi_clk\ : STD_LOGIC;
signal spicr_9_lsb_to_spi_clk : STD_LOGIC;
signal spicr_bits_7_8_frm_axi_clk : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^spisel_d1_reg_to_axi_clk\ : STD_LOGIC;
signal transfer_start_d1 : STD_LOGIC;
signal tx_FIFO_Empty_d1 : STD_LOGIC;
signal tx_FIFO_Occpncy_MSB_d1 : STD_LOGIC;
signal tx_fifo_count : STD_LOGIC_VECTOR ( 0 to 0 );
signal tx_fifo_count_d1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal tx_fifo_count_d2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal tx_fifo_empty : STD_LOGIC;
signal tx_occ_msb : STD_LOGIC;
signal tx_occ_msb_1 : STD_LOGIC;
signal tx_occ_msb_4 : STD_LOGIC;
signal wrack : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_almost_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_rd_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_wr_ack_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_wr_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_FIFO_EXISTS.RX_FIFO_II_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CASCADE_HEIGHT : integer;
attribute CASCADE_HEIGHT of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute CDC_SYNC_STAGES : integer;
attribute CDC_SYNC_STAGES of \FIFO_EXISTS.RX_FIFO_II\ : label is 2;
attribute DOUT_RESET_VALUE : string;
attribute DOUT_RESET_VALUE of \FIFO_EXISTS.RX_FIFO_II\ : label is "0";
attribute ECC_MODE : string;
attribute ECC_MODE of \FIFO_EXISTS.RX_FIFO_II\ : label is "no_ecc";
attribute EN_ADV_FEATURE_ASYNC : string;
attribute EN_ADV_FEATURE_ASYNC of \FIFO_EXISTS.RX_FIFO_II\ : label is "16'b0001111100011111";
attribute FIFO_MEMORY_TYPE : string;
attribute FIFO_MEMORY_TYPE of \FIFO_EXISTS.RX_FIFO_II\ : label is "auto";
attribute FIFO_READ_LATENCY : integer;
attribute FIFO_READ_LATENCY of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute FIFO_WRITE_DEPTH : integer;
attribute FIFO_WRITE_DEPTH of \FIFO_EXISTS.RX_FIFO_II\ : label is 256;
attribute FULL_RESET_VALUE : integer;
attribute FULL_RESET_VALUE of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute PROG_EMPTY_THRESH : integer;
attribute PROG_EMPTY_THRESH of \FIFO_EXISTS.RX_FIFO_II\ : label is 10;
attribute PROG_FULL_THRESH : integer;
attribute PROG_FULL_THRESH of \FIFO_EXISTS.RX_FIFO_II\ : label is 10;
attribute P_COMMON_CLOCK : integer;
attribute P_COMMON_CLOCK of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute P_ECC_MODE : integer;
attribute P_ECC_MODE of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute P_FIFO_MEMORY_TYPE : integer;
attribute P_FIFO_MEMORY_TYPE of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute P_READ_MODE : integer;
attribute P_READ_MODE of \FIFO_EXISTS.RX_FIFO_II\ : label is 1;
attribute P_WAKEUP_TIME : integer;
attribute P_WAKEUP_TIME of \FIFO_EXISTS.RX_FIFO_II\ : label is 2;
attribute RD_DATA_COUNT_WIDTH : integer;
attribute RD_DATA_COUNT_WIDTH of \FIFO_EXISTS.RX_FIFO_II\ : label is 9;
attribute READ_DATA_WIDTH : integer;
attribute READ_DATA_WIDTH of \FIFO_EXISTS.RX_FIFO_II\ : label is 8;
attribute READ_MODE : string;
attribute READ_MODE of \FIFO_EXISTS.RX_FIFO_II\ : label is "fwft";
attribute RELATED_CLOCKS : integer;
attribute RELATED_CLOCKS of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute SIM_ASSERT_CHK : integer;
attribute SIM_ASSERT_CHK of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute USE_ADV_FEATURES : string;
attribute USE_ADV_FEATURES of \FIFO_EXISTS.RX_FIFO_II\ : label is "1f1f";
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \FIFO_EXISTS.RX_FIFO_II\ : label is 0;
attribute WRITE_DATA_WIDTH : integer;
attribute WRITE_DATA_WIDTH of \FIFO_EXISTS.RX_FIFO_II\ : label is 8;
attribute WR_DATA_COUNT_WIDTH : integer;
attribute WR_DATA_COUNT_WIDTH of \FIFO_EXISTS.RX_FIFO_II\ : label is 9;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \FIFO_EXISTS.RX_FIFO_II\ : label is "TRUE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axi4_rdata_i[2]_i_6\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[3]_i_6\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[4]_i_5\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[4]_i_6\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[5]_i_6\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[6]_i_3\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[7]_i_4\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \s_axi4_rdata_i[7]_i_7\ : label is "soft_lutpair95";
begin
\RESET_FLOPS[15].RST_FLOPS\ <= \^reset_flops[15].rst_flops\;
SPISSR_frm_axi_clk <= \^spissr_frm_axi_clk\;
Tx_FIFO_Empty_SPISR_to_axi_clk <= \^tx_fifo_empty_spisr_to_axi_clk\;
Tx_FIFO_Full_int <= \^tx_fifo_full_int\;
data_valid <= \^data_valid\;
empty <= \^empty\;
ip2Bus_RdAck_core_reg <= \^ip2bus_rdack_core_reg\;
ip2Bus_WrAck_core_reg <= \^ip2bus_wrack_core_reg\;
p_1_in13_in <= \^p_1_in13_in\;
p_1_in16_in <= \^p_1_in16_in\;
p_1_in22_in <= \^p_1_in22_in\;
rx_fifo_empty_i <= \^rx_fifo_empty_i\;
scndry_out <= \^scndry_out\;
spicr_0_loop_frm_axi_clk <= \^spicr_0_loop_frm_axi_clk\;
spicr_1_spe_frm_axi_clk <= \^spicr_1_spe_frm_axi_clk\;
spicr_2_mst_n_slv_frm_axi_clk <= \^spicr_2_mst_n_slv_frm_axi_clk\;
spicr_3_cpol_frm_axi_clk <= \^spicr_3_cpol_frm_axi_clk\;
spicr_4_cpha_frm_axi_clk <= \^spicr_4_cpha_frm_axi_clk\;
spicr_5_txfifo_rst_frm_axi_clk <= \^spicr_5_txfifo_rst_frm_axi_clk\;
spicr_6_rxfifo_rst_frm_axi_clk <= \^spicr_6_rxfifo_rst_frm_axi_clk\;
spicr_7_ss_frm_axi_clk <= \^spicr_7_ss_frm_axi_clk\;
spicr_8_tr_inhibit_frm_axi_clk <= \^spicr_8_tr_inhibit_frm_axi_clk\;
spicr_9_lsb_frm_axi_clk <= \^spicr_9_lsb_frm_axi_clk\;
spisel_d1_reg_to_axi_clk <= \^spisel_d1_reg_to_axi_clk\;
CONTROL_REG_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_cntrl_reg
port map (
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]_0\ => \CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_0\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]_1\ => \CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\,
\CONTROL_REG_5_9_GENERATE[7].SPICR_data_int_reg[7]_0\ => \^spicr_2_mst_n_slv_frm_axi_clk\,
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]_0\ => \CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]\,
D(0) => bus2IP_Data_for_interrupt_core(23),
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]\ => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\,
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0\ => \^rx_fifo_empty_i\,
bus2ip_wrce_int(0) => bus2ip_wrce_int(0),
data_Exists_RcFIFO_int_d1 => data_Exists_RcFIFO_int_d1,
\ip_irpt_enable_reg_reg[8]\ => \^spisel_d1_reg_to_axi_clk\,
p_1_in13_in => \^p_1_in13_in\,
reset2ip_reset_int => reset2ip_reset_int,
s_axi4_aclk => s_axi4_aclk,
s_axi4_wdata(7 downto 5) => s_axi4_wdata(9 downto 7),
s_axi4_wdata(4 downto 0) => s_axi4_wdata(4 downto 0),
\s_axi4_wdata[8]\ => CONTROL_REG_I_n_12,
spicr_0_loop_frm_axi_clk => \^spicr_0_loop_frm_axi_clk\,
spicr_1_spe_frm_axi_clk => \^spicr_1_spe_frm_axi_clk\,
spicr_3_cpol_frm_axi_clk => \^spicr_3_cpol_frm_axi_clk\,
spicr_4_cpha_frm_axi_clk => \^spicr_4_cpha_frm_axi_clk\,
spicr_6_rxfifo_rst_frm_axi_clk => \^spicr_6_rxfifo_rst_frm_axi_clk\,
spicr_7_ss_frm_axi_clk => \^spicr_7_ss_frm_axi_clk\,
spicr_8_tr_inhibit_frm_axi_clk => \^spicr_8_tr_inhibit_frm_axi_clk\,
spicr_9_lsb_frm_axi_clk => \^spicr_9_lsb_frm_axi_clk\,
spicr_bits_7_8_frm_axi_clk(1 downto 0) => spicr_bits_7_8_frm_axi_clk(1 downto 0)
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => read_ack_delay_6,
I1 => read_ack_delay_7,
O => ip2Bus_RdAck_core_reg0
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_RdAck_core_reg_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => ip2Bus_RdAck_core_reg0,
Q => \^ip2bus_rdack_core_reg\,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => wr_ce_or_reduce_core_cmb,
Q => ip2Bus_WrAck_core_reg_d1,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.ip2Bus_WrAck_core_reg_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => ip2Bus_WrAck_core_reg0,
Q => \^ip2bus_wrack_core_reg\,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => rd_ce_or_reduce_core_cmb,
Q => read_ack_delay_1,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_2_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => read_ack_delay_1,
Q => read_ack_delay_2,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_3_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => read_ack_delay_2,
Q => read_ack_delay_3,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_4_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => read_ack_delay_3,
Q => read_ack_delay_4,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_5_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => read_ack_delay_4,
Q => read_ack_delay_5,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_6_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => read_ack_delay_5,
Q => read_ack_delay_6,
R => reset2ip_reset_int
);
\ENHANCED_MD_WR_RD_ACK_GEN.read_ack_delay_7_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => read_ack_delay_6,
Q => read_ack_delay_7,
R => reset2ip_reset_int
);
\FIFO_EXISTS.CLK_CROSS_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cross_clk_sync_fifo_1
port map (
Count_trigger => Count_trigger,
D(0) => data_in,
D0 => D0,
D01_out => D01_out,
D_0 => D_0,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\ => \^reset_flops[15].rst_flops\,
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg_0\ => \^rx_fifo_empty_i\,
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]\ => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\,
IP2Bus_WrAck_transmit_enable => IP2Bus_WrAck_transmit_enable,
\LOGIC_GENERATION_FDR.SPICR_2_MST_N_SLV_AX2S_2_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_25\,
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_20\,
\LOGIC_GENERATION_FDR.SPICR_3_CPOL_AX2S_2_1\ => \FIFO_EXISTS.CLK_CROSS_I_n_21\,
\LOGIC_GENERATION_FDR.SPICR_7_SS_AX2S_2_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_24\,
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_11\,
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_1\ => \FIFO_EXISTS.CLK_CROSS_I_n_12\,
\LOGIC_GENERATION_FDR.SYNC_SPIXFER_DONE_S2AX_3_2\ => \FIFO_EXISTS.CLK_CROSS_I_n_13\,
\LOGIC_GENERATION_FDR.TX_EMPT_4_SPISR_S2AX_2_0\ => \^tx_fifo_empty_spisr_to_axi_clk\,
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_9\,
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_2\,
R => R,
Ratio_Count => Ratio_Count,
Rst_to_spi => rst_to_spi_int,
S(0) => \FIFO_EXISTS.CLK_CROSS_I_n_10\,
SPICR_2_MST_N_SLV_to_spi_clk => SPICR_2_MST_N_SLV_to_spi_clk,
SPISSR_frm_axi_clk => \^spissr_frm_axi_clk\,
\SS_O_reg[0]\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_16\,
Tx_FIFO_Empty_intr => Tx_FIFO_Empty_intr,
Tx_FIFO_Full_i => Tx_FIFO_Full_i,
Tx_FIFO_Full_int => \^tx_fifo_full_int\,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
empty => tx_fifo_empty,
ext_spi_clk => ext_spi_clk,
icount_out0_carry => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3\,
io0_i_sync => io0_i_sync,
io1_i_sync => io1_i_sync,
p_1_in16_in => \^p_1_in16_in\,
p_1_in22_in => \^p_1_in22_in\,
register_Data_slvsel_int => register_Data_slvsel_int,
reset2ip_reset_int => reset2ip_reset_int,
rst => rst,
s_axi4_aclk => s_axi4_aclk,
s_axi4_wdata(1) => s_axi4_wdata(7),
s_axi4_wdata(0) => s_axi4_wdata(5),
\s_axi4_wdata[5]\ => \FIFO_EXISTS.CLK_CROSS_I_n_18\,
\s_axi4_wdata[7]\ => \FIFO_EXISTS.CLK_CROSS_I_n_17\,
serial_dout_int => serial_dout_int,
spiXfer_done_to_axi_1 => spiXfer_done_to_axi_1,
spiXfer_done_to_axi_d1 => spiXfer_done_to_axi_d1,
spicr_0_loop_frm_axi_clk => \^spicr_0_loop_frm_axi_clk\,
spicr_0_loop_to_spi_clk => spicr_0_loop_to_spi_clk,
spicr_1_spe_frm_axi_clk => \^spicr_1_spe_frm_axi_clk\,
spicr_2_mst_n_slv_frm_axi_clk => \^spicr_2_mst_n_slv_frm_axi_clk\,
spicr_3_cpol_frm_axi_clk => \^spicr_3_cpol_frm_axi_clk\,
spicr_3_cpol_to_spi_clk => spicr_3_cpol_to_spi_clk,
spicr_4_cpha_frm_axi_clk => \^spicr_4_cpha_frm_axi_clk\,
spicr_4_cpha_to_spi_clk => spicr_4_cpha_to_spi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => \^spicr_6_rxfifo_rst_frm_axi_clk\,
spicr_7_ss_frm_axi_clk => \^spicr_7_ss_frm_axi_clk\,
spicr_8_tr_inhibit_frm_axi_clk => \^spicr_8_tr_inhibit_frm_axi_clk\,
spicr_9_lsb_frm_axi_clk => \^spicr_9_lsb_frm_axi_clk\,
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
spicr_bits_7_8_frm_axi_clk(1 downto 0) => spicr_bits_7_8_frm_axi_clk(1 downto 0),
spisel_d1_reg_to_axi_clk => \^spisel_d1_reg_to_axi_clk\,
transfer_start_d1 => transfer_start_d1,
transfer_start_reg => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_6\,
tx_fifo_count_d2(7 downto 0) => tx_fifo_count_d2(7 downto 0),
tx_occ_msb => tx_occ_msb,
tx_occ_msb_4 => tx_occ_msb_4
);
\FIFO_EXISTS.FIFO_IF_MODULE_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_fifo_ifmodule
port map (
Bus_RNW_reg => Bus_RNW_reg,
Receive_ip2bus_error_reg_0 => \^rx_fifo_empty_i\,
Rx_FIFO_Full_Fifo_d1_synced_i => Rx_FIFO_Full_Fifo_d1_synced_i,
Transmit_ip2bus_error0 => Transmit_ip2bus_error0,
Tx_FIFO_Empty_intr => Tx_FIFO_Empty_intr,
p_4_in => p_4_in,
prmry_in => \^empty\,
rc_FIFO_Full_d1 => rc_FIFO_Full_d1,
receive_ip2bus_error => receive_ip2bus_error,
reset2ip_reset_int => reset2ip_reset_int,
s_axi4_aclk => s_axi4_aclk,
transmit_ip2bus_error => transmit_ip2bus_error,
tx_FIFO_Empty_d1 => tx_FIFO_Empty_d1,
tx_FIFO_Occpncy_MSB_d1 => tx_FIFO_Occpncy_MSB_d1,
tx_occ_msb => tx_occ_msb
);
\FIFO_EXISTS.RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
Rx_FIFO_Full_Fifo => Rx_FIFO_Full_Fifo,
almost_full => almost_full_0,
ext_spi_clk => ext_spi_clk,
prmry_in => \^empty\,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
\FIFO_EXISTS.RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
Rx_FIFO_Full_Fifo_d1_synced_i => Rx_FIFO_Full_Fifo_d1_synced_i,
empty => \^empty\,
prmry_in => Rx_FIFO_Full_Fifo_d1,
s_axi4_aclk => s_axi4_aclk,
scndry_out => \^scndry_out\
);
\FIFO_EXISTS.RX_FIFO_II\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xpm_fifo_async
port map (
almost_empty => \NLW_FIFO_EXISTS.RX_FIFO_II_almost_empty_UNCONNECTED\,
almost_full => almost_full_0,
data_valid => \^data_valid\,
dbiterr => \NLW_FIFO_EXISTS.RX_FIFO_II_dbiterr_UNCONNECTED\,
din(7) => data_to_rx_fifo(0),
din(6) => data_to_rx_fifo(1),
din(5) => data_to_rx_fifo(2),
din(4) => data_to_rx_fifo(3),
din(3) => data_to_rx_fifo(4),
din(2) => data_to_rx_fifo(5),
din(1) => data_to_rx_fifo(6),
din(0) => data_to_rx_fifo(7),
dout(7) => data_from_rx_fifo(0),
dout(6) => data_from_rx_fifo(1),
dout(5) => data_from_rx_fifo(2),
dout(4) => data_from_rx_fifo(3),
dout(3) => data_from_rx_fifo(4),
dout(2) => data_from_rx_fifo(5),
dout(1) => data_from_rx_fifo(6),
dout(0) => data_from_rx_fifo(7),
empty => \^empty\,
full => \NLW_FIFO_EXISTS.RX_FIFO_II_full_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
overflow => \NLW_FIFO_EXISTS.RX_FIFO_II_overflow_UNCONNECTED\,
prog_empty => \NLW_FIFO_EXISTS.RX_FIFO_II_prog_empty_UNCONNECTED\,
prog_full => \NLW_FIFO_EXISTS.RX_FIFO_II_prog_full_UNCONNECTED\,
rd_clk => s_axi4_aclk,
rd_data_count(8 downto 0) => Rx_FIFO_occ_Reversed(8 downto 0),
rd_en => rd_en,
rd_rst_busy => \NLW_FIFO_EXISTS.RX_FIFO_II_rd_rst_busy_UNCONNECTED\,
rst => rst,
sbiterr => \NLW_FIFO_EXISTS.RX_FIFO_II_sbiterr_UNCONNECTED\,
sleep => '0',
underflow => \NLW_FIFO_EXISTS.RX_FIFO_II_underflow_UNCONNECTED\,
wr_ack => \NLW_FIFO_EXISTS.RX_FIFO_II_wr_ack_UNCONNECTED\,
wr_clk => ext_spi_clk,
wr_data_count(8 downto 0) => \NLW_FIFO_EXISTS.RX_FIFO_II_wr_data_count_UNCONNECTED\(8 downto 0),
wr_en => spiXfer_done_int,
wr_rst_busy => \NLW_FIFO_EXISTS.RX_FIFO_II_wr_rst_busy_UNCONNECTED\
);
\FIFO_EXISTS.RX_FULL_EMP_MD_0_GEN.rx_fifo_empty_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \FIFO_EXISTS.CLK_CROSS_I_n_12\,
Q => \^rx_fifo_empty_i\,
R => '0'
);
\FIFO_EXISTS.Rx_FIFO_Full_Fifo_d1_reg\: unisim.vcomponents.FDRE
port map (
C => ext_spi_clk,
CE => '1',
D => Rx_FIFO_Full_Fifo,
Q => Rx_FIFO_Full_Fifo_d1,
R => rst_to_spi_int
);
\FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f
port map (
IP2Bus_WrAck_transmit_enable => IP2Bus_WrAck_transmit_enable,
S(0) => \FIFO_EXISTS.CLK_CROSS_I_n_10\,
TX_one_less_than_full => TX_one_less_than_full,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
\icount_out_reg[0]_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_11\,
\icount_out_reg[1]_0\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3\,
\icount_out_reg[2]_0\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_2\,
\icount_out_reg[3]_0\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_1\,
\icount_out_reg[4]_0\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5\,
\icount_out_reg[5]_0\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4\,
\icount_out_reg[6]_0\ => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6\,
\icount_out_reg[7]_0\ => \^reset_flops[15].rst_flops\,
\icount_out_reg[7]_1\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
s_axi4_aclk => s_axi4_aclk,
tx_fifo_count(0) => tx_fifo_count(0),
tx_occ_msb_1 => tx_occ_msb_1
);
\FIFO_EXISTS.TX_FIFO_II\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_async_fifo_fg
port map (
Bus_RNW_reg => Bus_RNW_reg,
D(7 downto 0) => D(7 downto 0),
IP2Bus_WrAck_transmit_enable => IP2Bus_WrAck_transmit_enable,
almost_full => almost_full,
dout(7) => data_from_txfifo(0),
dout(6) => data_from_txfifo(1),
dout(5) => data_from_txfifo(2),
dout(4) => data_from_txfifo(3),
dout(3) => data_from_txfifo(4),
dout(2) => data_from_txfifo(5),
dout(1) => data_from_txfifo(6),
dout(0) => data_from_txfifo(7),
empty => tx_fifo_empty,
ext_spi_clk => ext_spi_clk,
\gen_wr_a.gen_word_narrow.mem_reg\ => \FIFO_EXISTS.TX_FIFO_II_n_18\,
p_2_in => p_2_in,
rd_en => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_15\,
rst => reset_TxFIFO_ptr_int,
s_axi4_aclk => s_axi4_aclk,
\s_axi4_rdata_i_reg[0]\ => \s_axi4_rdata_i_reg[0]\,
\s_axi4_rdata_i_reg[0]_0\ => \s_axi4_rdata_i[0]_i_3_n_0\,
\s_axi4_rdata_i_reg[1]\ => \s_axi4_rdata_i_reg[1]\,
\s_axi4_rdata_i_reg[1]_0\ => \s_axi4_rdata_i[1]_i_4_n_0\,
\s_axi4_rdata_i_reg[2]\ => \s_axi4_rdata_i_reg[2]\,
\s_axi4_rdata_i_reg[2]_0\ => \s_axi4_rdata_i[2]_i_4_n_0\,
\s_axi4_rdata_i_reg[3]\ => \s_axi4_rdata_i_reg[3]\,
\s_axi4_rdata_i_reg[3]_0\ => \s_axi4_rdata_i[3]_i_4_n_0\,
\s_axi4_rdata_i_reg[4]\ => \s_axi4_rdata_i_reg[4]\,
\s_axi4_rdata_i_reg[4]_0\ => \s_axi4_rdata_i[4]_i_3_n_0\,
\s_axi4_rdata_i_reg[5]\ => \s_axi4_rdata_i_reg[5]\,
\s_axi4_rdata_i_reg[5]_0\ => \s_axi4_rdata_i[5]_i_4_n_0\,
\s_axi4_rdata_i_reg[6]\ => \s_axi4_rdata_i_reg[6]\,
\s_axi4_rdata_i_reg[6]_0\ => \s_axi4_rdata_i[6]_i_3_n_0\,
\s_axi4_rdata_i_reg[6]_1\ => \^tx_fifo_empty_spisr_to_axi_clk\,
\s_axi4_rdata_i_reg[7]\(7) => data_from_rx_fifo(0),
\s_axi4_rdata_i_reg[7]\(6) => data_from_rx_fifo(1),
\s_axi4_rdata_i_reg[7]\(5) => data_from_rx_fifo(2),
\s_axi4_rdata_i_reg[7]\(4) => data_from_rx_fifo(3),
\s_axi4_rdata_i_reg[7]\(3) => data_from_rx_fifo(4),
\s_axi4_rdata_i_reg[7]\(2) => data_from_rx_fifo(5),
\s_axi4_rdata_i_reg[7]\(1) => data_from_rx_fifo(6),
\s_axi4_rdata_i_reg[7]\(0) => data_from_rx_fifo(7),
\s_axi4_rdata_i_reg[7]_0\ => \s_axi4_rdata_i_reg[7]\,
\s_axi4_rdata_i_reg[7]_1\ => \s_axi4_rdata_i[7]_i_3_n_0\,
\s_axi4_rdata_i_reg[7]_2\ => \s_axi4_rdata_i[7]_i_4_n_0\,
\s_axi4_rdata_i_reg[7]_3\ => \s_axi4_rdata_i_reg[7]_0\,
s_axi4_wdata(7 downto 0) => s_axi4_wdata(7 downto 0),
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => SOFT_RESET_I_n_3,
Q => Tx_FIFO_Full_i,
R => '0'
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_int_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \FIFO_EXISTS.CLK_CROSS_I_n_13\,
Q => \^tx_fifo_full_int\,
R => '0'
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.spiXfer_done_to_axi_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => spiXfer_done_to_axi_1,
Q => spiXfer_done_to_axi_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count(0),
Q => tx_fifo_count_d1(0),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_3\,
Q => tx_fifo_count_d1(1),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_2\,
Q => tx_fifo_count_d1(2),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_1\,
Q => tx_fifo_count_d1(3),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_5\,
Q => tx_fifo_count_d1(4),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_4\,
Q => tx_fifo_count_d1(5),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => \FIFO_EXISTS.TX_FIFO_EMPTY_CNTR_I_n_6\,
Q => tx_fifo_count_d1(6),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_occ_msb_1,
Q => tx_fifo_count_d1(7),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d1(0),
Q => tx_fifo_count_d2(0),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d1(1),
Q => tx_fifo_count_d2(1),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d1(2),
Q => tx_fifo_count_d2(2),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d1(3),
Q => tx_fifo_count_d2(3),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d1(4),
Q => tx_fifo_count_d2(4),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d1(5),
Q => tx_fifo_count_d2(5),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d1(6),
Q => tx_fifo_count_d2(6),
R => reset2ip_reset_int
);
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.tx_fifo_count_d2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d1(7),
Q => tx_fifo_count_d2(7),
R => reset2ip_reset_int
);
\FIFO_EXISTS.data_Exists_RcFIFO_int_d1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^rx_fifo_empty_i\,
O => data_Exists_RcFIFO_int_d10
);
\FIFO_EXISTS.data_Exists_RcFIFO_int_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => data_Exists_RcFIFO_int_d10,
Q => data_Exists_RcFIFO_int_d1,
R => reset2ip_reset_int
);
\FIFO_EXISTS.tx_occ_msb_4_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => tx_fifo_count_d2(7),
Q => tx_occ_msb_4,
R => reset2ip_reset_int
);
INTERRUPT_CONTROL_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_interrupt_control
port map (
D(0) => bus2IP_Data_for_interrupt_core(23),
E(0) => E(0),
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_1\ => \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]_0\ => \GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]_0\ => \GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\,
\GEN_IP_IRPT_STATUS_REG[5].GEN_REG_STATUS.ip_irpt_status_reg_reg[5]_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_18\,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]_0\ => \GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\,
\GEN_IP_IRPT_STATUS_REG[7].GEN_REG_STATUS.ip_irpt_status_reg_reg[7]_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_17\,
\GEN_IP_IRPT_STATUS_REG[8].GEN_REG_STATUS.ip_irpt_status_reg_reg[8]_0\ => CONTROL_REG_I_n_12,
Q(0) => Q(0),
Tx_FIFO_Empty_SPISR_to_axi_clk => \^tx_fifo_empty_spisr_to_axi_clk\,
Tx_FIFO_Empty_intr => Tx_FIFO_Empty_intr,
burst_tr_int => burst_tr_int,
data_valid => \^data_valid\,
empty => \^empty\,
\gen_fwft.gdvld_fwft.data_valid_fwft_reg\ => \gen_fwft.gdvld_fwft.data_valid_fwft_reg\,
interrupt_wrce_strb => interrupt_wrce_strb,
intr2bus_rdack0 => intr2bus_rdack0,
intr2bus_rdack_reg_0 => intr2bus_rdack_reg,
intr2bus_wrack_reg_0 => intr2bus_wrack_reg,
ip2Bus_RdAck_core_reg => \^ip2bus_rdack_core_reg\,
ip2Bus_RdAck_intr_reg_hole => ip2Bus_RdAck_intr_reg_hole,
ip2Bus_WrAck_core_reg => \^ip2bus_wrack_core_reg\,
ip2Bus_WrAck_intr_reg_hole => ip2Bus_WrAck_intr_reg_hole,
ip2bus_error_int => ip2bus_error_int,
ip2intc_irpt => ip2intc_irpt,
\ip_irpt_enable_reg_reg[8]_0\(8 downto 0) => \ip_irpt_enable_reg_reg[8]\(8 downto 0),
\ip_irpt_enable_reg_reg[8]_1\(0) => \ip_irpt_enable_reg_reg[8]_0\(0),
ipif_glbl_irpt_enable_reg_reg_0 => ipif_glbl_irpt_enable_reg_reg,
irpt_rdack => irpt_rdack,
irpt_rdack_d1 => irpt_rdack_d1,
irpt_wrack => irpt_wrack,
irpt_wrack_d1 => irpt_wrack_d1,
p_0_in(0) => p_0_in(0),
p_1_in13_in => \^p_1_in13_in\,
p_1_in16_in => \^p_1_in16_in\,
p_1_in19_in => p_1_in19_in,
p_1_in22_in => \^p_1_in22_in\,
p_1_in25_in => p_1_in25_in,
p_1_in28_in => p_1_in28_in,
p_1_in31_in => p_1_in31_in,
p_1_in34_in => p_1_in34_in,
rc_FIFO_Full_d1 => rc_FIFO_Full_d1,
reset2ip_reset_int => reset2ip_reset_int,
s_axi4_aclk => s_axi4_aclk,
\s_axi4_rdata_i_reg[31]\ => \s_axi4_rdata_i_reg[31]\,
s_axi4_rready => s_axi4_rready,
s_axi4_wdata(7 downto 0) => s_axi4_wdata(7 downto 0),
scndry_out => \^scndry_out\,
tx_FIFO_Empty_d1 => tx_FIFO_Empty_d1,
tx_FIFO_Occpncy_MSB_d1 => tx_FIFO_Occpncy_MSB_d1,
tx_occ_msb_4 => tx_occ_msb_4,
wrack => wrack
);
\LOGIC_FOR_MD_0_GEN.SPI_MODULE_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_mode_0_module
port map (
Count_trigger => Count_trigger,
D(0) => data_in,
D0 => D0,
D01_out => D01_out,
D_0 => D_0,
\LOGIC_GENERATION_FDR.SPICR_0_LOOP_AX2S_2\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_16\,
\LOGIC_GENERATION_FDR.drr_Overrun_int_cdc_from_spi_int_2_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_9\,
\LOGIC_GENERATION_FDR.spiXfer_done_cdc_from_spi_int_2_reg\ => \FIFO_EXISTS.CLK_CROSS_I_n_2\,
\OTHER_RATIO_GENERATE.Serial_Dout_reg_0\ => \FIFO_EXISTS.TX_FIFO_II_n_18\,
\OTHER_RATIO_GENERATE.sck_o_int_reg_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_21\,
R => R,
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_0\ => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_6\,
\RX_DATA_GEN_OTHER_SCK_RATIOS.FIFO_PRESENT_GEN.SPIXfer_done_int_reg_1\ => \FIFO_EXISTS.CLK_CROSS_I_n_20\,
Ratio_Count => Ratio_Count,
Rst_to_spi => rst_to_spi_int,
SPICR_2_MST_N_SLV_to_spi_clk => SPICR_2_MST_N_SLV_to_spi_clk,
\SS_O_reg[0]_0\ => \FIFO_EXISTS.CLK_CROSS_I_n_24\,
almost_full => almost_full_0,
din(7) => data_to_rx_fifo(0),
din(6) => data_to_rx_fifo(1),
din(5) => data_to_rx_fifo(2),
din(4) => data_to_rx_fifo(3),
din(3) => data_to_rx_fifo(4),
din(2) => data_to_rx_fifo(5),
din(1) => data_to_rx_fifo(6),
din(0) => data_to_rx_fifo(7),
dout(7) => data_from_txfifo(0),
dout(6) => data_from_txfifo(1),
dout(5) => data_from_txfifo(2),
dout(4) => data_from_txfifo(3),
dout(3) => data_from_txfifo(4),
dout(2) => data_from_txfifo(5),
dout(1) => data_from_txfifo(6),
dout(0) => data_from_txfifo(7),
empty => tx_fifo_empty,
ext_spi_clk => ext_spi_clk,
io0_t => io0_t,
io1_o => io1_o,
io1_t => io1_t,
rd_en => \LOGIC_FOR_MD_0_GEN.SPI_MODULE_I_n_15\,
register_Data_slvsel_int => register_Data_slvsel_int,
sck_o => sck_o,
sck_t => sck_t,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain,
serial_dout_int => serial_dout_int,
spiXfer_done_int => spiXfer_done_int,
spicr_0_loop_to_spi_clk => spicr_0_loop_to_spi_clk,
spicr_3_cpol_to_spi_clk => spicr_3_cpol_to_spi_clk,
spicr_4_cpha_to_spi_clk => spicr_4_cpha_to_spi_clk,
spicr_9_lsb_to_spi_clk => spicr_9_lsb_to_spi_clk,
ss_o(0) => ss_o(0),
ss_t => ss_t,
transfer_start_d1 => transfer_start_d1,
transfer_start_reg_0 => \FIFO_EXISTS.CLK_CROSS_I_n_25\
);
RESET_SYNC_AXI_SPI_CLK_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_module
port map (
Rst_to_spi => rst_to_spi_int,
ext_spi_clk => ext_spi_clk,
reset2ip_reset_int => reset2ip_reset_int
);
SOFT_RESET_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_soft_reset
port map (
Bus2IP_Reset_i_reg => SOFT_RESET_I_n_3,
\FIFO_EXISTS.TX_FULL_EMP_INTR_MD_0_GEN.Tx_FIFO_Full_i_reg\ => \^spicr_5_txfifo_rst_frm_axi_clk\,
\RESET_FLOPS[15].RST_FLOPS_0\ => \^reset_flops[15].rst_flops\,
TX_one_less_than_full => TX_one_less_than_full,
Tx_FIFO_Full_i => Tx_FIFO_Full_i,
Tx_FIFO_Full_int => \^tx_fifo_full_int\,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
reset_trig0 => reset_trig0,
rst => reset_TxFIFO_ptr_int,
s_axi4_aclk => s_axi4_aclk,
sw_rst_cond => sw_rst_cond,
sw_rst_cond_d1 => sw_rst_cond_d1,
wrack => wrack
);
\STATUS_REG_MODE_0_GEN.STATUS_SLAVE_SEL_REG_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_status_slave_sel_reg
port map (
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]_0\ => \SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\,
SPISSR_frm_axi_clk => \^spissr_frm_axi_clk\,
reset2ip_reset_int => reset2ip_reset_int,
s_axi4_aclk => s_axi4_aclk
);
ip2Bus_RdAck_intr_reg_hole_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => intr_controller_rd_ce_or_reduce,
Q => ip2Bus_RdAck_intr_reg_hole_d1,
R => reset2ip_reset_int
);
ip2Bus_RdAck_intr_reg_hole_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => ip2Bus_RdAck_intr_reg_hole0,
Q => ip2Bus_RdAck_intr_reg_hole,
R => reset2ip_reset_int
);
ip2Bus_WrAck_intr_reg_hole_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => ip2Bus_WrAck_intr_reg_hole_d1_reg_0,
Q => ip2Bus_WrAck_intr_reg_hole_d1,
R => reset2ip_reset_int
);
ip2Bus_WrAck_intr_reg_hole_reg: unisim.vcomponents.FDRE
port map (
C => s_axi4_aclk,
CE => '1',
D => ip2Bus_WrAck_intr_reg_hole0,
Q => ip2Bus_WrAck_intr_reg_hole,
R => reset2ip_reset_int
);
\s_axi4_rdata_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => \s_axi4_rdata_i_reg[5]_0\,
I1 => Rx_FIFO_occ_Reversed(8),
I2 => Rx_FIFO_occ_Reversed(6),
I3 => \s_axi4_rdata_i[7]_i_8_n_0\,
I4 => Rx_FIFO_occ_Reversed(7),
I5 => Rx_FIFO_occ_Reversed(0),
O => \s_axi4_rdata_i[0]_i_3_n_0\
);
\s_axi4_rdata_i[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000002000"
)
port map (
I0 => p_1_in,
I1 => \^empty\,
I2 => Bus_RNW_reg,
I3 => \s_axi4_rdata_i[4]_i_5_n_0\,
I4 => Rx_FIFO_occ_Reversed(1),
I5 => Rx_FIFO_occ_Reversed(0),
O => \s_axi4_rdata_i[1]_i_4_n_0\
);
\s_axi4_rdata_i[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000002000"
)
port map (
I0 => p_1_in,
I1 => \^empty\,
I2 => Bus_RNW_reg,
I3 => \s_axi4_rdata_i[4]_i_5_n_0\,
I4 => \s_axi4_rdata_i[2]_i_6_n_0\,
I5 => Rx_FIFO_occ_Reversed(2),
O => \s_axi4_rdata_i[2]_i_4_n_0\
);
\s_axi4_rdata_i[2]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Rx_FIFO_occ_Reversed(0),
I1 => Rx_FIFO_occ_Reversed(1),
O => \s_axi4_rdata_i[2]_i_6_n_0\
);
\s_axi4_rdata_i[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000002000"
)
port map (
I0 => p_1_in,
I1 => \^empty\,
I2 => Bus_RNW_reg,
I3 => \s_axi4_rdata_i[4]_i_5_n_0\,
I4 => \s_axi4_rdata_i[3]_i_6_n_0\,
I5 => Rx_FIFO_occ_Reversed(3),
O => \s_axi4_rdata_i[3]_i_4_n_0\
);
\s_axi4_rdata_i[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Rx_FIFO_occ_Reversed(2),
I1 => Rx_FIFO_occ_Reversed(1),
I2 => Rx_FIFO_occ_Reversed(0),
O => \s_axi4_rdata_i[3]_i_6_n_0\
);
\s_axi4_rdata_i[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000002000"
)
port map (
I0 => p_1_in,
I1 => \^empty\,
I2 => Bus_RNW_reg,
I3 => \s_axi4_rdata_i[4]_i_5_n_0\,
I4 => \s_axi4_rdata_i[4]_i_6_n_0\,
I5 => Rx_FIFO_occ_Reversed(4),
O => \s_axi4_rdata_i[4]_i_3_n_0\
);
\s_axi4_rdata_i[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => Rx_FIFO_occ_Reversed(8),
I1 => Rx_FIFO_occ_Reversed(6),
I2 => \s_axi4_rdata_i[7]_i_8_n_0\,
I3 => Rx_FIFO_occ_Reversed(7),
O => \s_axi4_rdata_i[4]_i_5_n_0\
);
\s_axi4_rdata_i[4]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => Rx_FIFO_occ_Reversed(3),
I1 => Rx_FIFO_occ_Reversed(0),
I2 => Rx_FIFO_occ_Reversed(1),
I3 => Rx_FIFO_occ_Reversed(2),
O => \s_axi4_rdata_i[4]_i_6_n_0\
);
\s_axi4_rdata_i[5]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555000000005554"
)
port map (
I0 => \s_axi4_rdata_i_reg[5]_0\,
I1 => Rx_FIFO_occ_Reversed(8),
I2 => Rx_FIFO_occ_Reversed(6),
I3 => Rx_FIFO_occ_Reversed(7),
I4 => \s_axi4_rdata_i[5]_i_6_n_0\,
I5 => Rx_FIFO_occ_Reversed(5),
O => \s_axi4_rdata_i[5]_i_4_n_0\
);
\s_axi4_rdata_i[5]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => Rx_FIFO_occ_Reversed(4),
I1 => Rx_FIFO_occ_Reversed(2),
I2 => Rx_FIFO_occ_Reversed(1),
I3 => Rx_FIFO_occ_Reversed(0),
I4 => Rx_FIFO_occ_Reversed(3),
O => \s_axi4_rdata_i[5]_i_6_n_0\
);
\s_axi4_rdata_i[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"55000054"
)
port map (
I0 => \s_axi4_rdata_i_reg[5]_0\,
I1 => Rx_FIFO_occ_Reversed(8),
I2 => Rx_FIFO_occ_Reversed(7),
I3 => \s_axi4_rdata_i[7]_i_8_n_0\,
I4 => Rx_FIFO_occ_Reversed(6),
O => \s_axi4_rdata_i[6]_i_3_n_0\
);
\s_axi4_rdata_i[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FB0000000000"
)
port map (
I0 => Rx_FIFO_occ_Reversed(7),
I1 => \s_axi4_rdata_i[7]_i_7_n_0\,
I2 => Rx_FIFO_occ_Reversed(8),
I3 => Bus_RNW_reg,
I4 => \^empty\,
I5 => p_1_in,
O => \s_axi4_rdata_i[7]_i_3_n_0\
);
\s_axi4_rdata_i[7]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"56"
)
port map (
I0 => Rx_FIFO_occ_Reversed(7),
I1 => \s_axi4_rdata_i[7]_i_8_n_0\,
I2 => Rx_FIFO_occ_Reversed(6),
O => \s_axi4_rdata_i[7]_i_4_n_0\
);
\s_axi4_rdata_i[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => Rx_FIFO_occ_Reversed(6),
I1 => \s_axi4_rdata_i[7]_i_8_n_0\,
O => \s_axi4_rdata_i[7]_i_7_n_0\
);
\s_axi4_rdata_i[7]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => Rx_FIFO_occ_Reversed(5),
I1 => Rx_FIFO_occ_Reversed(3),
I2 => Rx_FIFO_occ_Reversed(0),
I3 => Rx_FIFO_occ_Reversed(1),
I4 => Rx_FIFO_occ_Reversed(2),
I5 => Rx_FIFO_occ_Reversed(4),
O => \s_axi4_rdata_i[7]_i_8_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi_top is
port (
s_axi4_rlast : out STD_LOGIC;
sck_t : out STD_LOGIC;
io0_t : out STD_LOGIC;
ss_t : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_o : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi4_awready : out STD_LOGIC;
s_axi4_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_arready : out STD_LOGIC;
s_axi4_rdata : out STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi4_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_wready : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
io1_o : out STD_LOGIC;
s_axi4_bvalid : out STD_LOGIC;
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi4_arvalid : in STD_LOGIC;
s_axi4_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi4_rready : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
ext_spi_clk : in STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 10 downto 0 );
io0_i : in STD_LOGIC;
io1_i : in STD_LOGIC;
s_axi4_bready : in STD_LOGIC;
s_axi4_awvalid : in STD_LOGIC;
s_axi4_wvalid : in STD_LOGIC;
s_axi4_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_aresetn : in STD_LOGIC;
s_axi4_wstrb : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi_top is
signal \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/interrupt_wrce_strb\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/intr2bus_rdack0\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_rdack\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_rdack_d1\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_wrack\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/irpt_wrack_d1\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in\ : STD_LOGIC_VECTOR ( 31 to 31 );
signal \INTERRUPT_CONTROL_I/p_0_in0_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in11_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in14_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in17_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in20_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in2_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in5_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_0_in8_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in13_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in16_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in19_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in22_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in25_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in28_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in31_in\ : STD_LOGIC;
signal \INTERRUPT_CONTROL_I/p_1_in34_in\ : STD_LOGIC;
signal IP2Bus_WrAck_transmit_enable : STD_LOGIC;
signal \I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_DECODER/p_1_in\ : STD_LOGIC;
signal \I_DECODER/p_2_in\ : STD_LOGIC;
signal \I_DECODER/p_4_in\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_23\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_38\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_46\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_48\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_57\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_68\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_12\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_13\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_14\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_15\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_21\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_22\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_29\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_31\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_35\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_36\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_37\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_38\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_39\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_40\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_41\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_44\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_45\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_46\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_47\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_50\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_51\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_52\ : STD_LOGIC;
signal \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_53\ : STD_LOGIC;
signal Rx_FIFO_Empty : STD_LOGIC;
signal Rx_FIFO_Full_Fifo_d1_synced : STD_LOGIC;
signal \SOFT_RESET_I/reset_trig0\ : STD_LOGIC;
signal \SOFT_RESET_I/sw_rst_cond\ : STD_LOGIC;
signal \SOFT_RESET_I/sw_rst_cond_d1\ : STD_LOGIC;
signal SPISSR_frm_axi_clk : STD_LOGIC;
signal TX_Fifo_full_indication : STD_LOGIC;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : STD_LOGIC;
signal Tx_FIFO_Full_int : STD_LOGIC;
signal burst_tr_int : STD_LOGIC;
signal bus2ip_reset_ipif_inverted : STD_LOGIC;
signal bus2ip_wrce_int : STD_LOGIC_VECTOR ( 7 to 7 );
signal data_valid : STD_LOGIC;
signal intr_controller_rd_ce_or_reduce : STD_LOGIC;
signal io0_i_sync : STD_LOGIC;
signal io1_i_sync : STD_LOGIC;
signal ip2Bus_RdAck_core_reg : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole0 : STD_LOGIC;
signal ip2Bus_RdAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2Bus_WrAck_core_reg : STD_LOGIC;
signal ip2Bus_WrAck_core_reg0 : STD_LOGIC;
signal ip2Bus_WrAck_core_reg_d1 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole0 : STD_LOGIC;
signal ip2Bus_WrAck_intr_reg_hole_d1 : STD_LOGIC;
signal ip2bus_data_int : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ip2bus_error_int : STD_LOGIC;
signal rd_ce_or_reduce_core_cmb : STD_LOGIC;
signal rd_en : STD_LOGIC;
signal receive_ip2bus_error : STD_LOGIC;
signal reset2ip_reset_int : STD_LOGIC;
signal rx_fifo_empty_i : STD_LOGIC;
signal s_axi4_rresp_i0 : STD_LOGIC;
signal spicr_0_loop_frm_axi_clk : STD_LOGIC;
signal spicr_1_spe_frm_axi_clk : STD_LOGIC;
signal spicr_2_mst_n_slv_frm_axi_clk : STD_LOGIC;
signal spicr_3_cpol_frm_axi_clk : STD_LOGIC;
signal spicr_4_cpha_frm_axi_clk : STD_LOGIC;
signal spicr_5_txfifo_rst_frm_axi_clk : STD_LOGIC;
signal spicr_6_rxfifo_rst_frm_axi_clk : STD_LOGIC;
signal spicr_7_ss_frm_axi_clk : STD_LOGIC;
signal spicr_8_tr_inhibit_frm_axi_clk : STD_LOGIC;
signal spicr_9_lsb_frm_axi_clk : STD_LOGIC;
signal spisel_d1_reg_to_axi_clk : STD_LOGIC;
signal transmit_ip2bus_error : STD_LOGIC;
signal wr_ce_or_reduce_core_cmb : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of IO0_I_REG : label is "FD";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of IO0_I_REG : label is "VCC:CE GND:R";
attribute box_type : string;
attribute box_type of IO0_I_REG : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of IO1_I_REG : label is "FD";
attribute XILINX_TRANSFORM_PINMAP of IO1_I_REG : label is "VCC:CE GND:R";
attribute box_type of IO1_I_REG : label is "PRIMITIVE";
begin
IO0_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => io0_i,
Q => io0_i_sync,
R => '0'
);
IO1_I_REG: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => ext_spi_clk,
CE => '1',
D => io1_i,
Q => io1_i_sync,
R => '0'
);
\QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_qspi_core_interface
port map (
Bus_RNW_reg => \I_DECODER/Bus_RNW_reg\,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_52\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_53\,
\CONTROL_REG_5_9_GENERATE[9].SPICR_data_int_reg[9]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_12\,
D(7 downto 0) => ip2bus_data_int(7 downto 0),
E(0) => s_axi4_rresp_i0,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_23\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_46\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_45\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_44\,
\GEN_IP_IRPT_STATUS_REG[6].GEN_REG_STATUS.ip_irpt_status_reg_reg[6]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_47\,
IP2Bus_WrAck_transmit_enable => IP2Bus_WrAck_transmit_enable,
Q(0) => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_21\,
\RESET_FLOPS[15].RST_FLOPS\ => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_38\,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_50\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
Transmit_ip2bus_error0 => \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_int => Tx_FIFO_Full_int,
almost_full => TX_Fifo_full_indication,
burst_tr_int => burst_tr_int,
bus2ip_reset_ipif_inverted => bus2ip_reset_ipif_inverted,
bus2ip_wrce_int(0) => bus2ip_wrce_int(7),
data_valid => data_valid,
empty => Rx_FIFO_Empty,
ext_spi_clk => ext_spi_clk,
\gen_fwft.gdvld_fwft.data_valid_fwft_reg\ => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_48\,
interrupt_wrce_strb => \INTERRUPT_CONTROL_I/interrupt_wrce_strb\,
intr2bus_rdack0 => \INTERRUPT_CONTROL_I/intr2bus_rdack0\,
intr2bus_rdack_reg => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_57\,
intr2bus_wrack_reg => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_46\,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
io0_i_sync => io0_i_sync,
io0_t => io0_t,
io1_i_sync => io1_i_sync,
io1_o => io1_o,
io1_t => io1_t,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg => ip2Bus_WrAck_core_reg,
ip2Bus_WrAck_core_reg0 => ip2Bus_WrAck_core_reg0,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1_reg_0 => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_14\,
ip2bus_error_int => ip2bus_error_int,
ip2intc_irpt => ip2intc_irpt,
\ip_irpt_enable_reg_reg[8]\(8) => \INTERRUPT_CONTROL_I/p_0_in20_in\,
\ip_irpt_enable_reg_reg[8]\(7) => \INTERRUPT_CONTROL_I/p_0_in17_in\,
\ip_irpt_enable_reg_reg[8]\(6) => \INTERRUPT_CONTROL_I/p_0_in14_in\,
\ip_irpt_enable_reg_reg[8]\(5) => \INTERRUPT_CONTROL_I/p_0_in11_in\,
\ip_irpt_enable_reg_reg[8]\(4) => \INTERRUPT_CONTROL_I/p_0_in8_in\,
\ip_irpt_enable_reg_reg[8]\(3) => \INTERRUPT_CONTROL_I/p_0_in5_in\,
\ip_irpt_enable_reg_reg[8]\(2) => \INTERRUPT_CONTROL_I/p_0_in2_in\,
\ip_irpt_enable_reg_reg[8]\(1) => \INTERRUPT_CONTROL_I/p_0_in0_in\,
\ip_irpt_enable_reg_reg[8]\(0) => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_68\,
\ip_irpt_enable_reg_reg[8]_0\(0) => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_13\,
ipif_glbl_irpt_enable_reg_reg => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_51\,
irpt_rdack => \INTERRUPT_CONTROL_I/irpt_rdack\,
irpt_rdack_d1 => \INTERRUPT_CONTROL_I/irpt_rdack_d1\,
irpt_wrack => \INTERRUPT_CONTROL_I/irpt_wrack\,
irpt_wrack_d1 => \INTERRUPT_CONTROL_I/irpt_wrack_d1\,
p_0_in(0) => \INTERRUPT_CONTROL_I/p_0_in\(31),
p_1_in => \I_DECODER/p_1_in\,
p_1_in13_in => \INTERRUPT_CONTROL_I/p_1_in13_in\,
p_1_in16_in => \INTERRUPT_CONTROL_I/p_1_in16_in\,
p_1_in19_in => \INTERRUPT_CONTROL_I/p_1_in19_in\,
p_1_in22_in => \INTERRUPT_CONTROL_I/p_1_in22_in\,
p_1_in25_in => \INTERRUPT_CONTROL_I/p_1_in25_in\,
p_1_in28_in => \INTERRUPT_CONTROL_I/p_1_in28_in\,
p_1_in31_in => \INTERRUPT_CONTROL_I/p_1_in31_in\,
p_1_in34_in => \INTERRUPT_CONTROL_I/p_1_in34_in\,
p_2_in => \I_DECODER/p_2_in\,
p_4_in => \I_DECODER/p_4_in\,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
rd_en => rd_en,
receive_ip2bus_error => receive_ip2bus_error,
reset2ip_reset_int => reset2ip_reset_int,
reset_trig0 => \SOFT_RESET_I/reset_trig0\,
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi4_aclk => s_axi4_aclk,
\s_axi4_rdata_i_reg[0]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_31\,
\s_axi4_rdata_i_reg[1]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_35\,
\s_axi4_rdata_i_reg[2]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_36\,
\s_axi4_rdata_i_reg[31]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_22\,
\s_axi4_rdata_i_reg[3]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_37\,
\s_axi4_rdata_i_reg[4]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_38\,
\s_axi4_rdata_i_reg[5]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_39\,
\s_axi4_rdata_i_reg[5]_0\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_15\,
\s_axi4_rdata_i_reg[6]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_40\,
\s_axi4_rdata_i_reg[7]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_29\,
\s_axi4_rdata_i_reg[7]_0\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_41\,
s_axi4_rready => s_axi4_rready,
s_axi4_wdata(9 downto 0) => s_axi4_wdata(9 downto 0),
sck_o => sck_o,
sck_t => sck_t,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced,
spicr_0_loop_frm_axi_clk => spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk => spicr_9_lsb_frm_axi_clk,
spisel_d1_reg_to_axi_clk => spisel_d1_reg_to_axi_clk,
ss_o(0) => ss_o(0),
ss_t => ss_t,
sw_rst_cond => \SOFT_RESET_I/sw_rst_cond\,
sw_rst_cond_d1 => \SOFT_RESET_I/sw_rst_cond_d1\,
transmit_ip2bus_error => transmit_ip2bus_error,
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
\QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_qspi_enhanced_mode
port map (
Bus_RNW_reg => \I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_12\,
Bus_RNW_reg_reg_0(0) => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_13\,
Bus_RNW_reg_reg_1 => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_14\,
\CONTROL_REG_3_4_GENERATE[3].SPICR_data_int_reg[3]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_52\,
\CONTROL_REG_3_4_GENERATE[4].SPICR_data_int_reg[4]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_53\,
D(7 downto 0) => ip2bus_data_int(7 downto 0),
E(0) => s_axi4_rresp_i0,
\FSM_onehot_axi_full_sm_ps_reg[2]_0\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_22\,
\FSM_onehot_axi_full_sm_ps_reg[3]_0\ => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_57\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_46\,
\GEN_BKEND_CE_REGISTERS[27].ce_out_i_reg[27]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_29\,
\GEN_BKEND_CE_REGISTERS[30].ce_out_i_reg[30]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_15\,
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_31\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_46\,
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]_0\ => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_23\,
\GEN_IP_IRPT_STATUS_REG[1].GEN_REG_STATUS.ip_irpt_status_reg_reg[1]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_45\,
\GEN_IP_IRPT_STATUS_REG[3].GEN_REG_STATUS.ip_irpt_status_reg_reg[3]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_44\,
IP2Bus_WrAck_transmit_enable => IP2Bus_WrAck_transmit_enable,
Q(0) => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_21\,
\SPISSR_WR_GEN[0].SPISSR_Data_reg_reg[0]\ => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_38\,
SPISSR_frm_axi_clk => SPISSR_frm_axi_clk,
SR(0) => bus2ip_reset_ipif_inverted,
Transmit_ip2bus_error0 => \FIFO_EXISTS.FIFO_IF_MODULE_I/Transmit_ip2bus_error0\,
Tx_FIFO_Empty_SPISR_to_axi_clk => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_int => Tx_FIFO_Full_int,
almost_full => TX_Fifo_full_indication,
burst_tr_int => burst_tr_int,
\bus2ip_BE_reg_reg[3]_0\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_47\,
bus2ip_wrce_int(0) => bus2ip_wrce_int(7),
data_valid => data_valid,
empty => Rx_FIFO_Empty,
interrupt_wrce_strb => \INTERRUPT_CONTROL_I/interrupt_wrce_strb\,
intr2bus_rdack0 => \INTERRUPT_CONTROL_I/intr2bus_rdack0\,
intr_controller_rd_ce_or_reduce => intr_controller_rd_ce_or_reduce,
ip2Bus_RdAck_core_reg => ip2Bus_RdAck_core_reg,
ip2Bus_RdAck_intr_reg_hole0 => ip2Bus_RdAck_intr_reg_hole0,
ip2Bus_RdAck_intr_reg_hole_d1 => ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_core_reg => ip2Bus_WrAck_core_reg,
ip2Bus_WrAck_core_reg0 => ip2Bus_WrAck_core_reg0,
ip2Bus_WrAck_core_reg_d1 => ip2Bus_WrAck_core_reg_d1,
ip2Bus_WrAck_intr_reg_hole0 => ip2Bus_WrAck_intr_reg_hole0,
ip2Bus_WrAck_intr_reg_hole_d1 => ip2Bus_WrAck_intr_reg_hole_d1,
ip2bus_error_int => ip2bus_error_int,
\ip_irpt_enable_reg_reg[1]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_35\,
\ip_irpt_enable_reg_reg[2]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_36\,
\ip_irpt_enable_reg_reg[3]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_37\,
\ip_irpt_enable_reg_reg[4]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_38\,
\ip_irpt_enable_reg_reg[5]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_39\,
\ip_irpt_enable_reg_reg[6]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_40\,
\ip_irpt_enable_reg_reg[7]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_41\,
irpt_rdack => \INTERRUPT_CONTROL_I/irpt_rdack\,
irpt_rdack_d1 => \INTERRUPT_CONTROL_I/irpt_rdack_d1\,
irpt_wrack => \INTERRUPT_CONTROL_I/irpt_wrack\,
irpt_wrack_d1 => \INTERRUPT_CONTROL_I/irpt_wrack_d1\,
p_0_in(0) => \INTERRUPT_CONTROL_I/p_0_in\(31),
p_1_in => \I_DECODER/p_1_in\,
p_1_in13_in => \INTERRUPT_CONTROL_I/p_1_in13_in\,
p_1_in16_in => \INTERRUPT_CONTROL_I/p_1_in16_in\,
p_1_in19_in => \INTERRUPT_CONTROL_I/p_1_in19_in\,
p_1_in22_in => \INTERRUPT_CONTROL_I/p_1_in22_in\,
p_1_in25_in => \INTERRUPT_CONTROL_I/p_1_in25_in\,
p_1_in28_in => \INTERRUPT_CONTROL_I/p_1_in28_in\,
p_1_in31_in => \INTERRUPT_CONTROL_I/p_1_in31_in\,
p_1_in34_in => \INTERRUPT_CONTROL_I/p_1_in34_in\,
p_2_in => \I_DECODER/p_2_in\,
p_4_in => \I_DECODER/p_4_in\,
rd_ce_or_reduce_core_cmb => rd_ce_or_reduce_core_cmb,
rd_en => rd_en,
receive_ip2bus_error => receive_ip2bus_error,
reset2ip_reset_int => reset2ip_reset_int,
reset_trig0 => \SOFT_RESET_I/reset_trig0\,
rx_fifo_empty_i => rx_fifo_empty_i,
s_axi4_aclk => s_axi4_aclk,
s_axi4_araddr(4 downto 0) => s_axi4_araddr(4 downto 0),
s_axi4_aresetn => s_axi4_aresetn,
s_axi4_arlen(7 downto 0) => s_axi4_arlen(7 downto 0),
s_axi4_arready => s_axi4_arready,
s_axi4_arvalid => s_axi4_arvalid,
s_axi4_awaddr(4 downto 0) => s_axi4_awaddr(4 downto 0),
s_axi4_awlen(7 downto 0) => s_axi4_awlen(7 downto 0),
s_axi4_awready => s_axi4_awready,
s_axi4_awvalid => s_axi4_awvalid,
s_axi4_bready => s_axi4_bready,
s_axi4_bresp(0) => s_axi4_bresp(0),
s_axi4_bvalid => s_axi4_bvalid,
s_axi4_rdata(10 downto 0) => s_axi4_rdata(10 downto 0),
\s_axi4_rdata_i_reg[8]_0\(8) => \INTERRUPT_CONTROL_I/p_0_in20_in\,
\s_axi4_rdata_i_reg[8]_0\(7) => \INTERRUPT_CONTROL_I/p_0_in17_in\,
\s_axi4_rdata_i_reg[8]_0\(6) => \INTERRUPT_CONTROL_I/p_0_in14_in\,
\s_axi4_rdata_i_reg[8]_0\(5) => \INTERRUPT_CONTROL_I/p_0_in11_in\,
\s_axi4_rdata_i_reg[8]_0\(4) => \INTERRUPT_CONTROL_I/p_0_in8_in\,
\s_axi4_rdata_i_reg[8]_0\(3) => \INTERRUPT_CONTROL_I/p_0_in5_in\,
\s_axi4_rdata_i_reg[8]_0\(2) => \INTERRUPT_CONTROL_I/p_0_in2_in\,
\s_axi4_rdata_i_reg[8]_0\(1) => \INTERRUPT_CONTROL_I/p_0_in0_in\,
\s_axi4_rdata_i_reg[8]_0\(0) => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_68\,
s_axi4_rlast => s_axi4_rlast,
s_axi4_rready => s_axi4_rready,
s_axi4_rresp(0) => s_axi4_rresp(0),
s_axi4_wdata(6) => s_axi4_wdata(10),
s_axi4_wdata(5 downto 4) => s_axi4_wdata(6 downto 5),
s_axi4_wdata(3 downto 0) => s_axi4_wdata(3 downto 0),
\s_axi4_wdata[31]\ => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_51\,
s_axi4_wdata_0_sp_1 => \QSPI_ENHANCED_MD_GEN.QSPI_ENHANCED_MD_IPIF_I_n_50\,
s_axi4_wready => s_axi4_wready,
s_axi4_wstrb(1 downto 0) => s_axi4_wstrb(1 downto 0),
s_axi4_wvalid => s_axi4_wvalid,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_1 => \QSPI_ENHANCED_MD_GEN.QSPI_CORE_INTERFACE_I_n_48\,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced,
spicr_0_loop_frm_axi_clk => spicr_0_loop_frm_axi_clk,
spicr_1_spe_frm_axi_clk => spicr_1_spe_frm_axi_clk,
spicr_2_mst_n_slv_frm_axi_clk => spicr_2_mst_n_slv_frm_axi_clk,
spicr_3_cpol_frm_axi_clk => spicr_3_cpol_frm_axi_clk,
spicr_4_cpha_frm_axi_clk => spicr_4_cpha_frm_axi_clk,
spicr_5_txfifo_rst_frm_axi_clk => spicr_5_txfifo_rst_frm_axi_clk,
spicr_6_rxfifo_rst_frm_axi_clk => spicr_6_rxfifo_rst_frm_axi_clk,
spicr_7_ss_frm_axi_clk => spicr_7_ss_frm_axi_clk,
spicr_8_tr_inhibit_frm_axi_clk => spicr_8_tr_inhibit_frm_axi_clk,
spicr_9_lsb_frm_axi_clk => spicr_9_lsb_frm_axi_clk,
spisel_d1_reg_to_axi_clk => spisel_d1_reg_to_axi_clk,
sw_rst_cond => \SOFT_RESET_I/sw_rst_cond\,
sw_rst_cond_d1 => \SOFT_RESET_I/sw_rst_cond_d1\,
transmit_ip2bus_error => transmit_ip2bus_error,
wr_ce_or_reduce_core_cmb => wr_ce_or_reduce_core_cmb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi is
port (
ext_spi_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi4_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_awaddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_awlock : in STD_LOGIC;
s_axi4_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awvalid : in STD_LOGIC;
s_axi4_awready : out STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_wlast : in STD_LOGIC;
s_axi4_wvalid : in STD_LOGIC;
s_axi4_wready : out STD_LOGIC;
s_axi4_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_bvalid : out STD_LOGIC;
s_axi4_bready : in STD_LOGIC;
s_axi4_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_araddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_arlock : in STD_LOGIC;
s_axi4_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arvalid : in STD_LOGIC;
s_axi4_arready : out STD_LOGIC;
s_axi4_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi4_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_rlast : out STD_LOGIC;
s_axi4_rvalid : out STD_LOGIC;
s_axi4_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
io2_i : in STD_LOGIC;
io2_o : out STD_LOGIC;
io2_t : out STD_LOGIC;
io3_i : in STD_LOGIC;
io3_o : out STD_LOGIC;
io3_t : out STD_LOGIC;
io0_1_i : in STD_LOGIC;
io0_1_o : out STD_LOGIC;
io0_1_t : out STD_LOGIC;
io1_1_i : in STD_LOGIC;
io1_1_o : out STD_LOGIC;
io1_1_t : out STD_LOGIC;
io2_1_i : in STD_LOGIC;
io2_1_o : out STD_LOGIC;
io2_1_t : out STD_LOGIC;
io3_1_i : in STD_LOGIC;
io3_1_o : out STD_LOGIC;
io3_1_t : out STD_LOGIC;
spisel : in STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ss_1_i : in STD_LOGIC;
ss_1_o : out STD_LOGIC;
ss_1_t : out STD_LOGIC;
cfgclk : out STD_LOGIC;
cfgmclk : out STD_LOGIC;
eos : out STD_LOGIC;
preq : out STD_LOGIC;
clk : in STD_LOGIC;
gsr : in STD_LOGIC;
gts : in STD_LOGIC;
keyclearb : in STD_LOGIC;
usrcclkts : in STD_LOGIC;
usrdoneo : in STD_LOGIC;
usrdonets : in STD_LOGIC;
pack : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
attribute Async_Clk : integer;
attribute Async_Clk of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_BYTE_LEVEL_INTERRUPT_EN : integer;
attribute C_BYTE_LEVEL_INTERRUPT_EN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_DUAL_QUAD_MODE : integer;
attribute C_DUAL_QUAD_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is "kintex7";
attribute C_FIFO_DEPTH : integer;
attribute C_FIFO_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 256;
attribute C_INSTANCE : string;
attribute C_INSTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is "axi_quad_spi_inst";
attribute C_LSB_STUP : integer;
attribute C_LSB_STUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_NEW_SEQ_EN : integer;
attribute C_NEW_SEQ_EN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 1;
attribute C_NUM_SS_BITS : integer;
attribute C_NUM_SS_BITS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 1;
attribute C_NUM_TRANSFER_BITS : integer;
attribute C_NUM_TRANSFER_BITS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 8;
attribute C_SCK_RATIO : integer;
attribute C_SCK_RATIO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 4;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_SHARED_STARTUP : integer;
attribute C_SHARED_STARTUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_SPI_MEMORY : integer;
attribute C_SPI_MEMORY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 1;
attribute C_SPI_MEM_ADDR_BITS : integer;
attribute C_SPI_MEM_ADDR_BITS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 24;
attribute C_SPI_MODE : integer;
attribute C_SPI_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_SUB_FAMILY : string;
attribute C_SUB_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is "kintex7";
attribute C_S_AXI4_ADDR_WIDTH : integer;
attribute C_S_AXI4_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 24;
attribute C_S_AXI4_BASEADDR : integer;
attribute C_S_AXI4_BASEADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is -1;
attribute C_S_AXI4_DATA_WIDTH : integer;
attribute C_S_AXI4_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 32;
attribute C_S_AXI4_HIGHADDR : integer;
attribute C_S_AXI4_HIGHADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_S_AXI4_ID_WIDTH : integer;
attribute C_S_AXI4_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 7;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 32;
attribute C_TYPE_OF_AXI4_INTERFACE : integer;
attribute C_TYPE_OF_AXI4_INTERFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 1;
attribute C_UC_FAMILY : integer;
attribute C_UC_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_USE_STARTUP : integer;
attribute C_USE_STARTUP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_USE_STARTUP_EXT : integer;
attribute C_USE_STARTUP_EXT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_XIP_MODE : integer;
attribute C_XIP_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 0;
attribute C_XIP_PERF_MODE : integer;
attribute C_XIP_PERF_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi is
signal \<const0>\ : STD_LOGIC;
signal \^io1_o\ : STD_LOGIC;
signal \^s_axi4_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi4_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi4_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
attribute initialval : string;
attribute initialval of spisel : signal is "VCC";
begin
cfgclk <= \<const0>\;
cfgmclk <= \<const0>\;
eos <= \<const0>\;
io0_1_o <= \<const0>\;
io0_1_t <= \<const0>\;
io0_o <= \^io1_o\;
io1_1_o <= \<const0>\;
io1_1_t <= \<const0>\;
io1_o <= \^io1_o\;
io2_1_o <= \<const0>\;
io2_1_t <= \<const0>\;
io2_o <= \<const0>\;
io2_t <= \<const0>\;
io3_1_o <= \<const0>\;
io3_1_t <= \<const0>\;
io3_o <= \<const0>\;
io3_t <= \<const0>\;
preq <= \<const0>\;
s_axi4_bid(0) <= \<const0>\;
s_axi4_bresp(1) <= \^s_axi4_bresp\(1);
s_axi4_bresp(0) <= \<const0>\;
s_axi4_rdata(31) <= \^s_axi4_rdata\(31);
s_axi4_rdata(30) <= \<const0>\;
s_axi4_rdata(29) <= \<const0>\;
s_axi4_rdata(28) <= \<const0>\;
s_axi4_rdata(27) <= \<const0>\;
s_axi4_rdata(26) <= \<const0>\;
s_axi4_rdata(25) <= \<const0>\;
s_axi4_rdata(24) <= \<const0>\;
s_axi4_rdata(23) <= \<const0>\;
s_axi4_rdata(22) <= \<const0>\;
s_axi4_rdata(21) <= \<const0>\;
s_axi4_rdata(20) <= \<const0>\;
s_axi4_rdata(19) <= \<const0>\;
s_axi4_rdata(18) <= \<const0>\;
s_axi4_rdata(17) <= \<const0>\;
s_axi4_rdata(16) <= \<const0>\;
s_axi4_rdata(15) <= \<const0>\;
s_axi4_rdata(14) <= \<const0>\;
s_axi4_rdata(13) <= \<const0>\;
s_axi4_rdata(12) <= \<const0>\;
s_axi4_rdata(11) <= \<const0>\;
s_axi4_rdata(10) <= \<const0>\;
s_axi4_rdata(9 downto 0) <= \^s_axi4_rdata\(9 downto 0);
s_axi4_rid(0) <= \<const0>\;
s_axi4_rresp(1) <= \^s_axi4_rresp\(1);
s_axi4_rresp(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
ss_1_o <= \<const0>\;
ss_1_t <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\NO_DUAL_QUAD_MODE.QSPI_NORMAL\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi_top
port map (
ext_spi_clk => ext_spi_clk,
io0_i => io0_i,
io0_t => io0_t,
io1_i => io1_i,
io1_o => \^io1_o\,
io1_t => io1_t,
ip2intc_irpt => ip2intc_irpt,
s_axi4_aclk => s_axi4_aclk,
s_axi4_araddr(4 downto 0) => s_axi4_araddr(6 downto 2),
s_axi4_aresetn => s_axi4_aresetn,
s_axi4_arlen(7 downto 0) => s_axi4_arlen(7 downto 0),
s_axi4_arready => s_axi4_arready,
s_axi4_arvalid => s_axi4_arvalid,
s_axi4_awaddr(4 downto 0) => s_axi4_awaddr(6 downto 2),
s_axi4_awlen(7 downto 0) => s_axi4_awlen(7 downto 0),
s_axi4_awready => s_axi4_awready,
s_axi4_awvalid => s_axi4_awvalid,
s_axi4_bready => s_axi4_bready,
s_axi4_bresp(0) => \^s_axi4_bresp\(1),
s_axi4_bvalid => s_axi4_bvalid,
s_axi4_rdata(10) => \^s_axi4_rdata\(31),
s_axi4_rdata(9 downto 0) => \^s_axi4_rdata\(9 downto 0),
s_axi4_rlast => s_axi4_rlast,
s_axi4_rready => s_axi4_rready,
s_axi4_rresp(0) => \^s_axi4_rresp\(1),
s_axi4_wdata(10) => s_axi4_wdata(31),
s_axi4_wdata(9 downto 0) => s_axi4_wdata(9 downto 0),
s_axi4_wready => s_axi4_wready,
s_axi4_wstrb(1) => s_axi4_wstrb(3),
s_axi4_wstrb(0) => s_axi4_wstrb(0),
s_axi4_wvalid => s_axi4_wvalid,
s_axi_rvalid_i_reg => s_axi4_rvalid,
sck_o => sck_o,
sck_t => sck_t,
ss_o(0) => ss_o(0),
ss_t => ss_t
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
ext_spi_clk : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
s_axi4_awaddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_awlock : in STD_LOGIC;
s_axi4_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awvalid : in STD_LOGIC;
s_axi4_awready : out STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_wlast : in STD_LOGIC;
s_axi4_wvalid : in STD_LOGIC;
s_axi4_wready : out STD_LOGIC;
s_axi4_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_bvalid : out STD_LOGIC;
s_axi4_bready : in STD_LOGIC;
s_axi4_araddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_arlock : in STD_LOGIC;
s_axi4_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arvalid : in STD_LOGIC;
s_axi4_arready : out STD_LOGIC;
s_axi4_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_rlast : out STD_LOGIC;
s_axi4_rvalid : out STD_LOGIC;
s_axi4_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "xlnx_axi_quad_spi,axi_quad_spi,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_quad_spi,Vivado 2021.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^s_axi4_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi4_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi4_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_U0_cfgclk_UNCONNECTED : STD_LOGIC;
signal NLW_U0_cfgmclk_UNCONNECTED : STD_LOGIC;
signal NLW_U0_eos_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io0_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io0_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io1_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io1_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io2_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_io3_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_preq_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ss_1_o_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ss_1_t_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi4_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi4_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi4_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 30 downto 10 );
signal NLW_U0_s_axi4_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi4_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute Async_Clk : integer;
attribute Async_Clk of U0 : label is 0;
attribute C_BYTE_LEVEL_INTERRUPT_EN : integer;
attribute C_BYTE_LEVEL_INTERRUPT_EN of U0 : label is 0;
attribute C_DUAL_QUAD_MODE : integer;
attribute C_DUAL_QUAD_MODE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "kintex7";
attribute C_FIFO_DEPTH : integer;
attribute C_FIFO_DEPTH of U0 : label is 256;
attribute C_INSTANCE : string;
attribute C_INSTANCE of U0 : label is "axi_quad_spi_inst";
attribute C_LSB_STUP : integer;
attribute C_LSB_STUP of U0 : label is 0;
attribute C_NEW_SEQ_EN : integer;
attribute C_NEW_SEQ_EN of U0 : label is 1;
attribute C_NUM_SS_BITS : integer;
attribute C_NUM_SS_BITS of U0 : label is 1;
attribute C_NUM_TRANSFER_BITS : integer;
attribute C_NUM_TRANSFER_BITS of U0 : label is 8;
attribute C_SCK_RATIO : integer;
attribute C_SCK_RATIO of U0 : label is 4;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SHARED_STARTUP : integer;
attribute C_SHARED_STARTUP of U0 : label is 0;
attribute C_SPI_MEMORY : integer;
attribute C_SPI_MEMORY of U0 : label is 1;
attribute C_SPI_MEM_ADDR_BITS : integer;
attribute C_SPI_MEM_ADDR_BITS of U0 : label is 24;
attribute C_SPI_MODE : integer;
attribute C_SPI_MODE of U0 : label is 0;
attribute C_SUB_FAMILY : string;
attribute C_SUB_FAMILY of U0 : label is "kintex7";
attribute C_S_AXI4_ADDR_WIDTH : integer;
attribute C_S_AXI4_ADDR_WIDTH of U0 : label is 24;
attribute C_S_AXI4_BASEADDR : integer;
attribute C_S_AXI4_BASEADDR of U0 : label is -1;
attribute C_S_AXI4_DATA_WIDTH : integer;
attribute C_S_AXI4_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI4_HIGHADDR : integer;
attribute C_S_AXI4_HIGHADDR of U0 : label is 0;
attribute C_S_AXI4_ID_WIDTH : integer;
attribute C_S_AXI4_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 7;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TYPE_OF_AXI4_INTERFACE : integer;
attribute C_TYPE_OF_AXI4_INTERFACE of U0 : label is 1;
attribute C_UC_FAMILY : integer;
attribute C_UC_FAMILY of U0 : label is 0;
attribute C_USE_STARTUP : integer;
attribute C_USE_STARTUP of U0 : label is 0;
attribute C_USE_STARTUP_EXT : integer;
attribute C_USE_STARTUP_EXT of U0 : label is 0;
attribute C_XIP_MODE : integer;
attribute C_XIP_MODE of U0 : label is 0;
attribute C_XIP_PERF_MODE : integer;
attribute C_XIP_PERF_MODE of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of ext_spi_clk : signal is "xilinx.com:signal:clock:1.0 spi_clk CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of ext_spi_clk : signal is "XIL_INTERFACENAME spi_clk, ASSOCIATED_BUSIF SPI_0, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of io0_i : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
attribute x_interface_parameter of io0_i : signal is "XIL_INTERFACENAME SPI_0, BOARD.ASSOCIATED_PARAM QSPI_BOARD_INTERFACE";
attribute x_interface_info of io0_o : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
attribute x_interface_info of io0_t : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
attribute x_interface_info of io1_i : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
attribute x_interface_info of io1_o : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
attribute x_interface_info of io1_t : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
attribute x_interface_info of ip2intc_irpt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
attribute x_interface_parameter of ip2intc_irpt : signal is "XIL_INTERFACENAME interrupt, SENSITIVITY EDGE_RISING, PortWidth 1";
attribute x_interface_info of s_axi4_aclk : signal is "xilinx.com:signal:clock:1.0 full_clk CLK";
attribute x_interface_parameter of s_axi4_aclk : signal is "XIL_INTERFACENAME full_clk, ASSOCIATED_BUSIF AXI_FULL, ASSOCIATED_RESET s_axi4_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of s_axi4_aresetn : signal is "xilinx.com:signal:reset:1.0 full_reset RST";
attribute x_interface_parameter of s_axi4_aresetn : signal is "XIL_INTERFACENAME full_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute x_interface_info of s_axi4_arlock : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARLOCK";
attribute x_interface_info of s_axi4_arready : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARREADY";
attribute x_interface_info of s_axi4_arvalid : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARVALID";
attribute x_interface_info of s_axi4_awlock : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWLOCK";
attribute x_interface_info of s_axi4_awready : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWREADY";
attribute x_interface_info of s_axi4_awvalid : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWVALID";
attribute x_interface_info of s_axi4_bready : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL BREADY";
attribute x_interface_info of s_axi4_bvalid : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL BVALID";
attribute x_interface_info of s_axi4_rlast : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL RLAST";
attribute x_interface_info of s_axi4_rready : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL RREADY";
attribute x_interface_info of s_axi4_rvalid : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL RVALID";
attribute x_interface_info of s_axi4_wlast : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL WLAST";
attribute x_interface_info of s_axi4_wready : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL WREADY";
attribute x_interface_info of s_axi4_wvalid : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL WVALID";
attribute x_interface_info of sck_i : signal is "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
attribute x_interface_info of sck_o : signal is "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
attribute x_interface_info of sck_t : signal is "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
attribute x_interface_info of ss_t : signal is "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
attribute x_interface_info of s_axi4_araddr : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARADDR";
attribute x_interface_info of s_axi4_arburst : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARBURST";
attribute x_interface_info of s_axi4_arcache : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARCACHE";
attribute x_interface_info of s_axi4_arlen : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARLEN";
attribute x_interface_info of s_axi4_arprot : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARPROT";
attribute x_interface_info of s_axi4_arsize : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL ARSIZE";
attribute x_interface_info of s_axi4_awaddr : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWADDR";
attribute x_interface_parameter of s_axi4_awaddr : signal is "XIL_INTERFACENAME AXI_FULL, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 24, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
attribute x_interface_info of s_axi4_awburst : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWBURST";
attribute x_interface_info of s_axi4_awcache : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWCACHE";
attribute x_interface_info of s_axi4_awlen : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWLEN";
attribute x_interface_info of s_axi4_awprot : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWPROT";
attribute x_interface_info of s_axi4_awsize : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL AWSIZE";
attribute x_interface_info of s_axi4_bresp : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL BRESP";
attribute x_interface_info of s_axi4_rdata : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL RDATA";
attribute x_interface_info of s_axi4_rresp : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL RRESP";
attribute x_interface_info of s_axi4_wdata : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL WDATA";
attribute x_interface_info of s_axi4_wstrb : signal is "xilinx.com:interface:aximm:1.0 AXI_FULL WSTRB";
attribute x_interface_info of ss_i : signal is "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
attribute x_interface_info of ss_o : signal is "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
begin
s_axi4_bresp(1) <= \^s_axi4_bresp\(1);
s_axi4_bresp(0) <= \<const0>\;
s_axi4_rdata(31) <= \^s_axi4_rdata\(31);
s_axi4_rdata(30) <= \<const0>\;
s_axi4_rdata(29) <= \<const0>\;
s_axi4_rdata(28) <= \<const0>\;
s_axi4_rdata(27) <= \<const0>\;
s_axi4_rdata(26) <= \<const0>\;
s_axi4_rdata(25) <= \<const0>\;
s_axi4_rdata(24) <= \<const0>\;
s_axi4_rdata(23) <= \<const0>\;
s_axi4_rdata(22) <= \<const0>\;
s_axi4_rdata(21) <= \<const0>\;
s_axi4_rdata(20) <= \<const0>\;
s_axi4_rdata(19) <= \<const0>\;
s_axi4_rdata(18) <= \<const0>\;
s_axi4_rdata(17) <= \<const0>\;
s_axi4_rdata(16) <= \<const0>\;
s_axi4_rdata(15) <= \<const0>\;
s_axi4_rdata(14) <= \<const0>\;
s_axi4_rdata(13) <= \<const0>\;
s_axi4_rdata(12) <= \<const0>\;
s_axi4_rdata(11) <= \<const0>\;
s_axi4_rdata(10) <= \<const0>\;
s_axi4_rdata(9 downto 0) <= \^s_axi4_rdata\(9 downto 0);
s_axi4_rresp(1) <= \^s_axi4_rresp\(1);
s_axi4_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_quad_spi
port map (
cfgclk => NLW_U0_cfgclk_UNCONNECTED,
cfgmclk => NLW_U0_cfgmclk_UNCONNECTED,
clk => '0',
eos => NLW_U0_eos_UNCONNECTED,
ext_spi_clk => ext_spi_clk,
gsr => '0',
gts => '0',
io0_1_i => '0',
io0_1_o => NLW_U0_io0_1_o_UNCONNECTED,
io0_1_t => NLW_U0_io0_1_t_UNCONNECTED,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_1_i => '0',
io1_1_o => NLW_U0_io1_1_o_UNCONNECTED,
io1_1_t => NLW_U0_io1_1_t_UNCONNECTED,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_1_i => '0',
io2_1_o => NLW_U0_io2_1_o_UNCONNECTED,
io2_1_t => NLW_U0_io2_1_t_UNCONNECTED,
io2_i => '0',
io2_o => NLW_U0_io2_o_UNCONNECTED,
io2_t => NLW_U0_io2_t_UNCONNECTED,
io3_1_i => '0',
io3_1_o => NLW_U0_io3_1_o_UNCONNECTED,
io3_1_t => NLW_U0_io3_1_t_UNCONNECTED,
io3_i => '0',
io3_o => NLW_U0_io3_o_UNCONNECTED,
io3_t => NLW_U0_io3_t_UNCONNECTED,
ip2intc_irpt => ip2intc_irpt,
keyclearb => '0',
pack => '0',
preq => NLW_U0_preq_UNCONNECTED,
s_axi4_aclk => s_axi4_aclk,
s_axi4_araddr(23 downto 7) => B"00000000000000000",
s_axi4_araddr(6 downto 2) => s_axi4_araddr(6 downto 2),
s_axi4_araddr(1 downto 0) => B"00",
s_axi4_arburst(1 downto 0) => B"00",
s_axi4_arcache(3 downto 0) => B"0000",
s_axi4_aresetn => s_axi4_aresetn,
s_axi4_arid(0) => '0',
s_axi4_arlen(7 downto 0) => s_axi4_arlen(7 downto 0),
s_axi4_arlock => '0',
s_axi4_arprot(2 downto 0) => B"000",
s_axi4_arready => s_axi4_arready,
s_axi4_arsize(2 downto 0) => B"000",
s_axi4_arvalid => s_axi4_arvalid,
s_axi4_awaddr(23 downto 7) => B"00000000000000000",
s_axi4_awaddr(6 downto 2) => s_axi4_awaddr(6 downto 2),
s_axi4_awaddr(1 downto 0) => B"00",
s_axi4_awburst(1 downto 0) => B"00",
s_axi4_awcache(3 downto 0) => B"0000",
s_axi4_awid(0) => '0',
s_axi4_awlen(7 downto 0) => s_axi4_awlen(7 downto 0),
s_axi4_awlock => '0',
s_axi4_awprot(2 downto 0) => B"000",
s_axi4_awready => s_axi4_awready,
s_axi4_awsize(2 downto 0) => B"000",
s_axi4_awvalid => s_axi4_awvalid,
s_axi4_bid(0) => NLW_U0_s_axi4_bid_UNCONNECTED(0),
s_axi4_bready => s_axi4_bready,
s_axi4_bresp(1) => \^s_axi4_bresp\(1),
s_axi4_bresp(0) => NLW_U0_s_axi4_bresp_UNCONNECTED(0),
s_axi4_bvalid => s_axi4_bvalid,
s_axi4_rdata(31) => \^s_axi4_rdata\(31),
s_axi4_rdata(30 downto 10) => NLW_U0_s_axi4_rdata_UNCONNECTED(30 downto 10),
s_axi4_rdata(9 downto 0) => \^s_axi4_rdata\(9 downto 0),
s_axi4_rid(0) => NLW_U0_s_axi4_rid_UNCONNECTED(0),
s_axi4_rlast => s_axi4_rlast,
s_axi4_rready => s_axi4_rready,
s_axi4_rresp(1) => \^s_axi4_rresp\(1),
s_axi4_rresp(0) => NLW_U0_s_axi4_rresp_UNCONNECTED(0),
s_axi4_rvalid => s_axi4_rvalid,
s_axi4_wdata(31) => s_axi4_wdata(31),
s_axi4_wdata(30 downto 10) => B"000000000000000000000",
s_axi4_wdata(9 downto 0) => s_axi4_wdata(9 downto 0),
s_axi4_wlast => '0',
s_axi4_wready => s_axi4_wready,
s_axi4_wstrb(3) => s_axi4_wstrb(3),
s_axi4_wstrb(2 downto 1) => B"00",
s_axi4_wstrb(0) => s_axi4_wstrb(0),
s_axi4_wvalid => s_axi4_wvalid,
s_axi_aclk => '0',
s_axi_araddr(6 downto 0) => B"0000000",
s_axi_aresetn => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arvalid => '0',
s_axi_awaddr(6 downto 0) => B"0000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awvalid => '0',
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sck_i => '0',
sck_o => sck_o,
sck_t => sck_t,
spisel => '1',
ss_1_i => '0',
ss_1_o => NLW_U0_ss_1_o_UNCONNECTED,
ss_1_t => NLW_U0_ss_1_t_UNCONNECTED,
ss_i(0) => '0',
ss_o(0) => ss_o(0),
ss_t => ss_t,
usrcclkts => '0',
usrdoneo => '1',
usrdonets => '0'
);
end STRUCTURE;
|
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
// Date : Tue Sep 20 00:10:14 2022
// Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_quad_spi_stub.v
// Design : xlnx_axi_quad_spi
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_quad_spi,Vivado 2021.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(ext_spi_clk, s_axi4_aclk, s_axi4_aresetn,
s_axi4_awaddr, s_axi4_awlen, s_axi4_awsize, s_axi4_awburst, s_axi4_awlock, s_axi4_awcache,
s_axi4_awprot, s_axi4_awvalid, s_axi4_awready, s_axi4_wdata, s_axi4_wstrb, s_axi4_wlast,
s_axi4_wvalid, s_axi4_wready, s_axi4_bresp, s_axi4_bvalid, s_axi4_bready, s_axi4_araddr,
s_axi4_arlen, s_axi4_arsize, s_axi4_arburst, s_axi4_arlock, s_axi4_arcache, s_axi4_arprot,
s_axi4_arvalid, s_axi4_arready, s_axi4_rdata, s_axi4_rresp, s_axi4_rlast, s_axi4_rvalid,
s_axi4_rready, io0_i, io0_o, io0_t, io1_i, io1_o, io1_t, sck_i, sck_o, sck_t, ss_i, ss_o, ss_t,
ip2intc_irpt)
/* synthesis syn_black_box black_box_pad_pin="ext_spi_clk,s_axi4_aclk,s_axi4_aresetn,s_axi4_awaddr[23:0],s_axi4_awlen[7:0],s_axi4_awsize[2:0],s_axi4_awburst[1:0],s_axi4_awlock,s_axi4_awcache[3:0],s_axi4_awprot[2:0],s_axi4_awvalid,s_axi4_awready,s_axi4_wdata[31:0],s_axi4_wstrb[3:0],s_axi4_wlast,s_axi4_wvalid,s_axi4_wready,s_axi4_bresp[1:0],s_axi4_bvalid,s_axi4_bready,s_axi4_araddr[23:0],s_axi4_arlen[7:0],s_axi4_arsize[2:0],s_axi4_arburst[1:0],s_axi4_arlock,s_axi4_arcache[3:0],s_axi4_arprot[2:0],s_axi4_arvalid,s_axi4_arready,s_axi4_rdata[31:0],s_axi4_rresp[1:0],s_axi4_rlast,s_axi4_rvalid,s_axi4_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt" */;
input ext_spi_clk;
input s_axi4_aclk;
input s_axi4_aresetn;
input [23:0]s_axi4_awaddr;
input [7:0]s_axi4_awlen;
input [2:0]s_axi4_awsize;
input [1:0]s_axi4_awburst;
input s_axi4_awlock;
input [3:0]s_axi4_awcache;
input [2:0]s_axi4_awprot;
input s_axi4_awvalid;
output s_axi4_awready;
input [31:0]s_axi4_wdata;
input [3:0]s_axi4_wstrb;
input s_axi4_wlast;
input s_axi4_wvalid;
output s_axi4_wready;
output [1:0]s_axi4_bresp;
output s_axi4_bvalid;
input s_axi4_bready;
input [23:0]s_axi4_araddr;
input [7:0]s_axi4_arlen;
input [2:0]s_axi4_arsize;
input [1:0]s_axi4_arburst;
input s_axi4_arlock;
input [3:0]s_axi4_arcache;
input [2:0]s_axi4_arprot;
input s_axi4_arvalid;
output s_axi4_arready;
output [31:0]s_axi4_rdata;
output [1:0]s_axi4_rresp;
output s_axi4_rlast;
output s_axi4_rvalid;
input s_axi4_rready;
input io0_i;
output io0_o;
output io0_t;
input io1_i;
output io1_o;
output io1_t;
input sck_i;
output sck_o;
output sck_t;
input [0:0]ss_i;
output [0:0]ss_o;
output ss_t;
output ip2intc_irpt;
endmodule
|
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Tue Sep 20 00:10:14 2022
-- Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_axi_quad_spi_stub.vhdl
-- Design : xlnx_axi_quad_spi
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
ext_spi_clk : in STD_LOGIC;
s_axi4_aclk : in STD_LOGIC;
s_axi4_aresetn : in STD_LOGIC;
s_axi4_awaddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_awlock : in STD_LOGIC;
s_axi4_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_awvalid : in STD_LOGIC;
s_axi4_awready : out STD_LOGIC;
s_axi4_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_wlast : in STD_LOGIC;
s_axi4_wvalid : in STD_LOGIC;
s_axi4_wready : out STD_LOGIC;
s_axi4_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_bvalid : out STD_LOGIC;
s_axi4_bready : in STD_LOGIC;
s_axi4_araddr : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axi4_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi4_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_arlock : in STD_LOGIC;
s_axi4_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi4_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi4_arvalid : in STD_LOGIC;
s_axi4_arready : out STD_LOGIC;
s_axi4_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi4_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi4_rlast : out STD_LOGIC;
s_axi4_rvalid : out STD_LOGIC;
s_axi4_rready : in STD_LOGIC;
io0_i : in STD_LOGIC;
io0_o : out STD_LOGIC;
io0_t : out STD_LOGIC;
io1_i : in STD_LOGIC;
io1_o : out STD_LOGIC;
io1_t : out STD_LOGIC;
sck_i : in STD_LOGIC;
sck_o : out STD_LOGIC;
sck_t : out STD_LOGIC;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out STD_LOGIC;
ip2intc_irpt : out STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "ext_spi_clk,s_axi4_aclk,s_axi4_aresetn,s_axi4_awaddr[23:0],s_axi4_awlen[7:0],s_axi4_awsize[2:0],s_axi4_awburst[1:0],s_axi4_awlock,s_axi4_awcache[3:0],s_axi4_awprot[2:0],s_axi4_awvalid,s_axi4_awready,s_axi4_wdata[31:0],s_axi4_wstrb[3:0],s_axi4_wlast,s_axi4_wvalid,s_axi4_wready,s_axi4_bresp[1:0],s_axi4_bvalid,s_axi4_bready,s_axi4_araddr[23:0],s_axi4_arlen[7:0],s_axi4_arsize[2:0],s_axi4_arburst[1:0],s_axi4_arlock,s_axi4_arcache[3:0],s_axi4_arprot[2:0],s_axi4_arvalid,s_axi4_arready,s_axi4_rdata[31:0],s_axi4_rresp[1:0],s_axi4_rlast,s_axi4_rvalid,s_axi4_rready,io0_i,io0_o,io0_t,io1_i,io1_o,io1_t,sck_i,sck_o,sck_t,ss_i[0:0],ss_o[0:0],ss_t,ip2intc_irpt";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_quad_spi,Vivado 2021.2";
begin
end;
|
version:1
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version:1
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|
// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
// IP Revision: 24
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
xlnx_axi_quad_spi your_instance_name (
.ext_spi_clk(ext_spi_clk), // input wire ext_spi_clk
.s_axi4_aclk(s_axi4_aclk), // input wire s_axi4_aclk
.s_axi4_aresetn(s_axi4_aresetn), // input wire s_axi4_aresetn
.s_axi4_awaddr(s_axi4_awaddr), // input wire [23 : 0] s_axi4_awaddr
.s_axi4_awlen(s_axi4_awlen), // input wire [7 : 0] s_axi4_awlen
.s_axi4_awsize(s_axi4_awsize), // input wire [2 : 0] s_axi4_awsize
.s_axi4_awburst(s_axi4_awburst), // input wire [1 : 0] s_axi4_awburst
.s_axi4_awlock(s_axi4_awlock), // input wire s_axi4_awlock
.s_axi4_awcache(s_axi4_awcache), // input wire [3 : 0] s_axi4_awcache
.s_axi4_awprot(s_axi4_awprot), // input wire [2 : 0] s_axi4_awprot
.s_axi4_awvalid(s_axi4_awvalid), // input wire s_axi4_awvalid
.s_axi4_awready(s_axi4_awready), // output wire s_axi4_awready
.s_axi4_wdata(s_axi4_wdata), // input wire [31 : 0] s_axi4_wdata
.s_axi4_wstrb(s_axi4_wstrb), // input wire [3 : 0] s_axi4_wstrb
.s_axi4_wlast(s_axi4_wlast), // input wire s_axi4_wlast
.s_axi4_wvalid(s_axi4_wvalid), // input wire s_axi4_wvalid
.s_axi4_wready(s_axi4_wready), // output wire s_axi4_wready
.s_axi4_bresp(s_axi4_bresp), // output wire [1 : 0] s_axi4_bresp
.s_axi4_bvalid(s_axi4_bvalid), // output wire s_axi4_bvalid
.s_axi4_bready(s_axi4_bready), // input wire s_axi4_bready
.s_axi4_araddr(s_axi4_araddr), // input wire [23 : 0] s_axi4_araddr
.s_axi4_arlen(s_axi4_arlen), // input wire [7 : 0] s_axi4_arlen
.s_axi4_arsize(s_axi4_arsize), // input wire [2 : 0] s_axi4_arsize
.s_axi4_arburst(s_axi4_arburst), // input wire [1 : 0] s_axi4_arburst
.s_axi4_arlock(s_axi4_arlock), // input wire s_axi4_arlock
.s_axi4_arcache(s_axi4_arcache), // input wire [3 : 0] s_axi4_arcache
.s_axi4_arprot(s_axi4_arprot), // input wire [2 : 0] s_axi4_arprot
.s_axi4_arvalid(s_axi4_arvalid), // input wire s_axi4_arvalid
.s_axi4_arready(s_axi4_arready), // output wire s_axi4_arready
.s_axi4_rdata(s_axi4_rdata), // output wire [31 : 0] s_axi4_rdata
.s_axi4_rresp(s_axi4_rresp), // output wire [1 : 0] s_axi4_rresp
.s_axi4_rlast(s_axi4_rlast), // output wire s_axi4_rlast
.s_axi4_rvalid(s_axi4_rvalid), // output wire s_axi4_rvalid
.s_axi4_rready(s_axi4_rready), // input wire s_axi4_rready
.io0_i(io0_i), // input wire io0_i
.io0_o(io0_o), // output wire io0_o
.io0_t(io0_t), // output wire io0_t
.io1_i(io1_i), // input wire io1_i
.io1_o(io1_o), // output wire io1_o
.io1_t(io1_t), // output wire io1_t
.sck_i(sck_i), // input wire sck_i
.sck_o(sck_o), // output wire sck_o
.sck_t(sck_t), // output wire sck_t
.ss_i(ss_i), // input wire [0 : 0] ss_i
.ss_o(ss_o), // output wire [0 : 0] ss_o
.ss_t(ss_t), // output wire ss_t
.ip2intc_irpt(ip2intc_irpt) // output wire ip2intc_irpt
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file xlnx_axi_quad_spi.v when simulating
// the core, xlnx_axi_quad_spi. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
|
-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 24
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT xlnx_axi_quad_spi
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : xlnx_axi_quad_spi
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi4_aclk => s_axi4_aclk,
s_axi4_aresetn => s_axi4_aresetn,
s_axi4_awaddr => s_axi4_awaddr,
s_axi4_awlen => s_axi4_awlen,
s_axi4_awsize => s_axi4_awsize,
s_axi4_awburst => s_axi4_awburst,
s_axi4_awlock => s_axi4_awlock,
s_axi4_awcache => s_axi4_awcache,
s_axi4_awprot => s_axi4_awprot,
s_axi4_awvalid => s_axi4_awvalid,
s_axi4_awready => s_axi4_awready,
s_axi4_wdata => s_axi4_wdata,
s_axi4_wstrb => s_axi4_wstrb,
s_axi4_wlast => s_axi4_wlast,
s_axi4_wvalid => s_axi4_wvalid,
s_axi4_wready => s_axi4_wready,
s_axi4_bresp => s_axi4_bresp,
s_axi4_bvalid => s_axi4_bvalid,
s_axi4_bready => s_axi4_bready,
s_axi4_araddr => s_axi4_araddr,
s_axi4_arlen => s_axi4_arlen,
s_axi4_arsize => s_axi4_arsize,
s_axi4_arburst => s_axi4_arburst,
s_axi4_arlock => s_axi4_arlock,
s_axi4_arcache => s_axi4_arcache,
s_axi4_arprot => s_axi4_arprot,
s_axi4_arvalid => s_axi4_arvalid,
s_axi4_arready => s_axi4_arready,
s_axi4_rdata => s_axi4_rdata,
s_axi4_rresp => s_axi4_rresp,
s_axi4_rlast => s_axi4_rlast,
s_axi4_rvalid => s_axi4_rvalid,
s_axi4_rready => s_axi4_rready,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ip2intc_irpt => ip2intc_irpt
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file xlnx_axi_quad_spi.vhd when simulating
-- the core, xlnx_axi_quad_spi. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
|
# file: xlnx_axi_quad_spi.xdc
# (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
## IOB constraints ######
set_property IOB true [get_cells -hierarchical -filter {NAME =~*IO*_I_REG}]
#####################################################################################################
# The following section list the board specific constraints (with/without STARTUPE2/E3 primitive) #
# as per guidance given in product guide. #
# User should uncomment, update constraints based on board delays and use #
#####################################################################################################
#####################################################################################################
# STARTUPE2 primitive is not used #
#####################################################################################################
#### All the delay numbers have to be provided by the user
#### CCLK max delay is 6.7 ns ; refer Data sheet
#### We need to consider the max delay for worst case analysis
##set cclk_delay 6.7
#### Following are the SPI device parameters
#### Max Tco
##set tco_max 7
#### Min Tco
##set tco_min 1
#### Setup time requirement
##set tsu 2
#### Hold time requirement
##set th 3
#### Following are the board/trace delay numbers
#### Assumption is that all Data lines are matched
##set tdata_trace_delay_max 0.25
##set tdata_trace_delay_min 0.25
##set tclk_trace_delay_max 0.2
##set tclk_trace_delay_min 0.2
##### End of user provided delay numbers
####create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}
##create_generated_clock -name clk_sck -source [get_pins -filter {REF_PIN_NAME==ext_spi_clk} -of [get_cells -hier -filter {REF_NAME=~axi_quad_spi_0}]] [get_ports SCK_IO] -edges {3 5 7}
#### Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge
#### Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk
##set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;
##set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;
##set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
##set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]
#### Data is captured into SPI on the following rising edge of SCK
#### Data is driven by the IP on alternate rising_edge of the ext_spi_clk
##set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];
##set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min - $th - $tclk_trace_delay_max] [get_ports IO*_IO];
##set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
##set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck
|
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<spirit:vendor>xilinx.com</spirit:vendor>
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</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_0_TO_STARTUP.BOARD.ASSOCIATED_PARAM">QSPI_BOARD_INTERFACE</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SPI_0_TO_STARTUP" xilinx:dependency="((spirit:decode(id('PARAM_VALUE.C_DUAL_QUAD_MODE')) = 1) and (spirit:decode(id('PARAM_VALUE.C_USE_STARTUP_INT')) = 0))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>SPI_1</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="spi" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="spi_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO0_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io0_1_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO0_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io0_1_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO0_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io0_1_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO1_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io1_1_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO1_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io1_1_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO1_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io1_1_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO2_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io2_1_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO2_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io2_1_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO2_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io2_1_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO3_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io3_1_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO3_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io3_1_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>IO3_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>io3_1_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SPISEL</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>spisel</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SS_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ss_1_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SS_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ss_1_o</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>SS_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ss_1_t</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_1.BOARD.ASSOCIATED_PARAM">QSPI_BOARD_INTERFACE</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.SPI_1" xilinx:dependency="((spirit:decode(id('PARAM_VALUE.C_DUAL_QUAD_MODE')) = 1))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>STARTUP_IO</spirit:name>
<spirit:displayName>STARTUP_IO</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_startup_io" spirit:name="startup_io" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_startup_io" spirit:name="startup_io_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>cfgclk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cfgclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>cfgmclk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cfgmclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eos</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>eos</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>preq</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>preq</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.STARTUP_IO" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_USE_STARTUP')) = 1) and (spirit:decode(id('PARAM_VALUE.UC_FAMILY')) = 0) and (spirit:decode(id('PARAM_VALUE.C_SHARED_STARTUP')) = 0))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>STARTUP_IO_S</spirit:name>
<spirit:displayName>STARTUP_IO</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="startup" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="startup_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>cfgclk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cfgclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>cfgmclk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>cfgmclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>clk</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eos</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>eos</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gsr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gsr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>gts</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gts</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>keyclearb</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>keyclearb</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>pack</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pack</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>preq</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>preq</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>userdoneo</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>usrdoneo</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>usrclkts</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>usrcclkts</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>usrdonets</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>usrdonets</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.STARTUP_IO_S" xilinx:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_USE_STARTUP')) = 1 and (spirit:decode(id('PARAM_VALUE.C_SHARED_STARTUP')) = 1)) or (spirit:decode(id('MODELPARAM_VALUE.C_USE_STARTUP')) = 1 and (spirit:decode(id('PARAM_VALUE.UC_FAMILY')) = 1)))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>AXI_LITE</spirit:name>
<spirit:displayName>AXI_LITE</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_araddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_arready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_arvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_awaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_awready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_awvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_bready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_bresp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_bvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_rdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_rready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_rresp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_rvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_wdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_wready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_wstrb</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_wvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>DATA_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.DATA_WIDTH">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PROTOCOL</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ID_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.ID_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ADDR_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.ADDR_WIDTH">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AWUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.AWUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ARUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.ARUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.WUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>RUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.RUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>BUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.BUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>READ_WRITE_MODE</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_BURST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_BURST">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_LOCK</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_LOCK">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_PROT</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_PROT">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_CACHE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_CACHE">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_QOS</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_QOS">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_REGION</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_REGION">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_WSTRB</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_WSTRB">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_BRESP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_BRESP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_RRESP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.HAS_RRESP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MAX_BURST_LENGTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_THREADS</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.NUM_READ_THREADS">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_THREADS</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_LITE.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_LITE" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 0 or spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE')) = 1">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>lite_clk</spirit:name>
<spirit:displayName>lite_clk</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_aclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.LITE_CLK.ASSOCIATED_BUSIF">AXI_LITE</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.LITE_CLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LITE_CLK.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LITE_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LITE_CLK.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LITE_CLK.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_PORT</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LITE_CLK.ASSOCIATED_PORT"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.LITE_CLK.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.lite_clk" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 0 or spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE')) = 1">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>lite_reset</spirit:name>
<spirit:displayName>lite_reset</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi_aresetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.LITE_RESET.POLARITY">ACTIVE_LOW</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.LITE_RESET.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.lite_reset" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 0 or spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE')) = 1">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>interrupt</spirit:name>
<spirit:displayName>interrupt</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ip2intc_irpt</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SENSITIVITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY">EDGE_RISING</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PortWidth</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTERRUPT.PortWidth">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>AXI_FULL</spirit:name>
<spirit:displayName>AXI_FULL</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="aximm"/>
</spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_araddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arburst</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARCACHE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arcache</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARLEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arlen</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arlock</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arprot</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arsize</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_arvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awburst</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWCACHE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awcache</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWLEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awlen</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWLOCK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awlock</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awprot</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awsize</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_awvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_bid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_bready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_bresp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_bvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_rdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_rid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_rlast</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_rready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_rresp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_rvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_wdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_wlast</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_wready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_wstrb</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_wvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>DATA_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.DATA_WIDTH">32</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PROTOCOL</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.PROTOCOL">AXI4</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ID_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.ID_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ADDR_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.ADDR_WIDTH">24</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AWUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.AWUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ARUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.ARUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.WUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>RUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.RUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>BUSER_WIDTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.BUSER_WIDTH">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>READ_WRITE_MODE</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.READ_WRITE_MODE">READ_WRITE</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_BURST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_BURST">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_LOCK</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_LOCK">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_PROT</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_PROT">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_CACHE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_CACHE">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_QOS</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_QOS">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_REGION</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_REGION">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_WSTRB</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_WSTRB">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_BRESP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_BRESP">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>HAS_RRESP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.HAS_RRESP">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.SUPPORTS_NARROW_BURST">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_OUTSTANDING</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.NUM_READ_OUTSTANDING">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.NUM_WRITE_OUTSTANDING">2</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MAX_BURST_LENGTH</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.MAX_BURST_LENGTH">256</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_READ_THREADS</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.NUM_READ_THREADS">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>NUM_WRITE_THREADS</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.NUM_WRITE_THREADS">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.RUSER_BITS_PER_BYTE">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.WUSER_BITS_PER_BYTE">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AXI_FULL.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.AXI_FULL" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 1 or spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE')) = 1">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>full_reset</spirit:name>
<spirit:displayName>full_reset</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_aresetn</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.FULL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.FULL_RESET.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.full_reset" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 1 or spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE')) = 1">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>full_clk</spirit:name>
<spirit:displayName>full_clk</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>s_axi4_aclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.FULL_CLK.ASSOCIATED_BUSIF">AXI_FULL</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.FULL_CLK.ASSOCIATED_RESET">s_axi4_aresetn</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FULL_CLK.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FULL_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FULL_CLK.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FULL_CLK.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_PORT</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.FULL_CLK.ASSOCIATED_PORT"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.FULL_CLK.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.full_clk" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 1 or spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE')) = 1">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>spi_clk</spirit:name>
<spirit:displayName>spi_clk</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>ext_spi_clk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_CLK.ASSOCIATED_BUSIF">SPI_0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_CLK.FREQ_HZ">100000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>PHASE</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_CLK.PHASE">0.0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLK_DOMAIN</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_CLK.CLK_DOMAIN"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_PORT</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_CLK.ASSOCIATED_PORT"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ASSOCIATED_RESET</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_CLK.ASSOCIATED_RESET"/>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>none</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>INSERT_VIP</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SPI_CLK.INSERT_VIP">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>aximm</spirit:name>
<spirit:displayName>AXI Register Map</spirit:displayName>
<spirit:description>Memory Map for aximm</spirit:description>
<spirit:addressBlock>
<spirit:name>MEM0</spirit:name>
<spirit:displayName>MEM0</spirit:displayName>
<spirit:description>Register Block</spirit:description>
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
<spirit:width spirit:format="long">32</spirit:width>
<spirit:usage>register</spirit:usage>
<spirit:access>read-write</spirit:access>
<spirit:parameters>
<spirit:parameter>
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.AXIMM.MEM0.OFFSET_BASE_PARAM">C_S_AXI4_BASEADDR</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.AXIMM.MEM0.OFFSET_HIGH_PARAM">C_S_AXI4_HIGHADDR</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:register>
<spirit:name>SRR</spirit:name>
<spirit:displayName>Software Reset Register</spirit:displayName>
<spirit:description>Software Reset Register</spirit:description>
<spirit:addressOffset>0x40</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>write-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Reset</spirit:name>
<spirit:displayName>AXI Quad SPI Reset</spirit:displayName>
<spirit:description>The only allowed operation on this register is a write of 0x0000000a, which resets the AXI Quad SPI core.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>write-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.SRR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPICR</spirit:name>
<spirit:displayName>SPI Control Register</spirit:displayName>
<spirit:description>SPI Control Register</spirit:description>
<spirit:addressOffset>0x60</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x180</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>LOOP</spirit:name>
<spirit:displayName>Loopback Mode</spirit:displayName>
<spirit:description>Local loopback mode
Enables local loopback operation and is functional only in standard SPI master mode.
When set to: 0 - Normal operation. 1 - Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data (from remote slave) is ignored.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>SPE</spirit:name>
<spirit:displayName>SPI System Enable</spirit:displayName>
<spirit:description>SPI system enable
When set to:
0 - SPI system disabled. Both master and slave outputs are in 3-state and slave inputs are ignored.
1 - SPI system enabled. Master outputs active (for example, IO0 (MOSI) and SCK in idle state) and slave outputs become active if SS becomes asserted. The master starts transferring when transmit data is available.
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Master</spirit:name>
<spirit:displayName>Master</spirit:displayName>
<spirit:description>Master (SPI master mode)
Setting this bit configures the SPI device as a master or a slave.
When set to:
0 - Slave configuration.
1 - Master configuration.
In dual/quad SPI mode only the master mode of the core is allowed.
Standard Slave mode is not supported for SCK ratio = 2
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL</spirit:name>
<spirit:displayName>Clock Polarity</spirit:displayName>
<spirit:description>Clock polarity
Setting this bit defines clock polarity.
When set to:
0 - Active-High clock; SCK idles Low.
1 - Active-Low clock; SCK idles High.
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPHA</spirit:name>
<spirit:displayName>Clock Phase</spirit:displayName>
<spirit:description>Clock phase
Setting this bit selects one of two fundamentally different transfer formats.
</spirit:description>
<spirit:bitOffset>4</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TX_FIFO_Reset</spirit:name>
<spirit:displayName>Transmit FIFO reset</spirit:displayName>
<spirit:description>Transmit FIFO reset
When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.
When set to: 0 - Transmit FIFO normal operation. 1 - Reset transmit FIFO pointer
</spirit:description>
<spirit:bitOffset>5</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>RX_FIFO_Reset</spirit:name>
<spirit:displayName>Receive FIFO reset</spirit:displayName>
<spirit:description>Receive FIFO reset
When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.
When set to: 0 - Receive FIFO normal operation. 1 - Reset receive FIFO pointer.
</spirit:description>
<spirit:bitOffset>6</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Manual_Slave_Select_Assertion_Enable</spirit:name>
<spirit:displayName>Manual Slave Select Assertion Enable</spirit:displayName>
<spirit:description>Manual slave select assertion enable
This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted).
This bit has no effect on slave operation.
When set to: 0 - Slave select output asserted by master core logic. 1 - Slave select output follows data in slave select register. The manual slave assertion mode is supported in standard SPI mode only.
</spirit:description>
<spirit:bitOffset>7</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Master_Transaction_Inhibit</spirit:name>
<spirit:displayName>Master_Transaction_Inhibit</spirit:displayName>
<spirit:description>Master transaction inhibit
This bit inhibits master transactions.
This bit has no effect on slave operation.
When set to: 0 - Master transactions enabled. 1 - Master transactions disabled. This bit immediately inhibits the transaction. Setting this bit while transfer is in progress would result in unpredictable outcome
</spirit:description>
<spirit:bitOffset>8</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>LSB_First</spirit:name>
<spirit:displayName>LSB First</spirit:displayName>
<spirit:description>LSB first
This bit selects LSB first data transfer format.
The default transfer format is MSB first.
When set to:
0 - MSB first transfer format.
1 - LSB first transfer format.
In Dual/Quad SPI mode, only the MSB first mode of the core is allowed.
</spirit:description>
<spirit:bitOffset>9</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.SPICR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPISR</spirit:name>
<spirit:displayName>SPI Status Register</spirit:displayName>
<spirit:description>SPI Status Register</spirit:description>
<spirit:addressOffset>0x64</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0A5</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>RX_Empty</spirit:name>
<spirit:displayName>Receive Empty</spirit:displayName>
<spirit:description>Receive Empty.
When a receive FIFO exists, this bit is set High when the receive FIFO is empty. The occupancy of the FIFO is decremented with each FIFO read operation.
Note: When FIFOs do not exist, this bit is set High when the receive register has been read (this option is available only in standard SPI mode). This bit is cleared at the end of a successful SPI transfer. For dual/quad SPI mode, the FIFO is always present in the core.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>RX_Full</spirit:name>
<spirit:displayName>Receive Full</spirit:displayName>
<spirit:description>Receive full.
When a receive FIFO exists, this bit is set High when the receive FIFO is full. The occupancy of the FIFO is incremented with the completion of each SPI transaction.
Note: When FIFOs do not exist, this bit is set High when an SPI transfer has completed (this option is available only in standard SPI mode). Rx_Empty and Rx_Full are complements in this case
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TX_Empty</spirit:name>
<spirit:displayName>Transmit Empty</spirit:displayName>
<spirit:description>Transmit empty.
When a transmit FIFO exists, this bit is set to High when the transmit FIFO is empty. This bit goes High as soon as the TX FIFO becomes empty. While this bit is High, the last byte of the data that is to be transmitted would still be in the pipeline.
The occupancy of the FIFO is decremented with the completion of each SPI transfer.
Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer (this option is available only in standard SPI mode). Either with or without FIFOs, this bit is cleared on an AXI write to the FIFO or transmit register. For Dual/Quad SPI mode, the FIFO is always present in the core.
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TX_Full</spirit:name>
<spirit:displayName>Transmit Full</spirit:displayName>
<spirit:description>Transmit full.
When a transmit FIFO exists, this bit is set High when the transmit FIFO is full.
Note: When FIFOs do not exist, this bit is set High when an AXI write to the transmit register has been made (this option is available only in standard SPI mode). This bit is cleared when the SPI transfer is completed
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>MODF</spirit:name>
<spirit:displayName>Mode-fault error flag</spirit:displayName>
<spirit:description>Mode-fault error flag.
This flag is set if the SS signal goes active while the SPI device is configured as a master. MODF is automatically cleared by reading the SPISR.
A Low-to-High MODF transition generates a single-cycle strobe interrupt. 0 - No error. 1 - Error condition detected
</spirit:description>
<spirit:bitOffset>4</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Mode_Select</spirit:name>
<spirit:displayName>Slave Mode Select</spirit:displayName>
<spirit:description>Slave_Mode_Select flag.
This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is activated as soon as the master SPI core asserts the chip select pin for the core.
1 - Default in standard mode.
0 - Asserted when core configured in slave mode and selected by external SPI master.
</spirit:description>
<spirit:bitOffset>5</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL_CPHA_Error</spirit:name>
<spirit:displayName>CPOL_CPHA_Error</spirit:displayName>
<spirit:description>CPOL_CPHA_Error flag.
When set to: 0 - Default. 1 - The CPOL and CPHA are set to 01 or 10. When the SPI memory is chosen as either Winbond, Micron or Spansion, and CPOL and CPHA are configured as 01 or 10, this bit is set.
These memories support CPOL=CPHA mode in 00 or in 11 mode. CPOL_CPHA_Error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface
</spirit:description>
<spirit:bitOffset>6</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_mode_error</spirit:name>
<spirit:displayName>Slave mode error</spirit:displayName>
<spirit:description>Slave mode error flag.
When set to: 1 - This bit is set when the core is configured with dual or quad SPI mode and the master is set to 0 in the control register (SPICR). 0 - Master mode is set in the control register (SPICR). Note: Quad SPI mode, only the master mode of the core is allowed. Slave mode error flag is only applicable when the core is configured either in dual or qu ad mode in legacy or enhanced AXI4 mode interface
</spirit:description>
<spirit:bitOffset>7</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>MSB_Error</spirit:name>
<spirit:displayName>MSB Error</spirit:displayName>
<spirit:description>MSB error flag.
When set to: 0 - Default. 1 - This bit is set when the core is configured to transfer the SPI transactions in either dual or quad SPI mode and LSB first bit is set in the control register (SPICR). Note: In dual/quad SPI mode, only the MSB first mode of the core is allowed. MSB error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface
</spirit:description>
<spirit:bitOffset>8</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Loopback_Error</spirit:name>
<spirit:displayName>Loopback Error</spirit:displayName>
<spirit:description>Loopback error flag.
When set to: 0 - Default. The loopback bit in the control register is at default state. 1 - When the SPI command, address, and data bits are set to be transferred in other than standard SPI protocol mode and this bit is set in control register (SPICR). Note: Loopback is only allowed when the core is configured in standard mode. Other modes setting of the bit causes an error and the interrupt bit is set in legacy or enhanced mode AXI4 interface
</spirit:description>
<spirit:bitOffset>9</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Command_Error</spirit:name>
<spirit:displayName>Command Error</spirit:displayName>
<spirit:description>Command error flag.
When set to: 0 - Default. 1 - When the core is configured in dual/quad SPI mode and the first entry in the SPI DTR FIFO (after reset) do not match with the supported command list for the particular memory, this bit is set. Note: Command error is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.
</spirit:description>
<spirit:bitOffset>10</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.SPISR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_DTR</spirit:name>
<spirit:displayName>SPI Data Transmit Register</spirit:displayName>
<spirit:description>SPI Data Transmit Register</spirit:description>
<spirit:addressOffset>0x68</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>write-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>TX_Data</spirit:name>
<spirit:displayName>TX_Data</spirit:displayName>
<spirit:description>SPI Transmit Data.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_TRANSFER_BITS')))">8</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>write-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.SPI_DTR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 1)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_DRR</spirit:name>
<spirit:displayName>SPI Data Receive Register</spirit:displayName>
<spirit:description>SPI Data Receive Register</spirit:description>
<spirit:addressOffset>0x6C</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>RX_Data</spirit:name>
<spirit:displayName>Receive Data</spirit:displayName>
<spirit:description>SPI Receive Data
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_TRANSFER_BITS')))">8</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.SPI_DRR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 1)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_SSR</spirit:name>
<spirit:displayName>SPI Slave Select Register</spirit:displayName>
<spirit:description>SPI Slave Select Register</spirit:description>
<spirit:addressOffset>0x70</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0xFFFF</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Selected_Slave</spirit:name>
<spirit:displayName>Selected Slave</spirit:displayName>
<spirit:description>Active-Low, one-hot encoded slave select
The slaves are numbered right to left starting at zero with the LSB. The slave numbers correspond to the indexes of signal SS
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_SS_BITS')))">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.SPI_SSR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_TXFIFO_OR</spirit:name>
<spirit:displayName>Transmit FIFO Occupancy Register</spirit:displayName>
<spirit:description>SPI Transmit FIFO Occupancy Register</spirit:description>
<spirit:addressOffset>0x74</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Occupancy_Value</spirit:name>
<spirit:displayName>Occupancy Value</spirit:displayName>
<spirit:description>The binary value plus 1 yields the occupancy.
Bit width is log(FIFO Depth).
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.SPI_TXFIFO_OR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_RXFIFO_OR</spirit:name>
<spirit:displayName>Receive FIFO Occupancy Register</spirit:displayName>
<spirit:description>SPI Receive FIFO Occupancy Register</spirit:description>
<spirit:addressOffset>0x78</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Occupancy_Value</spirit:name>
<spirit:displayName>Occupancy Value</spirit:displayName>
<spirit:description>The binary value plus 1 yields the occupancy.
Bit width is log(FIFO Depth).
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.SPI_RXFIFO_OR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>DGIER</spirit:name>
<spirit:displayName>Device Global Interrupt Enable Register</spirit:displayName>
<spirit:description>Device Global Interrupt Enable Register</spirit:description>
<spirit:addressOffset>0x1C</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>GIE</spirit:name>
<spirit:displayName>Global Interrupt Enable</spirit:displayName>
<spirit:description>Global Interrupt Enable.
Allows passing all individually enabled interrupts to the interrupt controller.
When set to: 0 - Disabled. 1 - Enabled.
</spirit:description>
<spirit:bitOffset>31</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.DGIER" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>IPISR</spirit:name>
<spirit:displayName>IP Interrupt Status Register</spirit:displayName>
<spirit:description>IP Interrupt Status Register</spirit:description>
<spirit:addressOffset>0x20</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>MODF</spirit:name>
<spirit:displayName>Mode Fault Error</spirit:displayName>
<spirit:description>Mode-fault error.
This interrupt is generated if the SS signal goes active while the SPI device is configured as a master. This bit is set immediately on SS going active.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_MODF</spirit:name>
<spirit:displayName>Slave Mode Fault Error</spirit:displayName>
<spirit:description>Slave mode-fault error.
This interrupt is generated if the SS signal goes active while the SPI device is configured as a slave, but is not enabled.
This bit is set immediately on SS going active and continually set if SS is active and the device is not enabled
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DTR_Empty</spirit:name>
<spirit:displayName>Data transmit register/FIFO empty</spirit:displayName>
<spirit:description>Data transmit register/FIFO empty.
It is set when the last byte of data has been transferred out to the external flash memory.
In the context of the M68HC11 reference manual, when configured without FIFOs, this interrupt is equivalent in information content to the complement of the SPI transfer complete flag (SPIF ) interrupt bit.
In master mode if this bit is set to 1, no more SPI transfers are permitted
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DTR_Underrun</spirit:name>
<spirit:displayName>Data transmit register/FIFO underrun</spirit:displayName>
<spirit:description>Data transmit register/FIFO underrun.
This bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register when data is requested from an empty transmit register/FIFO by the SPI core logic to perform a SPI transfer.
This can occur only when the SPI device is configured as a slave in standard SPI configuration and is enabled by the SPE bit as set. All zeros are loaded in the shift register and transmitted by the slave in an under-run condition
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Full</spirit:name>
<spirit:displayName>Data receive register/FIFO full</spirit:displayName>
<spirit:description>Data receive register/FIFO full.
Without FIFOs, this bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register (An element can be a byte, half-word, or word depending on the value of Transfer Width).
With FIFOs, this bit is set at the end of the SPI element transfer, when the receive FIFO has been completely filled by a one-clock period strobe to the interrupt register.
</spirit:description>
<spirit:bitOffset>4</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Overrun</spirit:name>
<spirit:displayName>Data receive register/FIFO overrun</spirit:displayName>
<spirit:description>Data receive register/FIFO overrun.
This bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI core logic to complete a SPI transfer.
This can occur when the SPI device is in either master or slave mode (in standard SPI mode) or if the IP is configured in SPI master mode (dual or quad SPI mode).
</spirit:description>
<spirit:bitOffset>5</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TXFIFO_Half_Empty</spirit:name>
<spirit:displayName>Transmit FIFO half empty</spirit:displayName>
<spirit:description>Transmit FIFO half empty.
In standard SPI configuration, IPISR Bit[6] is the transmit FIFO half-empty interrupt.
In dual or quad SPI configuration, based on the FIFO depth, this bit is set at half-empty condition.
Note: This interrupt exists only if the AXI Quad SPI core is configured with FIFOs (In standard, dual or quad SPI mode).
</spirit:description>
<spirit:bitOffset>6</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Select_Mode</spirit:name>
<spirit:displayName>Slave Select Mode</spirit:displayName>
<spirit:description>Slave select mode.
The assertion of this bit is applicable only when the core is configured in slave mode in standard SPI configuration.
This bit is set when the other SPI master core selects the core by asserting the slave select line. This bit is set by a one-clock period strobe to the interrupt register.
Note: This bit is applicable only in standard SPI slave mode
</spirit:description>
<spirit:bitOffset>7</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Not_Empty</spirit:name>
<spirit:displayName>DRR Not Empty</spirit:displayName>
<spirit:description>DRR not empty.
The assertion of this bit is applicable only in the case where FIFO Depth is 16 or 256 and the core is configured in slave mode and standard SPI mode. This bit is set when the DRR FIFO receives the first data value during the SPI transaction.
This bit is set by a one-clock period strobe to the interrupt register when the core receives the first data beat.
Note: The assertion of this bit is applicable only when the FIFO Depth parameter is 16 or 256 and the core is configured in slave mode in standard SPI mode. When FIFO Depth is set to 0, this bit always returns 0. This bit has no significance in dual/quad mode
</spirit:description>
<spirit:bitOffset>8</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL_CPHA_Error</spirit:name>
<spirit:displayName>CPOL_CPHA Error</spirit:displayName>
<spirit:description>CPOL_CPHA error.
This flag is asserted when:
The core is configured in either dual or quad SPI mode and
The CPOL - CPHA control register bits are set to 01 or 10.
In standard SPI mode, this bit is always in default state.
</spirit:description>
<spirit:bitOffset>9</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Mode_Error</spirit:name>
<spirit:displayName>I/O mode instruction Error</spirit:displayName>
<spirit:description>I/O mode instruction error.
This flag is asserted when:
The core is configured in either dual or quad SPI mode and
The core is configured in master = 0 in control register (SPICR(2)).
In standard SPI mode, this bit is always in default state.
</spirit:description>
<spirit:bitOffset>10</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>MSB_Error</spirit:name>
<spirit:displayName>MSB Error</spirit:displayName>
<spirit:description>MSB error.
This flag is asserted when:
The core is configured in either dual or quad SPI mode and
The LSB First bit in the control register (SPICR) is set to 1.
In standard SPI mode, this bit is always in default state.
</spirit:description>
<spirit:bitOffset>11</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Loopback_Error</spirit:name>
<spirit:displayName>Loopback Error</spirit:displayName>
<spirit:description>Loopback error.
This flag is asserted when:
The core is configured in dual or quad SPI transfer mode and
The LOOP bit is set in control register (SPICR(0)).
In standard SPI mode, this bit is always in default state.
</spirit:description>
<spirit:bitOffset>12</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Command_Error</spirit:name>
<spirit:displayName>Command Error</spirit:displayName>
<spirit:description>Command error.
This flag is asserted when: The core is configured in dual/quad SPI mode and The first entry in the SPI DTR FIFO (after reset) does not match with the supported command list for particular memory. When the SPI command in DTR FIFO does not match with the internal supported command list, the core completes the SPI transactions in standard SPI format. This bit is set to show this behavior of the core.
In standard SPI mode this bit is always in default state.
</spirit:description>
<spirit:bitOffset>13</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.IPISR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>IPIER</spirit:name>
<spirit:displayName>IP Interrupt Enable Register</spirit:displayName>
<spirit:description>IP Interrupt Enable Register</spirit:description>
<spirit:addressOffset>0x28</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>MODF</spirit:name>
<spirit:displayName>Mode-fault error flag</spirit:displayName>
<spirit:description>Mode-fault error flag.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_MODF</spirit:name>
<spirit:displayName>Slave mode-fault error flag</spirit:displayName>
<spirit:description>Slave mode-fault error flag.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DTR_Empty</spirit:name>
<spirit:displayName>Data transmit register/FIFO empty</spirit:displayName>
<spirit:description>Data transmit register/FIFO empty.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DTR_Underrun</spirit:name>
<spirit:displayName>Data transmit FIFO underrun</spirit:displayName>
<spirit:description>Data transmit FIFO underrun.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Full</spirit:name>
<spirit:displayName>Data receive register/FIFO full</spirit:displayName>
<spirit:description>Data receive register/FIFO full.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>4</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Overrun</spirit:name>
<spirit:displayName>Receive FIFO overrun</spirit:displayName>
<spirit:description>Receive FIFO overrun.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>5</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TX_FIFO_Half_Empty</spirit:name>
<spirit:displayName>Transmit FIFO half empty</spirit:displayName>
<spirit:description>Transmit FIFO half empty. 0 - Disabled. 1 - Enabled. Note: This bit is meaningful only if the AXI Quad SPI core is configured with FIFOs.
</spirit:description>
<spirit:bitOffset>6</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Select_Mode</spirit:name>
<spirit:displayName>Slave_Select_Mode</spirit:displayName>
<spirit:description>Slave_Select_Mode. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in slave mode by selecting the active-Low status on spisel.
In master mode, setting this bit has no effect.
</spirit:description>
<spirit:bitOffset>7</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Not_Empty</spirit:name>
<spirit:displayName>DRR_Not_Empty</spirit:displayName>
<spirit:description>DRR_Not_Empty. 0 - Disabled. 1 - Enabled. Note: The setting of this bit is applicable only when FIFO Depth is set to 1 and the core is configured in slave mode of standard SPI mode.
If FIFO Depth is set to 0, the setting of this bit has no effect. This is allowed only in standard SPI configuration. It means this bit is not set in the IPIER register. Therefore, this bit should only be used when FIFO Depth is set to 1 and when the core is configured in slave mode.
This bit has no significance in dual or quad mode.
</spirit:description>
<spirit:bitOffset>8</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL_CPHA_Error</spirit:name>
<spirit:displayName>CPOL_CPHA error</spirit:displayName>
<spirit:description>CPOL_CPHA error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>9</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Mode_Error</spirit:name>
<spirit:displayName>Slave_Mode_Error</spirit:displayName>
<spirit:description>I/O mode instruction error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>10</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>MSB_Error</spirit:name>
<spirit:displayName>MSB_Error</spirit:displayName>
<spirit:description>MSB_Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>11</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Loopback_Error</spirit:name>
<spirit:displayName>Loopback Error</spirit:displayName>
<spirit:description>Loopback Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>12</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Command_Error</spirit:name>
<spirit:displayName>Command_Error</spirit:displayName>
<spirit:description>Command_Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>13</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXIMM.MEM0.IPIER" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:vendorExtensions>
<xilinx:addressBlockInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.AXIMM.MEM0" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 1 or spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE')) = 1">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:addressBlockInfo>
</spirit:vendorExtensions>
</spirit:addressBlock>
</spirit:memoryMap>
<spirit:memoryMap>
<spirit:name>AXI_LITE</spirit:name>
<spirit:displayName>AXI Register Map</spirit:displayName>
<spirit:description>Memory Map for AXI_LITE</spirit:description>
<spirit:addressBlock>
<spirit:name>Reg</spirit:name>
<spirit:displayName>Reg</spirit:displayName>
<spirit:description>Register Block</spirit:description>
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:minimum="256" spirit:rangeType="long">4096</spirit:range>
<spirit:width spirit:format="long">32</spirit:width>
<spirit:usage>register</spirit:usage>
<spirit:access>read-write</spirit:access>
<spirit:parameters>
<spirit:parameter>
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.AXI_LITE.REG.OFFSET_BASE_PARAM">C_BASEADDR</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.AXI_LITE.REG.OFFSET_HIGH_PARAM">C_HIGHADDR</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:register>
<spirit:name>XIP_Config_Reg</spirit:name>
<spirit:displayName>XIP Configuration Register</spirit:displayName>
<spirit:description>XIP Configuration Register</spirit:description>
<spirit:addressOffset>0x60</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>CPHA</spirit:name>
<spirit:displayName>CPHA</spirit:displayName>
<spirit:description>CPHA
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL</spirit:name>
<spirit:displayName>CPOL</spirit:displayName>
<spirit:description>CPOL
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.XIP_Config_Reg" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>XIP_Status_Reg</spirit:name>
<spirit:displayName>XIP Status Register</spirit:displayName>
<spirit:description>XIP Status Register</spirit:description>
<spirit:addressOffset>0x64</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x1</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>RX_Empty</spirit:name>
<spirit:displayName>Receiver Empty</spirit:displayName>
<spirit:description>Receiver Empty.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>RX_Full</spirit:name>
<spirit:displayName>Receiver Full</spirit:displayName>
<spirit:description>Receiver Full.
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Master_MODF</spirit:name>
<spirit:displayName>Master Mode Fault</spirit:displayName>
<spirit:description>Master mode fault. This bit is set to 1 if the spisel line is deasserted.
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL_CPHA_Error</spirit:name>
<spirit:displayName>CPOL CPHA Error</spirit:displayName>
<spirit:description>CPOL_CPHA Error.
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>AXI_Transaction_Error</spirit:name>
<spirit:displayName>AXI Transaction Error</spirit:displayName>
<spirit:description>AXI Transaction Error.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.XIP_Status_Reg" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=1)">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SRR</spirit:name>
<spirit:displayName>Software Reset Register</spirit:displayName>
<spirit:description>Software Reset Register</spirit:description>
<spirit:addressOffset>0x40</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>write-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Reset</spirit:name>
<spirit:displayName>AXI Quad SPI Reset</spirit:displayName>
<spirit:description>The only allowed operation on this register is a write of 0x0000000a, which resets the AXI Quad SPI core.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>write-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.SRR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPICR</spirit:name>
<spirit:displayName>SPI Control Register</spirit:displayName>
<spirit:description>SPI Control Register</spirit:description>
<spirit:addressOffset>0x60</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x180</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>LOOP</spirit:name>
<spirit:displayName>Loopback Mode</spirit:displayName>
<spirit:description>Local loopback mode
Enables local loopback operation and is functional only in standard SPI master mode.
When set to: 0 - Normal operation. 1 - Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data (from remote slave) is ignored.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>SPE</spirit:name>
<spirit:displayName>SPI System Enable</spirit:displayName>
<spirit:description>SPI system enable
When set to:
0 - SPI system disabled. Both master and slave outputs are in 3-state and slave inputs are ignored.
1 - SPI system enabled. Master outputs active (for example, IO0 (MOSI) and SCK in idle state) and slave outputs become active if SS becomes asserted. The master starts transferring when transmit data is available.
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Master</spirit:name>
<spirit:displayName>Master</spirit:displayName>
<spirit:description>Master (SPI master mode)
Setting this bit configures the SPI device as a master or a slave.
When set to:
0 - Slave configuration.
1 - Master configuration.
In dual/quad SPI mode only the master mode of the core is allowed.
Standard Slave mode is not supported for SCK ratio = 2
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL</spirit:name>
<spirit:displayName>Clock Polarity</spirit:displayName>
<spirit:description>Clock polarity
Setting this bit defines clock polarity.
When set to:
0 - Active-High clock; SCK idles Low.
1 - Active-Low clock; SCK idles High.
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPHA</spirit:name>
<spirit:displayName>Clock Phase</spirit:displayName>
<spirit:description>Clock phase
Setting this bit selects one of two fundamentally different transfer formats.
</spirit:description>
<spirit:bitOffset>4</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TX_FIFO_Reset</spirit:name>
<spirit:displayName>Transmit FIFO reset</spirit:displayName>
<spirit:description>Transmit FIFO reset
When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.
When set to: 0 - Transmit FIFO normal operation. 1 - Reset transmit FIFO pointer
</spirit:description>
<spirit:bitOffset>5</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>RX_FIFO_Reset</spirit:name>
<spirit:displayName>Receive FIFO reset</spirit:displayName>
<spirit:description>Receive FIFO reset
When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.
When set to: 0 - Receive FIFO normal operation. 1 - Reset receive FIFO pointer.
</spirit:description>
<spirit:bitOffset>6</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Manual_Slave_Select_Assertion_Enable</spirit:name>
<spirit:displayName>Manual Slave Select Assertion Enable</spirit:displayName>
<spirit:description>Manual slave select assertion enable
This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted).
This bit has no effect on slave operation.
When set to: 0 - Slave select output asserted by master core logic. 1 - Slave select output follows data in slave select register. The manual slave assertion mode is supported in standard SPI mode only.
</spirit:description>
<spirit:bitOffset>7</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Master_Transaction_Inhibit</spirit:name>
<spirit:displayName>Master_Transaction_Inhibit</spirit:displayName>
<spirit:description>Master transaction inhibit
This bit inhibits master transactions.
This bit has no effect on slave operation.
When set to: 0 - Master transactions enabled. 1 - Master transactions disabled. This bit immediately inhibits the transaction. Setting this bit while transfer is in progress would result in unpredictable outcome
</spirit:description>
<spirit:bitOffset>8</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>LSB_First</spirit:name>
<spirit:displayName>LSB First</spirit:displayName>
<spirit:description>LSB first
This bit selects LSB first data transfer format.
The default transfer format is MSB first.
When set to:
0 - MSB first transfer format.
1 - LSB first transfer format.
In Dual/Quad SPI mode, only the MSB first mode of the core is allowed.
</spirit:description>
<spirit:bitOffset>9</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.SPICR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPISR</spirit:name>
<spirit:displayName>SPI Status Register</spirit:displayName>
<spirit:description>SPI Status Register</spirit:description>
<spirit:addressOffset>0x64</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0A5</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>RX_Empty</spirit:name>
<spirit:displayName>Receive Empty</spirit:displayName>
<spirit:description>Receive Empty.
When a receive FIFO exists, this bit is set High when the receive FIFO is empty. The occupancy of the FIFO is decremented with each FIFO read operation.
Note: When FIFOs do not exist, this bit is set High when the receive register has been read (this option is available only in standard SPI mode). This bit is cleared at the end of a successful SPI transfer. For dual/quad SPI mode, the FIFO is always present in the core.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>RX_Full</spirit:name>
<spirit:displayName>Receive Full</spirit:displayName>
<spirit:description>Receive full.
When a receive FIFO exists, this bit is set High when the receive FIFO is full. The occupancy of the FIFO is incremented with the completion of each SPI transaction.
Note: When FIFOs do not exist, this bit is set High when an SPI transfer has completed (this option is available only in standard SPI mode). Rx_Empty and Rx_Full are complements in this case
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TX_Empty</spirit:name>
<spirit:displayName>Transmit Empty</spirit:displayName>
<spirit:description>Transmit empty.
When a transmit FIFO exists, this bit is set to High when the transmit FIFO is empty. This bit goes High as soon as the TX FIFO becomes empty. While this bit is High, the last byte of the data that is to be transmitted would still be in the pipeline.
The occupancy of the FIFO is decremented with the completion of each SPI transfer.
Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer (this option is available only in standard SPI mode). Either with or without FIFOs, this bit is cleared on an AXI write to the FIFO or transmit register. For Dual/Quad SPI mode, the FIFO is always present in the core.
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TX_Full</spirit:name>
<spirit:displayName>Transmit Full</spirit:displayName>
<spirit:description>Transmit full.
When a transmit FIFO exists, this bit is set High when the transmit FIFO is full.
Note: When FIFOs do not exist, this bit is set High when an AXI write to the transmit register has been made (this option is available only in standard SPI mode). This bit is cleared when the SPI transfer is completed
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>MODF</spirit:name>
<spirit:displayName>Mode-fault error flag</spirit:displayName>
<spirit:description>Mode-fault error flag.
This flag is set if the SS signal goes active while the SPI device is configured as a master. MODF is automatically cleared by reading the SPISR.
A Low-to-High MODF transition generates a single-cycle strobe interrupt. 0 - No error. 1 - Error condition detected
</spirit:description>
<spirit:bitOffset>4</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Mode_Select</spirit:name>
<spirit:displayName>Slave Mode Select</spirit:displayName>
<spirit:description>Slave_Mode_Select flag.
This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is activated as soon as the master SPI core asserts the chip select pin for the core.
1 - Default in standard mode.
0 - Asserted when core configured in slave mode and selected by external SPI master.
</spirit:description>
<spirit:bitOffset>5</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL_CPHA_Error</spirit:name>
<spirit:displayName>CPOL_CPHA_Error</spirit:displayName>
<spirit:description>CPOL_CPHA_Error flag.
When set to: 0 - Default. 1 - The CPOL and CPHA are set to 01 or 10. When the SPI memory is chosen as either Winbond, Micron or Spansion, and CPOL and CPHA are configured as 01 or 10, this bit is set.
These memories support CPOL=CPHA mode in 00 or in 11 mode. CPOL_CPHA_Error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface
</spirit:description>
<spirit:bitOffset>6</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_mode_error</spirit:name>
<spirit:displayName>Slave mode error</spirit:displayName>
<spirit:description>Slave mode error flag.
When set to: 1 - This bit is set when the core is configured with dual or quad SPI mode and the master is set to 0 in the control register (SPICR). 0 - Master mode is set in the control register (SPICR). Note: Quad SPI mode, only the master mode of the core is allowed. Slave mode error flag is only applicable when the core is configured either in dual or qu ad mode in legacy or enhanced AXI4 mode interface
</spirit:description>
<spirit:bitOffset>7</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>MSB_Error</spirit:name>
<spirit:displayName>MSB Error</spirit:displayName>
<spirit:description>MSB error flag.
When set to: 0 - Default. 1 - This bit is set when the core is configured to transfer the SPI transactions in either dual or quad SPI mode and LSB first bit is set in the control register (SPICR). Note: In dual/quad SPI mode, only the MSB first mode of the core is allowed. MSB error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface
</spirit:description>
<spirit:bitOffset>8</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Loopback_Error</spirit:name>
<spirit:displayName>Loopback Error</spirit:displayName>
<spirit:description>Loopback error flag.
When set to: 0 - Default. The loopback bit in the control register is at default state. 1 - When the SPI command, address, and data bits are set to be transferred in other than standard SPI protocol mode and this bit is set in control register (SPICR). Note: Loopback is only allowed when the core is configured in standard mode. Other modes setting of the bit causes an error and the interrupt bit is set in legacy or enhanced mode AXI4 interface
</spirit:description>
<spirit:bitOffset>9</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Command_Error</spirit:name>
<spirit:displayName>Command Error</spirit:displayName>
<spirit:description>Command error flag.
When set to: 0 - Default. 1 - When the core is configured in dual/quad SPI mode and the first entry in the SPI DTR FIFO (after reset) do not match with the supported command list for the particular memory, this bit is set. Note: Command error is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.
</spirit:description>
<spirit:bitOffset>10</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.SPISR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_SSR</spirit:name>
<spirit:displayName>SPI Slave Select Register</spirit:displayName>
<spirit:description>SPI Slave Select Register</spirit:description>
<spirit:addressOffset>0x70</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0xFFFF</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Selected_Slave</spirit:name>
<spirit:displayName>Selected Slave</spirit:displayName>
<spirit:description>Active-Low, one-hot encoded slave select
The slaves are numbered right to left starting at zero with the LSB. The slave numbers correspond to the indexes of signal SS
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_SS_BITS')))">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.SPI_SSR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_TXFIFO_OR</spirit:name>
<spirit:displayName>Transmit FIFO Occupancy Register</spirit:displayName>
<spirit:description>SPI Transmit FIFO Occupancy Register</spirit:description>
<spirit:addressOffset>0x74</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Occupancy_Value</spirit:name>
<spirit:displayName>Occupancy Value</spirit:displayName>
<spirit:description>The binary value plus 1 yields the occupancy.
Bit width is log(FIFO Depth).
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.SPI_TXFIFO_OR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_RXFIFO_OR</spirit:name>
<spirit:displayName>Receive FIFO Occupancy Register</spirit:displayName>
<spirit:description>SPI Receive FIFO Occupancy Register</spirit:description>
<spirit:addressOffset>0x78</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>Occupancy_Value</spirit:name>
<spirit:displayName>Occupancy Value</spirit:displayName>
<spirit:description>The binary value plus 1 yields the occupancy.
Bit width is log(FIFO Depth).
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">32</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.SPI_RXFIFO_OR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>DGIER</spirit:name>
<spirit:displayName>Device Global Interrupt Enable Register</spirit:displayName>
<spirit:description>Device Global Interrupt Enable Register</spirit:description>
<spirit:addressOffset>0x1C</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>GIE</spirit:name>
<spirit:displayName>Global Interrupt Enable</spirit:displayName>
<spirit:description>Global Interrupt Enable.
Allows passing all individually enabled interrupts to the interrupt controller.
When set to: 0 - Disabled. 1 - Enabled.
</spirit:description>
<spirit:bitOffset>31</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.DGIER" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_DTR</spirit:name>
<spirit:displayName>SPI Data Transmit Register</spirit:displayName>
<spirit:description>SPI Data Transmit Register</spirit:description>
<spirit:addressOffset>0x68</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>write-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>TX_Data</spirit:name>
<spirit:displayName>TX_Data</spirit:displayName>
<spirit:description>SPI Transmit Data.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_TRANSFER_BITS')))">8</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>write-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.SPI_DTR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>SPI_DRR</spirit:name>
<spirit:displayName>SPI Data Receive Register</spirit:displayName>
<spirit:description>SPI Data Receive Register</spirit:description>
<spirit:addressOffset>0x6C</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>RX_Data</spirit:name>
<spirit:displayName>Receive Data</spirit:displayName>
<spirit:description>SPI Receive Data
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_TRANSFER_BITS')))">8</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-only</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.SPI_DRR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>IPISR</spirit:name>
<spirit:displayName>IP Interrupt Status Register</spirit:displayName>
<spirit:description>IP Interrupt Status Register</spirit:description>
<spirit:addressOffset>0x20</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>MODF</spirit:name>
<spirit:displayName>Mode Fault Error</spirit:displayName>
<spirit:description>Mode-fault error.
This interrupt is generated if the SS signal goes active while the SPI device is configured as a master. This bit is set immediately on SS going active.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_MODF</spirit:name>
<spirit:displayName>Slave Mode Fault Error</spirit:displayName>
<spirit:description>Slave mode-fault error.
This interrupt is generated if the SS signal goes active while the SPI device is configured as a slave, but is not enabled.
This bit is set immediately on SS going active and continually set if SS is active and the device is not enabled
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DTR_Empty</spirit:name>
<spirit:displayName>Data transmit register/FIFO empty</spirit:displayName>
<spirit:description>Data transmit register/FIFO empty.
It is set when the last byte of data has been transferred out to the external flash memory.
In the context of the M68HC11 reference manual, when configured without FIFOs, this interrupt is equivalent in information content to the complement of the SPI transfer complete flag (SPIF ) interrupt bit.
In master mode if this bit is set to 1, no more SPI transfers are permitted
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DTR_Underrun</spirit:name>
<spirit:displayName>Data transmit register/FIFO underrun</spirit:displayName>
<spirit:description>Data transmit register/FIFO underrun.
This bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register when data is requested from an empty transmit register/FIFO by the SPI core logic to perform a SPI transfer.
This can occur only when the SPI device is configured as a slave in standard SPI configuration and is enabled by the SPE bit as set. All zeros are loaded in the shift register and transmitted by the slave in an under-run condition
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Full</spirit:name>
<spirit:displayName>Data receive register/FIFO full</spirit:displayName>
<spirit:description>Data receive register/FIFO full.
Without FIFOs, this bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register (An element can be a byte, half-word, or word depending on the value of Transfer Width).
With FIFOs, this bit is set at the end of the SPI element transfer, when the receive FIFO has been completely filled by a one-clock period strobe to the interrupt register.
</spirit:description>
<spirit:bitOffset>4</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Overrun</spirit:name>
<spirit:displayName>Data receive register/FIFO overrun</spirit:displayName>
<spirit:description>Data receive register/FIFO overrun.
This bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI core logic to complete a SPI transfer.
This can occur when the SPI device is in either master or slave mode (in standard SPI mode) or if the IP is configured in SPI master mode (dual or quad SPI mode).
</spirit:description>
<spirit:bitOffset>5</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TXFIFO_Half_Empty</spirit:name>
<spirit:displayName>Transmit FIFO half empty</spirit:displayName>
<spirit:description>Transmit FIFO half empty.
In standard SPI configuration, IPISR Bit[6] is the transmit FIFO half-empty interrupt.
In dual or quad SPI configuration, based on the FIFO depth, this bit is set at half-empty condition.
Note: This interrupt exists only if the AXI Quad SPI core is configured with FIFOs (In standard, dual or quad SPI mode).
</spirit:description>
<spirit:bitOffset>6</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Select_Mode</spirit:name>
<spirit:displayName>Slave Select Mode</spirit:displayName>
<spirit:description>Slave select mode.
The assertion of this bit is applicable only when the core is configured in slave mode in standard SPI configuration.
This bit is set when the other SPI master core selects the core by asserting the slave select line. This bit is set by a one-clock period strobe to the interrupt register.
Note: This bit is applicable only in standard SPI slave mode
</spirit:description>
<spirit:bitOffset>7</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Not_Empty</spirit:name>
<spirit:displayName>DRR Not Empty</spirit:displayName>
<spirit:description>DRR not empty.
The assertion of this bit is applicable only in the case where FIFO Depth is 16 or 256 and the core is configured in slave mode and standard SPI mode. This bit is set when the DRR FIFO receives the first data value during the SPI transaction.
This bit is set by a one-clock period strobe to the interrupt register when the core receives the first data beat.
Note: The assertion of this bit is applicable only when the FIFO Depth parameter is 16 or 256 and the core is configured in slave mode in standard SPI mode. When FIFO Depth is set to 0, this bit always returns 0. This bit has no significance in dual/quad mode
</spirit:description>
<spirit:bitOffset>8</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL_CPHA_Error</spirit:name>
<spirit:displayName>CPOL_CPHA Error</spirit:displayName>
<spirit:description>CPOL_CPHA error.
This flag is asserted when:
The core is configured in either dual or quad SPI mode and
The CPOL - CPHA control register bits are set to 01 or 10.
In standard SPI mode, this bit is always in default state.
</spirit:description>
<spirit:bitOffset>9</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Mode_Error</spirit:name>
<spirit:displayName>I/O mode instruction Error</spirit:displayName>
<spirit:description>I/O mode instruction error.
This flag is asserted when:
The core is configured in either dual or quad SPI mode and
The core is configured in master = 0 in control register (SPICR(2)).
In standard SPI mode, this bit is always in default state.
</spirit:description>
<spirit:bitOffset>10</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>MSB_Error</spirit:name>
<spirit:displayName>MSB Error</spirit:displayName>
<spirit:description>MSB error.
This flag is asserted when:
The core is configured in either dual or quad SPI mode and
The LSB First bit in the control register (SPICR) is set to 1.
In standard SPI mode, this bit is always in default state.
</spirit:description>
<spirit:bitOffset>11</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Loopback_Error</spirit:name>
<spirit:displayName>Loopback Error</spirit:displayName>
<spirit:description>Loopback error.
This flag is asserted when:
The core is configured in dual or quad SPI transfer mode and
The LOOP bit is set in control register (SPICR(0)).
In standard SPI mode, this bit is always in default state.
</spirit:description>
<spirit:bitOffset>12</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Command_Error</spirit:name>
<spirit:displayName>Command Error</spirit:displayName>
<spirit:description>Command error.
This flag is asserted when: The core is configured in dual/quad SPI mode and The first entry in the SPI DTR FIFO (after reset) does not match with the supported command list for particular memory. When the SPI command in DTR FIFO does not match with the internal supported command list, the core completes the SPI transactions in standard SPI format. This bit is set to show this behavior of the core.
In standard SPI mode this bit is always in default state.
</spirit:description>
<spirit:bitOffset>13</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:modifiedWriteValue>oneToToggle</spirit:modifiedWriteValue>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:vendorExtensions>
<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.IPISR" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:registerInfo>
</spirit:vendorExtensions>
</spirit:register>
<spirit:register>
<spirit:name>IPIER</spirit:name>
<spirit:displayName>IP Interrupt Enable Register</spirit:displayName>
<spirit:description>IP Interrupt Enable Register</spirit:description>
<spirit:addressOffset>0x28</spirit:addressOffset>
<spirit:size spirit:format="long">32</spirit:size>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:reset>
<spirit:value spirit:format="long">0x0</spirit:value>
</spirit:reset>
<spirit:field>
<spirit:name>MODF</spirit:name>
<spirit:displayName>Mode-fault error flag</spirit:displayName>
<spirit:description>Mode-fault error flag.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>0</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_MODF</spirit:name>
<spirit:displayName>Slave mode-fault error flag</spirit:displayName>
<spirit:description>Slave mode-fault error flag.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>1</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DTR_Empty</spirit:name>
<spirit:displayName>Data transmit register/FIFO empty</spirit:displayName>
<spirit:description>Data transmit register/FIFO empty.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>2</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DTR_Underrun</spirit:name>
<spirit:displayName>Data transmit FIFO underrun</spirit:displayName>
<spirit:description>Data transmit FIFO underrun.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>3</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Full</spirit:name>
<spirit:displayName>Data receive register/FIFO full</spirit:displayName>
<spirit:description>Data receive register/FIFO full.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>4</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Overrun</spirit:name>
<spirit:displayName>Receive FIFO overrun</spirit:displayName>
<spirit:description>Receive FIFO overrun.
0 - Disabled.
1 - Enabled.
</spirit:description>
<spirit:bitOffset>5</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>TX_FIFO_Half_Empty</spirit:name>
<spirit:displayName>Transmit FIFO half empty</spirit:displayName>
<spirit:description>Transmit FIFO half empty. 0 - Disabled. 1 - Enabled. Note: This bit is meaningful only if the AXI Quad SPI core is configured with FIFOs.
</spirit:description>
<spirit:bitOffset>6</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Select_Mode</spirit:name>
<spirit:displayName>Slave_Select_Mode</spirit:displayName>
<spirit:description>Slave_Select_Mode. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in slave mode by selecting the active-Low status on spisel.
In master mode, setting this bit has no effect.
</spirit:description>
<spirit:bitOffset>7</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>DRR_Not_Empty</spirit:name>
<spirit:displayName>DRR_Not_Empty</spirit:displayName>
<spirit:description>DRR_Not_Empty. 0 - Disabled. 1 - Enabled. Note: The setting of this bit is applicable only when FIFO Depth is set to 1 and the core is configured in slave mode of standard SPI mode.
If FIFO Depth is set to 0, the setting of this bit has no effect. This is allowed only in standard SPI configuration. It means this bit is not set in the IPIER register. Therefore, this bit should only be used when FIFO Depth is set to 1 and when the core is configured in slave mode.
This bit has no significance in dual or quad mode.
</spirit:description>
<spirit:bitOffset>8</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>CPOL_CPHA_Error</spirit:name>
<spirit:displayName>CPOL_CPHA error</spirit:displayName>
<spirit:description>CPOL_CPHA error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>9</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Slave_Mode_Error</spirit:name>
<spirit:displayName>Slave_Mode_Error</spirit:displayName>
<spirit:description>I/O mode instruction error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>10</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>MSB_Error</spirit:name>
<spirit:displayName>MSB_Error</spirit:displayName>
<spirit:description>MSB_Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>11</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Loopback_Error</spirit:name>
<spirit:displayName>Loopback Error</spirit:displayName>
<spirit:description>Loopback Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>12</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
<spirit:field>
<spirit:name>Command_Error</spirit:name>
<spirit:displayName>Command_Error</spirit:displayName>
<spirit:description>Command_Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.
</spirit:description>
<spirit:bitOffset>13</spirit:bitOffset>
<spirit:bitWidth spirit:format="long">1</spirit:bitWidth>
<spirit:volatile>true</spirit:volatile>
<spirit:access>read-write</spirit:access>
<spirit:writeValueConstraint>
<spirit:minimum>0</spirit:minimum>
<spirit:maximum>0</spirit:maximum>
</spirit:writeValueConstraint>
<spirit:testable spirit:testConstraint="unconstrained">false</spirit:testable>
</spirit:field>
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<xilinx:registerInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="REGISTER_ENABLEMENT.AXI_LITE.REG.IPIER" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE'))=0)">true</xilinx:isEnabled>
</xilinx:enablement>
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</spirit:register>
<spirit:vendorExtensions>
<xilinx:addressBlockInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="ADDRBLOCK_ENABLEMENT.AXI_LITE.Reg" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE')) = 0 or spirit:decode(id('MODELPARAM_VALUE.C_XIP_MODE')) = 1">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:addressBlockInfo>
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</spirit:memoryMap>
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<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:fileSetRef>
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<spirit:parameters>
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<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_1_memory_0_mixed.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_1_memory_1_wb.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_1_memory_2_nm.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_1_memory_4_mx.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_2_memory_0_mixed.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_2_memory_1_wb.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_2_memory_2_nm.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_2_memory_4_mx.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_2_memory_3_sp.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>netlist/mode_1_memory_3_sp.mem</spirit:name>
<spirit:userFileType>mem</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/axi_quad_spi_v3_2_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>axi_quad_spi_v3_2_24</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>sim/xlnx_axi_quad_spi.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xlnx_axi_quad_spi_board.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_board</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>doc/axi_quad_spi_v3_2_changelog.txt</spirit:name>
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>xlnx_axi_quad_spi.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>xlnx_axi_quad_spi_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>xlnx_axi_quad_spi_stub.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>xlnx_axi_quad_spi_sim_netlist.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>xlnx_axi_quad_spi_sim_netlist.vhdl</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
</spirit:fileSets>
<spirit:description>SPI Interface for SPI Based Slave</spirit:description>
<spirit:parameters>
<spirit:parameter>
<spirit:name>C_SPI_MEMORY</spirit:name>
<spirit:displayName>SPI Memory</spirit:displayName>
<spirit:description>This parameter should be set for tagetting the SPI flash memory. Please refer PG for more reference. Allowed values are 0= Mixed Flash, 1= Winbond SPI Flash, 2= Micron SPI Flash(Numonyx), 3= Spansion SPI Flash, 4= Macronix SPI Flash.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SPI_MEMORY" spirit:choiceRef="choice_pairs_b1f7d961" spirit:order="40">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_SPI_MEMORY">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_USE_STARTUP</spirit:name>
<spirit:displayName>Use STARTUPE2 Primitive</spirit:displayName>
<spirit:description>This parameter should be set when the targeted FPGA have STARTUPE2 primitive for routing the SPI clock. Please refer PG for more reference. Allowed values are 0= STARTUP is not included, 1= STARTUP is included. Example Design is not supported when STARTUPE2 primitive is chosen in the design.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_STARTUP" spirit:choiceRef="choice_pairs_4873554b" spirit:order="70">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_STARTUP">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_USE_STARTUP_INT</spirit:name>
<spirit:displayName>STARTUP Primitive Usage</spirit:displayName>
<spirit:description>This parameter will determine if the STARTUP primitive is instantiated with-in IP or outside</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_USE_STARTUP_INT" spirit:choiceRef="choice_pairs_9f49441c" spirit:order="71" spirit:configGroups="1 UnGrouped">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_USE_STARTUP_INT">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_SPI_MODE</spirit:name>
<spirit:displayName>SPI Mode</spirit:displayName>
<spirit:description>This parameter should be set while choosing the SPI mode of the core. Please refer PG for more reference. Allowed values are 0= Standard SPI mode, 1= Dual SPI mode, 2= Quad SPI mode.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SPI_MODE" spirit:choiceRef="choice_pairs_c8de7e7d" spirit:order="29" spirit:configGroups="0 UnGrouped">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_SPI_MODE">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_NUM_TRANSFER_BITS</spirit:name>
<spirit:displayName>Num Transfer Bits</spirit:displayName>
<spirit:description>This parameter should be set while choosing the no. of bits in single SPI transaction. Please refer PG for more reference. Allowed values are 8 or 16 or 32. The Standard SPI mode supports all the three values while Dual and Quad SPI mode supports only the 8-bit transfer mode.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_TRANSFER_BITS" spirit:choiceRef="choice_list_8112d406" spirit:order="60">8</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_TRANSFER_BITS">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_DUAL_QUAD_MODE</spirit:name>
<spirit:displayName>Dual Quad Mode</spirit:displayName>
<spirit:description>This parameter should be set to access two flash in a mux fashion.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_DUAL_QUAD_MODE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="9">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_DUAL_QUAD_MODE">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_NUM_SS_BITS</spirit:name>
<spirit:displayName>No. of Slave Select Bits</spirit:displayName>
<spirit:description>This parameter should be set to choose the no. SPI slave memories in design. This parameter decides the length of Slave Select port width of the core.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_SS_BITS" spirit:order="80" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_NUM_SS_BITS">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_SCK_RATIO</spirit:name>
<spirit:displayName>SCK Ratio</spirit:displayName>
<spirit:description>This parameter should be set while choosing the division ratio for SPI clock. Please refer PG for more reference. Standard SPI mode has variable values for division ratio for SPI clock, while Dual and Quad mode allows only 2. XIP mode also allows division ratio of 2.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SCK_RATIO" spirit:choiceRef="choice_list_552a89ba" spirit:order="90">4</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_SCK_RATIO">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_FIFO_DEPTH</spirit:name>
<spirit:displayName>FIFO Depth</spirit:displayName>
<spirit:description>This parameter should be set while choosing FIFO depth. Please refer PG for more reference. Standard SPI mode provides the choice 0 or 16 or 256 beat FIFO depth, while Dual and Quad mode provides options of 16 or 256 beat FIFO depth.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_FIFO_DEPTH" spirit:choiceRef="choice_list_0051c444" spirit:order="100">256</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FIFO_DEPTH">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_XIP_MODE</spirit:name>
<spirit:displayName>XIP Mode</spirit:displayName>
<spirit:description>This parameter should be set while choosing the core to operate in eXecute In Place (XIP) mode. Please refer PG for more reference.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_XIP_MODE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="10">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_XIP_MODE">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_BYTE_LEVEL_INTERRUPT_EN</spirit:name>
<spirit:displayName>BYTE_LEVEL_INTERRUPT_EN</spirit:displayName>
<spirit:description>On Enabling this parameter, DRR NOT Empty Interrupt will be triggered on byte level basis instead of transaction level. Please refer PG for more reference.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_BYTE_LEVEL_INTERRUPT_EN" spirit:choiceRef="choice_pairs_4873554b" spirit:order="10">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_BYTE_LEVEL_INTERRUPT_EN">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_XIP_PERF_MODE</spirit:name>
<spirit:displayName>XIP Performance Mode</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_XIP_PERF_MODE" spirit:choiceRef="choice_pairs_b207e870" spirit:order="101">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_XIP_PERF_MODE">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_SPI_MEM_ADDR_BITS</spirit:name>
<spirit:displayName>XIP Mode Memory Addressing Bits</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SPI_MEM_ADDR_BITS" spirit:choiceRef="choice_list_83cf9db9" spirit:order="11">24</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_SPI_MEM_ADDR_BITS">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_FAMILY</spirit:name>
<spirit:displayName>Sub Mode</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_FAMILY" spirit:order="7">kintex7</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_FAMILY">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>UC_FAMILY</spirit:name>
<spirit:displayName>Sub Mode</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.UC_FAMILY" spirit:choiceRef="choice_list_8af5a703" spirit:order="8">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.UC_FAMILY">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_SHARED_STARTUP</spirit:name>
<spirit:displayName>Share the un-used startup ports</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SHARED_STARTUP" spirit:choiceRef="choice_list_8af5a703" spirit:order="100011">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_SHARED_STARTUP">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_SUB_FAMILY</spirit:name>
<spirit:displayName>Sub Mode</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_SUB_FAMILY" spirit:order="10000">kintex7</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_SUB_FAMILY">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_TYPE_OF_AXI4_INTERFACE</spirit:name>
<spirit:displayName>Type Of AXI4 Interface</spirit:displayName>
<spirit:description>This parameter should be set while choosing the type of AXI bus interface.Please refer PG for more reference. Allowed values are 0= AXI4 Lite Interface, 1= AXI4 Memory Mapped Interface.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE" spirit:choiceRef="choice_pairs_4873554b" spirit:order="20">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_TYPE_OF_AXI4_INTERFACE">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_INSTANCE</spirit:name>
<spirit:displayName>C Instance</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.C_INSTANCE" spirit:order="10001">axi_quad_spi_inst</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_INSTANCE">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Component_Name</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">xlnx_axi_quad_spi</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Master_mode</spirit:name>
<spirit:displayName>Enable Master Mode</spirit:displayName>
<spirit:description>This parameter should be set while choosing the core in Standard SPI mode. Please refer PG for more reference. Standard SPI mode can operate in Master SPI or Slave SPI mode, while Dual and Quad mode operates only in Master SPI mode.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Master_mode" spirit:choiceRef="choice_pairs_4873554b" spirit:order="200">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Master_mode">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FIFO_INCLUDED</spirit:name>
<spirit:displayName>Enable FIFO</spirit:displayName>
<spirit:description>This parameter should be set while choosing to include the FIFO in the design or notPlease refer PG for more reference. This parameter can be set only in Standard SPI mode where choice of FIFO inclusion or exclusion is provided. In case of Dual and Quad SPI modes the FIFO inclusion is mandatory.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FIFO_INCLUDED" spirit:choiceRef="choice_pairs_4873554b" spirit:order="30">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.FIFO_INCLUDED">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Multiples16</spirit:name>
<spirit:displayName>Multiples16</spirit:displayName>
<spirit:description>This parameter should be set while choosing the SPI clock in Standard SPI mode. Please refer PG for more reference.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Multiples16" spirit:order="150" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Multiples16">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_SCK_RATIO1</spirit:name>
<spirit:displayName>C Sck Ratio1</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SCK_RATIO1" spirit:order="3000" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_SCK_RATIO1">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>Async_Clk</spirit:name>
<spirit:displayName>Enable Async Clock Mode</spirit:displayName>
<spirit:description>This parameter should be set while choosing the core to be used in Standalone mode and if clocks to core are different.</spirit:description>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Async_Clk" spirit:choiceRef="choice_pairs_4873554b" spirit:order="2000">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Async_Clk">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S_AXI4_BASEADDR</spirit:name>
<spirit:displayName>C S Axi4 Base Address</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI4_BASEADDR" spirit:order="30000" spirit:configGroups="1 Addresses" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI4_BASEADDR">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S_AXI4_HIGHADDR</spirit:name>
<spirit:displayName>C S Axi4 High Address</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI4_HIGHADDR" spirit:order="40000" spirit:configGroups="1 Addresses" spirit:bitStringLength="32">0x00000000</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI4_HIGHADDR">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>USE_BOARD_FLOW</spirit:name>
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="38">false</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.USE_BOARD_FLOW">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>QSPI_BOARD_INTERFACE</spirit:name>
<spirit:displayName>QSPI Board Interface</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.QSPI_BOARD_INTERFACE" spirit:choiceRef="choice_list_86c70e21" spirit:order="39">Custom</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.QSPI_BOARD_INTERFACE">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_S_AXI4_ID_WIDTH</spirit:name>
<spirit:displayName>C S Axi4 Id Width</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI4_ID_WIDTH" spirit:order="40" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">0</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_S_AXI4_ID_WIDTH">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>C_SELECT_XPM</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_SELECT_XPM" spirit:choiceRef="choice_list_6727dfa6" spirit:order="40">0</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>AXI Quad SPI</xilinx:displayName>
<xilinx:xpmLibraries>
<xilinx:xpmLibrary>XPM_FIFO</xilinx:xpmLibrary>
<xilinx:xpmLibrary>XPM_MEMORY</xilinx:xpmLibrary>
<xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
</xilinx:xpmLibraries>
<xilinx:coreRevision>24</xilinx:coreRevision>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_FULL.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_FULL.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_FULL.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_FULL.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_FULL.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_FULL.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_FULL.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_FULL.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_FIFO_DEPTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_SCK_RATIO" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_S_AXI4_ID_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_TYPE_OF_AXI4_INTERFACE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_USE_STARTUP" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="d1bcc2b1"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="00000000"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d642462f"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="b1ee07ff"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5b4e6d06"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="24fbdc2f"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
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