name
stringlengths 1
473k
| code
stringlengths 7
647k
| asm
stringlengths 4
3.39M
| file
stringlengths 8
196
|
|---|---|---|---|
printVectorListFour
|
static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
{
// Normally, it's not safe to use register enum values directly with
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat0(O, "{");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
MI->flat_insn->detail->arm.op_count++;
}
SStream_concat0(O, "}");
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
leaq 0x76a98(%rip), %rsi # 0xd4f74
movq %rdx, %rdi
callq 0x44686
movq 0x320(%r14), %r15
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
movl %eax, %edi
callq *0x80(%r15)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%r14), %rax
cmpl $0x0, 0x68(%rax)
je 0x5e579
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x1, 0x64(%rax,%rcx,8)
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x50(%rcx), %edx
leaq (%rdx,%rdx,4), %rdx
movl %eax, 0x68(%rcx,%rdx,8)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
leaq 0x76ac2(%rip), %rsi # 0xd5042
movq %rbx, %rdi
callq 0x44686
movq 0x320(%r14), %r15
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
leal 0x1(%rax), %edi
callq *0x80(%r15)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%r14), %rax
cmpl $0x0, 0x68(%rax)
je 0x5e620
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x1, 0x64(%rax,%rcx,8)
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
incl %eax
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x50(%rcx), %edx
leaq (%rdx,%rdx,4), %rdx
movl %eax, 0x68(%rcx,%rdx,8)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
leaq 0x76a1b(%rip), %rsi # 0xd5042
movq %rbx, %rdi
callq 0x44686
movq 0x320(%r14), %r15
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
leal 0x2(%rax), %edi
callq *0x80(%r15)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%r14), %rax
cmpl $0x0, 0x68(%rax)
je 0x5e6c8
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x1, 0x64(%rax,%rcx,8)
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
addl $0x2, %eax
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x50(%rcx), %edx
leaq (%rdx,%rdx,4), %rdx
movl %eax, 0x68(%rcx,%rdx,8)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
leaq 0x76973(%rip), %rsi # 0xd5042
movq %rbx, %rdi
callq 0x44686
movq 0x320(%r14), %r15
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
leal 0x3(%rax), %edi
callq *0x80(%r15)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%r14), %rax
cmpl $0x0, 0x68(%rax)
je 0x5e770
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x1, 0x64(%rax,%rcx,8)
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
addl $0x3, %eax
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x50(%rcx), %edx
leaq (%rdx,%rdx,4), %rdx
movl %eax, 0x68(%rcx,%rdx,8)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
leaq 0xe87b1(%rip), %rsi # 0x146f28
movq %rbx, %rdi
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x44686
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
|
printAddrMode6Operand
|
static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
unsigned tmp;
SStream_concat0(O, "[");
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
tmp = (unsigned int)MCOperand_getImm(MO2);
if (tmp) {
if (tmp << 3 > HEX_THRESHOLD)
SStream_concat(O, ":0x%x", (tmp << 3));
else
SStream_concat(O, ":%u", (tmp << 3));
if (MI->csh->detail)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3;
}
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
callq 0x445a8
movq %rax, %r12
incl %ebp
movq %rbx, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %r15
leaq 0x7ed8c(%rip), %rsi # 0xddd83
movq %r14, %rdi
callq 0x44686
movq %rbx, %rdi
movl $0x1, %esi
callq 0x606ad
movq 0x320(%rbx), %r13
movq %r12, %rdi
callq 0x445fe
movl %eax, %edi
callq *0x80(%r13)
movq %r14, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x5f05e
movq %r12, %rdi
callq 0x445fe
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x50(%rcx), %edx
leaq (%rdx,%rdx,4), %rdx
movl %eax, 0x68(%rcx,%rdx,8)
movq %r15, %rdi
callq 0x44606
movq %rax, %r15
testl %r15d, %r15d
je 0x5f0bd
shll $0x3, %r15d
cmpl $0xa, %r15d
leaq 0x76178(%rip), %rax # 0xd51f5
leaq 0x76177(%rip), %rsi # 0xd51fb
cmovaeq %rax, %rsi
movq %r14, %rdi
movl %r15d, %edx
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x5f0bd
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl %r15d, 0x74(%rax,%rcx,8)
leaq 0x7f8b6(%rip), %rsi # 0xde97a
movq %r14, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x3, 0x68(%rax)
jne 0x5f0ee
movb $0x0, 0x70(%rax)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
|
printAddrModeTBH
|
static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, Op);
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
SStream_concat0(O, "[");
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat0(O, ", ");
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
SStream_concat0(O, ", lsl #1]");
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1;
}
set_mem_access(MI, false);
}
|
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %rsi, %r14
movq %rdi, %rbx
xorl %esi, %esi
callq 0x445a8
movq %rax, %r12
movq %rbx, %rdi
movl $0x1, %esi
callq 0x445a8
movq %rax, %r15
leaq 0x7da76(%rip), %rsi # 0xddd83
movq %r14, %rdi
callq 0x44686
movq %rbx, %rdi
movl $0x1, %esi
callq 0x606ad
movq 0x320(%rbx), %r13
movq %r12, %rdi
callq 0x445fe
movl %eax, %edi
callq *0x80(%r13)
movq %r14, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x60374
movq %r12, %rdi
callq 0x445fe
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x50(%rcx), %edx
leaq (%rdx,%rdx,4), %rdx
movl %eax, 0x68(%rcx,%rdx,8)
leaq 0x74cc7(%rip), %rsi # 0xd5042
movq %r14, %rdi
callq 0x44686
movq 0x320(%rbx), %r12
movq %r15, %rdi
callq 0x445fe
movl %eax, %edi
callq *0x80(%r12)
movq %r14, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x603d6
movq %r15, %rdi
callq 0x445fe
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x50(%rcx), %edx
leaq (%rdx,%rdx,4), %rdx
movl %eax, 0x6c(%rcx,%rdx,8)
leaq 0x74e33(%rip), %rsi # 0xd5210
movq %r14, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x60450
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x2, 0x5c(%rax,%rcx,8)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x1, 0x60(%rax,%rcx,8)
movq 0x320(%rbx), %rax
cmpl $0x3, 0x68(%rax)
jne 0x60450
movb $0x0, 0x70(%rax)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
|
printFBits32
|
static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned tmp;
tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (tmp > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", tmp);
else
SStream_concat(O, "#%u", tmp);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
MI->flat_insn->detail->arm.op_count++;
}
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rsi, %r14
movq %rdi, %rbx
movl $0x2, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movl $0x20, %ebp
subl %eax, %ebp
cmpl $0xa, %ebp
leaq 0x749b1(%rip), %rax # 0xd5136
leaq 0x749b2(%rip), %rsi # 0xd513e
cmovaeq %rax, %rsi
movq %r14, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x607f2
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x2, 0x64(%rax,%rcx,8)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl %ebp, 0x68(%rax,%rcx,8)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
|
printBitfieldInvMaskImmOperand
|
static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
int32_t lsb = CountTrailingZeros_32(v);
int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
//assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
if (lsb > HEX_THRESHOLD)
SStream_concat(O, "#0x%x", lsb);
else
SStream_concat(O, "#%u", lsb);
if (width > HEX_THRESHOLD)
SStream_concat(O, ", #0x%x", width);
else
SStream_concat(O, ", #%u", width);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
MI->flat_insn->detail->arm.op_count++;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
MI->flat_insn->detail->arm.op_count++;
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rdx, %r14
movq %rdi, %rbx
callq 0x445a8
movq %rax, %rdi
callq 0x44606
xorl $-0x1, %eax
movl $0x20, %r12d
movl $0x20, %ebp
je 0x60906
bsfl %eax, %ebp
testl %eax, %eax
je 0x60912
bsrl %eax, %r12d
xorl $0x1f, %r12d
addl %ebp, %r12d
movl $0x20, %r15d
subl %r12d, %r15d
cmpl $0xa, %ebp
leaq 0x7480e(%rip), %rax # 0xd5136
leaq 0x7480f(%rip), %rsi # 0xd513e
cmovaeq %rax, %rsi
movq %r14, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq 0x446cd
cmpl $0x17, %r12d
leaq 0x747ea(%rip), %rax # 0xd5134
leaq 0x747eb(%rip), %rsi # 0xd513c
cmovbq %rax, %rsi
movq %r14, %rdi
movl %r15d, %edx
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x60a03
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x2, %edx
movl %edx, 0x64(%rax,%rcx,8)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl %ebp, 0x68(%rax,%rcx,8)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl %edx, 0x64(%rax,%rcx,8)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl %r15d, 0x68(%rax,%rcx,8)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
|
printT2SOOperand
|
static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
unsigned Reg = MCOperand_getReg(MO1);
printRegName(MI->csh, O, Reg);
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
MI->flat_insn->detail->arm.op_count++;
}
// Print the shift opc.
//assert(MO2.isImm() && "Not a valid t2_so_reg value!");
printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
callq 0x445a8
movq %rax, %r12
incl %ebp
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %r15
movq %r12, %rdi
callq 0x445fe
movl %eax, %ebp
movq 0x320(%r14), %rax
movl %ebp, %edi
callq *0x80(%rax)
movq %rbx, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%r14), %rax
cmpl $0x0, 0x68(%rax)
je 0x610d2
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x1, 0x64(%rax,%rcx,8)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl %ebp, 0x68(%rax,%rcx,8)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
movq %r15, %rdi
callq 0x44606
movq %rax, %r12
andl $0x7, %r12d
movq %r15, %rdi
callq 0x44606
shrl $0x3, %eax
movq %r14, %rdi
movq %rbx, %rsi
movl %r12d, %edx
movl %eax, %ecx
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
jmp 0x62097
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
|
printRotImmOperand
|
static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
if (Imm == 0)
return;
SStream_concat0(O, ", ror #");
switch (Imm) {
default: //assert (0 && "illegal ror immediate!");
case 1: SStream_concat0(O, "8"); break;
case 2: SStream_concat0(O, "16"); break;
case 3: SStream_concat0(O, "24"); break;
}
if (MI->csh->detail) {
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
}
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r15
movq %rdi, %rbx
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movq %rax, %r14
testl %r14d, %r14d
je 0x61677
leaq 0x73c6e(%rip), %rsi # 0xd5266
movq %r15, %rdi
callq 0x44686
cmpl $0x2, %r14d
leaq 0x7d2e9(%rip), %rax # 0xde8f4
leaq 0x7d2cb(%rip), %rcx # 0xde8dd
cmoveq %rax, %rcx
cmpl $0x3, %r14d
leaq 0x7d15d(%rip), %rsi # 0xde77e
cmovneq %rcx, %rsi
movq %r15, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x61677
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl $0x4, 0x34(%rax,%rcx,8)
shll $0x3, %r14d
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl %r14d, 0x38(%rax,%rcx,8)
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
|
printT2AddrModeImm8s4Operand
|
static void printT2AddrModeImm8s4Operand(MCInst *MI,
unsigned OpNum, SStream *O, bool AlwaysPrintImm0)
{
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
int32_t OffImm;
bool isSub;
if (!MCOperand_isReg(MO1)) { // For label symbolic references.
printOperand(MI, OpNum, O);
return;
}
SStream_concat0(O, "[");
set_mem_access(MI, true);
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
OffImm = (int32_t)MCOperand_getImm(MO2);
isSub = OffImm < 0;
//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
// Don't print +0.
if (OffImm == INT32_MIN)
OffImm = 0;
if (isSub) {
SStream_concat(O, ", #-0x%x", -OffImm);
} else if (AlwaysPrintImm0 || OffImm > 0) {
if (OffImm > HEX_THRESHOLD)
SStream_concat(O, ", #0x%x", OffImm);
else
SStream_concat(O, ", #%u", OffImm);
}
if (MI->csh->detail)
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %ecx, %ebp
movq %rdx, %r14
movl %esi, %r13d
movq %rdi, %rbx
callq 0x445a8
movq %rax, %r12
leal 0x1(%r13), %esi
movq %rbx, %rdi
callq 0x445a8
movq %rax, %r15
movq %r12, %rdi
callq 0x445e6
testb %al, %al
je 0x61dd9
leaq 0x7c042(%rip), %rsi # 0xddd83
movq %r14, %rdi
callq 0x44686
movq %rbx, %rdi
movl $0x1, %esi
callq 0x606ad
movq 0x320(%rbx), %r13
movq %r12, %rdi
callq 0x445fe
movl %eax, %edi
callq *0x80(%r13)
movq %r14, %rdi
movq %rax, %rsi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x61da8
movq %r12, %rdi
callq 0x445fe
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x50(%rcx), %edx
leaq (%rdx,%rdx,4), %rdx
movl %eax, 0x68(%rcx,%rdx,8)
movq %r15, %rdi
callq 0x44606
xorl %r15d, %r15d
movl %eax, %ecx
negl %ecx
cmovnol %eax, %r15d
testl %eax, %eax
js 0x61df5
sete %cl
xorb $0x1, %bpl
testb %bpl, %cl
jne 0x61e19
cmpl $0xa, %eax
jb 0x61e06
leaq 0x7335d(%rip), %rsi # 0xd5134
jmp 0x61e0d
movq %rbx, %rdi
movl %r13d, %esi
movq %r14, %rdx
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x5ca57
movl %r15d, %edx
negl %edx
leaq 0x73323(%rip), %rsi # 0xd5124
movq %r14, %rdi
jmp 0x61e12
leaq 0x7332f(%rip), %rsi # 0xd513c
movq %r14, %rdi
movl %eax, %edx
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x61e41
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x50(%rax), %ecx
leaq (%rcx,%rcx,4), %rcx
movl %r15d, 0x74(%rax,%rcx,8)
leaq 0x7cb32(%rip), %rsi # 0xde97a
movq %r14, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x3, 0x68(%rax)
jne 0x61e72
movb $0x0, 0x70(%rax)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x50(%rax)
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMInstPrinter.c
|
ARM_reg_name
|
const char *ARM_reg_name(csh handle, unsigned int reg)
{
#ifndef CAPSTONE_DIET
if (reg >= ARM_REG_ENDING)
return NULL;
return reg_name_maps[reg].name;
#else
return NULL;
#endif
}
|
cmpl $0x6e, %esi
jbe 0x6231c
xorl %eax, %eax
retq
movl %esi, %eax
shlq $0x4, %rax
leaq 0x1205e7(%rip), %rcx # 0x182910
movq 0x8(%rax,%rcx), %rax
retq
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMMapping.c
|
ARM_blx_to_arm_mode
|
bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) {
int i;
for (i = 0; insn_blx_rel_to_arm[i]; i++)
if (id == insn_blx_rel_to_arm[i])
return true;
// not found
return false;
}
|
cmpl $0xa90, %esi # imm = 0xA90
sete %al
retq
nopl (%rax)
|
/sidneyp[P]capstone-tricore/arch/ARM/ARMMapping.c
|
DecodeTestAndBranch
|
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
uint64_t Addr, void *Decoder)
{
uint32_t Rt = fieldFromInstruction(insn, 0, 5);
uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5;
int32_t dst = fieldFromInstruction(insn, 5, 14);
bit |= fieldFromInstruction(insn, 19, 5);
// Sign-extend 14-bit immediate.
if (dst & (1 << (14 - 1)))
dst |= ~((1LL << 14) - 1);
if (fieldFromInstruction(insn, 31, 1) == 0)
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
else
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
MCOperand_CreateImm0(Inst, bit);
//if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
MCOperand_CreateImm0(Inst, dst);
return Success;
}
|
pushq %rbp
pushq %r14
pushq %rbx
movl %esi, %r14d
movq %rdi, %rbx
movl %esi, %eax
andl $0x1f, %eax
testl %esi, %esi
leaq 0x703c2(%rip), %rcx # 0xd6640
leaq 0x704bb(%rip), %rdx # 0xd6740
cmovnsq %rcx, %rdx
movl (%rdx,%rax,4), %esi
callq 0x44631
movl %r14d, %ebp
shll $0xd, %ebp
sarl $0x1f, %ebp
movl %r14d, %eax
shrl $0x5, %eax
andl $0x3fff, %eax # imm = 0x3FFF
andl $0xffffc000, %ebp # imm = 0xFFFFC000
orl %eax, %ebp
movl %r14d, %eax
shrl $0x13, %eax
andl $0x1f, %eax
shrl $0x1a, %r14d
andl $-0x20, %r14d
orl %eax, %r14d
movq %rbx, %rdi
movq %r14, %rsi
callq 0x4465e
movslq %ebp, %rsi
movq %rbx, %rdi
popq %rbx
popq %r14
popq %rbp
jmp 0x4465e
|
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64Disassembler.c
|
AArch64_printInst
|
void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
{
// Check for special encodings and print the canonical alias instead.
unsigned Opcode = MCInst_getOpcode(MI);
int LSB;
int Width;
char *mnem;
if (Opcode == AArch64_SYSxt && printSysAlias(MI, O))
return;
// SBFM/UBFM should print to a nicer aliased form if possible.
if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri ||
Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) {
MCOperand *Op0 = MCInst_getOperand(MI, 0);
MCOperand *Op1 = MCInst_getOperand(MI, 1);
MCOperand *Op2 = MCInst_getOperand(MI, 2);
MCOperand *Op3 = MCInst_getOperand(MI, 3);
bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri);
bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri);
if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) {
char *AsmMnemonic = NULL;
switch (MCOperand_getImm(Op3)) {
default:
break;
case 7:
if (IsSigned)
AsmMnemonic = "sxtb";
else if (!Is64Bit)
AsmMnemonic = "uxtb";
break;
case 15:
if (IsSigned)
AsmMnemonic = "sxth";
else if (!Is64Bit)
AsmMnemonic = "uxth";
break;
case 31:
// *xtw is only valid for signed 64-bit operations.
if (Is64Bit && IsSigned)
AsmMnemonic = "sxtw";
break;
}
if (AsmMnemonic) {
SStream_concat(O, "%s\t%s, %s", AsmMnemonic,
getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1));
MI->flat_insn->detail->arm64.op_count++;
}
MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
return;
}
}
// All immediate shifts are aliases, implemented using the Bitfield
// instruction. In all cases the immediate shift amount shift must be in
// the range 0 to (reg.size -1).
if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) {
char *AsmMnemonic = NULL;
int shift = 0;
int immr = (int)MCOperand_getImm(Op2);
int imms = (int)MCOperand_getImm(Op3);
if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
AsmMnemonic = "lsl";
shift = 31 - imms;
} else if (Opcode == AArch64_UBFMXri && imms != 0x3f &&
((imms + 1 == immr))) {
AsmMnemonic = "lsl";
shift = 63 - imms;
} else if (Opcode == AArch64_UBFMWri && imms == 0x1f) {
AsmMnemonic = "lsr";
shift = immr;
} else if (Opcode == AArch64_UBFMXri && imms == 0x3f) {
AsmMnemonic = "lsr";
shift = immr;
} else if (Opcode == AArch64_SBFMWri && imms == 0x1f) {
AsmMnemonic = "asr";
shift = immr;
} else if (Opcode == AArch64_SBFMXri && imms == 0x3f) {
AsmMnemonic = "asr";
shift = immr;
}
if (AsmMnemonic) {
SStream_concat(O, "%s\t%s, %s, ", AsmMnemonic,
getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
printInt32Bang(O, shift);
MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift;
MI->flat_insn->detail->arm64.op_count++;
}
return;
}
}
// SBFIZ/UBFIZ aliases
if (MCOperand_getImm(Op2) > MCOperand_getImm(Op3)) {
SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"),
getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2)));
SStream_concat0(O, ", ");
printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1);
MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz"));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op3) + 1;
MI->flat_insn->detail->arm64.op_count++;
}
return;
}
// Otherwise SBFX/UBFX is the preferred form
SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"),
getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName));
printInt32Bang(O, (int)MCOperand_getImm(Op2));
SStream_concat0(O, ", ");
printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1);
MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx"));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op2);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1;
MI->flat_insn->detail->arm64.op_count++;
}
return;
}
if (Opcode == AArch64_BFMXri || Opcode == AArch64_BFMWri) {
MCOperand *Op0 = MCInst_getOperand(MI, 0); // Op1 == Op0
MCOperand *Op2 = MCInst_getOperand(MI, 2);
int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3));
int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4));
// BFI alias
if (ImmS < ImmR) {
int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32;
LSB = (BitWidth - ImmR) % BitWidth;
Width = ImmS + 1;
SStream_concat(O, "bfi\t%s, %s, ",
getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName));
printInt32Bang(O, LSB);
SStream_concat0(O, ", ");
printInt32Bang(O, Width);
MCInst_setOpcodePub(MI, AArch64_map_insn("bfi"));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
MI->flat_insn->detail->arm64.op_count++;
}
return;
}
LSB = ImmR;
Width = ImmS - ImmR + 1;
// Otherwise BFXIL the preferred form
SStream_concat(O, "bfxil\t%s, %s, ",
getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName),
getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName));
printInt32Bang(O, LSB);
SStream_concat0(O, ", ");
printInt32Bang(O, Width);
MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil"));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
MI->flat_insn->detail->arm64.op_count++;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
MI->flat_insn->detail->arm64.op_count++;
}
return;
}
mnem = printAliasInstr(MI, O, Info);
if (mnem) {
MCInst_setOpcodePub(MI, AArch64_map_insn(mnem));
cs_mem_free(mnem);
} else {
printInstruction(MI, O, Info);
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
callq 0x445a1
cmpl $0x7c2, %eax # imm = 0x7C2
jne 0x6693f
movq %rbx, (%rsp)
movq %r12, 0x10(%rsp)
movq %r13, %rdi
xorl %esi, %esi
callq 0x445a8
movq %rax, %r14
movq %r13, %rdi
movl $0x1, %esi
callq 0x445a8
movq %rax, %r15
movq %r13, %rdi
movl $0x2, %esi
callq 0x445a8
movq %rax, %r12
movq %r13, 0x20(%rsp)
movq %r13, %rdi
movl $0x3, %esi
callq 0x445a8
movq %rax, %rbx
movq %r14, %rdi
callq 0x44606
movq %rax, %r13
movq %r15, %rdi
callq 0x44606
movq %rax, %rbp
movq %r12, %rdi
callq 0x44606
movq %rax, %r14
movq %rbx, %rdi
callq 0x44606
movq %rax, %r15
cmpl $0x8, %ebp
je 0x66a41
cmpl $0x7, %ebp
jne 0x67b55
decl %r14d
cmpl $0xd, %r14d
ja 0x67b55
leaq 0x706dc(%rip), %rax # 0xd6ff0
movslq (%rax,%r14,4), %rcx
addq %rax, %rcx
jmpq *%rcx
orl %r15d, %r13d
jne 0x67b55
movl $0x1c0, %esi # imm = 0x1C0
movl $0x1, %r14d
xorl %ebx, %ebx
leaq 0x771e7(%rip), %r12 # 0xddb21
jmp 0x67510
movl %eax, %r15d
movl %eax, %ebp
andl $-0x2, %ebp
leal -0x81e(%r15), %eax
cmpl $0x2, %eax
jb 0x66963
leal -0x500(%r15), %eax
cmpl $0x1, %eax
ja 0x66a94
cmpl $0x81f, %r15d # imm = 0x81F
sete 0xe(%rsp)
cmpl $0x501, %r15d # imm = 0x501
sete 0xf(%rsp)
movq %r13, %rdi
xorl %esi, %esi
callq 0x445a8
movq %rax, (%rsp)
movq %r13, %rdi
movl $0x1, %esi
callq 0x445a8
movq %rax, %rbx
movq %r13, %rdi
movl $0x2, %esi
callq 0x445a8
movq %rax, %r14
movq %r13, %rdi
movl $0x3, %esi
callq 0x445a8
movq %rax, 0x10(%rsp)
movq %r14, %rdi
callq 0x445ee
testb %al, %al
movq %rbx, 0x18(%rsp)
je 0x67282
movq %r14, %rdi
callq 0x44606
testq %rax, %rax
jne 0x67282
movq 0x10(%rsp), %rdi
callq 0x445ee
testb %al, %al
je 0x67282
movq 0x10(%rsp), %rdi
callq 0x44606
cmpq $0x1f, %rax
je 0x67121
cmpq $0xf, %rax
je 0x670f3
cmpq $0x7, %rax
jne 0x67282
cmpl $0x81f, %r15d # imm = 0x81F
setne %al
cmpl $0x500, %ebp # imm = 0x500
sete %cl
leaq 0x6ed59(%rip), %rdx # 0xd578e
leaq 0x6ee2d(%rip), %rsi # 0xd5869
jmp 0x67114
cmpl $0x7, %r14d
ja 0x67b55
movl %r14d, %eax
leaq 0x7057b(%rip), %rcx # 0xd6fd0
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
cmpl $0x4, %r13d
jne 0x67b55
movl $0x1c3, %esi # imm = 0x1C3
xorl %ebp, %ebp
cmpl $0x1, %r15d
je 0x67adf
cmpl $0x5, %r15d
jne 0x67b55
movl $0x10, %ebx
leaq 0x77227(%rip), %r12 # 0xddcb6
jmp 0x67bf0
movq %rbx, (%rsp)
movq %r12, 0x10(%rsp)
movq %r13, 0x20(%rsp)
cmpl $0x66, %ebp
jne 0x67b55
movq 0x20(%rsp), %rbp
movq %rbp, %rdi
xorl %esi, %esi
callq 0x445a8
movq %rax, %rbx
movq %rbp, %rdi
movl $0x2, %esi
callq 0x445a8
movq %rax, (%rsp)
movq %rbp, %rdi
movl $0x3, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movq %rax, %r12
movq %rbp, %rdi
movl $0x4, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movq %rax, %r14
movl %r14d, %r13d
subl %r12d, %r13d
movq %rbx, 0x18(%rsp)
jge 0x66dd2
xorl %ecx, %ecx
cmpl $0x67, %r15d
sete %cl
shll $0x5, %ecx
addl $0x20, %ecx
movl %ecx, %eax
subl %r12d, %eax
cltd
idivl %ecx
movl %edx, %r15d
incl %r14d
movq %rbx, %rdi
callq 0x445fe
decl %eax
movq %r14, %r13
leaq 0x76100(%rip), %r14 # 0xdcc40
movl (%r14,%rax,4), %ebx
leaq 0x16e835(%rip), %r12 # 0x1d5380
addq %r12, %rbx
movq (%rsp), %rdi
callq 0x445fe
decl %eax
movl (%r14,%rax,4), %ecx
addq %r12, %rcx
leaq 0x76f98(%rip), %rsi # 0xddaff
movq 0x10(%rsp), %r14
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq 0x446cd
movq %r14, %rdi
movl %r15d, %esi
callq 0x44848
leaq 0x6e4b7(%rip), %rsi # 0xd5042
movq %r14, %rdi
callq 0x44686
movq %r14, %rdi
movl %r13d, %esi
callq 0x44848
leaq 0x6e7e1(%rip), %rdi # 0xd5386
callq 0x82e71
movq %rbp, %rdi
movl %eax, %esi
callq 0x4459e
movq 0x320(%rbp), %rax
cmpl $0x0, 0x68(%rax)
je 0x67d2d
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, %ebx
movl %ebx, 0x50(%rax,%rcx)
movq 0x18(%rsp), %rdi
callq 0x445fe
movq 0x310(%rbp), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %ebx, 0x50(%rax,%rcx)
movq (%rsp), %rdi
callq 0x445fe
movq 0x310(%rbp), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x2, %edx
movl %edx, 0x50(%rax,%rcx)
movslq %r15d, %rax
movq 0x310(%rbp), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %esi
leaq (%rsi,%rsi,2), %rsi
shll $0x4, %esi
movq %rax, 0x58(%rcx,%rsi)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %edx, 0x50(%rax,%rcx)
movslq %r13d, %rax
jmp 0x66f8d
cmpl $0x4, %r13d
jne 0x67b55
movl $0x1c3, %esi # imm = 0x1C3
xorl %ebp, %ebp
cmpl $0x1, %r15d
je 0x67ace
cmpl $0x5, %r15d
jne 0x67b55
movl $0x12, %ebx
leaq 0x76fb6(%rip), %r12 # 0xddcd3
jmp 0x67bf0
cmpl $0x6, %r13d
je 0x67573
cmpl $0x4, %r13d
je 0x6753b
testl %r13d, %r13d
jne 0x67b55
cmpl $0x8, %r15d
jae 0x67b55
movl $0xaf, %eax
btl %r15d, %eax
jae 0x67b55
andl $0x7, %r15d
leaq 0x76c29(%rip), %rax # 0xdd98c
shll $0x2, %r15d
movslq (%r15,%rax), %r12
addq %rax, %r12
leaq 0x786bf(%rip), %rax # 0xdf434
jmp 0x675de
cmpl $0x6, %r13d
je 0x675ee
cmpl $0x4, %r13d
je 0x675a8
testl %r13d, %r13d
jne 0x67b55
cmpl $0x8, %r15d
jae 0x67b55
movl $0xaf, %eax
btl %r15d, %eax
jae 0x67b55
andl $0x7, %r15d
leaq 0x76c29(%rip), %rax # 0xdd9e4
shll $0x2, %r15d
movslq (%r15,%rax), %r12
addq %rax, %r12
leaq 0x78687(%rip), %rax # 0xdf454
jmp 0x675de
incl %r13d
movq %rbx, %rdi
callq 0x445fe
decl %eax
leaq 0x75e5a(%rip), %r14 # 0xdcc40
movl (%r14,%rax,4), %ebx
leaq 0x16e58f(%rip), %r15 # 0x1d5380
addq %r15, %rbx
movq (%rsp), %rdi
callq 0x445fe
decl %eax
movl (%r14,%rax,4), %ecx
addq %r15, %rcx
leaq 0x76cff(%rip), %rsi # 0xddb0c
movq 0x10(%rsp), %r14
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq 0x446cd
movq %r14, %rdi
movl %r12d, %esi
callq 0x44848
leaq 0x6e211(%rip), %rsi # 0xd5042
movq %r14, %rdi
callq 0x44686
movq %r14, %rdi
movl %r13d, %esi
callq 0x44848
leaq 0x76cd0(%rip), %rdi # 0xddb1b
callq 0x82e71
movq %rbp, %rdi
movl %eax, %esi
callq 0x4459e
movq 0x320(%rbp), %rax
cmpl $0x0, 0x68(%rax)
je 0x67d2d
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, %ebx
movl %ebx, 0x50(%rax,%rcx)
movq 0x18(%rsp), %rdi
callq 0x445fe
movq 0x310(%rbp), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %ebx, 0x50(%rax,%rcx)
movq (%rsp), %rdi
callq 0x445fe
movq 0x310(%rbp), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x2, %edx
movl %edx, 0x50(%rax,%rcx)
movslq %r12d, %rax
movq 0x310(%rbp), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %esi
leaq (%rsi,%rsi,2), %rsi
shll $0x4, %esi
movq %rax, 0x58(%rcx,%rsi)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%rbp), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %edx, 0x50(%rax,%rcx)
movslq %r13d, %rax
movq 0x310(%rbp), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x58(%rcx,%rdx)
movq 0x310(%rbp), %rax
jmp 0x67d23
movl %r13d, %eax
xorl $0x3, %eax
movl %r15d, %ecx
xorl $0x1, %ecx
movl $0x1c1, %esi # imm = 0x1C1
xorl %ebx, %ebx
orl %eax, %ecx
jne 0x674ba
movl $0x4, %r15d
leaq 0x76b74(%rip), %r12 # 0xddb53
jmp 0x67534
xorl $0x3, %r13d
xorl $0x1, %r15d
orl %r13d, %r15d
jne 0x67b55
movl $0x1c1, %esi # imm = 0x1C1
movl $0x1, %r15d
xorl %ebx, %ebx
leaq 0x76b34(%rip), %r12 # 0xddb3d
jmp 0x67534
xorl $0x3, %r13d
xorl $0x1, %r15d
orl %r13d, %r15d
jne 0x67b55
movl $0x1c1, %esi # imm = 0x1C1
movl $0x6, %r15d
xorl %ebx, %ebx
leaq 0x76b2f(%rip), %r12 # 0xddb62
jmp 0x67534
movl %r13d, %eax
xorl $0x3, %eax
movl %r15d, %ecx
xorl $0x1, %ecx
movl $0x1c1, %esi # imm = 0x1C1
xorl %ebx, %ebx
orl %eax, %ecx
jne 0x674d6
movl $0x7, %r15d
leaq 0x76b0a(%rip), %r12 # 0xddb6a
jmp 0x67534
movl $0x1c0, %esi # imm = 0x1C0
xorl %ebx, %ebx
movl %r13d, %eax
orl %r15d, %eax
jne 0x674f2
movl $0x2, %r14d
leaq 0x76aa7(%rip), %r12 # 0xddb2c
jmp 0x67510
movl %r15d, %eax
xorl $0x2, %eax
movl $0x1c1, %esi # imm = 0x1C1
xorl %ebx, %ebx
orl %r13d, %eax
jne 0x6751a
movl $0x3, %r15d
leaq 0x76a9f(%rip), %r12 # 0xddb4c
jmp 0x67534
cmpl $0x6, %r13d
je 0x67b2e
cmpl $0x4, %r13d
je 0x67af0
testl %r13d, %r13d
jne 0x67b55
cmpl $0x4, %r15d
jae 0x67b55
movl %r15d, %ebp
andl $0x3, %r15d
leaq 0x76875(%rip), %rax # 0xdd95c
movslq (%rax,%r15,4), %r12
addq %rax, %r12
jmp 0x67b22
cmpl $0x81f, %r15d # imm = 0x81F
setne %al
cmpl $0x500, %ebp # imm = 0x500
sete %cl
leaq 0x6e68d(%rip), %rdx # 0xd579a
leaq 0x6e761(%rip), %rsi # 0xd5875
cmoveq %rdx, %rsi
orb %al, %cl
jne 0x6714a
jmp 0x67282
cmpl $0x81f, %r15d # imm = 0x81F
je 0x67137
cmpl $0x501, %r15d # imm = 0x501
jne 0x67282
cmpl $0x500, %ebp # imm = 0x500
jne 0x67282
leaq 0x7698e(%rip), %rsi # 0xddad8
movq (%rsp), %rdi
movq %rsi, %rbp
callq 0x445fe
decl %eax
leaq 0x75ae1(%rip), %r15 # 0xdcc40
movq %rbx, %rdi
movl (%r15,%rax,4), %ebx
leaq 0x16e213(%rip), %r14 # 0x1d5380
addq %r14, %rbx
callq 0x445fe
movl %eax, %edi
callq 0x67d64
decl %eax
movl (%r15,%rax,4), %r8d
addq %r14, %r8
leaq 0x76951(%rip), %rsi # 0xddadd
movq %r12, %rdi
movq %rbp, %rdx
movq %rbx, %rcx
xorl %eax, %eax
callq 0x446cd
movq 0x320(%r13), %rax
cmpl $0x0, 0x68(%rax)
je 0x67262
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, %ebx
movl %ebx, 0x50(%rax,%rcx)
movq (%rsp), %rdi
callq 0x445fe
movq 0x310(%r13), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %ebx, 0x50(%rax,%rcx)
movq 0x18(%rsp), %rdi
callq 0x445fe
movl %eax, %edi
callq 0x67d64
movq 0x310(%r13), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq %rbp, %rdi
callq 0x82e71
movq %r13, %rdi
movl %eax, %esi
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x4459e
movl %ebp, 0x2c(%rsp)
movq %r14, %rbp
movq %r14, %rdi
callq 0x445ee
testb %al, %al
je 0x67650
movq 0x10(%rsp), %rdi
callq 0x445ee
testb %al, %al
je 0x67650
movl %r15d, %ebx
xorl $0x81e, %ebx # imm = 0x81E
movq %rbp, %rdi
callq 0x44606
movq %rax, %r14
movq 0x10(%rsp), %rdi
callq 0x44606
cmpl $0x1f, %eax
setne %cl
leal 0x1(%rax), %edx
xorl %r14d, %edx
movl %ebx, %esi
orl %edx, %esi
sete %sil
andb %cl, %sil
cmpb $0x1, %sil
jne 0x672ee
movl $0x1f, %r14d
jmp 0x67315
movl %r15d, %ecx
xorl $0x81f, %ecx # imm = 0x81F
cmpl $0x3f, %eax
setne %sil
orl %ecx, %edx
sete %dl
andb %sil, %dl
cmpb $0x1, %dl
jne 0x67497
movl $0x3f, %r14d
subl %eax, %r14d
leaq 0x78e0d(%rip), %r15 # 0xe012c
movq (%rsp), %rdi
callq 0x445fe
decl %eax
leaq 0x7590f(%rip), %rcx # 0xdcc40
movl (%rcx,%rax,4), %ebx
movq %r14, %rbp
leaq 0x16e042(%rip), %r14 # 0x1d5380
addq %r14, %rbx
movq 0x18(%rsp), %rdi
callq 0x445fe
decl %eax
leaq 0x758ec(%rip), %rcx # 0xdcc40
movl (%rcx,%rax,4), %r8d
addq %r14, %r8
movq %rbp, %r14
leaq 0x76782(%rip), %rsi # 0xddae7
movq %r12, %rdi
movq %r15, %rdx
movq %rbx, %rcx
xorl %eax, %eax
callq 0x446cd
movq %r12, %rdi
movl %ebp, %esi
callq 0x44848
movq %r15, %rdi
callq 0x82e71
movq %r13, %rdi
movl %eax, %esi
callq 0x4459e
movq 0x320(%r13), %rax
cmpl $0x0, 0x68(%rax)
je 0x67d2d
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, %ebx
movl %ebx, 0x50(%rax,%rcx)
movq (%rsp), %rdi
callq 0x445fe
movq 0x310(%r13), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %ebx, 0x50(%rax,%rcx)
movq 0x18(%rsp), %rdi
callq 0x445fe
movq 0x310(%r13), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x2, 0x50(%rax,%rcx)
movslq %r14d, %rax
movq 0x310(%r13), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x58(%rcx,%rdx)
jmp 0x67d1c
movl %eax, %edx
xorl $0x1f, %edx
leaq 0xe08c7(%rip), %rsi # 0x147d6a
orl %edx, %ebx
je 0x674b2
xorl $0x3f, %eax
orl %eax, %ecx
jne 0x67623
movq %rsi, %r15
jmp 0x6731f
xorl $0x2, %r15d
orl %r15d, %r13d
jne 0x67b55
movl $0x5, %r15d
leaq 0x76687(%rip), %r12 # 0xddb5b
jmp 0x67534
xorl $0x2, %r15d
orl %r15d, %r13d
jne 0x67b55
movl $0x8, %r15d
leaq 0x76683(%rip), %r12 # 0xddb73
jmp 0x67534
xorl $0x3, %r13d
xorl $0x1, %r15d
orl %r13d, %r15d
jne 0x67b55
movl $0x3, %r14d
leaq 0x76625(%rip), %r12 # 0xddb35
xorl %ebp, %ebp
xorl %r15d, %r15d
jmp 0x67bf6
xorl $0x1, %r15d
orl %r15d, %r13d
jne 0x67b55
movl $0x2, %r15d
leaq 0x76610(%rip), %r12 # 0xddb44
xorl %ebp, %ebp
jmp 0x67bf3
cmpl $0x7, %r15d
jae 0x67b55
movl $0x73, %eax
btl %r15d, %eax
jae 0x67b55
andl $0x7, %r15d
leaq 0x7644d(%rip), %rax # 0xdd9ac
shll $0x2, %r15d
movslq (%r15,%rax), %r12
addq %rax, %r12
leaq 0x76457(%rip), %rax # 0xdd9c8
jmp 0x675de
movl $0x1c3, %esi # imm = 0x1C3
testl %r15d, %r15d
je 0x67bd1
cmpl $0x5, %r15d
je 0x67bc1
cmpl $0x1, %r15d
jne 0x67b55
xorl %ebp, %ebp
movl $0xd, %ebx
leaq 0x766eb(%rip), %r12 # 0xddc8e
jmp 0x67bf0
cmpl $0x7, %r15d
jae 0x67b55
movl $0x73, %eax
btl %r15d, %eax
jae 0x67b55
andl $0x7, %r15d
leaq 0x76438(%rip), %rax # 0xdda04
shll $0x2, %r15d
movslq (%r15,%rax), %r12
addq %rax, %r12
leaq 0x76442(%rip), %rax # 0xdda20
movl (%r15,%rax), %ebx
movl $0x1c3, %esi # imm = 0x1C3
xorl %ebp, %ebp
jmp 0x67bf0
movl $0x1c3, %esi # imm = 0x1C3
testl %r15d, %r15d
je 0x67d3c
cmpl $0x5, %r15d
je 0x67be2
cmpl $0x1, %r15d
jne 0x67b55
xorl %ebp, %ebp
movl $0x1f, %ebx
leaq 0x7674e(%rip), %r12 # 0xddd6c
jmp 0x67bf0
movl %r15d, %ecx
xorl $0x500, %ecx # imm = 0x500
xorl $0x501, %r15d # imm = 0x501
orl %eax, %r15d
sete %al
orl %edx, %ecx
leaq 0xe763f(%rip), %r15 # 0x14ec81
je 0x6731f
testb %al, %al
jne 0x6731f
movq %r13, 0x20(%rsp)
movq %rbp, 0x30(%rsp)
movq %rbp, %rdi
callq 0x44606
movq %rax, %r14
movq 0x10(%rsp), %rdi
callq 0x44606
movq %rax, %rbx
movq (%rsp), %rdi
callq 0x445fe
decl %eax
leaq 0x755bc(%rip), %r13 # 0xdcc40
movl (%r13,%rax,4), %r15d
leaq 0x16dcf0(%rip), %rbp # 0x1d5380
addq %rbp, %r15
movq 0x18(%rsp), %rdi
callq 0x445fe
decl %eax
movl (%r13,%rax,4), %r8d
addq %rbp, %r8
cmpq %rbx, %r14
jle 0x678bf
movb 0xf(%rsp), %bl
orb 0xe(%rsp), %bl
cmpl $0x500, 0x2c(%rsp) # imm = 0x500
leaq 0x7642c(%rip), %rax # 0xddaf3
leaq 0x7642b(%rip), %r14 # 0xddaf9
cmoveq %rax, %r14
leaq 0x7640e(%rip), %rsi # 0xddae7
movq %r12, %rdi
movq %r14, %rdx
movq %r15, %rcx
xorl %eax, %eax
callq 0x446cd
movzbl %bl, %ebx
shll $0x5, %ebx
addl $0x20, %ebx
movq 0x30(%rsp), %r13
movq %r13, %rdi
callq 0x44606
movl %ebx, %esi
subl %eax, %esi
movq %r12, %rdi
callq 0x44848
leaq 0x6d930(%rip), %rsi # 0xd5042
movq %r12, %rdi
callq 0x44686
movq 0x10(%rsp), %rbp
movq %rbp, %rdi
callq 0x44606
leal 0x1(%rax), %esi
movq %r12, %rdi
callq 0x44848
movq %r14, %rdi
callq 0x82e71
movq 0x20(%rsp), %r15
movq %r15, %rdi
movl %eax, %esi
callq 0x4459e
movq 0x320(%r15), %rax
cmpl $0x0, 0x68(%rax)
je 0x67d2d
movq %rbp, %r12
movq 0x310(%r15), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, %ebp
movl %ebp, 0x50(%rax,%rcx)
movq (%rsp), %rdi
callq 0x445fe
movq 0x310(%r15), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r15), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r15), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %ebp, 0x50(%rax,%rcx)
movq 0x18(%rsp), %rdi
callq 0x445fe
movq 0x310(%r15), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r15), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r15), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x2, %r14d
movl %r14d, 0x50(%rax,%rcx)
movq %r13, %rdi
callq 0x44606
subl %eax, %ebx
movslq %ebx, %rax
movq 0x310(%r15), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x58(%rcx,%rdx)
movq 0x310(%r15), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r15), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %r14d, 0x50(%rax,%rcx)
movq %r12, %rdi
callq 0x44606
incl %eax
cltq
movq 0x310(%r15), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x58(%rcx,%rdx)
movq 0x310(%r15), %rax
jmp 0x67d23
cmpl $0x500, 0x2c(%rsp) # imm = 0x500
leaq 0x6dc64(%rip), %rax # 0xd5532
leaq 0x6dee1(%rip), %r14 # 0xd57b6
cmoveq %rax, %r14
leaq 0x76207(%rip), %rsi # 0xddae7
movq %r12, %rdi
movq %r14, %rdx
movq %r15, %rcx
xorl %eax, %eax
callq 0x446cd
movq 0x30(%rsp), %r13
movq %r13, %rdi
callq 0x44606
movq %r12, %rdi
movl %eax, %esi
callq 0x44848
leaq 0x6d734(%rip), %rsi # 0xd5042
movq %r12, %rdi
callq 0x44686
movq 0x10(%rsp), %r15
movq %r15, %rdi
callq 0x44606
movq %rax, %rbx
movq %r13, %rdi
callq 0x44606
subl %eax, %ebx
incl %ebx
movq %r12, %rdi
movl %ebx, %esi
callq 0x44848
movq %r14, %rdi
callq 0x82e71
movq 0x20(%rsp), %r14
movq %r14, %rdi
movl %eax, %esi
callq 0x4459e
movq 0x320(%r14), %rax
cmpl $0x0, 0x68(%rax)
je 0x67d2d
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, %ebx
movl %ebx, 0x50(%rax,%rcx)
movq (%rsp), %rdi
callq 0x445fe
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %ebx, 0x50(%rax,%rcx)
movq 0x18(%rsp), %rdi
callq 0x445fe
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x2, %ebx
movl %ebx, 0x50(%rax,%rcx)
movq %r13, %rdi
callq 0x44606
cltq
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x58(%rcx,%rdx)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %ebx, 0x50(%rax,%rcx)
movq %r15, %rdi
callq 0x44606
movq %rax, %rbx
movq %r13, %rdi
callq 0x44606
subl %eax, %ebx
incl %ebx
movslq %ebx, %rax
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x58(%rcx,%rdx)
movq 0x310(%r14), %rax
jmp 0x67d23
movl $0x11, %ebx
leaq 0x761ec(%rip), %r12 # 0xddcc6
jmp 0x67bf0
movl $0xf, %ebx
leaq 0x761bc(%rip), %r12 # 0xddca7
jmp 0x67bf0
cmpl $0x8, %r15d
jae 0x67b55
movl $0xf3, %eax
btl %r15d, %eax
jae 0x67b55
andl $0x7, %r15d
leaq 0x75e60(%rip), %rax # 0xdd96c
shll $0x2, %r15d
movslq (%r15,%rax), %r12
addq %rax, %r12
leaq 0x778f6(%rip), %rax # 0xdf414
movl (%r15,%rax), %ebp
movl $0x1c2, %esi # imm = 0x1C2
xorl %ebx, %ebx
jmp 0x67bf0
movl $0x1c2, %esi # imm = 0x1C2
testl %r15d, %r15d
je 0x67d4d
cmpl $0x1, %r15d
jne 0x67b55
movl $0xb, %ebp
xorl %ebx, %ebx
leaq 0x76092(%rip), %r12 # 0xddbe2
jmp 0x67bf0
movq 0x20(%rsp), %rbx
movq %rbx, %rdi
movq 0x10(%rsp), %r15
movq %r15, %rsi
movq (%rsp), %r12
movq %r12, %rdx
callq 0x67e5f
testq %rax, %rax
je 0x67ba5
movq %rax, %r14
movq %rax, %rdi
callq 0x82e71
movq %rbx, %rdi
movl %eax, %esi
callq 0x4459e
leaq 0x12c536(%rip), %rax # 0x1940c8
movq %r14, %rdi
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmpq *(%rax)
movq %rbx, %rdi
movq %r15, %rsi
movq %r12, %rdx
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x7f9cd
xorl %ebp, %ebp
movl $0xe, %ebx
leaq 0x760cb(%rip), %r12 # 0xddc9a
jmp 0x67bf0
movl $0xc, %ebx
leaq 0x760a4(%rip), %r12 # 0xddc81
jmp 0x67d48
xorl %ebp, %ebp
movl $0x20, %ebx
leaq 0x76186(%rip), %r12 # 0xddd76
xorl %r15d, %r15d
xorl %r14d, %r14d
movq 0x20(%rsp), %r13
movq %r13, %rdi
callq 0x4459e
movq 0x10(%rsp), %rdi
movq %r12, %rsi
callq 0x44686
movq 0x320(%r13), %rax
cmpl $0x0, 0x68(%rax)
je 0x67c75
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x44, 0x50(%rax,%rcx)
addl %ebx, %ebp
addl %r14d, %r15d
addl %ebp, %r15d
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %r15d, 0x58(%rax,%rcx)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
leaq 0x6f054(%rip), %rsi # 0xd6cd0
movq %r12, %rdi
callq 0x43130
testq %rax, %rax
jne 0x67d2d
movq %r13, %rdi
movl $0x4, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
movl %eax, %r14d
leal -0x1(%r14), %eax
leaq 0x74f90(%rip), %rcx # 0xdcc40
movl (%rcx,%rax,4), %eax
leaq 0x16d6c6(%rip), %rdx # 0x1d5380
addq %rax, %rdx
leaq 0x75e1e(%rip), %rsi # 0xddae2
movq 0x10(%rsp), %rdi
xorl %eax, %eax
callq 0x446cd
movq 0x320(%r13), %rax
cmpl $0x0, 0x68(%rax)
je 0x67d2d
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, 0x50(%rax,%rcx)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %r14d, 0x58(%rax,%rcx)
movq 0x310(%r13), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movl $0x1e, %ebx
leaq 0x76019(%rip), %r12 # 0xddd61
movl %r15d, %ebp
jmp 0x67d5c
movl $0xa, %ebp
leaq 0x75e80(%rip), %r12 # 0xddbd9
movl %r15d, %ebx
movl %r15d, %r14d
jmp 0x67bf6
|
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
|
printTypedVectorList
|
static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind, MCRegisterInfo *MRI)
{
char Suffix[32];
arm64_vas vas = 0;
arm64_vess vess = 0;
if (NumLanes) {
cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind);
switch(LaneKind) {
default: break;
case 'b':
switch(NumLanes) {
default: break;
case 8:
vas = ARM64_VAS_8B;
break;
case 16:
vas = ARM64_VAS_16B;
break;
}
break;
case 'h':
switch(NumLanes) {
default: break;
case 4:
vas = ARM64_VAS_4H;
break;
case 8:
vas = ARM64_VAS_8H;
break;
}
break;
case 's':
switch(NumLanes) {
default: break;
case 2:
vas = ARM64_VAS_2S;
break;
case 4:
vas = ARM64_VAS_4S;
break;
}
break;
case 'd':
switch(NumLanes) {
default: break;
case 1:
vas = ARM64_VAS_1D;
break;
case 2:
vas = ARM64_VAS_2D;
break;
}
break;
case 'q':
switch(NumLanes) {
default: break;
case 1:
vas = ARM64_VAS_1Q;
break;
}
break;
}
} else {
cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind);
switch(LaneKind) {
default: break;
case 'b':
vess = ARM64_VESS_B;
break;
case 'h':
vess = ARM64_VESS_H;
break;
case 's':
vess = ARM64_VESS_S;
break;
case 'd':
vess = ARM64_VESS_D;
break;
}
}
printVectorList(MI, OpNum, O, Suffix, MRI, vas, vess);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %r9, %r15
movq %rdx, 0x8(%rsp)
movl %esi, %ebp
movq %rdi, %r14
movsbl %r8b, %ebx
testl %ecx, %ecx
je 0x81682
movl %ecx, %r12d
leaq 0x5c851(%rip), %rdx # 0xdde76
movl $0x0, 0x4(%rsp)
leaq 0x10(%rsp), %rdi
movl $0x20, %esi
xorl %eax, %eax
callq 0x4772c
cmpl $0x67, %ebx
jle 0x816c8
cmpl $0x68, %ebx
je 0x81705
cmpl $0x71, %ebx
je 0x8171a
cmpl $0x73, %ebx
jne 0x81740
cmpl $0x4, %r12d
je 0x81779
cmpl $0x2, %r12d
jne 0x81740
movl $0x5, (%rsp)
jmp 0x81789
leaq 0x5c7f3(%rip), %rdx # 0xdde7c
movl $0x0, (%rsp)
leaq 0x10(%rsp), %rdi
movl $0x20, %esi
movl %r8d, %ecx
xorl %eax, %eax
callq 0x4772c
cmpl $0x67, %ebx
jg 0x816ee
cmpl $0x62, %ebx
je 0x81753
cmpl $0x64, %ebx
jne 0x81749
movl $0x4, 0x4(%rsp)
jmp 0x81789
cmpl $0x62, %ebx
je 0x8172b
cmpl $0x64, %ebx
jne 0x81740
cmpl $0x2, %r12d
je 0x81782
cmpl $0x1, %r12d
jne 0x81740
movl $0x7, (%rsp)
jmp 0x81789
cmpl $0x68, %ebx
je 0x8175d
cmpl $0x73, %ebx
jne 0x81749
movl $0x3, 0x4(%rsp)
jmp 0x81789
cmpl $0x8, %r12d
je 0x81767
cmpl $0x4, %r12d
jne 0x81740
movl $0x3, (%rsp)
jmp 0x81789
xorl %eax, %eax
cmpl $0x1, %r12d
sete %al
leal (%rax,%rax,8), %eax
movl %eax, (%rsp)
jmp 0x81789
cmpl $0x10, %r12d
je 0x81770
cmpl $0x8, %r12d
jne 0x81740
movl $0x1, (%rsp)
jmp 0x81789
movl $0x0, (%rsp)
jmp 0x81789
movl $0x0, 0x4(%rsp)
jmp 0x81789
movl $0x1, 0x4(%rsp)
jmp 0x81789
movl $0x2, 0x4(%rsp)
jmp 0x81789
movl $0x4, (%rsp)
jmp 0x81789
movl $0x2, (%rsp)
jmp 0x81789
movl $0x6, (%rsp)
jmp 0x81789
movl $0x8, (%rsp)
movq %r14, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
movl %eax, %r13d
leaq 0x537cf(%rip), %rsi # 0xd4f74
movq 0x8(%rsp), %rdi
callq 0x44686
movq %r15, %rdi
movl $0x10, %esi
callq 0x475fa
movq %rax, %rdi
movl %r13d, %esi
callq 0x47578
movl $0x2, %ebp
testb %al, %al
jne 0x8186f
movq %r15, %rdi
movl $0x15, %esi
callq 0x475fa
movq %rax, %rdi
movl %r13d, %esi
callq 0x47578
testb %al, %al
jne 0x8186f
movq %r15, %rdi
movl $0x13, %esi
callq 0x475fa
movq %rax, %rdi
movl %r13d, %esi
callq 0x47578
movl $0x3, %ebp
testb %al, %al
jne 0x8186f
movq %r15, %rdi
movl $0x19, %esi
callq 0x475fa
movq %rax, %rdi
movl %r13d, %esi
callq 0x47578
testb %al, %al
jne 0x8186f
movq %r15, %rdi
movl $0x14, %esi
callq 0x475fa
movq %rax, %rdi
movl %r13d, %esi
callq 0x47578
testb %al, %al
jne 0x8186a
movq %r15, %rdi
movl $0x20, %esi
callq 0x475fa
movq %rax, %rdi
movl %r13d, %esi
callq 0x47578
movl $0x1, %ebp
testb %al, %al
je 0x8186f
movl $0x4, %ebp
movq %r15, %rdi
movl %r13d, %esi
movl $0x3, %edx
callq 0x4759a
movl %eax, %r12d
testl %eax, %eax
jne 0x8189f
movq %r15, %rdi
movl %r13d, %esi
movl $0xa, %edx
callq 0x4759a
testl %eax, %eax
cmovnel %eax, %r13d
movl %r13d, %r12d
movq %r15, %rdi
movl $0xa, %esi
callq 0x475fa
movq %rax, %rdi
movl %r12d, %esi
callq 0x47578
testb %al, %al
je 0x818de
movq %r15, %rdi
movl $0x11, %esi
callq 0x475fa
movq %r15, %rdi
movl %r12d, %esi
movl $0x2, %edx
movq %rax, %rcx
callq 0x474c7
movl %eax, %r12d
leaq 0x15419b(%rip), %rbx # 0x1d5a80
leaq 0x5c594(%rip), %r15 # 0xdde80
leaq 0x10(%rsp), %r13
leal -0x1(%r12), %eax
leaq 0x5b9d3(%rip), %rcx # 0xdd2d0
movl (%rcx,%rax,4), %edx
addq %rbx, %rdx
movq 0x8(%rsp), %rdi
movq %r15, %rsi
movq %r13, %rcx
xorl %eax, %eax
callq 0x446cd
cmpl $0x1, %ebp
je 0x8192b
movq 0x8(%rsp), %rdi
leaq 0x5371c(%rip), %rsi # 0xd5042
callq 0x44686
movq 0x320(%r14), %rax
cmpl $0x0, 0x68(%rax)
je 0x819d4
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, 0x50(%rax,%rcx)
movl %r12d, %edi
callq 0x82eae
movq 0x310(%r14), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x58(%rcx,%rdx)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl (%rsp), %edx
movl %edx, 0x3c(%rax,%rcx)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl 0x4(%rsp), %edx
movl %edx, 0x40(%rax,%rcx)
movq 0x310(%r14), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
addl $-0x69, %r12d
movl $0x69, %eax
cmpl $0x1e, %r12d
ja 0x819f0
movl %r12d, %eax
leaq 0x5c04f(%rip), %rcx # 0xdda3c
movl (%rcx,%rax,4), %eax
movl %eax, %r12d
decl %ebp
jne 0x818f1
leaq 0xc5526(%rip), %rsi # 0x146f28
movq 0x8(%rsp), %rdi
callq 0x44686
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
|
printSysCROperand
|
static void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
//assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
SStream_concat(O, "c%u", MCOperand_getImm(Op));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op);
MI->flat_insn->detail->arm64.op_count++;
}
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r15
movq %rdi, %rbx
callq 0x445a8
movq %rax, %r14
movq %rax, %rdi
callq 0x44606
leaq 0x52edf(%rip), %rsi # 0xd5120
movq %r15, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x822b5
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x40, 0x50(%rax,%rcx)
movq %r14, %rdi
callq 0x44606
cltq
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x58(%rcx,%rdx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
|
printLogicalImm64
|
static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
{
int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Val = AArch64_AM_decodeLogicalImmediate(Val, 64);
switch(MI->flat_insn->id) {
default:
printInt64Bang(O, Val);
break;
case ARM64_INS_ORR:
case ARM64_INS_AND:
case ARM64_INS_EOR:
case ARM64_INS_TST:
// do not print number in negative form
if (Val >= 0 && Val <= HEX_THRESHOLD)
SStream_concat(O, "#%u", (int)Val);
else
SStream_concat(O, "#0x%"PRIx64, Val);
break;
}
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)Val;
MI->flat_insn->detail->arm64.op_count++;
}
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r14
movq %rdi, %rbx
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movl %eax, %edi
shrl $0x6, %edi
andl $0x3f, %eax
movl %edi, %ecx
andl $0x40, %ecx
orl %eax, %ecx
xorl $0x3f, %ecx
movl $0xffffffff, %edx # imm = 0xFFFFFFFF
movl %edx, %esi
leal 0x1(%rsi), %edx
cmpl $0x1d, %esi
je 0x82666
addl %ecx, %ecx
jns 0x82658
movl $0x40000000, %esi # imm = 0x40000000
movl %edx, %ecx
shrl %cl, %esi
leal -0x1(%rsi), %r8d
andl %r8d, %eax
incb %al
movq $-0x1, %r15
movl %eax, %ecx
shlq %cl, %r15
andl %r8d, %edi
notq %r15
andl $0x3f, %edi
je 0x826a5
movl %r8d, %ecx
movl %r15d, %eax
andl $0x1, %eax
shlq %cl, %rax
shrq %r15
orq %rax, %r15
decl %edi
jne 0x82692
cmpl $0x18, %edx
je 0x826bc
movq %r15, %rax
movl %esi, %ecx
shlq %cl, %rax
orq %rax, %r15
addl %esi, %esi
cmpl $0x40, %esi
jne 0x826aa
movq 0x310(%rbx), %rax
movl (%rax), %eax
cmpl $0xc7, %eax
jg 0x826d8
cmpl $0xe, %eax
je 0x826e6
cmpl $0x3f, %eax
je 0x826e6
jmp 0x82718
cmpl $0xc8, %eax
je 0x826e6
cmpl $0x1b3, %eax # imm = 0x1B3
jne 0x82718
cmpq $0x9, %r15
ja 0x82702
leaq 0x52a4b(%rip), %rsi # 0xd513e
movq %r14, %rdi
movl %r15d, %edx
xorl %eax, %eax
callq 0x446cd
jmp 0x82723
leaq 0x3fefd(%rip), %rsi # 0xc2606
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq 0x446cd
jmp 0x82723
movq %r14, %rdi
movq %r15, %rsi
callq 0x44778
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x82783
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x2, 0x50(%rax,%rcx)
movslq %r15d, %rax
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x36(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x58(%rcx,%rdx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x36(%rax)
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
|
printArithExtend
|
static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O)
{
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val);
unsigned ShiftVal = AArch64_AM_getArithShiftValue(Val);
// If the destination or first source register operand is [W]SP, print
// UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
// all.
if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) {
unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0));
unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1));
if ( ((Dest == AArch64_SP || Src1 == AArch64_SP) &&
ExtType == AArch64_AM_UXTX) ||
((Dest == AArch64_WSP || Src1 == AArch64_WSP) &&
ExtType == AArch64_AM_UXTW) ) {
if (ShiftVal != 0) {
SStream_concat0(O, ", lsl ");
printInt32Bang(O, ShiftVal);
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
}
}
return;
}
}
SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType));
if (MI->csh->detail) {
arm64_extender ext = ARM64_EXT_INVALID;
switch(ExtType) {
default: // never reach
case AArch64_AM_UXTB:
ext = ARM64_EXT_UXTW;
break;
case AArch64_AM_UXTH:
ext = ARM64_EXT_UXTW;
break;
case AArch64_AM_UXTW:
ext = ARM64_EXT_UXTW;
break;
case AArch64_AM_UXTX:
ext = ARM64_EXT_UXTW;
break;
case AArch64_AM_SXTB:
ext = ARM64_EXT_UXTW;
break;
case AArch64_AM_SXTH:
ext = ARM64_EXT_UXTW;
break;
case AArch64_AM_SXTW:
ext = ARM64_EXT_UXTW;
break;
case AArch64_AM_SXTX:
ext = ARM64_EXT_UXTW;
break;
}
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].ext = ext;
}
if (ShiftVal != 0) {
SStream_concat0(O, " ");
printInt32Bang(O, ShiftVal);
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal;
}
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r15
movq %rdi, %rbx
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movq %rax, %r14
shrl $0x3, %eax
andl $0x7, %eax
leaq 0x558cc(%rip), %rcx # 0xd815c
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl $0x5, %r12d
jmp 0x8295c
movl $0x9, %r12d
jmp 0x8295c
movl $0x7, %r12d
movb $0x1, %r13b
movl $0x0, 0x4(%rsp)
jmp 0x828d1
movl $0x8, %r12d
movb $0x1, %al
movl %eax, 0x4(%rsp)
xorl %r13d, %r13d
andl $0x7, %r14d
movq %rbx, %rdi
xorl %esi, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
movl %eax, %ebp
movq %rbx, %rdi
movl $0x1, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
cmpl $0x4, %ebp
sete %cl
cmpl $0x4, %eax
sete %dl
cmpb $0x0, 0x4(%rsp)
je 0x82915
orb %dl, %cl
jne 0x8292c
cmpl $0x5, %ebp
sete %cl
cmpl $0x5, %eax
sete %al
orb %cl, %al
andb %al, %r13b
cmpb $0x1, %r13b
jne 0x82960
testl %r14d, %r14d
je 0x82a19
leaq 0x528c3(%rip), %rsi # 0xd51ff
jmp 0x829ba
movl $0xc, %r12d
jmp 0x8295c
movl $0x6, %r12d
jmp 0x8295c
movl $0xa, %r12d
jmp 0x8295c
movl $0xb, %r12d
andl $0x7, %r14d
leaq 0x5b151(%rip), %rax # 0xddab8
movslq -0x14(%rax,%r12,4), %rdx
addq %rax, %rdx
leaq 0x5b16c(%rip), %rsi # 0xddae2
movq %r15, %rdi
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x829ae
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x3, 0x1c(%rax,%rcx)
testl %r14d, %r14d
je 0x82a19
leaq 0x60b9c(%rip), %rsi # 0xe3556
movq %r15, %rdi
callq 0x44686
movq %r15, %rdi
movl %r14d, %esi
callq 0x44848
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x82a19
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, 0x14(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x36(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %r14d, 0x18(%rax,%rcx)
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64InstPrinter.c
|
AArch64_group_name
|
const char *AArch64_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
// verify group id
if (id >= ARM64_GRP_ENDING || (id > ARM64_GRP_JUMP && id < ARM64_GRP_CRYPTO))
return NULL;
// NOTE: when new generic groups are added, 2 must be changed accordingly
if (id >= 128)
return group_name_maps[id - 128 + 2].name;
else
return group_name_maps[id].name;
#else
return NULL;
#endif
}
|
cmpl $0x84, %esi
setae %al
leal -0x2(%rsi), %ecx
cmpl $0x7e, %ecx
setb %cl
orb %al, %cl
je 0x82e57
xorl %eax, %eax
retq
leal -0x7e(%rsi), %eax
cmpl $0x7f, %esi
cmovbel %esi, %eax
shlq $0x4, %rax
leaq 0x103685(%rip), %rcx # 0x1864f0
movq 0x8(%rax,%rcx), %rax
retq
|
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64Mapping.c
|
DecodeCOP3Mem
|
static DecodeStatus DecodeCOP3Mem(MCInst *Inst,
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
{
int Offset = SignExtend32(Insn & 0xffff, 16);
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Reg = getReg(Decoder, Mips_COP3RegClassID, Reg);
Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
MCOperand_CreateReg0(Inst, Reg);
MCOperand_CreateReg0(Inst, Base);
MCOperand_CreateImm0(Inst, Offset);
return MCDisassembler_Success;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdx, %r15
movl %esi, %r14d
movq %rdi, %rbx
movq %rdx, %rdi
movl $0x3, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %r14d, %ecx
shrl $0xf, %ecx
andl $0x3e, %ecx
movzwl (%rax,%rcx), %ebp
movq %r15, %rdi
movl $0x8, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %r14d, %ecx
shrl $0x14, %ecx
andl $0x3e, %ecx
movzwl (%rax,%rcx), %r15d
movq %rbx, %rdi
movl %ebp, %esi
callq 0x44631
movq %rbx, %rdi
movl %r15d, %esi
callq 0x44631
movswq %r14w, %rsi
movq %rbx, %rdi
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x4465e
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
|
DecodeHI32DSPRegisterClass
|
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
unsigned Reg;
if (RegNo >= 4)
return MCDisassembler_Fail;
Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo);
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
|
xorl %eax, %eax
cmpl $0x3, %esi
ja 0x86af9
pushq %rbp
pushq %rbx
pushq %rax
movl %esi, %ebp
movq %rdi, %rbx
movq %rdx, %rdi
movl $0x14, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %ebp, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movl $0x3, %eax
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
|
DecodeLO32DSPRegisterClass
|
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
unsigned Reg;
if (RegNo >= 4)
return MCDisassembler_Fail;
Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo);
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
|
xorl %eax, %eax
cmpl $0x3, %esi
ja 0x86b33
pushq %rbp
pushq %rbx
pushq %rax
movl %esi, %ebp
movq %rdi, %rbx
movq %rdx, %rdi
movl $0x15, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %ebp, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movl $0x3, %eax
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
|
DecodeFGR64RegisterClass
|
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
unsigned Reg;
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo);
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
|
xorl %eax, %eax
cmpl $0x1f, %esi
ja 0x86c1b
pushq %rbp
pushq %rbx
pushq %rax
movl %esi, %ebp
movq %rdi, %rbx
movq %rdx, %rdi
movl $0x1b, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %ebp, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movl $0x3, %eax
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
|
DecodeMSA128WRegisterClass
|
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
unsigned Reg;
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo);
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
|
xorl %eax, %eax
cmpl $0x1f, %esi
ja 0x86d47
pushq %rbp
pushq %rbx
pushq %rax
movl %esi, %ebp
movq %rdi, %rbx
movq %rcx, %rdi
movl $0x2d, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %ebp, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movl $0x3, %eax
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
|
DecodeFGRCCRegisterClass
|
static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
unsigned Reg;
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo);
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
|
xorl %eax, %eax
cmpl $0x1f, %esi
ja 0x873ee
pushq %rbp
pushq %rbx
pushq %rax
movl %esi, %ebp
movq %rdi, %rbx
movq %rdx, %rdi
movl $0x6, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %ebp, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movl $0x3, %eax
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
|
DecodeCOP2RegisterClass
|
static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
unsigned Reg;
if (RegNo > 31)
return MCDisassembler_Fail;
Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo);
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
|
xorl %eax, %eax
cmpl $0x1f, %esi
ja 0x87428
pushq %rbp
pushq %rbx
pushq %rax
movl %esi, %ebp
movq %rdi, %rbx
movq %rdx, %rdi
movl $0x2, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %ebp, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movl $0x3, %eax
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
|
DecodeDaddiGroupBranch_4
|
static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
uint64_t Address, MCRegisterInfo *Decoder)
{
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
// (otherwise we would have matched the ADDI instruction from the earlier
// ISA's instead).
//
// We have:
// 0b011000 sssss ttttt iiiiiiiiiiiiiiii
// BNVC if rs >= rt
// BNEZALC if rs == 0 && rt != 0
// BNEC if rs < rt && rs != 0
uint32_t Rs = fieldFromInstruction(insn, 21, 5);
uint32_t Rt = fieldFromInstruction(insn, 16, 5);
uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
bool HasRs = false;
if (Rs >= Rt) {
MCInst_setOpcode(MI, Mips_BNVC);
HasRs = true;
} else if (Rs != 0 && Rs < Rt) {
MCInst_setOpcode(MI, Mips_BNEC);
HasRs = true;
} else
MCInst_setOpcode(MI, Mips_BNEZALC);
if (HasRs)
MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
MCOperand_CreateImm0(MI, Imm);
return MCDisassembler_Success;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movl %esi, %r15d
shrl $0x15, %r15d
andl $0x1f, %r15d
movl %esi, %r12d
shrl $0x10, %r12d
andl $0x1f, %r12d
movl $0x111, %esi # imm = 0x111
cmpl %r12d, %r15d
jae 0x875c7
movl $0x103, %esi # imm = 0x103
testl %r15d, %r15d
je 0x8762a
movq %rbx, %rdi
callq 0x4459a
movq %r14, %rdi
movl $0x8, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %r15d, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movswl %bp, %r15d
shll $0x2, %r15d
movq %r14, %rdi
movl $0x8, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %r12d, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movq %rbx, %rdi
movq %r15, %rsi
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
jmp 0x4465e
movq %rbx, %rdi
movl $0x10d, %esi # imm = 0x10D
callq 0x4459a
jmp 0x875ef
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsDisassembler.c
|
printMemOperand
|
static void printMemOperand(MCInst *MI, int opNum, SStream *O)
{
// Load/Store memory operands -- imm($reg)
// If PIC target the target is loaded as the
// pattern lw $25,%call16($28)
set_mem_access(MI, true);
printOperand(MI, opNum + 1, O);
SStream_concat0(O, "(");
printOperand(MI, opNum, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r14
movl %esi, %r15d
movq %rdi, %rbx
movl $0x1, %esi
callq 0x89953
leal 0x1(%r15), %esi
movq %rbx, %rdi
movq %r14, %rdx
callq 0x894a6
leaq 0x429c0(%rip), %rsi # 0xcc1b7
movq %r14, %rdi
callq 0x44686
movq %rbx, %rdi
movl %r15d, %esi
movq %r14, %rdx
callq 0x894a6
leaq 0xbd6c7(%rip), %rsi # 0x146edb
movq %r14, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
movb $0x0, 0x70(%rax)
cmpl $0x3, 0x68(%rax)
jne 0x8983e
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x30(%rax)
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsInstPrinter.c
|
printUnsignedImm8
|
static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, opNum);
if (MCOperand_isImm(MO)) {
uint8_t imm = (uint8_t)MCOperand_getImm(MO);
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
if (MI->csh->detail) {
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
MI->flat_insn->detail->mips.op_count++;
}
} else
printOperand(MI, opNum, O);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
callq 0x445a8
movq %rax, %r15
movq %rax, %rdi
callq 0x445ee
testb %al, %al
je 0x8993c
movq %r15, %rdi
callq 0x44606
movq %rax, %r15
movzbl %r15b, %edx
cmpl $0xa, %edx
leaq 0x5d9a4(%rip), %rax # 0xe7265
leaq 0x4280e(%rip), %rsi # 0xcc0d6
cmovaeq %rax, %rsi
movq %r14, %rdi
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x89931
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x30(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
movl $0x2, 0x38(%rax,%rcx,8)
movzbl %r15b, %eax
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
movq %rax, 0x40(%rcx,%rdx,8)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x30(%rax)
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
movq %rbx, %rdi
movl %ebp, %esi
movq %r14, %rdx
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x894a6
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsInstPrinter.c
|
Mips_reg_name
|
const char *Mips_reg_name(csh handle, unsigned int reg)
{
#ifndef CAPSTONE_DIET
if (reg >= MIPS_REG_ENDING)
return NULL;
return reg_name_maps[reg].name;
#else
return NULL;
#endif
}
|
cmpl $0x87, %esi
jbe 0x899d7
xorl %eax, %eax
retq
movl %esi, %eax
shlq $0x4, %rax
leaq 0xfcb6c(%rip), %rcx # 0x186550
movq 0x8(%rax,%rcx), %rax
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsMapping.c
|
Mips_group_name
|
const char *Mips_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
// verify group id
if (id >= MIPS_GRP_ENDING || (id > MIPS_GRP_JUMP && id < MIPS_GRP_BITCOUNT))
return NULL;
// NOTE: when new generic groups are added, 2 must be changed accordingly
if (id >= 128)
return group_name_maps[id - 128 + 2].name;
else
return group_name_maps[id].name;
#else
return NULL;
#endif
}
|
cmpl $0xa1, %esi
setae %al
leal -0x2(%rsi), %ecx
cmpl $0x7e, %ecx
setb %cl
orb %al, %cl
je 0x89af6
xorl %eax, %eax
retq
leal -0x7e(%rsi), %eax
cmpl $0x7f, %esi
cmovbel %esi, %eax
shlq $0x4, %rax
leaq 0xfd2c6(%rip), %rcx # 0x186dd0
movq 0x8(%rax,%rcx), %rax
retq
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsMapping.c
|
Mips_map_register
|
mips_reg Mips_map_register(unsigned int r)
{
// for some reasons different Mips modes can map different register number to
// the same Mips register. this function handles the issue for exposing Mips
// operands by mapping internal registers to 'public' register.
unsigned int map[] = { 0,
MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG,
MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2,
MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5,
MIPS_REG_3, MIPS_REG_7, 0, MIPS_REG_RA, MIPS_REG_SP,
MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3,
MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_AT,
MIPS_REG_CC0, MIPS_REG_CC1, MIPS_REG_CC2, MIPS_REG_CC3, MIPS_REG_CC4,
MIPS_REG_CC5, MIPS_REG_CC6, MIPS_REG_CC7, MIPS_REG_0, MIPS_REG_1,
MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6,
MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_0, MIPS_REG_1,
MIPS_REG_2, MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6,
MIPS_REG_7, MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11,
MIPS_REG_12, MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16,
MIPS_REG_17, MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21,
MIPS_REG_22, MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26,
MIPS_REG_27, MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31,
MIPS_REG_10, MIPS_REG_11, MIPS_REG_12, MIPS_REG_13, MIPS_REG_14,
MIPS_REG_15, MIPS_REG_16, MIPS_REG_17, MIPS_REG_18, MIPS_REG_19,
MIPS_REG_20, MIPS_REG_21, MIPS_REG_22, MIPS_REG_23, MIPS_REG_24,
MIPS_REG_25, MIPS_REG_26, MIPS_REG_27, MIPS_REG_28, MIPS_REG_29,
MIPS_REG_30, MIPS_REG_31, MIPS_REG_F0, MIPS_REG_F2, MIPS_REG_F4,
MIPS_REG_F6, MIPS_REG_F8, MIPS_REG_F10, MIPS_REG_F12, MIPS_REG_F14,
MIPS_REG_F16, MIPS_REG_F18, MIPS_REG_F20, MIPS_REG_F22, MIPS_REG_F24,
MIPS_REG_F26, MIPS_REG_F28, MIPS_REG_F30, MIPS_REG_DSPOUTFLAG20, MIPS_REG_DSPOUTFLAG21,
MIPS_REG_DSPOUTFLAG22, MIPS_REG_DSPOUTFLAG23, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2,
MIPS_REG_F3, MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7,
MIPS_REG_F8, MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12,
MIPS_REG_F13, MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17,
MIPS_REG_F18, MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22,
MIPS_REG_F23, MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27,
MIPS_REG_F28, MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_FCC0,
MIPS_REG_FCC1, MIPS_REG_FCC2, MIPS_REG_FCC3, MIPS_REG_FCC4, MIPS_REG_FCC5,
MIPS_REG_FCC6, MIPS_REG_FCC7, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2,
MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7,
MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12,
MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17,
MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22,
MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27,
MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_FP,
MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3, MIPS_REG_F4,
MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8, MIPS_REG_F9,
MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13, MIPS_REG_F14,
MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18, MIPS_REG_F19,
MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23, MIPS_REG_F24,
MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28, MIPS_REG_F29,
MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_GP, MIPS_REG_AC0, MIPS_REG_AC1,
MIPS_REG_AC2, MIPS_REG_AC3, MIPS_REG_0, MIPS_REG_1, MIPS_REG_2,
MIPS_REG_3, MIPS_REG_4, MIPS_REG_5, MIPS_REG_6, MIPS_REG_7,
MIPS_REG_8, MIPS_REG_9, MIPS_REG_10, MIPS_REG_11, MIPS_REG_12,
MIPS_REG_13, MIPS_REG_14, MIPS_REG_15, MIPS_REG_16, MIPS_REG_17,
MIPS_REG_18, MIPS_REG_19, MIPS_REG_20, MIPS_REG_21, MIPS_REG_22,
MIPS_REG_23, MIPS_REG_24, MIPS_REG_25, MIPS_REG_26, MIPS_REG_27,
MIPS_REG_28, MIPS_REG_29, MIPS_REG_30, MIPS_REG_31, MIPS_REG_K0,
MIPS_REG_K1, MIPS_REG_AC0, MIPS_REG_AC1, MIPS_REG_AC2, MIPS_REG_AC3,
MIPS_REG_MPL0, MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1,
MIPS_REG_P2, MIPS_REG_RA, MIPS_REG_S0, MIPS_REG_S1, MIPS_REG_S2,
MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6, MIPS_REG_S7,
MIPS_REG_SP, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3,
MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8,
MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1, MIPS_REG_W0, MIPS_REG_W1,
MIPS_REG_W2, MIPS_REG_W3, MIPS_REG_W4, MIPS_REG_W5, MIPS_REG_W6,
MIPS_REG_W7, MIPS_REG_W8, MIPS_REG_W9, MIPS_REG_W10, MIPS_REG_W11,
MIPS_REG_W12, MIPS_REG_W13, MIPS_REG_W14, MIPS_REG_W15, MIPS_REG_W16,
MIPS_REG_W17, MIPS_REG_W18, MIPS_REG_W19, MIPS_REG_W20, MIPS_REG_W21,
MIPS_REG_W22, MIPS_REG_W23, MIPS_REG_W24, MIPS_REG_W25, MIPS_REG_W26,
MIPS_REG_W27, MIPS_REG_W28, MIPS_REG_W29, MIPS_REG_W30, MIPS_REG_W31,
MIPS_REG_ZERO, MIPS_REG_A0, MIPS_REG_A1, MIPS_REG_A2, MIPS_REG_A3,
MIPS_REG_AC0, MIPS_REG_F0, MIPS_REG_F1, MIPS_REG_F2, MIPS_REG_F3,
MIPS_REG_F4, MIPS_REG_F5, MIPS_REG_F6, MIPS_REG_F7, MIPS_REG_F8,
MIPS_REG_F9, MIPS_REG_F10, MIPS_REG_F11, MIPS_REG_F12, MIPS_REG_F13,
MIPS_REG_F14, MIPS_REG_F15, MIPS_REG_F16, MIPS_REG_F17, MIPS_REG_F18,
MIPS_REG_F19, MIPS_REG_F20, MIPS_REG_F21, MIPS_REG_F22, MIPS_REG_F23,
MIPS_REG_F24, MIPS_REG_F25, MIPS_REG_F26, MIPS_REG_F27, MIPS_REG_F28,
MIPS_REG_F29, MIPS_REG_F30, MIPS_REG_F31, MIPS_REG_DSPOUTFLAG16_19, MIPS_REG_HI,
MIPS_REG_K0, MIPS_REG_K1, MIPS_REG_LO, MIPS_REG_S0, MIPS_REG_S1,
MIPS_REG_S2, MIPS_REG_S3, MIPS_REG_S4, MIPS_REG_S5, MIPS_REG_S6,
MIPS_REG_S7, MIPS_REG_T0, MIPS_REG_T1, MIPS_REG_T2, MIPS_REG_T3,
MIPS_REG_T4, MIPS_REG_T5, MIPS_REG_T6, MIPS_REG_T7, MIPS_REG_T8,
MIPS_REG_T9, MIPS_REG_V0, MIPS_REG_V1,
};
if (r < ARR_SIZE(map))
return map[r];
// cannot find this register
return 0;
}
|
xorl %eax, %eax
cmpl $0x189, %edi # imm = 0x189
ja 0x89b45
movl %edi, %eax
leaq 0x59b5e(%rip), %rcx # 0xe36a0
movl (%rcx,%rax,4), %eax
retq
nop
|
/sidneyp[P]capstone-tricore/arch/Mips/MipsMapping.c
|
decodeMemRIOperands
|
static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder)
{
// Decode the memri field (imm, reg), which has the low 16-bits as the
// displacement and the next 5 bits as the register #.
uint64_t Base = Imm >> 16;
uint64_t Disp = Imm & 0xFFFF;
// assert(Base < 32 && "Invalid base register");
if (Base >= 32)
return MCDisassembler_Fail;
switch (MCInst_getOpcode(Inst)) {
default: break;
case PPC_LBZU:
case PPC_LHAU:
case PPC_LHZU:
case PPC_LWZU:
case PPC_LFSU:
case PPC_LFDU:
// Add the tied output operand.
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
break;
case PPC_STBU:
case PPC_STHU:
case PPC_STWU:
case PPC_STFSU:
case PPC_STFDU:
MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
break;
}
MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16));
MCOperand_CreateReg0(Inst, GP0Regs[Base]);
return MCDisassembler_Success;
}
|
xorl %eax, %eax
cmpq $0x1fffff, %rsi # imm = 0x1FFFFF
ja 0x8aff0
pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
movq %rdi, %rbx
movq %rsi, %r15
shrq $0x10, %r15
callq 0x445a1
leal -0x262(%rax), %ecx
cmpl $0x30, %ecx
jbe 0x8afa4
leal -0x347(%rax), %ecx
cmpl $0x29, %ecx
ja 0x8aff1
movabsq $0x20001042001, %rdx # imm = 0x20001042001
btq %rcx, %rdx
jae 0x8aff1
leaq 0x59d67(%rip), %rax # 0xe4cf0
movl (%rax,%r15,4), %esi
movq %rbx, %rdi
callq 0x4461c
movq %rbx, %rdi
xorl %esi, %esi
movq %rax, %rdx
callq 0x4455c
jmp 0x8afc7
movabsq $0x1000000100841, %rdx # imm = 0x1000000100841
btq %rcx, %rdx
jae 0x8af67
leaq 0x59d35(%rip), %rax # 0xe4cf0
movl (%rax,%r15,4), %esi
movq %rbx, %rdi
callq 0x44631
movswq %r14w, %rsi
movq %rbx, %rdi
callq 0x4465e
leaq 0x59d16(%rip), %rax # 0xe4cf0
movl (%rax,%r15,4), %esi
movq %rbx, %rdi
callq 0x44631
movl $0x3, %eax
popq %rbx
popq %r14
popq %r15
retq
cmpl $0x24e, %eax # imm = 0x24E
je 0x8afb4
jmp 0x8afc7
|
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCDisassembler.c
|
printS16ImmOperand
|
static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
SStream_concat(O, "%u", Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -Imm);
else
SStream_concat(O, "-%u", -Imm);
}
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
MI->flat_insn->detail->ppc.op_count++;
}
} else
printOperand(MI, OpNo, O);
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
callq 0x445a8
movq %rax, %rdi
callq 0x445ee
testb %al, %al
je 0x9cc6b
movq %rbx, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movswl %ax, %ebp
testl %ebp, %ebp
js 0x9cc7c
cmpl $0xa, %ebp
jb 0x9cc8e
leaq 0x4a5fc(%rip), %rsi # 0xe7265
jmp 0x9cc95
movq %rbx, %rdi
movl %ebp, %esi
movq %r14, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0x8c65c
movl %ebp, %edx
negl %edx
cmpl $-0xa, %ebp
ja 0x9cc9c
leaq 0x3849b(%rip), %rsi # 0xd5127
jmp 0x9cca3
leaq 0x2f441(%rip), %rsi # 0xcc0d6
movq %r14, %rdi
movl %ebp, %edx
jmp 0x9cca6
leaq 0x3848d(%rip), %rsi # 0xd5130
movq %r14, %rdi
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x9cd01
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x39(%rax), %ecx
shll $0x4, %ecx
movl $0x2, 0x3c(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x39(%rax), %ecx
shll $0x4, %ecx
movl %ebp, 0x40(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x39(%rax)
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCInstPrinter.c
|
printU16ImmOperand
|
static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
SStream_concat(O, "%u", Imm);
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
MI->flat_insn->detail->ppc.op_count++;
}
} else
printOperand(MI, OpNo, O);
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
callq 0x445a8
movq %rax, %rdi
callq 0x445ee
testb %al, %al
je 0x9cdb6
movq %rbx, %rdi
movl %ebp, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movzwl %ax, %ebp
cmpl $0xa, %ebp
leaq 0x4a51f(%rip), %rax # 0xe7265
leaq 0x2f389(%rip), %rsi # 0xcc0d6
cmovaeq %rax, %rsi
movq %r14, %rdi
movl %ebp, %edx
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0x9cdb1
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x39(%rax), %ecx
shll $0x4, %ecx
movl $0x2, 0x3c(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x39(%rax), %ecx
shll $0x4, %ecx
movl %ebp, 0x40(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x39(%rax)
popq %rbx
popq %r14
popq %rbp
retq
movq %rbx, %rdi
movl %ebp, %esi
movq %r14, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0x8c65c
|
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCInstPrinter.c
|
printMemRegReg
|
static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O)
{
// When used as the base register, r0 reads constant zero rather than
// the value contained in the register. For this reason, the darwin
// assembler requires that we print r0 as 0 (no r) when used as the base.
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0)
SStream_concat0(O, "0");
else
printOperand(MI, OpNo, O);
SStream_concat0(O, ", ");
printOperand(MI, OpNo + 1, O);
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
callq 0x445a8
movq %rax, %rdi
callq 0x445fe
cmpl $0x36, %eax
jne 0x9d1d5
leaq 0x4aad8(%rip), %rsi # 0xe7ca3
movq %rbx, %rdi
callq 0x44686
jmp 0x9d1e2
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
callq 0x8c65c
leaq 0x37e59(%rip), %rsi # 0xd5042
movq %rbx, %rdi
callq 0x44686
incl %ebp
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0x8c65c
|
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCInstPrinter.c
|
set_mem_access
|
static void set_mem_access(MCInst *MI, bool status)
{
if (MI->csh->detail != CS_OPT_ON)
return;
MI->csh->doing_mem = status;
if (status) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
MI->flat_insn->detail->ppc.op_count++;
}
}
|
movq 0x320(%rdi), %rax
cmpl $0x3, 0x68(%rax)
jne 0x9d6ab
movb %sil, 0x70(%rax)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
testb %sil, %sil
je 0x9d6a8
movzbl 0x39(%rax), %ecx
shll $0x4, %ecx
movl $0x3, 0x3c(%rax,%rcx)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
movzbl 0x39(%rax), %ecx
shll $0x4, %ecx
xorl %edx, %edx
movl %edx, 0x40(%rax,%rcx)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
movzbl 0x39(%rax), %ecx
shll $0x4, %ecx
movl %edx, 0x44(%rax,%rcx)
retq
incb 0x39(%rax)
retq
|
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCInstPrinter.c
|
PPC_group_name
|
const char *PPC_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
// verify group id
if (id >= PPC_GRP_ENDING || (id > PPC_GRP_JUMP && id < PPC_GRP_ALTIVEC))
return NULL;
// NOTE: when new generic groups are added, 2 must be changed accordingly
if (id >= 128)
return group_name_maps[id - 128 + 2].name;
else
return group_name_maps[id].name;
#else
return NULL;
#endif
}
|
cmpl $0x8a, %esi
setae %al
leal -0x2(%rsi), %ecx
cmpl $0x7e, %ecx
setb %cl
orb %al, %cl
je 0x9d808
xorl %eax, %eax
retq
leal -0x7e(%rsi), %eax
cmpl $0x7f, %esi
cmovbel %esi, %eax
shlq $0x4, %rax
leaq 0xea344(%rip), %rcx # 0x187b60
movq 0x8(%rax,%rcx), %rax
retq
|
/sidneyp[P]capstone-tricore/arch/PowerPC/PPCMapping.c
|
printDstIdx
|
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat(O, "es:[");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
SStream_concat(O, "[");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movq 0x320(%rdi), %rax
cmpl $0x0, 0x68(%rax)
je 0xa0bba
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x3, 0x60(%rax,%rcx)
movb 0x328(%rbx), %al
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movb %al, 0x80(%rcx,%rdx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
xorl %edx, %edx
movl %edx, 0x68(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %edx, 0x6c(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %edx, 0x70(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1, 0x74(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movq $0x0, 0x78(%rax,%rcx)
movq 0x320(%rbx), %rax
cmpl $0x8, 0x4(%rax)
jne 0xa0bd3
leaq 0x3d1bc(%rip), %rsi # 0xddd83
movq %r14, %rdi
xorl %eax, %eax
callq 0x446cd
jmp 0xa0c12
leaq 0xa62f6(%rip), %rsi # 0x146ed0
movq %r14, %rdi
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xa0c12
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x1c, 0x68(%rax,%rcx)
movq 0x320(%rbx), %rax
cmpl $0x3, 0x68(%rax)
jne 0xa0c23
movb $0x1, 0x70(%rax)
movq %rbx, %rdi
movl %ebp, %esi
movq %r14, %rdx
callq 0xa2319
leaq 0x3dd43(%rip), %rsi # 0xde97a
movq %r14, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x3, 0x68(%rax)
jne 0xa0c61
movb $0x0, 0x70(%rax)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x5c(%rax)
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
|
printopaquemem
|
static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O)
{
SStream_concat0(O, "ptr ");
switch(MI->csh->mode) {
case CS_MODE_16:
if (MI->flat_insn->id == X86_INS_LJMP || MI->flat_insn->id == X86_INS_LCALL)
MI->x86opsize = 4;
else
MI->x86opsize = 2;
break;
case CS_MODE_32:
if (MI->flat_insn->id == X86_INS_LJMP || MI->flat_insn->id == X86_INS_LCALL)
MI->x86opsize = 6;
else
MI->x86opsize = 4;
break;
case CS_MODE_64:
if (MI->flat_insn->id == X86_INS_LJMP || MI->flat_insn->id == X86_INS_LCALL)
MI->x86opsize = 10;
else
MI->x86opsize = 8;
break;
default: // never reach
break;
}
printMemReference(MI, OpNo, O);
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
leaq 0xa4534(%rip), %rsi # 0x146ec0
movq %rdx, %rdi
callq 0x44686
movq 0x320(%r14), %rax
movl 0x4(%rax), %eax
cmpl $0x8, %eax
je 0xa29f1
cmpl $0x4, %eax
je 0xa29ca
cmpl $0x2, %eax
jne 0xa2a16
movq 0x310(%r14), %rax
movl (%rax), %eax
andl $-0x2, %eax
cmpl $0x9c, %eax
je 0xa29e7
movb $0x2, 0x328(%r14)
jmp 0xa2a16
movq 0x310(%r14), %rax
movl (%rax), %eax
andl $-0x2, %eax
cmpl $0x9c, %eax
jne 0xa29e7
movb $0x6, 0x328(%r14)
jmp 0xa2a16
movb $0x4, 0x328(%r14)
jmp 0xa2a16
movq 0x310(%r14), %rax
movl (%rax), %eax
andl $-0x2, %eax
cmpl $0x9c, %eax
jne 0xa2a0e
movb $0xa, 0x328(%r14)
jmp 0xa2a16
movb $0x8, 0x328(%r14)
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xa2bb4
|
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
|
printRoundingControl
|
static void printRoundingControl(MCInst *MI, unsigned Op, SStream *O)
{
int64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, Op)) & 0x3;
switch (Imm) {
case 0: SStream_concat0(O, "{rn-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RN); break;
case 1: SStream_concat0(O, "{rd-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RD); break;
case 2: SStream_concat0(O, "{ru-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RU); break;
case 3: SStream_concat0(O, "{rz-sae}"); op_addAvxSae(MI); op_addAvxRoundingMode(MI, X86_AVX_RM_RZ); break;
default: break; // never reach
}
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rsi, %r14
movq %rdi, %rbx
movl $0x2, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x44606
andl $0x3, %eax
leaq 0xa4314(%rip), %rcx # 0x146ea0
movslq (%rcx,%rax,4), %rsi
addq %rcx, %rsi
leal 0x1(%rax), %ebp
movq %r14, %rdi
callq 0x44686
movq %rbx, %rdi
callq 0xa3e55
movq %rbx, %rdi
movl %ebp, %esi
popq %rbx
popq %r14
popq %rbp
jmp 0xa3e0a
|
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
|
printMemReference
|
static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
{
bool NeedPlus = false;
MCOperand *BaseReg = MCInst_getOperand(MI, Op + X86_AddrBaseReg);
uint64_t ScaleVal = MCOperand_getImm(MCInst_getOperand(MI, Op + X86_AddrScaleAmt));
MCOperand *IndexReg = MCInst_getOperand(MI, Op + X86_AddrIndexReg);
MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp);
MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg);
int reg;
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = MCOperand_getReg(BaseReg);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = MCOperand_getReg(IndexReg);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = (int)ScaleVal;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
// If this has a segment register, print it.
reg = MCOperand_getReg(SegReg);
if (reg) {
_printOperand(MI, Op + X86_AddrSegmentReg, O);
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
}
SStream_concat0(O, ":");
}
SStream_concat0(O, "[");
if (MCOperand_getReg(BaseReg)) {
_printOperand(MI, Op + X86_AddrBaseReg, O);
NeedPlus = true;
}
if (MCOperand_getReg(IndexReg)) {
if (NeedPlus) SStream_concat0(O, " + ");
_printOperand(MI, Op + X86_AddrIndexReg, O);
if (ScaleVal != 1)
SStream_concat(O, "*%u", ScaleVal);
NeedPlus = true;
}
if (MCOperand_isImm(DispSpec)) {
int64_t DispVal = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = DispVal;
if (DispVal) {
if (NeedPlus) {
if (DispVal < 0) {
if (DispVal < -HEX_THRESHOLD)
SStream_concat(O, " - 0x%"PRIx64, -DispVal);
else
SStream_concat(O, " - %"PRIu64, -DispVal);
} else {
if (DispVal > HEX_THRESHOLD)
SStream_concat(O, " + 0x%"PRIx64, DispVal);
else
SStream_concat(O, " + %"PRIu64, DispVal);
}
} else {
// memory reference to an immediate address
if (DispVal < 0) {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & DispVal);
} else {
if (DispVal > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, DispVal);
else
SStream_concat(O, "%"PRIu64, DispVal);
}
}
} else {
// DispVal = 0
if (!NeedPlus) // [0]
SStream_concat0(O, "0");
}
}
SStream_concat0(O, "]");
if (MI->csh->detail)
MI->flat_insn->detail->x86.op_count++;
if (MI->op1_size == 0)
MI->op1_size = MI->x86opsize;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, 0x18(%rsp)
movl %esi, %ebp
movq %rdi, %rbx
callq 0x445a8
movq %rax, %r12
leal 0x1(%rbp), %esi
movq %rbx, %rdi
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movq %rax, %r13
leal 0x2(%rbp), %esi
movq %rbx, %rdi
movl %esi, 0xc(%rsp)
callq 0x445a8
movq %rax, %r14
leal 0x3(%rbp), %esi
movq %rbx, %rdi
callq 0x445a8
movq %rax, 0x10(%rsp)
leal 0x4(%rbp), %esi
movq %rbx, %rdi
movl %esi, 0x8(%rsp)
callq 0x445a8
movq %rax, %r15
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xa2d21
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x3, 0x60(%rax,%rcx)
movb 0x328(%rbx), %al
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movb %al, 0x80(%rcx,%rdx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x0, 0x68(%rax,%rcx)
movq %r12, %rdi
callq 0x445fe
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x6c(%rcx,%rdx)
movq %r14, %rdi
callq 0x445fe
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x70(%rcx,%rdx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %r13d, 0x74(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movq $0x0, 0x78(%rax,%rcx)
movq %r13, 0x20(%rsp)
movq %r15, %rdi
callq 0x445fe
testl %eax, %eax
movq 0x18(%rsp), %r13
je 0xa2d88
movl %eax, %r15d
movq %rbx, %rdi
movl 0x8(%rsp), %esi
movq %r13, %rdx
callq 0xa2265
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xa2d74
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %r15d, 0x68(%rax,%rcx)
leaq 0x40783(%rip), %rsi # 0xe34fe
movq 0x18(%rsp), %r13
movq %r13, %rdi
callq 0x44686
leaq 0x3aff4(%rip), %rsi # 0xddd83
movq %r13, %rdi
callq 0x44686
movq %r12, %rdi
callq 0x445fe
testl %eax, %eax
je 0xa2db5
movq %rbx, %rdi
movl %ebp, %esi
movq %r13, %rdx
callq 0xa2265
movb $0x1, %bpl
jmp 0xa2db7
xorl %ebp, %ebp
movq 0x10(%rsp), %r15
movq %r14, %rdi
callq 0x445fe
testl %eax, %eax
je 0xa2e0a
testb %bpl, %bpl
je 0xa2ddc
leaq 0xa4156(%rip), %rsi # 0x146f2a
movq %r13, %rdi
callq 0x44686
movq %rbx, %rdi
movl 0xc(%rsp), %esi
movq %r13, %rdx
callq 0xa2265
movb $0x1, %bpl
movq 0x20(%rsp), %rdx
cmpq $0x1, %rdx
je 0xa2e0a
leaq 0xa412e(%rip), %rsi # 0x146f2e
movq %r13, %rdi
xorl %eax, %eax
callq 0x446cd
movq %r15, %rdi
callq 0x445ee
testb %al, %al
je 0xa2ef9
movq %r15, %rdi
callq 0x44606
movq 0x320(%rbx), %rcx
cmpl $0x0, 0x68(%rcx)
je 0xa2e4d
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x78(%rcx,%rdx)
testq %rax, %rax
je 0xa2e6b
testb %bpl, %bpl
je 0xa2e85
testq %rax, %rax
js 0xa2e99
cmpq $0xa, %rax
jb 0xa2ed0
leaq 0xa40d9(%rip), %rsi # 0x146f42
jmp 0xa2ee0
testb %bpl, %bpl
jne 0xa2ef9
leaq 0x44e28(%rip), %rsi # 0xe7ca3
movq %r13, %rdi
callq 0x44686
jmp 0xa2ef9
testq %rax, %rax
js 0xa2eae
cmpq $0xa, %rax
jb 0xa2ed9
leaq 0xa40ae(%rip), %rsi # 0x146f45
jmp 0xa2ee0
movq %rax, %rdx
negq %rdx
cmpq $-0xa, %rax
ja 0xa2ee8
leaq 0xa4086(%rip), %rsi # 0x146f32
jmp 0xa2eef
movq 0x320(%rbx), %rcx
movslq 0x4(%rcx), %rcx
leaq 0x189300(%rip), %rdx # 0x22c1c0
movq (%rdx,%rcx,8), %rdx
andq %rax, %rdx
leaq 0xa4077(%rip), %rsi # 0x146f45
jmp 0xa2eef
leaq 0xa4074(%rip), %rsi # 0x146f4b
jmp 0xa2ee0
leaq 0xa406e(%rip), %rsi # 0x146f4e
movq %r13, %rdi
movq %rax, %rdx
jmp 0xa2ef2
leaq 0xa404c(%rip), %rsi # 0x146f3b
movq %r13, %rdi
xorl %eax, %eax
callq 0x446cd
leaq 0x3ba7a(%rip), %rsi # 0xde97a
movq %r13, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xa2f26
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x5c(%rax)
cmpb $0x0, 0x6(%rbx)
jne 0xa2f35
movb 0x328(%rbx), %al
movb %al, 0x6(%rbx)
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
|
printMemOffset
|
static void printMemOffset(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *DispSpec = MCInst_getOperand(MI, Op);
MCOperand *SegReg = MCInst_getOperand(MI, Op + 1);
int reg;
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
// If this has a segment register, print it.
reg = MCOperand_getReg(SegReg);
if (reg) {
_printOperand(MI, Op + 1, O);
SStream_concat0(O, ":");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
}
}
SStream_concat0(O, "[");
if (MCOperand_isImm(DispSpec)) {
int64_t imm = MCOperand_getImm(DispSpec);
if (MI->csh->detail)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
if (imm < 0) {
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->csh->mode] & imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
}
}
SStream_concat0(O, "]");
if (MI->csh->detail)
MI->flat_insn->detail->x86.op_count++;
if (MI->op1_size == 0)
MI->op1_size = MI->x86opsize;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
xorl %ebp, %ebp
xorl %esi, %esi
callq 0x445a8
movq %rax, %r15
movq %rbx, %rdi
movl $0x1, %esi
callq 0x445a8
movq 0x320(%rbx), %rcx
cmpl $0x0, 0x68(%rcx)
je 0xa305c
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl $0x3, 0x60(%rcx,%rdx)
movb 0x328(%rbx), %cl
movq 0x310(%rbx), %rdx
movq 0xe8(%rdx), %rdx
movzbl 0x5c(%rdx), %esi
leaq (%rsi,%rsi,2), %rsi
shll $0x4, %esi
movb %cl, 0x80(%rdx,%rsi)
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %ebp, 0x68(%rcx,%rdx)
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %ebp, 0x6c(%rcx,%rdx)
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %ebp, 0x70(%rcx,%rdx)
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl $0x1, 0x74(%rcx,%rdx)
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq $0x0, 0x78(%rcx,%rdx)
movq %rax, %rdi
callq 0x445fe
testl %eax, %eax
je 0xa30b3
movl %eax, %ebp
movq %rbx, %rdi
movl $0x1, %esi
movq %r14, %rdx
callq 0xa2265
leaq 0x4047d(%rip), %rsi # 0xe34fe
movq %r14, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xa30b3
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl %ebp, 0x68(%rax,%rcx)
leaq 0x3acc9(%rip), %rsi # 0xddd83
movq %r14, %rdi
callq 0x44686
movq %r15, %rdi
callq 0x445ee
testb %al, %al
je 0xa3152
movq %r15, %rdi
callq 0x44606
movq 0x320(%rbx), %rcx
cmpl $0x0, 0x68(%rcx)
je 0xa3105
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x78(%rcx,%rdx)
testq %rax, %rax
js 0xa3119
cmpq $0xa, %rax
jb 0xa313e
leaq 0xa3e2e(%rip), %rsi # 0x146f45
jmp 0xa3145
movq 0x320(%rbx), %rcx
movslq 0x4(%rcx), %rcx
leaq 0x189095(%rip), %rdx # 0x22c1c0
movq (%rdx,%rcx,8), %rdx
andq %rax, %rdx
leaq 0xa3e0c(%rip), %rsi # 0x146f45
movq %r14, %rdi
jmp 0xa314b
leaq 0xa3e09(%rip), %rsi # 0x146f4e
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq 0x446cd
leaq 0x3b821(%rip), %rsi # 0xde97a
movq %r14, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xa317f
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x5c(%rax)
cmpb $0x0, 0x6(%rbx)
jne 0xa318e
movb 0x328(%rbx), %al
movb %al, 0x6(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
nopl (%rax)
|
/sidneyp[P]capstone-tricore/arch/X86/X86IntelInstPrinter.c
|
X86_get_insn_id
|
void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
// special cases when regs_write[] depends on arch
switch(id) {
default:
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
break;
case X86_RDTSC:
if (h->mode == CS_MODE_64) {
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
} else {
insn->detail->regs_write[0] = X86_REG_EAX;
insn->detail->regs_write[1] = X86_REG_EDX;
insn->detail->regs_write_count = 2;
}
break;
case X86_RDTSCP:
if (h->mode == CS_MODE_64) {
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
} else {
insn->detail->regs_write[0] = X86_REG_EAX;
insn->detail->regs_write[1] = X86_REG_ECX;
insn->detail->regs_write[2] = X86_REG_EDX;
insn->detail->regs_write_count = 3;
}
break;
}
switch(insn->id) {
default:
break;
case X86_INS_LOOP:
case X86_INS_LOOPE:
case X86_INS_LOOPNE:
switch(h->mode) {
default: break;
case CS_MODE_16:
insn->detail->regs_read[0] = X86_REG_CX;
insn->detail->regs_read_count = 1;
insn->detail->regs_write[0] = X86_REG_CX;
insn->detail->regs_write_count = 1;
break;
case CS_MODE_32:
insn->detail->regs_read[0] = X86_REG_ECX;
insn->detail->regs_read_count = 1;
insn->detail->regs_write[0] = X86_REG_ECX;
insn->detail->regs_write_count = 1;
break;
case CS_MODE_64:
insn->detail->regs_read[0] = X86_REG_RCX;
insn->detail->regs_read_count = 1;
insn->detail->regs_write[0] = X86_REG_RCX;
insn->detail->regs_write_count = 1;
break;
}
// LOOPE & LOOPNE also read EFLAGS
if (insn->id != X86_INS_LOOP) {
insn->detail->regs_read[1] = X86_REG_EFLAGS;
insn->detail->regs_read_count = 2;
}
break;
case X86_INS_LODSB:
case X86_INS_LODSD:
case X86_INS_LODSQ:
case X86_INS_LODSW:
switch(h->mode) {
default:
break;
case CS_MODE_16:
arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI);
arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI);
break;
case CS_MODE_64:
arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI);
arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI);
break;
}
break;
case X86_INS_SCASB:
case X86_INS_SCASW:
case X86_INS_SCASQ:
case X86_INS_STOSB:
case X86_INS_STOSD:
case X86_INS_STOSQ:
case X86_INS_STOSW:
switch(h->mode) {
default:
break;
case CS_MODE_16:
arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI);
arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI);
break;
case CS_MODE_64:
arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI);
arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI);
break;
}
break;
case X86_INS_CMPSB:
case X86_INS_CMPSD:
case X86_INS_CMPSQ:
case X86_INS_CMPSW:
case X86_INS_MOVSB:
case X86_INS_MOVSW:
case X86_INS_MOVSD:
case X86_INS_MOVSQ:
switch(h->mode) {
default:
break;
case CS_MODE_16:
arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_DI);
arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_DI);
arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_SI);
arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_SI);
break;
case CS_MODE_64:
arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_EDI, X86_REG_RDI);
arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_EDI, X86_REG_RDI);
arr_replace(insn->detail->regs_read, insn->detail->regs_read_count, X86_REG_ESI, X86_REG_RSI);
arr_replace(insn->detail->regs_write, insn->detail->regs_write_count, X86_REG_ESI, X86_REG_RSI);
break;
}
break;
}
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
insn->detail->groups[insn->detail->groups_count] = X86_GRP_JUMP;
insn->detail->groups_count++;
}
switch (insns[i].id) {
case X86_OUT8ir:
case X86_OUT16ir:
case X86_OUT32ir:
if (insn->detail->x86.operands[0].imm == -78) {
// Writing to port 0xb2 causes an SMI on most platforms
// See: http://cs.gmu.edu/~tr-admin/papers/GMU-CS-TR-2011-8.pdf
insn->detail->groups[insn->detail->groups_count] = X86_GRP_INT;
insn->detail->groups_count++;
}
break;
default:
break;
}
#endif
}
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r15
leaq 0x78(%rdi), %rcx
leaq 0x189181(%rip), %r14 # 0x22c3f0
movq %r14, %rdi
movl $0x1726, %esi # imm = 0x1726
callq 0x47614
testw %ax, %ax
je 0xa3793
movzwl %ax, %eax
imulq $0x2e, %rax, %rax
movzwl 0x2(%rax,%r14), %ecx
movl %ecx, (%rbx)
cmpl $0x0, 0x68(%r15)
je 0xa3793
addq %rax, %r14
movq 0xe8(%rbx), %rax
leaq 0x4(%r14), %rdi
movl 0xc(%r14), %ecx
movl %ecx, 0x8(%rax)
movq 0x4(%r14), %rcx
movq %rcx, (%rax)
callq 0x476de
movq 0xe8(%rbx), %rcx
movb %al, 0xc(%rcx)
cmpl $0x935, %ebp # imm = 0x935
je 0xa3302
cmpl $0x936, %ebp # imm = 0x936
jne 0xa3326
addq $0xd, %rcx
cmpl $0x8, 0x4(%r15)
je 0xa3311
movb $0x13, (%rcx)
movq 0xe8(%rbx), %rax
movb $0x16, 0xe(%rax)
movq 0xe8(%rbx), %rax
movb $0x18, 0xf(%rax)
movb $0x3, %al
jmp 0xa333f
addq $0xd, %rcx
cmpl $0x8, 0x4(%r15)
jne 0xa345e
leaq 0x10(%r14), %rdi
movl 0x20(%r14), %eax
movl %eax, 0x10(%rcx)
movups 0x10(%r14), %xmm0
movups %xmm0, (%rcx)
jmp 0xa333a
leaq 0x10(%r14), %rdi
movl 0x20(%r14), %eax
movl %eax, 0x1d(%rcx)
movups 0x10(%r14), %xmm0
movups %xmm0, 0xd(%rcx)
callq 0x476de
movq 0xe8(%rbx), %rcx
movb %al, 0x21(%rcx)
movl (%rbx), %eax
cmpl $0x1ce, %eax # imm = 0x1CE
jg 0xa33a9
leal -0x60(%rax), %edx
cmpl $0x4, %edx
jbe 0xa341d
leal -0x148(%rax), %edx
cmpl $0x4, %edx
jae 0xa3473
movl 0x4(%r15), %eax
cmpl $0x8, %eax
je 0xa34f3
cmpl $0x2, %eax
jne 0xa371a
movzbl 0xc(%rcx), %eax
testq %rax, %rax
je 0xa36cb
xorl %edx, %edx
cmpb $0x1d, (%rcx,%rdx)
je 0xa36c0
incq %rdx
cmpq %rdx, %rax
jne 0xa3392
jmp 0xa36cb
leal -0x266(%rax), %edx
cmpl $0x38, %edx
ja 0xa3400
movabsq $0x1e000000000000d, %rsi # imm = 0x1E000000000000D
btq %rdx, %rsi
jae 0xa3400
movl 0x4(%r15), %eax
cmpl $0x8, %eax
je 0xa34cd
cmpl $0x2, %eax
jne 0xa371a
movzbl 0xc(%rcx), %eax
testq %rax, %rax
je 0xa3665
xorl %edx, %edx
cmpb $0x17, (%rcx,%rdx)
je 0xa365a
incq %rdx
cmpq %rdx, %rax
jne 0xa33e9
jmp 0xa3665
addl $0xfffffe31, %eax # imm = 0xFFFFFE31
cmpl $0x6, %eax
ja 0xa371a
movl $0x53, %edx
btl %eax, %edx
jb 0xa3426
jmp 0xa371a
cmpl $0x3, %edx
je 0xa335e
movl 0x4(%r15), %eax
cmpl $0x8, %eax
je 0xa34a7
cmpl $0x2, %eax
jne 0xa371a
movzbl 0xc(%rcx), %eax
testq %rax, %rax
je 0xa3524
xorl %edx, %edx
cmpb $0x17, (%rcx,%rdx)
je 0xa3519
incq %rdx
cmpq %rdx, %rax
jne 0xa3447
jmp 0xa3524
movb $0x13, (%rcx)
movq 0xe8(%rbx), %rax
movb $0x18, 0xe(%rax)
movb $0x2, %al
jmp 0xa333f
addl $0xfffffeb4, %eax # imm = 0xFFFFFEB4
cmpl $0x3, %eax
jae 0xa371a
movl 0x4(%r15), %eax
cmpl $0x2, %eax
je 0xa361d
cmpl $0x8, %eax
je 0xa3619
cmpl $0x4, %eax
jne 0xa363a
movb $0x16, %al
jmp 0xa361f
movzbl 0xc(%rcx), %eax
testq %rax, %rax
je 0xa35a4
xorl %edx, %edx
cmpb $0x17, (%rcx,%rdx)
je 0xa3599
incq %rdx
cmpq %rdx, %rax
jne 0xa34b6
jmp 0xa35a4
movzbl 0xc(%rcx), %eax
testq %rax, %rax
je 0xa369d
xorl %edx, %edx
cmpb $0x17, (%rcx,%rdx)
je 0xa3692
incq %rdx
cmpq %rdx, %rax
jne 0xa34dc
jmp 0xa369d
movzbl 0xc(%rcx), %eax
testq %rax, %rax
je 0xa36f9
xorl %edx, %edx
cmpb $0x1d, (%rcx,%rdx)
je 0xa36ee
incq %rdx
cmpq %rdx, %rax
jne 0xa3502
jmp 0xa36f9
movb $0xe, (%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0x21(%rcx), %eax
testq %rax, %rax
je 0xa354c
xorl %edx, %edx
cmpb $0x17, 0xd(%rcx,%rdx)
je 0xa3540
incq %rdx
cmpq %rdx, %rax
jne 0xa352f
jmp 0xa354c
movb $0xe, 0xd(%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0xc(%rcx), %eax
testq %rax, %rax
je 0xa3572
xorl %edx, %edx
cmpb $0x1d, (%rcx,%rdx)
je 0xa3567
incq %rdx
cmpq %rdx, %rax
jne 0xa3557
jmp 0xa3572
movb $0x2d, (%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0x21(%rcx), %eax
testq %rax, %rax
je 0xa371a
xorl %edx, %edx
cmpb $0x1d, 0xd(%rcx,%rdx)
je 0xa36e7
incq %rdx
cmpq %rdx, %rax
jne 0xa3581
jmp 0xa371a
movb $0x27, (%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0x21(%rcx), %eax
testq %rax, %rax
je 0xa35cc
xorl %edx, %edx
cmpb $0x17, 0xd(%rcx,%rdx)
je 0xa35c0
incq %rdx
cmpq %rdx, %rax
jne 0xa35af
jmp 0xa35cc
movb $0x27, 0xd(%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0xc(%rcx), %eax
testq %rax, %rax
je 0xa35f2
xorl %edx, %edx
cmpb $0x1d, (%rcx,%rdx)
je 0xa35e7
incq %rdx
cmpq %rdx, %rax
jne 0xa35d7
jmp 0xa35f2
movb $0x2b, (%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0x21(%rcx), %eax
testq %rax, %rax
je 0xa371a
xorl %edx, %edx
cmpb $0x1d, 0xd(%rcx,%rdx)
je 0xa3715
incq %rdx
cmpq %rdx, %rax
jne 0xa3601
jmp 0xa371a
movb $0x26, %al
jmp 0xa361f
movb $0xc, %al
movb %al, (%rcx)
movq 0xe8(%rbx), %rcx
movb $0x1, %dl
movb %dl, 0xc(%rcx)
movb %al, 0xd(%rcx)
movq 0xe8(%rbx), %rcx
movb %dl, 0x21(%rcx)
cmpl $0x14c, (%rbx) # imm = 0x14C
je 0xa371a
movb $0x19, 0x1(%rcx)
movq 0xe8(%rbx), %rax
movb $0x2, 0xc(%rax)
jmp 0xa371a
movb $0xe, (%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0x21(%rcx), %eax
testq %rax, %rax
je 0xa371a
xorl %edx, %edx
cmpb $0x17, 0xd(%rcx,%rdx)
je 0xa3688
incq %rdx
cmpq %rdx, %rax
jne 0xa3674
jmp 0xa371a
movb $0xe, 0xd(%rcx,%rdx)
jmp 0xa371a
movb $0x27, (%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0x21(%rcx), %eax
testq %rax, %rax
je 0xa371a
xorl %edx, %edx
cmpb $0x17, 0xd(%rcx,%rdx)
je 0xa36b9
incq %rdx
cmpq %rdx, %rax
jne 0xa36a8
jmp 0xa371a
movb $0x27, 0xd(%rcx,%rdx)
jmp 0xa371a
movb $0x2d, (%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0x21(%rcx), %eax
testq %rax, %rax
je 0xa371a
xorl %edx, %edx
cmpb $0x1d, 0xd(%rcx,%rdx)
je 0xa36e7
incq %rdx
cmpq %rdx, %rax
jne 0xa36d6
jmp 0xa371a
movb $0x2d, 0xd(%rcx,%rdx)
jmp 0xa371a
movb $0x2b, (%rcx,%rdx)
movq 0xe8(%rbx), %rcx
movzbl 0x21(%rcx), %eax
testq %rax, %rax
je 0xa371a
xorl %edx, %edx
cmpb $0x1d, 0xd(%rcx,%rdx)
je 0xa3715
incq %rdx
cmpq %rdx, %rax
jne 0xa3704
jmp 0xa371a
movb $0x2b, 0xd(%rcx,%rdx)
movq 0xe8(%rbx), %rax
leaq 0x24(%r14), %rdi
movq 0x24(%r14), %rcx
movq %rcx, 0x22(%rax)
callq 0x476de
movq 0xe8(%rbx), %rcx
movb %al, 0x2a(%rcx)
cmpb $0x0, 0x2c(%r14)
jne 0xa374a
cmpb $0x1, 0x2d(%r14)
jne 0xa3761
movzbl %al, %eax
movb $0x1, 0x22(%rcx,%rax)
movq 0xe8(%rbx), %rcx
movb 0x2a(%rcx), %al
incb %al
movb %al, 0x2a(%rcx)
movzwl (%r14), %edx
addl $0xfffff89a, %edx # imm = 0xFFFFF89A
cmpl $0x4, %edx
ja 0xa3793
movl $0x15, %esi
btl %edx, %esi
jae 0xa3793
cmpq $-0x4e, 0x68(%rcx)
jne 0xa3793
movzbl %al, %eax
movb $0x4, 0x22(%rcx,%rax)
movq 0xe8(%rbx), %rax
incb 0x2a(%rax)
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
|
X86_insn_reg_intel
|
x86_reg X86_insn_reg_intel(unsigned int id)
{
unsigned int i;
for (i = 0; i < ARR_SIZE(insn_regs_intel); i++) {
if (insn_regs_intel[i].insn == id) {
return insn_regs_intel[i].reg;
}
}
// not found
return 0;
}
|
xorl %eax, %eax
leaq 0xa3b49(%rip), %rcx # 0x1472f0
movzwl (%rcx,%rax,8), %edx
cmpl %edi, %edx
je 0xa37bb
incq %rax
cmpq $0x6f, %rax
jne 0xa37a7
xorl %eax, %eax
retq
movl 0x4(%rcx,%rax,8), %eax
retq
|
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
|
X86_insn_reg_att2
|
bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, x86_reg *reg2)
{
unsigned int i;
for (i = 0; i < ARR_SIZE(insn_regs_intel2); i++) {
if (insn_regs_intel2[i].insn == id) {
// reverse order of Intel syntax registers
*reg1 = insn_regs_intel2[i].reg2;
*reg2 = insn_regs_intel2[i].reg1;
return true;
}
}
// not found
return false;
}
|
cmpl $0x37f, %edi # imm = 0x37F
jne 0xa3820
leaq 0xa3e54(%rip), %rcx # 0x147670
movb $0x1, %al
jmp 0xa384c
movq $-0x1, %rax
leaq 0xa3e42(%rip), %rcx # 0x147670
cmpq $0x4, %rax
je 0xa3857
movzwl 0xc(%rcx), %r8d
addq $0xc, %rcx
incq %rax
cmpl %edi, %r8d
jne 0xa382e
cmpq $0x5, %rax
setb %al
movl 0x4(%rcx), %edi
movl 0x8(%rcx), %ecx
movl %ecx, (%rsi)
movl %edi, (%rdx)
retq
xorl %eax, %eax
retq
|
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
|
add_cx
|
static void add_cx(MCInst *MI)
{
if (MI->csh->detail) {
x86_reg cx;
if (MI->csh->mode & CS_MODE_16)
cx = X86_REG_CX;
else if (MI->csh->mode & CS_MODE_32)
cx = X86_REG_ECX;
else // 64-bit
cx = X86_REG_RCX;
MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = cx;
MI->flat_insn->detail->regs_read_count++;
MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = cx;
MI->flat_insn->detail->regs_write_count++;
}
}
|
movq 0x320(%rdi), %rax
cmpl $0x0, 0x68(%rax)
je 0xa3c5a
movl 0x4(%rax), %eax
testb $0x4, %al
sete %cl
shlb $0x4, %cl
addb $0x16, %cl
testb $0x2, %al
movzbl %cl, %eax
movl $0xc, %ecx
cmovel %eax, %ecx
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
movzbl 0xc(%rax), %edx
movb %cl, (%rax,%rdx)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
incb 0xc(%rax)
movzbl 0x21(%rax), %edx
movb %cl, 0xd(%rax,%rdx)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
incb 0x21(%rax)
retq
|
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
|
op_addReg
|
void op_addReg(MCInst *MI, int reg)
{
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
MI->flat_insn->detail->x86.op_count++;
}
if (MI->op1_size == 0)
MI->op1_size = MI->csh->regsize_map[reg];
}
|
movq 0x320(%rdi), %rax
cmpl $0x0, 0x68(%rax)
movslq %esi, %rax
je 0xa3cef
movq 0x310(%rdi), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl $0x1, 0x60(%rcx,%rdx)
movq 0x310(%rdi), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movl %eax, 0x68(%rcx,%rdx)
movq 0x310(%rdi), %rcx
movq 0x320(%rdi), %rdx
movq 0xa8(%rdx), %rdx
movb (%rdx,%rax), %dl
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %esi
leaq (%rsi,%rsi,2), %rsi
shll $0x4, %esi
movb %dl, 0x80(%rcx,%rsi)
movq 0x310(%rdi), %rcx
movq 0xe8(%rcx), %rcx
incb 0x5c(%rcx)
cmpb $0x0, 0x6(%rdi)
je 0xa3cf6
retq
movq 0x320(%rdi), %rcx
movq 0xa8(%rcx), %rcx
movb (%rcx,%rax), %al
movb %al, 0x6(%rdi)
retq
|
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
|
op_addImm
|
void op_addImm(MCInst *MI, int v)
{
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = v;
// if op_count > 0, then this operand's size is taken from the destination op
if (MI->csh->syntax == CS_OPT_SYNTAX_INTEL) {
if (MI->flat_insn->detail->x86.op_count > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size;
else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
} else
MI->has_imm = true;
MI->flat_insn->detail->x86.op_count++;
}
if (MI->op1_size == 0)
MI->op1_size = MI->imm_size;
}
|
movq 0x320(%rdi), %rax
cmpl $0x0, 0x68(%rax)
je 0xa3dbb
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movl $0x2, 0x60(%rax,%rcx)
movslq %esi, %rax
movq 0x310(%rdi), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x5c(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
shll $0x4, %edx
movq %rax, 0x68(%rcx,%rdx)
movq 0x320(%rdi), %rax
cmpl $0x1, 0x6c(%rax)
jne 0xa3d98
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
movzbl 0x5c(%rax), %ecx
testq %rcx, %rcx
je 0xa3d9e
movb 0x80(%rax), %dl
leaq (%rcx,%rcx,2), %rcx
shll $0x4, %ecx
movb %dl, 0x80(%rax,%rcx)
jmp 0xa3daa
movb $0x1, 0x5(%rdi)
jmp 0xa3daa
movb 0x32d(%rdi), %cl
movb %cl, 0x80(%rax)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
incb 0x5c(%rax)
cmpb $0x0, 0x6(%rdi)
je 0xa3dc2
retq
movb 0x32d(%rdi), %al
movb %al, 0x6(%rdi)
retq
|
/sidneyp[P]capstone-tricore/arch/X86/X86Mapping.c
|
Sparc_getInstruction
|
static DecodeStatus readInstruction32(const uint8_t *code, size_t len, uint32_t *Insn)
{
uint8_t Bytes[4];
if (len < 4)
// not enough data
return MCDisassembler_Fail;
memcpy(Bytes, code, 4);
// Encoded as a big-endian 32-bit word in the stream.
*Insn = (Bytes[3] << 0) |
(Bytes[2] << 8) |
(Bytes[1] << 16) |
(Bytes[0] << 24);
return MCDisassembler_Success;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
cmpq $0x4, %rdx
jae 0xa3ebc
xorl %r15d, %r15d
jmp 0xa4b8f
movq %r9, %rbx
movq %r8, 0x20(%rsp)
movzbl (%rsi), %ebp
movzbl 0x1(%rsi), %r15d
movzbl 0x2(%rsi), %eax
movzbl 0x3(%rsi), %esi
movq %rax, 0x18(%rsp)
shll $0x8, %eax
movl %r15d, %r12d
shll $0x10, %r12d
orl %eax, %r12d
movq %rbp, 0x8(%rsp)
shll $0x18, %ebp
orl %r12d, %ebp
movq %rcx, (%rsp)
movq 0x310(%rcx), %rax
movq 0xe8(%rax), %rdi
testq %rdi, %rdi
je 0xa3f1a
movl $0x5f8, %edx # imm = 0x5F8
movq %rsi, %r14
xorl %esi, %esi
callq 0x430c0
movq %r14, %rsi
movq %rsi, 0x10(%rsp)
orl %esi, %ebp
leaq 0x1cada8(%rip), %r9 # 0x26ecd0
xorl %r8d, %r8d
leaq 0xa5e1e(%rip), %rsi # 0x149d50
movl $0xffffffff, %edi # imm = 0xFFFFFFFF
movzbl (%r9), %eax
decl %eax
cmpl $0x5, %eax
ja 0xa3eb4
movslq (%rsi,%rax,4), %rax
addq %rsi, %rax
jmpq *%rax
movq %r9, %rax
incq %rax
xorl %edx, %edx
xorl %r10d, %r10d
xorl %ecx, %ecx
movzbl (%rax,%rdx), %r9d
movl %r9d, %r11d
andl $0x7f, %r11d
shll %cl, %r11d
addl %r11d, %r10d
addl $0x7, %ecx
incq %rdx
testb %r9b, %r9b
js 0xa3f5c
movl %edx, %ecx
leaq (%rax,%rcx), %r9
addq $0x2, %r9
cmpl %r10d, %r8d
je 0xa3f37
addq %rcx, %rax
movzwl (%rax), %eax
addq %rax, %r9
jmp 0xa3f37
leaq 0x1(%r9), %rax
xorl %ecx, %ecx
cmpb $0x0, (%rax,%rcx)
leaq 0x1(%rcx), %rcx
js 0xa3f99
movl %ecx, %ecx
addq %rcx, %rax
addq %r9, %rcx
incq %rcx
xorl %edx, %edx
cmpb $0x0, (%rcx,%rdx)
leaq 0x1(%rdx), %rdx
js 0xa3fb0
movl %edx, %ecx
addq %rcx, %rax
movq %rax, %r9
jmp 0xa3f37
movzbl 0x1(%r9), %eax
movb 0x2(%r9), %dl
movl $0xffffffff, %r10d # imm = 0xFFFFFFFF
movl %edx, %ecx
shll %cl, %r10d
notl %r10d
movl %eax, %ecx
shll %cl, %r10d
cmpb $0x20, %dl
cmovel %edi, %r10d
movq %r9, %rdx
addq $0x3, %rdx
xorl %r9d, %r9d
xorl %r11d, %r11d
xorl %ecx, %ecx
movzbl (%rdx,%r9), %r14d
movl %r14d, %r13d
andl $0x7f, %r13d
shll %cl, %r13d
addl %r13d, %r11d
addl $0x7, %ecx
incq %r9
testb %r14b, %r14b
js 0xa3ff9
andl %ebp, %r10d
movl %eax, %ecx
shrl %cl, %r10d
movl %r9d, %eax
leaq (%rdx,%rax), %r9
addq $0x2, %r9
cmpl %r11d, %r10d
je 0xa3f37
addq %rax, %rdx
movzwl (%rdx), %eax
addq %rax, %r9
jmp 0xa3f37
incq %r9
xorl %eax, %eax
cmpb $0x0, (%r9,%rax)
leaq 0x1(%rax), %rax
js 0xa4045
movl %eax, %eax
addq %rax, %r9
addq $0x2, %r9
jmp 0xa3f37
movb 0x1(%r9), %al
movb 0x2(%r9), %dl
addq $0x3, %r9
movl $0xffffffff, %r8d # imm = 0xFFFFFFFF
movl %edx, %ecx
shll %cl, %r8d
notl %r8d
movl %eax, %ecx
shll %cl, %r8d
cmpb $0x20, %dl
cmovel %edi, %r8d
andl %ebp, %r8d
shrl %cl, %r8d
jmp 0xa3f37
incq %r9
xorl %eax, %eax
xorl %esi, %esi
xorl %ecx, %ecx
movzbl (%r9,%rax), %edx
movl %edx, %edi
andl $0x7f, %edi
shll %cl, %edi
addl %edi, %esi
addl $0x7, %ecx
incq %rax
testb %dl, %dl
js 0xa4098
movl %eax, %eax
addq %rax, %r9
xorl %r13d, %r13d
xorl %ecx, %ecx
movzbl (%r9), %eax
movl %eax, %edx
andl $0x7f, %edx
shll %cl, %edx
addl %edx, %r13d
addl $0x7, %ecx
incq %r9
testb %al, %al
js 0xa40ba
movq (%rsp), %rdi
callq 0x4459a
decl %r13d
cmpl $0x45, %r13d
ja 0xa4b70
leaq 0xa5c79(%rip), %rax # 0x149d68
movslq (%rax,%r13,4), %rcx
addq %rax, %rcx
jmpq *%rcx
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5d79(%rip), %rbx # 0x149e80
jmp 0xa4a40
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5d65(%rip), %r14 # 0x149e80
movl (%r14,%rax,2), %ebx
movq (%rsp), %r15
movq %r15, %rdi
movl %ebx, %esi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
movl (%r12,%r14), %esi
movq %r15, %rdi
callq 0x44631
movq 0x10(%rsp), %rax
andl $0x1f, %eax
movl (%r14,%rax,4), %esi
movq %r15, %rdi
callq 0x44631
movq %r15, %rdi
jmp 0xa440e
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5d14(%rip), %rbx # 0x149e80
jmp 0xa493f
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa5d80(%rip), %rax # 0x149f00
jmp 0xa43fa
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5d6c(%rip), %rbx # 0x149f00
movl (%rbx,%rax,2), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
leaq 0xa5cce(%rip), %rax # 0x149e80
movl (%r12,%rax), %esi
jmp 0xa4a5b
leaq 0xa89(%rip), %r9 # 0xa4c4b
jmp 0xa4635
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5d2a(%rip), %r14 # 0x149f00
jmp 0xa47d2
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa5c96(%rip), %rax # 0x149e80
jmp 0xa4320
movq 0x10(%rsp), %rcx
andl $0x1f, %ecx
leaq 0xa5c82(%rip), %rax # 0x149e80
movl (%rax,%rcx,4), %esi
movq (%rsp), %rdi
jmp 0xa4aa6
movq (%rsp), %rdi
movl %ebp, %esi
callq 0xa4ce8
jmp 0xa4923
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa5cd7(%rip), %rax # 0x149f00
jmp 0xa4715
movq 0x8(%rsp), %rcx
shrl %ecx
andl $0x1f, %ecx
movl $0xcccccccc, %eax # imm = 0xCCCCCCCC
btl %ecx, %eax
jb 0xa3eb4
leaq 0xa5db3(%rip), %rax # 0x14a000
movl (%rax,%rcx,4), %esi
jmp 0xa452c
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5d1c(%rip), %rbx # 0x149f80
jmp 0xa4a40
movq 0x8(%rsp), %rcx
shrl %ecx
andl $0x1f, %ecx
movl $0xcccccccc, %eax # imm = 0xCCCCCCCC
btl %ecx, %eax
jb 0xa3eb4
leaq 0xa5d78(%rip), %rax # 0x14a000
movl (%rax,%rcx,4), %esi
jmp 0xa4323
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5be1(%rip), %r14 # 0x149e80
jmp 0xa47d2
leaq 0x97d(%rip), %r9 # 0xa4c28
jmp 0xa4635
movq 0x8(%rsp), %rcx
shrl %ecx
andl $0x1f, %ecx
cmpl $0x3, %ecx
ja 0xa3eb4
leaq 0xa5db6(%rip), %rax # 0x14a080
movl (%rax,%rcx,4), %esi
jmp 0xa49a3
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5b9f(%rip), %rbx # 0x149e80
movl (%rbx,%rax,2), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
movl (%r12,%rbx), %esi
movq %r14, %rdi
callq 0x44631
movq 0x10(%rsp), %rsi
andl $0x3f, %esi
jmp 0xa4887
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa5be0(%rip), %rax # 0x149f00
movl (%rax,%rcx,2), %esi
movq (%rsp), %rbx
movq %rbx, %rdi
callq 0x44631
movq 0x10(%rsp), %rcx
andl $0x1f, %ecx
leaq 0xa5c42(%rip), %rax # 0x149f80
jmp 0xa4aa0
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa5b2e(%rip), %rax # 0x149e80
movl (%rax,%rcx,2), %esi
jmp 0xa4763
shrl $0xc, %r12d
andl $0x7c, %r12d
leaq 0xa5b17(%rip), %rax # 0x149e80
movl (%r12,%rax), %esi
movq (%rsp), %rbx
movq %rbx, %rdi
callq 0x44631
movl 0x10(%rsp), %esi
movq %rbx, %rdi
jmp 0xa4503
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5aec(%rip), %rbx # 0x149e80
movl (%rbx,%rax,2), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
movl (%r12,%rbx), %esi
movq %r14, %rdi
callq 0x44631
andl $0x1fff, %ebp # imm = 0x1FFF
jmp 0xa47bb
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa5aaf(%rip), %rax # 0x149e80
movl (%rax,%rcx,2), %esi
movq (%rsp), %rbx
movq %rbx, %rdi
callq 0x44631
andl $0x3fffff, %ebp # imm = 0x3FFFFF
jmp 0xa4680
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa5b86(%rip), %rax # 0x149f80
movl (%rax,%rcx,2), %ebx
movq (%rsp), %r14
movq %r14, %rdi
movl %ebx, %esi
callq 0x44631
movq %r14, %rdi
movl %ebx, %esi
jmp 0xa4aa6
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5b5c(%rip), %r14 # 0x149f80
jmp 0xa49d2
leaq 0x7b2(%rip), %r9 # 0xa4be2
jmp 0xa4635
leaq 0x7ec(%rip), %r9 # 0xa4c28
jmp 0xa490a
shrl $0xc, %r12d
andl $0x7c, %r12d
leaq 0xa5a30(%rip), %rbx # 0x149e80
movl (%r12,%rbx), %esi
jmp 0xa4942
movl $0xcccccccc, %ebx # imm = 0xCCCCCCCC
movq 0x8(%rsp), %rax
shrl %eax
andl $0x1f, %eax
btl %eax, %ebx
jb 0xa3eb4
leaq 0xa5b88(%rip), %r14 # 0x14a000
movl (%r14,%rax,4), %esi
movq (%rsp), %r15
jmp 0xa4b1c
andl $0x3fffff, %ebp # imm = 0x3FFFFF
jmp 0xa44f9
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5ae4(%rip), %rbx # 0x149f80
jmp 0xa493f
shrl $0xc, %r12d
andl $0x7c, %r12d
leaq 0xa59d0(%rip), %rax # 0x149e80
movl (%r12,%rax), %esi
movq (%rsp), %rbx
movq %rbx, %rdi
callq 0x44631
andl $0x3fff, %ebp # imm = 0x3FFF
andl $0x30, %r15d
shll $0xa, %r15d
orl %ebp, %r15d
movq %rbx, %rdi
movq %r15, %rsi
jmp 0xa4b7d
shll $0x13, %ebp
sarl $0x13, %ebp
jmp 0xa4b76
leaq 0x75d(%rip), %r9 # 0xa4c4b
jmp 0xa490a
andl $0x7ffff, %ebp # imm = 0x7FFFF
movq (%rsp), %rbx
movq %rbx, %rdi
movq %rbp, %rsi
callq 0x4465e
movq 0x8(%rsp), %rsi
shrl %esi
andl $0xf, %esi
movq %rbx, %rdi
jmp 0xa4b7d
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa5a57(%rip), %rax # 0x149f80
movl (%rax,%rcx,2), %esi
movq (%rsp), %rbx
movq %rbx, %rdi
callq 0x44631
movq 0x10(%rsp), %rcx
andl $0x1f, %ecx
leaq 0xa59b9(%rip), %rax # 0x149f00
jmp 0xa4aa0
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5925(%rip), %r14 # 0x149e80
jmp 0xa49d2
andl $0x7ffff, %ebp # imm = 0x7FFFF
movq (%rsp), %rbx
movq %rbx, %rdi
movq %rbp, %rsi
callq 0x4465e
movq 0x8(%rsp), %rsi
shrl %esi
andl $0xf, %esi
movq %rbx, %rdi
callq 0x4465e
shrl $0x2, %r15d
andl $0xc, %r15d
leaq 0xa5aea(%rip), %rax # 0x14a080
movl (%r15,%rax), %esi
jmp 0xa4aa3
shll $0x2, %ebp
jmp 0xa4b76
movl $0xcccccccc, %r14d # imm = 0xCCCCCCCC
movq 0x8(%rsp), %rax
shrl %eax
andl $0x1f, %eax
btl %eax, %r14d
jb 0xa3eb4
leaq 0xa5a38(%rip), %r15 # 0x14a000
movl (%r15,%rax,4), %ebx
movq (%rsp), %r13
movq %r13, %rdi
movl %ebx, %esi
callq 0x44631
movq 0x10(%rsp), %rax
btl %eax, %r14d
jb 0xa3eb4
andl $0x1f, %eax
movl (%r15,%rax,4), %esi
movq %r13, %rdi
callq 0x44631
movq %r13, %rdi
movl %ebx, %esi
callq 0x44631
shrl $0xe, %r12d
andl $0xf, %r12d
movq %r13, %rdi
jmp 0xa4a29
movq (%rsp), %rdi
movl %ebp, %esi
callq 0xa4d5a
jmp 0xa4923
leaq 0x5dc(%rip), %r9 # 0xa4c05
jmp 0xa490a
leaq 0x5d0(%rip), %r9 # 0xa4c05
xorl %r15d, %r15d
movq (%rsp), %rdi
movl %ebp, %esi
movq %rbx, %rdx
movq 0x60(%rsp), %rcx
xorl %r8d, %r8d
callq 0xa4dc9
testl %eax, %eax
jne 0xa4b82
jmp 0xa4b8f
shrl $0xc, %r12d
andl $0x7c, %r12d
leaq 0xa5816(%rip), %rax # 0x149e80
movl (%r12,%rax), %esi
movq (%rsp), %rbx
movq %rbx, %rdi
callq 0x44631
shll $0x13, %ebp
sarl $0x13, %ebp
movq %rbx, %rdi
jmp 0xa4b7a
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa57e9(%rip), %rax # 0x149e80
movl (%rax,%rcx,2), %ebx
movq (%rsp), %r14
movq %r14, %rdi
movl %ebx, %esi
jmp 0xa481b
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa57c9(%rip), %rbx # 0x149e80
movl (%rbx,%rax,2), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
movl (%r12,%rbx), %esi
movq %r14, %rdi
callq 0x44631
shll $0x13, %ebp
sarl $0x13, %ebp
jmp 0xa47bb
movq 0x8(%rsp), %rcx
shrl %ecx
andl $0x1f, %ecx
movl $0xcccccccc, %eax # imm = 0xCCCCCCCC
btl %ecx, %eax
jb 0xa3eb4
leaq 0xa58fc(%rip), %rax # 0x14a000
jmp 0xa4760
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa586b(%rip), %rax # 0x149f80
movl (%rax,%rcx,2), %esi
movq (%rsp), %rbx
movq %rbx, %rdi
callq 0x44631
movl $0xcccccccc, %eax # imm = 0xCCCCCCCC
movq 0x10(%rsp), %rcx
btl %ecx, %eax
jb 0xa3eb4
andl $0x1f, %ecx
leaq 0xa58bf(%rip), %rax # 0x14a000
jmp 0xa4aa0
movq 0x8(%rsp), %rcx
shrl %ecx
andl $0x1f, %ecx
cmpl $0x3, %ecx
ja 0xa3eb4
leaq 0xa5920(%rip), %rax # 0x14a080
movl (%rax,%rcx,4), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
leaq 0xa5802(%rip), %rbx # 0x149f80
jmp 0xa4a57
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa56ee(%rip), %rbx # 0x149e80
movl (%rbx,%rax,2), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
movl (%r12,%rbx), %esi
movq %r14, %rdi
callq 0x44631
andl $0x3ff, %ebp # imm = 0x3FF
movq %r14, %rdi
jmp 0xa4b7a
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa57ae(%rip), %r14 # 0x149f80
movl (%r14,%rax,2), %ebx
movq (%rsp), %r15
movq %r15, %rdi
movl %ebx, %esi
jmp 0xa49fb
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa568d(%rip), %rax # 0x149e80
movl (%rax,%rcx,2), %ebx
movq (%rsp), %r14
movq %r14, %rdi
movl %ebx, %esi
callq 0x44631
movq 0x18(%rsp), %rcx
shrl %ecx
andl $0xc, %ecx
leaq 0xa586b(%rip), %rax # 0x14a080
movl (%rcx,%rax), %esi
movq %r14, %rdi
callq 0x44631
andl $0x7ff, %ebp # imm = 0x7FF
movq %r14, %rdi
movq %rbp, %rsi
callq 0x4465e
movq %r14, %rdi
movl %ebx, %esi
callq 0x44631
shrl $0xe, %r12d
andl $0xf, %r12d
movq %r14, %rdi
jmp 0xa4a29
shrl $0xc, %r12d
andl $0x7c, %r12d
leaq 0xa5626(%rip), %rbx # 0x149e80
movl (%r12,%rbx), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
movq 0x10(%rsp), %rax
andl $0x1f, %eax
movl (%rbx,%rax,4), %esi
movq %r14, %rdi
callq 0x44631
movq 0x8(%rsp), %rsi
shrl %esi
andl $0xf, %esi
movq %r14, %rdi
jmp 0xa4b7d
movl $0xcccccccc, %r15d # imm = 0xCCCCCCCC
movq 0x8(%rsp), %rax
shrl %eax
andl $0x1f, %eax
btl %eax, %r15d
jb 0xa3eb4
leaq 0xa5750(%rip), %r13 # 0x14a000
movl (%r13,%rax,4), %ebx
movq (%rsp), %r14
movq %r14, %rdi
movl %ebx, %esi
callq 0x44631
movq 0x18(%rsp), %rcx
shrl %ecx
andl $0xc, %ecx
leaq 0xa57ac(%rip), %rax # 0x14a080
movl (%rcx,%rax), %esi
movq %r14, %rdi
callq 0x44631
movq 0x10(%rsp), %rax
btl %eax, %r15d
jb 0xa3eb4
andl $0x1f, %eax
movl (%r13,%rax,4), %esi
movq %r14, %rdi
callq 0x44631
jmp 0xa4831
leaq 0x2d8(%rip), %r9 # 0xa4be2
movq (%rsp), %rdi
movl %ebp, %esi
movq %rbx, %rdx
movq 0x60(%rsp), %rcx
movl $0x1, %r8d
callq 0xa4dc9
testl %eax, %eax
jne 0xa4b82
jmp 0xa3eb4
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa55c1(%rip), %rbx # 0x149f00
movl (%rbx,%rax,2), %esi
movq (%rsp), %r14
jmp 0xa4a5b
movl $0xcccccccc, %ebx # imm = 0xCCCCCCCC
movq 0x8(%rsp), %rax
shrl %eax
andl $0x1f, %eax
btl %eax, %ebx
jb 0xa3eb4
leaq 0xa5696(%rip), %r14 # 0x14a000
movl (%r14,%rax,4), %esi
movq (%rsp), %r15
movq %r15, %rdi
callq 0x44631
shrl $0xe, %r12d
andl $0x1f, %r12d
btl %r12d, %ebx
jb 0xa3eb4
jmp 0xa4b18
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa55e0(%rip), %rax # 0x149f80
movl (%rax,%rcx,2), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
leaq 0xa5542(%rip), %rbx # 0x149f00
jmp 0xa4a57
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa552e(%rip), %r14 # 0x149f00
movl (%r14,%rax,2), %ebx
movq (%rsp), %r15
movq %r15, %rdi
movl %ebx, %esi
callq 0x44631
movq 0x18(%rsp), %rcx
shrl %ecx
andl $0xc, %ecx
leaq 0xa568b(%rip), %rax # 0x14a080
movl (%rcx,%rax), %esi
movq %r15, %rdi
callq 0x44631
movq 0x10(%rsp), %rax
andl $0x1f, %eax
movl (%r14,%rax,4), %esi
movq %r15, %rdi
callq 0x44631
movq %r15, %rdi
movl %ebx, %esi
callq 0x44631
shrl $0xe, %r12d
andl $0xf, %r12d
movq %r15, %rdi
movq %r12, %rsi
jmp 0xa4b7d
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa54c0(%rip), %rbx # 0x149f00
movl (%rbx,%rax,2), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
movl (%r12,%rbx), %esi
movq %r14, %rdi
callq 0x44631
movq 0x10(%rsp), %rax
andl $0x1f, %eax
movl (%rbx,%rax,4), %esi
movq %r14, %rdi
jmp 0xa4aa6
movq 0x8(%rsp), %rcx
andl $0x3e, %ecx
leaq 0xa54fe(%rip), %rax # 0x149f80
movl (%rax,%rcx,2), %esi
movq (%rsp), %rbx
movq %rbx, %rdi
callq 0x44631
movq 0x10(%rsp), %rcx
andl $0x1f, %ecx
leaq 0xa53e0(%rip), %rax # 0x149e80
movl (%rax,%rcx,4), %esi
movq %rbx, %rdi
callq 0x44631
jmp 0xa4b82
movq (%rsp), %rdi
movl %ebp, %esi
callq 0xa4c79
jmp 0xa4923
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5431(%rip), %rbx # 0x149f00
jmp 0xa4b50
movq 0x8(%rsp), %rcx
shrl %ecx
andl $0x1f, %ecx
cmpl $0x3, %ecx
ja 0xa3eb4
movl $0xcccccccc, %ebx # imm = 0xCCCCCCCC
leaq 0xa5590(%rip), %rax # 0x14a080
movl (%rax,%rcx,4), %esi
movq (%rsp), %r15
movq %r15, %rdi
callq 0x44631
shrl $0xe, %r12d
andl $0x1f, %r12d
btl %r12d, %ebx
jb 0xa3eb4
leaq 0xa54e8(%rip), %r14 # 0x14a000
movl (%r14,%r12,4), %esi
movq %r15, %rdi
callq 0x44631
movq 0x10(%rsp), %rax
btl %eax, %ebx
jb 0xa3eb4
andl $0x1f, %eax
movl (%r14,%rax,4), %esi
movq %r15, %rdi
jmp 0xa4aa6
movq 0x8(%rsp), %rax
andl $0x3e, %eax
leaq 0xa5430(%rip), %rbx # 0x149f80
movl (%rbx,%rax,2), %esi
movq (%rsp), %r14
movq %r14, %rdi
callq 0x44631
shrl $0xc, %r12d
andl $0x7c, %r12d
movl (%r12,%rbx), %esi
jmp 0xa4a6e
andl $0x3fffff, %ebp # imm = 0x3FFFFF
movq (%rsp), %rdi
movq %rbp, %rsi
callq 0x4465e
movq 0x20(%rsp), %rax
movw $0x4, (%rax)
movb $0x1, %r15b
movl %r15d, %eax
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/Sparc/SparcDisassembler.c
|
DecodeJMPL
|
static DecodeStatus DecodeJMPL(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder)
{
DecodeStatus status;
unsigned rd = fieldFromInstruction_4(insn, 25, 5);
unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
unsigned rs2 = 0;
unsigned simm13 = 0;
if (isImm)
simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
else
rs2 = fieldFromInstruction_4(insn, 0, 5);
// Decode RD.
status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode RS1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode RS1 | SIMM13.
if (isImm)
MCOperand_CreateImm0(MI, simm13);
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
}
return MCDisassembler_Success;
}
|
pushq %r15
pushq %r14
pushq %rbx
movl %esi, %r14d
movq %rdi, %rbx
movl %esi, %eax
shrl $0x17, %eax
andl $0x7c, %eax
leaq 0xa51ed(%rip), %r15 # 0x149e80
movl (%rax,%r15), %esi
callq 0x44631
movl %r14d, %eax
shrl $0xc, %eax
andl $0x7c, %eax
movl (%rax,%r15), %esi
movq %rbx, %rdi
callq 0x44631
btl $0xd, %r14d
jb 0xa4cca
andl $0x1f, %r14d
movl (%r15,%r14,4), %esi
movq %rbx, %rdi
callq 0x44631
jmp 0xa4cdd
shll $0x13, %r14d
sarl $0x13, %r14d
movq %rbx, %rdi
movq %r14, %rsi
callq 0x4465e
movl $0x3, %eax
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/Sparc/SparcDisassembler.c
|
DecodeReturn
|
static DecodeStatus DecodeReturn(MCInst *MI, unsigned insn, uint64_t Address,
const void *Decoder)
{
DecodeStatus status;
unsigned rs1 = fieldFromInstruction_4(insn, 14, 5);
unsigned isImm = fieldFromInstruction_4(insn, 13, 1);
unsigned rs2 = 0;
unsigned simm13 = 0;
if (isImm)
simm13 = SignExtend32(fieldFromInstruction_4(insn, 0, 13), 13);
else
rs2 = fieldFromInstruction_4(insn, 0, 5);
// Decode RS1.
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode RS2 | SIMM13.
if (isImm)
MCOperand_CreateImm0(MI, simm13);
else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
}
return MCDisassembler_Success;
}
|
pushq %r15
pushq %r14
pushq %rbx
movl %esi, %r14d
movq %rdi, %rbx
movl %esi, %eax
shrl $0xe, %eax
andl $0x1f, %eax
btl $0xd, %esi
jb 0xa4d28
andl $0x1f, %r14d
movl %eax, %eax
leaq 0xa5172(%rip), %r15 # 0x149e80
movl (%r15,%rax,4), %esi
movq %rbx, %rdi
callq 0x44631
movl (%r15,%r14,4), %esi
movq %rbx, %rdi
callq 0x44631
jmp 0xa4d4f
shll $0x13, %r14d
sarl $0x13, %r14d
movl %eax, %eax
leaq 0xa5147(%rip), %rcx # 0x149e80
movl (%rcx,%rax,4), %esi
movq %rbx, %rdi
callq 0x44631
movq %rbx, %rdi
movq %r14, %rsi
callq 0x4465e
movl $0x3, %eax
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/Sparc/SparcDisassembler.c
|
printOperand
|
static void printOperand(MCInst *MI, int opNum, SStream *O)
{
int Imm;
unsigned reg;
MCOperand *MO = MCInst_getOperand(MI, opNum);
if (MCOperand_isReg(MO)) {
reg = MCOperand_getReg(MO);
printRegName(O, reg);
reg = Sparc_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = reg;
else
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = reg;
} else {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
MI->flat_insn->detail->sparc.op_count++;
}
}
return;
}
if (MCOperand_isImm(MO)) {
Imm = (int)MCOperand_getImm(MO);
// Conditional branches displacements needs to be signextended to be
// able to jump backwards.
//
// Displacements are measured as the number of instructions forward or
// backward, so they need to be multiplied by 4
switch (MI->Opcode) {
case SP_CALL:
Imm = SignExtend32(Imm, 30);
Imm += (uint32_t)MI->address;
break;
// Branch on integer condition with prediction (BPcc)
// Branch on floating point condition with prediction (FBPfcc)
case SP_BPICC:
case SP_BPICCA:
case SP_BPICCANT:
case SP_BPICCNT:
case SP_BPXCC:
case SP_BPXCCA:
case SP_BPXCCANT:
case SP_BPXCCNT:
case SP_BPFCC:
case SP_BPFCCA:
case SP_BPFCCANT:
case SP_BPFCCNT:
Imm = SignExtend32(Imm, 19);
Imm = (uint32_t)MI->address + Imm * 4;
break;
// Branch on integer condition (Bicc)
// Branch on floating point condition (FBfcc)
case SP_BA:
case SP_BCOND:
case SP_BCONDA:
case SP_FBCOND:
case SP_FBCONDA:
Imm = SignExtend32(Imm, 22);
Imm = (uint32_t)MI->address + Imm * 4;
break;
// Branch on integer register with prediction (BPr)
case SP_BPGEZapn:
case SP_BPGEZapt:
case SP_BPGEZnapn:
case SP_BPGEZnapt:
case SP_BPGZapn:
case SP_BPGZapt:
case SP_BPGZnapn:
case SP_BPGZnapt:
case SP_BPLEZapn:
case SP_BPLEZapt:
case SP_BPLEZnapn:
case SP_BPLEZnapt:
case SP_BPLZapn:
case SP_BPLZapt:
case SP_BPLZnapn:
case SP_BPLZnapt:
case SP_BPNZapn:
case SP_BPNZapt:
case SP_BPNZnapn:
case SP_BPNZnapt:
case SP_BPZapn:
case SP_BPZapt:
case SP_BPZnapn:
case SP_BPZnapt:
Imm = SignExtend32(Imm, 16);
Imm = (uint32_t)MI->address + Imm * 4;
break;
}
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
SStream_concat(O, "%u", Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -Imm);
else
SStream_concat(O, "-%u", -Imm);
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
} else {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
MI->flat_insn->detail->sparc.op_count++;
}
}
}
return;
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r14
movq %rdi, %rbx
callq 0x445a8
movq %rax, %r15
movq %rax, %rdi
callq 0x445e6
testb %al, %al
je 0xbb3d4
movq %r15, %rdi
callq 0x445fe
movl %eax, %r15d
leaq 0x912ad(%rip), %rsi # 0x14c60b
movq %r14, %rdi
callq 0x44686
leal -0x1(%r15), %eax
leaq 0x8f01f(%rip), %rcx # 0x14a390
movl (%rcx,%rax,4), %eax
leaq 0x1b5e45(%rip), %rsi # 0x2711c0
addq %rax, %rsi
movq %r14, %rdi
callq 0x44686
movl %r15d, %edi
callq 0xbb910
movq 0x320(%rbx), %rdx
cmpl $0x0, 0x68(%rdx)
je 0xbb511
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x38(%rcx), %esi
addq $0x3c, %rcx
cmpb $0x1, 0x70(%rdx)
jne 0xbb414
leaq (%rsi,%rsi,2), %rdx
leaq (%rcx,%rdx,4), %rcx
addq $0x4, %rcx
cmpb $0x0, (%rcx)
je 0xbb448
movb %al, 0x1(%rcx)
jmp 0xbb511
movq %r15, %rdi
callq 0x445ee
testb %al, %al
je 0xbb511
movq %r15, %rdi
callq 0x44606
movq %rax, %r15
movl 0x8(%rbx), %eax
addl $-0x47, %eax
cmpl $0x4f, %eax
ja 0xbb45e
leaq 0x8ee43(%rip), %rcx # 0x14a244
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movswl %r15w, %r15d
shll $0x2, %r15d
jmp 0xbb457
leaq (%rsi,%rsi,2), %rdx
movl $0x1, (%rcx,%rdx,4)
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x38(%rcx), %edx
leaq (%rdx,%rdx,2), %rdx
movl %eax, 0x40(%rcx,%rdx,4)
jmp 0xbb500
shll $0xd, %r15d
sarl $0xb, %r15d
jmp 0xbb457
movb %al, (%rcx)
jmp 0xbb511
shll $0xa, %r15d
sarl $0x8, %r15d
addl 0x318(%rbx), %r15d
testl %r15d, %r15d
js 0xbb472
cmpl $0xa, %r15d
jb 0xbb486
leaq 0x2bdf5(%rip), %rsi # 0xe7265
jmp 0xbb48d
movl %r15d, %edx
negl %edx
cmpl $-0xa, %r15d
ja 0xbb495
leaq 0x19ca3(%rip), %rsi # 0xd5127
jmp 0xbb49c
leaq 0x10c49(%rip), %rsi # 0xcc0d6
movq %r14, %rdi
movl %r15d, %edx
jmp 0xbb49f
leaq 0x19c94(%rip), %rsi # 0xd5130
movq %r14, %rdi
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rcx
cmpl $0x0, 0x68(%rcx)
je 0xbb511
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x38(%rax), %edx
addq $0x3c, %rax
cmpb $0x1, 0x70(%rcx)
jne 0xbb4da
leaq (%rdx,%rdx,2), %rcx
movl %r15d, 0x8(%rax,%rcx,4)
jmp 0xbb511
leaq (%rdx,%rdx,2), %rcx
movl $0x2, (%rax,%rcx,4)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x38(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
movl %r15d, 0x40(%rax,%rcx,4)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x38(%rax)
popq %rbx
popq %r14
popq %r15
retq
shll $0x2, %r15d
sarl $0x2, %r15d
jmp 0xbb457
|
/sidneyp[P]capstone-tricore/arch/Sparc/SparcInstPrinter.c
|
set_mem_access
|
static void set_mem_access(MCInst *MI, bool status)
{
if (MI->csh->detail != CS_OPT_ON)
return;
MI->csh->doing_mem = status;
if (status) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_MEM;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = SPARC_REG_INVALID;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = 0;
} else {
// done, create the next operand slot
MI->flat_insn->detail->sparc.op_count++;
}
}
|
movq 0x320(%rdi), %rax
cmpl $0x3, 0x68(%rax)
jne 0xbb673
movb %sil, 0x70(%rax)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
testb %sil, %sil
je 0xbb670
movzbl 0x38(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
movl $0x3, 0x3c(%rax,%rcx,4)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
movzbl 0x38(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
movb $0x0, 0x40(%rax,%rcx,4)
movq 0x310(%rdi), %rax
movq 0xe8(%rax), %rax
movzbl 0x38(%rax), %ecx
leaq (%rcx,%rcx,2), %rcx
movl $0x0, 0x44(%rax,%rcx,4)
retq
incb 0x38(%rax)
retq
|
/sidneyp[P]capstone-tricore/arch/Sparc/SparcInstPrinter.c
|
Sparc_get_insn_id
|
void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
unsigned short i;
i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
insn->detail->groups_count = (uint8_t)count_positive(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
insn->detail->groups[insn->detail->groups_count] = SPARC_GRP_JUMP;
insn->detail->groups_count++;
}
#endif
// hint code
for (i = 0; i < ARR_SIZE(insn_hints); i++) {
if (id == insn_hints[i].id) {
insn->detail->sparc.hint = insn_hints[i].hints;
break;
}
}
}
}
}
|
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r12
leaq 0x78(%rdi), %rcx
leaq 0x1b78ce(%rip), %r15 # 0x2730a0
movq %r15, %rdi
movl $0x1b9, %esi # imm = 0x1B9
callq 0x47614
testw %ax, %ax
je 0xbb8ae
movzwl %ax, %eax
imulq $0x2e, %rax, %rax
movzwl 0x2(%rax,%r15), %ecx
movl %ecx, (%r14)
cmpl $0x0, 0x68(%r12)
je 0xbb8ae
addq %rax, %r15
movq 0xe8(%r14), %rax
leaq 0x4(%r15), %rdi
movl 0xc(%r15), %ecx
movl %ecx, 0x8(%rax)
movq 0x4(%r15), %rcx
movq %rcx, (%rax)
callq 0x476de
movq 0xe8(%r14), %rcx
movb %al, 0xc(%rcx)
leaq 0x10(%r15), %rdi
movl 0x20(%r15), %eax
movl %eax, 0x1d(%rcx)
movups 0x10(%r15), %xmm0
movups %xmm0, 0xd(%rcx)
callq 0x476de
movq 0xe8(%r14), %rcx
movb %al, 0x21(%rcx)
leaq 0x24(%r15), %rdi
movq 0x24(%r15), %rax
movq %rax, 0x22(%rcx)
callq 0x476de
movq 0xe8(%r14), %rcx
movb %al, 0x2a(%rcx)
cmpb $0x0, 0x2c(%r15)
jne 0xbb87b
cmpb $0x1, 0x2d(%r15)
jne 0xbb88d
movzbl %al, %eax
movb $0x1, 0x22(%rcx,%rax)
movq 0xe8(%r14), %rcx
incb 0x2a(%rcx)
xorl %eax, %eax
leaq 0x90e0a(%rip), %rdx # 0x14c6a0
cmpl %ebx, (%rdx,%rax,8)
je 0xbb8a6
incq %rax
cmpq $0x12, %rax
jne 0xbb896
jmp 0xbb8ae
movzbl 0x4(%rdx,%rax,8), %eax
movl %eax, 0x34(%rcx)
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/Sparc/SparcMapping.c
|
Sparc_group_name
|
const char *Sparc_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
// verify group id
if (id >= SPARC_GRP_ENDING || (id > SPARC_GRP_JUMP && id < SPARC_GRP_HARDQUAD))
return NULL;
// NOTE: when new generic groups are added, 2 must be changed accordingly
if (id >= 128)
return group_name_maps[id - 128 + 2].name;
else
return group_name_maps[id].name;
#else
return NULL;
#endif
}
|
cmpl $0x87, %esi
setae %al
leal -0x2(%rsi), %ecx
cmpl $0x7e, %ecx
setb %cl
orb %al, %cl
je 0xbb8f6
xorl %eax, %eax
retq
leal -0x7e(%rsi), %eax
cmpl $0x7f, %esi
cmovbel %esi, %eax
shlq $0x4, %rax
leaq 0xd3016(%rip), %rcx # 0x18e920
movq 0x8(%rax,%rcx), %rax
retq
|
/sidneyp[P]capstone-tricore/arch/Sparc/SparcMapping.c
|
decodeBDLAddr64Disp12Len8Operand
|
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst *Inst, uint64_t Field,
uint64_t Address, const void *Decoder)
{
return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC_GR64Regs);
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
movl %ebx, %eax
shrl $0xc, %eax
andl $0xf, %eax
je 0xbd528
leaq 0x91e3d(%rip), %rcx # 0x14f360
movl (%rcx,%rax,4), %esi
jmp 0xbd52a
xorl %esi, %esi
movl %ebx, %r15d
andl $0xfff, %r15d # imm = 0xFFF
shrq $0x10, %rbx
movq %r14, %rdi
callq 0x44631
movq %r14, %rdi
movq %r15, %rsi
callq 0x4465e
incq %rbx
movq %r14, %rdi
movq %rbx, %rsi
popq %rbx
popq %r14
popq %r15
jmp 0x4465e
|
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZDisassembler.c
|
printCond4Operand
|
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
{
static char *const CondNames[] = {
"o", "h", "nle", "l", "nhe", "lh", "ne",
"e", "nlh", "he", "nl", "le", "nh", "no"
};
uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// assert(Imm > 0 && Imm < 15 && "Invalid condition");
SStream_concat0(O, CondNames[Imm - 1]);
if (MI->csh->detail)
MI->flat_insn->detail->sysz.cc = (sysz_cc)Imm;
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r15
movq %rdi, %rbx
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movq %rax, %r14
leaq 0x902ce(%rip), %rax # 0x14e434
movslq -0x4(%rax,%r14,4), %rsi
addq %rax, %rsi
movq %r15, %rdi
callq 0x44686
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xbe195
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movl %r14d, 0x30(%rax)
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZInstPrinter.c
|
printU6ImmOperand
|
static void printU6ImmOperand(MCInst *MI, int OpNum, SStream *O)
{
uint32_t Value = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// assert(isUInt<6>(Value) && "Invalid u6imm argument");
if (Value > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Value);
else
SStream_concat(O, "%u", Value);
if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = (int64_t)Value;
MI->flat_insn->detail->sysz.op_count++;
}
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r15
movq %rdi, %rbx
movl $0x5, %esi
callq 0x445a8
movq %rax, %rdi
callq 0x44606
movq %rax, %r14
cmpl $0xa, %r14d
leaq 0x28b88(%rip), %rax # 0xe7265
leaq 0xd9f2(%rip), %rsi # 0xcc0d6
cmovaeq %rax, %rsi
movq %r15, %rdi
movl %r14d, %edx
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xbe74d
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x34(%rax), %ecx
shll $0x5, %ecx
movl $0x2, 0x38(%rax,%rcx)
movl %r14d, %eax
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x34(%rcx), %edx
shll $0x5, %edx
movq %rax, 0x40(%rcx,%rdx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x34(%rax)
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZInstPrinter.c
|
SystemZ_reg_name
|
const char *SystemZ_reg_name(csh handle, unsigned int reg)
{
#ifndef CAPSTONE_DIET
if (reg >= SYSZ_REG_ENDING)
return NULL;
return reg_name_maps[reg].name;
#else
return NULL;
#endif
}
|
cmpl $0x22, %esi
jbe 0xbe930
xorl %eax, %eax
retq
movl %esi, %eax
shlq $0x4, %rax
leaq 0xd00a3(%rip), %rcx # 0x18e9e0
movq 0x8(%rax,%rcx), %rax
retq
|
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZMapping.c
|
SystemZ_insn_name
|
const char *SystemZ_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
unsigned int i;
if (id >= SYSZ_INS_ENDING)
return NULL;
// handle special alias first
for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
if (alias_insn_names[i].id == id)
return alias_insn_names[i].name;
}
return insn_name_maps[id].name;
#else
return NULL;
#endif
}
|
leal -0x2aa(%rsi), %eax
cmpl $0xfffffd57, %eax # imm = 0xFFFFFD57
jae 0xbea28
xorl %eax, %eax
retq
movl %esi, %eax
shlq $0x4, %rax
leaq 0xd01db(%rip), %rcx # 0x18ec10
movq 0x8(%rax,%rcx), %rax
retq
|
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZMapping.c
|
SystemZ_map_register
|
sysz_reg SystemZ_map_register(unsigned int r)
{
static unsigned int map[] = { 0,
SYSZ_REG_CC, SYSZ_REG_F0, SYSZ_REG_F1, SYSZ_REG_F2, SYSZ_REG_F3,
SYSZ_REG_F4, SYSZ_REG_F5, SYSZ_REG_F6, SYSZ_REG_F7, SYSZ_REG_F8,
SYSZ_REG_F9, SYSZ_REG_F10, SYSZ_REG_F11, SYSZ_REG_F12, SYSZ_REG_F13,
SYSZ_REG_F14, SYSZ_REG_F15, SYSZ_REG_F0, SYSZ_REG_F1, SYSZ_REG_F4,
SYSZ_REG_F5, SYSZ_REG_F8, SYSZ_REG_F9, SYSZ_REG_F12, SYSZ_REG_F13,
SYSZ_REG_F0, SYSZ_REG_F1, SYSZ_REG_F2, SYSZ_REG_F3, SYSZ_REG_F4,
SYSZ_REG_F5, SYSZ_REG_F6, SYSZ_REG_F7, SYSZ_REG_F8, SYSZ_REG_F9,
SYSZ_REG_F10, SYSZ_REG_F11, SYSZ_REG_F12, SYSZ_REG_F13, SYSZ_REG_F14,
SYSZ_REG_F15, SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2, SYSZ_REG_3,
SYSZ_REG_4, SYSZ_REG_5, SYSZ_REG_6, SYSZ_REG_7, SYSZ_REG_8,
SYSZ_REG_9, SYSZ_REG_10, SYSZ_REG_11, SYSZ_REG_12, SYSZ_REG_13,
SYSZ_REG_14, SYSZ_REG_15, SYSZ_REG_0, SYSZ_REG_1, SYSZ_REG_2,
SYSZ_REG_3, SYSZ_REG_4, SYSZ_REG_5, SYSZ_REG_6, SYSZ_REG_7,
SYSZ_REG_8, SYSZ_REG_9, SYSZ_REG_10, SYSZ_REG_11, SYSZ_REG_12,
SYSZ_REG_13, SYSZ_REG_14, SYSZ_REG_15, SYSZ_REG_0, SYSZ_REG_1,
SYSZ_REG_2, SYSZ_REG_3, SYSZ_REG_4, SYSZ_REG_5, SYSZ_REG_6,
SYSZ_REG_7, SYSZ_REG_8, SYSZ_REG_9, SYSZ_REG_10, SYSZ_REG_11,
SYSZ_REG_12, SYSZ_REG_13, SYSZ_REG_14, SYSZ_REG_15, SYSZ_REG_0,
SYSZ_REG_2, SYSZ_REG_4, SYSZ_REG_6, SYSZ_REG_8, SYSZ_REG_10,
SYSZ_REG_12, SYSZ_REG_14,
};
if (r < ARR_SIZE(map))
return map[r];
// cannot find this register
return 0;
}
|
xorl %eax, %eax
cmpl $0x61, %edi
ja 0xbea81
movl %edi, %eax
leaq 0x8fa22(%rip), %rcx # 0x14e4a0
movl (%rcx,%rax,4), %eax
retq
nop
|
/sidneyp[P]capstone-tricore/arch/SystemZ/SystemZMapping.c
|
DecodeGRRegsRegisterClass
|
static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address, void *Decoder)
{
unsigned Reg;
if (RegNo > 11)
return MCDisassembler_Fail;
Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo);
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
|
xorl %eax, %eax
cmpl $0xb, %esi
ja 0xbf5d0
pushq %rbp
pushq %rbx
pushq %rax
movl %esi, %ebp
movq %rdi, %rbx
movq %rdx, %rdi
movl $0x1, %esi
callq 0x475fa
movq 0x8(%rax), %rax
movl %ebp, %ecx
movzwl (%rax,%rcx,2), %esi
movq %rbx, %rdi
callq 0x44631
movl $0x3, %eax
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
Decode2RUSInstruction
|
static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
if (S == MCDisassembler_Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
MCOperand_CreateImm0(Inst, Op3);
}
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %r14
movl %esi, %eax
movq %rdi, %rbx
leaq 0xc(%rsp), %rsi
leaq 0x8(%rsp), %rdx
leaq 0x4(%rsp), %rcx
movl %eax, %edi
callq 0xc0175
movl %eax, %ebp
cmpl $0x3, %eax
jne 0xbf68f
movl 0xc(%rsp), %esi
movq %rbx, %rdi
movq %r14, %rdx
callq 0xbf597
movl 0x8(%rsp), %esi
movq %rbx, %rdi
movq %r14, %rdx
callq 0xbf597
movl 0x4(%rsp), %esi
movq %rbx, %rdi
callq 0x4465e
movl %ebp, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
DecodeR2RInstruction
|
static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1);
if (S != MCDisassembler_Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
leaq 0x8(%rsp), %rsi
leaq 0xc(%rsp), %rdx
movl %ebp, %edi
callq 0xbffb9
cmpl $0x3, %eax
jne 0xbf6ec
movl 0xc(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x8(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl $0x3, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
jmp 0xc000e
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
Decode2RImmInstruction
|
static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
if (S != MCDisassembler_Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
MCOperand_CreateImm0(Inst, Op1);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
leaq 0xc(%rsp), %rsi
leaq 0x8(%rsp), %rdx
movl %ebp, %edi
callq 0xbffb9
cmpl $0x3, %eax
jne 0xbf7b5
movl 0xc(%rsp), %esi
movq %r14, %rdi
callq 0x4465e
movl 0x8(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl $0x3, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
jmp 0xc000e
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
Decode2RSrcDstInstruction
|
static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
if (S != MCDisassembler_Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
leaq 0xc(%rsp), %rsi
leaq 0x8(%rsp), %rdx
movl %ebp, %edi
callq 0xbffb9
cmpl $0x3, %eax
jne 0xbf82b
movl 0xc(%rsp), %ebp
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
callq 0xbf597
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
callq 0xbf597
movl 0x8(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl $0x3, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
jmp 0xc000e
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
DecodeRUSSrcDstBitpInstruction
|
static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
if (S != MCDisassembler_Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
leaq 0xc(%rsp), %rsi
leaq 0x8(%rsp), %rdx
movl %ebp, %edi
callq 0xbffb9
cmpl $0x3, %eax
jne 0xbf8ae
movl 0xc(%rsp), %ebp
movq %rbx, %rdi
movl %ebp, %esi
movq %r14, %rdx
callq 0xbf597
movq %rbx, %rdi
movl %ebp, %esi
movq %r14, %rdx
callq 0xbf597
movl 0x8(%rsp), %eax
cmpq $0xb, %rax
ja 0xbf8a0
leaq 0x8fdcb(%rip), %rcx # 0x14f660
movl (%rcx,%rax,4), %esi
movq %rbx, %rdi
callq 0x4465e
movl $0x3, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
movq %rbx, %rdi
movl %ebp, %esi
movq %r14, %rdx
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
jmp 0xc000e
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
DecodeRUSBitpInstruction
|
static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
if (S != MCDisassembler_Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
leaq 0xc(%rsp), %rsi
leaq 0x8(%rsp), %rdx
movl %ebp, %edi
callq 0xbffb9
cmpl $0x3, %eax
jne 0xbf9bd
movl 0xc(%rsp), %esi
movq %rbx, %rdi
movq %r14, %rdx
callq 0xbf597
movl 0x8(%rsp), %eax
cmpq $0xb, %rax
ja 0xbf9af
leaq 0x8fcbc(%rip), %rcx # 0x14f660
movl (%rcx,%rax,4), %esi
movq %rbx, %rdi
callq 0x4465e
movl $0x3, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
movq %rbx, %rdi
movl %ebp, %esi
movq %r14, %rdx
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
jmp 0xc000e
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
Decode2RUSBitpInstruction
|
static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
if (S == MCDisassembler_Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeBitpOperand(Inst, Op3, Address, Decoder);
}
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %r14
movl %esi, %eax
movq %rdi, %rbx
leaq 0xc(%rsp), %rsi
leaq 0x8(%rsp), %rdx
leaq 0x4(%rsp), %rcx
movl %eax, %edi
callq 0xc0175
movl %eax, %ebp
cmpl $0x3, %eax
jne 0xbfa39
movl 0xc(%rsp), %esi
movq %rbx, %rdi
movq %r14, %rdx
callq 0xbf597
movl 0x8(%rsp), %esi
movq %rbx, %rdi
movq %r14, %rdx
callq 0xbf597
movl 0x4(%rsp), %eax
cmpq $0xb, %rax
ja 0xbfa39
leaq 0x8fc32(%rip), %rcx # 0x14f660
movl (%rcx,%rax,4), %esi
movq %rbx, %rdi
callq 0x4465e
movl %ebp, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
Decode3RImmInstruction
|
static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
if (S == MCDisassembler_Success) {
MCOperand_CreateImm0(Inst, Op1);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movl %esi, %eax
movq %rdi, %r14
leaq 0xc(%rsp), %rsi
leaq 0x8(%rsp), %rdx
leaq 0x4(%rsp), %rcx
movl %eax, %edi
callq 0xc0175
movl %eax, %ebp
cmpl $0x3, %eax
jne 0xbfa9b
movl 0xc(%rsp), %esi
movq %r14, %rdi
callq 0x4465e
movl 0x8(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x4(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl %ebp, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
DecodeL4RSrcDstInstruction
|
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2, Op3;
unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
if (S == MCDisassembler_Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
}
if (S == MCDisassembler_Success) {
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
movzwl %bp, %edi
leaq 0xc(%rsp), %rsi
leaq 0x8(%rsp), %rdx
leaq 0x4(%rsp), %rcx
callq 0xc0175
cmpl $0x3, %eax
jne 0xbfbf5
shrl $0x10, %ebp
andl $0xf, %ebp
movl 0xc(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
callq 0xbf597
cmpl $0x3, %eax
jne 0xbfbf5
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
callq 0xbf597
movl 0x8(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x4(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl $0x3, %eax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
DecodeL5RInstruction
|
static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2, Op3, Op4, Op5;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
if (S != MCDisassembler_Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5);
if (S != MCDisassembler_Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
movzwl %bp, %edi
leaq 0x1c(%rsp), %rsi
leaq 0x18(%rsp), %rdx
leaq 0x14(%rsp), %rcx
callq 0xc0175
cmpl $0x3, %eax
jne 0xbfd3e
movl %ebp, %edi
shrl $0x10, %edi
leaq 0x10(%rsp), %rsi
leaq 0xc(%rsp), %rdx
callq 0xbffb9
cmpl $0x3, %eax
jne 0xbfd3e
movl 0x1c(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x10(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x18(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x14(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0xc(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl $0x3, %eax
addq $0x20, %rsp
popq %rbx
popq %r14
popq %rbp
retq
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
addq $0x20, %rsp
popq %rbx
popq %r14
popq %rbp
jmp 0xc044e
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
DecodeL6RInstruction
|
static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Op1, Op2, Op3, Op4, Op5, Op6;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
if (S != MCDisassembler_Success)
return S;
S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6);
if (S != MCDisassembler_Success)
return S;
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
return S;
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
movzwl %bp, %edi
leaq 0x1c(%rsp), %rsi
leaq 0x18(%rsp), %rdx
leaq 0x14(%rsp), %rcx
callq 0xc0175
cmpl $0x3, %eax
jne 0xbfdfc
shrl $0x10, %ebp
leaq 0x10(%rsp), %rsi
leaq 0xc(%rsp), %rdx
leaq 0x8(%rsp), %rcx
movl %ebp, %edi
callq 0xc0175
cmpl $0x3, %eax
jne 0xbfdfc
movl 0x1c(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x10(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x18(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x14(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0xc(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl 0x8(%rsp), %esi
movq %r14, %rdi
movq %rbx, %rdx
callq 0xbf597
movl $0x3, %eax
addq $0x20, %rsp
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
Decode2OpInstructionFail
|
static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
// Try and decode as a 3R instruction.
unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
switch (Opcode) {
case 0x0:
MCInst_setOpcode(Inst, XCore_STW_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x1:
MCInst_setOpcode(Inst, XCore_LDW_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x2:
MCInst_setOpcode(Inst, XCore_ADD_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x3:
MCInst_setOpcode(Inst, XCore_SUB_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x4:
MCInst_setOpcode(Inst, XCore_SHL_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x5:
MCInst_setOpcode(Inst, XCore_SHR_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x6:
MCInst_setOpcode(Inst, XCore_EQ_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x7:
MCInst_setOpcode(Inst, XCore_AND_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x8:
MCInst_setOpcode(Inst, XCore_OR_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x9:
MCInst_setOpcode(Inst, XCore_LDW_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x10:
MCInst_setOpcode(Inst, XCore_LD16S_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x11:
MCInst_setOpcode(Inst, XCore_LD8U_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x12:
MCInst_setOpcode(Inst, XCore_ADD_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x13:
MCInst_setOpcode(Inst, XCore_SUB_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x14:
MCInst_setOpcode(Inst, XCore_SHL_2rus);
return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x15:
MCInst_setOpcode(Inst, XCore_SHR_2rus);
return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x16:
MCInst_setOpcode(Inst, XCore_EQ_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x17:
MCInst_setOpcode(Inst, XCore_TSETR_3r);
return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
case 0x18:
MCInst_setOpcode(Inst, XCore_LSS_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x19:
MCInst_setOpcode(Inst, XCore_LSU_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler_Fail;
}
|
pushq %rbp
pushq %r14
pushq %rbx
movl %esi, %eax
shrl $0xb, %eax
andl $0x1f, %eax
cmpl $0x19, %eax
ja 0xc00ad
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
leaq 0x8f5be(%rip), %rcx # 0x14f5f0
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq %r14, %rdi
movl $0xe4, %esi
jmp 0xc015f
movq %r14, %rdi
movl $0xa4, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0xe6, %esi
jmp 0xc015f
movq %r14, %rdi
movl $0x7d, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0x14, %esi
jmp 0xc015f
movq %r14, %rdi
movl $0xa6, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0x15, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0xd7, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0x7e, %esi
jmp 0xc0123
xorl %eax, %eax
popq %rbx
popq %r14
popq %rbp
retq
movq %r14, %rdi
movl $0xa1, %esi
jmp 0xc015f
movq %r14, %rdi
movl $0x54, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0x19, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0xd4, %esi
jmp 0xc00e7
movq %r14, %rdi
movl $0xd6, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbf9d2
movq %r14, %rdi
movl $0xe7, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0xd5, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0xa2, %esi
jmp 0xc0123
movq %r14, %rdi
movl $0xb0, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbf701
movq %r14, %rdi
movl $0xed, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbfa44
movq %r14, %rdi
movl $0x53, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbf638
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
DecodeL2OpInstructionFail
|
static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
// Try and decode as a L3R / L2RUS instruction.
unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
fieldFromInstruction_4(Insn, 27, 5) << 4;
switch (Opcode) {
case 0x0c:
MCInst_setOpcode(Inst, XCore_STW_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x1c:
MCInst_setOpcode(Inst, XCore_XOR_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x2c:
MCInst_setOpcode(Inst, XCore_ASHR_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x3c:
MCInst_setOpcode(Inst, XCore_LDAWF_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x4c:
MCInst_setOpcode(Inst, XCore_LDAWB_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x5c:
MCInst_setOpcode(Inst, XCore_LDA16F_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x6c:
MCInst_setOpcode(Inst, XCore_LDA16B_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x7c:
MCInst_setOpcode(Inst, XCore_MUL_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x8c:
MCInst_setOpcode(Inst, XCore_DIVS_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x9c:
MCInst_setOpcode(Inst, XCore_DIVU_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x10c:
MCInst_setOpcode(Inst, XCore_ST16_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x11c:
MCInst_setOpcode(Inst, XCore_ST8_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x12c:
MCInst_setOpcode(Inst, XCore_ASHR_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x12d:
MCInst_setOpcode(Inst, XCore_OUTPW_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x12e:
MCInst_setOpcode(Inst, XCore_INPW_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x13c:
MCInst_setOpcode(Inst, XCore_LDAWF_l2rus);
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x14c:
MCInst_setOpcode(Inst, XCore_LDAWB_l2rus);
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x15c:
MCInst_setOpcode(Inst, XCore_CRC_l3r);
return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
case 0x18c:
MCInst_setOpcode(Inst, XCore_REMS_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x19c:
MCInst_setOpcode(Inst, XCore_REMU_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler_Fail;
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
movl %esi, %ecx
shrl $0x10, %ecx
andl $0xf, %ecx
movl %esi, %eax
shrl $0x17, %eax
andl $-0x10, %eax
orl %ecx, %eax
cmpl $0x10b, %eax # imm = 0x10B
jg 0xc024a
cmpl $0x5b, %eax
jg 0xc028a
cmpl $0x2b, %eax
jle 0xc02f8
cmpl $0x2c, %eax
je 0xc03a7
cmpl $0x3c, %eax
je 0xc037c
cmpl $0x4c, %eax
jne 0xc0447
movq %r14, %rdi
movl $0x87, %esi
jmp 0xc0413
cmpl $0x13b, %eax # imm = 0x13B
jg 0xc02bf
cmpl $0x12b, %eax # imm = 0x12B
jle 0xc0317
cmpl $0x12c, %eax # imm = 0x12C
je 0xc03b1
cmpl $0x12d, %eax # imm = 0x12D
je 0xc0389
cmpl $0x12e, %eax # imm = 0x12E
jne 0xc0447
movq %r14, %rdi
movl $0x6f, %esi
jmp 0xc03b9
cmpl $0x7b, %eax
jle 0xc033a
cmpl $0x7c, %eax
je 0xc03cf
cmpl $0x8c, %eax
je 0xc0393
cmpl $0x9c, %eax
jne 0xc0447
movq %r14, %rdi
movl $0x46, %esi
jmp 0xc0413
cmpl $0x15b, %eax # imm = 0x15B
jle 0xc0359
cmpl $0x15c, %eax # imm = 0x15C
je 0xc03d9
cmpl $0x18c, %eax # imm = 0x18C
je 0xc039d
cmpl $0x19c, %eax # imm = 0x19C
jne 0xc0447
movq %r14, %rdi
movl $0xb9, %esi
jmp 0xc0413
cmpl $0xc, %eax
je 0xc03f7
cmpl $0x1c, %eax
jne 0xc0447
movq %r14, %rdi
movl $0xf2, %esi
jmp 0xc0413
cmpl $0x10c, %eax # imm = 0x10C
je 0xc0401
cmpl $0x11c, %eax # imm = 0x11C
jne 0xc0447
movq %r14, %rdi
movl $0xda, %esi
jmp 0xc0413
cmpl $0x5c, %eax
je 0xc040b
cmpl $0x6c, %eax
jne 0xc0447
movq %r14, %rdi
movl $0x7f, %esi
jmp 0xc0413
cmpl $0x13c, %eax # imm = 0x13C
je 0xc0429
cmpl $0x14c, %eax # imm = 0x14C
jne 0xc0447
movq %r14, %rdi
movl $0x86, %esi
jmp 0xc0431
movq %r14, %rdi
movl $0x8e, %esi
jmp 0xc0413
movq %r14, %rdi
movl $0xb3, %esi
jmp 0xc03b9
movq %r14, %rdi
movl $0x45, %esi
jmp 0xc0413
movq %r14, %rdi
movl $0xb8, %esi
jmp 0xc0413
movq %r14, %rdi
movl $0x1b, %esi
jmp 0xc0413
movq %r14, %rdi
movl $0x1a, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbfe6d
movq %r14, %rdi
movl $0xad, %esi
jmp 0xc0413
movq %r14, %rdi
movl $0x41, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbff3f
movq %r14, %rdi
movl $0xe5, %esi
jmp 0xc0413
movq %r14, %rdi
movl $0xd9, %esi
jmp 0xc0413
movq %r14, %rdi
movl $0x80, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbfb0e
movq %r14, %rdi
movl $0x8d, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbfede
xorl %eax, %eax
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
DecodeL5RInstructionFail
|
static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
void *Decoder)
{
unsigned Opcode;
// Try and decode as a L6R instruction.
MCInst_clear(Inst);
Opcode = fieldFromInstruction_4(Insn, 27, 5);
switch (Opcode) {
default:
break;
case 0x00:
MCInst_setOpcode(Inst, XCore_LMUL_l6r);
return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler_Fail;
}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
callq 0x44557
cmpl $0x7ffffff, %ebp # imm = 0x7FFFFFF
ja 0xc0485
movq %r14, %rdi
movl $0xa3, %esi
callq 0x4459a
movq %r14, %rdi
movl %ebp, %esi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %rbp
jmp 0xbfd53
xorl %eax, %eax
popq %rbx
popq %r14
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreDisassembler.c
|
XCore_insn_extract
|
void XCore_insn_extract(MCInst *MI, const char *code)
{
int id;
char *p, *p2;
char tmp[128];
// make MSVC shut up on strcpy()
#ifdef _MSC_VER
#pragma warning(push)
#pragma warning(disable : 4996)
#endif
strcpy(tmp, code); // safe because code is way shorter than 128 bytes
#ifdef _MSC_VER
#pragma warning(pop)
#endif
// find the first space
p = strchr(tmp, ' ');
if (p) {
p++;
// find the next ','
p2 = strchr(p, ',');
if (p2) {
*p2 = '\0';
id = XCore_reg_id(p);
if (id) {
// register
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
}
}
// next should be register, or memory?
// skip space
p2++;
while(*p2 && *p2 == ' ')
p2++;
if (*p2) {
// find '['
p = p2;
while(*p && *p != '[')
p++;
if (*p) {
// this is '['
*p = '\0';
id = XCore_reg_id(p2);
if (id) {
// base register
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = id;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
}
p++;
p2 = p;
// until ']'
while(*p && *p != ']')
p++;
if (*p) {
*p = '\0';
// p2 is either index, or disp
id = XCore_reg_id(p2);
if (id) {
// index register
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = id;
}
} else {
// a number means disp
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2);
}
}
}
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.op_count++;
}
}
} else {
// a register?
id = XCore_reg_id(p2);
if (id) {
// register
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
}
}
}
}
} else {
id = XCore_reg_id(p);
if (id) {
// register
if (MI->csh->detail) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
MI->flat_insn->detail->xcore.op_count++;
}
}
}
}
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x80, %rsp
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdi
callq 0x43060
movq %r14, %rdi
movl $0x20, %esi
callq 0x43090
testq %rax, %rax
je 0xc0710
movq %rax, %r15
incq %r15
movq %r15, %rdi
movl $0x2c, %esi
callq 0x43090
testq %rax, %rax
je 0xc056e
movq %rax, %r14
movb $0x0, (%rax)
movq %r15, %rdi
callq 0xc107f
testl %eax, %eax
je 0xc053f
movq 0x320(%rbx), %rcx
cmpl $0x0, 0x68(%rcx)
je 0xc053f
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
shll $0x4, %edx
movl $0x1, 0x34(%rcx,%rdx)
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
shll $0x4, %edx
movl %eax, 0x38(%rcx,%rdx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x30(%rax)
incq %r14
movzbl (%r14), %eax
incq %r14
cmpl $0x20, %eax
je 0xc0542
testl %eax, %eax
je 0xc0710
leaq -0x1(%r14), %rdi
testb %al, %al
je 0xc0571
movzbl %al, %eax
cmpl $0x5b, %eax
je 0xc05d1
movb (%r14), %al
incq %r14
jmp 0xc055a
movq %r15, %rdi
callq 0xc107f
testl %eax, %eax
je 0xc0710
movq 0x320(%rbx), %rcx
cmpl $0x0, 0x68(%rcx)
je 0xc0710
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
shll $0x4, %edx
movl $0x1, 0x34(%rcx,%rdx)
movq 0x310(%rbx), %rcx
addq $0x310, %rbx # imm = 0x310
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
shll $0x4, %edx
movl %eax, 0x38(%rcx,%rdx)
jmp 0xc0703
movb $0x0, -0x1(%r14)
callq 0xc107f
testl %eax, %eax
je 0xc0710
movq 0x320(%rbx), %rcx
cmpl $0x0, 0x68(%rcx)
je 0xc067e
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
shll $0x4, %edx
movl $0x3, 0x34(%rcx,%rdx)
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
shll $0x4, %edx
movb %al, 0x38(%rcx,%rdx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x30(%rax), %ecx
shll $0x4, %ecx
movb $0x0, 0x39(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x30(%rax), %ecx
shll $0x4, %ecx
movl $0x0, 0x3c(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x30(%rax), %ecx
shll $0x4, %ecx
movl $0x1, 0x40(%rax,%rcx)
movq %r14, %rax
movzbl (%rax), %ecx
testl %ecx, %ecx
je 0xc06ef
cmpl $0x5d, %ecx
je 0xc0692
incq %rax
jmp 0xc0681
movb $0x0, (%rax)
movq %r14, %rdi
callq 0xc107f
movq 0x320(%rbx), %rcx
movl 0x68(%rcx), %ecx
testl %eax, %eax
je 0xc06ca
testl %ecx, %ecx
je 0xc06ef
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
shll $0x4, %edx
movb %al, 0x39(%rcx,%rdx)
jmp 0xc06ef
testl %ecx, %ecx
je 0xc06ef
movq %r14, %rdi
callq 0x43110
movq 0x310(%rbx), %rcx
movq 0xe8(%rcx), %rcx
movzbl 0x30(%rcx), %edx
shll $0x4, %edx
movl %eax, 0x3c(%rcx,%rdx)
movq 0x320(%rbx), %rax
cmpl $0x0, 0x68(%rax)
je 0xc0710
addq $0x310, %rbx # imm = 0x310
movq (%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x30(%rax)
addq $0x80, %rsp
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreInstPrinter.c
|
printOperand
|
static void printOperand(MCInst *MI, int OpNum, SStream *O)
{
if (OpNum >= MI->size)
return;
_printOperand(MI, MCInst_getOperand(MI, OpNum), O);
}
|
movzbl 0x4(%rdi), %eax
cmpl %esi, %eax
jle 0xc1063
pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r15
movq %rdi, %rbx
callq 0x445a8
movq %rax, %r14
movq %rax, %rdi
callq 0x445e6
testb %al, %al
je 0xc0f82
movq %r14, %rdi
callq 0x445fe
movl %eax, %r14d
leal -0x1(%r14), %eax
leaq 0x8ebe8(%rip), %rcx # 0x14fb10
movl (%rcx,%rax,4), %eax
leaq 0x1c37ee(%rip), %rsi # 0x284720
addq %rax, %rsi
movq %r15, %rdi
callq 0x44686
movq 0x320(%rbx), %rdx
cmpl $0x0, 0x68(%rdx)
je 0xc105e
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x30(%rax), %ecx
addq $0x34, %rax
cmpb $0x1, 0x70(%rdx)
jne 0xc0fb1
shll $0x4, %ecx
addq %rcx, %rax
addq $0x4, %rax
cmpb $0x0, (%rax)
je 0xc0fe0
movb %r14b, 0x1(%rax)
jmp 0xc105e
movq %r14, %rdi
callq 0x445ee
testb %al, %al
je 0xc105e
movq %r14, %rdi
callq 0x44606
movq %rax, %r14
testl %r14d, %r14d
js 0xc0fbd
cmpl $0xa, %r14d
jb 0xc0fd1
leaq 0x262b6(%rip), %rsi # 0xe7265
jmp 0xc0fd8
shll $0x4, %ecx
movl $0x1, (%rax,%rcx)
jmp 0xc1033
movl %r14d, %edx
negl %edx
cmpl $-0xa, %r14d
ja 0xc0fe5
leaq 0x14158(%rip), %rsi # 0xd5127
jmp 0xc0fec
leaq 0xb0fe(%rip), %rsi # 0xcc0d6
movq %r15, %rdi
movl %r14d, %edx
jmp 0xc0fef
movb %r14b, (%rax)
jmp 0xc105e
leaq 0x14144(%rip), %rsi # 0xd5130
movq %r15, %rdi
xorl %eax, %eax
callq 0x446cd
movq 0x320(%rbx), %rdx
cmpl $0x0, 0x68(%rdx)
je 0xc105e
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x30(%rax), %ecx
addq $0x34, %rax
cmpb $0x1, 0x70(%rdx)
jne 0xc1029
shll $0x4, %ecx
movl %r14d, 0x8(%rax,%rcx)
jmp 0xc105e
shll $0x4, %ecx
movl $0x2, (%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
movzbl 0x30(%rax), %ecx
shll $0x4, %ecx
movl %r14d, 0x38(%rax,%rcx)
movq 0x310(%rbx), %rax
movq 0xe8(%rax), %rax
incb 0x30(%rax)
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreInstPrinter.c
|
XCore_reg_id
|
xcore_reg XCore_reg_id(char *name)
{
int i;
for(i = 1; i < ARR_SIZE(reg_name_maps); i++) {
if (!strcmp(name, reg_name_maps[i].name))
return reg_name_maps[i].id;
}
// not found
return 0;
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl $0x18, %r14d
leaq 0xd068c(%rip), %r15 # 0x191720
movq (%r14,%r15), %rsi
movq %rbx, %rdi
callq 0x430d0
testl %eax, %eax
je 0xc10b5
addq $0x10, %r14
cmpq $0x1a8, %r14 # imm = 0x1A8
jne 0xc1094
xorl %eax, %eax
jmp 0xc10ba
movl -0x8(%r14,%r15), %eax
popq %rbx
popq %r14
popq %r15
retq
|
/sidneyp[P]capstone-tricore/arch/XCore/XCoreMapping.c
|
A64NamedImmMapper_fromString
|
uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid)
{
unsigned i;
for (i = 0; i < N->NumPairs; ++i) {
if (compare_lower_str(N->Pairs[i].Name, Name)) {
*Valid = true;
return N->Pairs[i].Value;
}
}
*Valid = false;
return (uint32_t)-1;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, 0x8(%rsp)
movq %rsi, 0x10(%rsp)
cmpq $0x0, 0x8(%rdi)
je 0xc12a6
movq %rdi, %r14
xorl %r15d, %r15d
xorl %ebx, %ebx
movq (%r14), %rax
shlq $0x4, %r15
movq (%rax,%r15), %r13
movq 0x10(%rsp), %rdi
callq 0x476ec
movq %rax, %r12
movb (%rax), %al
testb %al, %al
je 0xc127e
leaq 0x1(%r12), %rbp
movsbl %al, %edi
callq 0x430f0
movb %al, -0x1(%rbp)
movb (%rbp), %al
incq %rbp
testb %al, %al
jne 0xc1269
movq %r13, %rdi
movq %r12, %rsi
callq 0x430d0
movl %eax, %ebp
movq %r12, %rdi
leaq 0xd2e33(%rip), %rax # 0x1940c8
callq *(%rax)
testl %ebp, %ebp
je 0xc12b5
incl %ebx
movq %rbx, %r15
cmpq %rbx, 0x8(%r14)
ja 0xc1246
movq 0x8(%rsp), %rax
movb $0x0, (%rax)
movl $0xffffffff, %eax # imm = 0xFFFFFFFF
jmp 0xc12c5
movq 0x8(%rsp), %rax
movb $0x1, (%rax)
movq (%r14), %rax
movl 0x8(%rax,%r15), %eax
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/sidneyp[P]capstone-tricore/arch/AArch64/AArch64BaseInfo.c
|
bool sptk::ReadStream<unsigned long>(bool, int, int, int, std::vector<unsigned long, std::allocator<unsigned long>>*, std::istream*, int*)
|
bool ReadStream(bool zero_padding, int stream_skip, int read_point,
int read_size, std::vector<T>* sequence_to_read,
std::istream* input_stream, int* actual_read_size) {
if (stream_skip < 0 || read_point < 0 || read_size <= 0 ||
NULL == sequence_to_read || NULL == input_stream || input_stream->eof()) {
return false;
}
const int type_byte(sizeof((*sequence_to_read)[0]));
if (0 < stream_skip) {
input_stream->ignore(type_byte * stream_skip);
if (input_stream->eof()) return false;
}
const int end(read_point + read_size);
if (sequence_to_read->size() < static_cast<std::size_t>(end)) {
sequence_to_read->resize(end);
}
const int num_read_bytes(type_byte * read_size);
input_stream->read(
reinterpret_cast<char*>(&((*sequence_to_read)[0]) + read_point),
num_read_bytes);
const int gcount(static_cast<int>(input_stream->gcount()));
if (NULL != actual_read_size) {
*actual_read_size = gcount / type_byte;
}
if (num_read_bytes == gcount) {
return !input_stream->fail();
} else if (zero_padding && 0 < gcount) {
// Use std::ceil to zero incomplete data
// as gcount may not be a multiple of sizeof(double).
const int num_zeros(static_cast<int>(
std::ceil(static_cast<double>(num_read_bytes - gcount) / type_byte)));
if (num_zeros < 0) {
return false; // Something wrong!
}
std::fill_n(sequence_to_read->begin() + end - num_zeros, num_zeros,
static_cast<T>(0));
return !input_stream->bad();
}
return false;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movl %ecx, %r15d
movl %edx, %r13d
movl %edx, %eax
orl %esi, %eax
sets %al
testl %ecx, %ecx
setle %cl
orb %al, %cl
testq %r8, %r8
sete %al
testq %r9, %r9
sete %dl
orb %al, %dl
orb %cl, %dl
jne 0xb1a4
movq %r9, %rbx
movq (%r9), %rax
movq -0x18(%rax), %rax
testb $0x2, 0x20(%r9,%rax)
jne 0xb1a4
movq %r8, %r14
movl %edi, %ebp
testl %esi, %esi
jle 0xb0ea
shll $0x3, %esi
movq %rbx, %rdi
callq 0x4070
movq (%rbx), %rax
movq -0x18(%rax), %rax
testb $0x2, 0x20(%rbx,%rax)
jne 0xb1a4
leal (%r15,%r13), %r12d
movq 0x8(%r14), %rax
subq (%r14), %rax
sarq $0x3, %rax
cmpq %r12, %rax
jae 0xb109
movq %r14, %rdi
movq %r12, %rsi
callq 0xb1b6
shll $0x3, %r15d
movl %r13d, %esi
shlq $0x3, %rsi
addq (%r14), %rsi
movq %rbx, %rdi
movq %r15, %rdx
callq 0x43c0
movl 0x8(%rbx), %eax
movq 0x40(%rsp), %rdx
testq %rdx, %rdx
je 0xb13c
leal 0x7(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $0x3, %ecx
movl %ecx, (%rdx)
movl $0x5, %r13d
subl %eax, %r15d
jne 0xb158
movq (%rbx), %rax
movq -0x18(%rax), %rax
testl %r13d, 0x20(%rbx,%rax)
sete %al
jmp 0xb1a6
testl %eax, %eax
setle %al
xorb $0x1, %bpl
orb %al, %bpl
jne 0xb1a4
cvtsi2sd %r15d, %xmm0
mulsd 0x1fa05(%rip), %xmm0 # 0x2ab78
callq 0x40b0
cvttsd2si %xmm0, %eax
testl %eax, %eax
js 0xb1a4
movl $0x1, %r13d
je 0xb147
shlq $0x3, %r12
addq (%r14), %r12
movl %eax, %edx
shlq $0x3, %rdx
subq %rdx, %r12
movq %r12, %rdi
xorl %esi, %esi
callq 0x4200
jmp 0xb147
xorl %eax, %eax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/sp-nitech[P]SPTK/src/utils/sptk_utils.cc
|
sptk::reaper::EpochTracker::GetVoiceTransitionFeatures()
|
void EpochTracker::GetVoiceTransitionFeatures(void) {
int32_t frame_offset = RoundUp(0.5 * time_span_ / internal_frame_interval_);
if (frame_offset <= 0) {
frame_offset = 1;
}
voice_onset_prob_.resize(n_feature_frames_);
voice_offset_prob_.resize(n_feature_frames_);
int32_t limit = n_feature_frames_ - frame_offset;
for (int32_t frame = frame_offset; frame < limit; ++frame) {
float delta_rms = (bandpassed_rms_[frame + frame_offset] -
bandpassed_rms_[frame - frame_offset]) / level_change_den_;
if (delta_rms > 1.0) {
delta_rms = 1.0;
} else {
if (delta_rms < -1.0) {
delta_rms = -1.0;
}
}
float prob_onset = delta_rms;
float prob_offset = -prob_onset;
if (prob_onset > 1.0) {
prob_onset = 1.0;
} else {
if (prob_onset < 0.0) {
prob_onset = 0.0;
}
}
if (prob_offset > 1.0) {
prob_offset = 1.0;
} else {
if (prob_offset < 0.0) {
prob_offset = 0.0;
}
}
voice_onset_prob_[frame] = prob_onset;
voice_offset_prob_[frame] = prob_offset;
}
// Just set the onset and offset probs to zero in the end zones.
for (int32_t frame = 0; frame < frame_offset; ++frame) {
int32_t bframe = n_feature_frames_ - 1 - frame;
voice_onset_prob_[frame] = voice_offset_prob_[frame] = 0.0;
voice_onset_prob_[bframe] = voice_offset_prob_[bframe] = 0.0;
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
cvtss2sd 0x1a8(%rdi), %xmm0
movsd 0x1bd3a(%rip), %xmm1 # 0x2a028
mulsd %xmm1, %xmm0
cvtss2sd 0x174(%rdi), %xmm2
divsd %xmm2, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm1, %xmm0
cvttsd2si %xmm0, %eax
cmpl $0x2, %eax
movl $0x1, %ebp
cmovgel %eax, %ebp
leaq 0xb0(%rdi), %r14
movslq 0x134(%rdi), %rsi
movq %r14, %rdi
callq 0x8ad6
leaq 0xc8(%rbx), %r15
movslq 0x134(%rbx), %rsi
movq %r15, %rdi
callq 0x8ad6
movl 0x134(%rbx), %eax
movl %eax, %esi
subl %ebp, %esi
movl %ebp, %ecx
cmpl %esi, %ebp
jge 0xe405
movq 0x98(%rbx), %rdx
movl %esi, %esi
leaq (%rdx,%rcx,8), %rdi
leaq (,%rcx,4), %r8
movq 0xb0(%rbx), %r9
addq %r8, %r9
addq 0xc8(%rbx), %r8
subq %rcx, %rsi
xorl %r10d, %r10d
movss 0x1c9c7(%rip), %xmm0 # 0x2ad54
movaps 0x1c6ac(%rip), %xmm1 # 0x2aa40
movss 0x1c9bc(%rip), %xmm2 # 0x2ad58
xorps %xmm3, %xmm3
movss (%rdi,%r10,4), %xmm5
subss (%rdx,%r10,4), %xmm5
divss 0x1ac(%rbx), %xmm5
ucomiss %xmm0, %xmm5
movaps %xmm0, %xmm4
ja 0xe3c6
ucomiss %xmm5, %xmm2
movaps %xmm5, %xmm4
jbe 0xe3c6
movaps %xmm2, %xmm4
ucomiss %xmm0, %xmm4
movaps %xmm0, %xmm5
ja 0xe3d9
ucomiss %xmm4, %xmm3
movaps %xmm4, %xmm5
jbe 0xe3d9
xorps %xmm5, %xmm5
ucomiss %xmm4, %xmm2
movaps %xmm0, %xmm6
ja 0xe3f1
ucomiss %xmm3, %xmm4
jbe 0xe3eb
xorps %xmm6, %xmm6
jmp 0xe3f1
xorps %xmm1, %xmm4
movaps %xmm4, %xmm6
movss %xmm5, (%r9,%r10,4)
movss %xmm6, (%r8,%r10,4)
incq %r10
cmpq %r10, %rsi
jne 0xe39f
movq (%r15), %rdx
movq (%r14), %rsi
decl %eax
xorl %edi, %edi
xorl %r8d, %r8d
movl %edi, (%rdx,%r8,4)
movl %edi, (%rsi,%r8,4)
cltq
movl %edi, (%rdx,%rax,4)
movl %edi, (%rsi,%rax,4)
incq %r8
decl %eax
cmpq %r8, %rcx
jne 0xe412
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
nop
|
/sp-nitech[P]SPTK/third_party/REAPER/epoch_tracker/epoch_tracker.cc
|
sptk::reaper::LpcAnalyzer::~LpcAnalyzer()
|
~LpcAnalyzer(void) { }
|
pushq %rbx
movq %rdi, %rbx
movq 0x18(%rdi), %rdi
testq %rdi, %rdi
je 0x10cd0
callq 0x4300
movq (%rbx), %rdi
testq %rdi, %rdi
je 0x10cde
popq %rbx
jmp 0x4300
popq %rbx
retq
|
/sp-nitech[P]SPTK/third_party/REAPER/epoch_tracker/lpc_analyzer.h
|
sptk::reaper::LpcAnalyzer::Durbin(float*, float*, float*, int, float*)
|
void LpcAnalyzer::Durbin(float* r, float* k, float* a, int p, float* ex) {
float bb[BIGSORD];
int i, j;
float e, s, *b = bb;
e = *r;
*k = -r[1] / e;
*a = *k;
e *= (1.0 - (*k) * (*k));
for (i = 1; i < p; i++) {
s = 0;
for (j = 0; j < i; j++) {
s -= a[j] * r[i - j];
}
k[i] = (s - r[i + 1]) / e;
a[i] = k[i];
for (j = 0; j <= i; j++) {
b[j] = a[j];
}
for (j = 0; j < i; j++) {
a[j] += k[i] * b[i - j - 1];
}
e *= (1.0 - (k[i] * k[i]));
}
*ex = e;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1c8, %rsp # imm = 0x1C8
movq %r9, 0x10(%rsp)
movss (%rsi), %xmm0
movss 0x4(%rsi), %xmm1
xorps 0x16ab6(%rip), %xmm1 # 0x2aa40
divss %xmm0, %xmm1
movss %xmm1, (%rdx)
movss %xmm1, (%rcx)
movss (%rdx), %xmm1
mulss %xmm1, %xmm1
cvtss2sd %xmm1, %xmm1
movsd 0x16bde(%rip), %xmm2 # 0x2ab88
subsd %xmm1, %xmm2
cvtss2sd %xmm0, %xmm0
mulsd %xmm2, %xmm0
xorps %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
cmpl $0x2, %r8d
jl 0x140c0
movq %rcx, %r15
movq %rdx, %r12
decl %r8d
leaq 0x4(%rsi), %rbx
movl $0x1, %r13d
leaq 0x30(%rsp), %r14
xorl %ebp, %ebp
movq %r8, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
leaq 0x8(,%rbp,4), %rdx
xorps %xmm0, %xmm0
movq %rbx, %rax
xorl %ecx, %ecx
movss (%r15,%rcx,4), %xmm1
mulss (%rax), %xmm1
subss %xmm1, %xmm0
incq %rcx
addq $-0x4, %rax
cmpq %rcx, %r13
jne 0x13ffb
subss 0x4(%rsi,%r13,4), %xmm0
leaq 0x1(%r13), %rax
movq %rax, 0x28(%rsp)
movss %xmm2, 0xc(%rsp)
divss %xmm2, %xmm0
movss %xmm0, (%r12,%r13,4)
movss %xmm0, (%r15,%r13,4)
leaq 0x30(%rsp), %rdi
movq %r15, %rsi
callq 0x42c0
movq %r14, %rax
xorl %ecx, %ecx
movss (%r12,%r13,4), %xmm0
mulss (%rax), %xmm0
addss (%r15,%rcx,4), %xmm0
movss %xmm0, (%r15,%rcx,4)
incq %rcx
addq $-0x4, %rax
cmpq %rcx, %r13
jne 0x1404d
movss (%r12,%r13,4), %xmm0
mulss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movsd 0x16b03(%rip), %xmm1 # 0x2ab88
subsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtss2sd 0xc(%rsp), %xmm0
mulsd %xmm1, %xmm0
xorps %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
incq %rbp
addq $0x4, %rbx
addq $0x4, %r14
movq 0x28(%rsp), %r13
movq 0x20(%rsp), %r8
cmpq %r8, %rbp
movq 0x18(%rsp), %rsi
jne 0x13feb
movq 0x10(%rsp), %rax
movss %xmm2, (%rax)
addq $0x1c8, %rsp # imm = 0x1C8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/sp-nitech[P]SPTK/third_party/REAPER/epoch_tracker/lpc_analyzer.cc
|
sptk::swipe::im2m(sptk::swipe::intmatrix)
|
matrix im2m(intmatrix yr_matrix) {
matrix nw_matrix = makem(yr_matrix.x, yr_matrix.y);
int i, j;
for (i = 0; i < yr_matrix.x; i++)
for (j = 0; j < yr_matrix.y; j++)
nw_matrix.m[i][j] = yr_matrix.m[i][j];
return(nw_matrix);
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r14
movq %rdi, %r15
shrq $0x20, %r15
movl %r15d, %esi
callq 0x16c00
testl %r14d, %r14d
jle 0x17233
andl $0x7fffffff, %r14d # imm = 0x7FFFFFFF
xorl %ecx, %ecx
testl %r15d, %r15d
jle 0x1722b
movq (%rbx,%rcx,8), %rsi
movq (%rdx,%rcx,8), %rdi
xorl %r8d, %r8d
xorps %xmm0, %xmm0
cvtsi2sdl (%rsi,%r8,4), %xmm0
movsd %xmm0, (%rdi,%r8,8)
incq %r8
cmpq %r8, %r15
jne 0x17214
incq %rcx
cmpq %r14, %rcx
jne 0x17204
popq %rbx
popq %r14
popq %r15
retq
|
/sp-nitech[P]SPTK/third_party/SWIPE/vector.cc
|
sptk::world::fft_plan_dft_r2c_1d(int, double*, double (*) [2], unsigned int)
|
fft_plan fft_plan_dft_r2c_1d(int n, double *in, fft_complex *out,
unsigned int flags) {
#if 0
void makewt(int nw, int *ip, double *w);
void makect(int nc, int *ip, double *c);
#endif
fft_plan output = {0};
output.n = n;
output.in = in;
output.c_in = NULL;
output.out = NULL;
output.c_out = out;
output.sign = FFT_FORWARD;
output.flags = flags;
output.input = new double[n];
output.ip = new int[n];
output.w = new double[n * 5 / 4];
output.ip[0] = 0;
makewt(output.n >> 2, output.ip, output.w);
makect(output.n >> 2, output.ip, output.w + (output.n >> 2));
return output;
}
|
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movslq %esi, %rbx
leal (%rbx,%rbx,4), %eax
leal (%rbx,%rbx,4), %esi
addl $0x3, %esi
testl %eax, %eax
cmovnsl %eax, %esi
sarl $0x2, %esi
movslq %esi, %r15
shlq $0x3, %r15
testl %ebx, %ebx
movq $-0x1, %rax
cmovsq %rax, %r15
leaq (,%rbx,4), %r12
testl %ebx, %ebx
cmovsq %rax, %r12
movq %rdi, %r14
movq %rbx, %rdi
shlq $0x3, %rdi
testl %ebx, %ebx
xorps %xmm0, %xmm0
movups %xmm0, (%r14)
movups %xmm0, 0x10(%r14)
movups %xmm0, 0x20(%r14)
cmovsq %rax, %rdi
xorl %eax, %eax
movq %rax, 0x40(%r14)
movups %xmm0, 0x30(%r14)
movl %ebx, (%r14)
movq %rdx, 0x18(%r14)
movq %rax, 0x10(%r14)
movq %rax, 0x28(%r14)
movq %rcx, 0x20(%r14)
movl $0x1, 0x4(%r14)
movl %r8d, 0x8(%r14)
callq 0x4030
movq %rax, 0x30(%r14)
movq %r12, %rdi
callq 0x4030
movq %rax, %r12
movq %rax, 0x38(%r14)
movq %r15, %rdi
callq 0x4030
movq %rax, %r15
movq %rax, 0x40(%r14)
movl $0x0, (%r12)
sarl $0x2, %ebx
movl %ebx, %edi
movq %r12, %rsi
movq %rax, %rdx
callq 0x1d4af
movslq %ebx, %rdi
leaq (%r15,%rdi,8), %rdx
movq %r12, %rsi
callq 0x1d7cf
movq %r14, %rax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
|
/sp-nitech[P]SPTK/third_party/WORLD/fft_world.cc
|
nga_sdot_patch_
|
Real nga_sdot_patch_(Integer *g_a, char *t_a, int alen, Integer *alo, Integer *ahi, Integer *g_b, char *t_b, int blen, Integer *blo, Integer *bhi)
#endif
{
Real retval;
Integer atype, btype;
pnga_inquire_type(*g_a, &atype);
pnga_inquire_type(*g_b, &btype);
if (atype != btype || atype != C_FLOAT) pnga_error(" wrong types ", 0L);
wnga_dot_patch(*g_a, t_a, alo, ahi, *g_b, t_b, blo, bhi, &retval);
return retval;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r9, 0x8(%rsp)
movq %r8, %r13
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbp
movq (%rdi), %rdi
leaq 0x20(%rsp), %rbx
movq %rbx, %rsi
callq 0x6697b
movq (%r13), %rdi
leaq 0x10(%rsp), %rsi
callq 0x6697b
cmpq $0x3eb, (%rbx) # imm = 0x3EB
jne 0x7b18
cmpq $0x3eb, 0x10(%rsp) # imm = 0x3EB
je 0x7b26
leaq 0xa98af(%rip), %rdi # 0xb13ce
xorl %esi, %esi
callq 0x18f07
movq (%rbp), %rdi
movq (%r13), %r8
subq $0x8, %rsp
leaq 0x24(%rsp), %rbx
movq %r12, %rsi
movq %r15, %rdx
movq %r14, %rcx
movq 0x10(%rsp), %r9
pushq %rbx
pushq 0x78(%rsp)
pushq 0x78(%rsp)
callq 0x13b13
addq $0x20, %rsp
movss (%rbx), %xmm0
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/GlobalArrays[P]ga/global/src/fapi.c
|
ga_cadd_patch_
|
void FATR ga_cadd_patch_(SingleComplex *alpha, Integer *g_a, Integer *ailo, Integer *aihi, Integer *ajlo, Integer *ajhi, SingleComplex *beta, Integer *g_b, Integer *bilo, Integer *bihi, Integer *bjlo, Integer *bjhi, Integer *g_c, Integer *cilo, Integer *cihi, Integer *cjlo, Integer *cjhi)
{
Integer atype, btype, ctype;
pnga_inquire_type(*g_a, &atype);
pnga_inquire_type(*g_b, &btype);
pnga_inquire_type(*g_c, &ctype);
if (atype != btype || atype != ctype || atype != C_SCPL)
pnga_error(" wrong types ", 0L);
sga_add_patch(alpha, *g_a, ailo, aihi, ajlo, ajhi, beta, *g_b, bilo, bihi, bjlo, bjhi, *g_c, cilo, cihi, cjlo, cjhi);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %r9, 0x18(%rsp)
movq %r8, 0x10(%rsp)
movq %rcx, 0x8(%rsp)
movq %rdx, %r12
movq %rsi, %rbp
movq %rdi, %r13
movq 0xa0(%rsp), %r15
movq 0x78(%rsp), %r14
movq (%rsi), %rdi
leaq 0x30(%rsp), %rbx
movq %rbx, %rsi
callq 0x6697b
movq (%r14), %rdi
leaq 0x28(%rsp), %r14
movq %r14, %rsi
callq 0x6697b
movq (%r15), %rdi
leaq 0x20(%rsp), %rsi
callq 0x6697b
movq (%rbx), %rax
cmpq (%r14), %rax
jne 0x8493
cmpq $0x3ee, %rax # imm = 0x3EE
jne 0x8493
cmpq $0x3ee, 0x20(%rsp) # imm = 0x3EE
je 0x84a1
leaq 0xa8f34(%rip), %rdi # 0xb13ce
xorl %esi, %esi
callq 0x18f07
movq (%rbp), %rsi
subq $0x8, %rsp
movq %r13, %rdi
movq %r12, %rdx
movq 0x10(%rsp), %rcx
movq 0x18(%rsp), %r8
movq 0x20(%rsp), %r9
pushq 0xc8(%rsp)
pushq 0xc8(%rsp)
pushq 0xc8(%rsp)
pushq 0xc8(%rsp)
movq 0xc8(%rsp), %rax
pushq (%rax)
pushq 0xc8(%rsp)
pushq 0xc8(%rsp)
pushq 0xc8(%rsp)
pushq 0xc8(%rsp)
movq 0xc8(%rsp), %rax
pushq (%rax)
pushq 0xc8(%rsp)
callq 0x832d
addq $0x98, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/GlobalArrays[P]ga/global/src/fapi.c
|
pnga_copy_patch_dp
|
void pnga_copy_patch_dp(t_a, g_a, ailo, aihi, ajlo, ajhi,
g_b, bilo, bihi, bjlo, bjhi)
Integer g_a, ailo, aihi, ajlo, ajhi;
Integer g_b, bilo, bihi, bjlo, bjhi;
char *t_a;
{
Integer atype, btype, adim1, adim2, bdim1, bdim2;
Integer ilos, ihis, jlos, jhis;
Integer ilod, ihid, jlod, jhid, corr, nelem;
Integer me= pnga_nodeid(), ld, i,j;
Integer lo[2], hi[2];
Integer ldT;
char transp;
DoublePrecision *dbl_ptrA=NULL, *dbl_ptrB=NULL;
Integer ndim, dims[2];
pnga_check_handle(g_a, "pnga_copy_patch_dp");
pnga_check_handle(g_b, "pnga_copy_patch_dp");
/* if(g_a == g_b) pnga_error("pnga_copy_patch_dp: arrays have to different ", 0L); */
pnga_inquire(g_a, &atype, &ndim, dims);
adim1 = dims[0];
adim2 = dims[1];
pnga_inquire(g_b, &btype, &ndim, dims);
bdim1 = dims[0];
bdim2 = dims[1];
if(atype != btype || (atype != C_DBL ))
pnga_error("pnga_copy_patch_dp: wrong types ", 0L);
/* check if patch indices and dims match */
if (ailo <= 0 || aihi > adim1 || ajlo <= 0 || ajhi > adim2)
pnga_error(" pnga_copy_patch_dp: g_a indices out of range ", 0L);
if (bilo <= 0 || bihi > bdim1 || bjlo <= 0 || bjhi > bdim2)
pnga_error(" pnga_copy_patch_dp: g_b indices out of range ", 0L);
/* check if numbers of elements in two patches match each other */
if (((bihi - bilo + 1) != (aihi - ailo + 1)) ||
( (bjhi - bjlo + 1) != (ajhi - ajlo + 1)) )
pnga_error(" pnga_copy_patch_dp: shapes two of patches do not match ", 0L);
/* is transpose operation required ? */
transp = (*t_a == 'n' || *t_a =='N')? 'n' : 't';
/* now find out cordinates of a patch of g_a that I own */
pnga_distribution(g_a, me, lo, hi);
ilos = lo[0];
jlos = lo[1];
ihis = hi[0];
jhis = hi[1];
if(patch_intersect(ailo, aihi, ajlo, ajhi, &ilos, &ihis, &jlos, &jhis)){
pnga_access_ptr(g_a, lo, hi, &dbl_ptrA, &ld);
nelem = (ihis-ilos+1)*(jhis-jlos+1);
if ( transp == 'n' ) {
corr = bilo - ailo;
ilod = ilos + corr;
ihid = ihis + corr;
corr = bjlo - ajlo;
jlod = jlos + corr;
jhid = jhis + corr;
} else {
/* If this is a transpose copy, we need local scratch space */
dbl_ptrB = (DoublePrecision*) pnga_malloc(nelem,MT_F_DBL,"copypatch_dp");
/* Copy from the source into this local array, transposed */
ldT = jhis-jlos+1;
for(j=0; j< jhis-jlos+1; j++)
for(i=0; i< ihis-ilos+1; i++)
*(dbl_ptrB + i*ldT + j) = *(dbl_ptrA + j*ld + i);
/* Now we can reset index to point to the transposed stuff */
pnga_release(g_a, lo, hi);
dbl_ptrA = dbl_ptrB;
ld = ldT;
/* And finally, figure out what the destination indices are */
corr = bilo - ajlo;
ilod = jlos + corr;
ihid = jhis + corr;
corr = bjlo - ailo;
jlod = ilos + corr;
jhid = ihis + corr;
}
/* Put it where it belongs */
lo[0] = ilod;
lo[1] = jlod;
hi[0] = ihid;
hi[1] = jhid;
pnga_put(g_b, lo, hi, dbl_ptrA, &ld);
/* Get rid of local memory if we used it */
if( transp == 't') pnga_free(dbl_ptrB);
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r9, (%rsp)
movq %r8, 0x10(%rsp)
movq %rcx, 0x8(%rsp)
movq %rdx, 0x48(%rsp)
movq %rsi, %r14
movq %rdi, 0x18(%rsp)
movq 0xe0(%rsp), %rbp
xorl %eax, %eax
callq 0x685c6
movq %rax, 0x30(%rsp)
movq $0x0, 0x20(%rsp)
leaq 0xa784c(%rip), %rbx # 0xb12d0
movq %r14, %rdi
movq %rbx, %rsi
callq 0x5d393
movq %rbp, %rdi
movq %rbx, %rsi
callq 0x5d393
leaq 0x88(%rsp), %rbx
leaq 0x80(%rsp), %r15
leaq 0x90(%rsp), %r12
movq %r14, 0x38(%rsp)
movq %r14, %rdi
movq %rbx, %rsi
movq %r15, %rdx
movq %r12, %rcx
callq 0x6688f
movq (%r12), %r14
movq 0x8(%r12), %r13
leaq 0x78(%rsp), %rsi
movq %rbp, %rdi
movq %r15, %rdx
movq %r12, %rcx
callq 0x6688f
movq (%r12), %r15
movq 0x8(%r12), %rax
movq %rax, 0x28(%rsp)
cmpq $0x3ec, (%rbx) # imm = 0x3EC
jne 0x9b06
cmpq $0x3ec, 0x78(%rsp) # imm = 0x3EC
je 0x9b14
leaq 0xa77d6(%rip), %rdi # 0xb12e3
xorl %esi, %esi
callq 0x18f07
movq 0xe8(%rsp), %r12
movq 0x48(%rsp), %rbp
testq %rbp, %rbp
jle 0x9b3b
cmpq $0x0, 0x10(%rsp)
jle 0x9b3b
cmpq 0x8(%rsp), %r14
jl 0x9b3b
cmpq (%rsp), %r13
jge 0x9b49
leaq 0xa77c2(%rip), %rdi # 0xb1304
xorl %esi, %esi
callq 0x18f07
movq 0x100(%rsp), %rbx
movq 0xf8(%rsp), %r13
movq 0xf0(%rsp), %r14
testq %r12, %r12
jle 0x9b77
testq %r13, %r13
jle 0x9b77
cmpq %r14, %r15
jl 0x9b77
cmpq %rbx, 0x28(%rsp)
jge 0x9b85
leaq 0xa77b5(%rip), %rdi # 0xb1333
xorl %esi, %esi
callq 0x18f07
subq %r12, %r14
movq 0x8(%rsp), %rax
subq %rbp, %rax
cmpq %rax, %r14
jne 0x9ba6
subq %r13, %rbx
movq (%rsp), %rax
subq 0x10(%rsp), %rax
cmpq %rax, %rbx
je 0x9bb4
leaq 0xa77b5(%rip), %rdi # 0xb1362
xorl %esi, %esi
callq 0x18f07
movq 0x18(%rsp), %rax
movb (%rax), %r13b
leaq 0x60(%rsp), %rbx
leaq 0x50(%rsp), %r15
movq 0x38(%rsp), %rdi
movq 0x30(%rsp), %rsi
movq %rbx, %rdx
movq %r15, %rcx
callq 0x5f51f
movq (%rbx), %r14
movq 0x8(%rbx), %r9
movq (%r15), %rsi
movq 0x8(%r15), %r15
movq 0x8(%rsp), %r8
cmpq %rbp, %r8
setl %al
movq (%rsp), %rdi
cmpq 0x10(%rsp), %rdi
setl %cl
orb %al, %cl
cmpq %r14, %rsi
setl %al
orb %cl, %al
cmpq %r9, %r15
setl %cl
orb %al, %cl
movb $0x1, %al
jne 0x9c26
cmpq %r8, %r14
setg %cl
cmpq %rbp, %rsi
setl %dl
orb %cl, %dl
je 0x9c7f
movl %r13d, %ebx
testb %al, %al
jne 0x9de9
movq %r9, %r13
movq %rsi, 0x8(%rsp)
andb $-0x21, %bl
leaq 0x60(%rsp), %rsi
leaq 0x50(%rsp), %rdx
leaq 0x20(%rsp), %rcx
leaq 0x40(%rsp), %r8
movq 0x38(%rsp), %rdi
callq 0x6b58f
cmpb $0x4e, %bl
jne 0x9cbc
movq $0x0, (%rsp)
movq %rbp, %rcx
movq %r14, %rax
movq 0x8(%rsp), %rdx
movq 0x10(%rsp), %rsi
movq %r13, %r14
jmp 0x9d92
cmpq %rdi, %r9
setg %cl
cmpq 0x10(%rsp), %r15
setl %dl
orb %cl, %dl
movl %r13d, %ebx
jne 0x9c29
cmpq %rbp, %r14
cmovleq %rbp, %r14
cmpq %r8, %rsi
cmovgeq %r8, %rsi
movq 0x10(%rsp), %rax
cmpq %rax, %r9
cmovleq %rax, %r9
cmpq %rdi, %r15
cmovgeq %rdi, %r15
xorl %eax, %eax
jmp 0x9c29
movb %bl, 0x30(%rsp)
movq 0x8(%rsp), %rbx
subq %r14, %rbx
leaq 0x1(%rbx), %rbp
movq %r15, 0x28(%rsp)
subq %r13, %r15
leaq 0x1(%r15), %rdi
movq %rdi, 0x18(%rsp)
imulq %rbp, %rdi
leaq 0xa76b3(%rip), %rdx # 0xb139b
movl $0x3f5, %esi # imm = 0x3F5
callq 0x5d36c
movq %rax, (%rsp)
testq %r15, %r15
js 0x9d50
movq 0x20(%rsp), %rax
movq 0x40(%rsp), %rcx
movq 0x18(%rsp), %rdx
leaq (,%rdx,8), %rdx
shlq $0x3, %rcx
xorl %edi, %edi
movq (%rsp), %rsi
testq %rbx, %rbx
js 0x9d3d
movq %rsi, %r8
xorl %r9d, %r9d
movsd (%rax,%r9,8), %xmm0
movsd %xmm0, (%r8)
incq %r9
addq %rdx, %r8
cmpq %r9, %rbp
jne 0x9d27
leaq 0x1(%rdi), %r8
addq $0x8, %rsi
addq %rcx, %rax
cmpq %r15, %rdi
movq %r8, %rdi
jne 0x9d1c
leaq 0x60(%rsp), %rsi
leaq 0x50(%rsp), %rdx
movq 0x38(%rsp), %rdi
callq 0x6dcc8
movq (%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x18(%rsp), %rax
movq %rax, 0x40(%rsp)
movq 0x10(%rsp), %rcx
movq %r13, %rax
movq 0x28(%rsp), %rdx
movq 0x48(%rsp), %rsi
movb 0x30(%rsp), %bl
movq 0x8(%rsp), %r15
subq %rcx, %r12
addq %r12, %rax
addq %rdx, %r12
movq 0xf8(%rsp), %rcx
subq %rsi, %rcx
addq %rcx, %r14
addq %r15, %rcx
leaq 0x60(%rsp), %rsi
movq %rax, (%rsi)
movq %r14, 0x8(%rsi)
leaq 0x50(%rsp), %rdx
movq %r12, (%rdx)
movq %rcx, 0x8(%rdx)
movq 0x20(%rsp), %rcx
leaq 0x40(%rsp), %r8
movq 0xe0(%rsp), %rdi
callq 0x6a333
cmpb $0x4e, %bl
je 0x9de9
movq (%rsp), %rdi
callq 0x5d385
addq $0xa8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/GlobalArrays[P]ga/global/src/DP.c
|
pnga_add
|
void pnga_add(void *alpha, Integer g_a, void* beta, Integer g_b, Integer g_c)
{
Integer ndim, type, typeC, me, elems=0, elemsb=0, elemsa=0;
register Integer i;
void *ptr_a, *ptr_b, *ptr_c;
Integer a_grp, b_grp, c_grp;
int local_sync_begin,local_sync_end;
Integer _dims[MAXDIM];
Integer _ld[MAXDIM-1];
Integer _lo[MAXDIM];
Integer _hi[MAXDIM];
Integer andim, adims[MAXDIM];
Integer bndim, bdims[MAXDIM];
Integer cndim, cdims[MAXDIM];
local_sync_begin = _ga_sync_begin; local_sync_end = _ga_sync_end;
_ga_sync_begin = 1; _ga_sync_end=1; /*remove any previous masking*/
a_grp = pnga_get_pgroup(g_a);
b_grp = pnga_get_pgroup(g_b);
c_grp = pnga_get_pgroup(g_c);
if (a_grp != b_grp || b_grp != c_grp)
pnga_error("All three arrays must be on same group for ga_add",0L);
if(local_sync_begin)pnga_pgroup_sync(a_grp);
me = pnga_pgroup_nodeid(a_grp);
if((pnga_compare_distr(g_a,g_b) == FALSE) ||
(pnga_compare_distr(g_a,g_c) == FALSE) ||
pnga_has_ghosts(g_a) || pnga_has_ghosts(g_b) || pnga_has_ghosts(g_c) ||
pnga_total_blocks(g_a) > 0 || pnga_total_blocks(g_b) > 0 ||
pnga_total_blocks(g_c) > 0) {
/* distributions not identical */
pnga_inquire(g_a, &type, &andim, adims);
pnga_inquire(g_b, &type, &bndim, bdims);
pnga_inquire(g_b, &type, &cndim, cdims);
pnga_add_patch(alpha, g_a, one_arr, adims, beta, g_b, one_arr, bdims,
g_c, one_arr, cdims);
return;
}
pnga_pgroup_sync(a_grp);
pnga_inquire(g_c, &typeC, &ndim, _dims);
pnga_distribution(g_c, me, _lo, _hi);
if ( _lo[0]>0 ){
pnga_access_ptr(g_c, _lo, _hi, &ptr_c, _ld);
GET_ELEMS(ndim,_lo,_hi,_ld,&elems);
}
if(g_a == g_c){
ptr_a = ptr_c;
elemsa = elems;
}else {
pnga_inquire(g_a, &type, &ndim, _dims);
if(type != typeC) pnga_error("types not consistent", g_a);
pnga_distribution(g_a, me, _lo, _hi);
if ( _lo[0]>0 ){
pnga_access_ptr(g_a, _lo, _hi, &ptr_a, _ld);
GET_ELEMS(ndim,_lo,_hi,_ld,&elemsa);
}
}
if(g_b == g_c){
ptr_b = ptr_c;
elemsb = elems;
}else {
pnga_inquire(g_b, &type, &ndim, _dims);
if(type != typeC) pnga_error("types not consistent", g_b);
pnga_distribution(g_b, me, _lo, _hi);
if ( _lo[0]>0 ){
pnga_access_ptr(g_b, _lo, _hi, &ptr_b, _ld);
GET_ELEMS(ndim,_lo,_hi,_ld,&elemsb);
}
}
if(elems!= elemsb)pnga_error("inconsistent number of elements a",elems-elemsb);
if(elems!= elemsa)pnga_error("inconsistent number of elements b",elems-elemsa);
if ( _lo[0]>0 ){
/* operation on the "local" piece of data */
switch(type){
int *ia, *ib, *ic;
double *da,*db,*dc;
float *fa, *fb, *fc;
long *la,*lb,*lc;
long long *lla,*llb,*llc;
case C_DBL:
da = (double*)ptr_a;
db = (double*)ptr_b;
dc = (double*)ptr_c;
for(i=0; i<elems; i++)
dc[i] = *(double*)alpha *da[i] +
*(double*)beta * db[i];
break;
case C_DCPL:
for(i=0; i<elems; i++){
DoubleComplex a = ((DoubleComplex*)ptr_a)[i];
DoubleComplex b = ((DoubleComplex*)ptr_b)[i];
DoubleComplex *ac = (DoubleComplex*)ptr_c;
DoubleComplex x= *(DoubleComplex*)alpha;
DoubleComplex y= *(DoubleComplex*)beta;
/* c = x*a + y*b */
ac[i].real = x.real*a.real -
x.imag*a.imag + y.real*b.real - y.imag*b.imag;
ac[i].imag = x.real*a.imag +
x.imag*a.real + y.real*b.imag + y.imag*b.real;
}
break;
case C_SCPL:
for(i=0; i<elems; i++){
SingleComplex a = ((SingleComplex*)ptr_a)[i];
SingleComplex b = ((SingleComplex*)ptr_b)[i];
SingleComplex *ac = (SingleComplex*)ptr_c;
SingleComplex x= *(SingleComplex*)alpha;
SingleComplex y= *(SingleComplex*)beta;
/* c = x*a + y*b */
ac[i].real = x.real*a.real -
x.imag*a.imag + y.real*b.real - y.imag*b.imag;
ac[i].imag = x.real*a.imag +
x.imag*a.real + y.real*b.imag + y.imag*b.real;
}
break;
case C_FLOAT:
fa = (float*)ptr_a;
fb = (float*)ptr_b;
fc = (float*)ptr_c;
for(i=0; i<elems; i++)
fc[i] = *(float*)alpha *fa[i] + *(float*)beta *fb[i];
break;
case C_INT:
ia = (int*)ptr_a;
ib = (int*)ptr_b;
ic = (int*)ptr_c;
for(i=0; i<elems; i++)
ic[i] = *(int*)alpha *ia[i] + *(int*)beta *ib[i];
break;
case C_LONG:
la = (long*)ptr_a;
lb = (long*)ptr_b;
lc = (long*)ptr_c;
for(i=0; i<elems; i++)
lc[i] = *(long*)alpha *la[i] + *(long*)beta *lb[i];
break;
case C_LONGLONG:
lla = (long long*)ptr_a;
llb = (long long*)ptr_b;
llc = (long long*)ptr_c;
for(i=0; i<elems; i++)
llc[i] = ( *(long long*)alpha *lla[i] +
*(long long*)beta * llb[i] );
}
/* release access to the data */
pnga_release_update(g_c, _lo, _hi);
if(g_c != g_a)pnga_release(g_a, _lo, _hi);
if(g_c != g_b)pnga_release(g_b, _lo, _hi);
}
if(local_sync_end)pnga_pgroup_sync(a_grp);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x148, %rsp # imm = 0x148
movq %r8, %r13
movq %rcx, %r12
movq %rdx, 0x58(%rsp)
movq %rsi, %r15
movq %rdi, 0x38(%rsp)
leaq 0xc576b(%rip), %rax # 0xd7160
movl (%rax), %r14d
leaq 0xc5765(%rip), %rcx # 0xd7164
movl (%rcx), %edx
movl %edx, 0x54(%rsp)
movl $0x1, %edx
movl %edx, (%rax)
movl %edx, (%rcx)
movq %rsi, %rdi
callq 0x6071a
movq %rax, %rbp
movq %r12, 0x28(%rsp)
movq %r12, %rdi
callq 0x6071a
movq %rax, %r12
movq %r13, 0x10(%rsp)
movq %r13, %rdi
callq 0x6071a
movq %rbp, %rcx
xorq %r12, %rcx
xorq %r12, %rax
orq %rcx, %rax
je 0x11a52
leaq 0xa0a4a(%rip), %rdi # 0xb2495
xorl %esi, %esi
callq 0x18f07
testl %r14d, %r14d
je 0x11a5f
movq %rbp, %rdi
callq 0x6979c
movq %rbp, %rdi
callq 0x62fe1
movq %rax, %r12
movq %r15, %rdi
movq 0x28(%rsp), %r14
movq %r14, %rsi
callq 0x68630
testq %rax, %rax
je 0x11ae7
movq %r15, %rdi
movq 0x10(%rsp), %rsi
callq 0x68630
testq %rax, %rax
je 0x11ae7
movq %r15, %rdi
callq 0x652f9
testq %rax, %rax
jne 0x11ae7
movq %r14, %rdi
callq 0x652f9
testq %rax, %rax
jne 0x11ae7
movq 0x10(%rsp), %rdi
callq 0x652f9
testq %rax, %rax
jne 0x11ae7
movq %r15, %rdi
callq 0x693e7
testq %rax, %rax
jg 0x11ae7
movq %r14, %rdi
callq 0x693e7
testq %rax, %rax
jg 0x11ae7
movq 0x10(%rsp), %rdi
callq 0x693e7
testq %rax, %rax
jle 0x11b7f
leaq 0x48(%rsp), %r12
leaq 0xe0(%rsp), %rdx
leaq 0x110(%rsp), %rbp
movq %r15, %rdi
movq %r12, %rsi
movq %rbp, %rcx
callq 0x6688f
leaq 0x8(%rsp), %rdx
leaq 0x60(%rsp), %r13
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rcx
callq 0x6688f
leaq 0x40(%rsp), %rdx
leaq 0xa0(%rsp), %rbx
movq %r14, %rdi
movq %r12, %rsi
movq %rbx, %rcx
callq 0x6688f
subq $0x8, %rsp
leaq 0xc54d8(%rip), %rdx # 0xd7020
movq 0x40(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rcx
movq 0x60(%rsp), %r8
movq %r14, %r9
pushq %rbx
pushq %rdx
pushq 0x28(%rsp)
pushq %r13
pushq %rdx
callq 0x15cbe
addq $0x30, %rsp
addq $0x148, %rsp # imm = 0x148
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq %rbp, %rdi
callq 0x6979c
leaq 0x40(%rsp), %rsi
leaq 0x8(%rsp), %rdx
leaq 0x110(%rsp), %rcx
movq 0x10(%rsp), %r14
movq %r14, %rdi
callq 0x6688f
leaq 0x60(%rsp), %r13
leaq 0xa0(%rsp), %rcx
movq %r14, %rdi
movq %r12, %rsi
movq %r13, %rdx
callq 0x5f51f
cmpq $0x0, (%r13)
jle 0x11c59
leaq 0x60(%rsp), %rsi
leaq 0xa0(%rsp), %rdx
movq %rsp, %rcx
leaq 0xe0(%rsp), %r8
movq %r14, %rdi
callq 0x6b58f
movq 0x8(%rsp), %rax
movq 0x98(%rsp,%rax,8), %r13
subq 0x58(%rsp,%rax,8), %r13
incq %r13
cmpq $0x2, %rax
jl 0x11c5c
xorl %r14d, %r14d
movq 0xa0(%rsp,%r14,8), %rax
subq 0x60(%rsp,%r14,8), %rax
incq %rax
cmpq %rax, 0xe0(%rsp,%r14,8)
je 0x11c33
leaq 0xa0775(%rip), %rdi # 0xb23a0
movq %r14, %rsi
callq 0x18f07
movq 0xa0(%rsp,%r14,8), %rax
subq 0x60(%rsp,%r14,8), %rax
incq %rax
imulq %rax, %r13
incq %r14
movq 0x8(%rsp), %rax
decq %rax
cmpq %r14, %rax
jg 0x11c0a
jmp 0x11c5c
xorl %r13d, %r13d
cmpq 0x10(%rsp), %r15
movq %r13, 0x30(%rsp)
jne 0x11c7b
movq (%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x28(%rsp), %r14
jmp 0x11d6c
leaq 0x48(%rsp), %r14
leaq 0x8(%rsp), %rdx
leaq 0x110(%rsp), %rcx
movq %r15, %rdi
movq %r14, %rsi
callq 0x6688f
movq (%r14), %rax
cmpq 0x40(%rsp), %rax
je 0x11cb1
leaq 0xa081e(%rip), %rdi # 0xb24c7
movq %r15, %rsi
callq 0x18f07
leaq 0x60(%rsp), %r14
leaq 0xa0(%rsp), %rcx
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
callq 0x5f51f
cmpq $0x0, (%r14)
movq 0x28(%rsp), %r14
jle 0x11d69
leaq 0x60(%rsp), %rsi
leaq 0xa0(%rsp), %rdx
leaq 0x20(%rsp), %rcx
leaq 0xe0(%rsp), %r8
movq %r15, %rdi
callq 0x6b58f
movq 0x8(%rsp), %rax
movq 0x98(%rsp,%rax,8), %r13
subq 0x58(%rsp,%rax,8), %r13
incq %r13
cmpq $0x2, %rax
jl 0x11d6c
xorl %ebx, %ebx
movq 0xa0(%rsp,%rbx,8), %rax
subq 0x60(%rsp,%rbx,8), %rax
incq %rax
cmpq %rax, 0xe0(%rsp,%rbx,8)
je 0x11d43
leaq 0xa0665(%rip), %rdi # 0xb23a0
movq %rbx, %rsi
callq 0x18f07
movq 0xa0(%rsp,%rbx,8), %rax
subq 0x60(%rsp,%rbx,8), %rax
incq %rax
imulq %rax, %r13
incq %rbx
movq 0x8(%rsp), %rax
decq %rax
cmpq %rbx, %rax
jg 0x11d1a
jmp 0x11d6c
xorl %r13d, %r13d
cmpq 0x10(%rsp), %r14
jne 0x11d8b
movq (%rsp), %rax
movq %rax, 0x18(%rsp)
movq 0x30(%rsp), %r14
movq 0x38(%rsp), %rbx
jmp 0x11e7d
leaq 0x48(%rsp), %rbx
leaq 0x8(%rsp), %rdx
leaq 0x110(%rsp), %rcx
movq %r14, %rdi
movq %rbx, %rsi
callq 0x6688f
movq (%rbx), %rax
cmpq 0x40(%rsp), %rax
je 0x11dc1
leaq 0xa070e(%rip), %rdi # 0xb24c7
movq %r14, %rsi
callq 0x18f07
leaq 0x60(%rsp), %rbx
leaq 0xa0(%rsp), %rcx
movq %r14, %rdi
movq %r12, %rsi
movq %rbx, %rdx
callq 0x5f51f
cmpq $0x0, (%rbx)
movq 0x38(%rsp), %rbx
jle 0x11e7a
leaq 0x60(%rsp), %rsi
leaq 0xa0(%rsp), %rdx
leaq 0x18(%rsp), %rcx
leaq 0xe0(%rsp), %r8
movq %r14, %rdi
callq 0x6b58f
movq 0x8(%rsp), %rax
movq 0x98(%rsp,%rax,8), %r14
subq 0x58(%rsp,%rax,8), %r14
incq %r14
cmpq $0x2, %rax
jl 0x11e7d
xorl %r12d, %r12d
movq 0xa0(%rsp,%r12,8), %rax
subq 0x60(%rsp,%r12,8), %rax
incq %rax
cmpq %rax, 0xe0(%rsp,%r12,8)
je 0x11e54
leaq 0xa0554(%rip), %rdi # 0xb23a0
movq %r12, %rsi
callq 0x18f07
movq 0xa0(%rsp,%r12,8), %rax
subq 0x60(%rsp,%r12,8), %rax
incq %rax
imulq %rax, %r14
incq %r12
movq 0x8(%rsp), %rax
decq %rax
cmpq %r12, %rax
jg 0x11e2b
jmp 0x11e7d
xorl %r14d, %r14d
movq 0x30(%rsp), %rsi
subq %r14, %rsi
je 0x11e93
leaq 0xa064e(%rip), %rdi # 0xb24dc
callq 0x18f07
movq 0x30(%rsp), %rsi
subq %r13, %rsi
movq 0x10(%rsp), %r14
movq 0x58(%rsp), %r12
je 0x11eb3
leaq 0xa0650(%rip), %rdi # 0xb24fe
callq 0x18f07
cmpq $0x0, 0x60(%rsp)
jle 0x12194
movq $-0x3e9, %rax # imm = 0xFC17
addq 0x48(%rsp), %rax
cmpq $0xf, %rax
movq 0x30(%rsp), %r9
ja 0x12147
leaq 0xa03f7(%rip), %rcx # 0xb22d8
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
testq %r9, %r9
jle 0x12147
movq 0x20(%rsp), %rax
movq 0x18(%rsp), %rcx
movq (%rsp), %rdx
xorl %esi, %esi
movl (%rax,%rsi,4), %edi
imull (%rbx), %edi
movl (%rcx,%rsi,4), %r8d
imull (%r12), %r8d
addl %edi, %r8d
movl %r8d, (%rdx,%rsi,4)
incq %rsi
cmpq %rsi, %r9
jne 0x11f03
jmp 0x12147
testq %r9, %r9
jle 0x12147
movq 0x20(%rsp), %rax
movq 0x18(%rsp), %rcx
movq (%rsp), %rdx
xorl %esi, %esi
movapd 0x9f559(%rip), %xmm0 # 0xb14a0
movsd (%rbx), %xmm3
movsd 0x8(%rbx), %xmm4
movapd %xmm4, %xmm5
xorpd %xmm0, %xmm5
movsd (%r12), %xmm1
movsd 0x8(%r12), %xmm6
movapd %xmm6, %xmm2
xorpd %xmm0, %xmm2
movupd (%rax,%rsi), %xmm7
movupd (%rcx,%rsi), %xmm8
unpcklpd %xmm4, %xmm5 # xmm5 = xmm5[0],xmm4[0]
unpcklpd %xmm3, %xmm3 # xmm3 = xmm3[0,0]
mulpd %xmm7, %xmm3
shufpd $0x1, %xmm7, %xmm7 # xmm7 = xmm7[1,0]
mulpd %xmm5, %xmm7
addpd %xmm7, %xmm3
unpcklpd %xmm1, %xmm1 # xmm1 = xmm1[0,0]
mulpd %xmm8, %xmm1
shufpd $0x1, %xmm8, %xmm8 # xmm8 = xmm8[1,0]
addpd %xmm3, %xmm1
unpcklpd %xmm6, %xmm2 # xmm2 = xmm2[0],xmm6[0]
mulpd %xmm8, %xmm2
addpd %xmm1, %xmm2
movupd %xmm2, (%rdx,%rsi)
addq $0x10, %rsi
decq %r9
jne 0x11f47
jmp 0x12147
testq %r9, %r9
jle 0x12147
movq 0x20(%rsp), %rax
movq 0x18(%rsp), %rcx
movq (%rsp), %rdx
xorl %esi, %esi
movq (%rax,%rsi,8), %rdi
imulq (%rbx), %rdi
movq (%rcx,%rsi,8), %r8
imulq (%r12), %r8
addq %rdi, %r8
movq %r8, (%rdx,%rsi,8)
incq %rsi
cmpq %rsi, %r9
jne 0x11fdd
jmp 0x12147
testq %r9, %r9
jle 0x12147
movq 0x20(%rsp), %rax
movq 0x18(%rsp), %rcx
movq (%rsp), %rdx
xorl %esi, %esi
movq (%rax,%rsi,8), %rdi
imulq (%rbx), %rdi
movq (%rcx,%rsi,8), %r8
imulq (%r12), %r8
addq %rdi, %r8
movq %r8, (%rdx,%rsi,8)
incq %rsi
cmpq %rsi, %r9
jne 0x1201b
jmp 0x12147
testq %r9, %r9
jle 0x12147
movq 0x20(%rsp), %rax
movq 0x18(%rsp), %rcx
movq (%rsp), %rdx
xorl %esi, %esi
movss (%rbx), %xmm0
movss (%r12), %xmm1
mulss (%rcx,%rsi,4), %xmm1
mulss (%rax,%rsi,4), %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%rdx,%rsi,4)
incq %rsi
cmpq %rsi, %r9
jne 0x12059
jmp 0x12147
testq %r9, %r9
jle 0x12147
movq 0x20(%rsp), %rax
movq 0x18(%rsp), %rcx
movq (%rsp), %rdx
xorl %esi, %esi
movsd (%rbx), %xmm0
movsd (%r12), %xmm1
mulsd (%rcx,%rsi,8), %xmm1
mulsd (%rax,%rsi,8), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rdx,%rsi,8)
incq %rsi
cmpq %rsi, %r9
jne 0x1209c
jmp 0x12147
testq %r9, %r9
jle 0x12147
movq 0x20(%rsp), %rax
movq 0x18(%rsp), %rcx
movq (%rsp), %rdx
xorl %esi, %esi
movaps 0x9f3ae(%rip), %xmm0 # 0xb1490
movss (%rbx), %xmm3
movss 0x4(%rbx), %xmm4
movaps %xmm4, %xmm5
xorps %xmm0, %xmm5
movss (%r12), %xmm1
movss 0x4(%r12), %xmm6
movaps %xmm6, %xmm2
xorps %xmm0, %xmm2
movsd (%rax,%rsi,8), %xmm7
movsd (%rcx,%rsi,8), %xmm8
unpcklps %xmm4, %xmm5 # xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1]
unpcklps %xmm3, %xmm3 # xmm3 = xmm3[0,0,1,1]
mulps %xmm7, %xmm3
shufps $0xe1, %xmm7, %xmm7 # xmm7 = xmm7[1,0,2,3]
mulps %xmm5, %xmm7
addps %xmm7, %xmm3
unpcklps %xmm1, %xmm1 # xmm1 = xmm1[0,0,1,1]
mulps %xmm8, %xmm1
shufps $0xe1, %xmm8, %xmm8 # xmm8 = xmm8[1,0,2,3]
addps %xmm3, %xmm1
unpcklps %xmm6, %xmm2 # xmm2 = xmm2[0],xmm6[0],xmm2[1],xmm6[1]
mulps %xmm8, %xmm2
addps %xmm1, %xmm2
movlps %xmm2, (%rdx,%rsi,8)
incq %rsi
cmpq %rsi, %r9
jne 0x120e2
leaq 0x60(%rsp), %rsi
leaq 0xa0(%rsp), %rdx
movq %r14, %rdi
callq 0x6dcc9
cmpq %r14, %r15
je 0x12176
leaq 0x60(%rsp), %rsi
leaq 0xa0(%rsp), %rdx
movq %r15, %rdi
callq 0x6dcc8
cmpq %r14, 0x28(%rsp)
je 0x12194
leaq 0x60(%rsp), %rsi
leaq 0xa0(%rsp), %rdx
movq 0x28(%rsp), %rdi
callq 0x6dcc8
cmpl $0x0, 0x54(%rsp)
je 0x11b6d
movq %rbp, %rdi
callq 0x6979c
jmp 0x11b6d
|
/GlobalArrays[P]ga/global/src/global.nalg.c
|
pnga_patch_intersect
|
logical pnga_patch_intersect(Integer *lo, Integer *hi,
Integer *lop, Integer *hip, Integer ndim)
{
Integer i;
/* check consistency of patch coordinates */
for(i=0; i<ndim; i++) {
if(hi[i] < lo[i]) return FALSE; /* inconsistent */
if(hip[i] < lop[i]) return FALSE; /* inconsistent */
}
/* find the intersection and update (ilop: ihip, jlop: jhip) */
for(i=0; i<ndim; i++) {
if(hi[i] < lop[i]) return FALSE; /* don't intersect */
if(hip[i] < lo[i]) return FALSE; /* don't intersect */
}
for(i=0; i<ndim; i++) {
lop[i] = GA_MAX(lo[i], lop[i]);
hip[i] = GA_MIN(hi[i], hip[i]);
}
return TRUE;
}
|
testq %r8, %r8
jle 0x12516
xorl %eax, %eax
xorl %r9d, %r9d
movq (%rsi,%r9,8), %r10
cmpq (%rdi,%r9,8), %r10
jl 0x12577
movq (%rcx,%r9,8), %r10
cmpq (%rdx,%r9,8), %r10
jl 0x12577
incq %r9
cmpq %r9, %r8
jne 0x124fa
testq %r8, %r8
jle 0x1253c
xorl %eax, %eax
xorl %r9d, %r9d
movq (%rsi,%r9,8), %r10
cmpq (%rdx,%r9,8), %r10
jl 0x12577
movq (%rcx,%r9,8), %r10
cmpq (%rdi,%r9,8), %r10
jl 0x12577
incq %r9
cmpq %r9, %r8
jne 0x12520
movl $0x1, %eax
testq %r8, %r8
jle 0x12577
xorl %r9d, %r9d
movq (%rdi,%r9,8), %r10
movq (%rdx,%r9,8), %r11
cmpq %r11, %r10
cmovgq %r10, %r11
movq %r11, (%rdx,%r9,8)
movq (%rsi,%r9,8), %r10
movq (%rcx,%r9,8), %r11
cmpq %r11, %r10
cmovlq %r10, %r11
movq %r11, (%rcx,%r9,8)
incq %r9
cmpq %r9, %r8
jne 0x12549
retq
|
/GlobalArrays[P]ga/global/src/global.npatch.c
|
pnga_dot_patch
|
void pnga_dot_patch(Integer g_a, char *t_a, Integer *alo, Integer *ahi, Integer g_b, char *t_b, Integer *blo, Integer *bhi, void *retval)
{
Integer i=0, j=0;
Integer compatible=0;
Integer atype=0, btype=0, andim=0, adims[MAXDIM], bndim=0, bdims[MAXDIM];
Integer loA[MAXDIM], hiA[MAXDIM], ldA[MAXDIM];
Integer loB[MAXDIM], hiB[MAXDIM], ldB[MAXDIM];
Integer g_A = g_a, g_B = g_b;
char *A_ptr=NULL, *B_ptr=NULL;
Integer ctype=0;
Integer atotal=0, btotal=0;
int isum=0, alen=0;
long lsum=0;
long long llsum=0;
double dsum=0;
DoubleComplex zsum={0,0};
DoubleComplex csum={0,0};
float fsum=0;
Integer me= pnga_nodeid(), temp_created=0;
Integer nproc = pnga_nnodes();
Integer num_blocks_a=0, num_blocks_b=0;
char *tempname = "temp", transp, transp_a, transp_b;
int local_sync_begin=0;
Integer a_grp=0, b_grp=0;
_iterator_hdl hdl_a, hdl_b;
local_sync_begin = _ga_sync_begin;
_ga_sync_begin = 1; _ga_sync_end=1; /*remove any previous masking*/
if(local_sync_begin)pnga_sync();
a_grp = pnga_get_pgroup(g_a);
b_grp = pnga_get_pgroup(g_b);
if (a_grp != b_grp)
pnga_error("Both arrays must be defined on same group",0L);
me = pnga_pgroup_nodeid(a_grp);
pnga_inquire(g_a, &atype, &andim, adims);
pnga_inquire(g_b, &btype, &bndim, bdims);
if(atype != btype ) pnga_error(" type mismatch ", 0L);
/* check if patch indices and g_a dims match */
for(i=0; i<andim; i++)
if(alo[i] <= 0 || ahi[i] > adims[i])
pnga_error("g_a indices out of range ", g_a);
for(i=0; i<bndim; i++)
if(blo[i] <= 0 || bhi[i] > bdims[i])
pnga_error("g_b indices out of range ", g_b);
/* check if numbers of elements in two patches match each other */
atotal = 1; for(i=0; i<andim; i++) atotal *= (ahi[i] - alo[i] + 1);
btotal = 1; for(i=0; i<bndim; i++) btotal *= (bhi[i] - blo[i] + 1);
if(atotal != btotal)
pnga_error(" capacities of patches do not match ", 0L);
/* is transpose operation required ? */
/* -- only if for one array transpose operation requested*/
transp_a = (*t_a == 'n' || *t_a =='N')? 'n' : 't';
transp_b = (*t_b == 'n' || *t_b =='N')? 'n' : 't';
transp = (transp_a == transp_b)? 'n' : 't';
/* Find out if distribution is block-cyclic */
num_blocks_a = pnga_total_blocks(g_a);
num_blocks_b = pnga_total_blocks(g_b);
if (num_blocks_a >= 0 || num_blocks_b >= 0) {
if (transp_a == 't' || transp_b == 't')
pnga_error("transpose not supported for block-cyclic data ", 0);
}
isum = 0; dsum = 0.; zsum.real = 0.; zsum.imag = 0.; fsum = 0;lsum=0;llsum=0;
csum.real = 0.; csum.imag = 0.;
switch (atype){
case C_INT:
*(int*)retval = isum;
alen = 1;
break;
case C_DCPL:
((double*)retval)[0] = zsum.real;
((double*)retval)[1] = zsum.imag;
alen = 2;
break;
case C_SCPL:
((float*)retval)[0] = csum.real;
((float*)retval)[1] = csum.imag;
alen = 2;
break;
case C_DBL:
*(double*)retval = dsum;
alen = 1;
break;
case C_FLOAT:
*(float*)retval = fsum;
alen = 1;
break;
case C_LONG:
*(long*)retval = lsum;
alen = 1;
break;
case C_LONGLONG:
*(long long*)retval = llsum;
alen = 1;
break;
default:
pnga_error("snga_dot_local_patch: type not supported",atype);
}
if (num_blocks_a < 0 && num_blocks_b < 0) {
/* find out coordinates of patches of g_A and g_B that I own */
pnga_distribution(g_A, me, loA, hiA);
pnga_distribution(g_B, me, loB, hiB);
if(pnga_comp_patch(andim, loA, hiA, bndim, loB, hiB) &&
pnga_comp_patch(andim, alo, ahi, bndim, blo, bhi)) compatible = 1;
else compatible = 0;
/* pnga_gop(pnga_type_f2c(MT_F_INT), &compatible, 1, "*"); */
pnga_gop(pnga_type_f2c(MT_F_INT), &compatible, 1, "&&");
if(!(compatible && (transp=='n'))) {
/* either patches or distributions do not match:
* - create a temp array that matches distribution of g_a
* - copy & reshape patch of g_b into g_B
*/
if (!pnga_duplicate(g_a, &g_B, tempname))
pnga_error("duplicate failed",0L);
pnga_copy_patch(&transp, g_b, blo, bhi, g_B, alo, ahi);
bndim = andim;
temp_created = 1;
pnga_distribution(g_B, me, loB, hiB);
}
if(!pnga_comp_patch(andim, loA, hiA, bndim, loB, hiB))
pnga_error(" patches mismatch ",0);
/* A[83:125,1:1] <==> B[83:125] */
if(andim > bndim) andim = bndim; /* need more work */
/* determine subsets of my patches to access */
if(pnga_patch_intersect(alo, ahi, loA, hiA, andim)){
pnga_access_ptr(g_A, loA, hiA, &A_ptr, ldA);
pnga_access_ptr(g_B, loA, hiA, &B_ptr, ldB);
snga_dot_local_patch(atype, andim, loA, hiA, ldA, A_ptr, B_ptr,
&alen, retval);
/* release access to the data */
pnga_release(g_A, loA, hiA);
pnga_release(g_B, loA, hiA);
}
} else {
/* Create copy of g_b identical with identical distribution as g_a */
if (!pnga_duplicate(g_a, &g_B, tempname))
pnga_error("duplicate failed",0L);
pnga_copy_patch(&transp, g_b, blo, bhi, g_B, alo, ahi);
temp_created = 1;
#if 1
pnga_local_iterator_init(g_a, &hdl_a);
pnga_local_iterator_init(g_B, &hdl_b);
while(pnga_local_iterator_next(&hdl_a, loA, hiA, &A_ptr, ldA)) {
Integer lo[MAXDIM]/*, hi[MAXDIM]*/;
Integer offset, jtot, last;
pnga_local_iterator_next(&hdl_b, loB, hiB, &B_ptr, ldB);
/* make copies of loA and hiA since pnga_patch_intersect destroys
original versions */
for (j=0; j<andim; j++) {
lo[j] = loA[j];
/*hi[j] = hiA[j];*/
}
if(pnga_patch_intersect(alo, ahi, loA, hiA, andim)){
/* evaluate offsets for system */
offset = 0;
last = andim-1;
jtot = 1;
for (j=0; j<last; j++) {
offset += (loA[j] - lo[j])*jtot;
jtot *= ldA[j];
}
offset += (loA[last]-lo[last])*jtot;
/* offset pointers by correct amount */
switch (atype){
case C_INT:
A_ptr = (void*)((int*)(A_ptr) + offset);
B_ptr = (void*)((int*)(B_ptr) + offset);
break;
case C_DCPL:
A_ptr = (void*)((DoubleComplex*)(A_ptr) + offset);
B_ptr = (void*)((DoubleComplex*)(B_ptr) + offset);
break;
case C_SCPL:
A_ptr = (void*)((SingleComplex*)(A_ptr) + offset);
B_ptr = (void*)((SingleComplex*)(B_ptr) + offset);
break;
case C_DBL:
A_ptr = (void*)((double*)(A_ptr) + offset);
B_ptr = (void*)((double*)(B_ptr) + offset);
break;
case C_FLOAT:
A_ptr = (void*)((float*)(A_ptr) + offset);
B_ptr = (void*)((float*)(B_ptr) + offset);
break;
case C_LONG:
A_ptr = (void*)((long*)(A_ptr) + offset);
B_ptr = (void*)((long*)(B_ptr) + offset);
break;
case C_LONGLONG:
A_ptr = (void*)((long long*)(A_ptr) + offset);
B_ptr = (void*)((long long*)(B_ptr) + offset);
break;
}
snga_dot_local_patch(atype, andim, loA, hiA, ldA, A_ptr, B_ptr,
&alen, retval);
}
}
#else
/* If g_a regular distribution, then just use normal dot product on patch */
if (num_blocks_a < 0) {
/* find out coordinates of patches of g_A and g_B that I own */
pnga_distribution(g_A, me, loA, hiA);
pnga_distribution(g_B, me, loB, hiB);
if(!pnga_comp_patch(andim, loA, hiA, bndim, loB, hiB))
pnga_error(" patches mismatch ",0);
/* A[83:125,1:1] <==> B[83:125] */
if(andim > bndim) andim = bndim; /* need more work */
if(pnga_patch_intersect(alo, ahi, loA, hiA, andim)){
pnga_access_ptr(g_A, loA, hiA, &A_ptr, ldA);
pnga_access_ptr(g_B, loA, hiA, &B_ptr, ldB);
snga_dot_local_patch(atype, andim, loA, hiA, ldA, A_ptr, B_ptr,
&alen, retval);
/* release access to the data */
pnga_release(g_A, loA, hiA);
pnga_release(g_B, loA, hiA);
}
} else {
Integer lo[MAXDIM]/*, hi[MAXDIM]*/;
Integer offset, jtot, last;
/* simple block cyclic data distribution */
if (!pnga_uses_proc_grid(g_a)) {
for (i=me; i<num_blocks_a; i += nproc) {
pnga_distribution(g_A, i, loA, hiA);
/* make copies of loA and hiA since pnga_patch_intersect destroys
original versions */
for (j=0; j<andim; j++) {
lo[j] = loA[j];
/*hi[j] = hiA[j];*/
}
if(pnga_patch_intersect(alo, ahi, loA, hiA, andim)){
pnga_access_block_ptr(g_A, i, &A_ptr, ldA);
pnga_access_block_ptr(g_B, i, &B_ptr, ldB);
/* evaluate offsets for system */
offset = 0;
last = andim-1;
jtot = 1;
for (j=0; j<last; j++) {
offset += (loA[j] - lo[j])*jtot;
jtot *= ldA[j];
}
offset += (loA[last]-lo[last])*jtot;
/* offset pointers by correct amount */
switch (atype){
case C_INT:
A_ptr = (void*)((int*)(A_ptr) + offset);
B_ptr = (void*)((int*)(B_ptr) + offset);
break;
case C_DCPL:
A_ptr = (void*)((DoubleComplex*)(A_ptr) + offset);
B_ptr = (void*)((DoubleComplex*)(B_ptr) + offset);
break;
case C_SCPL:
A_ptr = (void*)((SingleComplex*)(A_ptr) + offset);
B_ptr = (void*)((SingleComplex*)(B_ptr) + offset);
break;
case C_DBL:
A_ptr = (void*)((double*)(A_ptr) + offset);
B_ptr = (void*)((double*)(B_ptr) + offset);
break;
case C_FLOAT:
A_ptr = (void*)((float*)(A_ptr) + offset);
B_ptr = (void*)((float*)(B_ptr) + offset);
break;
case C_LONG:
A_ptr = (void*)((long*)(A_ptr) + offset);
B_ptr = (void*)((long*)(B_ptr) + offset);
break;
case C_LONGLONG:
A_ptr = (void*)((long long*)(A_ptr) + offset);
B_ptr = (void*)((long long*)(B_ptr) + offset);
break;
}
snga_dot_local_patch(atype, andim, loA, hiA, ldA, A_ptr, B_ptr,
&alen, retval);
/* release access to the data */
pnga_release_block(g_A, i);
pnga_release_block(g_B, i);
}
}
} else {
/* Uses scalapack block-cyclic data distribution */
Integer proc_index[MAXDIM], index[MAXDIM];
Integer topology[MAXDIM]/*, chk*/;
Integer blocks[MAXDIM], block_dims[MAXDIM];
pnga_get_proc_index(g_a, me, proc_index);
pnga_get_proc_index(g_a, me, index);
pnga_get_block_info(g_a, blocks, block_dims);
pnga_get_proc_grid(g_a, topology);
while (index[andim-1] < blocks[andim-1]) {
/* find bounding coordinates of block */
/*chk = 1;*/
for (i = 0; i < andim; i++) {
loA[i] = index[i]*block_dims[i]+1;
hiA[i] = (index[i] + 1)*block_dims[i];
if (hiA[i] > adims[i]) hiA[i] = adims[i];
/*if (hiA[i] < loA[i]) chk = 0;*/
}
/* make copies of loA and hiA since pnga_patch_intersect destroys
original versions */
for (j=0; j<andim; j++) {
lo[j] = loA[j];
/*hi[j] = hiA[j];*/
}
if(pnga_patch_intersect(alo, ahi, loA, hiA, andim)){
pnga_access_block_grid_ptr(g_A, index, &A_ptr, ldA);
pnga_access_block_grid_ptr(g_B, index, &B_ptr, ldB);
/* evaluate offsets for system */
offset = 0;
last = andim-1;
jtot = 1;
for (j=0; j<last; j++) {
offset += (loA[j] - lo[j])*jtot;
jtot *= ldA[j];
}
offset += (loA[last]-lo[last])*jtot;
/* offset pointers by correct amount */
switch (atype){
case C_INT:
A_ptr = (void*)((int*)(A_ptr) + offset);
B_ptr = (void*)((int*)(B_ptr) + offset);
break;
case C_DCPL:
A_ptr = (void*)((DoubleComplex*)(A_ptr) + offset);
B_ptr = (void*)((DoubleComplex*)(B_ptr) + offset);
break;
case C_SCPL:
A_ptr = (void*)((SingleComplex*)(A_ptr) + offset);
B_ptr = (void*)((SingleComplex*)(B_ptr) + offset);
break;
case C_DBL:
A_ptr = (void*)((double*)(A_ptr) + offset);
B_ptr = (void*)((double*)(B_ptr) + offset);
break;
case C_FLOAT:
A_ptr = (void*)((float*)(A_ptr) + offset);
B_ptr = (void*)((float*)(B_ptr) + offset);
break;
case C_LONG:
A_ptr = (void*)((long*)(A_ptr) + offset);
B_ptr = (void*)((long*)(B_ptr) + offset);
break;
case C_LONGLONG:
A_ptr = (void*)((long long*)(A_ptr) + offset);
B_ptr = (void*)((long long*)(B_ptr) + offset);
break;
}
snga_dot_local_patch(atype, andim, loA, hiA, ldA, A_ptr, B_ptr,
&alen, retval);
/* release access to the data */
pnga_release_block_grid(g_A, index);
pnga_release_block_grid(g_B, index);
}
/* increment index to get next block on processor */
index[0] += topology[0];
for (i = 0; i < andim; i++) {
if (index[i] >= blocks[i] && i<andim-1) {
index[i] = proc_index[i];
index[i+1] += topology[i+1];
}
}
}
}
}
#endif
}
/*convert from C data type to ARMCI type */
switch(atype) {
case C_FLOAT: ctype=ARMCI_FLOAT; break;
case C_DBL: ctype=ARMCI_DOUBLE; break;
case C_INT: ctype=ARMCI_INT; break;
case C_LONG: ctype=ARMCI_LONG; break;
case C_LONGLONG: ctype=ARMCI_LONG_LONG; break;
case C_DCPL: ctype=ARMCI_DOUBLE; break;
case C_SCPL: ctype=ARMCI_FLOAT; break;
default: pnga_error("pnga_dot_patch: type not supported",atype);
}
if (pnga_is_mirrored(g_a) && pnga_is_mirrored(g_b)) {
armci_msg_gop_scope(SCOPE_NODE,retval,alen,"+",ctype);
} else {
if (a_grp == -1) {
armci_msg_gop_scope(SCOPE_ALL,retval,alen,"+",ctype);
#ifdef MSG_COMMS_MPI
} else {
armci_msg_group_gop_scope(SCOPE_ALL,retval,alen,"+",ctype,
ga_get_armci_group_((int)a_grp));
#endif
}
}
if(temp_created) pnga_destroy(g_B);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x8b8, %rsp # imm = 0x8B8
movq %r9, 0x10(%rsp)
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, 0x28(%rsp)
movq %rdi, %r15
xorl %eax, %eax
movq %rax, 0x78(%rsp)
movq %rax, 0x58(%rsp)
movq %rax, 0x70(%rsp)
movq %rax, 0x18(%rsp)
movq %rax, 0x48(%rsp)
movq %r8, 0x40(%rsp)
movq %r8, 0x38(%rsp)
movq %rax, 0x20(%rsp)
movq %rax, 0x30(%rsp)
xorl %eax, %eax
callq 0x685c6
xorl %eax, %eax
callq 0x68602
leaq 0xc35e5(%rip), %rax # 0xd7160
cmpl $0x0, (%rax)
movl $0x1, %ecx
movl %ecx, (%rax)
leaq 0xc35d8(%rip), %rax # 0xd7164
movl %ecx, (%rax)
je 0x13b97
xorl %eax, %eax
callq 0x6983a
movq %r15, %rdi
callq 0x6071a
movq %rax, %rbp
movq 0x40(%rsp), %rdi
callq 0x6071a
cmpq %rax, %rbp
je 0x13bbf
leaq 0x9e83f(%rip), %rdi # 0xb23f7
xorl %esi, %esi
callq 0x18f07
movq %rbp, %rdi
callq 0x62fe1
movq %rax, 0x60(%rsp)
leaq 0x58(%rsp), %rbx
leaq 0x18(%rsp), %rdx
leaq 0x280(%rsp), %rcx
movq %r15, %rdi
movq %rbx, %rsi
callq 0x6688f
leaq 0x70(%rsp), %r14
leaq 0x48(%rsp), %rdx
leaq 0x240(%rsp), %rcx
movq 0x40(%rsp), %rdi
movq %r14, %rsi
callq 0x6688f
movq (%rbx), %rax
cmpq (%r14), %rax
je 0x13c1e
leaq 0x9e922(%rip), %rdi # 0xb2539
xorl %esi, %esi
callq 0x18f07
cmpq $0x0, 0x18(%rsp)
jle 0x13c5b
xorl %r14d, %r14d
leaq 0x9facc(%rip), %rbx # 0xb36fc
cmpq $0x0, (%r13,%r14,8)
jle 0x13c46
movq (%r12,%r14,8), %rax
cmpq 0x280(%rsp,%r14,8), %rax
jle 0x13c51
movq %rbx, %rdi
movq %r15, %rsi
callq 0x18f07
incq %r14
cmpq 0x18(%rsp), %r14
jl 0x13c30
movq %rbp, 0x68(%rsp)
movq %r15, 0x50(%rsp)
movq 0x8f8(%rsp), %r15
movq 0x8f0(%rsp), %rbp
movq 0x48(%rsp), %rax
testq %rax, %rax
jle 0x13cb9
xorl %r14d, %r14d
leaq 0x9fa8f(%rip), %rbx # 0xb3718
cmpq $0x0, (%rbp,%r14,8)
jle 0x13c9f
movq (%r15,%r14,8), %rax
cmpq 0x240(%rsp,%r14,8), %rax
jle 0x13cac
movq %rbx, %rdi
movq 0x40(%rsp), %rsi
callq 0x18f07
incq %r14
movq 0x48(%rsp), %rax
cmpq %rax, %r14
jl 0x13c89
movq 0x18(%rsp), %rsi
movl $0x1, %ecx
movl $0x1, %edx
testq %rsi, %rsi
jle 0x13ce7
xorl %edi, %edi
movq (%r12,%rdi,8), %r8
subq (%r13,%rdi,8), %r8
incq %r8
imulq %r8, %rdx
incq %rdi
cmpq %rdi, %rsi
jne 0x13ccf
testq %rax, %rax
jle 0x13d0b
movl $0x1, %ecx
xorl %esi, %esi
movq (%r15,%rsi,8), %rdi
subq (%rbp,%rsi,8), %rdi
incq %rdi
imulq %rdi, %rcx
incq %rsi
cmpq %rsi, %rax
jne 0x13cf3
cmpq %rcx, %rdx
je 0x13d1e
leaq 0xa0126(%rip), %rdi # 0xb3e3d
xorl %esi, %esi
callq 0x18f07
movq 0x28(%rsp), %rax
movb (%rax), %al
andb $-0x21, %al
cmpb $0x4e, %al
setne %bl
movq 0x10(%rsp), %rax
movb (%rax), %al
andb $-0x21, %al
cmpb $0x4e, %al
setne %r14b
sete %al
xorb %bl, %al
movb %al, 0xf(%rsp)
movl $0x6e, %eax
movl $0x74, %ecx
cmovnel %eax, %ecx
movb %cl, 0xe(%rsp)
movq 0x50(%rsp), %rdi
callq 0x693e7
movq %rax, %r15
movq 0x40(%rsp), %rdi
callq 0x693e7
movq %rax, %rdx
movq %r15, 0x28(%rsp)
testq %rax, %r15
setns %al
orb %bl, %r14b
andb %al, %r14b
cmpb $0x1, %r14b
jne 0x13d9a
leaq 0x9ec7c(%rip), %rdi # 0xb2a09
xorl %esi, %esi
movq %rdx, %rbx
callq 0x18f07
movq %rbx, %rdx
movq 0x58(%rsp), %rsi
leaq -0x3e9(%rsi), %rax
cmpq $0xf, %rax
ja 0x13de5
leaq 0x9e8a1(%rip), %rcx # 0xb2654
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0x900(%rsp), %rax
movq $0x0, (%rax)
jmp 0x13ddb
movq 0x900(%rsp), %rax
movl $0x0, (%rax)
movl $0x1, 0x10(%rsp)
jmp 0x13e28
leaq 0x9ec4c(%rip), %rdi # 0xb2a38
movq %rdx, %rbx
callq 0x18f07
movq %rbx, %rdx
movl $0x0, 0x10(%rsp)
jmp 0x13e28
movq 0x900(%rsp), %rax
movq $0x0, (%rax)
jmp 0x13e20
xorps %xmm0, %xmm0
movq 0x900(%rsp), %rax
movups %xmm0, (%rax)
movl $0x2, 0x10(%rsp)
movq 0x28(%rsp), %rax
movq 0x8f8(%rsp), %r15
testq %rdx, %rax
jns 0x13f1c
leaq 0x80(%rsp), %rdx
leaq 0xc0(%rsp), %rcx
movq 0x50(%rsp), %rdi
movq 0x60(%rsp), %rbx
movq %rbx, %rsi
callq 0x5f51f
movq 0x38(%rsp), %rdi
leaq 0x140(%rsp), %rdx
leaq 0x100(%rsp), %rcx
movq %rbx, %rsi
callq 0x5f51f
movq 0x18(%rsp), %r14
movq 0x48(%rsp), %rbx
movq %r14, %rdi
leaq 0x80(%rsp), %rsi
leaq 0xc0(%rsp), %rdx
movq %rbx, %rcx
leaq 0x140(%rsp), %r8
leaq 0x100(%rsp), %r9
callq 0x12578
testq %rax, %rax
je 0x13ed8
movq %r14, %rdi
movq %r13, %rsi
movq %r12, %rdx
movq %rbx, %rcx
movq %rbp, %r8
movq %r15, %r9
callq 0x12578
movl $0x1, %ecx
testq %rax, %rax
jne 0x13eda
xorl %ecx, %ecx
leaq 0x78(%rsp), %rbx
movq %rcx, (%rbx)
movl $0x3f2, %edi # imm = 0x3F2
callq 0x99e0
leaq 0x9d9dc(%rip), %rcx # 0xb18cf
movl $0x1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq 0x781a5
cmpq $0x0, (%rbx)
setne %al
testb %al, 0xf(%rsp)
je 0x14134
xorl %r15d, %r15d
jmp 0x141b3
leaq 0x9ddbe(%rip), %rdx # 0xb1ce1
leaq 0x38(%rsp), %rsi
movq 0x50(%rsp), %r14
movq %r14, %rdi
callq 0x653c7
testq %rax, %rax
jne 0x13f48
leaq 0x9e17a(%rip), %rdi # 0xb20bb
xorl %esi, %esi
callq 0x18f07
movq 0x38(%rsp), %r8
subq $0x8, %rsp
leaq 0x16(%rsp), %rdi
movq 0x48(%rsp), %rsi
movq %rbp, %rdx
movq %r15, %rcx
movq %r13, %r9
pushq %r12
callq 0x125de
addq $0x10, %rsp
leaq 0x5b8(%rsp), %rbx
movq %r14, %rdi
movq %rbx, %rsi
callq 0x1e308
movq 0x38(%rsp), %rdi
leaq 0x2b8(%rsp), %rsi
callq 0x1e308
leaq 0x80(%rsp), %rsi
leaq 0xc0(%rsp), %rdx
leaq 0x20(%rsp), %rcx
leaq 0x180(%rsp), %r8
movq %rbx, %rdi
callq 0x1e731
movl $0x1, %r15d
testl %eax, %eax
je 0x142d2
leaq 0x80(%rsp), %rbp
leaq 0xc0(%rsp), %rbx
leaq 0x180(%rsp), %r14
leaq 0x2b8(%rsp), %rdi
leaq 0x140(%rsp), %rsi
leaq 0x100(%rsp), %rdx
leaq 0x30(%rsp), %rcx
leaq 0x200(%rsp), %r8
callq 0x1e731
movq 0x18(%rsp), %r15
testq %r15, %r15
jle 0x1402b
leaq (,%r15,8), %rdx
leaq 0x1c0(%rsp), %rdi
movq %rbp, %rsi
callq 0x3220
movq %r13, %rdi
movq %r12, %rsi
movq %rbp, %rdx
movq %rbx, %rcx
movq %r15, %r8
callq 0x124f0
testq %rax, %rax
je 0x14101
cmpq $0x2, %r15
jl 0x14085
leaq -0x1(%r15), %rdx
movl $0x1, %eax
xorl %ecx, %ecx
xorl %esi, %esi
movq 0x80(%rsp,%rsi,8), %rdi
subq 0x1c0(%rsp,%rsi,8), %rdi
imulq %rax, %rdi
addq %rdi, %rcx
imulq 0x180(%rsp,%rsi,8), %rax
incq %rsi
cmpq %rsi, %rdx
jne 0x1405b
jmp 0x1408c
movl $0x1, %eax
xorl %ecx, %ecx
movq 0x58(%rsp), %rdi
leaq -0x3e9(%rdi), %rsi
cmpq $0xf, %rsi
ja 0x140dc
movq 0x78(%rsp,%r15,8), %rdx
subq 0x1b8(%rsp,%r15,8), %rdx
imulq %rax, %rdx
addq %rcx, %rdx
leaq 0x9e5db(%rip), %rcx # 0xb2694
movslq (%rcx,%rsi,4), %rax
addq %rcx, %rax
jmpq *%rax
shlq $0x3, %rdx
jmp 0x140d2
shlq $0x2, %rdx
jmp 0x140d2
shlq $0x4, %rdx
addq %rdx, 0x20(%rsp)
addq %rdx, 0x30(%rsp)
movq 0x20(%rsp), %r9
movq %r15, %rsi
movq %rbp, %rdx
movq %rbx, %rcx
movq %r14, %r8
pushq 0x900(%rsp)
pushq 0x38(%rsp)
callq 0x143af
addq $0x10, %rsp
leaq 0x5b8(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
leaq 0x20(%rsp), %rcx
movq %r14, %r8
callq 0x1e731
testl %eax, %eax
jne 0x13fdf
movq 0x50(%rsp), %rbp
movl $0x1, %r15d
jmp 0x142d5
leaq 0x9dba6(%rip), %rdx # 0xb1ce1
leaq 0x38(%rsp), %rsi
movq 0x50(%rsp), %rdi
callq 0x653c7
testq %rax, %rax
jne 0x1415d
leaq 0x9df65(%rip), %rdi # 0xb20bb
xorl %esi, %esi
callq 0x18f07
movq 0x38(%rsp), %r8
subq $0x8, %rsp
leaq 0x16(%rsp), %rdi
movq 0x48(%rsp), %rsi
movq %rbp, %rdx
movq %r15, %rcx
movq %r13, %r9
pushq %r12
callq 0x125de
addq $0x10, %rsp
movq 0x18(%rsp), %rax
movq %rax, 0x48(%rsp)
movq 0x38(%rsp), %rdi
leaq 0x140(%rsp), %rdx
leaq 0x100(%rsp), %rcx
movq 0x60(%rsp), %rsi
callq 0x5f51f
movl $0x1, %r15d
movq 0x18(%rsp), %rdi
movq 0x48(%rsp), %rcx
leaq 0x80(%rsp), %rsi
leaq 0xc0(%rsp), %rdx
leaq 0x140(%rsp), %r8
leaq 0x100(%rsp), %r9
callq 0x12578
testq %rax, %rax
movq 0x50(%rsp), %rbp
jne 0x141fa
leaq 0x9e86e(%rip), %rdi # 0xb2a61
xorl %esi, %esi
callq 0x18f07
movq 0x48(%rsp), %rax
cmpq %rax, 0x18(%rsp)
jle 0x1420b
movq %rax, 0x18(%rsp)
movq 0x18(%rsp), %r8
leaq 0x80(%rsp), %rdx
leaq 0xc0(%rsp), %rcx
movq %r13, %rdi
movq %r12, %rsi
callq 0x124f0
testq %rax, %rax
je 0x142d5
leaq 0x80(%rsp), %rbx
leaq 0xc0(%rsp), %r14
leaq 0x20(%rsp), %r12
leaq 0x180(%rsp), %r8
movq %rbp, %rdi
movq %rbx, %rsi
movq %r14, %rdx
movq %r12, %rcx
callq 0x6b58f
movq 0x38(%rsp), %rdi
leaq 0x30(%rsp), %r13
leaq 0x200(%rsp), %r8
movq %rbx, %rsi
movq %r14, %rdx
movq %r13, %rcx
callq 0x6b58f
movq 0x58(%rsp), %rdi
movq 0x18(%rsp), %rsi
movq (%r12), %r9
movq %rbx, %rdx
movq %r14, %rcx
leaq 0x180(%rsp), %r8
pushq 0x900(%rsp)
pushq (%r13)
callq 0x143af
addq $0x10, %rsp
movq %rbp, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq 0x6dcc8
movq 0x38(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq 0x6dcc8
jmp 0x142d5
movq %r14, %rbp
movq 0x58(%rsp), %rsi
leaq -0x3e9(%rsi), %rax
cmpq $0x10, %rax
jae 0x14301
movl $0x806f, %ecx # imm = 0x806F
btl %eax, %ecx
jae 0x14301
leaq 0x9e61c(%rip), %rax # 0xb2914
movl -0xfa4(%rax,%rsi,4), %ebx
jmp 0x1430f
leaq 0x9e76c(%rip), %rdi # 0xb2a74
callq 0x18f07
xorl %ebx, %ebx
movq %rbp, %rdi
callq 0x5de62
testq %rax, %rax
je 0x14339
movq 0x40(%rsp), %rdi
callq 0x5de62
testq %rax, %rax
je 0x14339
leaq 0x9e158(%rip), %rcx # 0xb248a
movl $0x151, %edi # imm = 0x151
jmp 0x1437a
movq 0x68(%rsp), %rdi
cmpq $-0x1, %rdi
je 0x1436e
callq 0x60285
leaq 0x9e13a(%rip), %rcx # 0xb248a
movl $0x14d, %edi # imm = 0x14D
movq 0x900(%rsp), %rsi
movl 0x10(%rsp), %edx
movl %ebx, %r8d
movq %rax, %r9
callq 0x5a21f
jmp 0x1438e
leaq 0x9e115(%rip), %rcx # 0xb248a
movl $0x14d, %edi # imm = 0x14D
movq 0x900(%rsp), %rsi
movl 0x10(%rsp), %edx
movl %ebx, %r8d
callq 0x59d9a
testq %r15, %r15
je 0x1439d
movq 0x38(%rsp), %rdi
callq 0x63281
addq $0x8b8, %rsp # imm = 0x8B8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/GlobalArrays[P]ga/global/src/global.npatch.c
|
pnga_print_patch_file2d
|
void pnga_print_patch_file2d(file, g_a, ilo, ihi, jlo, jhi, pretty)
FILE *file;
Integer g_a, ilo, ihi, jlo, jhi, pretty;
/*
Pretty = 0 ... spew output out with no formatting
Pretty = 1 ... format output so that it is readable
*/
{
#define BUFSIZE 6
#define FLEN 80
Integer i, j,jj, dim1, dim2, type, jmax, ld=1, bufsize ;
Integer a_grp;
int ibuf[BUFSIZE];
DoublePrecision dbuf[BUFSIZE];
float fbuf[BUFSIZE];
long lbuf[BUFSIZE];
long long llbuf[BUFSIZE];
char *name;
Integer ndim, dims[2];
Integer lo[2], hi[2];
a_grp = pnga_get_pgroup(g_a);
pnga_pgroup_sync(a_grp);
pnga_check_handle(g_a, "ga_print");
if(pnga_pgroup_nodeid(a_grp) == 0){
pnga_inquire(g_a, &type, &ndim, dims);
dim1 = dims[0];
dim2 = dims[1];
/* name[FLEN-1]='\0';*/
pnga_inquire_name(g_a, &name);
if (ilo <= 0 || ihi > dim1 || jlo <= 0 || jhi > dim2){
fprintf(stderr,"%ld %ld %ld %ld dims: [%ld,%ld]\n",
(long)ilo,(long)ihi, (long)jlo,(long)jhi,
(long)dim1, (long)dim2);
pnga_error(" ga_print: indices out of range ", g_a);
}
fprintf(file,"\n global array: %s[%ld:%ld,%ld:%ld], handle: %d \n",
name, (long)ilo, (long)ihi, (long)jlo, (long)jhi, (int)g_a);
bufsize = (type==C_DCPL)? BUFSIZE/2 : BUFSIZE;
bufsize = (type==C_SCPL)? BUFSIZE/2 : BUFSIZE;
if (!pretty) {
for (i=ilo; i <ihi+1; i++){
for (j=jlo; j <jhi+1; j+=bufsize){
jmax = GA_MIN(j+bufsize-1,jhi);
lo[0] = i;
lo[1] = j;
hi[0] = i;
hi[1] = jmax;
switch(type){
case C_INT:
pnga_get(g_a, lo, hi, ibuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %8d",ibuf[jj]);
break;
case C_DBL:
pnga_get(g_a, lo, hi, dbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %11.5f",dbuf[jj]);
break;
case C_DCPL:
pnga_get(g_a, lo, hi, dbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj+=2)
fprintf(file," %11.5f,%11.5f",dbuf[jj], dbuf[jj+1]);
break;
case C_SCPL:
pnga_get(g_a, lo, hi, dbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj+=2)
fprintf(file," %11.5f,%11.5f",dbuf[jj], dbuf[jj+1]);
break;
case C_FLOAT:
pnga_get(g_a, lo, hi, fbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %11.5f",fbuf[jj]);
break;
case C_LONG:
pnga_get(g_a, lo, hi, lbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %8ld",lbuf[jj]);
break;
case C_LONGLONG:
pnga_get(g_a, lo, hi, llbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %8lld",llbuf[jj]);
break;
default: pnga_error("ga_print: wrong type",0);
}
}
fprintf(file,"\n");
}
fflush(file);
} else {
for (j=jlo; j<jhi+1; j+=bufsize){
jmax = GA_MIN(j+bufsize-1,jhi);
fprintf(file, "\n"); fprintf(file, "\n");
/* Print out column headers */
fprintf(file, " ");
switch(type){
case C_INT:
for (jj=j; jj<=jmax; jj++) fprintf(file, "%6ld ", (long)jj);
fprintf(file,"\n ");
for (jj=j; jj<=jmax; jj++) fprintf(file," -------");
break;
case C_LONG:
for (jj=j; jj<=jmax; jj++) fprintf(file, "%6ld ", (long)jj);
fprintf(file,"\n ");
for (jj=j; jj<=jmax; jj++) fprintf(file," -------");
break;
case C_LONGLONG:
for (jj=j; jj<=jmax; jj++) fprintf(file, "%6ld ", (long)jj);
fprintf(file,"\n ");
for (jj=j; jj<=jmax; jj++) fprintf(file," -------");
break;
case C_DCPL:
for (jj=j; jj<=jmax; jj++) fprintf(file,"%20ld ", (long)jj);
fprintf(file,"\n ");
for (jj=j; jj<=2*jmax; jj++) fprintf(file," -----------");
break;
case C_SCPL:
for (jj=j; jj<=jmax; jj++) fprintf(file,"%20ld ", (long)jj);
fprintf(file,"\n ");
for (jj=j; jj<=2*jmax; jj++) fprintf(file," -----------");
break;
case C_DBL:
for (jj=j; jj<=jmax; jj++) fprintf(file,"%8ld ", (long)jj);
fprintf(file,"\n ");
for (jj=j; jj<=jmax; jj++) fprintf(file," -----------");
case C_FLOAT:
for (jj=j; jj<=jmax; jj++) fprintf(file,"%8ld ", (long)jj);
fprintf(file,"\n ");
for (jj=j; jj<=jmax; jj++) fprintf(file," -----------");
}
fprintf(file,"\n");
for(i=ilo; i <ihi+1; i++){
fprintf(file,"%4ld ",(long)i);
lo[0] = i;
lo[1] = i;
hi[0] = j;
hi[1] = jmax;
switch(type){
case C_INT:
pnga_get(g_a, lo, hi, ibuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %8d",ibuf[jj]);
break;
case C_LONG:
pnga_get(g_a, lo, hi, lbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %8ld",lbuf[jj]);
break;
case C_LONGLONG:
pnga_get(g_a, lo, hi, llbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %8lld",llbuf[jj]);
break;
case C_DBL:
pnga_get(g_a, lo, hi, dbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %11.5f",dbuf[jj]);
break;
case C_FLOAT:
pnga_get(g_a, lo, hi, dbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj++)
fprintf(file," %11.5f",fbuf[jj]);
break;
case C_DCPL:
pnga_get(g_a, lo, hi, dbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj+=2)
fprintf(file," %11.5f,%11.5f",dbuf[jj], dbuf[jj+1]);
break;
case C_SCPL:
pnga_get(g_a, lo, hi, dbuf, &ld);
for(jj=0; jj<(jmax-j+1); jj+=2)
fprintf(file," %11.5f,%11.5f",dbuf[jj], dbuf[jj+1]);
break;
default: pnga_error("ga_print: wrong type",0);
}
fprintf(file,"\n");
}
fflush(file);
}
}
}
pnga_pgroup_sync(a_grp);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x178, %rsp # imm = 0x178
movq %r9, %rbx
movq %r8, %r14
movq %rcx, 0x68(%rsp)
movq %rdx, 0x48(%rsp)
movq %rsi, %r12
movq %rdi, %r13
movq $0x1, 0x18(%rsp)
movq %rsi, %rdi
callq 0x6071a
movq %rax, %r15
movq %rax, %rdi
callq 0x6979c
leaq 0x9ae94(%rip), %rsi # 0xb3182
movq %r12, 0x8(%rsp)
movq %r12, %rdi
callq 0x5d393
movq %r15, 0xb0(%rsp)
movq %r15, %rdi
callq 0x62fe1
testq %rax, %rax
je 0x1832f
movq 0xb0(%rsp), %rdi
callq 0x6979c
addq $0x178, %rsp # imm = 0x178
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq %rbx, %r8
movq %r14, 0x10(%rsp)
movq 0x1b0(%rsp), %rbx
leaq 0x70(%rsp), %rsi
leaq 0xf8(%rsp), %rdx
leaq 0x160(%rsp), %r15
movq 0x8(%rsp), %r12
movq %r12, %rdi
movq %r15, %rcx
movq %r8, 0x50(%rsp)
callq 0x6688f
movq (%r15), %r14
movq 0x8(%r15), %r15
leaq 0xb8(%rsp), %rsi
movq %r12, %rdi
callq 0x66a33
movq 0x50(%rsp), %r10
movq 0x48(%rsp), %rbp
testq %rbp, %rbp
movq 0x68(%rsp), %r12
jle 0x18ebe
cmpq $0x0, 0x10(%rsp)
jle 0x18ebe
cmpq %r12, %r14
jl 0x18ebe
cmpq %r10, %r15
jl 0x18ebe
movq 0xb8(%rsp), %rdx
leaq 0x9a9ed(%rip), %rsi # 0xb2db2
movq %r13, %rdi
movq %rbp, %rcx
movq %r12, %r8
movq 0x10(%rsp), %r15
movq %r15, %r9
xorl %eax, %eax
pushq 0x8(%rsp)
pushq %r10
movq %r10, %r14
callq 0x3440
addq $0x10, %rsp
xorl %eax, %eax
cmpq $0x3ee, 0x70(%rsp) # imm = 0x3EE
setne %al
leaq (%rax,%rax,2), %rax
addq $0x3, %rax
movq %rax, 0x60(%rsp)
testq %rbx, %rbx
je 0x18b6b
cmpq %r14, %r15
movq 0x60(%rsp), %rbx
jg 0x18310
movq %r14, %rax
leaq (%r15,%rbx), %r14
decq %r14
movl $0x1, %ecx
subq %r15, %rcx
movq %rcx, 0x58(%rsp)
leaq -0x1(%r15), %rcx
movq %rcx, 0x40(%rsp)
cmpq %r14, %rax
movq %r14, 0x78(%rsp)
cmovlq %rax, %r14
movq %r15, 0x10(%rsp)
leaq (%r15,%rbx), %r12
decq %r12
cmpq %rax, %r12
cmovgeq %rax, %r12
movl $0xa, %edi
movq %r13, %rsi
callq 0x3380
movl $0xa, %edi
movq %r13, %rsi
callq 0x3380
movl $0x6, %esi
movl $0x1, %edx
leaq 0x9a9a5(%rip), %rdi # 0xb2e2b
movq %r13, %rcx
callq 0x3570
movq 0x70(%rsp), %rax
movq $-0x3e9, %rcx # imm = 0xFC17
addq %rcx, %rax
cmpq $0xf, %rax
ja 0x1882a
leaq 0x9a61e(%rip), %rcx # 0xb2acc
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0x10(%rsp), %rbx
cmpq %rbx, %r12
leaq 0x9a95d(%rip), %r15 # 0xb2e23
jl 0x184e7
movq %rbx, %rbp
movq %r13, %rdi
movq %r15, %rsi
movq %rbp, %rdx
xorl %eax, %eax
callq 0x3440
leaq 0x1(%rbp), %rax
cmpq %r12, %rbp
movq %rax, %rbp
jl 0x184cb
movl $0x7, %esi
movl $0x1, %edx
leaq 0x9a932(%rip), %rdi # 0xb2e2a
movq %r13, %rcx
callq 0x3570
cmpq %rbx, %r12
leaq 0x9a928(%rip), %r15 # 0xb2e32
jl 0x1882a
movq 0x40(%rsp), %rbx
movl $0x8, %esi
movl $0x1, %edx
movq %r15, %rdi
movq %r13, %rcx
callq 0x3570
incq %rbx
cmpq %r12, %rbx
jl 0x18515
jmp 0x1882a
movq 0x10(%rsp), %r15
movq %r15, %rbp
cmpq %r15, %r12
leaq 0x9a8f2(%rip), %rbx # 0xb2e3b
jl 0x18567
movq %r13, %rdi
movq %rbx, %rsi
movq %rbp, %rdx
xorl %eax, %eax
callq 0x3440
leaq 0x1(%rbp), %rax
cmpq %r12, %rbp
movq %rax, %rbp
jl 0x1854b
movl $0x7, %esi
movl $0x1, %edx
leaq 0x9a8b2(%rip), %rdi # 0xb2e2a
movq %r13, %rcx
callq 0x3570
leaq (%r12,%r12), %rbx
cmpq %rbx, %r15
leaq 0x9a8b7(%rip), %rbp # 0xb2e45
jg 0x1882a
movq 0x40(%rsp), %r15
movl $0xc, %esi
movl $0x1, %edx
movq %rbp, %rdi
movq %r13, %rcx
callq 0x3570
incq %r15
cmpq %rbx, %r15
jl 0x18599
jmp 0x1882a
movq 0x10(%rsp), %rbx
movq %rbx, %rbp
cmpq %rbx, %r12
leaq 0x9a856(%rip), %r15 # 0xb2e23
jl 0x185eb
movq %r13, %rdi
movq %r15, %rsi
movq %rbp, %rdx
xorl %eax, %eax
callq 0x3440
leaq 0x1(%rbp), %rax
cmpq %r12, %rbp
movq %rax, %rbp
jl 0x185cf
movl $0x7, %esi
movl $0x1, %edx
leaq 0x9a82e(%rip), %rdi # 0xb2e2a
movq %r13, %rcx
callq 0x3570
cmpq %rbx, %r12
leaq 0x9a824(%rip), %r15 # 0xb2e32
jl 0x1882a
movq 0x40(%rsp), %rbx
movl $0x8, %esi
movl $0x1, %edx
movq %r15, %rdi
movq %r13, %rcx
callq 0x3570
incq %rbx
cmpq %r12, %rbx
jl 0x18619
jmp 0x1882a
movq 0x10(%rsp), %rbx
movq %rbx, %rbp
cmpq %rbx, %r12
leaq 0x9a7d6(%rip), %r15 # 0xb2e23
jl 0x1866b
movq %r13, %rdi
movq %r15, %rsi
movq %rbp, %rdx
xorl %eax, %eax
callq 0x3440
leaq 0x1(%rbp), %rax
cmpq %r12, %rbp
movq %rax, %rbp
jl 0x1864f
movl $0x7, %esi
movl $0x1, %edx
leaq 0x9a7ae(%rip), %rdi # 0xb2e2a
movq %r13, %rcx
callq 0x3570
cmpq %rbx, %r12
leaq 0x9a7a4(%rip), %r15 # 0xb2e32
jl 0x1882a
movq 0x40(%rsp), %rbx
movl $0x8, %esi
movl $0x1, %edx
movq %r15, %rdi
movq %r13, %rcx
callq 0x3570
incq %rbx
cmpq %r12, %rbx
jl 0x18699
jmp 0x1882a
movq 0x10(%rsp), %rbx
movq %rbx, %rbp
cmpq %rbx, %r12
leaq 0x9a785(%rip), %r15 # 0xb2e52
jl 0x186eb
movq %r13, %rdi
movq %r15, %rsi
movq %rbp, %rdx
xorl %eax, %eax
callq 0x3440
leaq 0x1(%rbp), %rax
cmpq %r12, %rbp
movq %rax, %rbp
jl 0x186cf
movl $0x7, %esi
movl $0x1, %edx
leaq 0x9a72e(%rip), %rdi # 0xb2e2a
movq %r13, %rcx
callq 0x3570
cmpq %rbx, %r12
leaq 0x9a737(%rip), %r15 # 0xb2e45
jl 0x18732
movq 0x40(%rsp), %rbx
movl $0xc, %esi
movl $0x1, %edx
movq %r15, %rdi
movq %r13, %rcx
callq 0x3570
incq %rbx
cmpq %r12, %rbx
jl 0x18715
movq 0x10(%rsp), %rbx
cmpq %rbx, %r12
leaq 0x9a711(%rip), %r15 # 0xb2e52
jl 0x18762
movq %rbx, %rbp
movq %r13, %rdi
movq %r15, %rsi
movq %rbp, %rdx
xorl %eax, %eax
callq 0x3440
leaq 0x1(%rbp), %rax
cmpq %r12, %rbp
movq %rax, %rbp
jl 0x18746
movl $0x7, %esi
movl $0x1, %edx
leaq 0x9a6b7(%rip), %rdi # 0xb2e2a
movq %r13, %rcx
callq 0x3570
cmpq %rbx, %r12
leaq 0x9a6c0(%rip), %r15 # 0xb2e45
jl 0x1882a
movq 0x40(%rsp), %rbx
movl $0xc, %esi
movl $0x1, %edx
movq %r15, %rdi
movq %r13, %rcx
callq 0x3570
incq %rbx
cmpq %r12, %rbx
jl 0x18790
jmp 0x1882a
movq 0x10(%rsp), %r15
movq %r15, %rbp
cmpq %r15, %r12
leaq 0x9a67a(%rip), %rbx # 0xb2e3b
jl 0x187df
movq %r13, %rdi
movq %rbx, %rsi
movq %rbp, %rdx
xorl %eax, %eax
callq 0x3440
leaq 0x1(%rbp), %rax
cmpq %r12, %rbp
movq %rax, %rbp
jl 0x187c3
movl $0x7, %esi
movl $0x1, %edx
leaq 0x9a63a(%rip), %rdi # 0xb2e2a
movq %r13, %rcx
callq 0x3570
leaq (%r12,%r12), %rbx
cmpq %rbx, %r15
leaq 0x9a63f(%rip), %rbp # 0xb2e45
jg 0x1882a
movq 0x40(%rsp), %r15
movl $0xc, %esi
movl $0x1, %edx
movq %rbp, %rdi
movq %r13, %rcx
callq 0x3570
incq %r15
cmpq %rbx, %r15
jl 0x1880d
movl $0xa, %edi
movq %r13, %rsi
callq 0x3380
movq 0x48(%rsp), %rax
cmpq 0x68(%rsp), %rax
movq 0x10(%rsp), %r15
jg 0x18b36
addq 0x58(%rsp), %r14
movq %r12, %rbx
subq %r15, %rbx
movq 0x48(%rsp), %rbp
movq %r13, %rdi
leaq 0x9a5f5(%rip), %rsi # 0xb2e5b
movq %rbp, %rdx
xorl %eax, %eax
callq 0x3440
movq %rbp, 0x30(%rsp)
movq %rbp, 0x38(%rsp)
movq %r15, 0x20(%rsp)
movq %r12, 0x28(%rsp)
movq 0x70(%rsp), %rax
movq $-0x3e9, %rcx # imm = 0xFC17
addq %rcx, %rax
cmpq $0xf, %rax
ja 0x188fc
leaq 0x9a26c(%rip), %rcx # 0xb2b0c
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0xc0(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %r15, %r12
jl 0x18b12
xorl %r15d, %r15d
movl 0xc0(%rsp,%r15,4), %edx
movq %r13, %rdi
leaq 0x9a4fd(%rip), %rsi # 0xb2de5
xorl %eax, %eax
callq 0x3440
incq %r15
cmpq %r15, %r14
jne 0x188d6
jmp 0x18b12
leaq 0x9a50b(%rip), %rdi # 0xb2e0e
xorl %esi, %esi
callq 0x18f07
jmp 0x18b12
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x80(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
testq %rbx, %rbx
js 0x18b12
xorl %r15d, %r15d
movsd 0x80(%rsp,%r15,8), %xmm0
movsd 0x88(%rsp,%r15,8), %xmm1
movq %r13, %rdi
leaq 0x9a498(%rip), %rsi # 0xb2df2
movb $0x2, %al
callq 0x3440
addq $0x2, %r15
cmpq %rbx, %r15
jle 0x1893c
jmp 0x18b12
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x130(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %r15, %r12
jl 0x18b12
xorl %r15d, %r15d
movq 0x130(%rsp,%r15,8), %rdx
movq %r13, %rdi
leaq 0x9a453(%rip), %rsi # 0xb2e01
xorl %eax, %eax
callq 0x3440
incq %r15
cmpq %r15, %r14
jne 0x1899c
jmp 0x18b12
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x100(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %r15, %r12
jl 0x18b12
xorl %r15d, %r15d
movq 0x100(%rsp,%r15,8), %rdx
movq %r13, %rdi
leaq 0x9a406(%rip), %rsi # 0xb2e07
xorl %eax, %eax
callq 0x3440
incq %r15
cmpq %r15, %r14
jne 0x189ef
jmp 0x18b12
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x80(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %r15, %r12
jl 0x18b12
xorl %r15d, %r15d
xorps %xmm0, %xmm0
cvtss2sd 0xe0(%rsp,%r15,4), %xmm0
movq %r13, %rdi
leaq 0x9a391(%rip), %rsi # 0xb2dea
movb $0x1, %al
callq 0x3440
incq %r15
cmpq %r15, %r14
jne 0x18a42
jmp 0x18b12
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x80(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %r15, %r12
jl 0x18b12
xorl %r15d, %r15d
movsd 0x80(%rsp,%r15,8), %xmm0
movq %r13, %rdi
leaq 0x9a340(%rip), %rsi # 0xb2dea
movb $0x1, %al
callq 0x3440
incq %r15
cmpq %r15, %r14
jne 0x18a96
jmp 0x18b12
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x80(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
testq %rbx, %rbx
js 0x18b12
xorl %r15d, %r15d
movsd 0x80(%rsp,%r15,8), %xmm0
movsd 0x88(%rsp,%r15,8), %xmm1
movq %r13, %rdi
leaq 0x9a2f0(%rip), %rsi # 0xb2df2
movb $0x2, %al
callq 0x3440
addq $0x2, %r15
cmpq %rbx, %r15
jle 0x18ae4
movl $0xa, %edi
movq %r13, %rsi
callq 0x3380
leaq 0x1(%rbp), %rax
cmpq 0x68(%rsp), %rbp
movq %rax, %rbp
movq 0x10(%rsp), %r15
jne 0x1885c
movq 0x60(%rsp), %rbx
addq %rbx, %r15
movq %r13, %rdi
callq 0x3310
movq 0x78(%rsp), %r14
addq %rbx, %r14
subq %rbx, 0x58(%rsp)
addq %rbx, 0x40(%rsp)
movq 0x50(%rsp), %rax
cmpq %rax, %r15
jle 0x1843c
jmp 0x18310
cmpq %r12, %rbp
movq 0x60(%rsp), %r12
jg 0x18eb1
leaq (%r12,%r15), %rax
decq %rax
movq %rax, 0x78(%rsp)
movl $0x1, %eax
subq %r15, %rax
movq %rax, 0x58(%rsp)
movq %rbp, 0x48(%rsp)
movq 0x50(%rsp), %rax
cmpq %rax, %r15
jg 0x18e8b
movq 0x58(%rsp), %r14
movq 0x78(%rsp), %r15
movq 0x10(%rsp), %rbx
cmpq %r15, %rax
movq %r15, %rbp
cmovlq %rax, %rbp
addq %rbx, %r12
decq %r12
cmpq %rax, %r12
cmovgeq %rax, %r12
movq 0x48(%rsp), %rax
movq %rax, 0x30(%rsp)
movq %rbx, 0x38(%rsp)
movq %rax, 0x20(%rsp)
movq %r12, 0x28(%rsp)
movq 0x70(%rsp), %rax
movq $-0x3e9, %rcx # imm = 0xFC17
addq %rcx, %rax
cmpq $0xf, %rax
ja 0x18c5f
addq %r14, %rbp
leaq 0x99f49(%rip), %rcx # 0xb2b4c
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0xc0(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %rbx, %r12
jl 0x18e6f
xorl %r12d, %r12d
movl 0xc0(%rsp,%r12,4), %edx
movq %r13, %rdi
leaq 0x9a19a(%rip), %rsi # 0xb2de5
xorl %eax, %eax
callq 0x3440
incq %r12
cmpq %r12, %rbp
jne 0x18c39
jmp 0x18e6f
leaq 0x9a1a8(%rip), %rdi # 0xb2e0e
xorl %esi, %esi
callq 0x18f07
jmp 0x18e6f
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x80(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
subq %rbx, %r12
js 0x18e6f
xorl %ebp, %ebp
movsd 0x80(%rsp,%rbp,8), %xmm0
movsd 0x88(%rsp,%rbp,8), %xmm1
movq %r13, %rdi
leaq 0x9a138(%rip), %rsi # 0xb2df2
movb $0x2, %al
callq 0x3440
addq $0x2, %rbp
cmpq %r12, %rbp
jle 0x18c9e
jmp 0x18e6f
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x130(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %rbx, %r12
jl 0x18e6f
xorl %r12d, %r12d
movq 0x130(%rsp,%r12,8), %rdx
movq %r13, %rdi
leaq 0x9a0f3(%rip), %rsi # 0xb2e01
xorl %eax, %eax
callq 0x3440
incq %r12
cmpq %r12, %rbp
jne 0x18cfc
jmp 0x18e6f
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x100(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %rbx, %r12
jl 0x18e6f
xorl %r12d, %r12d
movq 0x100(%rsp,%r12,8), %rdx
movq %r13, %rdi
leaq 0x9a0a6(%rip), %rsi # 0xb2e07
xorl %eax, %eax
callq 0x3440
incq %r12
cmpq %r12, %rbp
jne 0x18d4f
jmp 0x18e6f
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0xe0(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %rbx, %r12
jl 0x18e6f
xorl %r12d, %r12d
xorps %xmm0, %xmm0
cvtss2sd 0xe0(%rsp,%r12,4), %xmm0
movq %r13, %rdi
leaq 0x9a031(%rip), %rsi # 0xb2dea
movb $0x1, %al
callq 0x3440
incq %r12
cmpq %r12, %rbp
jne 0x18da2
jmp 0x18e6f
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x80(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
cmpq %rbx, %r12
jl 0x18e6f
xorl %r12d, %r12d
movsd 0x80(%rsp,%r12,8), %xmm0
movq %r13, %rdi
leaq 0x99fe0(%rip), %rsi # 0xb2dea
movb $0x1, %al
callq 0x3440
incq %r12
cmpq %r12, %rbp
jne 0x18df6
jmp 0x18e6f
movq 0x8(%rsp), %rdi
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x80(%rsp), %rcx
leaq 0x18(%rsp), %r8
callq 0x6abb1
subq %rbx, %r12
js 0x18e6f
xorl %ebp, %ebp
movsd 0x80(%rsp,%rbp,8), %xmm0
movsd 0x88(%rsp,%rbp,8), %xmm1
movq %r13, %rdi
leaq 0x99f93(%rip), %rsi # 0xb2df2
movb $0x2, %al
callq 0x3440
addq $0x2, %rbp
cmpq %r12, %rbp
jle 0x18e43
movq 0x60(%rsp), %r12
addq %r12, %rbx
addq %r12, %r15
subq %r12, %r14
movq 0x50(%rsp), %rax
cmpq %rax, %rbx
jle 0x18bb4
movl $0xa, %edi
movq %r13, %rsi
callq 0x3380
movq 0x48(%rsp), %rcx
leaq 0x1(%rcx), %rbp
cmpq 0x68(%rsp), %rcx
movq 0x10(%rsp), %r15
jne 0x18b92
movq %r13, %rdi
callq 0x3310
jmp 0x18310
movq 0xbe0d3(%rip), %rax # 0xd6f98
movq (%rax), %rdi
leaq 0x99ea1(%rip), %rsi # 0xb2d70
movq %rbp, %rdx
movq %r12, %rcx
movq 0x10(%rsp), %r8
movq %r10, %r9
xorl %eax, %eax
pushq %r15
pushq %r14
callq 0x3440
addq $0x10, %rsp
leaq 0x99e9e(%rip), %rdi # 0xb2d91
movq 0x8(%rsp), %rsi
callq 0x18f07
movq 0x50(%rsp), %r10
jmp 0x183b6
|
/GlobalArrays[P]ga/global/src/global.util.c
|
pnga_summarize
|
void pnga_summarize(Integer verbose)
{
#define DEV stdout
Integer i, j, g_a;
Integer printed, arr_no;
Integer type, active;
char *name;
Integer ndim, dims[MAXDIM];
Integer lop[MAXDIM], hip[MAXDIM];
Integer nproc = pnga_nnodes();
fprintf(DEV, " Summary of allocated global arrays\n");
fprintf(DEV, "-----------------------------------\n");
printed = 0;
arr_no = 0;
for(g_a=-1000; g_a<-900; g_a++) {
active = pnga_verify_handle(g_a);
if(active == 1) {
printed = 1;
pnga_inquire(g_a, &type, &ndim, dims);
pnga_inquire_name(g_a, &name);
switch(type) {
case C_INT:
fprintf(DEV, " array %d => integer ", (int)arr_no);
break;
case C_DBL:
fprintf(DEV, " array %d => double precision ",(int)arr_no);
break;
case C_DCPL:
fprintf(DEV, " array %d => double complex ", (int)arr_no);
break;
case C_SCPL:
fprintf(DEV, " array %d => float (single) complex ", (int)arr_no);
break;
case C_FLOAT:
fprintf(DEV, " array %d => float ",(int)arr_no);
break;
case C_LONG:
fprintf(DEV, " array %d => long ",(int)arr_no);
break;
case C_LONGLONG:
fprintf(DEV, " array %d => long long",(int)arr_no);
break;
default: pnga_error("ga_print: wrong type",0);
}
arr_no++;
fprintf(DEV,"%s(", name);
for(i=0; i<ndim; i++)
if(i != (ndim-1)) fprintf(DEV, "%ld,", (long)dims[i]);
else fprintf(DEV, "%ld", (long)dims[i]);
fprintf(DEV,"), handle: %d \n",(int) g_a);
if(verbose) {
for(i=0; i<nproc; i++){
pnga_distribution(g_a, i, lop, hip);
fprintf(DEV," (");
for(j=0; j<ndim; j++)
if(j != (ndim-1))
fprintf(DEV, "%ld:%ld,",(long)lop[j], (long)hip[j]);
else
fprintf(DEV, "%ld:%ld", (long)lop[j], (long)hip[j]);
fprintf(DEV,") -> %d \n",(int) i);
}
}
}
}
if(!printed) fprintf(DEV, " No active global arrays\n");
fprintf(DEV, "\n\n");
fflush(DEV);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %rdi, %r14
xorl %eax, %eax
callq 0x68602
movq %rax, %rbx
movq 0xbbf1c(%rip), %rbp # 0xd6ef0
movq (%rbp), %rcx
leaq 0x9828f(%rip), %rdi # 0xb326e
movl $0x24, %esi
movl $0x1, %edx
callq 0x3570
movq (%rbp), %rcx
leaq 0x9829a(%rip), %rdi # 0xb3293
movl $0x24, %esi
movl $0x1, %edx
callq 0x3570
testq %r14, %r14
sete %al
movq %rbx, 0x28(%rsp)
testq %rbx, %rbx
setle %bl
orb %al, %bl
movq $-0x3e8, %r14 # imm = 0xFC18
leaq 0x9817f(%rip), %r15 # 0xb31a8
leaq 0x9816f(%rip), %r12 # 0xb319f
movq $0x0, 0x10(%rsp)
xorl %r13d, %r13d
movb %bl, 0xf(%rsp)
movq %r14, %rdi
callq 0x65f0c
cmpq $0x1, %rax
jne 0x1b243
movq %r14, %rdi
leaq 0x38(%rsp), %rsi
leaq 0x18(%rsp), %rdx
leaq 0xc0(%rsp), %rcx
callq 0x6688f
movq %r14, %rdi
leaq 0x30(%rsp), %rsi
callq 0x66a33
movq 0x38(%rsp), %rax
movq $-0x3e9, %rcx # imm = 0xFC17
addq %rcx, %rax
cmpq $0xf, %rax
movq %r14, 0x20(%rsp)
ja 0x1b0b0
leaq 0x97c72(%rip), %rcx # 0xb2d0c
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq (%rbp), %rdi
leaq 0x9820a(%rip), %rsi # 0xb32b8
jmp 0x1b10c
leaq 0x97d57(%rip), %rdi # 0xb2e0e
xorl %esi, %esi
callq 0x18f07
jmp 0x1b118
movq (%rbp), %rdi
leaq 0x98224(%rip), %rsi # 0xb32ef
jmp 0x1b10c
movq (%rbp), %rdi
leaq 0x98270(%rip), %rsi # 0xb3348
jmp 0x1b10c
movq (%rbp), %rdi
leaq 0x98277(%rip), %rsi # 0xb335c
jmp 0x1b10c
movq (%rbp), %rdi
leaq 0x98241(%rip), %rsi # 0xb3333
jmp 0x1b10c
movq (%rbp), %rdi
leaq 0x981d0(%rip), %rsi # 0xb32cf
jmp 0x1b10c
movq (%rbp), %rdi
leaq 0x98201(%rip), %rsi # 0xb330d
movq 0x10(%rsp), %rdx
xorl %eax, %eax
callq 0x3440
movq (%rbp), %rdi
movq 0x30(%rsp), %rdx
leaq 0x98088(%rip), %rsi # 0xb31b0
xorl %eax, %eax
callq 0x3440
movq 0x18(%rsp), %rax
testq %rax, %rax
leaq 0x9be0e(%rip), %r13 # 0xb6f4c
leaq 0x9805e(%rip), %r14 # 0xb31a3
jle 0x1b176
xorl %ebx, %ebx
decq %rax
cmpq %rax, %rbx
movq (%rbp), %rdi
movq 0xc0(%rsp,%rbx,8), %rdx
movq %r14, %rsi
cmoveq %r13, %rsi
xorl %eax, %eax
callq 0x3440
incq %rbx
movq 0x18(%rsp), %rax
cmpq %rax, %rbx
jl 0x1b149
incq 0x10(%rsp)
movq (%rbp), %rdi
leaq 0x981ee(%rip), %rsi # 0xb3374
movq 0x20(%rsp), %r14
movl %r14d, %edx
xorl %eax, %eax
callq 0x3440
movl $0x1, %r13d
movb 0xf(%rsp), %bl
testb %bl, %bl
jne 0x1b243
xorl %r13d, %r13d
movq %r14, %rdi
movq %r13, %rsi
leaq 0x80(%rsp), %rdx
leaq 0x40(%rsp), %rcx
callq 0x5f51f
movq (%rbp), %rcx
movl $0x5, %esi
movl $0x1, %edx
leaq 0x981ae(%rip), %rdi # 0xb3385
callq 0x3570
movq 0x18(%rsp), %rax
testq %rax, %rax
jle 0x1b21a
xorl %ebx, %ebx
decq %rax
cmpq %rax, %rbx
movq (%rbp), %rdi
movq 0x80(%rsp,%rbx,8), %rdx
movq 0x40(%rsp,%rbx,8), %rcx
movq %r12, %rsi
cmoveq %r15, %rsi
xorl %eax, %eax
callq 0x3440
incq %rbx
movq 0x18(%rsp), %rax
cmpq %rax, %rbx
jl 0x1b1e8
movq (%rbp), %rdi
leaq 0x98166(%rip), %rsi # 0xb338b
movl %r13d, %edx
xorl %eax, %eax
callq 0x3440
incq %r13
cmpq 0x28(%rsp), %r13
jne 0x1b1aa
movl $0x1, %r13d
incq %r14
cmpq $-0x384, %r14 # imm = 0xFC7C
jne 0x1b040
testq %r13, %r13
jne 0x1b272
movq (%rbp), %rcx
leaq 0x98132(%rip), %rdi # 0xb3395
movl $0x1a, %esi
movl $0x1, %edx
callq 0x3570
movq (%rbp), %rcx
leaq 0x97eae(%rip), %rdi # 0xb312b
movl $0x2, %esi
movl $0x1, %edx
callq 0x3570
movq (%rbp), %rdi
callq 0x3310
addq $0xf8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/GlobalArrays[P]ga/global/src/global.util.c
|
printBlock
|
void printBlock(char * banner, Integer type, void *ptr, Integer lo[],
Integer hi[], Integer ld[])
{
Integer i,j;
Integer offset;
printf("p[%d] %s lo[0]: %d hi[0]: %d lo[1]: %d hi[1]: %d\n",
(int)pnga_nodeid(),banner,(int)lo[0],(int)hi[0],(int)lo[1],(int)hi[1]);
printf(" ");
for (i=lo[0]; i<=hi[0]; i++) printf(" %12d",(int)i);
printf("\n");
for (j=lo[1]; j<=hi[1]; j++) {
printf("J: %d",(int)j);
for (i=lo[0]; i<=hi[0]; i++) {
offset = (j-lo[1])*ld[0] + i-lo[0];
switch (type) {
case C_FLOAT:
printf(" %12.4f",*((float*)ptr+offset));
break;
case C_DBL:
printf(" %12.4f",*((double*)ptr+offset));
break;
case C_DCPL:
printf(" [%12.4f:%12.4f]",*((double*)ptr+2*offset),
*((double*)ptr+2*offset+1));
break;
case C_SCPL:
printf(" [%12.4f:%12.4f]",*((float*)ptr+2*offset),
*((float*)ptr+2*offset+1));
break;
default:
pnga_error("ga_matmul_basic: wrong data type", type);
}
}
printf("\n");
}
printf("\n\n");
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r9, 0x20(%rsp)
movq %r8, %r12
movq %rcx, %r15
movq %rdx, 0x10(%rsp)
movq %rsi, 0x18(%rsp)
movq %rdi, %r13
xorl %eax, %eax
callq 0x685c6
movl (%r15), %ecx
movl 0x8(%r15), %r9d
movl (%r12), %r8d
movl 0x8(%r12), %edx
movl %edx, (%rsp)
leaq 0x8e267(%rip), %rdi # 0xb3869
movl %eax, %esi
movq %r13, %rdx
xorl %eax, %eax
callq 0x3050
leaq 0x8d818(%rip), %rdi # 0xb2e2d
xorl %eax, %eax
callq 0x3050
movq (%r15), %r13
cmpq (%r12), %r13
jg 0x25646
leaq 0x8e26f(%rip), %rbp # 0xb389b
movq %rbp, %rdi
movl %r13d, %esi
xorl %eax, %eax
callq 0x3050
leaq 0x1(%r13), %rax
cmpq (%r12), %r13
movq %rax, %r13
jl 0x2562c
movl $0xa, %edi
callq 0x33f0
movq 0x8(%r15), %rbp
cmpq 0x8(%r12), %rbp
jg 0x2575b
movq 0x18(%rsp), %rax
leaq -0x3eb(%rax), %r13
leaq 0x8dfda(%rip), %rbx # 0xb364c
leaq 0x8e228(%rip), %rdi # 0xb38a1
movl %ebp, %esi
xorl %eax, %eax
callq 0x3050
movq (%r15), %r14
cmpq (%r12), %r14
jg 0x2573f
cmpq $0x4, %r13
ja 0x2571d
movq %rbp, %rax
subq 0x8(%r15), %rax
movq 0x20(%rsp), %rcx
imulq (%rcx), %rax
subq (%r15), %rax
addq %r14, %rax
movslq (%rbx,%r13,4), %rcx
addq %rbx, %rcx
jmpq *%rcx
movq 0x10(%rsp), %rcx
xorps %xmm0, %xmm0
cvtss2sd (%rcx,%rax,4), %xmm0
jmp 0x256e9
movq 0x10(%rsp), %rcx
xorps %xmm0, %xmm0
cvtss2sd (%rcx,%rax,8), %xmm0
xorps %xmm1, %xmm1
cvtss2sd 0x4(%rcx,%rax,8), %xmm1
jmp 0x2570d
movq 0x10(%rsp), %rcx
movsd (%rcx,%rax,8), %xmm0
leaq 0x8e1b7(%rip), %rdi # 0xb38a7
movb $0x1, %al
callq 0x3050
jmp 0x2572e
shlq $0x4, %rax
movq 0x10(%rsp), %rcx
movsd (%rcx,%rax), %xmm0
movsd 0x8(%rcx,%rax), %xmm1
leaq 0x8e19b(%rip), %rdi # 0xb38af
movb $0x2, %al
callq 0x3050
jmp 0x2572e
leaq 0x8e19c(%rip), %rdi # 0xb38c0
movq 0x18(%rsp), %rsi
callq 0x18f07
leaq 0x1(%r14), %rax
cmpq (%r12), %r14
movq %rax, %r14
jl 0x2568f
movl $0xa, %edi
callq 0x33f0
leaq 0x1(%rbp), %rax
cmpq 0x8(%r12), %rbp
movq %rax, %rbp
jl 0x25672
leaq 0x8d9ca(%rip), %rdi # 0xb312c
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x3460
|
/GlobalArrays[P]ga/global/src/matmul.c
|
pnga_set_diagonal
|
void pnga_set_diagonal(Integer g_a, Integer g_v)
{
Integer vndim, vdims, dim1, dim2, vtype, atype, type;
Integer me = pnga_nodeid (), i, nproc = pnga_nnodes();
Integer andim, adims[2];
Integer loA[2], hiA[2], ld;
Integer num_blocks_a;
int local_sync_begin,local_sync_end;
char *ptr;
_iterator_hdl hdl;
local_sync_begin = _ga_sync_begin; local_sync_end = _ga_sync_end;
_ga_sync_begin = 1; _ga_sync_end=1; /*remove any previous masking*/
if(local_sync_begin)pnga_sync();
pnga_check_handle (g_a, "ga_set_diagonal_");
pnga_check_handle (g_v, "ga_set_diagonal_");
pnga_inquire (g_a, &atype, &andim, adims);
dim1 = adims[0];
dim2 = adims[1];
type = atype;
pnga_inquire (g_v, &vtype, &vndim, &vdims);
/* Perform some error checking */
if (andim != 2)
pnga_error("ga_set_diagonal: wrong dimension for g_a.", andim);
if (vndim != 1)
pnga_error("ga_set_diagonal: wrong dimension for g_v.", vndim);
if (vdims != GA_MIN (dim1, dim2))
pnga_error
("ga_set_diagonal: The size of the first array's diagonal is greater than the size of the second array.",
type);
if (vtype != atype)
{
pnga_error
("ga_set_diagonal: input global arrays do not have the same data type. Global array type =",
atype);
}
#if 1
pnga_local_iterator_init(g_a, &hdl);
while (pnga_local_iterator_next(&hdl,loA,hiA,&ptr,&ld)) {
sgai_set_diagonal_block(g_a, ptr, g_v, loA, hiA, ld, type);
}
#else
num_blocks_a = pnga_total_blocks(g_a);
if (num_blocks_a < 0) {
pnga_distribution(g_a, me, loA, hiA);
pnga_access_ptr(g_a, loA, hiA, &ptr, &ld);
sgai_set_diagonal_block(g_a, ptr, g_v, loA, hiA, ld, type);
pnga_release_update(g_a, loA, hiA);
} else {
Integer idx;
/* Simple block-cyclic data distribution */
if (!pnga_uses_proc_grid(g_a)) {
for (idx = me; idx < num_blocks_a; idx += nproc) {
pnga_distribution(g_a, idx, loA, hiA);
pnga_access_block_ptr(g_a, idx, &ptr, &ld);
sgai_set_diagonal_block(g_a, ptr, g_v, loA, hiA, ld, type);
pnga_release_update_block(g_a, idx);
}
} else {
/* Uses scalapack block-cyclic data distribution */
Integer chk;
Integer proc_index[MAXDIM], index[MAXDIM];
Integer topology[MAXDIM];
Integer blocks[MAXDIM], block_dims[MAXDIM];
pnga_get_proc_index(g_a, me, proc_index);
pnga_get_proc_index(g_a, me, index);
pnga_get_block_info(g_a, blocks, block_dims);
pnga_get_proc_grid(g_a, topology);
while (index[andim-1] < blocks[andim-1]) {
/* find bounding coordinates of block */
chk = 1;
for (i = 0; i < andim; i++) {
loA[i] = index[i]*block_dims[i]+1;
hiA[i] = (index[i] + 1)*block_dims[i];
if (hiA[i] > adims[i]) hiA[i] = adims[i];
if (hiA[i] < loA[i]) chk = 0;
}
if (chk) {
pnga_access_block_grid_ptr(g_a, index, &ptr, &ld);
sgai_set_diagonal_block(g_a, ptr, g_v, loA, hiA, ld, type);
pnga_release_update_block_grid(g_a, index);
}
/* increment index to get next block on processor */
index[0] += topology[0];
for (i = 0; i < andim; i++) {
if (index[i] >= blocks[i] && i<andim-1) {
index[i] = proc_index[i];
index[i+1] += topology[i+1];
}
}
}
}
}
#endif
if(local_sync_end)pnga_sync();
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x3e8, %rsp # imm = 0x3E8
movq %rsi, 0x48(%rsp)
movq %rdi, 0x38(%rsp)
xorl %eax, %eax
callq 0x685c6
xorl %eax, %eax
callq 0x68602
leaq 0xae1bc(%rip), %rax # 0xd7160
leaq 0xae1b9(%rip), %rcx # 0xd7164
cmpl $0x0, (%rax)
movl (%rcx), %edx
movl %edx, 0x44(%rsp)
movl $0x1, %edx
movl %edx, (%rax)
movl %edx, (%rcx)
je 0x28fc6
xorl %eax, %eax
callq 0x6983a
leaq 0x8b21c(%rip), %rbx # 0xb41e9
movq 0x38(%rsp), %r12
movq %r12, %rdi
movq %rbx, %rsi
callq 0x5d393
movq 0x48(%rsp), %r13
movq %r13, %rdi
movq %rbx, %rsi
callq 0x5d393
leaq 0x98(%rsp), %rbx
leaq 0xc8(%rsp), %r14
leaq 0xd0(%rsp), %r15
movq %r12, %rdi
movq %rbx, %rsi
movq %r14, %rdx
movq %r15, %rcx
callq 0x6688f
movq (%r15), %r12
movq 0x8(%r15), %r15
movq (%rbx), %rax
movq %rax, 0x30(%rsp)
leaq 0xa0(%rsp), %rsi
leaq 0xb0(%rsp), %rdx
leaq 0xa8(%rsp), %rcx
movq %r13, %rdi
callq 0x6688f
movq (%r14), %rsi
cmpq $0x2, %rsi
je 0x2905a
leaq 0x8b1a5(%rip), %rdi # 0xb41fa
callq 0x18f07
movq 0xb0(%rsp), %rsi
cmpq $0x1, %rsi
je 0x29074
leaq 0x8b1b5(%rip), %rdi # 0xb4224
callq 0x18f07
cmpq %r15, %r12
cmovlq %r12, %r15
cmpq %r15, 0xa8(%rsp)
je 0x29096
leaq 0x8b1c2(%rip), %rdi # 0xb424e
movq 0x30(%rsp), %rsi
callq 0x18f07
movq 0x98(%rsp), %rsi
cmpq %rsi, 0xa0(%rsp)
je 0x290b4
leaq 0x8b205(%rip), %rdi # 0xb42b4
callq 0x18f07
leaq 0xe8(%rsp), %rbx
movq 0x38(%rsp), %rdi
movq %rbx, %rsi
callq 0x1e308
leaq 0x70(%rsp), %rsi
leaq 0x60(%rsp), %rdx
leaq 0x50(%rsp), %rcx
leaq 0x58(%rsp), %r8
movq %rbx, %rdi
callq 0x1e731
testl %eax, %eax
je 0x2945b
movq 0x30(%rsp), %rax
addq $-0x3e9, %rax # imm = 0xFC17
movq %rax, 0x80(%rsp)
movq 0x70(%rsp), %r13
testq %r13, %r13
jle 0x29432
movq 0x50(%rsp), %rdx
movq 0x58(%rsp), %r12
movq 0x78(%rsp), %rbp
movq 0x60(%rsp), %rax
movq 0x68(%rsp), %rcx
cmpq %rbp, %r13
movq %rbp, %rbx
cmovgq %r13, %rbx
movq %rbx, (%rsp)
movq %rbx, 0x8(%rsp)
cmpq %rcx, %rax
movq %rcx, %r14
cmovlq %rax, %r14
movq %r14, 0x20(%rsp)
movq %r14, 0x28(%rsp)
movq %r14, %r15
subq %rbx, %r15
jl 0x29432
movq %rdx, 0x18(%rsp)
movq %rcx, 0x88(%rsp)
movq %rax, 0x90(%rsp)
movq 0x30(%rsp), %rdi
callq 0x5d34c
movq %rbx, 0xc0(%rsp)
movq %r14, 0xb8(%rsp)
incq %r15
imulq %rax, %r15
movq %r15, %rdi
callq 0x33b0
movq %rax, %r15
testq %rax, %rax
jne 0x291ae
leaq 0x8b549(%rip), %rdi # 0xb46f0
xorl %esi, %esi
callq 0x18f07
movq 0x48(%rsp), %rdi
leaq 0xc0(%rsp), %rsi
leaq 0xb8(%rsp), %rdx
movq %r15, %rcx
movq %rdx, %r8
callq 0x6abb1
movq 0x80(%rsp), %rax
cmpq $0x6, %rax
ja 0x292ef
leaq 0x8aae5(%rip), %rcx # 0xb3ccc
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movq (%rsp), %rcx
movq 0x20(%rsp), %rax
subq %rcx, %rax
jl 0x293f5
movq 0x8(%rsp), %rdx
subq %rbp, %rdx
imulq %r12, %rdx
subq %r13, %rcx
movq 0x18(%rsp), %rsi
leaq (%rsi,%rcx,4), %rcx
leaq (%rcx,%rdx,4), %rcx
leaq 0x4(,%r12,4), %rdx
incq %rax
xorl %esi, %esi
movl (%r15,%rsi,4), %edi
movl %edi, (%rcx)
incq %rsi
addq %rdx, %rcx
cmpq %rsi, %rax
jne 0x2922b
jmp 0x293f5
movq (%rsp), %rcx
movq 0x20(%rsp), %rax
subq %rcx, %rax
jl 0x293f5
movq 0x8(%rsp), %rdx
subq %rbp, %rdx
imulq %r12, %rdx
subq %r13, %rcx
movq 0x18(%rsp), %rsi
leaq (%rsi,%rcx,4), %rcx
leaq (%rcx,%rdx,4), %rcx
leaq 0x4(,%r12,4), %rdx
incq %rax
xorl %esi, %esi
movss (%r15,%rsi,4), %xmm0
movss %xmm0, (%rcx)
incq %rsi
addq %rdx, %rcx
cmpq %rsi, %rax
jne 0x2927c
jmp 0x293f5
movq (%rsp), %rdx
movq 0x20(%rsp), %rax
subq %rdx, %rax
jl 0x293f5
movq 0x8(%rsp), %rcx
subq %rbp, %rcx
imulq %r12, %rcx
subq %r13, %rdx
shlq $0x4, %rdx
movq 0x18(%rsp), %rsi
addq %rdx, %rsi
shlq $0x4, %rcx
addq %rsi, %rcx
shlq $0x4, %r12
addq $0x10, %r12
incq %rax
movq %r15, %rdx
movups (%rdx), %xmm0
movups %xmm0, (%rcx)
addq %r12, %rcx
addq $0x10, %rdx
decq %rax
jne 0x292d8
jmp 0x293f5
leaq 0x8b436(%rip), %rdi # 0xb472c
movq 0x30(%rsp), %rsi
callq 0x18f07
jmp 0x293f5
movq (%rsp), %rcx
movq 0x20(%rsp), %rax
subq %rcx, %rax
jl 0x293f5
movq 0x8(%rsp), %rdx
subq %rbp, %rdx
imulq %r12, %rdx
subq %r13, %rcx
movq 0x18(%rsp), %rsi
leaq (%rsi,%rcx,8), %rcx
leaq (%rcx,%rdx,8), %rcx
leaq 0x8(,%r12,8), %rdx
incq %rax
xorl %esi, %esi
movq (%r15,%rsi,8), %rdi
movq %rdi, (%rcx)
incq %rsi
addq %rdx, %rcx
cmpq %rsi, %rax
jne 0x29340
jmp 0x293f5
movq (%rsp), %rcx
movq 0x20(%rsp), %rax
subq %rcx, %rax
jl 0x293f5
movq 0x8(%rsp), %rdx
subq %rbp, %rdx
imulq %r12, %rdx
subq %r13, %rcx
movq 0x18(%rsp), %rsi
leaq (%rsi,%rcx,8), %rcx
leaq (%rcx,%rdx,8), %rcx
leaq 0x8(,%r12,8), %rdx
incq %rax
xorl %esi, %esi
movsd (%r15,%rsi,8), %xmm0
movsd %xmm0, (%rcx)
incq %rsi
addq %rdx, %rcx
cmpq %rsi, %rax
jne 0x29392
jmp 0x293f5
movq (%rsp), %rcx
movq 0x20(%rsp), %rax
subq %rcx, %rax
jl 0x293f5
movq 0x8(%rsp), %rdx
subq %rbp, %rdx
imulq %r12, %rdx
subq %r13, %rcx
movq 0x18(%rsp), %rsi
leaq (%rsi,%rcx,8), %rcx
leaq (%rcx,%rdx,8), %rcx
leaq 0x8(,%r12,8), %rdx
incq %rax
xorl %esi, %esi
movsd (%r15,%rsi,8), %xmm0
movsd %xmm0, (%rcx)
incq %rsi
addq %rdx, %rcx
cmpq %rsi, %rax
jne 0x293e0
movq %r15, %rdi
callq 0x3330
movq %r13, (%rsp)
movq %rbp, 0x8(%rsp)
movq 0x90(%rsp), %rax
movq %rax, 0x20(%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0x28(%rsp)
movq 0x38(%rsp), %rdi
movq %rsp, %rsi
leaq 0x20(%rsp), %rdx
callq 0x6dcc9
leaq 0xe8(%rsp), %rdi
leaq 0x70(%rsp), %rsi
leaq 0x60(%rsp), %rdx
leaq 0x50(%rsp), %rcx
leaq 0x58(%rsp), %r8
callq 0x1e731
testl %eax, %eax
jne 0x29100
cmpl $0x0, 0x44(%rsp)
je 0x29469
xorl %eax, %eax
callq 0x6983a
addq $0x3e8, %rsp # imm = 0x3E8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/GlobalArrays[P]ga/global/src/matrix.c
|
pnga_shift_diagonal
|
void pnga_shift_diagonal(Integer g_a, void *c)
{
Integer loA[2], hiA[2]/*, dim1, dim2*/, ld;
Integer andim, adims[2], type, atype;
Integer me = pnga_nodeid (), i, nproc = pnga_nnodes();
char *ptr;
Integer num_blocks_a;
int local_sync_begin,local_sync_end;
_iterator_hdl hdl;
local_sync_begin = _ga_sync_begin; local_sync_end = _ga_sync_end;
_ga_sync_begin = 1; _ga_sync_end=1; /*remove any previous masking*/
if(local_sync_begin)pnga_sync();
pnga_check_handle (g_a, "ga_shift_diagonal_");
pnga_inquire (g_a, &atype, &andim, adims);
/*dim1 = adims[0];*/
/*dim2 = adims[1];*/
type = atype;
if (andim != 2)
pnga_error("Dimension must be 2 for shift diagonal operation",andim);
#if 1
pnga_local_iterator_init(g_a, &hdl);
while (pnga_local_iterator_next(&hdl,loA,hiA,&ptr,&ld)) {
sgai_shift_diagonal_block(g_a, ptr, loA, hiA, ld, c, type);
}
#else
num_blocks_a = pnga_total_blocks(g_a);
if (num_blocks_a < 0) {
pnga_distribution(g_a, me, loA, hiA);
pnga_access_ptr(g_a, loA, hiA, &ptr, &ld);
sgai_shift_diagonal_block(g_a, ptr, loA, hiA, ld, c, type);
pnga_release_update(g_a, loA, hiA);
} else {
Integer idx;
/* Simple block-cyclic data distribution */
if (!pnga_uses_proc_grid(g_a)) {
for (idx = me; idx < num_blocks_a; idx += nproc) {
pnga_distribution(g_a, idx, loA, hiA);
pnga_access_block_ptr(g_a, idx, &ptr, &ld);
sgai_shift_diagonal_block(g_a, ptr, loA, hiA, ld, c, type);
pnga_release_update_block(g_a, idx);
}
} else {
/* Uses scalapack block-cyclic data distribution */
Integer chk;
Integer proc_index[MAXDIM], index[MAXDIM];
Integer topology[MAXDIM];
Integer blocks[MAXDIM], block_dims[MAXDIM];
pnga_get_proc_index(g_a, me, proc_index);
pnga_get_proc_index(g_a, me, index);
pnga_get_block_info(g_a, blocks, block_dims);
pnga_get_proc_grid(g_a, topology);
while (index[andim-1] < blocks[andim-1]) {
/* find bounding coordinates of block */
chk = 1;
for (i = 0; i < andim; i++) {
loA[i] = index[i]*block_dims[i]+1;
hiA[i] = (index[i] + 1)*block_dims[i];
if (hiA[i] > adims[i]) hiA[i] = adims[i];
if (hiA[i] < loA[i]) chk = 0;
}
if (chk) {
pnga_access_block_grid_ptr(g_a, index, &ptr, &ld);
sgai_shift_diagonal_block(g_a, ptr, loA, hiA, ld, c, type);
pnga_release_update_block_grid(g_a, index);
}
/* increment index to get next block on processor */
index[0] += topology[0];
for (i = 0; i < andim; i++) {
if (index[i] >= blocks[i] && i<andim-1) {
index[i] = proc_index[i];
index[i+1] += topology[i+1];
}
}
}
}
}
#endif
if(local_sync_end)pnga_sync();
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x368, %rsp # imm = 0x368
movq %rsi, %rbx
movq %rdi, %r14
xorl %eax, %eax
callq 0x685c6
xorl %eax, %eax
callq 0x68602
leaq 0xadcb9(%rip), %rax # 0xd7160
leaq 0xadcb6(%rip), %rcx # 0xd7164
cmpl $0x0, (%rax)
movl (%rcx), %edx
movl %edx, 0x4(%rsp)
movl $0x1, %edx
movl %edx, (%rax)
movl %edx, (%rcx)
je 0x294c9
xorl %eax, %eax
callq 0x6983a
leaq 0x8ae3d(%rip), %rsi # 0xb430d
movq %r14, %rdi
callq 0x5d393
leaq 0x40(%rsp), %r15
leaq 0x48(%rsp), %r12
leaq 0x50(%rsp), %rcx
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
callq 0x6688f
movq (%r15), %rax
movq %rax, 0x8(%rsp)
movq (%r12), %rsi
cmpq $0x2, %rsi
je 0x29513
leaq 0x8ae12(%rip), %rdi # 0xb4320
callq 0x18f07
leaq 0x68(%rsp), %r15
movq %r14, %rdi
movq %r15, %rsi
callq 0x1e308
leaq 0x30(%rsp), %rsi
leaq 0x20(%rsp), %rdx
leaq 0x10(%rsp), %rcx
leaq 0x18(%rsp), %r8
movq %r15, %rdi
callq 0x1e731
testl %eax, %eax
je 0x29743
movq 0x8(%rsp), %rax
leaq -0x3e9(%rax), %r12
leaq 0x30(%rsp), %r13
leaq 0x20(%rsp), %rbp
leaq 0x10(%rsp), %r15
leaq 0x18(%rsp), %r14
movq 0x30(%rsp), %rdx
testq %rdx, %rdx
jle 0x29596
movq 0x38(%rsp), %r9
movq 0x20(%rsp), %rcx
movq 0x28(%rsp), %rax
cmpq %r9, %rdx
movq %r9, %rsi
cmovgq %rdx, %rsi
cmpq %rax, %rcx
cmovlq %rcx, %rax
subq %rsi, %rax
jge 0x295b5
leaq 0x68(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movq %r15, %rcx
movq %r14, %r8
callq 0x1e731
testl %eax, %eax
jne 0x29567
jmp 0x29743
cmpq $0x6, %r12
ja 0x29686
movq 0x10(%rsp), %rdi
movq 0x18(%rsp), %rcx
leaq 0x8a718(%rip), %r10 # 0xb3ce8
movslq (%r10,%r12,4), %r8
addq %r10, %r8
jmpq *%r8
movq %rsi, %r8
subq %r9, %r8
imulq %rcx, %r8
subq %rdx, %rsi
leaq (%rdi,%rsi,4), %rdx
leaq (%rdx,%r8,4), %rdx
incq %rax
leaq 0x4(,%rcx,4), %rcx
movl (%rbx), %esi
addl %esi, (%rdx)
addq %rcx, %rdx
decq %rax
jne 0x295fa
jmp 0x29596
movq %rsi, %r8
subq %r9, %r8
imulq %rcx, %r8
subq %rdx, %rsi
leaq (%rdi,%rsi,4), %rdx
leaq (%rdx,%r8,4), %rdx
incq %rax
leaq 0x4(,%rcx,4), %rcx
movss (%rbx), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq %rcx, %rdx
decq %rax
jne 0x29628
jmp 0x29596
movq %rsi, %r8
subq %r9, %r8
imulq %rcx, %r8
subq %rdx, %rsi
shlq $0x4, %rsi
addq %rsi, %rdi
shlq $0x4, %r8
addq %rdi, %r8
incq %rax
shlq $0x4, %rcx
addq $0x10, %rcx
movupd (%rbx), %xmm0
movupd (%r8), %xmm1
addpd %xmm0, %xmm1
movupd %xmm1, (%r8)
addq %rcx, %r8
decq %rax
jne 0x29667
jmp 0x29596
leaq 0x8b0c2(%rip), %rdi # 0xb474f
movq 0x8(%rsp), %rsi
callq 0x18f07
jmp 0x29596
movq %rsi, %r8
subq %r9, %r8
imulq %rcx, %r8
subq %rdx, %rsi
leaq (%rdi,%rsi,8), %rdx
leaq (%rdx,%r8,8), %rdx
incq %rax
leaq 0x8(,%rcx,8), %rcx
movq (%rbx), %rsi
addq %rsi, (%rdx)
addq %rcx, %rdx
decq %rax
jne 0x296bc
jmp 0x29596
movq %rsi, %r8
subq %r9, %r8
imulq %rcx, %r8
subq %rdx, %rsi
leaq (%rdi,%rsi,8), %rdx
leaq (%rdx,%r8,8), %rdx
incq %rax
leaq 0x8(,%rcx,8), %rcx
movsd (%rbx), %xmm0
addsd (%rdx), %xmm0
movsd %xmm0, (%rdx)
addq %rcx, %rdx
decq %rax
jne 0x296ef
jmp 0x29596
movq %rsi, %r8
subq %r9, %r8
imulq %rcx, %r8
subq %rdx, %rsi
leaq (%rdi,%rsi,8), %rdx
leaq (%rdx,%r8,8), %rdx
leaq 0x8(,%rcx,8), %rcx
incq %rax
movsd (%rbx), %xmm0
movsd (%rdx), %xmm1
addps %xmm0, %xmm1
movlps %xmm1, (%rdx)
addq %rcx, %rdx
decq %rax
jne 0x29728
jmp 0x29596
cmpl $0x0, 0x4(%rsp)
je 0x29751
xorl %eax, %eax
callq 0x6983a
addq $0x368, %rsp # imm = 0x368
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/GlobalArrays[P]ga/global/src/matrix.c
|
pnga_diag_reuse
|
void pnga_diag_reuse(Integer reuse, Integer g_a, Integer g_s,
Integer g_v, DoublePrecision *eval) {
#if ENABLE_PEIGS
# if ENABLE_F77
gai_diag_reuse_(&reuse, &g_a, &g_s, &g_v, eval);
# else
pnga_error("ga_diag:peigs interfaced, need to configure --enable-f77",0L);
# endif
#else
pnga_error("ga_diag:peigs not interfaced",0L);
#endif
}
|
leaq 0x8a51d(%rip), %rdi # 0xb4858
xorl %esi, %esi
jmp 0x18f07
nop
|
/GlobalArrays[P]ga/global/src/peigstubs.c
|
pnga_lu_solve
|
void pnga_lu_solve(char *tran, Integer g_a, Integer g_b) {
Integer dimA1, dimA2, typeA;
Integer dimB1, dimB2, typeB;
Integer dimsA[2], dimsB[2], ndim;
/** check GA info for input arrays */
pnga_check_handle(g_a, "ga_lu_solve: a");
pnga_check_handle(g_b, "ga_lu_solve: b");
pnga_inquire (g_a, &typeA, &ndim, dimsA);
pnga_inquire (g_b, &typeB, &ndim, dimsB);
dimA1 = dimsA[0];
dimA2 = dimsA[1];
dimB1 = dimsB[0];
dimB2 = dimsB[1];
if( (dimA1*dimA2 > _MAX_PROB_SIZE_) || (dimB1*dimB2 > _MAX_PROB_SIZE_) )
pnga_error("ga_lu_solve:Array size too large. Use scalapack for optimum performance. configure --with-scalapack or --with-scalapack-i8 for ga_lu_solve to use Scalapack interface",0L);
pnga_lu_solve_seq(tran, g_a, g_b);
}
|
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x40, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x87bf1(%rip), %rsi # 0xb1f60
movq %r14, %rdi
callq 0x5d393
leaq 0x87bf1(%rip), %rsi # 0xb1f6f
movq %rbx, %rdi
callq 0x5d393
leaq 0x28(%rsp), %rsi
leaq 0x18(%rsp), %r12
leaq 0x30(%rsp), %r13
movq %r14, %rdi
movq %r12, %rdx
movq %r13, %rcx
callq 0x6688f
leaq 0x20(%rsp), %rsi
movq %rsp, %rcx
movq %rbx, %rdi
movq %r12, %rdx
callq 0x6688f
movq 0x8(%r13), %rax
imulq (%r13), %rax
cmpq $0x2710, %rax # imm = 0x2710
jg 0x2a3d9
movq (%rsp), %rax
imulq 0x8(%rsp), %rax
cmpq $0x2711, %rax # imm = 0x2711
jl 0x2a3e7
leaq 0x8a4ba(%rip), %rdi # 0xb489a
xorl %esi, %esi
callq 0x18f07
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq 0xf8f1
addq $0x40, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
|
/GlobalArrays[P]ga/global/src/sclstubs.c
|
pnga_bin_index
|
void pnga_bin_index(Integer g_bin, Integer g_cnt, Integer g_off,
Integer *values, Integer *subs, Integer n, Integer sortit)
{
int i, my_nbin=0;
int *all_bin_contrib, *offset;
Integer type, ndim, nbin;
pnga_inquire(g_bin, &type, &ndim, &nbin);
if(ndim !=1) pnga_error("ga_bin_index: 1-dim array required",ndim);
if(type!= C_INT && type!=C_LONG && type!=C_LONGLONG)
pnga_error("ga_bin_index: not integer type",type);
all_bin_contrib = (int*)calloc(nbin,sizeof(int));
if(!all_bin_contrib)pnga_error("ga_binning:calloc failed",nbin);
offset = (int*)malloc(nbin*sizeof(int));
if(!offset)pnga_error("ga_binning:malloc failed",nbin);
/* count how many elements go to each bin */
for(i=0; i< n; i++){
int selected = subs[i];
if(selected <1 || selected> nbin) pnga_error("wrong bin",selected);
if(all_bin_contrib[selected-1] ==0) my_nbin++; /* new bin found */
all_bin_contrib[selected-1]++;
}
/* process bins in chunks to match available buffer space */
for(i=0; i<nbin; i+=NWORK){
int cnbin = ((i+NWORK)<nbin) ? NWORK: nbin -i;
sgai_bin_offset(SCOPE_ALL, all_bin_contrib+i, cnbin, offset+i);
}
for(i=0; i< n; ){
Integer lo, hi;
Integer selected = subs[i];
int elems = all_bin_contrib[selected-1];
pnga_get(g_off,&selected,&selected, &lo, &selected);
lo += offset[selected-1]+1;
hi = lo + elems -1;
/*
printf("%d: elems=%d lo=%d sel=%d off=%d contrib=%d nbin=%d\n",pnga_nodeid(), elems, lo, selected,offset[selected-1],all_bin_contrib[0],nbin);
*/
if(lo > nbin) {
printf("Writing off end of bins array: index=%d elems=%d lo=%ld hi=%ld values=%ld nbin=%ld\n",
i,elems,(long)lo,(long)hi,(long)values+i,(long)nbin);
break;
}else{
pnga_put(g_bin, &lo, &hi, values+i, &selected);
}
i+=elems;
}
free(offset);
free(all_bin_contrib);
if(sortit)pnga_bin_sorter(g_bin, g_cnt, g_off);
else pnga_sync();
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r9, %r13
movq %r8, %rbp
movq %rcx, 0x58(%rsp)
movq %rdx, 0x60(%rsp)
movq %rsi, 0x80(%rsp)
leaq 0x98(%rsp), %rsi
leaq 0xa0(%rsp), %rbx
leaq 0x30(%rsp), %rcx
movq %rdi, 0x50(%rsp)
movq %rbx, %rdx
callq 0x6688f
movq (%rbx), %rsi
cmpq $0x1, %rsi
je 0x39f30
leaq 0x7b611(%rip), %rdi # 0xb553c
callq 0x18f07
movq 0x98(%rsp), %rsi
leaq -0x3e9(%rsi), %rax
cmpq $0xf, %rax
ja 0x39f50
movl $0x8003, %ecx # imm = 0x8003
btq %rax, %rcx
jb 0x39f5c
leaq 0x7b608(%rip), %rdi # 0xb555f
callq 0x18f07
movq 0x30(%rsp), %rbx
movl $0x4, %esi
movq %rbx, %rdi
callq 0x3190
movq %rax, 0x20(%rsp)
testq %rax, %rax
jne 0x39f87
leaq 0x7b6f1(%rip), %rdi # 0xb5670
movq %rbx, %rsi
callq 0x18f07
movq 0x30(%rsp), %rbx
leaq (,%rbx,4), %rdi
callq 0x33b0
movq %rax, 0x40(%rsp)
testq %rax, %rax
jne 0x39fb2
leaq 0x7b6df(%rip), %rdi # 0xb5689
movq %rbx, %rsi
callq 0x18f07
testq %r13, %r13
jle 0x3a00b
xorl %r14d, %r14d
leaq 0x7b6e1(%rip), %rbx # 0xb56a2
movabsq $-0x100000000, %r15 # imm = 0xFFFFFFFF00000000
movq (%rbp,%r14,8), %r12
testl %r12d, %r12d
jle 0x39fe4
movl %r12d, %eax
andl $0x7fffffff, %eax # imm = 0x7FFFFFFF
cmpq 0x30(%rsp), %rax
jle 0x39fef
movslq %r12d, %rsi
movq %rbx, %rdi
callq 0x18f07
shlq $0x20, %r12
addq %r15, %r12
sarq $0x1e, %r12
movq 0x20(%rsp), %rax
incl (%rax,%r12)
incq %r14
cmpq %r14, %r13
jne 0x39fcb
movq %rbp, 0x68(%rsp)
movq %r13, 0x70(%rsp)
movq 0x30(%rsp), %rax
testq %rax, %rax
jle 0x3a27a
leaq 0xa0156(%rip), %rbp # 0xda180
leaq 0x9e20f(%rip), %rbx # 0xd8240
movq 0x40(%rsp), %r12
movq 0x20(%rsp), %r14
xorl %edx, %edx
movq $0x0, 0x78(%rsp)
leaq 0x7d0(%rdx), %rcx
movl %eax, %r13d
movq %rdx, 0x88(%rsp)
subl %edx, %r13d
movq %rcx, 0x90(%rsp)
cmpq %rcx, %rax
movl $0x7d0, %eax # imm = 0x7D0
cmovgl %eax, %r13d
xorl %eax, %eax
callq 0x5a04a
movl %eax, 0xc(%rsp)
cmpq $0x0, 0x20(%rsp)
jne 0x3a091
movslq %r13d, %rsi
leaq 0x7b7ac(%rip), %rdi # 0xb5838
callq 0x18f07
cmpl $0x7d1, %r13d # imm = 0x7D1
jl 0x3a0a9
movl %r13d, %esi
leaq 0x7b7b2(%rip), %rdi # 0xb5856
callq 0x18f07
leal (,%r13,4), %r15d
movl $0x14d, %edi # imm = 0x14D
leaq 0x28(%rsp), %rsi
leaq 0x48(%rsp), %rdx
leaq 0x10(%rsp), %rcx
leaq 0x1c(%rsp), %r8
callq 0x59f95
movl 0x10(%rsp), %r8d
testl %r8d, %r8d
js 0x3a0ee
movl $0x7d64, %edi # imm = 0x7D64
movq %rbp, %rsi
movl %r15d, %edx
leaq 0x3c(%rsp), %rcx
callq 0x5968c
movl 0x1c(%rsp), %r8d
testl %r8d, %r8d
js 0x3a10d
movl $0x7d64, %edi # imm = 0x7D64
movq %rbx, %rsi
movl %r15d, %edx
leaq 0x3c(%rsp), %rcx
callq 0x5968c
movl 0x10(%rsp), %eax
movl 0x1c(%rsp), %ecx
orl %eax, %ecx
js 0x3a138
testl %r13d, %r13d
jle 0x3a17a
movl %r13d, %eax
xorl %ecx, %ecx
movl (%r14,%rcx,4), %edx
addl (%rbx,%rcx,4), %edx
addl %edx, (%rbp,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne 0x3a123
jmp 0x3a17a
testl %eax, %eax
js 0x3a158
testl %r13d, %r13d
jle 0x3a17a
movl %r13d, %eax
xorl %ecx, %ecx
movl (%r14,%rcx,4), %edx
addl %edx, (%rbp,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne 0x3a146
jmp 0x3a17a
testl %r13d, %r13d
jle 0x3a17a
imulq $0x1f40, 0x78(%rsp), %rsi # imm = 0x1F40
addq 0x20(%rsp), %rsi
movl %r13d, %edx
shlq $0x2, %rdx
movq %rbp, %rdi
callq 0x3220
movl 0xc(%rsp), %eax
cmpl 0x28(%rsp), %eax
setne %al
movl 0x48(%rsp), %ecx
cmpl $-0x1, %ecx
setne %dl
andb %al, %dl
cmpb $0x1, %dl
jne 0x3a1a6
movl $0x7d64, %edi # imm = 0x7D64
movq %rbp, %rsi
movl %r15d, %edx
callq 0x59542
movl 0xc(%rsp), %eax
cmpl 0x28(%rsp), %eax
setne %al
movl 0x48(%rsp), %r8d
cmpl $-0x1, %r8d
setne %cl
andb %al, %cl
cmpb $0x1, %cl
jne 0x3a1d9
movl $0x7d64, %edi # imm = 0x7D64
movq %rbp, %rsi
movl %r15d, %edx
leaq 0x3c(%rsp), %rcx
callq 0x5968c
testl %r13d, %r13d
jle 0x3a1f7
movl %r13d, %eax
xorl %ecx, %ecx
movl (%rbp,%rcx,4), %edx
subl (%r14,%rcx,4), %edx
movl %edx, (%r12,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne 0x3a1e3
movl 0x1c(%rsp), %ecx
testl %ecx, %ecx
movl %r15d, %edx
js 0x3a220
movq 0x40(%rsp), %rax
movq 0x88(%rsp), %rsi
leaq (%rax,%rsi,4), %rsi
movl $0x7d64, %edi # imm = 0x7D64
callq 0x59542
movl %r15d, %edx
movl 0x10(%rsp), %ecx
testl %ecx, %ecx
js 0x3a251
testl %r13d, %r13d
jle 0x3a244
movl %r13d, %eax
xorl %edi, %edi
movl (%r12,%rdi,4), %esi
subl (%rbx,%rdi,4), %esi
movl %esi, (%rbx,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne 0x3a232
movl $0x7d64, %edi # imm = 0x7D64
movq %rbx, %rsi
callq 0x59542
movq 0x30(%rsp), %rax
incq 0x78(%rsp)
movl $0x1f40, %ecx # imm = 0x1F40
addq %rcx, %r14
addq %rcx, %r12
movq 0x90(%rsp), %rcx
movq %rcx, %rdx
cmpq %rcx, %rax
jg 0x3a046
leaq 0x28(%rsp), %r15
leaq 0x10(%rsp), %rdx
xorl %esi, %esi
movq 0x70(%rsp), %rax
movq 0x68(%rsp), %rcx
movslq %esi, %r13
cmpq %rax, %r13
jge 0x3a370
movl %esi, 0xc(%rsp)
movq (%rcx,%r13,8), %rax
movq %rax, 0x10(%rsp)
movq 0x20(%rsp), %rcx
movslq -0x4(%rcx,%rax,4), %rbp
movq 0x60(%rsp), %rdi
movq %rdx, %rsi
movq %r15, %rcx
movq %rdx, %r14
movq %rdx, %r8
callq 0x6abb1
movq 0x10(%rsp), %rax
movq 0x40(%rsp), %rcx
movslq -0x4(%rcx,%rax,4), %rax
movq 0x28(%rsp), %rcx
leaq (%rax,%rcx), %rdx
leaq (%rax,%rcx), %r12
incq %r12
movq %r12, 0x28(%rsp)
leaq (%rdx,%rbp), %r8
incq %r8
decq %r8
movq %r8, 0x48(%rsp)
movq 0x30(%rsp), %rbx
cmpq %rbx, %r12
jle 0x3a32f
movq 0x58(%rsp), %rax
leaq (%rax,%r13), %r9
movq %rbx, (%rsp)
leaq 0x7b392(%rip), %rdi # 0xb56ac
movl %r13d, %esi
movl %ebp, %edx
movq %r12, %rcx
xorl %eax, %eax
callq 0x3050
movl 0xc(%rsp), %esi
jmp 0x3a353
movq 0x58(%rsp), %rax
leaq (%rax,%r13,8), %rcx
movq 0x50(%rsp), %rdi
movq %r15, %rsi
leaq 0x48(%rsp), %rdx
movq %r14, %r8
callq 0x6a333
addl %ebp, %r13d
movl %r13d, %esi
cmpq %rbx, %r12
movq 0x70(%rsp), %rax
movq 0x68(%rsp), %rcx
leaq 0x28(%rsp), %r15
leaq 0x10(%rsp), %rdx
jle 0x3a290
movq 0x40(%rsp), %rdi
callq 0x3330
movq 0x20(%rsp), %rdi
callq 0x3330
cmpq $0x0, 0xe0(%rsp)
je 0x3a3a8
movq 0x50(%rsp), %rdi
movq 0x80(%rsp), %rsi
movq 0x60(%rsp), %rdx
callq 0x39d0c
jmp 0x3a3af
xorl %eax, %eax
callq 0x6983a
addq $0xa8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nopl (%rax)
|
/GlobalArrays[P]ga/global/src/sparse.c
|
pnga_sprs_array_column_distribution
|
void pnga_sprs_array_column_distribution(Integer s_a, Integer iproc, Integer *lo,
Integer *hi)
{
Integer hdl = GA_OFFSET + s_a;
Integer nproc = SPA[hdl].nprocs;
Integer jdim = SPA[hdl].jdim;
*lo = (SPA[hdl].jdim*iproc)/nproc;
while (((*lo)*nproc)/jdim < iproc) {
(*lo)++;
}
while (((*lo)*nproc)/jdim > iproc) {
(*lo)--;
}
if (iproc < nproc-1) {
(*hi) = (jdim*(iproc+1))/nproc;
while (((*hi)*nproc)/jdim < iproc+1) {
(*hi)++;
}
while (((*hi)*nproc)/jdim > iproc+1) {
(*hi)--;
}
(*hi)--;
} else {
*hi = jdim-1;
}
}
|
pushq %r14
pushq %rbx
movq %rdx, %r8
leaq 0x9fcbb(%rip), %rax # 0xdc0c0
movq (%rax), %rax
imulq $0xc8, %rdi, %rdx
movq 0x30d48(%rax,%rdx), %r11
movq 0x30d90(%rax,%rdx), %rbx
movq %r11, %rax
imulq %rsi, %rax
cqto
idivq %rbx
movq %rax, %r9
leaq -0x1(%rax), %r14
movq %rbx, %r10
imulq %r14, %r10
leaq -0x2(%rax), %rdi
imulq %rbx, %rdi
imulq %rbx, %r9
movq %r9, %rax
cqto
idivq %r11
addq %rbx, %r10
addq %rbx, %rdi
incq %r14
addq %rbx, %r9
cmpq %rsi, %rax
jl 0x3c445
movq %r14, (%r8)
movq %r10, %rax
cqto
idivq %r11
cmpq %rsi, %rax
jle 0x3c484
decq %r14
movq %rdi, %rax
cqto
idivq %r11
subq %rbx, %rdi
cmpq %rsi, %rax
jg 0x3c46e
movq %r14, (%r8)
leaq -0x1(%rbx), %rax
cmpq %rsi, %rax
jle 0x3c4f8
leaq 0x1(%rsi), %r14
movq %r11, %rax
imulq %r14, %rax
cqto
idivq %rbx
movq %rax, %r8
leaq -0x1(%rax), %r10
movq %rbx, %r9
imulq %r10, %r9
leaq -0x2(%rax), %rdi
imulq %rbx, %rdi
imulq %rbx, %r8
movq %r8, %rax
cqto
idivq %r11
addq %rbx, %r9
addq %rbx, %rdi
incq %r10
addq %rbx, %r8
cmpq %rsi, %rax
jle 0x3c4b7
movq %r10, (%rcx)
movq %r9, %rax
cqto
idivq %r11
cmpq %r14, %rax
jle 0x3c4fb
decq %r10
movq %rdi, %rax
cqto
idivq %r11
subq %rbx, %rdi
cmpq %r14, %rax
jg 0x3c4e0
movq %r10, (%rcx)
jmp 0x3c4fb
movq %r11, %r10
decq %r10
movq %r10, (%rcx)
popq %rbx
popq %r14
retq
|
/GlobalArrays[P]ga/global/src/sparse.array.c
|
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