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#undef ROTATE |
#ifndef PEDANTIC |
# if defined(_MSC_VER) |
# if defined(_WIN64) /* applies to both IA-64 and AMD64 */ |
# include <stdlib.h> |
# pragma intrinsic(_rotl64) |
# define ROTATE(a,n) _rotl64((a),n) |
# endif |
# elif defined(__GNUC__) && __GNUC__>=2 |
# if defined(__x86_64) || defined(__x86_64__) |
# if defined(L_ENDIAN) |
# define ROTATE(a,n) ({ u64 ret; asm (""rolq %1,%0"" \ |
: ""=r""(ret) : ""J""(n),""0""(a) : ""cc""); ret; }) |
# elif defined(B_ENDIAN) |
/* |
* Most will argue that x86_64 is always little-endian. Well, yes, but |
* then we have stratus.com who has modified gcc to ""emulate"" |
* big-endian on x86. Is there evidence that they [or somebody else] |
* won't do same for x86_64? Naturally no. And this line is waiting |
* ready for that brave soul:-) |
*/ |
# define ROTATE(a,n) ({ u64 ret; asm (""rorq %1,%0"" \ |
: ""=r""(ret) : ""J""(n),""0""(a) : ""cc""); ret; }) |
# endif |
# elif defined(__ia64) || defined(__ia64__) |
# if defined(L_ENDIAN) |
# define ROTATE(a,n) ({ u64 ret; asm (""shrp %0=%1,%1,%2"" \ |
: ""=r""(ret) : ""r""(a),""M""(64-(n))); ret; }) |
# elif defined(B_ENDIAN) |
# define ROTATE(a,n) ({ u64 ret; asm (""shrp %0=%1,%1,%2"" \ |
: ""=r""(ret) : ""r""(a),""M""(n)); ret; }) |
# endif |
# endif |
# endif |
#endif |
#if defined(OPENSSL_SMALL_FOOTPRINT) |
# if !defined(ROTATE) |
# if defined(L_ENDIAN) /* little-endians have to rotate left */ |
# define ROTATE(i,n) ((i)<<(n) ^ (i)>>(64-n)) |
# elif defined(B_ENDIAN) /* big-endians have to rotate right */ |
# define ROTATE(i,n) ((i)>>(n) ^ (i)<<(64-n)) |
# endif |
# endif |
# if defined(ROTATE) && !defined(STRICT_ALIGNMENT) |
# define STRICT_ALIGNMENT /* ensure smallest table size */ |
# endif |
#endif |
/* |
* Table size depends on STRICT_ALIGNMENT and whether or not endian- |
* specific ROTATE macro is defined. If STRICT_ALIGNMENT is not |
* defined, which is normally the case on x86[_64] CPUs, the table is |
* 4KB large unconditionally. Otherwise if ROTATE is defined, the |
* table is 2KB large, and otherwise - 16KB. 2KB table requires a |
* whole bunch of additional rotations, but I'm willing to ""trade,"" |
* because 16KB table certainly trashes L1 cache. I wish all CPUs |
* could handle unaligned load as 4KB table doesn't trash the cache, |
* nor does it require additional rotations. |
*/ |
/* |
* Note that every Cn macro expands as two loads: one byte load and |
* one quadword load. One can argue that that many single-byte loads |
* is too excessive, as one could load a quadword and ""milk"" it for |
* eight 8-bit values instead. Well, yes, but in order to do so *and* |
* avoid excessive loads you have to accommodate a handful of 64-bit |
* values in the register bank and issue a bunch of shifts and mask. |
* It's a tradeoff: loads vs. shift and mask in big register bank[!]. |
* On most CPUs eight single-byte loads are faster and I let other |
* ones to depend on smart compiler to fold byte loads if beneficial. |
* Hand-coded assembler would be another alternative:-) |
*/ |
#ifdef STRICT_ALIGNMENT |
# if defined(ROTATE) |
# define N 1 |
# define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7 |
# define C0(K,i) (Cx.q[K.c[(i)*8+0]]) |
# define C1(K,i) ROTATE(Cx.q[K.c[(i)*8+1]],8) |
# define C2(K,i) ROTATE(Cx.q[K.c[(i)*8+2]],16) |
# define C3(K,i) ROTATE(Cx.q[K.c[(i)*8+3]],24) |
# define C4(K,i) ROTATE(Cx.q[K.c[(i)*8+4]],32) |
# define C5(K,i) ROTATE(Cx.q[K.c[(i)*8+5]],40) |
# define C6(K,i) ROTATE(Cx.q[K.c[(i)*8+6]],48) |
# define C7(K,i) ROTATE(Cx.q[K.c[(i)*8+7]],56) |
# else |
# define N 8 |
# define LL(c0,c1,c2,c3,c4,c5,c6,c7) c0,c1,c2,c3,c4,c5,c6,c7, \ |
c7,c0,c1,c2,c3,c4,c5,c6, \ |
c6,c7,c0,c1,c2,c3,c4,c5, \ |
c5,c6,c7,c0,c1,c2,c3,c4, \ |
c4,c5,c6,c7,c0,c1,c2,c3, \ |
c3,c4,c5,c6,c7,c0,c1,c2, \ |
c2,c3,c4,c5,c6,c7,c0,c1, \ |
c1,c2,c3,c4,c5,c6,c7,c0 |
# define C0(K,i) (Cx.q[0+8*K.c[(i)*8+0]]) |
# define C1(K,i) (Cx.q[1+8*K.c[(i)*8+1]]) |
# define C2(K,i) (Cx.q[2+8*K.c[(i)*8+2]]) |
# define C3(K,i) (Cx.q[3+8*K.c[(i)*8+3]]) |
# define C4(K,i) (Cx.q[4+8*K.c[(i)*8+4]]) |
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