repo_name
stringlengths 6
97
| path
stringlengths 3
341
| text
stringlengths 8
1.02M
|
|---|---|---|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/FB_W2100_SCU_MEA256/Device_config.h
|
#ifndef DEVICE_CONFIG_H_
#define DEVICE_CONFIG_H_
#define DEVICE_REGISTER(reg) (*(volatile Uint32 *)(0xa0000000+(reg<<2)))
// enable for W2100
#define _W2100
// enable for SCU based devices
//#define _SCU
#define INCLUDE_HS1_DATA
//#define INCLUDE_HS2_DATA
#define INCLUDE_IF_DATA
//#define INCLUDE_HS2_FILTER_DATA
//#define INCLUDE_DIGITAL_DATA
//#define INCLUDE_TIMESTAMP_DATA
#ifdef INCLUDE_HS1_DATA
#ifdef _W2100
#define HS1_CHANNELS 48
#define HS1_DATA_ENABLE 0x0000001F
#define NUM_SEG_HS1 5
#elif defined _SCU
#define HS1_CHANNELS 256
#define HS1_DATA_ENABLE 0xF
#define NUM_SEG_HS1 4
#else
#define HS1_CHANNELS 256
#define HS1_DATA_ENABLE 0x1
#define NUM_SEG_HS1 1
#endif
#else
#define HS1_CHANNELS 0
#define HS1_DATA_ENABLE 0
#define NUM_SEG_HS1 0
#endif
#ifdef INCLUDE_HS2_DATA
#ifdef _W2100
#define HS2_CHANNELS 48
#define HS2_DATA_ENABLE 0x0000001F
#define NUM_SEG_HS2 5
#elif defined _SCU
#define HS2_CHANNELS 256
#define HS2_DATA_ENABLE 0xF
#define NUM_SEG_HS2 4
#else
#define HS2_CHANNELS 256
#define HS2_DATA_ENABLE 0x1
#define NUM_SEG_HS2 1
#endif
#else
#define HS2_CHANNELS 0
#define HS2_DATA_ENABLE 0
#define NUM_SEG_HS2 0
#endif
#ifdef INCLUDE_IF_DATA
#define IF_CHANNELS 8
#define IF_DATA_ENABLE 1
#define NUM_SEG_IF 1
#else
#define IF_CHANNELS 0
#define IF_DATA_ENABLE 0
#define NUM_SEG_IF 0
#endif
#ifdef INCLUDE_DIGITAL_DATA // for now, 8 channels of digital data from interfaceboard
#define DIGITAL_CHANNELS 8
#define DIGITAL_DATA_ENABLE 1
#define NUM_SEG_DIGITAL 1
#else
#define DIGITAL_CHANNELS 0
#define DIGITAL_DATA_ENABLE 0
#define NUM_SEG_DIGITAL 0
#endif
#ifdef INCLUDE_TIMESTAMP_DATA
#define TIMESTAMP_CHANNELS 2
#define TIMESTAMP_DATA_ENABLE 1
#define NUM_SEG_TIMESTAMP 1
#else
#define TIMESTAMP_CHANNELS 0
#define TIMESTAMP_DATA_ENABLE 0
#define NUM_SEG_TIMESTAMP 0
#endif
#define MAX_DATAPOINTS_PER_FRAME 512
#define NUM_SEGMENTS (NUM_SEG_HS1 + NUM_SEG_HS2 + NUM_SEG_IF + NUM_SEG_DIGITAL + NUM_SEG_TIMESTAMP)
#ifdef _W2100
#define INDATA_CONFIG0_VALUE 0
#define INDATA_CONFIG1_VALUE (HS1_DATA_ENABLE)
#define INDATA_CONFIG2_VALUE (HS2_DATA_ENABLE)
#define INDATA_CONFIG3_VALUE (IF_DATA_ENABLE)
#define INDATA_CONFIG4_VALUE 0
#define INDATA_CONFIG5_VALUE 0
#define INDATA_CONFIG6_VALUE 0
#define INDATA_CONFIG7_VALUE (DIGITAL_DATA_ENABLE)
#define INDATA_CONFIG8_VALUE 0
#define INDATA_CONFIG9_VALUE 0
#define INDATA_CONFIGa_VALUE 0
#define INDATA_CONFIGb_VALUE 0
#define INDATA_CONFIGc_VALUE 0
#define INDATA_CONFIGd_VALUE 0
#define INDATA_CONFIGe_VALUE 0
#define INDATA_CONFIGf_VALUE (TIMESTAMP_DATA_ENABLE)
#else
#define INDATA_CONFIG0_VALUE 0
#define INDATA_CONFIG1_VALUE (HS1_DATA_ENABLE)
#define INDATA_CONFIG2_VALUE 0
#define INDATA_CONFIG3_VALUE 0
#define INDATA_CONFIG4_VALUE 0
#define INDATA_CONFIG5_VALUE (HS2_DATA_ENABLE)
#define INDATA_CONFIG6_VALUE 0
#define INDATA_CONFIG7_VALUE 0
#define INDATA_CONFIG8_VALUE 0
#define INDATA_CONFIG9_VALUE (IF_DATA_ENABLE)
#define INDATA_CONFIGa_VALUE 0
#define INDATA_CONFIGb_VALUE 0
#define INDATA_CONFIGc_VALUE 0
#define INDATA_CONFIGd_VALUE (DIGITAL_DATA_ENABLE)
#define INDATA_CONFIGe_VALUE 0
#define INDATA_CONFIGf_VALUE (TIMESTAMP_DATA_ENABLE)
#endif
#endif /* DEVICE_CONFIG_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcExcep.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/**
* @file csl_intcExcep.c
*
* @brief File for functional layer of CSL Exceptions APIs
*
* PATH $(CSLPATH)\src\intc
*/
/* =============================================================================
* Revision History
* ===============
* 12-Jun-2004 <NAME> File Created
*
* 16-Mar-2005 brn modified for doxygen documentation
* =============================================================================
*/
#include <csl_intc.h>
/** ============================================================================
* @n@b CSL_intcExcepAllEnable
*
* @b Description
* @n This enables the events as specified in the bitmask in either
* EXPMASK0/1/2/3.
*
* @b Arguments
* @verbatim
excepMask Exception Mask
excVal Event Value
prevState Previous state information
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Intc Excep All Enable return successful
*
* <b> Pre Condition </b>
* @n CSL_intcInit() must be called before use of this API.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_IntcContext context;
CSL_Status intcStat;
CSL_IntcParam vectId;
CSL_IntcEventHandlerRecord recordTable[10];
CSL_IntcGlobalEnableState prevState;
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK) {
exit;
// Enable exception events 9,10,11.
intcStat = CSL_intcExcepAllEnable(CSL_INTC_EXCEP_0TO31,
0x0F00,&prevState);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_intcExcepAllEnable, ".text:csl_section:intc");
CSL_Status CSL_intcExcepAllEnable (
CSL_IntcExcepEn excepMask,
CSL_BitMask32 excVal,
CSL_BitMask32 *prevState
)
{
CSL_Status stat = CSL_SOK;
if ((prevState) && ((excepMask >= 0) && (excepMask <= 3))) {
*prevState = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[excepMask];
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[excepMask] &= ~excVal;
}
else {
stat = CSL_ESYS_INVPARAMS;
}
return (stat);
}
/** ============================================================================
* @n@b CSL_intcExcepAllDisable
*
* @b Description
* @n This disables the events as specified in the bitmask in either
* EXPMASK0/1/2/3.
*
* @b Arguments
* @verbatim
excepMask Exception Mask
excVal Event Value
prevState Pre state information
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Intc Excep All Disable return successful
*
* <b> Pre Condition </b>
* @n CSL_intcInit() must be called before use of this API.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_IntcContext context;
CSL_Status intcStat;
CSL_IntcParam vectId;
CSL_IntcEventHandlerRecord recordTable[10];
CSL_IntcGlobalEnableState prevState;
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK) {
exit;
// Enable exception events 9,10,11.
intcStat = CSL_intcExcepAllDisable(CSL_INTC_EXCEP_0TO31, \
0x0F00,&prevState);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_intcExcepAllDisable, ".text:csl_section:intc");
CSL_Status CSL_intcExcepAllDisable (
CSL_IntcExcepEn excepMask,
CSL_BitMask32 excVal,
CSL_BitMask32 *prevState
)
{
CSL_Status stat = CSL_SOK;
if ((prevState) && ((excepMask >= 0) && (excepMask <= 3))) {
*prevState = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[excepMask];
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[excepMask] |= excVal;
}
else {
stat = CSL_ESYS_INVPARAMS;
}
return (stat);
}
/** ============================================================================
* @n@b CSL_intcExcepAllRestore
*
* @b Description
* @n This restores the exception enable mask.
*
* @b Arguments
* @verbatim
excepMask Exception Mask
restoreVal BitMask to be restored
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Intc Excep All Restore return successful
*
* <b> Pre Condition </b>
* @n CSL_intcInit() and CSL_intcExcepAllDisable()/CSL_intcExcepAllEnable()
* must be called before use of this API
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_IntcContext context;
CSL_Status intcStat;
CSL_IntcParam vectId;
CSL_bitMask32 exp0Stat;
CSL_IntcEventHandlerRecord recordTable[10];
CSL_IntcGlobalEnableState prevState;
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK) {
exit;
intcStat = CSL_intcExcepAllDisable(CSL_INTC_EXCEP_0TO31,0x0F00, \
&prevState);
// Restore
intcStat = CSL_intcExcepAllRestore(CSL_INTC_EXCEP_0TO31,prevState);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_intcExcepAllRestore, ".text:csl_section:intc");
CSL_Status CSL_intcExcepAllRestore (
CSL_IntcExcepEn excepMask,
CSL_IntcGlobalEnableState restoreVal
)
{
CSL_Status stat = CSL_SOK;
if ((excepMask >= 0) && (excepMask <= 3)) {
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EXPMASK[excepMask] = restoreVal;
}
else {
stat = CSL_ESYS_INVPARAMS;
}
return (stat);
}
/** ============================================================================
* @n@b CSL_intcExcepAllClear
*
* @b Description
* @n This clears the exception flags.
*
* @b Arguments
* @verbatim
excepMask Exception Mask
excVal Holder for the event bitmask to be cleared
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Intc Excep All Clear return successful
*
* <b> Pre Condition </b>
* @n CSL_intcInit() and CSL_intcExcepAllEnable() must be called before
* use of this API
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_IntcContext context;
CSL_Status intcStat;
CSL_IntcParam vectId;
CSL_IntcEventHandlerRecord recordTable[10];
CSL_IntcGlobalEnableState prevState;
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK) {
exit;
// Clear exception events 9,10,11.
intcStat = CSL_intcExcepAllClear(CSL_INTC_EXCEP_0TO31,0x0F00);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_intcExcepAllClear, ".text:csl_section:intc");
CSL_Status CSL_intcExcepAllClear (
CSL_IntcExcepEn excepMask,
CSL_BitMask32 excVal
)
{
CSL_Status stat = CSL_SOK;
if ((excepMask >= 0) && (excepMask <= 3)) {
((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->EVTCLR[excepMask] = excVal;
}
else{
stat = CSL_ESYS_INVPARAMS;
}
return (stat);
}
/** ============================================================================
* @n@b CSL_intcExcepAllStatus
*
* @b Description
* @n This obtains the status of the exception flags
*
* @b Arguments
* @verbatim
excepMask Exception Mask
excVal Holder for the event bitmask to be cleared
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - intc Excep All Status return successful
*
* <b> Pre Condition </b>
* @n CSL_intcInit() must be called before use of this API
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_IntcContext context;
CSL_Status intcStat;
CSL_IntcParam vectId;
CSL_bitMask32 exp0Stat;
CSL_IntcEventHandlerRecord recordTable[10];
CSL_IntcGlobalEnableState prevState;
context.numEvtEntries = 10;
context.eventhandlerRecord = &recordTable;
// Init Module
...
if (CSL_intcInit(&context) != CSL_SOK) {
exit;
intcStat = CSL_intcExcepAllStatus(CSL_INTC_EXCEP_0TO31,&exp0Stat);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_intcExcepAllStatus, ".text:csl_section:intc");
CSL_Status CSL_intcExcepAllStatus (
CSL_IntcExcepEn excepMask,
CSL_BitMask32 *status
)
{
CSL_Status stat = CSL_SOK;
if ((status) && ((excepMask >= 0) && (excepMask <= 3))) {
*status = ((CSL_IntcRegsOvly)CSL_INTC_0_REGS)->MEXPFLAG[excepMask] ;
}
else {
stat = CSL_ESYS_INVPARAMS;
}
return (stat);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/srio/csl_srioHwControl.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/srio/csl_srioHwControl.c<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* =============================================================================
*/
/** ===========================================================================
* @file csl_srioHwControl.c
*
* @brief File for functional layer of CSL API CSL_srioHwControl()
*
* @path $(CSLPATH)\srio\src
*
* @desc The CSL_srioHwControl() function definition and it's associated
* functions
*/
/* ============================================================================
* Revision History
* ===============
* 24-Aug-2005 PSK File Created.
* ============================================================================
*/
#include <csl_srio.h>
#include <csl_srioAux.h>
/** ============================================================================
* @n@b CSL_srioHwControl
*
* @b Description
* @n This function performs various control operations on the SRIO instance,
* based on the command passed.
*
* @b Arguments
* @verbatim
hSrio Handle to the SRIO instance
cmd Operation to be performed on the SRIO
cmdArg Arguement specific to the command
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command execution successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Registers of the SRIO instance are configured according to the command
* and the command arguments. The command determines which registers are
* modified.
*
* @b Modifies
* @n Registers determined by the command
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioPortData clearData;
CSL_Status status;
Uint32 mask;
Uint8 index;
...
// for clearing LSU interrupts status [0..3]
index = 1;
mask = CSL_SRIO_LSU_INTR3 | CSL_SRIO_LSU_INTR2 |
CSL_SRIO_LSU_INTR1 | CSL_SRIO_LSU_INTR0;
clearData.index = index;
clearData.data = mask;
...
CSL_srioHwControl(hSrio, CSL_SRIO_CMD_LSU_INTR_CLEAR, &clearData);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_srioHwControl, ".text:csl_section:srio");
CSL_Status CSL_srioHwControl (
CSL_SrioHandle hSrio,
CSL_SrioHwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK ;
if (hSrio == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (arg == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (cmd) {
/* Enables/disables the peripheral */
case CSL_SRIO_CMD_PER_ENABLE:
CSL_SrioPerEn(hSrio, *(Bool*)arg);
break;
/* Enable/disable the SERDES PLLs */
case CSL_SRIO_CMD_PLL_CONTROL:
CSL_SrioPllCntlSet(hSrio, *(Uint8 *)arg);
break;
/* Clears doorbell interrupts */
case CSL_SRIO_CMD_DOORBELL_INTR_CLEAR:
CSL_SrioDoorbellIntrClear(hSrio, (CSL_SrioPortData *)arg);
break;
/* Clear load/store module interrupts */
case CSL_SRIO_CMD_LSU_INTR_CLEAR:
CSL_SrioLsuIntrClear(hSrio, *(Uint32 *)arg);
break;
/* Clears Error, Reset, and Special Event interrupts */
case CSL_SRIO_CMD_ERR_RST_INTR_CLEAR:
CSL_SrioErrRstIntrClear(hSrio, *(Uint32 *)arg);
break;
/* Sets 32-bit DSP byte source address */
case CSL_SRIO_CMD_DIRECTIO_SRC_NODE_ADDR_SET:
CSL_SrioSrcAddrSet(hSrio, (CSL_SrioPortData *)arg);
break;
/* Sets the rapid IO destination MSB address */
case CSL_SRIO_CMD_DIRECTIO_DST_ADDR_MSB_SET:
CSL_SrioDstAddrMsbSet(hSrio, (CSL_SrioPortData *)arg);
break;
/* Sets the rapid IO destination LSB address */
case CSL_SRIO_CMD_DIRECTIO_DST_ADDR_LSB_SET:
CSL_SrioDstAddrLsbSet(hSrio, (CSL_SrioPortData *)arg);
break;
/* Number of data bytes to Read/Write - up to 4KB */
case CSL_SRIO_CMD_DIRECTIO_XFR_BYTECNT_SET:
CSL_SrioLsuXfrByteCntSet(hSrio, (CSL_SrioPortData *)arg);
break;
/* sets the LSU transfer type */
case CSL_SRIO_CMD_DIRECTIO_LSU_XFR_TYPE_SET:
CSL_SrioLsuXfrTypeSet(hSrio, (CSL_SrioPortData *)arg);
break;
/* Sets RapidIO doorbell info field for type 10 packets */
case CSL_SRIO_CMD_DOORBELL_XFR_SET:
CSL_SrioDoorbellXfrTypeSet(hSrio, (CSL_SrioPortData *)arg);
break;
/* Sets LSU flow masks */
case CSL_SRIO_CMD_DIRECTIO_LSU_FLOW_MASK_SET:
CSL_SrioLsuFlowMaskSet(hSrio, (CSL_SrioPortData *)arg);
break;
/* Sets the command to be sent in link-request control symbol */
case CSL_SRIO_CMD_PORT_COMMAND_SET:
CSL_SrioPortCmdSet(hSrio, (CSL_SrioPortData *)arg);
break;
/* Clear port errors status of SP_ERR_STAT register */
case CSL_SRIO_CMD_SP_ERR_STAT_CLEAR:
CSL_SrioSpErrStatClear(hSrio, (CSL_SrioPortData *)arg);
break;
/* Clear status of Logical/Transport layer errors */
case CSL_SRIO_CMD_LGCL_TRANS_ERR_STAT_CLEAR:
CSL_SrioLgclTrnsErrStatClear(hSrio, *(Uint32 *)arg);
break;
/* Clears status of port errors interrupts of SP_ERR_DET register */
case CSL_SRIO_CMD_SP_ERR_DET_STAT_CLEAR:
CSL_SrioSpErrDetStatClear(hSrio, (CSL_SrioPortData *)arg);
break;
/* clears status of the fields of SP_CTL_INDEP_ERR register*/
case CSL_SRIO_CMD_SP_CTL_INDEP_ERR_STAT_CLEAR:
CSL_SrioSpCtlIndepErrStatClear(hSrio, (CSL_SrioPortData *)arg);
break;
/* Set control symbols used for packet acknowledgment */
case CSL_SRIO_CMD_CNTL_SYM_SET:
CSL_SrioCntlSymSet(hSrio, (CSL_SrioCntlSym *)arg);
break;
/* sets interrupt rate control counter */
case CSL_SRIO_CMD_INTDST_RATE_CNTL:
CSL_SrioSetIntdstRateCntl(hSrio, *(Uint32 *)arg);
break;
default:
status = CSL_ESYS_INVCMD;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_pwrdwn.h
|
<filename>DSP/TI-Header/csl_c6455_src/inc/csl_pwrdwn.h
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ===========================================================================
* @mainpage PWRDOWN CSL 3.x
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to describe the common API's and data
* structures for the power Down Module module.
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
*
* @subsection References
* -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
* ===========================================================================
*/
/** ===========================================================================
* @file csl_pwrdwn.h
*
* @brief Header file for functional layer of CSL
*
* @path $(CSLPATH)\inc
*
* Description
* - The different enumerations, structure definitions
* and function declarations
*
* Modification 1
* - modified on: 07/17/2004
* - reason: Created
* @date 17th July, 2004
* @author <NAME>
* ===========================================================================
*/
#ifndef _CSL_PWRDWN_H_
#define _CSL_PWRDWN_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <soc.h>
#include <cslr_pwrdwnPdc.h>
#include <cslr_pwrdwnL2.h>
/**************************************************************************\
* PWRDWN global macro declarations
\**************************************************************************/
/** @brief Enumeration for queries passed to @a CSL_pwrdwnGetHwStatus()
*
* This is used to get the status of different operations or to get the
* existing setup of PWRDWN.
*/
typedef enum {
/** Gets the page0 sleep status
* @param (CSL_PwrdwnPortData *)
*/
CSL_PWRDWN_QUERY_PAGE0_STATUS,
/** Gets the page1 sleep status
* @param (CSL_PwrdwnPortData *)
*/
CSL_PWRDWN_QUERY_PAGE1_STATUS
} CSL_PwrdwnHwStatusQuery;
/** @brief Enumeration for queries passed to @a CSL_pwrdwnHwControl()
*
* This is used to select the commands to control the operations
* existing setup of PWRDWN. The arguments to be passed with each
* enumeration if any are specified next to the enumeration.
*/
typedef enum {
/** manual power down, port0 or port1, page0 sleep
* @param (CSL_PwrdwnPortData *)
*/
CSL_PWRDWN_CMD_PAGE0_SLEEP,
/** manual power down, port0 or port1, page1 sleep
* @param (CSL_PwrdwnPortData *)
*/
CSL_PWRDWN_CMD_PAGE1_SLEEP,
/** manual power down, port0 or port1, page0 wake
* @param (CSL_PwrdwnPortData *)
*/
CSL_PWRDWN_CMD_PAGE0_WAKE,
/** manual power down, port0 or port1, page1 wake
* @param (CSL_PwrdwnPortData *)
*/
CSL_PWRDWN_CMD_PAGE1_WAKE
} CSL_PwrdwnHwControlCmd;
/**************************************************************************\
* PWRDWN global typedef declarations
\**************************************************************************/
/** @brief This object contains the reference to the instance of PWRDWN opened
* using the @a CSL_pwrdwnOpen().
*/
typedef struct {
/** This is a pointer to the registers of the instance of PDC
* referred to by this object
*/
CSL_PdcRegsOvly pdcRegs;
/** This is a pointer to the registers of the instance of L2 PWRDWN
* referred to by this object
*/
CSL_L2pwrdwnRegsOvly l2pwrdwnRegs;
/** This is the instance of PWRDWN being referred to by this object */
CSL_InstNum instNum;
} CSL_PwrdwnObj;
/** @brief Pointer to the powerdown object. This handle contains the reference to the
* instance of PWRDWN opened @a CSL_pwrdwnOpen().
*
* The pointer to this, is passed to all PWRDWN CSL APIs.
*/
typedef CSL_PwrdwnObj *CSL_PwrdwnHandle;
/** @brief This will have the base-address information for the module
* instance
*/
typedef struct {
/** Base-address of the PDC registers */
CSL_PdcRegsOvly regs;
/** Base-address of the L2 Powerdown registers */
CSL_L2pwrdwnRegsOvly l2pwrdwnRegs;
} CSL_PwrdwnBaseAddress;
/** @brief Module specific parameters. None in this implementation.
*/
typedef struct{
/** Perhaps useful for future use */
void *futureUse;
} CSL_PwrdwnParam;
/** @brief Module specific context information. Present implementation doesn't have
* any Context information.
*/
typedef struct {
/** Context information of PWRDWN.
* The below declaration is just a place-holder for future
* implementation. This is a Dummy.
*/
Uint16 contextInfo;
} CSL_PwrdwnContext;
typedef struct {
/** port number */
Bool portNum;
/** 8-bit mask */
CSL_BitMask8 data;
} CSL_PwrdwnPortData;
/**
* @brief The manual powerdown setup structure
*
*/
typedef struct {
/** Bitmask of the pages that need to be woken on UMAP0 */
CSL_BitMask8 port0PageWake;
/** Bitmask of the pages that need to be woken on UMAP1 */
CSL_BitMask8 port1PageWake;
/** Bitmask of the pages that need to be put to sleep on UMAP0 */
CSL_BitMask8 port0PageSleep;
/** Bitmask of the pages that need to be put to sleep on UMAP1 */
CSL_BitMask8 port1PageSleep;
} CSL_PwrdwnL2Manual;
/** @brief This has all the fields required to configure PWRDWN at Power Up
* (After a Hardware Reset) or a Soft Reset
*
* This structure is used to setup or obtain existing setup of
* PWRDWN using @a CSL_pwrdwnHwSetup() & @a CSL_pwrdwnGetHwSetup() functions
* respectively.
*/
typedef struct {
/** idle powerdown */
Bool idlePwrdwn;
/** Manual power down setup */
CSL_PwrdwnL2Manual *manualPwrdwn;
} CSL_PwrdwnHwSetup;
/**
* @brief The config-structure
*
* Used to configure the PWRDWN using CSL_pwrdwnHwSetupRaw(..)
*/
typedef struct {
/**< PDCCMD register */
Uint32 PDCCMD;
/**< Per page manual awake port0 */
Uint32 L2PDWAKE0;
/**< Per page manual awake for port1 */
Uint32 L2PDWAKE1;
/**< Per page manual sleep for port0 */
Uint32 L2PDSLEEP0;
/**< Per page manual sleep for port1 */
Uint32 L2PDSLEEP1;
} CSL_PwrdwnConfig;
/**************************************************************************\
* PWRDWN global function declarations
\**************************************************************************/
/**
* ============================================================================
* @brief Initializes the module
*
* CSL_pwrdwnInit(..) initializes the PWRDWN module.
* This function is idempotent -- calling it several times would
* have the same effect as calling it the first time.
* This function initializes the CSL data structures, and doesn't
* touches the hardware.
*
* @b Arguments
* @verbatim
pContext Pointer to module-context. As PWRDWN doesn't have any
context based information user is expected to pass NULL.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The PWRDWN module is initialized
*
* @b Modifies
* @n None
*
* Note: As PWRDWN doesn't have any context based information, the function
* just returns CSL_SOK. User is expected to pass NULL.
*
* @b Example
* @verbatim
...
if (CSL_SOK != CSL_pwrdwnInit(NULL)) {
return;
}
@endverbatim
* ============================================================================
*/
CSL_Status CSL_pwrdwnInit (
/* PWRDWN specific context information
*/
CSL_PwrdwnContext *pContext
);
/** ============================================================================
* @b CSL_ pwrdwnOpen
*
* @b Description
* @n This function populates the peripheral data object for the PWRDWN
* instance and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of PWRDWN device. The device can be re-opened anytime after it has been
* normally closed if so required. The handle returned by this call is
* input as an essential argument for rest of the APIs described
* for this module.
*
* @b Arguments
* @verbatim
pwrdwnObj Pointer to PWRDWN object.
pwrdwnNum Instance of pwrdwn CSL to be opened.
There are three instance of the PWRDWN
available. So, the value for this parameter will be
based on the instance.
pPwrdwnParam Module specific parameters.
status Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_pwrdwnHandle
* @n Valid pwrdwn handle will be returned if
* status value is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen()must be opened prior to this call
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid pwrdwn handle is returned
* @li CSL_ESYS_FAIL The pwrdwn instance is invalid
*
* 2. pwrdwn object structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. pwrdwn object structure
*
* @b Example
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments fof the Config structure
...
@endverbatim
* ============================================================================
*/
CSL_PwrdwnHandle CSL_pwrdwnOpen (
/* Pointer to the object that holds reference to the
* instance of PWRDWN requested after the call
*/
CSL_PwrdwnObj *hPwrdwnObj,
/* Instance of PWRDWN to which a handle is requested
*/
CSL_InstNum pwrdwnNum,
/* Module specific parameters;
* Currently there are none; the user should pass 'NULL'
*/
CSL_PwrdwnParam *hPwrdwnParam,
/* This returns the status (success/errors) of the call.
* Could be 'NULL' if the user does not want status information.
*/
CSL_Status *hStatus
);
/** ===========================================================================
* @n@b CSL_pwrdwnClose
*
* @b Description
* @n This function closes the specified instance of pwrdwn.
*
* @b Arguments
* @verbatim
hPwrdwn Handle to the PWRDWN instance
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call.
*
* <b> Post Condition </b>
* @n 1. The PWRDWN CSL APIs can not be called until the PWRDWN
* CSL is reopened again using CSL_pwrdwnOpen()
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen(&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments fof the Config structure
...
// Close
CSL_pwrdwnClose(hPwr);
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_pwrdwnClose (
/* Pointer to the object that holds reference to the
* instance of PWRDWN requested after the call
*/
CSL_PwrdwnHandle hPwrdwn
);
/** ===========================================================================
* @n@b CSL_pwrdwnHwSetup
*
* @b Description
* @n It configures the PWRDWN instance registers as per the values passed
* in the hardware setup structure.
*
* @b Arguments
* @verbatim
hPwrdwn Handle to the pwrdwn instance
setup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Hardware structure is not
* properly initialized
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call
*
* <b> Post Condition </b>
* @n The specified instance will be setup according to value passed
*
* @b Modifies
* @n Hardware registers for the specified instance
*
* @b Example:
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnHwSetup pwrSetup;
CSL_PwrdwnHandle hPwr;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Setup structure
...
// Setup
CSL_pwrdwnHwSetup(hPwr,&pwrSetup);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbatim
* ============================================================================
*/
CSL_Status CSL_pwrdwnHwSetup (
/* Pointer to the object that holds reference to the
* instance of PWRDWN. */
CSL_PwrdwnHandle hPwrdwn,
/* Pointer to setup structure which contains the
* information to program PWRDWN to a useful state
*/
CSL_PwrdwnHwSetup *setup
);
/** ===========================================================================
* @n@b CSL_pwrdwnGetHwSetup
*
* @b Description
* @n It retrives the hardware setup parameters
*
* @b Arguments
* @verbatim
hPwr Handle to the PWRDWN instance
hwSetup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup retrived
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @b CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call.
*
* <b> Post Condition </b>
* @n The hardware set up structure will be populated with values from
* the registers
*
* @b Modifies
* @n None
*
* @b Example
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnHwSetup pwrSetup,querySetup;
CSL_PwrdwnHandle hPwr;
CSL_BitMask32 pageSleep;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Setup structure
...
// Setup
CSL_pwrdwnHwSetup(hPwr,&pwrSetup);
// Query Setup
CSL_pwrdwnGetHwSetup(hPwr,&querySetup);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbatim
* ============================================================================
*/
CSL_Status CSL_pwrdwnGetHwSetup (
/* Pointer to the object that holds reference to the
* instance of PWRDWN requested after the call
*/
CSL_PwrdwnHandle hPwrdwn,
/* Pointer to setup structure which contains the
* information to program PWRDWN to a useful state
*/
CSL_PwrdwnHwSetup *setup
);
/** ===========================================================================
* @n@b CSL_pwrdwnHwControl
*
* @b Description
* @n This function performs various control operations on the PWRDWN instance,
* based on the command passed.
*
* @b Arguments
* @verbatim
hPwrdwn Handle to the PWRDWN instance
cmd Operation to be performed on the PWRDWN
cmdArg Arguement specific to the command
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command execution successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
*
* <b> Pre Condition </b>
* CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call
*
* <b> Post Condition </b>
* @n Registers of the PWRDWN instance are configured according to the command
* and the command arguments. The command determines which registers are
* modified.
*
* @b Modifies
* @n Registers determined by the command
*
* @b Example:
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnHwSetup pwrSetup;
CSL_PwrdwnHandle hPwr;
CSL_PwrdwnPortData pageSleep;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Setup structure
...
// Setup
CSL_pwrdwnHwSetup(hPwr,&pwrSetup);
// Hw Control
pageSleep.portNum = 0x0;
pageSleep.data = 0x0;
CSL_pwrdwnHwControl(hPwr,CSL_PWRDWN_CMD_PAGE0_SLEEP,&pageSleep);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbtim
* ============================================================================
*/
CSL_Status CSL_pwrdwnHwControl (
/* Pointer to the object that holds reference to the
* instance of PWRDWN.
*/
CSL_PwrdwnHandle hPwrdwn,
/* The command to this API indicates the action to be taken
*/
CSL_PwrdwnHwControlCmd cmd,
/* An optional argument @a void* casted
*/
void *arg
);
/** ===========================================================================
* @n@b CSL_pwrdwnGetHwStatus
*
* @b Description
* @n This function is used to get the value of various parameters of the
* PWRDWN instance. The value returned depends on the query passed.
*
* @b Arguments
* @verbatim
hPwr Handle to the PWRDWN instance
query Query to be performed
response Pointer to buffer to return the data requested by
the query passed
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Successful completion of the
* query
*
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* @li CSL_ESYS_INVQUERY - Query command not supported
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call
*
* <b> Post Condition </b>
* Data requested by the query is returned through the variable "response"
*
* @b Modifies
* @n The input arguement "response" is modified
*
* @b Example:
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnHwSetup pwrSetup;
CSL_PwrdwnHandle hPwr;
CSL_PwrdwnPortData pageSleep;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Setup structure
...
// Setup
//
CSL_pwrdwnHwSetup(hPwr,&pwrSetup);
// Hw Status Query
pageSleep.portNum = 0x0;
CSL_pwrdwnGetHwStatus(hPwr,CSL_PWRDWN_QUERY_PAGE0_STATUS,&pageSleep);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbatim
* ============================================================================
*/
CSL_Status CSL_pwrdwnGetHwStatus (
/* Pointer to the object that holds reference to the
* instance of PWRDWN requested after the call
*/
CSL_PwrdwnHandle hPwrdwn,
/* The query to this API which indicates the status
* to be returned
*/
CSL_PwrdwnHwStatusQuery query,
/* Placeholder to return the status. @a void* casted */
void *response
);
/** ============================================================================
* @n@b CSL_pwrdwnGetBaseAddress
*
* @b Description
* @n This function gets the base address of the given pwrdwn
* instance.
*
* @b Arguments
* @verbatim
hPwrdwn Pointer to the peripheral data object for pwrdwn
pwrdwnNum Specifies the instance of the pwrdwn to be
opened.
pPwrdwnParam pwrdwn module specific parameters.
pBaseAddress Pointer to base address structure containing base
address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Open call is successful
* @li CSL_ESYS_FAIL pwrdwn instance is not
* available.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure is modified.
*
* @b Example
* @verbatim
CSL_PwrdwnHandle hPwrdwn;
CSL_PwrdwnBaseAddress baseAddress;
CSL_PwrdwnParam params;
CSL_pwrdwnGetBaseAddress(CSL_PWRDWN, ¶ms, &baseAddress) ;
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_pwrdwnGetBaseAddress (
/* Instance number */
CSL_InstNum pwrdwnNum,
/* Module specific parameters */
CSL_PwrdwnParam *hPwrdwnParam,
/* Base address details */
CSL_PwrdwnBaseAddress *pBaseAddress
);
/** ===========================================================================
* @n@b CSL_pwrdwnHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the config data structure.
*
* @b Arguments
* @verbatim
hPwrdwn Pointer to the object that holds reference to the
instance of PWRDWN requested after the call
config Pointer to the config structure containing the
device register values
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration structure
* pointer is not properly
* initialized
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call
*
* <b> Post Condition </b>
* @n The registers of the specified PWRDWN instance will be setup
* according to the values passed through the config structure
*
* @b Modifies
* @n Hardware registers of the specified PWRDWN instance
*
* @b Example
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Config structure
...
// Setup
CSL_pwrdwnHwSetupRaw(hPwr,&pwrConfig);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbatim
* ============================================================================
*/
CSL_Status CSL_pwrdwnHwSetupRaw (
/* Pointer to the object that holds reference to the
* instance of PWRDWN requested after the call
*/
CSL_PwrdwnHandle hPwrdwn,
/* Pointer to config structure which contains the
* register values to program PWRDWN to a useful state
*/
CSL_PwrdwnConfig *config
);
#ifdef __cplusplus
}
#endif
#endif /* _CSL_PWRDWN_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/FB_W2100_SCU_MEA256/main.c
|
#include <stdio.h>
#include <string.h>
#include <cslr_pllc.h>
#include <cslr_gpio.h>
#include <cslr_emifa.h>
#include <cslr_ddr2.h>
#include <cslr_dev.h>
#include <cslr_intc.h>
#include <cslr_chip.h>
#include <cslr_edma3cc.h>
#include <soc.h>
#include <c6x.h>
#include "main.h"
#include "version.h"
#include "Device_lib.h"
#include "Stimulation.h"
char dsp_version[] = "(>)"SW_STRING"(<)";
int initFromMailbox(int mailboxRegister, int defaultValue)
{
int value = READ_REGISTER(MAILBOX_BASE + mailboxRegister);
if (!value)
{
return defaultValue;
}
else
{
return value;
}
}
void main()
{
volatile int i;
MEA21_init();
WRITE_REGISTER(IFB_AUX_DIR, 0x3); // set AUX 1 and 2 as output
MEA21_enableData();
threshold = initFromMailbox(MAILBOX_THRSHOLD, 0);
deadtime = initFromMailbox(MAILBOX_DEADTIME, 0);
StimAmplitude = initFromMailbox(MAILBOX_AMPLITUDE, 100);
StimDuration = initFromMailbox(MAILBOX_DURATION, 5);
StimRepeats = initFromMailbox(MAILBOX_REPEATS, 1);
StimStepsize = initFromMailbox(MAILBOX_STEPSIZE, 1);
WRITE_REGISTER(IFB_AUX_OUT, 0x0); // set AUX 1 to value 0
WRITE_REGISTER(IFB_AUX_OUT, 0x1); // set AUX 1 to value one
// Do not use for W2100: STG there works differently
//UploadBiphaseRect(0, 0, StimAmplitude, StimDuration, StimRepeats);
// other segments not implemented yet
// UploadBiphaseRect(0, 1, StimAmplitude, StimPeriod, StimRepeats);
WRITE_REGISTER(IFB_AUX_OUT, 0x0); // set AUX 1 to value 0
SetupTrigger();
WRITE_REGISTER(DIGITAL_MUX, 0x42080200); // Sideband data 0 HS 1 (0x42) bit 8 to Digital Out (0x02) bit 0
while(1)
{
}
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/dat/src/Dat_example.c
|
<filename>DSP/TI-Header/csl_c6455/example/dat/src/Dat_example.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file DAT_example.c
*
* @path $(CSLPATH)\example\dat\src
*
* @desc Example of DAT
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
*
* 1D transfer mode:
* - Opens the dat module.
* - Copies a linear block of data from src to dst.
* - Waits for a previous transfer to complete.
* - Does the data comparision to ensure the copied data is proper or
* not and
* - Fills a linear block of memory with the specified fillVal
* using EDMA.
* - Does the data comparision to ensure the filled data is proper or
* not and
* - Displays the message based on previous step
*
* 2D transfer mode:
* - Opens the dat module.
* - Initializes the source and destination buffer with data
* - Performs a 2-dimensional data copy (2D2D) using EDMA
* - Waits for a previous transfer to complete.
* - Does the data comparision to ensure the copied data is proper or
* not and
* - Performs a 2-dimensional data copy (2D1D) using EDMA
* - Waits for a previous transfer to complete.
* - Does the data comparision to ensure the copied data is proper or
* not and
* - Displays the message based on previous step
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Dat_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 16-Dec-2005 ds Updated documentation
* ============================================================================
*/
#include <stdio.h>
#include <csl_dat.h>
/* Global Setup, Data */
#define DAT_CSL_EXA_OK 1
#define NUMBER_OF_ROW 8
#define NUM_OF_BYTES 256
#define ARRAY_INDEX 16
#define FILL_VALUE 0x55555555
#define LINE_PITCH 20
/* Function forwards */
Int dat_1dXfer(void);
Int dat_2dXfer(void);
/* global buffers used during transfer */
Uint8 src[NUM_OF_BYTES];
Uint8 dst[NUM_OF_BYTES];
Uint8 dst1d[NUM_OF_BYTES];
Uint8 src1d[NUM_OF_BYTES];
Uint8 src2d[NUMBER_OF_ROW][LINE_PITCH];
Uint8 dst2d[NUMBER_OF_ROW][LINE_PITCH];
/* Variable to verify example status */
Int pass = 1;
/*
* ============================================================================
* @func main
*
* @desc
* main function to call dat function
* ============================================================================
*/
void main(void)
{
if (dat_1dXfer() && pass) {
printf("<< EXAMPLE PASSED >>: Dat 1D DAT Example Passed \n");
}
else {
printf("<< EXAMPLE FAILED >>: Dat 1D DAT Example Failed \n");
}
if (dat_2dXfer() && pass) {
printf("<< EXAMPLE PASSED >>: Dat 2D DAT Example Passed \n");
}
else {
printf("<< EXAMPLE FAILED >>: Dat 2D DAT Example Failed \n");
}
}
/*
* =============================================================================
* @func dat_1dXfer
*
* @arg
* NONE
*
* @desc
* The example function shows the usage of dat CSL APIs. This function
* demonstrates the usage of CSL APIs in configuring the dat 1D transfer
* mode.
*
* @return
* NONE
*
* =============================================================================
*/
Int dat_1dXfer(void)
{
Int loopIdx;
Int id;
Uint32 fillVal;
DAT_Setup datSetup;
/* dat setup */
datSetup.qchNum = CSL_DAT_QCHA_0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
/* Initialize the memory */
for (loopIdx = 0; loopIdx < NUM_OF_BYTES; loopIdx++){
src[loopIdx] = loopIdx;
dst[loopIdx] = 0xff;
}
/* opening the dat module */
DAT_open (&datSetup);
/* Copies a linear block of data from Src to Dst */
id = DAT_copy (&src, &dst, NUM_OF_BYTES);
/* Waits for a previous transfer to complete */
DAT_wait(id);
/* Verify received data */
for (loopIdx = 0; loopIdx < NUM_OF_BYTES; loopIdx++) {
if (dst[loopIdx] != loopIdx) {
printf("Linear block of data transfer from src to dst is failed\n");
pass = 0;
}
}
fillVal = FILL_VALUE;
/* Fills a linear block of memory with the specified fillVal
using EDMA */
DAT_fill (&dst, NUM_OF_BYTES, &fillVal);
DAT_wait (id);
/* Verify fill data */
for (loopIdx = 0; loopIdx < NUM_OF_BYTES; loopIdx++) {
if (dst[loopIdx] != ((Uint8)fillVal)) {
printf("Filling linear block of memory with the specified ");
printf("fillVal is failed\n");
pass = 0;
}
}
return DAT_CSL_EXA_OK;
}
/*
* =============================================================================
* @func dat_2dXfer
*
* @arg
* NONE
*
* @desc
* The example function shows the usage of dat CSL APIs.This examples
* performs 2D data transfers iteratively using DAT module.
*
* @return
* NONE
*
* =============================================================================
*/
Int dat_2dXfer (void)
{
Int loopIdx,inLoopIdx;
Int id = 0;
DAT_Setup datSetup;
Uint8 srcVal = 4;
/* dat setup */
datSetup.qchNum = CSL_DAT_QCHA_0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
/* opening the dat module */
DAT_open (&datSetup);
/* Initialize the source memory */
for (loopIdx = 0; loopIdx < NUMBER_OF_ROW; loopIdx++) {
for (inLoopIdx = 0; inLoopIdx < ARRAY_INDEX ; inLoopIdx++)
src2d[loopIdx][inLoopIdx] = loopIdx*0x10 + inLoopIdx;
src2d[loopIdx][ARRAY_INDEX ] = srcVal;
src2d[loopIdx][ARRAY_INDEX + 1 ] = srcVal;
src2d[loopIdx][ARRAY_INDEX + 2 ] = srcVal;
src2d[loopIdx][ARRAY_INDEX + 3 ] = srcVal;
}
/* Initialize the destination memory */
for (loopIdx = 0; loopIdx < NUMBER_OF_ROW; loopIdx++) {
for (inLoopIdx = 0; inLoopIdx < LINE_PITCH; inLoopIdx++)
dst2d[loopIdx][inLoopIdx] = 0;
}
/* Performs a 2-dimensional(2D2D) data copy using EDMA */
DAT_copy2d (DAT_2D2D, src2d, dst2d, ARRAY_INDEX , \
NUMBER_OF_ROW, LINE_PITCH);
/* Waits for a previous transfer to complete */
DAT_wait(id);
/* Verify received data */
for (loopIdx = 0; loopIdx < NUMBER_OF_ROW; loopIdx++) {
for (inLoopIdx = 0; inLoopIdx < ARRAY_INDEX ; inLoopIdx++)
if (src2d[loopIdx][inLoopIdx] != (loopIdx*0x10 + inLoopIdx)) {
printf("2-dimensional(2D2D) data copy using EDMA is failed\n");
pass = 0;
}
}
for (loopIdx = 0; loopIdx < NUMBER_OF_ROW*ARRAY_INDEX ; loopIdx++)
dst1d[loopIdx] = 0;
/* Performs a 2-dimensional data copy (2D1D) using EDMA */
DAT_copy2d (DAT_2D1D, src2d, dst1d, ARRAY_INDEX , \
NUMBER_OF_ROW, LINE_PITCH);
/* Waits for a previous transfer to complete */
DAT_wait(id);
/* Verify received data */
for (loopIdx = 0; loopIdx < NUMBER_OF_ROW*ARRAY_INDEX ; loopIdx++)
if (dst1d[loopIdx] != loopIdx) {
printf("2-dimensional(2D1D) data copy using EDMA is failed\n");
pass = 0;
}
/* Initialize the source memory for 1D */
for (loopIdx = 0; loopIdx < NUMBER_OF_ROW*ARRAY_INDEX ; loopIdx++)
src1d[loopIdx] = loopIdx;
/* Initialize the destination memory for 2D */
for (loopIdx = 0; loopIdx < NUMBER_OF_ROW; loopIdx++) {
for (inLoopIdx = 0; inLoopIdx < LINE_PITCH; inLoopIdx++)
dst2d[loopIdx][inLoopIdx] = 0;
}
/* Performs a 2-dimensional data copy (1D2D) using EDMA */
DAT_copy2d (DAT_1D2D, src1d, dst2d, ARRAY_INDEX , NUMBER_OF_ROW, LINE_PITCH);
/* Waits for a previous transfer to complete */
DAT_wait (id);
/* verify write */
for (loopIdx = 0; loopIdx < NUMBER_OF_ROW; loopIdx++) {
for (inLoopIdx = 0; inLoopIdx < ARRAY_INDEX ; inLoopIdx++)
if (dst2d[loopIdx][inLoopIdx] != (0x10*loopIdx + inLoopIdx)) {
printf("2-dimensional(1D2D) data copy using EDMA is failed\n");
pass = 0;
}
}
return DAT_CSL_EXA_OK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3Param.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3Param.c
*
* @path $(CSLPATH)\src\edma
*
* @desc CSL for Edma Parameter Entries
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
* 23-Mar-2006 ds Added invalid handle check for CSL_edma3ParamWriteWord() API.
* =============================================================================
*/
#include <csl_edma3.h>
/** ============================================================================
* @n@b CSL_edma3GetParamHandle
*
* @b Description
* @n Acquires the Param entry as specified by the argument.
*
* @b Arguments
* @verbatim
hEdma Channel Handle
paramNum Parameter entry number
status Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_Edma3ParamHandle
* @n Valid param handle will be returned if status value
* is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before this API can be invoked
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelObj chObj;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] =
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Status status;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// DRAE Enable(Bits 0-15) for the Shadow Region 0.
regionAccess.region = CSL_EDMA3_REGION_0 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
// Interrupt Enable (Bits 0-11) for the Shadow Region 0.
regionIntr.region = CSL_EDMA3_REGION_0 ;
regionIntr.intr = 0x0FFF ;
regionIntr.intrh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,®ionIntr);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj,
CSL_EDMA3,
&chAttr,
&status);
// Obtain a handle to parameter entry 0
hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3GetParamHandle, ".text:csl_section:edma3");
CSL_Edma3ParamHandle CSL_edma3GetParamHandle (
CSL_Edma3ChannelHandle hEdma,
Int16 paramNum,
CSL_Status *status
)
{
CSL_Edma3ParamHandle handle = (CSL_Edma3ParamHandle)NULL;
if (status == NULL) {
/* Do nothing */
}
else if (hEdma == NULL) {
*status = CSL_ESYS_BADHANDLE;
}
else if (paramNum < 0 || paramNum > 255) {
*status = CSL_ESYS_INVPARAMS;
}
else {
handle = (&hEdma->regs->PARAMSET[paramNum]);
*status = CSL_SOK;
}
return (handle);
}
/** ============================================================================
* @n@b CSL_edma3ParamSetup
*
* @b Description
* @n Configures the EDMA parameter Entry using the values passed in through
* the Param setup structure.
*
* @b Arguments
* @verbatim
hParamHndl Handle to the param entry
setup Pointer to param setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command execution successful
* @li CSL_ESYS_BADHANDLE - The handle passed is
* invalid
* @li CSL_ESYS_INVPARAMS - The parameter passed is invalid
*
* <b> Pre Condition </b>
* @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before this API can be invoked
*
* <b> Post Condition </b>
* @n Configures the EDMA parameter Entry
*
* @b Modifies
* @n Parameter entry
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelObj chObj;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] =
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Status status;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// DRAE Enable(Bits 0-15) for the Shadow Region 0.
regionAccess.region = CSL_EDMA3_REGION_0 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
// Interrupt Enable (Bits 0-11) for the Shadow Region 0.
regionIntr.region = CSL_EDMA3_REGION_0 ;
regionIntr.intr = 0x0FFF ;
regionIntr.intrh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,®ionIntr);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj,
CSL_EDMA3,
&chAttr,
&status);
// Obtain a handle to parameter entry 0
hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL);
// Setup the first param Entry (Ping buffer)
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
0,CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1);
myParamSetup.linkBcntrld =
CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1);
myParamSetup.cCnt = 1;
CSL_edma3ParamSetup(hParamBasic,&myParamSetup);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3ParamSetup, ".text:csl_section:edma3");
CSL_Status CSL_edma3ParamSetup (
CSL_Edma3ParamHandle hParamHndl,
CSL_Edma3ParamSetup *setup
)
{
Uint32 *paramHndl = (Uint32*)hParamHndl;
Uint32 i;
CSL_Status status = CSL_SOK;
if (hParamHndl == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (setup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
for (i = 0; i < 8 ; i++)
paramHndl[i] = ((Uint32*)setup)[i];
}
return (status);
}
/** ============================================================================
* @n@b CSL_edma3ParamWriteWord
*
* @b Description
* @n This is for the ease of QDMA channels. Once the QDMA channel transfer is
* triggered, subsequent triggers may be done with only writing the modified
* words in the parameter entry along with the trigger word. This API is
* expected to achieve this purpose. Most usage scenarios, the user
* should not be writing more than the trigger word entry.
*
* @b Arguments
* @verbatim
hParamHndl Handle to the param entry
wordOffset word offset in the 8 word paramater entry
word word to be written
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Param Write Word successful
* @li CSL_ESYS_BADHANDLE - Invlaid handle
*
* <b> Pre Condition </b>
* @n CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() and
* must be CSL_edma3GetParamHandle(), CSL_edma3ParamSetup()
* called successfully in that order before this API can be invoked.
* The main setup structure consists of pointers to sub-structures.The
* user has to allocate space for & fill in the parameter setup structure.
*
* <b> Post Condition </b>
* @n Configure trigger word
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelObj chObj;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdQrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3ParamHandle hParamBasic;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] =
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] =
CSL_EDMA3_QDMACHANNELSETUP_DEFAULT;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = &qdmahwSetup[0];;
CSL_edma3HwSetup(hModule,&hwSetup);
// DRAE Enable(Bits 0-15) for the Shadow Region 0.
regionAccess.region = CSL_EDMA3_REGION_0 ;
regionAccess.qrae = 0x000F ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_QDMAREGION_ENABLE, \
®ionAccess);
// Interrupt Enable (Bits 0-11) for the Shadow Region 0.
regionIntr.region = CSL_EDMA3_REGION_0 ;
regionIntr.intr = 0x0FFF ;
regionIntr.intrh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE, ®ionIntr);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_QCHA_0;
hChannel = CSL_edma3ChannelOpen(&ChObj,
CSL_EDMA3,
&chAttr,
&status);
// Obtain a handle to parameter entry 0
hParamBasic = CSL_edma3GetParamHandle(hChannel,0,NULL);
// Setup the first param Entry (Ping buffer)
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
0,CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_EN, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1);
myParamSetup.linkBcntrld =
CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1);
myParamSetup.cCnt = 1;
CSL_edma3ParamSetup(hParamBasic,&myParamSetup);
// Enable Channel
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);
// Write trigger word
CSL_edma3ParamWriteWord(hParamBasic,7,myParamSetup.cCnt);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3ParamWriteWord, ".text:csl_section:edma3");
CSL_Status CSL_edma3ParamWriteWord(
CSL_Edma3ParamHandle hParamHndl,
Uint16 wordOffset,
Uint32 word
)
{
Uint32 *hParam = (Uint32*)(hParamHndl);
CSL_Status status = CSL_SOK;
if (hParamHndl == NULL)
status = CSL_ESYS_BADHANDLE;
else
hParam[wordOffset] = word;
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/srio/csl_srioHwSetupRaw.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ===========================================================================
* @file csl_srioHwSetupRaw.c
*
* @brief File for functional layer of CSL API CSL_srioHwSetupRaw()
*
* @path $(CSLPATH)\srio\src
*
* @desc The CSL_srioHwSetupRaw() function definition and it's associated
* functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 24-Aug-2005 PSK File Created.
* ============================================================================
*/
#include <csl_srio.h>
#include <csl_srioAux.h>
/** ============================================================================
* @n@b CSL_srioHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the config data structure.
*
* @b Arguments
* @verbatim
hSrio Handle to the SRIO instance
config Pointer to the config structure containing the
device register values
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration structure
* pointer is not properly
* initialized
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The registers of the specified SRIO instance will be setup
* according to the values passed through the config structure
*
* @b Modifies
* @n Hardware registers of the specified SRIO
*
* @b Example
* @verbatim
CSL_SrioHandle hSrio;
CSL_SrioConfig config = CSL_SRIO_CONFIG_DEFAULTS;
CSL_Status status;
...
status = CSL_srioHwSetupRaw(hSrio, &config);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION(CSL_srioHwSetupRaw, ".text:csl_section:srio");
CSL_Status CSL_srioHwSetupRaw (
CSL_SrioHandle hSrio,
CSL_SrioConfig *config
)
{
CSL_Status status = CSL_SOK;
int i;
if (hSrio == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (config == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
/* Configures Peripheral settings control register */
hSrio->regs->PER_SET_CNTL = config->PER_SET_CNTL;
/* Configures Peripheral global enable register */
hSrio->regs->GBL_EN = config->GBL_EN;
/* Configures Block enable registers */
for (i = 0; i < CSL_SRIO_BLOCKS_MAX; i++) {
hSrio->regs->BLK_ENABLE[i].BLK_EN = config->BLK_EN[i];
}
/* Configures Device ID register 1 */
hSrio->regs->DEVICEID_REG1 = config->DEVICEID_REG1;
/* Configures Device ID register 2 */
hSrio->regs->DEVICEID_REG2 = config->DEVICEID_REG2;
/* Configures Packet forwarding registers for 16-bit and 8bbit
* device IDs
*/
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL =
config->HW_PKT_FWD[i].PF_16BIT_CNTL;
hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL =
config->HW_PKT_FWD[i].PF_8BIT_CNTL;
}
/* Configures SerDes RX channels configuration control registers*/
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->SERDES_CFGRX_CNTL[i] = config->SERDES_CFGRX_CNTL[i];
}
/* Configures SerDes TX channels configuration control registers*/
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->SERDES_CFGTX_CNTL[i] = config->SERDES_CFGTX_CNTL[i];
}
/* Configures SerDes macros configuration control registers */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->SERDES_CFG_CNTL[i] = config->SERDES_CFG_CNTL[i];
}
/* Configures Doorbell interrupt clear registers */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->DOORBELL_INTR[i].DOORBELL_ICCR =
config->DOORBELL_ICCR[i];
}
/* Configures LSU interrupt clear registers */
hSrio->regs->LSU_ICCR = config->LSU_ICCR;
/* Configures Error, Reset, and Special event interrupt clear
* registers
*/
hSrio->regs->ERR_RST_EVNT_ICCR = config->ERR_RST_EVNT_ICCR;
/* Configures INTDST interrupt rate control register for DST 0 */
hSrio->regs->INTDST_RATE_CNTL[0] = config->INTDST_RATE_CNTL;
/* Configures LSU registers */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->LSU[i].LSU_REG0 = config->LSU[i].LSU_REG0;
hSrio->regs->LSU[i].LSU_REG1 = config->LSU[i].LSU_REG1;
hSrio->regs->LSU[i].LSU_REG2 = config->LSU[i].LSU_REG2;
hSrio->regs->LSU[i].LSU_REG3 = config->LSU[i].LSU_REG3;
hSrio->regs->LSU[i].LSU_REG4 = config->LSU[i].LSU_REG4;
hSrio->regs->LSU[i].LSU_FLOW_MASKS = config->LSU[i].LSU_FLOW_MASKS;
}
/* Configures Flow control table entry registers */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->FLOW_CNTL[i] = config->FLOW_CNTL[i];
}
/* Configures Processing element logical layer control CSR register */
hSrio->regs->PE_LL_CTL = config->PE_LL_CTL;
/* Configures Base device ID CSR register */
hSrio->regs->BASE_ID = config->BASE_ID;
/* Configures Host base device ID lock CSR */
hSrio->regs->HOST_BASE_ID_LOCK = config->HOST_BASE_ID_LOCK;
/* Configures Component tag CSR */
hSrio->regs->COMP_TAG = config->COMP_TAG;
/* Configures Port link time-out control CSR */
hSrio->regs->SP_LT_CTL = config->SP_LT_CTL;
/* Configures Port link response time-out control CSR */
hSrio->regs->SP_RT_CTL = config->SP_RT_CTL;
/* Configures Port general control CSR */
hSrio->regs->SP_GEN_CTL = config->SP_GEN_CTL;
/* Configures Port registers */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->PORT[i].SP_LM_REQ = config->PORT[i].SP_LM_REQ;
hSrio->regs->PORT[i].SP_ACKID_STAT = config->PORT[i].SP_ACKID_STAT;
hSrio->regs->PORT[i].SP_ERR_STAT = config->PORT[i].SP_ERR_STAT;
hSrio->regs->PORT[i].SP_CTL = config->PORT[i].SP_CTL;
}
/* Configures Logical/Transport layer error detect CSR */
hSrio->regs->ERR_DET = config->ERR_DET;
/* Configures Logical/Transport layer error enable CSR */
hSrio->regs->ERR_EN = config->ERR_EN;
/* Configures Port-write target device ID CSR */
hSrio->regs->PW_TGT_ID = config->PW_TGT_ID;
/* Configures Port error CSR */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->PORT_ERROR[i].SP_ERR_DET =
config->PORT_ERROR[i].SP_ERR_DET;
hSrio->regs->PORT_ERROR[i].SP_RATE_EN =
config->PORT_ERROR[i].SP_RATE_EN;
hSrio->regs->PORT_ERROR[i].SP_ERR_RATE =
config->PORT_ERROR[i].SP_ERR_RATE;
hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH =
config->PORT_ERROR[i].SP_ERR_THRESH;
}
/* Configures Port IP discovery timer in 4x mode */
hSrio->regs->SP_IP_DISCOVERY_TIMER = config->SP_IP_DISCOVERY_TIMER;
/* Configures Port IP mode CSR */
hSrio->regs->SP_IP_MODE = config->SP_IP_MODE;
/* Configures Serial port IP prescalar */
hSrio->regs->IP_PRESCAL = config->IP_PRESCALAR;
/* Configures Port options CSR */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hSrio->regs->PORT_OPTION[i].SP_RST_OPT =
config->PORT_OPTION[i].SP_RST_OPT;
hSrio->regs->PORT_OPTION[i].SP_CTL_INDEP =
config->PORT_OPTION[i].SP_CTL_INDEP;
hSrio->regs->PORT_OPTION[i].SP_SILENCE_TIMER =
config->PORT_OPTION[i].SP_SILENCE_TIMER;
hSrio->regs->PORT_OPTION[i].SP_MULT_EVNT_CS =
config->PORT_OPTION[i].SP_MULT_EVNT_CS;
hSrio->regs->PORT_OPTION[i].SP_CS_TX =
config->PORT_OPTION[i].SP_CS_TX;
}
/* Configures Peripheral control register */
hSrio->regs->PCR = config->PCR;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiGetHwStatus.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/hpi/csl_hpiGetHwStatus.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ===========================================================================
*/
/**
* @file csl_hpiGetHwStatus.c
*
* @path $(CSLPATH)\src\hpi
*
* @brief File for functional layer of CSL API @a CSL_hpiGetHwStatus()
*
*/
/* =============================================================================
* Revision History
* ===============
* 06-Feb-2006 ds Removed CSL_HPI_QUERY_PID_REV, CSL_HPI_QUERY_PID_TYPE and
* CSL_HPI_QUERY_PID_CLASS
*
* =============================================================================
*/
#include <csl_hpi.h>
#include <csl_hpiAux.h>
/** ============================================================================
* @n@b CSL_hpiGetHwStatus
*
* @b Description
* @n Gets the status of the different operations of HPI.
*
* @b Arguments
* @verbatim
hHpi Handle to the HPI instance
query The query to this API of HPI which indicates the
status to be returned.
response Placeholder to return the status.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Query successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVQUERY - The Query passed is invalid
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n CSL_hpiInit() and CSL_hpiOpen() must be called successfully in order
* before calling CSL_hpiGetHwStatus().
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Third parameter response vlaue
*
* @b Example
* @verbatim
CSL_HpiHandle hHpi;
CSL_HpiHwStatusQuery query;
void reponse;
status = CSL_hpiGetHwStatus(hHpi, query, &response);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_hpiGetHwStatus, ".text:csl_section:hpi");
CSL_Status CSL_hpiGetHwStatus (
CSL_HpiHandle hHpi,
CSL_HpiHwStatusQuery query,
void *response
)
{
CSL_Status status = CSL_SOK;
if (hHpi == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (query) {
case CSL_HPI_QUERY_HRDY:
CSL_hpiGetHpicHrdy(hHpi,response);
break;
case CSL_HPI_QUERY_FETCH:
CSL_hpiGetHpicFetch(hHpi,response);
break;
case CSL_HPI_QUERY_HPI_RST:
CSL_hpiGetHpicHpiRst(hHpi,response);
break;
case CSL_HPI_QUERY_HWOB_STAT:
CSL_hpiGetHpicHwobStat(hHpi,response);
break;
default:
status = CSL_ESYS_INVQUERY ;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/cache/csl_cacheWait.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_cacheWait.c
*
* @path $(CSLPATH)\src\cache
*
* @desc File for functional layer of Cache Waite State
*
*/
/* =============================================================================
* Revision History
* ===============
* - 23-Mar-2004 <NAME> File Created
*
* 21-Jun-2004 <NAME> modified.
*
* =============================================================================
*/
#include <csl_cache.h>
#include <_csl_cache.h>
/** ============================================================================
* @n@b CACHE_wait
*
* @b Description
* @n Waits for previously issued block operations to complete. This does a
* partial wait. i.e waits for the cache status register to read back as
* done. (if required)
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CACHE_wait();
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_wait, ".text:csl_section:cache");
void CACHE_wait (void)
{
CACHE_waitInternal();
_CSL_cacheApplyPatch();
return;
}
/** ============================================================================
* @n@b CACHE_waitInternal
*
* @b Description
* @n Waits for previously issued block operations to complete. This does a
* partial wait. i.e waits for the cache status register to read back as
* done. (if required)
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CACHE_waitInternal();
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CACHE_waitInternal, ".text:csl_section:cache");
void CACHE_waitInternal(void)
{
switch(_CSL_cachebusyState) {
case CACHE_WAIT_NONE:
break;
case CACHE_WAIT_L1DINVALL:
while (CSL_FEXT(((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DINV, \
CACHE_L1DINV_CMDANDSTAT) == \
CSL_CACHE_L1DINV_CMDANDSTAT_NOTDONE);
break;
case CACHE_WAIT_L1DINV:
while (((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DIWC != 0);
break;
case CACHE_WAIT_L1DWBALL:
while (CSL_FEXT(((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWB, \
CACHE_L1DWB_CMDANDSTAT) == \
CSL_CACHE_L1DWB_CMDANDSTAT_NOTDONE);
break;
case CACHE_WAIT_L1DWB:
while (((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWWC != 0);
break;
case CACHE_WAIT_L1DWBINVALL:
while (CSL_FEXT(((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWBINV, \
CACHE_L1DINV_CMDANDSTAT) == \
CSL_CACHE_L1DINV_CMDANDSTAT_NOTDONE);
break;
case CACHE_WAIT_L1DWBINV:
while (((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1DWIWC != 0);
break;
case CACHE_WAIT_L1PINVALL:
while (CSL_FEXT(((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PINV, \
CACHE_L1PINV_CMDANDSTAT) == \
CSL_CACHE_L1PINV_CMDANDSTAT_NOTDONE);
break;
case CACHE_WAIT_L1PINV:
while (((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L1PIWC != 0);
break;
case CACHE_WAIT_L2INVALL:
while (CSL_FEXT(((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2INV, \
CACHE_L2INV_CMDANDSTAT) == \
CSL_CACHE_L2INV_CMDANDSTAT_NOTDONE);
break;
case CACHE_WAIT_L2INV:
while (((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2IWC != 0);
break;
case CACHE_WAIT_L2WBALL:
while (CSL_FEXT(((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WB, \
CACHE_L2WB_CMDANDSTAT) == \
CSL_CACHE_L2WB_CMDANDSTAT_NOTDONE);
break;
case CACHE_WAIT_L2WB:
while (((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WWC != 0);
break;
case CACHE_WAIT_L2WBINVALL:
while (CSL_FEXT(((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WBINV, \
CACHE_L2WBINV_CMDANDSTAT) == \
CSL_CACHE_L2WBINV_CMDANDSTAT_NOTDONE);
break;
case CACHE_WAIT_L2WBINV:
while (((CSL_CacheRegsOvly)CSL_CACHE_0_REGS)->L2WIWC != 0);
break;
default:
break;
}
_CSL_cachebusyState = CACHE_WAIT_NONE;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2GetHwSetup.c
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_ddr2GetHwSetup.c
*
* @path $(CSLPATH)\src\ddr2
*
* @desc File for functional layer of CSL API @a CSL_ddr2GetHwSetup()
* - The @a CSL_ddr2GetHwSetup() function definition & it's associated
* functions
*/
/* =============================================================================
* Revision History
* ===============
* 12-Apr-2005 RM File Created.
*
* 05-Oct-2005 NG Updation done according to new register layer
*
* 03-Feb-2006 ds Updated according to TCI6482/C6455 user guide
* =============================================================================
*/
#include <csl_ddr2.h>
/** ============================================================================
* @n@b CSL_ddr2GetHwSetup
*
* @b Description
* @n This function gets the current setup of the DDR2. The status is
* returned through @a CSL_Ddr2HwSetup. The obtaining of status
* is the reverse operation of @a CSL_ddr2HwSetup() function.
*
* @b Arguments
* @verbatim
hDdr2 Handle to the external memory interface instance
setup Pointer to setup structure which contains the
information to program DDR2 to a useful state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup successful
* @li CSL_ESYS_INVPARAMS - The param passed is invalid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called successfully
* in order before calling @a CSL_ddr2GetHwSetup().
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Second parameter setup value
*
* @b Example:
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Status status;
CSL_Ddr2Timing1 tim1;
CSL_Ddr2Timing2 tim2;
CSL_Ddr2Settings set;
CSL_Ddr2HwSetup hwSetup ;
hwSetup.timing1Param = &tim1;
hwSetup.timing2Param = &tim2;
hwSetup.setParam = &set;
...
status = CSL_ddr2GetHwSetup(hDdr2, &hwSetup);
@endverbatim
*
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_ddr2GetHwSetup, ".text:csl_section:ddr2")
CSL_Status CSL_ddr2GetHwSetup(
CSL_Ddr2Handle hDdr2,
CSL_Ddr2HwSetup *setup
)
{
CSL_Status status = CSL_SOK;
/* invalid parameter checking */
if (setup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else if (hDdr2 == NULL) {
/* bad handle checking */
status = CSL_ESYS_BADHANDLE;
}
else {
/* Get the SDRAM Refresh Rate Configuration */
setup->refreshRate = (Uint16)CSL_FEXT(hDdr2->regs->SDRFC,
DDR2_SDRFC_REFRESH_RATE);
/* Get the SDRAM Configuration */
if (setup->setParam != NULL) {
setup->setParam->casLatncy = (CSL_Ddr2CasLatency)CSL_FEXT(
hDdr2->regs->SDCFG, DDR2_SDCFG_CL);
setup->setParam->ibank = (CSL_Ddr2IntBank)CSL_FEXT(hDdr2->regs->SDCFG,
DDR2_SDCFG_IBANK);
setup->setParam->pageSize = (CSL_Ddr2PageSize)CSL_FEXT(
hDdr2->regs->SDCFG,
DDR2_SDCFG_PAGESIZE);
setup->setParam->narrowMode = (CSL_Ddr2Mode)CSL_FEXT(
hDdr2->regs->SDCFG, DDR2_SDCFG_NM);
setup->setParam->ddrDrive = (CSL_Ddr2Drive)
CSL_FEXT(hDdr2->regs->SDCFG, DDR2_SDCFG_DDR_DRIVE);
}
/* Get the SDRAM Timing1 Configuration */
if(setup->timing1Param != NULL) {
setup->timing1Param->trfc = CSL_FEXT(hDdr2->regs->SDTIM1,
DDR2_SDTIM1_T_RFC);
setup->timing1Param->trp = CSL_FEXT(hDdr2->regs->SDTIM1,
DDR2_SDTIM1_T_RP);
setup->timing1Param->trcd = CSL_FEXT(hDdr2->regs->SDTIM1,
DDR2_SDTIM1_T_RCD);
setup->timing1Param->twr = CSL_FEXT(hDdr2->regs->SDTIM1,
DDR2_SDTIM1_T_WR);
setup->timing1Param->tras = CSL_FEXT(hDdr2->regs->SDTIM1,
DDR2_SDTIM1_T_RAS);
setup->timing1Param->trc = CSL_FEXT(hDdr2->regs->SDTIM1,
DDR2_SDTIM1_T_RC);
setup->timing1Param->trrd = CSL_FEXT(hDdr2->regs->SDTIM1,
DDR2_SDTIM1_T_RRD);
setup->timing1Param->twtr = CSL_FEXT(hDdr2->regs->SDTIM1,
DDR2_SDTIM1_T_WTR);
}
/* Get the SDRAM Timing2 Configuration */
if (setup->timing2Param != NULL) {
setup->timing2Param->todt = CSL_FEXT(hDdr2->regs->SDTIM2,
DDR2_SDTIM2_T_ODT);
setup->timing2Param->tsxnr = CSL_FEXT(hDdr2->regs->SDTIM2,
DDR2_SDTIM2_T_SXNR);
setup->timing2Param->tsxrd = CSL_FEXT(hDdr2->regs->SDTIM2,
DDR2_SDTIM2_T_SXRD);
setup->timing2Param->trtp = CSL_FEXT(hDdr2->regs->SDTIM2,
DDR2_SDTIM2_T_RTP);
setup->timing2Param->tcke = CSL_FEXT(hDdr2->regs->SDTIM2,
DDR2_SDTIM2_T_CKE);
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/edma/edma_self_chain/src/Edma_self_chaining.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455/example/edma/edma_self_chain/src/Edma_self_chaining.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
*
* @file edma_self_chaining.c
*
* @path $(CSLPATH)\example\edma\edma_self_chaining\src
*
* @desc Example of EDMA
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This example illustrates a EDMA Self chaining. The following steps
* shows the EDMA3 setup and illustration of the broken up smaller packet
* transfers.
* 1. Initializes the CSL EDMA module
* 2. Opens and Sets up Edma module to default values
* 3. Opens EDMA channel 0 in the region 5
* 4. Sets up the EDMA PARAM entry
- Enables intermediate transfer chaining to break up a large
transfer into smaller transfers
- Sets up the A-synchronized transfer to move a 16K bytes of memory
- Sets up to transfer 16 arrays of 1 Kbyte elements, for a total
of 16K byte elements
- Sets TCC value as the channel number (channel 0)
- Sets TCINTEN to trigger interrupt 0 when the last 1 Kbyte array
is transferred
* 5. Enable the channel 0
* 6. Manually triggers the channel 0
* 7. Waits for EDMA transfer till it will complete the 16K byte transfer
* 8. Does the data comparision to ensure the transffered data is proper
* or not and
* 9. Displays the messages based on step 8
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Edma_self_chain.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 8-Feb-2006 ds File Created
* =============================================================================
*/
#include <stdio.h>
#include <csl_edma3.h>
#include <soc.h>
/* Number of bytes to transfer */
#define NOF_BYTES_XFR 16384
/* Globals */
Uint8 srcBuff1[NOF_BYTES_XFR];
Uint8 dstBuff1[NOF_BYTES_XFR];
Uint32 passStatus = 1;
/* Forward declaration */
void edma_self_chaining (void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main(void)
{
/* Invoke example */
edma_self_chaining ();
return;
}
/*
* =============================================================================
* @func edma_self_chaining
*
* @arg
* NONE
*
* @desc
* This example illustrates a EDMA Self chaining. The following steps
* shows the EDMA3 setup and illustration of the broken up smaller packet
* transfers.
* 1. Initializes the CSL EDMA module
* 2. Opens and Sets up Edma module to default values
* 3. Opens EDMA channel 0 in the region 5
* 4. Sets up the EDMA PARAM entry
5. Enable the channel 0
* 6. Manually triggers the channel 0
* 7. Waits for EDMA transfer till it will complete the 16K byte transfer
* 8. Does the data comparision to ensure the transffered data is proper
* or not and
* 9. Displays the messages based on step 8
*
* @return
* NONE
*
* =============================================================================
*/
void edma_self_chaining (void)
{
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamBasic;
CSL_Edma3ChannelObj chObj;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Status status;
CSL_Edma3HwDmaChannelSetup dmahwSetup;
volatile Uint32 loopIndex;
Uint32 numXfr;
printf ("Running Edma Example\n");
/* Module Initialization */
status = CSL_edma3Init(&context);
if (status != CSL_SOK) {
printf ("Edma module initialization failed\n");
return;
}
/* Module level open */
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
if ( (hModule == NULL) || (status != CSL_SOK)) {
printf ("Edma module open failed\n");
return;
}
/* Module setup */
dmahwSetup.paramNum = 0;
dmahwSetup.que = CSL_EDMA3_QUE_0;
hwSetup.dmaChaSetup = &dmahwSetup;
hwSetup.qdmaChaSetup = NULL;
status = CSL_edma3HwSetup(hModule,&hwSetup);
if (status != CSL_SOK) {
printf ("Hardware setup failed\n");
CSL_edma3Close (hModule);
return;
}
/* DRAE enable(Bits 0-15) for the shadow region 5 */
regionAccess.region = CSL_EDMA3_REGION_5 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
if (status != CSL_SOK) {
printf ("Edma region enable command failed\n");
return;
}
/* Channel 0 open in context of shadow region 5 */
chAttr.regionNum = CSL_EDMA3_REGION_5;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status);
if ((hChannel == NULL) || (status != CSL_SOK)) {
printf ("Edma channel open failed\n");
return;
}
/* Obtain a handle to parameter set 0 */
hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status);
if (hParamBasic == NULL) {
printf ("Edma get param handle for param entry 0 failed\n");
return;
}
/* ACNT value */
numXfr = NOF_BYTES_XFR/16;
/* Setup the first param set */
myParamSetup.option = CSL_EDMA3_OPT_MAKE (CSL_EDMA3_ITCCH_EN, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
0, CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR
);
myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(numXfr,16);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(numXfr, numXfr);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(1, 1);
myParamSetup.cCnt = 1;
status = CSL_edma3ParamSetup(hParamBasic, &myParamSetup);
if (status != CSL_SOK) {
printf("Edma parameter entry setup is failed\n");
return;
}
/* Enable channel */
status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \
NULL);
if (status != CSL_SOK) {
printf("Edma channel enable command is failed\n");
return;
}
/* Initialize data */
for (loopIndex = 0; loopIndex < NOF_BYTES_XFR; loopIndex++) {
srcBuff1[loopIndex] = loopIndex;
dstBuff1[loopIndex] = 0;
}
/* Manually trigger the channel */
status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
if (status != CSL_SOK) {
printf("Edma channel set command is failed\n");
return;
}
regionIntr.region = CSL_EDMA3_REGION_5;
regionIntr.intr = 0;
regionIntr.intrh = 0;
do {
/* Poll on interrupt bit 0 */
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
} while (!(regionIntr.intr & 0x1));
/* Clear interrupt bit 0 */
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \
®ionIntr);
if (status != CSL_SOK) {
printf("Edma clear interrupt bit 0 command is failed\n");
return;
}
/* Check transfer */
if(Verify_Transfer(NOF_BYTES_XFR, 1, 1, 0, 0, 0, 0, srcBuff1, dstBuff1, \
TRUE) == FALSE) {
passStatus = 0;
}
if (passStatus == 1)
printf ("<<EXAMPLE PASSED>>: Edma Self Chaining Transfer Passed\n");
else {
printf ("<<EXAMPLE FAILED>>: Edma Self Chaining Transfer Failed\n");
return;
}
/* Close channel */
status = CSL_edma3ChannelClose(hChannel);
if (status != CSL_SOK) {
printf("Edma channel close failed\n");
return;
}
/* Close edma module */
status = CSL_edma3Close(hModule);
if (status != CSL_SOK) {
printf("Edma module close failed\n");
return;
}
printf ("=============================================================\n");
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/mcbsp/_csl_mcbspRegReset.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file _csl_mcbspRegReset.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API _CSL_mcbspRegReset()
*
*/
/* ============================================================================
* Revision History
* ================
* July 04, 2005 ds - Register Naming convention used for
* Multichannel registers are changed according
* the changes in cslr_mcbsp.h
* ============================================================================
*/
#include <csl_mcbsp.h>
#include <_csl_mcbsp.h>
/* ============================================================================
* @n@b _CSL_mcbspRegReset
*
* @b Description
* @n Function to reset all the registers values
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before _CSL_mcbspRegReset() can be called.
*
* <b> Post Condition </b>
* @n Reset all the registers values
*
* @b Modifies
* @n MCBSP registers
*
* @b Example
* @verbatim
CSL_McbspHandle hMcbsp;
hMcbsp = CSL_mcbspOpen(hMcbsp, CSL_MCBSP_1,NULL, &status );
_CSL_mcbspRegReset(hMcbsp);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (_CSL_mcbspRegReset, ".text:csl_section:mcbsp");
void _CSL_mcbspRegReset (
CSL_McbspHandle hMcbsp
)
{
CSL_McbspRegsOvly mcbspRegs = hMcbsp->regs;
mcbspRegs->DXR = CSL_MCBSP_DXR_RESETVAL;
mcbspRegs->SPCR = CSL_MCBSP_SPCR_RESETVAL;
mcbspRegs->RCR = CSL_MCBSP_RCR_RESETVAL;
mcbspRegs->XCR = CSL_MCBSP_XCR_RESETVAL;
mcbspRegs->SRGR = CSL_MCBSP_SRGR_RESETVAL;
mcbspRegs->MCR = CSL_MCBSP_MCR_RESETVAL;
mcbspRegs->PCR = CSL_MCBSP_PCR_RESETVAL;
mcbspRegs->XCERE0 = CSL_MCBSP_XCERE0_RESETVAL;
mcbspRegs->XCERE1 = CSL_MCBSP_XCERE1_RESETVAL;
mcbspRegs->XCERE2 = CSL_MCBSP_XCERE2_RESETVAL;
mcbspRegs->XCERE3 = CSL_MCBSP_XCERE3_RESETVAL;
mcbspRegs->RCERE0 = CSL_MCBSP_RCERE0_RESETVAL;
mcbspRegs->RCERE1 = CSL_MCBSP_RCERE1_RESETVAL;
mcbspRegs->RCERE2 = CSL_MCBSP_RCERE2_RESETVAL;
mcbspRegs->RCERE3 = CSL_MCBSP_RCERE3_RESETVAL;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_idma.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_idma.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for IDMA
*/
#ifndef _CSLR_IDMA_H_
#define _CSLR_IDMA_H_
#include <cslr.h>
#include <csl_types.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 IDMA0_STAT;
volatile Uint32 IDMA0_MASK;
volatile Uint32 IDMA0_SRC;
volatile Uint32 IDMA0_DST;
volatile Uint32 IDMA0_CNT;
volatile Uint8 RSVD0[236];
volatile Uint32 IDMA1_STAT;
volatile Uint8 RSVD1[4];
volatile Uint32 IDMA1_SRC;
volatile Uint32 IDMA1_DST;
volatile Uint32 IDMA1_CNT;
} CSL_IdmaRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_IdmaRegs * CSL_IdmaRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* IDMA0_STAT */
#define CSL_IDMA_IDMA0_STAT_ACTV_MASK (0x00000001u)
#define CSL_IDMA_IDMA0_STAT_ACTV_SHIFT (0x00000000u)
#define CSL_IDMA_IDMA0_STAT_ACTV_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA0_STAT_ACTV_ACTIVE (0x00000001u)
#define CSL_IDMA_IDMA0_STAT_ACTV_INACTIVE (0x00000000u)
#define CSL_IDMA_IDMA0_STAT_PEND_MASK (0x00000002u)
#define CSL_IDMA_IDMA0_STAT_PEND_SHIFT (0x00000001u)
#define CSL_IDMA_IDMA0_STAT_PEND_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA0_STAT_PEND_PENDING (0x00000001u)
#define CSL_IDMA_IDMA0_STAT_PEND_NOPENDING (0x00000000u)
#define CSL_IDMA_IDMA0_STAT_RESETVAL (0x00000000u)
/* IDMA0_MASK */
#define CSL_IDMA_IDMA0_MASK_BITMASK_MASK (0xFFFFFFFFu)
#define CSL_IDMA_IDMA0_MASK_BITMASK_SHIFT (0x00000000u)
#define CSL_IDMA_IDMA0_MASK_BITMASK_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA0_MASK_RESETVAL (0x00000000u)
/* IDMA0_SRC */
#define CSL_IDMA_IDMA0_SRC_SRCADDR_MASK (0xFFFFFFFCu)
#define CSL_IDMA_IDMA0_SRC_SRCADDR_SHIFT (0x00000002u)
#define CSL_IDMA_IDMA0_SRC_SRCADDR_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA0_SRC_RESETVAL (0x00000000u)
/* IDMA0_DST */
#define CSL_IDMA_IDMA0_DST_DSTADDR_MASK (0xFFFFFFFCu)
#define CSL_IDMA_IDMA0_DST_DSTADDR_SHIFT (0x00000002u)
#define CSL_IDMA_IDMA0_DST_DSTADDR_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA0_DST_RESETVAL (0x00000000u)
/* IDMA0_CNT */
#define CSL_IDMA_IDMA0_CNT_COUNT_MASK (0x0000000Fu)
#define CSL_IDMA_IDMA0_CNT_COUNT_SHIFT (0x00000000u)
#define CSL_IDMA_IDMA0_CNT_COUNT_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA0_CNT_INT_MASK (0x10000000u)
#define CSL_IDMA_IDMA0_CNT_INT_SHIFT (0x0000001Cu)
#define CSL_IDMA_IDMA0_CNT_INT_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA0_CNT_INT_YES (0x00000001u)
#define CSL_IDMA_IDMA0_CNT_INT_NO (0x00000000u)
#define CSL_IDMA_IDMA0_CNT_RESETVAL (0x00000000u)
/* IDMA1_STAT */
#define CSL_IDMA_IDMA1_STAT_ACTV_MASK (0x00000001u)
#define CSL_IDMA_IDMA1_STAT_ACTV_SHIFT (0x00000000u)
#define CSL_IDMA_IDMA1_STAT_ACTV_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA1_STAT_ACTV_ACTIVE (0x00000001u)
#define CSL_IDMA_IDMA1_STAT_ACTV_INACTIVE (0x00000000u)
#define CSL_IDMA_IDMA1_STAT_PEND_MASK (0x00000002u)
#define CSL_IDMA_IDMA1_STAT_PEND_SHIFT (0x00000001u)
#define CSL_IDMA_IDMA1_STAT_PEND_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA1_STAT_PEND_PENDING (0x00000001u)
#define CSL_IDMA_IDMA1_STAT_PEND_NOPENDING (0x00000000u)
#define CSL_IDMA_IDMA1_STAT_RESETVAL (0x00000000u)
/* IDMA1_SRC */
#define CSL_IDMA_IDMA1_SRC_SRCADDR_MASK (0xFFFFFFFFu)
#define CSL_IDMA_IDMA1_SRC_SRCADDR_SHIFT (0x00000000u)
#define CSL_IDMA_IDMA1_SRC_SRCADDR_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA1_SRC_SRCADDR_ZEROFILL (0x00000000u)
#define CSL_IDMA_IDMA1_SRC_SRCADDR_ONESFILL (0xFFFFFFFFu)
#define CSL_IDMA_IDMA1_SRC_RESETVAL (0x00000000u)
/* IDMA1_DST */
#define CSL_IDMA_IDMA1_DST_DSTADDR_MASK (0xFFFFFFFFu)
#define CSL_IDMA_IDMA1_DST_DSTADDR_SHIFT (0x00000000u)
#define CSL_IDMA_IDMA1_DST_DSTADDR_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA1_DST_RESETVAL (0x00000000u)
/* IDMA1_CNT */
#define CSL_IDMA_IDMA1_CNT_COUNT_MASK (0x0000FFFFu)
#define CSL_IDMA_IDMA1_CNT_COUNT_SHIFT (0x00000000u)
#define CSL_IDMA_IDMA1_CNT_COUNT_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA1_CNT_FILL_MASK (0x00010000u)
#define CSL_IDMA_IDMA1_CNT_FILL_SHIFT (0x00000010u)
#define CSL_IDMA_IDMA1_CNT_FILL_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA1_CNT_FILL_FILL (0x00000001u)
#define CSL_IDMA_IDMA1_CNT_FILL_XFER (0x00000000u)
#define CSL_IDMA_IDMA1_CNT_INT_MASK (0x10000000u)
#define CSL_IDMA_IDMA1_CNT_INT_SHIFT (0x0000001Cu)
#define CSL_IDMA_IDMA1_CNT_INT_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA1_CNT_INT_YES (0x00000001u)
#define CSL_IDMA_IDMA1_CNT_INT_NO (0x00000000u)
#define CSL_IDMA_IDMA1_CNT_PRI_MASK (0xE0000000u)
#define CSL_IDMA_IDMA1_CNT_PRI_SHIFT (0x0000001Du)
#define CSL_IDMA_IDMA1_CNT_PRI_RESETVAL (0x00000000u)
#define CSL_IDMA_IDMA1_CNT_PRI_PRI0 (0x00000000u)
#define CSL_IDMA_IDMA1_CNT_PRI_PRI1 (0x00000001u)
#define CSL_IDMA_IDMA1_CNT_PRI_PRI2 (0x00000002u)
#define CSL_IDMA_IDMA1_CNT_PRI_PRI3 (0x00000003u)
#define CSL_IDMA_IDMA1_CNT_PRI_PRI4 (0x00000004u)
#define CSL_IDMA_IDMA1_CNT_PRI_PRI5 (0x00000005u)
#define CSL_IDMA_IDMA1_CNT_PRI_PRI6 (0x00000006u)
#define CSL_IDMA_IDMA1_CNT_PRI_PRI7 (0x00000007u)
#define CSL_IDMA_IDMA1_CNT_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_dat.h
|
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @mainpage DAT
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to detail the DAT Module APIs
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
*
* @subsection References
* -# EDMA: Enhanced Direct Memory Access
* @subsection Assumptions
* The user must allocate a free QDMA channel, free parameter set number,
* free transfer completion interrupt number and must also specify the shadow
* region of the DAT modules operation.
*
* A second transfer cannot be submitted before the previous one is complete.
*/
/** ============================================================================
* @file csl_dat.h
*
* @brief Header file for DAT System Service APIs
*
* @path $(CSLPATH)\inc
*
*/
#ifndef _CSL_DAT_H_
#define _CSL_DAT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <soc.h>
#include <cslr_edma3cc.h>
/* global defines */
#define DAT_1D2D 0x1
/**< Transfer type is 1D2D */
#define DAT_2D1D 0x2
/**< Transfer type is 2D1D */
#define DAT_2D2D 0x3
/**< Transfer type is 2D2D */
/* global typedef declarations */
/* global variable declarations */
/**
* @brief DAT Setup structure
*/
typedef struct DAT_Setup {
/** QDMA Channel number being requested */
Int qchNum;
/** Region of operation */
Int regionNum;
/** Transfer completion code dedicated for DAT */
Int tccNum;
/** Parameter Set number for this channel */
Int paramNum;
/** Priority/Queue number on which the transfer requests are submitted */
Int priority;
} DAT_Setup;
/* global function declarations */
/* ============================================================================
* @n@b DAT_open
*
* @b Description
* @n This API
* a. Sets up the channel to Parameter set mapping \n
* b. Sets up the priority. This is essentially done by specifying the
* queue to which the channel is submitted to viz Queue0- Queue7.
* Queue 0 being the highest priority. \n
* c. Enables the region access bit for the channel if a region is
* specified.
*
* @b Arguments
@verbatim
setup Pointer to the DAT setup structure
@endverbatim
*
* <b> Return Value </b> CSL_SOK
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The EDMA registers are configured with the setup values passed.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
DAT_Setup datSetup;
datSetup.qchNum = CSL_DAT_QCHA0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
DAT_open(&datSetup);
@endverbatim
* ===========================================================================
*/
Int16 DAT_open (
DAT_Setup *setup
);
/* ============================================================================
* @n@b DAT_close
*
* @b Description
* @n This API
* a. Disables the region access bit if specified.
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n DAT_open() must be successfully invoked prior to this call.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
DAT_Setup datSetup;
datSetup.qchNum = CSL_DAT_QCHA0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
DAT_open(&datSetup);
...
DAT_close();
@endverbatim
* ===========================================================================
*/
void DAT_close (
void
);
/* ============================================================================
* @n@b DAT_copy
*
* @b Description
* @n This API copies data from source to destination for one dimension
* transfer.
*
* @b Arguments
@verbatim
src Source memory address for the data transfer
dst Destination memory address of the data transfer
byteCnt Number of bytes to be transferred
@endverbatim
*
* <b> Return Value </b> tccNum
*
* <b> Pre Condition </b>
* @n DAT_open() must be successfully invoked prior to this call.
*
* <b> Post Condition </b>
* @n The EDMA registers are configured to transfer byteCnt bytes from the
* source memory address to the destination memory address
*
* @b Modifies
* @n EDMA registers
*
* @b Example
* @verbatim
DAT_Setup datSetup;
Uint8 dst1d[8*16];
Uint8 src1d[8*16];
datSetup.qchNum = CSL_DAT_QCHA0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
DAT_open(&datSetup);
...
DAT_copy(&src1d,&dst1d,256);
...
DAT_close();
@endverbatim
* ===========================================================================
*/
Uint32 DAT_copy (
void *src ,
void *dst ,
Uint16 byteCnt
);
/* ============================================================================
* @n@b DAT_fill
*
* @b Description
* @n This API fill destination by given fill value.
*
* @b Arguments
@verbatim
dst Destination memory address to be filled
byteCnt Number of bytes to be filled
value Value to be filled
@endverbatim
*
* <b> Return Value </b> tccNum
*
* <b> Pre Condition </b>
* @n DAT_open() must be successfully invoked prior to this call.
*
* <b> Post Condition </b>
* @n The EDMA registers are configured to transfer a value to byteCnt bytes
* of the destination memory address
*
* @b Modifies
* @n EDMA registers
*
* @b Example
* @verbatim
DAT_Setup datSetup;
Uint8 dst[8*16];
Uint8 fillVal;
datSetup.qchNum = CSL_DAT_QCHA0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
DAT_open(&datSetup);
...
fillVal = 0x5a;
DAT_fill(&dst,256,&fillval);
...
DAT_close();
@endverbatim
* ===========================================================================
*/
Uint32 DAT_fill(
void *dst,
Uint16 byteCnt,
Uint32 *value
);
/* ============================================================================
* @n@b DAT_wait
*
* @b Description
* @n This API Waits for completion of the ongoing transfer.
*
* @b Arguments
@verbatim
id Channel number of the previous transfer
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n DAT_copy()/DAT_fill must be successfully invoked prior to this call.
*
* <b> Post Condition </b>
* @n Indicates that the transfer ongoing is complete
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
DAT_Setup datSetup;
Uint8 dst1d[8*16];
Uint8 src1d[8*16];
datSetup.qchNum = CSL_DAT_QCHA0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
DAT_open(&datSetup);
...
id = DAT_copy(&src1d,&dst1d,256);
DAT_wait(id);
...
DAT_close();
@endverbatim
* ===========================================================================
*/
void DAT_wait (
Uint32 id
);
/* ============================================================================
* @n@b DAT_busy
*
* @b Description
* @n This API polls for transfer completion.
*
* @b Arguments
@verbatim
id Channel number of the previous transfer
@endverbatim
*
* <b> Return Value </b> Int16
* TRUE/FALSE
*
* <b> Pre Condition </b>
* @n DAT_copy()/DAT_fill must be successfully invoked prior to this call.
*
* <b> Post Condition </b>
* @n Indicates that the transfer ongoing is complete
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
DAT_Setup datSetup;
Uint8 dst1d[8*16];
Uint8 src1d[8*16];
datSetup.qchNum = CSL_DAT_QCHA0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
DAT_open(&datSetup);
...
id = DAT_copy(&src1d,&dst1d,256);
do {
...
}while (DAT_busy(id));
...
DAT_close();
@endverbatim
*
*/
Int16 DAT_busy (
Uint32 id
);
/* ============================================================================
* @n@b DAT_copy2d
*
* @b Description
* @n This API copies data from source to destination for two dimension
* transfer.
*
* @b Arguments
@verbatim
type Indicates the type of the transfer
DAT_1D2D - 1 dimension to 2 dimension
DAT_2D1D - 2 dimension to 1 dimension
DAT_2D2D - 2 dimension to 2 dimension
src Source memory address for the data transfer
dst Destination memory address of the data transfer
lineLen Number of bytes per line
lineCnt Number of lines
linePitch Number of bytes between start of one line to start
of next line
@endverbatim
*
* <b> Return Value </b> tccNum
*
* <b> Pre Condition </b>
* @n DAT_open() must be successfully invoked prior to this call.
*
* <b> Post Condition </b>
* @n The EDMA registers are configured for the transfer
*
* @b Modifies
* @n EDMA registers
*
* @b Example
* @verbatim
DAT_Setup datSetup;
Uint8 dst2d[8][20];
Uint8 src1d[8*16];
datSetup.qchNum = CSL_DAT_QCHA0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
DAT_open(&datSetup);
...
id = DAT_copy2d(DAT_1D2D,src1d,dst2d,16,8,20);
do {
...
}while (DAT_busy(id));
...
DAT_close();
@endverbatim
* ===========================================================================
*/
Uint32 DAT_copy2d (
Uint32 type,
void *src,
void *dst,
Uint16 lineLen,
Uint16 lineCnt,
Uint16 linePitch
);
/* ============================================================================
* @n@b DAT_setPriority
*
* @b Description
* @n Sets the priority bit value PRI of OPT register. The priority value
* can be set by using the type CSL_DatPriority.
*
* @b Arguments
@verbatim
priority priority value
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n DAT_open must be successfully invoked prior to this call.
*
* <b> Post Condition </b>
* @n OPT register is set for the priority value
*
* @b Modifies
* @n OPT register
*
* @b Example
* @verbatim
DAT_Setup datSetup;
Uint8 dst2d[8][20];
Uint8 src1d[8*16];
datSetup.qchNum = CSL_DAT_QCHA0;
datSetup.regionNum = CSL_DAT_REGION_GLOBAL ;
datSetup.tccNum = 1;
datSetup.paramNum = 0 ;
datSetup.priority = CSL_DAT_PRI_0;
DAT_open(&datSetup);
...
DAT_setPriority(CSL_DAT_PRI_3);
@endverbatim
*
*/
void DAT_setPriority (
Int priority
);
#ifdef __cplusplus
}
#endif
#endif /*_CSL_DAT_H_*/
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaHwSetupRaw.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_emifaHwSetupRaw.c
*
* @path $(CSLPATH)\src\emifa
*
* @desc File for functional layer of CSL API @a CSL_emifaHwSetupRaw()
* - The @a CSL_emifaHwSetupRaw() function definition & it's
* associated functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 12-May-2005 RM File Created.
*
* 12-Jul-2005 RM - Changed the module name from EMIF64 to EMIFA
* - Changes made in accordance to the change in cslr_emifa.h
*
* 09-Sep-2005 NG Updation according to coding guidelines
*
* =============================================================================
*/
#include <csl_emifa.h>
/** ============================================================================
* @n@b CSL_emifaHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the Config data structure.This configures registers
* based on a structure of register values, as compared to HwSetup, which
* configures registers based on structure of bit field values.
*
* @b Arguments
* @verbatim
hEmifa Handle to the EMIFA external memory interface instance
config Pointer to the config structure containing the
device register values
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration structure
* pointer is not properly
* initialized
*
* <b> Pre Condition </b>
* @n Both CSL_ emifaInit () and CSL_emifaOpen() must be called successfully
* in order before calling this function
*
* <b> Post Condition </b>
* @n The registers of the specified EMIFA instance will be
* setup according to the values passed through the Config structure
*
* @b Modifies
* @n Hardware registers of the EMIFA
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_EmifaConfig config = CSL_EMIFA_CONFIG_DEFAULTS;
CSL_Status status;
..
status = CSL_emifaHwSetupRaw(hEmifa, &config);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_emifaHwSetupRaw, ".text:csl_section:emifa");
CSL_Status CSL_emifaHwSetupRaw (
CSL_EmifaHandle hEmifa,
CSL_EmifaConfig *config
)
{
CSL_Status status = CSL_SOK;
if(hEmifa == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if(config == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
/* setting the Chip Enable2 Configuration register */
hEmifa->regs->CE2CFG = config->CE2CFG;
/* setting the Chip Enable3 Configuration register */
hEmifa->regs->CE3CFG = config->CE3CFG;
/* setting the Chip Enable4 Configuration register */
hEmifa->regs->CE4CFG = config->CE4CFG;
/* setting the Chip Enable5 Configuration register */
hEmifa->regs->CE5CFG = config->CE5CFG;
/* setting the Asynchronous Wait Cycle Configuration register */
hEmifa->regs->AWCC = config->AWCC;
/* setting the Interrupt Raw Register */
hEmifa->regs->INTRAW = config->INTRAW;
/* setting Interrupt Masked Register */
hEmifa->regs->INTMSK = config->INTMSK;
/* setting the Interrupt Mask Set Register */
hEmifa->regs->INTMSKSET = config->INTMSKSET;
/* setting the Interrupt Mask Clear Register */
hEmifa->regs->INTMSKCLR = config->INTMSKCLR;
/* setting the Burst Priority Register */
hEmifa->regs->BPRIO = config->BPRIO;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/hpi/src/Hpi_example.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
*
* @file Hpi_example.c
*
* @path $(CSLPATH)\example\hpi\src
*
* @desc In this example, demonstrates the CSL HPI functionalities.
*
* =============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @verbatim
This Example,
1. Enables the powersaver clock of HPI.
2. Initializes and Opens the HPI CSL module.
3. Takes HPI out of reset.
4. Sets Host Interrupt
5. Queries for peripheral revision Id, class, type.
6. Queries for host ready.
@endverbatim
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Hpi_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
* =============================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 21-Sep-2005 NG Created
*
* 30-Nov-2005 NG Updated documentation
*
* 25-Jan-2006 NG Updated Example
* =============================================================================
*/
#include <stdio.h>
#include <csl.h>
#include <csl_hpi.h>
#include <cslr_dev.h>
/* HPI Handle Initialize to NULL */
CSL_HpiHandle hHpi = (CSL_HpiHandle) NULL;
/* CSL status */
CSL_Status status;
Uint32 response;
/* forward declaration */
void hpi_error_exit(void);
CSL_Status hpi_example(void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main (
)
{
Bool hpi2En;
/* Unlock the control register */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the HPI */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_HPICTL,
ENABLE);
do {
hpi2En = (Bool)CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_HPISTAT);
} while(hpi2En != TRUE);
status = hpi_example();
if (status == CSL_SOK) {
printf ("HPI CSL example complete\n");
}
else {
printf ("HPI CSL example is not complete\n");
}
}
/*
* ============================================================================
* @func hpi_example
*
* @desc
* This function will initialize the HPI module and also write and read
* back the value from the HPI register.
*
* @arg
* NONE
*
* @return
* NONE
* ============================================================================
*/
CSL_Status hpi_example (
void
)
{
CSL_HpiObj hpiObj;
CSL_HpiHwSetup hwSetup;
Uint32 arg;
/* hardware setup for HPI */
hwSetup.hpiCtrl = (CSL_HpiCtrl)0x4;
hwSetup.hpiAddr.hpiaReadAddr = 0x0;
hwSetup.hpiAddr.hpiaWrtAddr = 0x0;
/* Initialiaze device config registers related to HPI */
status = CSL_hpiInit(NULL);
if (status != CSL_SOK) {
printf("\nNot Initialized");
hpi_error_exit();
return status;
}
/* Open the hpi CSL module */
hHpi = CSL_hpiOpen(&hpiObj, CSL_HPI, NULL, &status);
if ((hHpi == NULL) || (status != CSL_SOK)) {
printf("HPI: Error opening the instance. [status = 0x%x, hHpi \
= 0x%x]\n", status, hHpi);
hpi_error_exit();
return status;
}
status = CSL_hpiHwSetup(hHpi, &hwSetup);
if (status != CSL_SOK) {
printf("HPI: Hardware setup is NOT successfull\n");
hpi_error_exit();
return status;
}
else {
printf("HPI: Hardware setup is successfull\n");
}
/* Set Host Interrupt */
arg = 1;
status = CSL_hpiHwControl(hHpi, CSL_HPI_CMD_SET_HINT, &arg);
if (status != CSL_SOK) {
printf("HPI: Not able to set Host Interrupt.\n");
hpi_error_exit();
return status;
}
else {
printf("HPI: Host Interrupt set \n");
}
/* Query for Host Ready */
status = CSL_hpiGetHwStatus(hHpi, CSL_HPI_QUERY_HRDY, &response);
if (status != CSL_SOK) {
printf("HPI: Host Not ready. \n");
return status;
}
else {
printf("HPI: Host is Ready. \n");
printf("HPI: Response is 0x%x.\n", response);
}
hpi_error_exit();
return status;
}
/******************************************************************************
* @func hpi_error_exit
*
* @desc Error in executing the example. As error is occurred closing the HPI
* handle and returning.
*
* @arg
* NONE
*
* @return
* NONE
******************************************************************************/
void hpi_error_exit (
void
)
{
status = CSL_hpiClose(hHpi);
if (status != CSL_SOK) {
printf("HPI:Unable to close the instance\n");
}
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/common/csl_i2cGetBaseAddress.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_i2cGetBaseAddress.c
*
* @path $(CSLPATH)\src\common
*
* @desc CSL Implementation of CSL_i2cGetBaseAddress
*
* @date 28th May, 2004
* @author <NAME>.
*/
/* ============================================================================
* Revision History
* ===============
* 11-oct-2004 Hs updated according to code review comments.
* 31-aug-2004 Hs File Created.
*
* ============================================================================
*/
#include <csl_i2c.h>
/** ============================================================================
* @n@b CSL_i2cGetBaseAddress
*
* @b Description
* @n Function to get the base address of the peripheral instance.
* This function is used for getting the base address of the peripheral
* instance. This function will be called inside the CSL_i2cOpen()
* function call. This function is open for re-implementing if the user
* wants to modify the base address of the peripheral object to point to
* a different location and there by allow CSL initiated write/reads into
* peripheral MMR's go to an alternate location.
*
* @b Arguments
* @verbatim
i2cNum Specifies the instance of I2C to be opened.
pI2cParam Module specific parameters.
pBaseAddress Pointer to baseaddress structure containing base
address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Successful on getting the base
* address of i2c
* @li CSL_ESYS_FAIL The instance number is invalid.
* @li CSL_ESYS_INVPARAMS Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base Address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure is modified.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_I2cBaseAddress baseAddress;
...
status = CSL_i2cGetBaseAddress(CSL_I2C, NULL, &baseAddress);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_i2cGetBaseAddress, ".text:csl_section:i2c");
CSL_Status CSL_i2cGetBaseAddress (
CSL_InstNum i2cNum,
CSL_I2cParam *pI2cParam,
CSL_I2cBaseAddress *pBaseAddress
)
{
CSL_Status status = CSL_SOK;
/* Added according to review comment 2. */
if (pBaseAddress == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (i2cNum) {
case CSL_I2C:
pBaseAddress->regs = (CSL_I2cRegsOvly)CSL_I2C_0_REGS;
break;
default:
pBaseAddress->regs = NULL;
status = CSL_ESYS_FAIL;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaClose.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_emifaClose.c
*
* @path $(CSLPATH)\src\emifa
*
* @desc File for functional layer of CSL API @a CSL_emifaClose()
* - The @a CSL_emifaClose() function definition & it's associated
* functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 10-May-2005 RM File Created.
*
* 09-Sep-2005 NG Updation according to coding guidelines
*
* =============================================================================
*/
#include <csl_emifa.h>
/** ===========================================================================
* @n@b csl_emifaClose.c
*
* @b Description
* @n This function marks that CSL for the external memory interface instance
* needsto be reopened before using any external memory interface CSL APIs.
*
* @b Arguments
* @verbatim
hEmifa Handle to the external memory interface instance
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - external memory interface is
* closed successfully
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling @a CSL_emifaClose().
*
* <b> Post Condition </b>
* @n 1. The external memory interface CSL APIs cannot be called until the
* external memory interface CSL is reopened again using
* CSL_emifaOpen().
*
* @b Modifies
* @n hEmifa structure
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
...
CSL_emifaClose(hEmifa);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_emifaClose, ".text:csl_section:emifa");
CSL_Status CSL_emifaClose (
CSL_EmifaHandle hEmifa
)
{
CSL_Status status = CSL_SOK;
if (hEmifa != NULL) {
hEmifa->regs = (CSL_EmifaRegsOvly)NULL;
hEmifa->perNum = (CSL_InstNum)-1;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cWrite.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cWrite.c<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_i2cWrite.c
*
* @brief File for functional layer of CSL API @a CSL_i2cWrite()
*
* @path $(CSLPATH)\i2c\src
*
* Description
* - The @a CSL_i2cWrite() function definition & it's associated functions
*
* Modification 1
* - Created on: 28/5/2004
* - Reason: created the sources
*
* @date 28th May, 2004
* @author <NAME>.
* ============================================================================
*/
#include <csl_i2c.h>
/** ============================================================================
* @n@b CSL_i2cWrite
*
* @b Description
* @n This function writes the specified data into I2C data register.
*
* @b Arguments
* @verbatim
hI2c Handle to I2C instance
buf data to be written
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Success (doesnot verify
written data)
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully
* in that order before @a CSL_i2cWrite() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
Uint16 inData;
CSL_Status status;
CSL_I2cHandle hI2c;
...
// I2C object defined and HwSetup structure defined and initialized
...
// Init, Open, HwSetup successfully done in that order
...
status = CSL_i2cWrite(hi2c, &inData);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_i2cWrite, ".text:csl_section:i2c");
CSL_Status CSL_i2cWrite (
CSL_I2cHandle hI2c,
void *buf
)
{
CSL_Status status = CSL_SOK;
if (hI2c == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (buf == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
hI2c->regs->ICDXR = (hI2c->regs->ICDXR & 0xFF00) |
(CSL_FMK(I2C_ICDXR_D,*(Uint8 *)buf));
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/soc.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
#ifndef _SOC_H_
#define _SOC_H_
/* =============================================================================
* Revision History
* ===============
* 14-Mar-2005 brn Moved the Event Ids from csl_intc.h to soc64plus.h
* 20-Jun-2005 sd Changed the interrupt ID defines
* 22-Aug-2005 sd added the defines for MDIO
* 14-Dec-2005 sd updated for the PLLC_2 based address and removed the EVENT ID
* for VLYNQ and EDC
* =============================================================================
*/
#include <cslr.h>
/**************************************************************************\
* 64 soc file
\**************************************************************************/
/*****************************************************************************\
* Static inline definition
\*****************************************************************************/
#ifndef CSL_IDEF_INLINE
#define CSL_IDEF_INLINE static inline
#endif
/**************************************************************************\
* Peripheral Instance count
\**************************************************************************/
/** @brief Number of MCBSP instances */
#define CSL_MCBSP_CNT 2
/** @brief Number of TIMER 64 instances */
#define CSL_TMR_CNT 2
/** @brief Number of DDR2 instances */
#define CSL_DDR2_CNT 1
/** @brief Number of EMIF64 instances */
#define CSL_EMIF64_CNT 1
/** @brief Number of EDMA3 CC instances */
#define CSL_EDMA3_CC_CNT 1
/** @brief Number of EDMA3 CC instances */
#define CSL_EDMA3_TC_CNT 4
/** @brief Number of EMAC instances */
#define CSL_EMAC_CNT 1
/** @brief Number of ECTL instances */
#define CSL_ECTL_CNT 1
/** @brief Number of HPI instances */
#define CSL_HPI_CNT 1
/** @brief Number of UTOPIA instances */
#define CSL_UTOPIA2_CNT 1
/** @brief Number of I2C instances */
#define CSL_I2C_CNT 1
/** @brief Number of GPIO instances */
#define CSL_GPIO_CNT 1
/** @brief Number of MDIO instances */
#define CSL_MDIO_CNT 1
/** @brief Number of SRIO instances */
#define CSL_SRIO_CNT 1
/**************************************************************************\
* Peripheral Instance definitions.
\**************************************************************************/
/** @brief Peripheral Instances of MCBSP instances */
#define CSL_MCBSP_0 (0)
#define CSL_MCBSP_1 (1)
/** @brief Peripheral Instances of Timer 64 instances */
#define CSL_TMR_0 (0)
#define CSL_TMR_1 (1)
/** @brief Peripheral Instance of EDMA instances */
#define CSL_EDMA3 (0)
/** @brief Peripheral Instance for DDR2 */
#define CSL_DDR2 (0)
/** @brief Peripheral Instance for EMIFA */
#define CSL_EMIFA (0)
/** @brief Peripheral Instance for EMAC */
#define CSL_EMAC (0)
/** @brief Peripheral Instance for ECTL */
#define CSL_ECTL (0)
/** @brief Peripheral Instance for HPI */
#define CSL_HPI (0)
/** @brief Peripheral Instance for UTOPIA */
#define CSL_UTOPIA2 (0)
/** @brief Peripheral Instance for I2C */
#define CSL_I2C (0)
/** @brief Peripheral Instance for GPIO */
#define CSL_GPIO (0)
/** @brief Peripheral Instances for MDIO */
#define CSL_MDIO (0)
/** @brief Peripheral Instances for PWRDWN */
#define CSL_PWRDWN (0)
/** @brief Instance number of L2 memory protection */
#define CSL_MEMPROT_L2 (0)
/** @brief Instance number of L1P memory protection */
#define CSL_MEMPROT_L1P (1)
/** @brief Instance number of L1D memory protection */
#define CSL_MEMPROT_L1D (2)
/** @brief Instance number of memory protection config */
#define CSL_MEMPROT_CONFIG (3)
/** @brief Instance number of Bandwidth Management */
#define CSL_BWMNGMT (0)
/** @brief Instance number of PLL controller 1 */
#define CSL_PLLC_1 (0)
/** @brief Instance number of PLL controller 1 */
#define CSL_PLLC_2 (1)
/** @brief Instance number of RAPID IO */
#define CSL_SRIO (0)
/**************************************************************************\
* Peripheral Base Address
\**************************************************************************/
/** @brief Base address of MCBSP memory mapped registers */
#define CSL_MCBSP_0_REGS (0x028C0000u)
#define CSL_MCBSP_1_REGS (0x02900000u)
/** @brief Base address of MCBSP EDMA memory mapped registers */
#define CSL_MCBSP_0_TX_EDMA_REGS (0x30000010u)
#define CSL_MCBSP_0_RX_EDMA_REGS (0x30000000u)
#define CSL_MCBSP_1_TX_EDMA_REGS (0x34000010u)
#define CSL_MCBSP_1_RX_EDMA_REGS (0x34000000u)
/** @brief Base address of timer64 memory mapped registers */
#define CSL_TMR_0_REGS (0x02940000u)
#define CSL_TMR_1_REGS (0x02980000u)
/** #brief DDR2 Module memory mapped address */
#define CSL_DDR2_0_REGS (0x78000000)
/** #brief EMIF64 Module memory mapped address */
#define CSL_EMIFA_0_REGS (0x70000000)
/** #brief I2C Module memory mapped address */
#define CSL_I2C_0_REGS (0x02B04000u)
/** #brief Cache Module memory mapped address */
#define CSL_CACHE_0_REGS (0x01840000u)
/** #brief IDMA Module memory mapped address */
#define CSL_IDMA_0_REGS (0x01820000u)
/** @brief Base address of INTC memory mapped registers */
#define CSL_INTC_0_REGS (0x01800000u)
/** @brief Base address of Channel controller memory mapped registers */
#define CSL_EDMA3CC_0_REGS (0x02A00000u)
/** @brief Base address of Transfer controller memory mapped registers */
#define CSL_EDMA3TC_0_REGS (0x02A20000u)
#define CSL_EDMA3TC_1_REGS (0x02A28000u)
#define CSL_EDMA3TC_2_REGS (0x02A30000u)
#define CSL_EDMA3TC_3_REGS (0x02A38000u)
/** @brief Base address of TCP2 memory mapped registers */
#define CSL_TCP2_0_REGS (0x02BA0000u)
/** @brief Base address of TCP2 configuration registers */
#define CSL_TCP2_CFG_REGS (0x50000000u)
/** @brief Base address of TCP2 memories */
#define CSL_TCP2_X0_MEM (0x50010000u)
#define CSL_TCP2_W0_MEM (0x50030000u)
#define CSL_TCP2_W1_MEM (0x50040000u)
#define CSL_TCP2_I0_MEM (0x50050000u)
#define CSL_TCP2_O0_MEM (0x50060000u)
#define CSL_TCP2_S0_MEM (0x50070000u)
#define CSL_TCP2_T0_MEM (0x50080000u)
#define CSL_TCP2_C0_MEM (0x50090000u)
#define CSL_TCP2_A0_MEM (0x500A0000u)
#define CSL_TCP2_B0_MEM (0x500B0000u)
/** @brief Base address of VCP2 memory mapped registers */
#define CSL_VCP2_0_REGS (0x02B80000u)
/** @brief Base address of VCP2 regsiters accessed via EDMA */
#define CSL_VCP2_EDMA_REGS (0x58000000u)
/** @brief Base address of EMAC memory mapped registers */
#define CSL_EMAC_0_REGS (0x02c80000u)
/** @brief Base address of EMAC control memory mapped registers */
#define CSL_ECTL_0_REGS (0x02C81000u)
/** @brief HPI Module memory mapped address */
#define CSL_HPI_0_REGS (0x02880000u)
/** @brief UTOPIA Module memory mapped address */
#define CSL_UTOPIA2_0_REGS (0x02B40000u)
/** @brief UTOPIA RX data Module memory mapped address */
#define CSL_UTOPIA2_RX_EDMA_REGS (0x3C000000u)
/** @brief UTOPIA TX data memory mapped address */
#define CSL_UTOPIA2_TX_EDMA_REGS (0x3C000400u)
/** @brief GPIO Module memory mapped address */
#define CSL_GPIO_0_REGS (0x02B00000u)
/** @brief MDIO Module memory mapped address */
#define CSL_MDIO_0_REGS (0x02C81800u)
/** @brief device configuration registers memory mapped address */
#define CSL_DEV_REGS (0x02A80000u)
/** @brief Base address of PDC registers */
#define CSL_PWRDWN_PDC_REGS (0x01810000)
/** @brief Base address of L2 power Down registers */
#define CSL_PWRDWN_L2_REGS (0x0184c000)
/** @brief Base address of UMC Memory protection registers */
#define CSL_MEMPROT_L2_REGS (0x184A000u)
/** @brief Base address of PMC memory Protection registers */
#define CSL_MEMPROT_L1P_REGS (0x184A400u)
/** @brief Base address of DMC memory protection registers */
#define CSL_MEMPROT_L1D_REGS (0x184AC00u)
/** @brief Base address of CONFIG memory protection registers */
#define CSL_MEMPROT_CONFIG_REGS (0x1820300u)
/** @brief Bandwidth Management module address */
#define CSL_BWMNGMT_0_REGS (0x01820200u)
/** @brief PLL controller instance 1 module address */
#define CSL_PLLC_1_REGS (0x029A0000u)
/** @brief PLL controller instance 2 module address */
#define CSL_PLLC_2_REGS (0x029C0000u)
/** @brief SRIO module base address */
#define CSL_SRIO_0_REGS (0x02D00000u)
/*****************************************************************************\
* Interrupt Event IDs
\*****************************************************************************/
/**
* @brief Interrupt Event IDs
*/
/* Output of event combiner 0, for events 1 to 31 */
#define CSL_INTC_EVENTID_EVT0 (0)
/* Output of event combiner 0, for events 32 to 63 */
#define CSL_INTC_EVENTID_EVT1 (1)
/* Output of event combiner 0, for events 64 to 95 */
#define CSL_INTC_EVENTID_EVT2 (2)
/* Output of event combiner 0, for events 96 to 127 */
#define CSL_INTC_EVENTID_EVT3 (3)
/* Event ID 4-8 are reserved */
/** EMU interrupt for:
* 1. Host scan access
* 2. DTDMA transfer complete
* 3. AET interrupt
*/
#define CSL_INTC_EVENTID_EMU_DTDMA (9)
/* Event ID 10 is reserved */
/* EMU real time data exchange receive complete */
#define CSL_INTC_EVENTID_EMU_RTDXRX (11)
/* EMU RTDX transmit complete */
#define CSL_INTC_EVENTID_EMU_RTDXTX (12)
/* IDMA Channel 0 Interrupt */
#define CSL_INTC_EVENTID_IDMA0 (13)
/* IDMA Channel 1 Interrupt */
#define CSL_INTC_EVENTID_IDMA1 (14)
/* HPI/PCI Host interrupt */
#define CSL_INTC_EVENTID_HINT (15)
/* I2C interrupt */
#define CSL_INTC_EVENTID_I2CINT (16)
/* Ethernet MAC interrupt */
#define CSL_INTC_EVENTID_MACINT (17)
/* EMIFA Error Interrupt */
#define CSL_INTC_EVENTID_AEASYNCERR (18)
/* Event ID 19 is reserved */
/* RapidIO interrupt 0 */
#define CSL_INTC_EVENTID_RIOINT0 (20)
/* RapidIO interrupt 1 */
#define CSL_INTC_EVENTID_RIOINT1 (21)
/* RapidIO interrupt 4 */
#define CSL_INTC_EVENTID_RIOINT4 (22)
/* Event ID 23 is reserved */
/* EDMA3 channel global completion interrupt */
#define CSL_INTC_EVENTID_EDMA3CC_GINT (24)
/* Event ID 25-29 is reserved */
/* L2 Wakeup interrupt 0 */
#define CSL_INTC_EVENTID_L2PDWAKE0 (30)
/* L2 Wakeup interrupt 1 */
#define CSL_INTC_EVENTID_L2PDWAKE1 (31)
/* VCP2 error interrupt */
#define CSL_INTC_EVENTID_VCP2_INT (32)
/* TCP2 error interrupt */
#define CSL_INTC_EVENTID_TCP2_INT (33)
/* Event ID 34-35 is reserved */
/* Utopia interrupt */
#define CSL_INTC_EVENTID_UINT (36)
/* Event ID 37-39 is reserved */
/* McBSP0 receive interrupt */
#define CSL_INTC_EVENTID_RINT0 (40)
/* McBSP0 transmit interrupt */
#define CSL_INTC_EVENTID_XINT0 (41)
/* McBSP1 receive interrupt */
#define CSL_INTC_EVENTID_RINT1 (42)
/* McBSP1 transmit interrupt */
#define CSL_INTC_EVENTID_XINT1 (43)
/* Event ID 44-50 is reserved */
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT0 (51)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT1 (52)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT2 (53)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT3 (54)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT4 (55)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT5 (56)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT6 (57)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT7 (58)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT8 (59)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT9 (60)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT10 (61)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT11 (62)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT12 (63)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT13 (64)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT14 (65)
/* GPIO Interrupt */
#define CSL_INTC_EVENTID_GPINT15 (66)
/* Timer 0 lower counter interrupt */
#define CSL_INTC_EVENTID_TINTLO0 (67)
/* Timer 0 higher counter interrupt */
#define CSL_INTC_EVENTID_TINTHI0 (68)
/* Timer 1 lower counter interrupt */
#define CSL_INTC_EVENTID_TINTLO1 (69)
/* Timer 1 higher counter interrupt */
#define CSL_INTC_EVENTID_TINTHI1 (70)
/* CC Completion Interrupt - Mask0 */
#define CSL_INTC_EVENTID_EDMA3CC_INT0 (71)
/* CC Completion Interrupt - Mask1 */
#define CSL_INTC_EVENTID_EDMA3CC_INT1 (72)
/* CC Completion Interrupt - Mask2 */
#define CSL_INTC_EVENTID_EDMA3CC_INT2 (73)
/* CC Completion Interrupt - Mask3 */
#define CSL_INTC_EVENTID_EDMA3CC_INT3 (74)
/* CC Completion Interrupt - Mask4 */
#define CSL_INTC_EVENTID_EDMA3CC_INT4 (75)
/* CC Completion Interrupt - Mask5 */
#define CSL_INTC_EVENTID_EDMA3CC_INT5 (76)
/* CC Completion Interrupt - Mask6 */
#define CSL_INTC_EVENTID_EDMA3CC_INT6 (77)
/* CC Completion Interrupt - Mask7 */
#define CSL_INTC_EVENTID_EDMA3CC_INT7 (78)
/* CC Error Interrupt */
#define CSL_INTC_EVENTID_EDMA3CC_ERRINT (79)
/* CC Memory Protection Interrupt */
#define CSL_INTC_EVENTID_EDMA3CC_MPINT (80)
/* TC0 Error Interrupt */
#define CSL_INTC_EVENTID_EDMA3TC0_ERRINT (81)
/* TC1 Error Interrupt */
#define CSL_INTC_EVENTID_EDMA3TC1_ERRINT (82)
/* TC2 Error Interrupt */
#define CSL_INTC_EVENTID_EDMA3TC2_ERRINT (83)
/* TC3 Error Interrupt */
#define CSL_INTC_EVENTID_EDMA3TC3_ERRINT (84)
/* Event ID 85-95 is reserved */
/* Dropped CPU interrupt event */
#define CSL_INTC_EVENTID_INTERR (96)
/* EMC Invalid IDMA parameters */
#define CSL_INTC_EVENTID_EMC_IDMAERR (97)
/* Event ID 98 - 99 is reserved */
/* EFI Interrupt from side A */
#define CSL_INTC_EVENTID_EFIINTA (100)
/* EFI Interrupt from side B */
#define CSL_INTC_EVENTID_EFIINTB (101)
/* Event ID 102-117 is reserved */
/* Power Down sleep interrupt */
#define CSL_INTC_EVENTID_PDC_INT (118)
/* Event ID 119 is reserved */
/* L1P CPU memory protection fault */
#define CSL_INTC_EVENTID_L1P_CMPA (120)
/* L1P DMA memory protection fault */
#define CSL_INTC_EVENTID_L1P_DMPA (121)
/* L1D CPU memory protection fault */
#define CSL_INTC_EVENTID_L1D_CMPA (122)
/* L1D DMA memory protection fault */
#define CSL_INTC_EVENTID_L1D_DMPA (123)
/* L2 CPU memory protection fault */
#define CSL_INTC_EVENTID_L2_CMPA (124)
/* L2 DMA memory protection fault */
#define CSL_INTC_EVENTID_L2_DMPA (125)
/* IDMA CPU memory protection fault */
#define CSL_INTC_EVENTID_IDMA_CMPA (126)
/* IDMA Bus error interrupt */
#define CSL_INTC_EVENTID_IDMA_BUSERR (127)
/**** EDMA RELATED DEFINES *********/
/**************************************************************************\
* Parameterizable Configuration:- These are fed directly from the RTL
* parameters for the given SOC
\**************************************************************************/
#define CSL_EDMA3_NUM_DMACH 64
#define CSL_EDMA3_NUM_QDMACH 4
#define CSL_EDMA3_NUM_PARAMSETS 256
#define CSL_EDMA3_NUM_EVQUE 4
#define CSL_EDMA3_CHMAPEXIST 1
#define CSL_EDMA3_NUM_REGIONS 8
#define CSL_EDMA3_MEMPROTECT 1
/**************************************************************************\
* Channel Instance count
\**************************************************************************/
#define CSL_EDMA3_CHA_CNT 68
/* EDMA channel synchronization events */
/* HPI/PCI-to-DSP event */
#define CSL_EDMA3_CHA_DSP_EVT 0
/* Timer 0 lower counter event */
#define CSL_EDMA3_CHA_TEVTLO0 1
/* Timer 0 higher counter event */
#define CSL_EDMA3_CHA_TEVTHI0 2
/* EDMA3 channel 3 */
#define CSL_EDMA3_CHA_3 3
/* EDMA3 channel 4 */
#define CSL_EDMA3_CHA_4 4
/* EDMA3 channel 5 */
#define CSL_EDMA3_CHA_5 5
/* EDMA3 channel 6 */
#define CSL_EDMA3_CHA_6 6
/* EDMA3 channel 7 */
#define CSL_EDMA3_CHA_7 7
/* EDMA3 channel 8 */
#define CSL_EDMA3_CHA_8 8
/* EDMA3 channel 9 */
#define CSL_EDMA3_CHA_9 9
/* EDMA3 channel 10 */
#define CSL_EDMA3_CHA_10 10
/* EDMA3 channel 11 */
#define CSL_EDMA3_CHA_11 11
/* McBSP0 transmit event */
#define CSL_EDMA3_CHA_XEVT0 12
/* McBSP0 receive event */
#define CSL_EDMA3_CHA_REVT0 13
/* McBSP1 transmit event */
#define CSL_EDMA3_CHA_XEVT1 14
/* McBSP1 receive event */
#define CSL_EDMA3_CHA_REVT1 15
/* Timer 1 lower counter event */
#define CSL_EDMA3_CHA_TEVTLO1 16
/* Timer 1 higher counter event */
#define CSL_EDMA3_CHA_TEVTHI1 17
/* EDMA channel 18*/
#define CSL_EDMA3_CHA_18 18
/* EDMA3 channel 19*/
#define CSL_EDMA3_CHA_19 19
/* Rapid IO Interrupt 1 */
#define CSL_EDMA3_CHA_RIOINT1 20
/* EDMA3 channel 21*/
#define CSL_EDMA3_CHA_21 21
/* EDMA3 channel 22*/
#define CSL_EDMA3_CHA_22 22
/* EDMA3 channel 23*/
#define CSL_EDMA3_CHA_23 23
/* EDMA3 channel 24*/
#define CSL_EDMA3_CHA_24 24
/* EDMA3 channel 25*/
#define CSL_EDMA3_CHA_25 25
/* EDMA3 channel 26*/
#define CSL_EDMA3_CHA_26 26
/* EDMA3 channel 27*/
#define CSL_EDMA3_CHA_27 27
/* VCP2 receive event */
#define CSL_EDMA3_CHA_VCP2REVT 28
/* VCP2 transmit event */
#define CSL_EDMA3_CHA_VCP2XEVT 29
/* TCP2 receive event */
#define CSL_EDMA3_CHA_TCP2REVT 30
/* TCP2 transmit event */
#define CSL_EDMA3_CHA_TCP2XEVT 31
/* UTOPIA receive event */
#define CSL_EDMA3_CHA_UREVT 32
/* EDMA3 channel 33 */
#define CSL_EDMA3_CHA_33 33
/* EDMA3 channel 34 */
#define CSL_EDMA3_CHA_34 34
/* EDMA3 channel 35 */
#define CSL_EDMA3_CHA_35 35
/* EDMA3 channel 36 */
#define CSL_EDMA3_CHA_36 36
/* EDMA3 channel 37 */
#define CSL_EDMA3_CHA_37 37
/* EDMA3 channel 38 */
#define CSL_EDMA3_CHA_38 38
/* EDMA3 channel 39 */
#define CSL_EDMA3_CHA_39 39
/* UTOPIA transmit event */
#define CSL_EDMA3_CHA_UXEVT 40
/* EDMA3 channel 41*/
#define CSL_EDMA3_CHA_41 41
/* EDMA3 channel 42*/
#define CSL_EDMA3_CHA_42 42
/* EDMA3 channel 43*/
#define CSL_EDMA3_CHA_43 43
/* I2C receive event */
#define CSL_EDMA3_CHA_ICREVT 44
/* I2C transmit event */
#define CSL_EDMA3_CHA_ICXEVT 45
/** EDMA3 channel 46*/
#define CSL_EDMA3_CHA_46 46
/** EDMA3 channel 47*/
#define CSL_EDMA3_CHA_47 47
/* GPIO event 0 */
#define CSL_EDMA3_CHA_GPINT0 48
/* GPIO event 1 */
#define CSL_EDMA3_CHA_GPINT1 49
/* GPIO event 2 */
#define CSL_EDMA3_CHA_GPINT2 50
/* GPIO event 3 */
#define CSL_EDMA3_CHA_GPINT3 51
/* GPIO event 4 */
#define CSL_EDMA3_CHA_GPINT4 52
/* GPIO event 5 */
#define CSL_EDMA3_CHA_GPINT5 53
/* GPIO event 6 */
#define CSL_EDMA3_CHA_GPINT6 54
/* GPIO event 7 */
#define CSL_EDMA3_CHA_GPINT7 55
/* GPIO event 8 */
#define CSL_EDMA3_CHA_GPINT8 56
/* GPIO event 9 */
#define CSL_EDMA3_CHA_GPINT9 57
/* GPIO event 10 */
#define CSL_EDMA3_CHA_GPINT10 58
/* GPIO event 11 */
#define CSL_EDMA3_CHA_GPINT11 59
/* GPIO event 12 */
#define CSL_EDMA3_CHA_GPINT12 60
/* GPIO event 13 */
#define CSL_EDMA3_CHA_GPINT13 61
/* GPIO event 14 */
#define CSL_EDMA3_CHA_GPINT14 62
/* GPIO event 15 */
#define CSL_EDMA3_CHA_GPINT15 63
/* QDMA channels */
#define CSL_EDMA3_QCHA_0 64 /* QDMA Channel 0*/
#define CSL_EDMA3_QCHA_1 65 /* QDMA Channel 1*/
#define CSL_EDMA3_QCHA_2 66 /* QDMA Channel 2*/
#define CSL_EDMA3_QCHA_3 67 /* QDMA Channel 3*/
/* Enumerations for EDMA Event Queues */
typedef enum {
CSL_EDMA3_QUE_0 = 0, /* Queue 0 */
CSL_EDMA3_QUE_1 = 1, /* Queue 1 */
CSL_EDMA3_QUE_2 = 2, /* Queue 2 */
CSL_EDMA3_QUE_3 = 3 /* Queue 3 */
} CSL_Edma3Que;
/* Enumerations for EDMA Transfer Controllers
*
* There are 4 Transfer Controllers. Typically a one to one mapping exists
* between Event Queues and Transfer Controllers.
*
*/
typedef enum {
CSL_EDMA3_TC_0 = 0, /* TC 0 */
CSL_EDMA3_TC_1 = 1, /* TC 1 */
CSL_EDMA3_TC_2 = 2, /* TC 2 */
CSL_EDMA3_TC_3 = 3 /* TC 3 */
} CSL_Edma3Tc;
#define CSL_EDMA3_REGION_GLOBAL -1
#define CSL_EDMA3_REGION_0 0
#define CSL_EDMA3_REGION_1 1
#define CSL_EDMA3_REGION_2 2
#define CSL_EDMA3_REGION_3 3
#define CSL_EDMA3_REGION_4 4
#define CSL_EDMA3_REGION_5 5
#define CSL_EDMA3_REGION_6 6
#define CSL_EDMA3_REGION_7 7
/*********** DAT RELATED DEFINES ******************/
/**************************************************************************\
* Parameterizable Configuration:- These are fed directly from the RTL
* parameters for the given SOC
\**************************************************************************/
/**************************************************************************\
* Channel Instance count
\**************************************************************************/
/** @brief Number of Generic Channel instances */
/** @brief Enumerations for EDMA channels
*
* There are 4 QDMA channels -
*
*/
#define CSL_DAT_QCHA_0 0 /* QDMA Channel 0*/
#define CSL_DAT_QCHA_1 1 /* QDMA Channel 1*/
#define CSL_DAT_QCHA_2 2 /* QDMA Channel 2*/
#define CSL_DAT_QCHA_3 3 /* QDMA Channel 3*/
/** @brief Enumerations for EDMA Event Queues
*
* There are 8 Event Queues. Q0 is the highest priority and Q3 is the least priority
*
*/
typedef enum {
CSL_DAT_PRI_DEFAULT = 0, /* Queue 0 is default */
CSL_DAT_PRI_0 = 0, /* Queue 0 */
CSL_DAT_PRI_1 = 1, /* Queue 1 */
CSL_DAT_PRI_2 = 2, /* Queue 2 */
CSL_DAT_PRI_3 = 3 /* Queue 3 */
} CSL_DatPriority;
/** @brief Enumeration for EDMA Regions
*
*
*/
#define CSL_DAT_REGION_GLOBAL -1 /* Global Region */
#define CSL_DAT_REGION_0 0 /* EDMA Region 0 */
#define CSL_DAT_REGION_1 1 /* EDMA Region 1 */
#define CSL_DAT_REGION_2 2 /* EDMA Region 2 */
#define CSL_DAT_REGION_3 3 /* EDMA Region 3 */
#define CSL_DAT_REGION_4 4 /* EDMA Region 4 */
#define CSL_DAT_REGION_5 5 /* EDMA Region 5 */
#define CSL_DAT_REGION_6 6 /* EDMA Region 6 */
#define CSL_DAT_REGION_7 7 /* EDMA Region 7 */
#endif /* _SOC_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_tsc.h
|
<filename>DSP/TI-Header/csl_c6455_src/inc/csl_tsc.h<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004,2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* provided
* ============================================================================
*/
/** ============================================================================
* @file csl_tsc.h
*
* @path $(CSLPATH)\inc
*
* @desc Header file for functional layer of CSL
*
*/
/** @mainpage Time Stamp Counter Module
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to identify a set of common CSL APIs for
* the Time Stamp Counter
*
* @subsection aaa Terms and Abbreviations
* -# CSL : Chip Support Library
* -# API : Application Programmer Interface
* -# TSC : Time Stamp Counter
*
* @subsection Assumptions
* The abbreviations CSL, TSC have been used throughout this
* document to refer to the C64Plus Time Stamp Counter
*/
/* =============================================================================
* Revision History
* ===============
* 09-Jun-2004 <NAME> File Created.
*
* 14-Nov-2005 ds - Removed CSL_ctimerStart() and CSL_ctimerRead ().
* - Added CSL_tscEnable() and CSL_tscRead ()
* =============================================================================
*/
#ifndef _CSL_TSC_H_
#define _CSL_TSC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
/** ===========================================================================
* @n@b CSL_tscEnable
*
* @b Description
* @n This API enable the 64 bit time stamp counter. The Time Stamp Counter
* (TSC) stops only upon Reset or powerdown. When time stamp counter is
* enabled (following a reset or powerdown of the CPU) it will initialize
* to 0 and begin incrementing once per CPU cycle. You cannot reset the
* time stamp counter.
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Time Stamp Counter value starts incrementing
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_tscEnable ();
* @endverbatim
* ============================================================================
*/
extern void CSL_tscEnable(void);
/** ============================================================================
* @n@b CSL_tscRead
*
* @b Description
* @n Reads the 64 bit timer stamp conter and return the 64-bit counter value.
*
* @b Arguments
* @verbatim
None
@endverbatim
*
* <b> Return Value </b> CSL_Uint64
* @li 64 Bit Time Stamp Counter value
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies None
*
* @b Example
* @verbatim
CSL_Uint64 counterVal;
...
CSL_tscStart();
counterVal = CSL_tscRead();
* @endverbatim
* ============================================================================
*/
extern CSL_Uint64 CSL_tscRead (void);
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_hpiAux.h
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ===========================================================================
*/
/**
* @file csl_hpiAux.h
*
* @path $(CSLPATH)\inc
*
* @brief HPI CSL implementation on DSP side.
*
*/
/* =============================================================================
* Revision History
* ===============
* 06-Feb-2006 ds Updated according to TCI6482/C6455 User Guide
*
* =============================================================================
*/
#ifndef _CSL_HPIAUX_H_
#define _CSL_HPIAUX_H_
#include <csl_hpi.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Hardware Control functions of the hpi */
/** ============================================================================
* @n@b CSL_hpiSetDspInt
*
* @b Description
* @n Gets the HPIC Host-to-DSP Interrupt status of the hpi.
*
* @b Arguments
* @verbatim
hHpi Handle to the HPI instance
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Sets the DSP_INT bit of HPIC register
*
* @b Example
* @verbatim
CSL_HpiHandle hHpi;
CSL_hpiSetDspInt(hHpi);
@endverbatim
* =============================================================================
*/
static inline
void CSL_hpiSetDspInt (
CSL_HpiHandle hHpi
)
{
CSL_FINS(hHpi->regs->HPIC, HPI_HPIC_DSPINT, TRUE);
}
/** ============================================================================
* @n@b CSL_hpiResetDspInt
*
* @b Description
* @n Gets the Reset HPIC Host-to-DSP Interrupt status of the hpi.
*
* @b Arguments
* @verbatim
hHpi Handle to the HPI instance
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Resets the DSP_INT bit of HPIC register
*
* @b Example
* @verbatim
CSL_HpiHandle hHpi;
CSL_hpiResetDspInt(hHpi);
@endverbatim
* =============================================================================
*/
static inline
void CSL_hpiResetDspInt (
CSL_HpiHandle hHpi
)
{
CSL_FINS(hHpi->regs->HPIC, HPI_HPIC_DSPINT, FALSE);
}
/** ============================================================================
* @n@b CSL_hpiSetHint
*
* @b Description
* @n Gets the HPIC DSP-to-Host Interrupt status of the hpi.
*
* @b Arguments
* @verbatim
hHpi Handle to the HPI instance
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Sets the HINT bit of HPIC register
*
* @b Example
* @verbatim
CSL_HpiHandle hHpi;
CSL_hpiSetHint(hHpi);
@endverbatim
* =============================================================================
*/
static inline
void CSL_hpiSetHint (
CSL_HpiHandle hHpi
)
{
CSL_FINS(hHpi->regs->HPIC, HPI_HPIC_HINT, TRUE);
}
/** ============================================================================
* @n@b CSL_hpiResetHint
*
* @b Description
* @n Gets the Reset HPIC DSP-to-Host Interrupt status of the hpi.
*
* @b Arguments
* @verbatim
hHpi Handle to the HPI instance
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Resets the HINT bit of HPIC register
*
* @b Example
* @verbatim
CSL_HpiHandle hHpi;
CSL_hpiSetHint(hHpi);
@endverbatim
* =============================================================================
*/
static inline
void CSL_hpiResetHint (
CSL_HpiHandle hHpi
)
{
CSL_FINS(hHpi->regs->HPIC, HPI_HPIC_HINT, FALSE);
}
/** ===========================================================================
* @n@b CSL_hpiGetHpicHrdy
*
* @b Description
* @n This function gets HRDY bit of the HPIC.
*
* @b Arguments
* @verbatim
hHpi Handle to HPI instance
response Placeholder to return status.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_hpiGetHpicHrdy(hHpi, &response);
@endverbatim
* ===========================================================================
*/
static inline
void CSL_hpiGetHpicHrdy (
CSL_HpiHandle hHpi,
void *response
)
{
*((Uint32 *)response) = CSL_FEXT(hHpi->regs->HPIC, HPI_HPIC_HRDY);
}
/** ===========================================================================
* @n@b CSL_hpiGetHpicFetch
*
* @b Description
* @n This function gets FETCH bit of the HPIC Register.
*
* @b Arguments
* @verbatim
hHpi Handle to HPI instance
response Placeholder to return status.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_hpiGetHpicFetch(hHpi, &response);
@endverbatim
* ===========================================================================
*/
static inline
void CSL_hpiGetHpicFetch (
CSL_HpiHandle hHpi,
void *response
)
{
*((Uint32 *)response) = CSL_FEXT(hHpi->regs->HPIC, HPI_HPIC_FETCH);
}
/** ===========================================================================
* @n@b CSL_hpiGetHpicHpiRst
*
* @b Description
* @n This function gets HPI_RST bit of the HPIC Register.
*
* @b Arguments
* @verbatim
hHpi Handle to HPI instance
response Placeholder to return status.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_hpiGetHpicHpiRst(hHpi, &response);
@endverbatim
* ===========================================================================
*/
static inline
void CSL_hpiGetHpicHpiRst (
CSL_HpiHandle hHpi,
void *response
)
{
*((Uint32 *)response) = CSL_FEXT(hHpi->regs->HPIC, HPI_HPIC_HPIRST);
}
/** ===========================================================================
* @n@b CSL_hpiGetHpicHwobStat
*
* @b Description
* @n This function gets HWOB_STAT bit of the HPIC Register.
*
* @b Arguments
* @verbatim
hHpi Handle to HPI instance
response Placeholder to return status.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_hpiGetHpicHwobStat(hHpi, &response);
@endverbatim
* ===========================================================================
*/
static inline
void CSL_hpiGetHpicHwobStat (
CSL_HpiHandle hHpi,
void *response
)
{
*((Uint32 *)response) = CSL_FEXT(hHpi->regs->HPIC, HPI_HPIC_HWOBSTAT);
}
#ifdef __cplusplus
}
#endif
#endif /* _CSL_HPIAUX_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_gpio.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_gpio.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for GPIO
*/
#ifndef _CSLR_GPIO_H_
#define _CSLR_GPIO_H_
#include <cslr.h>
#include <tistdtypes.h>
#define CSL_GPIO_NUM_PINS (16)
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint8 RSVD0[8];
volatile Uint32 BINTEN;
volatile Uint8 RSVD1[4];
volatile Uint32 DIR;
volatile Uint32 OUT_DATA;
volatile Uint32 SET_DATA;
volatile Uint32 CLR_DATA;
volatile Uint32 IN_DATA;
volatile Uint32 SET_RIS_TRIG;
volatile Uint32 CLR_RIS_TRIG;
volatile Uint32 SET_FAL_TRIG;
volatile Uint32 CLR_FAL_TRIG;
} CSL_GpioRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_GpioRegs *CSL_GpioRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* BINTEN */
#define CSL_GPIO_BINTEN_EN_MASK (0x00000001u)
#define CSL_GPIO_BINTEN_EN_SHIFT (0x00000000u)
#define CSL_GPIO_BINTEN_EN_RESETVAL (0x00000000u)
/*----EN Tokens----*/
#define CSL_GPIO_BINTEN_EN_DISABLE (0x00000000u)
#define CSL_GPIO_BINTEN_EN_ENABLE (0x00000001u)
#define CSL_GPIO_BINTEN_RESETVAL (0x00000000u)
/* DIR */
#define CSL_GPIO_DIR_DIR15_MASK (0x00008000u)
#define CSL_GPIO_DIR_DIR15_SHIFT (0x0000000Fu)
#define CSL_GPIO_DIR_DIR15_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR14_MASK (0x00004000u)
#define CSL_GPIO_DIR_DIR14_SHIFT (0x0000000Eu)
#define CSL_GPIO_DIR_DIR14_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR13_MASK (0x00002000u)
#define CSL_GPIO_DIR_DIR13_SHIFT (0x0000000Du)
#define CSL_GPIO_DIR_DIR13_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR12_MASK (0x00001000u)
#define CSL_GPIO_DIR_DIR12_SHIFT (0x0000000Cu)
#define CSL_GPIO_DIR_DIR12_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR11_MASK (0x00000800u)
#define CSL_GPIO_DIR_DIR11_SHIFT (0x0000000Bu)
#define CSL_GPIO_DIR_DIR11_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR10_MASK (0x00000400u)
#define CSL_GPIO_DIR_DIR10_SHIFT (0x0000000Au)
#define CSL_GPIO_DIR_DIR10_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR9_MASK (0x00000200u)
#define CSL_GPIO_DIR_DIR9_SHIFT (0x00000009u)
#define CSL_GPIO_DIR_DIR9_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR8_MASK (0x00000100u)
#define CSL_GPIO_DIR_DIR8_SHIFT (0x00000008u)
#define CSL_GPIO_DIR_DIR8_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR7_MASK (0x00000080u)
#define CSL_GPIO_DIR_DIR7_SHIFT (0x00000007u)
#define CSL_GPIO_DIR_DIR7_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR6_MASK (0x00000040u)
#define CSL_GPIO_DIR_DIR6_SHIFT (0x00000006u)
#define CSL_GPIO_DIR_DIR6_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR5_MASK (0x00000020u)
#define CSL_GPIO_DIR_DIR5_SHIFT (0x00000005u)
#define CSL_GPIO_DIR_DIR5_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR4_MASK (0x00000010u)
#define CSL_GPIO_DIR_DIR4_SHIFT (0x00000004u)
#define CSL_GPIO_DIR_DIR4_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR3_MASK (0x00000008u)
#define CSL_GPIO_DIR_DIR3_SHIFT (0x00000003u)
#define CSL_GPIO_DIR_DIR3_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR2_MASK (0x00000004u)
#define CSL_GPIO_DIR_DIR2_SHIFT (0x00000002u)
#define CSL_GPIO_DIR_DIR2_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR1_MASK (0x00000002u)
#define CSL_GPIO_DIR_DIR1_SHIFT (0x00000001u)
#define CSL_GPIO_DIR_DIR1_RESETVAL (0x00000001u)
#define CSL_GPIO_DIR_DIR0_MASK (0x00000001u)
#define CSL_GPIO_DIR_DIR0_SHIFT (0x00000000u)
#define CSL_GPIO_DIR_DIR0_RESETVAL (0x00000001u)
/*----DIR Tokens----*/
#define CSL_GPIO_DIR_DIR_OUT (0x00000000u)
#define CSL_GPIO_DIR_DIR_IN (0x00000001u)
#define CSL_GPIO_DIR_RESETVAL (0x0000FFFFu)
/* OUT_DATA */
#define CSL_GPIO_OUT_DATA_OUT15_MASK (0x00008000u)
#define CSL_GPIO_OUT_DATA_OUT15_SHIFT (0x0000000Fu)
#define CSL_GPIO_OUT_DATA_OUT15_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT14_MASK (0x00004000u)
#define CSL_GPIO_OUT_DATA_OUT14_SHIFT (0x0000000Eu)
#define CSL_GPIO_OUT_DATA_OUT14_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT13_MASK (0x00002000u)
#define CSL_GPIO_OUT_DATA_OUT13_SHIFT (0x0000000Du)
#define CSL_GPIO_OUT_DATA_OUT13_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT12_MASK (0x00001000u)
#define CSL_GPIO_OUT_DATA_OUT12_SHIFT (0x0000000Cu)
#define CSL_GPIO_OUT_DATA_OUT12_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT11_MASK (0x00000800u)
#define CSL_GPIO_OUT_DATA_OUT11_SHIFT (0x0000000Bu)
#define CSL_GPIO_OUT_DATA_OUT11_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT10_MASK (0x00000400u)
#define CSL_GPIO_OUT_DATA_OUT10_SHIFT (0x0000000Au)
#define CSL_GPIO_OUT_DATA_OUT10_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT9_MASK (0x00000200u)
#define CSL_GPIO_OUT_DATA_OUT9_SHIFT (0x00000009u)
#define CSL_GPIO_OUT_DATA_OUT9_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT8_MASK (0x00000100u)
#define CSL_GPIO_OUT_DATA_OUT8_SHIFT (0x00000008u)
#define CSL_GPIO_OUT_DATA_OUT8_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT7_MASK (0x00000080u)
#define CSL_GPIO_OUT_DATA_OUT7_SHIFT (0x00000007u)
#define CSL_GPIO_OUT_DATA_OUT7_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT6_MASK (0x00000040u)
#define CSL_GPIO_OUT_DATA_OUT6_SHIFT (0x00000006u)
#define CSL_GPIO_OUT_DATA_OUT6_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT5_MASK (0x00000020u)
#define CSL_GPIO_OUT_DATA_OUT5_SHIFT (0x00000005u)
#define CSL_GPIO_OUT_DATA_OUT5_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT4_MASK (0x00000010u)
#define CSL_GPIO_OUT_DATA_OUT4_SHIFT (0x00000004u)
#define CSL_GPIO_OUT_DATA_OUT4_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT3_MASK (0x00000008u)
#define CSL_GPIO_OUT_DATA_OUT3_SHIFT (0x00000003u)
#define CSL_GPIO_OUT_DATA_OUT3_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT2_MASK (0x00000004u)
#define CSL_GPIO_OUT_DATA_OUT2_SHIFT (0x00000002u)
#define CSL_GPIO_OUT_DATA_OUT2_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT1_MASK (0x00000002u)
#define CSL_GPIO_OUT_DATA_OUT1_SHIFT (0x00000001u)
#define CSL_GPIO_OUT_DATA_OUT1_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT0_MASK (0x00000001u)
#define CSL_GPIO_OUT_DATA_OUT0_SHIFT (0x00000000u)
#define CSL_GPIO_OUT_DATA_OUT0_RESETVAL (0x00000000u)
#define CSL_GPIO_OUT_DATA_RESETVAL (0x00000000u)
/* SET_DATA */
#define CSL_GPIO_SET_DATA_SET15_MASK (0x00008000u)
#define CSL_GPIO_SET_DATA_SET15_SHIFT (0x0000000Fu)
#define CSL_GPIO_SET_DATA_SET15_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET14_MASK (0x00004000u)
#define CSL_GPIO_SET_DATA_SET14_SHIFT (0x0000000Eu)
#define CSL_GPIO_SET_DATA_SET14_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET13_MASK (0x00002000u)
#define CSL_GPIO_SET_DATA_SET13_SHIFT (0x0000000Du)
#define CSL_GPIO_SET_DATA_SET13_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET12_MASK (0x00001000u)
#define CSL_GPIO_SET_DATA_SET12_SHIFT (0x0000000Cu)
#define CSL_GPIO_SET_DATA_SET12_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET11_MASK (0x00000800u)
#define CSL_GPIO_SET_DATA_SET11_SHIFT (0x0000000Bu)
#define CSL_GPIO_SET_DATA_SET11_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET10_MASK (0x00000400u)
#define CSL_GPIO_SET_DATA_SET10_SHIFT (0x0000000Au)
#define CSL_GPIO_SET_DATA_SET10_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET9_MASK (0x00000200u)
#define CSL_GPIO_SET_DATA_SET9_SHIFT (0x00000009u)
#define CSL_GPIO_SET_DATA_SET9_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET8_MASK (0x00000100u)
#define CSL_GPIO_SET_DATA_SET8_SHIFT (0x00000008u)
#define CSL_GPIO_SET_DATA_SET8_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET7_MASK (0x00000080u)
#define CSL_GPIO_SET_DATA_SET7_SHIFT (0x00000007u)
#define CSL_GPIO_SET_DATA_SET7_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET6_MASK (0x00000040u)
#define CSL_GPIO_SET_DATA_SET6_SHIFT (0x00000006u)
#define CSL_GPIO_SET_DATA_SET6_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET5_MASK (0x00000020u)
#define CSL_GPIO_SET_DATA_SET5_SHIFT (0x00000005u)
#define CSL_GPIO_SET_DATA_SET5_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET4_MASK (0x00000010u)
#define CSL_GPIO_SET_DATA_SET4_SHIFT (0x00000004u)
#define CSL_GPIO_SET_DATA_SET4_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET3_MASK (0x00000008u)
#define CSL_GPIO_SET_DATA_SET3_SHIFT (0x00000003u)
#define CSL_GPIO_SET_DATA_SET3_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET2_MASK (0x00000004u)
#define CSL_GPIO_SET_DATA_SET2_SHIFT (0x00000002u)
#define CSL_GPIO_SET_DATA_SET2_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET1_MASK (0x00000002u)
#define CSL_GPIO_SET_DATA_SET1_SHIFT (0x00000001u)
#define CSL_GPIO_SET_DATA_SET1_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_DATA_SET0_MASK (0x00000001u)
#define CSL_GPIO_SET_DATA_SET0_SHIFT (0x00000000u)
#define CSL_GPIO_SET_DATA_SET0_RESETVAL (0x00000000u)
/*----SET Tokens----*/
#define CSL_GPIO_SET_DATA_SET_SET (0x00000001u)
#define CSL_GPIO_SET_DATA_RESETVAL (0x00000000u)
/* CLR_DATA */
#define CSL_GPIO_CLR_DATA_CLR15_MASK (0x00008000u)
#define CSL_GPIO_CLR_DATA_CLR15_SHIFT (0x0000000Fu)
#define CSL_GPIO_CLR_DATA_CLR15_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR14_MASK (0x00004000u)
#define CSL_GPIO_CLR_DATA_CLR14_SHIFT (0x0000000Eu)
#define CSL_GPIO_CLR_DATA_CLR14_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR13_MASK (0x00002000u)
#define CSL_GPIO_CLR_DATA_CLR13_SHIFT (0x0000000Du)
#define CSL_GPIO_CLR_DATA_CLR13_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR12_MASK (0x00001000u)
#define CSL_GPIO_CLR_DATA_CLR12_SHIFT (0x0000000Cu)
#define CSL_GPIO_CLR_DATA_CLR12_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR11_MASK (0x00000800u)
#define CSL_GPIO_CLR_DATA_CLR11_SHIFT (0x0000000Bu)
#define CSL_GPIO_CLR_DATA_CLR11_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR10_MASK (0x00000400u)
#define CSL_GPIO_CLR_DATA_CLR10_SHIFT (0x0000000Au)
#define CSL_GPIO_CLR_DATA_CLR10_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR9_MASK (0x00000200u)
#define CSL_GPIO_CLR_DATA_CLR9_SHIFT (0x00000009u)
#define CSL_GPIO_CLR_DATA_CLR9_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR8_MASK (0x00000100u)
#define CSL_GPIO_CLR_DATA_CLR8_SHIFT (0x00000008u)
#define CSL_GPIO_CLR_DATA_CLR8_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR7_MASK (0x00000080u)
#define CSL_GPIO_CLR_DATA_CLR7_SHIFT (0x00000007u)
#define CSL_GPIO_CLR_DATA_CLR7_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR6_MASK (0x00000040u)
#define CSL_GPIO_CLR_DATA_CLR6_SHIFT (0x00000006u)
#define CSL_GPIO_CLR_DATA_CLR6_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR5_MASK (0x00000020u)
#define CSL_GPIO_CLR_DATA_CLR5_SHIFT (0x00000005u)
#define CSL_GPIO_CLR_DATA_CLR5_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR4_MASK (0x00000010u)
#define CSL_GPIO_CLR_DATA_CLR4_SHIFT (0x00000004u)
#define CSL_GPIO_CLR_DATA_CLR4_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR3_MASK (0x00000008u)
#define CSL_GPIO_CLR_DATA_CLR3_SHIFT (0x00000003u)
#define CSL_GPIO_CLR_DATA_CLR3_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR2_MASK (0x00000004u)
#define CSL_GPIO_CLR_DATA_CLR2_SHIFT (0x00000002u)
#define CSL_GPIO_CLR_DATA_CLR2_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR1_MASK (0x00000002u)
#define CSL_GPIO_CLR_DATA_CLR1_SHIFT (0x00000001u)
#define CSL_GPIO_CLR_DATA_CLR1_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR0_MASK (0x00000001u)
#define CSL_GPIO_CLR_DATA_CLR0_SHIFT (0x00000000u)
#define CSL_GPIO_CLR_DATA_CLR0_RESETVAL (0x00000000u)
/*----CLR Tokens----*/
#define CSL_GPIO_CLR_DATA_CLR_CLR (0x00000001u)
#define CSL_GPIO_CLR_DATA_RESETVAL (0x00000000u)
/* IN_DATA */
#define CSL_GPIO_IN_DATA_IN15_MASK (0x00008000u)
#define CSL_GPIO_IN_DATA_IN15_SHIFT (0x0000000Fu)
#define CSL_GPIO_IN_DATA_IN15_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN14_MASK (0x00004000u)
#define CSL_GPIO_IN_DATA_IN14_SHIFT (0x0000000Eu)
#define CSL_GPIO_IN_DATA_IN14_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN13_MASK (0x00002000u)
#define CSL_GPIO_IN_DATA_IN13_SHIFT (0x0000000Du)
#define CSL_GPIO_IN_DATA_IN13_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN12_MASK (0x00001000u)
#define CSL_GPIO_IN_DATA_IN12_SHIFT (0x0000000Cu)
#define CSL_GPIO_IN_DATA_IN12_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN11_MASK (0x00000800u)
#define CSL_GPIO_IN_DATA_IN11_SHIFT (0x0000000Bu)
#define CSL_GPIO_IN_DATA_IN11_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN10_MASK (0x00000400u)
#define CSL_GPIO_IN_DATA_IN10_SHIFT (0x0000000Au)
#define CSL_GPIO_IN_DATA_IN10_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN9_MASK (0x00000200u)
#define CSL_GPIO_IN_DATA_IN9_SHIFT (0x00000009u)
#define CSL_GPIO_IN_DATA_IN9_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN8_MASK (0x00000100u)
#define CSL_GPIO_IN_DATA_IN8_SHIFT (0x00000008u)
#define CSL_GPIO_IN_DATA_IN8_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN7_MASK (0x00000080u)
#define CSL_GPIO_IN_DATA_IN7_SHIFT (0x00000007u)
#define CSL_GPIO_IN_DATA_IN7_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN6_MASK (0x00000040u)
#define CSL_GPIO_IN_DATA_IN6_SHIFT (0x00000006u)
#define CSL_GPIO_IN_DATA_IN6_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN5_MASK (0x00000020u)
#define CSL_GPIO_IN_DATA_IN5_SHIFT (0x00000005u)
#define CSL_GPIO_IN_DATA_IN5_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN4_MASK (0x00000010u)
#define CSL_GPIO_IN_DATA_IN4_SHIFT (0x00000004u)
#define CSL_GPIO_IN_DATA_IN4_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN3_MASK (0x00000008u)
#define CSL_GPIO_IN_DATA_IN3_SHIFT (0x00000003u)
#define CSL_GPIO_IN_DATA_IN3_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN2_MASK (0x00000004u)
#define CSL_GPIO_IN_DATA_IN2_SHIFT (0x00000002u)
#define CSL_GPIO_IN_DATA_IN2_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN1_MASK (0x00000002u)
#define CSL_GPIO_IN_DATA_IN1_SHIFT (0x00000001u)
#define CSL_GPIO_IN_DATA_IN1_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_IN0_MASK (0x00000001u)
#define CSL_GPIO_IN_DATA_IN0_SHIFT (0x00000000u)
#define CSL_GPIO_IN_DATA_IN0_RESETVAL (0x00000000u)
#define CSL_GPIO_IN_DATA_RESETVAL (0x00000000u)
/* SET_RIS_TRIG */
#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_MASK (0x00008000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_SHIFT (0x0000000Fu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_MASK (0x00004000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_SHIFT (0x0000000Eu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_MASK (0x00002000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_SHIFT (0x0000000Du)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_MASK (0x00001000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_SHIFT (0x0000000Cu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_MASK (0x00000800u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_SHIFT (0x0000000Bu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_MASK (0x00000400u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_SHIFT (0x0000000Au)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_MASK (0x00000200u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_SHIFT (0x00000009u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_MASK (0x00000100u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_SHIFT (0x00000008u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_MASK (0x00000080u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_SHIFT (0x00000007u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_MASK (0x00000040u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_SHIFT (0x00000006u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_MASK (0x00000020u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_SHIFT (0x00000005u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_MASK (0x00000010u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_SHIFT (0x00000004u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_MASK (0x00000008u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_SHIFT (0x00000003u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_MASK (0x00000004u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_SHIFT (0x00000002u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_MASK (0x00000002u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_SHIFT (0x00000001u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_MASK (0x00000001u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_SHIFT (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_RESETVAL (0x00000000u)
/*----SETRIS Tokens----*/
#define CSL_GPIO_SET_RIS_TRIG_SETRIS_ENABLE (0x00000001u)
#define CSL_GPIO_SET_RIS_TRIG_RESETVAL (0x00000000u)
/* CLR_RIS_TRIG */
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_MASK (0x00008000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_SHIFT (0x0000000Fu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_MASK (0x00004000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_SHIFT (0x0000000Eu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_MASK (0x00002000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_SHIFT (0x0000000Du)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_MASK (0x00001000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_SHIFT (0x0000000Cu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_MASK (0x00000800u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_SHIFT (0x0000000Bu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_MASK (0x00000400u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_SHIFT (0x0000000Au)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_MASK (0x00000200u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_SHIFT (0x00000009u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_MASK (0x00000100u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_SHIFT (0x00000008u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_MASK (0x00000080u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_SHIFT (0x00000007u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_MASK (0x00000040u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_SHIFT (0x00000006u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_MASK (0x00000020u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_SHIFT (0x00000005u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_MASK (0x00000010u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_SHIFT (0x00000004u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_MASK (0x00000008u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_SHIFT (0x00000003u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_MASK (0x00000004u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_SHIFT (0x00000002u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_MASK (0x00000002u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_SHIFT (0x00000001u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_MASK (0x00000001u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_SHIFT (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_RESETVAL (0x00000000u)
/*----CLRRIS Tokens----*/
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS_DISABLE (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_RESETVAL (0x00000000u)
/* SET_FAL_TRIG */
#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_MASK (0x00008000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_SHIFT (0x0000000Fu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_MASK (0x00004000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_SHIFT (0x0000000Eu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_MASK (0x00002000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_SHIFT (0x0000000Du)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_MASK (0x00001000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_SHIFT (0x0000000Cu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_MASK (0x00000800u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_SHIFT (0x0000000Bu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_MASK (0x00000400u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_SHIFT (0x0000000Au)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_MASK (0x00000200u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_SHIFT (0x00000009u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_MASK (0x00000100u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_SHIFT (0x00000008u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_MASK (0x00000080u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_SHIFT (0x00000007u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_MASK (0x00000040u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_SHIFT (0x00000006u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_MASK (0x00000020u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_SHIFT (0x00000005u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_MASK (0x00000010u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_SHIFT (0x00000004u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_MASK (0x00000008u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_SHIFT (0x00000003u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_MASK (0x00000004u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_SHIFT (0x00000002u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_MASK (0x00000002u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_SHIFT (0x00000001u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_RESETVAL (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_MASK (0x00000001u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_SHIFT (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_RESETVAL (0x00000000u)
/*----SETFAL Tokens----*/
#define CSL_GPIO_SET_FAL_TRIG_SETFAL_ENABLE (0x00000001u)
#define CSL_GPIO_SET_FAL_TRIG_RESETVAL (0x00000000u)
/* CLR_FAL_TRIG */
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_MASK (0x00008000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_SHIFT (0x0000000Fu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_MASK (0x00004000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_SHIFT (0x0000000Eu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_MASK (0x00002000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_SHIFT (0x0000000Du)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_MASK (0x00001000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_SHIFT (0x0000000Cu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_MASK (0x00000800u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_SHIFT (0x0000000Bu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_MASK (0x00000400u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_SHIFT (0x0000000Au)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_MASK (0x00000200u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_SHIFT (0x00000009u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_MASK (0x00000100u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_SHIFT (0x00000008u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_MASK (0x00000080u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_SHIFT (0x00000007u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_MASK (0x00000040u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_SHIFT (0x00000006u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_MASK (0x00000020u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_SHIFT (0x00000005u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_MASK (0x00000010u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_SHIFT (0x00000004u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_MASK (0x00000008u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_SHIFT (0x00000003u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_MASK (0x00000004u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_SHIFT (0x00000002u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_MASK (0x00000002u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_SHIFT (0x00000001u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_RESETVAL (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_MASK (0x00000001u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_SHIFT (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_RESETVAL (0x00000000u)
/*----CLRFAL Tokens----*/
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL_DISABLE (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/FB_W2100_SCU_MEA256/version.h
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
#define SW_MAJOR 0
#define SW_MINOR 3
#define SW_STRING "0.03"
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/tcp2/tcp2_standalone_mode/src/tcpExampleData.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004 , 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file tcpExampleData.c
*
* @path $(CSLPATH)\example\c6455\tcp2\tcp2_standalone_mode\src
*
* @desc Example file for the TCP2 CSL
*
*/
#include <tistdtypes.h>
Uint32 sysParData [] = {
0x14029f,
0x4c0530,
0x20037a,
0x180434,
0xc80bc1,
0x200b42,
0xd80fc7,
0xc0cdf,
0xbc0cd6,
0xa407fd,
0x440d2f,
0xf40110,
0x2803be,
0xc0203,
0xd80fc4,
0xc00c65,
0x500e4a,
0x80b41,
0xbc0e88,
0x40c40,
0xd40eb7,
0xc52,
0xdc0231,
0xbc012d,
0x28093c,
0xd4008c,
0x4001b8,
0x540537,
0x400cfc,
0xd40ff6,
0x4407a9,
0x180f49,
0x2005b4,
0xec0b7e,
0x200465,
0x500a18,
0x180f41,
0x6c0d45,
0xc4099a,
0x400e71,
0x000000
};
Uint32 interleaverTbl [] = {
0x190027,
0x90011,
0x230001,
0x15001b,
0x5000b,
0x1a0022,
0xa0014,
0x260004,
0x16001e,
0x6000e,
0x1c0024,
0xc0012,
0x250002,
0x13001d,
0x3000d,
0x180020,
0x80010,
0x210000,
0x17001f,
0x7000f,
0x290028,
0x2b002a
};
Int8 tailData []= {
0x2f, 0x31, 0x30, 0x20,
0x32, 0x27, 0x30, 0x0d,
0x10, 0x3f, 0x18, 0x3b
};
/* hard decisions expected */
Uint32 hdRefBuff [] = {0x082336bc1, 0x0ea};
Uint32 frameLength = 40;
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrClose.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ===========================================================================
* @file csl_tmrClose.c
*
* @brief File for functional layer of CSL API CSL_tmrClose()
*
* @path $(CSLPATH)\src\timer
*
* @desc The CSL_tmrClose() function definition & it's associated
* functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 1-Sept-2004 HMM File Created.
* ============================================================================
*/
#include <csl_tmr.h>
/** ============================================================================
* @n@b CSL_tmrClose.c
*
* @b Description
* @n This function marks that CSL for the Timer instance is closed.
* CSL for the timer instance need to be reopened before using any
* timer CSL API.
*
* @b Arguments
* @verbatim
hTmr Pointer to the object that holds reference to the
instance of TIMER requested after the call
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Timer is closed
* successfully
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n 1. The Timer CSL APIs can not be called until the Timer CSL is
* reopened again using CSL_tmrOpen()
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_tmrClose(hTmr);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_tmrClose, ".text:csl_section:tmr");
CSL_Status CSL_tmrClose (
CSL_TmrHandle hTmr
)
{
CSL_Status st;
if (hTmr != NULL) {
hTmr->regs = (CSL_TmrRegsOvly)NULL;
hTmr->perNum = (CSL_InstNum)-1;
st = CSL_SOK;
}
else {
st = CSL_ESYS_BADHANDLE;
}
return st;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/FB_W2100_SCU_MEA256/Common/MCS_USB_commands.h
|
<filename>DSP/FB_W2100_SCU_MEA256/Common/MCS_USB_commands.h
// keep_internal
// shared between windows and embedded devices
#ifndef _MCS_USB_COMMANDS_H_
#define _MCS_USB_COMMANDS_H_
/*! \cond internal */
/*! \file
* \brief Structures needed for communication with the STG200x
*/
#ifndef __C30
#ifndef __18CXX
#ifndef __TMS320C28XX__
#ifndef __TMS320C55XX__
#ifndef _TMS320C6X
#ifndef __C51__
#pragma pack(1)
#endif
#endif
#endif
#endif
#endif
#endif
#ifndef DOXYGEN_SHOULD_SKIP_THIS
#include "MCS_USB_def.h"
#define MCS_VENDOR_ID 0x1E26
#define CYPRESS_VENDOR_ID 0x04B4
#define ALA_VC3_VENDOR_ID 0x1234
// Product IDs
// Product IDs for Ala Vendor ID
#define ALA_VC3_PRODUCT_ID 0x0002
// Prduct IDs for Cypress Vendor ID
#define CY_FX1_PRODUCT_ID 0x6473
#define CY_FX2_PRODUCT_ID 0x8613
#define CY_FX3_PRODUCT_ID 0x00F3
// Product ID for MC_Card
#define MCS_PRODUCT_ID_MC_CARD 0x80E8
// Product IDs for MCS Vendor ID
// Range 0xA1xx for Campden instrumenst
#define MCS_PRODUCT_ID_CAMPDEN_CI4600EPHYS_VIDEO_DATA_INTEGRATOR 0xA100
// Range 0xB1xx for HEKA
#define MCS_PRODUCT_ID_HEKA_LIH30 0xB101
// Range 0xCxxx for MCS
#define MCS_PRODUCT_ID_STG 0xc104
#define MCS_PRODUCT_ID_MEAUSB 0xc204 // only used with old Vendor ID 0xabcd
#define MCS_PRODUCT_ID_OCTOPOT 0xc205
#define MCS_PRODUCT_ID_TERSENS 0xc206
#define MCS_PRODUCT_ID_DOTRIAPOT 0xc207
#define MCS_PRODUCT_ID_ME256_OLD_UNUSED_DONOTUSE 0xc208 // changed to 0xc504 (MCS_PRODUCT_ID_ME256) to have all MEA products in the 0xc5xx range
#define MCS_PRODUCT_ID_HLA 0xc209
#define MCS_PRODUCT_ID_STG400x 0xc240
#define MCS_PRODUCT_ID_STG4002 0xc241
#define MCS_PRODUCT_ID_STG4004 0xc242
#define MCS_PRODUCT_ID_STG4008 0xc243
#define MCS_PRODUCT_ID_STG400x_OPTO 0xc244
#define MCS_PRODUCT_ID_STG4002_OPTO 0xc245
#define MCS_PRODUCT_ID_STG4004_OPTO 0xc246
#define MCS_PRODUCT_ID_STG4008_OPTO 0xc247
#define MCS_PRODUCT_ID_STG400x_REV_E 0xc248
#define MCS_PRODUCT_ID_STG3008_FA 0xc24b
#define MCS_PRODUCT_ID_STG500x 0xc250
#define MCS_PRODUCT_ID_MULTIWELLOPTOSTIM 0xc260
#define MCS_PRODUCT_ID_STG_RANGE_END 0xc280
#define MCS_PRODUCT_ID_GENERIC 0xc300
#define MCS_PRODUCT_ID_PGA 0xc301
#define MCS_PRODUCT_ID_PCX 0xC321
#define MCS_PRODUCT_ID_TCX 0xC322
#define MCS_PRODUCT_ID_FCX 0xC323
#define MCS_PRODUCT_ID_FCB 0xC324
#define MCS_PRODUCT_ID_TC01 0xC325
#define MCS_PRODUCT_ID_TC02 0xC326
#define MCS_PRODUCT_ID_RETINA_LED 0xC330
#define MCS_PRODUCT_ID_RETINA_AMS_DONGLE 0xC331
#define MCS_PRODUCT_ID_OKUVISION_STIMULATOR 0xC332
#define MCS_PRODUCT_ID_RETINAIMPLANT_EXTERNBCTESTER 0xC333
#define MCS_PRODUCT_ID_RIAG_TRIGGERBOX_IMS 0xC334
#define MCS_PRODUCT_ID_RIAG_TRIGGERBOX_AMS 0xC335
#define MCS_PRODUCT_ID_RIAG_TRIGGERBOX_AMS3 0xC336
#define MCS_PRODUCT_ID_RETINAIMPLANT_EXTERNDTESTER 0xC337
#define MCS_PRODUCT_ID_RIAG_FUNKDONGLES 0xC338
#define MCS_PRODUCT_ID_RIAG_EXTERNSTESTER 0xC339
#define MCS_PRODUCT_ID_RIAG_DONGLES 0xC33A
#define MCS_PRODUCT_ID_RIAG_TRIGGERBOX_R5 0xC33B
#define MCS_PRODUCT_ID_FYI 0xC350
#define MCS_PRODUCT_ID_HEPARAT 0xC351
#define MCS_PRODUCT_ID_MEA_SWITCH 0xC401
#define MCS_PRODUCT_ID_MEA_IMPEDANCE 0xC402
#define MCS_PRODUCT_ID_CHANNELTEST 0xC403
#define MCS_PRODUCT_ID_SW2TO64 0xC404
#define MCS_PRODUCT_ID_PERISTALTIC_PUMP 0xC405
#define MCS_PRODUCT_ID_MEA_SWITCH_2_1 0xC406
#define MCS_PRODUCT_ID_MEA_SWITCH_4_2 0xC407
#define MCS_PRODUCT_ID_PPS4plus1 0xC408
#define MCS_PRODUCT_ID_PPS5 0xC409
#define MCS_PRODUCT_ID_PPS2 0xC40A
#define MCS_PRODUCT_ID_PPS5_DIG 0xC40B
#define MCS_PRODUCT_ID_MEA_CLEAN 0xC410
#define MCS_PRODUCT_ID_MEA_COAT 0xC411
#define MCS_PRODUCT_ID_MULTIWELL_ICC 0xC412
#define MCS_PRODUCT_ID_MBC08 0xC413
#define MCS_PRODUCT_ID_PPC 0xC414
#define MCS_PRODUCT_ID_MEA1060 0xc501
#define MCS_PRODUCT_ID_MEA_SANOFI 0xc502
#define MCS_PRODUCT_ID_ME16_C54xx 0xc503 // TI C54xx based design
#define MCS_PRODUCT_ID_ME256 0xc504
#define MCS_PRODUCT_ID_ME128 0xc505
#define MCS_PRODUCT_ID_ME64 0xc506
#define MCS_PRODUCT_ID_ME32 0xc507
#define MCS_PRODUCT_ID_ME16 0xc508
#define MCS_PRODUCT_ID_MEA2100_MINI_USB_DEVELOP 0xc520
#define MCS_PRODUCT_ID_MEA256 0xc540
#define MCS_PRODUCT_ID_MEA2100 0xc541
#define MCS_PRODUCT_ID_MEA2100_32 0xc542
#define MCS_PRODUCT_ID_MEA21_LITE 0xc543
#define MCS_PRODUCT_ID_MULTIWELL 0xc544
#define MCS_PRODUCT_ID_MEA2100_256 0xc545
#define MCS_PRODUCT_ID_ME2100 0xc546
#define MCS_PRODUCT_ID_MEA2100_BETA_SCREEN 0xc547
#define MCS_PRODUCT_ID_MEA2100_MINI 0xc548
#define MCS_PRODUCT_ID_TBSI_DACQ 0xC549
#define MCS_PRODUCT_ID_MULTIWELL_MEA_MINI 0xC54A
#define MCS_PRODUCT_ID_MULTIBOOT 0xc550
#define MCS_PRODUCT_ID_WPA8 0xc580
#define MCS_PRODUCT_ID_WPA4 0xc581
#define MCS_PRODUCT_ID_WPA16 0xc582
#define MCS_PRODUCT_ID_WPA32 0xc583
#define MCS_PRODUCT_ID_W2100 0xc588
#define MCS_PRODUCT_ID_NEUROCHIP 0xc5a0
#define MCS_PRODUCT_ID_WPA 0xC580
#define MCS_PRODUCT_ID_WPA_MASK 0xFFF8
#define MCS_PRODUCT_ID_USB_TEST 0xC600
#define MCS_PRODUCT_ID_SOFTWAREDONGLE 0xC601
#define MCS_PRODUCT_ID_PATHIDENT 0xC701
#define MCS_PRODUCT_ID_NF_GEN 0xC702
#define MCS_PRODUCT_ID_SAFEIS 0xC703
#define MCS_PRODUCT_ID_ENCAPSULATOR 0xC704
#define MCS_PRODUCT_ID_NEUROCHIP_CONFIG 0xC705
#define MCS_PRODUCT_ID_MEASURETABLE 0xC706
#define MCS_PRODUCT_ID_PEDOTER 0xC707
#define MCS_PRODUCT_ID_ROBOOCYTE2 0xC801
#define MCS_PRODUCT_ID_ROBOINJECT 0xC802
#define MCS_PRODUCT_ID_HICLAMP 0xC803
#define MCS_PRODUCT_ID_PATCHSERVER 0xC804
#define MCS_PRODUCT_ID_DILUTOR 0xC805
#define MCS_PRODUCT_ID_HICLAMP4UART 0xC806
#define MCS_PRODUCT_ID_USSING_TER 0xC807
#define MCS_PRODUCT_ID_IM16S16KRA 0xC901
#define MCS_PRODUCT_ID_IM64KRB 0xC902
#define MCS_PRODUCT_ID_IS32KRA 0xC903
#define MCS_PRODUCT_ID_IM64KRC 0xC904
#define MCS_PRODUCT_ID_IM16S8KRA 0xC905
#define MCS_PRODUCT_ID_IM16KRC 0xC906
#define MCS_PRODUCT_ID_SMARTIMPLANT 0xC907
#define MCS_PRODUCT_ID_POSITION_IMP 0xC908
#define MCS_PRODUCT_ID_POSITION_BASE 0xC909
//Range 0xD1xx for Warner devices
#define MCS_PRODUCT_ID_WARNER_VALVE_CONTROL 0xD101
#define MCS_PRODUCT_ID_WARNER_TEER_MACHINE 0xD111
#define MCS_PRODUCT_ID_WARNER_USSING 0xD121
/* Vendor requests */
#define STG_START 0x18
#define STG_STOP 0x19
/* bitmask of devices to start and stop */
#define STARTSTOP_DEVICE_STG 0x0001
#define STARTSTOP_DEVICE_DACQ 0x0002
#define STARTSTOP_DEVICE_DACQ_D0 0x0002
#define STARTSTOP_DEVICE_DACQ_D1 0x0004
#define STARTSTOP_DEVICE_DACQ_D2 0x0008
#define STARTSTOP_DEVICE_DACQ_D3 0x0010
#define STARTSTOP_DEVICE_DACQ_VMASK 0x001e // 4bit for virtual MEA devices
#define STOP_OPTION_SAVESTOP 0x80 /* Stop only if bypass is not active */
#define SET_DACQ_SAMPLERATE 0x23
#define DACQ_COMMAND 0x25
#define SET_TRIGGERPERIOD 0x00
#define SET_TRIGGERMASKVALUE 0x01
#define DACQ_UART_COMMAND 0x10
#define DACQ_SET_POTI 0x20
#define DACQ_GET_POTI 0x21
#define TER_COMMAND 0x26
#define TER_SET_DAC_VALUE 0x00
#define TER_SET_MODE 0x01
#define TER_SET_CHANNEL 0x02
#define PGA_COMMAND 0x27
#define PGA_SETGAIN 0x01
#define PGA_APPLYGAIN 0x02
#define PGA_DEFINE_NUMFREQRANGE 0x21 /* int32 */
#define PGA_DEFINE_FREQRANGE 0x22 /* int32 index, int32 low, int32 high, int32 gain */
#define PGA_DEFINE_NUMAMPLIFICATIONS 0x23 /* int32 */
#define PGA_DEFINE_AMPLIFICATION 0x24 /* int32 index, int32 amplification, int32 poti1, int32 poti2 */
#define PGA_GET_NUMFREQRANGE 0x81
#define PGA_GET_FREQRANGE 0x82
#define PGA_GET_NUMAMPLIFICATIONS 0x83
#define PGA_GET_AMPLIFICATION 0x84
#define PGA_GET_GAIN 0x85
#define MCS_CONTROL_COMMAND 0x28
#define CX_SET_CHANNELS_C 0x00
#define CX_SET_CHANNELS_M 0x01
#define CX_SET_CONTRAST 0x02
#define CX_SET_SP 0x10 // per channel property
#define CX_SET_DEVICE 0x11
#define CX_SET_ON_OFF 0x12
#define CX_SET_CALI 0x13
#define CX_SET_P 0x18 // per device property
#define CX_SET_I 0x19
#define CX_SET_D 0x1a
#define CX_SET_MAXP 0x1b
#define CX_SET_DEVNAME 0x1c
#define CX_SET_DEVICETYPE 0x1d
#define CX_SET_INTERNAL_ON_OFF 0x1e
#define CX_SET_DEVICE_DEFAULT 0x20 // restore device to mcs default
#define CX_SET_CHANNEL_DEFAULT 0x21 // restore channel to mcs default
#define CX_FACTORY_RESET 0x23
#define CX_SET_HEATER_LIMIT 0x50
#define CX_SET_ENABLE_HEATER_LIMIT 0x51
#define CX_SET_ENABLE_THERMOCOUPLE 0x52
#define CX_SET_SENSOR_TYPE 0x53
#define CX_GET_CHANNELS_C 0x80 // get number of control channels
#define CX_GET_CHANNELS_M 0x81 // get number of measure only channels
#define CX_GET_CONTRAST 0x82 // display contrast
#define CX_GET_VAL 0x83
#define CX_GET_UNIT 0x84
#define CX_GET_BOARD_TEMP 0x85
#define CX_GET_VOLTI 0x86
#define CX_GET_NUM_DEVICES 0x87
#define CX_GET_VAL_HIRES 0x88 // get value in higher resolution
#define CX_GET_VAL_HEATER 0x89 // get temp of the heater element
#define CX_GET_HAS_THERMO 0x8a // query if the device includes a thermocouple
#define CX_GET_SP 0x90 // per channel property
#define CX_GET_DEVICE 0x91
#define CX_GET_ON_OFF 0x92
#define CX_GET_CALI 0x93
#define CX_GET_P 0x98 // per device property
#define CX_GET_I 0x99
#define CX_GET_D 0x9a
#define CX_GET_MAXP 0x9b
#define CX_GET_DEVNAME 0x9c
#define CX_GET_DEVICETYPE 0x9d
#define CX_GET_INTERNAL_ON_OFF 0x9e
#define CX_GET_SP_MIN 0xa0
#define CX_GET_CALI_MIN 0xa3
#define CX_GET_P_MIN 0xa8
#define CX_GET_I_MIN 0xa9
#define CX_GET_D_MIN 0xaa
#define CX_GET_MAXP_MIN 0xab
#define CX_GET_HEATER_LIMIT_MIN 0xac
#define CX_GET_SP_MAX 0xb0
#define CX_GET_CALI_MAX 0xb3
#define CX_GET_P_MAX 0xb8
#define CX_GET_I_MAX 0xb9
#define CX_GET_D_MAX 0xba
#define CX_GET_MAXP_MAX 0xbb
#define CX_GET_HEATER_LIMIT_MAX 0xbc
#define CX_GET_SP_DECP 0xc0
#define CX_GET_CALI_DECP 0xc3
#define CX_GET_P_DECP 0xc8
#define CX_GET_I_DECP 0xc9
#define CX_GET_D_DECP 0xca
#define CX_GET_MAXP_DECP 0xcb
#define CX_GET_HEATER_LIMIT_DECP 0xcc
#define CX_GET_HEATER_LIMIT 0xd0
#define CX_GET_ENABLE_HEATER_LIMIT 0xd1
#define CX_GET_ENABLE_THERMOCOUPLE 0xd2
#define CX_GET_SENSOR_TYPE 0xd3
#define CX_GET_RES_X 0xf0
#define CX_GET_RES_S 0xf1
#define CX_GET_RES_1 0xf2
#define CX_GET_RES_2 0xf3
#define CX_GET_PWR_SET 0xf4
#define CX_GET_PWR_OUT 0xf5
#define CX_GET_DUTY 0xf6
#define CX_GET_U_OUT 0xf7
#define CX_GET_I_OUT 0xf8
#define CX_GET_R_OUT 0xf9
#define CX_GET_P_OUT 0xfa
#define CX_GET_CURR 0xfb
#define PIDCONTROL_MAX_DEVNAME 24
#define STG200x_COMMAND 0x29 // interface change: we collect all STG only commands under this Request Id, compability with Firmware < 2.30 STG200x devices has been dropped in McsUsbDLL 3.3.17 (20.5.2019)
#define STG200x_SETUP_TRIGGER 0x11
#define STG200x_CHANNEL_RESET 0x12
#define STG200x_CHANNEL_DATA 0x13 // to extra endpoint
#define STG200x_SYNC_RESET 0x14
#define STG200x_SYNC_DATA 0x15 // to extra endpoint
#define STG200x_SET_CAPACITY 0x16
#define STG200x_GET_AVAILABLE_MEM 0x17 // return the memory avaiable in the current segment (former name: STG200x_GET_MEM)
#define STG200x_SET_STGOUTPUT 0x18
#define STG200x_STG_RESET_STATUS 0x20
#define STG200x_CLEAR_MULTIPLEXED_DATA 0x21 // currently only on HEKA IH3.0
#define STG200x_SET_OUTPUTRATE 0x23
#define STG200x_DISABLE_TRIGGER 0x25
#define STG200x_ENABLE_TRIGGER 0x26
#define STG200x_DISABLE_AUTORESET 0x27
#define STG200x_ENABLE_AUTORESET 0x28
#define STG200x_GET_UVAL 0x30
#define STG200x_GET_IVAL 0x31
#define STG200x_GET_DAC_RESOLUTION 0x32 // query the number of bits the DAC has, if not implemented assume a value of 13
#define STG200x_GET_T_RESOLUTION 0x33
#define STG200x_GET_BOOSTPRETIME 0x34 // return the time the W2100 boost needs to power up
#define STG200x_SET_URANGE 0x38
#define STG200x_SET_URESOLUTION 0x39
#define STG200x_SET_IRANGE 0x3a
#define STG200x_SET_IRESOLUTION 0x3b
#define STG200x_STORE_RESRANGE 0x3c // store range and resolution data in eeprom
#define STG200x_GET_PROGRAM_INFO 0x41
#define STG200x_SET_PROGRAM_INFO 0x42
#define STG200x_GET_SWEEP_COUNT 0x44
#define STG200x_GET_TRIGGERMAP 0x45
#define STG200x_GET_OUTPUTRATE 0x46
#define STG200x_GET_CAPACITY 0x47
#define STG200x_GET_NUMBER_ANALOGOUT 0x48
#define STG200x_GET_NUMBER_SYNCOUT 0x49
#define STG200x_GET_NUMBER_TRIGGER 0x4a
#define STG200x_HAS_PREAMPLIFIER 0x4b
#define STG200x_GET_NUMBER_HWDACPATH 0x4c
#define STG200x_GET_STIMSOURCES_PER_ELECTRODE 0x4d
#define STG200x_STIMULATION_LAYOUT_CONFIGURATION 0x4e
#define STG200x_GET_MULTIPLEXED_CHANNELS_IN_BLOCK 0x4f // currently only on HEKA IH3.0
#define STG200x_GET_MEMORY_USAGE_DAC 0x50
#define STG200x_GET_MEMORY_USAGE_SYNC 0x51
#define STG200x_COMMAND_DOWNLOADMODE 0x61
#define STG200x_COMMAND_STREAMINGMODE 0x62
#define STG200x_COMMAND_CONT_MODE_OFF 0x63
#define STG200x_COMMAND_CONT_MODE_ON 0x64
#define STG200x_MULTIFILE_MODE_OFF 0x65
#define STG200x_MULTIFILE_MODE_ON 0x66
#define STG200x_SET_VOLTAGE_MODE 0x67 // not needed and not implemented on old STG200x series
#define STG200x_SET_CURRENT_MODE 0x68 // not needed and not implemented on old STG200x series
#define STG200x_SET_MEASUREMENT_MODE 0x69 // only for STG3008-FA (with Filter Amplifier)
#define STG200x_SEGMENT_DEFINE 0x80
#define STG200x_SEGMENT_SELECT 0x81
#define STG200x_SEGMENT_START 0x83 // SEGMENT_SELECT && STG_START
#define STG200x_GET_TOTALMEM 0x84 // get total memory of the STG
#define STG200x_GET_MAX_NUM_SEGMENTS 0x85
#define STG200x_SETUP_RETRIGGER_MODE 0x86 // reaction on trigger while running
#define STG200x_GET_STIMMEM_DESTADDR 0x87
#define STG200x_GET_STIMMEM_CLEARADDR 0x88
#define STG200x_DIGOUT_MODE 0x89 // configure the function of the digout port
#define STG200x_DIGOUT_VALUE 0x8a // the pattern on the digout port
#define STG200x_DIGIN_VALUE 0x8b // the pattern on the digin port
#define STG200x_SYNCOUT_MAP 0x8c // map betwenn internal and external syncout, allows mapping of more than one internal syncout to the external pin
#define STG200x_DEBUG_CHANNELDATA 0x90
#define STG200x_GET_EEPROM_ID 0x91
// these commands are new in the TI-DSP Stg implementation
#define STG200x_QUERY_TRIGGERSTATUS 0xa0
#define STG200x_SET_OUTPUTMAP 0xa1
// commands for the STG30008-FA
#define STG200x_FA_AMPLIFICATION 0xa2 // for STG3008-FA
#define STG200x_AUTOCALIB_DISABLE 0xa3 // for STG3008-FA and STG400x with new Analog Firmware (Release 2011)
// commands for the MEA21 sideband to electrode mapping
#define STG200x_ELECTRODE_SIDEBAND 0xa4
#define STG200x_BLANKING_ENABLE 0xa5
#define STG200x_TRIGGER_SOURCE 0xa6
#define STG200x_ENABLE_PROTECTION_SWITCH 0xa7 // was: STG200x_STIMULATION_ENABLE
#define STG200x_GET_NUM_STIMULATION_ELECTRODES 0xa8
#define STG200x_ELECTRODE_SIDEBAND_EX 0xa9
#define STG200x_BLANKING_ENABLE_EX 0xaa
#define STG200x_ENABLE_PROTECTION_SWITCH_EX 0xab
#define STG200x_GET_MODULETEMP 0xb0
#define STG200x_GET_MODULECURRENT 0xb1
#define STG200x_CAN_DISABLE_CALIBRATION 0xc0
#define STG200x_HAS_LOW_CURRENTSWITCH_LATENCY 0xc1
#define STG200x_CAN_DISABLE_CURRENTSWITCH 0xc2
#define STG200x_GET_MODULE_TYPE 0xc3
// select headstage to which the STG commands are sent
#define STG200x_MEA21_SELECT_HS 0xd0
// commands for the MEA2100 Listmode
#define STG200x_MEA21_LISTMODE_INDEXRANGE 0xe0
#define STG200x_MEA21_LISTMODE_TRIGGERSOURCE 0xe1
#define STG200x_MEA21_LISTMODE_START 0xe2
#define STG200x_MEA21_LISTMODE_STOP 0xe3
#define STG200x_MULTIWELL_DAC_AMPLIFICATION 0xf0
#define STG200x_MULTIWELL_OPTOSTIM_WAVELENGTH 0xF1
#define STG200x_MULTIWELL_OPTOSTIM_MAX_CURRENT 0xF2
#define STG200x_MULTIWELL_OPTOSTIM_MAX_DURATION 0xF3
#define STG200x_MULTIWELL_OPTOSTIM_MAX_CURRENT_DUTY_CYCLE 0xF4
#define STG200x_MULTIWELL_OPTOSTIM_PERMANENT_CURRENT 0xF5
#define STG200x_MULTIWELL_OPTOSTIM_COLOR_RGB 0xF6
#define STG200x_MULTIWELL_OPTOSTIM_COLOR_STR 0xF7
// commands for the MEA21 output mapping
#define STG200x_ELECTRODE_DAC_MUX 0x200 // use bit 0..7 of wValue for slice (listmode index)
#define STG200x_ELECTRODE_ENABLE 0x300 // use bit 0..7 of wValue for slice (listmode index)
#define STG200x_CMOS_DAC_SELECT 0x400
#define STG200x_REPEAT_PATTERN 0x500 // set/get how many times the stimulation pattern shall be repeated; introduced for wireless headstage
// commands for the DIGOUT stimulator of the IFB device
#define STG200x_DIGOUT_CLEARDATA 0x600
#define STG200x_DIGOUT_APPENDDATA 0x601
#define STG200x_DIGOUT_NUMBER_OF_CHANNELS 0x602
// 0x603 unused
#define STG200x_DIGOUT_GLOBAL_REPEAT 0x604
#define STG200x_DIGOUT_START_TRIGGER_SLOPE 0x605
#define STG200x_DIGOUT_STOP_TRIGGER_SLOPE 0x606
#define STG200x_EXTERNALELECTRODE_ENABLE 0x700 // use bit 0..7 of wValue for slice (listmode index)
#define STG200x_ELECTRODE_DAC_MUX_EX 0xA00 // use bit 0..7 of wValue for slice (listmode index)
#define STG200x_ELECTRODE_ENABLE_EX 0xE00 // use bit 0..7 of wValue for slice (listmode index)
#define STIMULATOR_COMMAND 0x2a // new (2018) generic stimulator commands, extend STG200x_COMMAND
#define STIMULATOR_DAC_OFFSET 0x10
#define STIMULATOR_BURN_DAC_OFFSET 0x11
/* end of STG200x commands */
#define MEA21_COMMAND 0x2d // Use only bit 0...7 for Command, other bits are for Virtual Device
#define MEA_GROUP_IDCOUNT 0x01 // Number of Groups supported by this device
#define MEA_GROUP_SUPPORTEDID 0x02 // GroupID by count supported by this device
#define MEA_GROUP_NUMBEROFCHANNELS 0x03 // Number of Channels for a requested Group supported by this device
#define MEA_GROUP_TYPE 0x04 // Analog = 1, Digital = 2, Frame Context = 3
#define MEA_GROUP_ENABLECHANNELS 0x05 // Set/Get a Group(s) Channel Bitwise
#define MEA_GROUP_SAMPLESIZE 0x07 // bit width, (un-)signed Enumerations: SampleSize
#define CMOSMEA_GROUP_DIGITRESOLUTION 0x0A // Get Resolution per Digit of Analog Value
#define CMOSMEA_GROUP_VALUEUNIT 0x0B // Physical Unit of Analog Value
#define CMOSMEA_GROUP_DCOFFSET 0x0D // Get DC Offset of Analog Value
#define CMOSMEA_GROUP_HWPROP_ADCBITWIDTH 0x0E // Get the HW Bit width of data source
#define CMOSMEA_GROUP_CHANNEL_BITMASK_SELECT 0x0C // legacy call, do not use in future!!
#define MEA_COMMAND 0x2e
#define MEA_ENABLE_DIGITALIN 0x01
#define MEA_SET_DIGITALOUT 0x02
#define MEA_SET_NUMBEROFCHANNELS 0x03
#define MEA_ENABLE_TIMESTAMP 0x04
#define MEA_ENABLE_CHECKSUM 0x05
#define MEA_SET_AUDIO 0x06
#define MEA_RESET_CHANNELMAP 0x07
#define MEA_SET_CHANNELMAP 0x08
#define MEA_GET_AUDIO 0x09
#define MEA_SET_SELECTED_CHANNELS 0x0A
#define MEA_SET_RF_LOST_BEHAVIOUR 0x0B
#define MEA_SET_HEADSTAGE_ON_OFF 0x0C
#define MEA_SET_IVOLTAGERANGE 0x0D // index of new voltagerange
#define MEA_RFFREQUENCY_HEADSTAGE 0x0E
#define MEA_RFFREQUENCY_RECEIVER 0x0F
#define MEA_SERIALNUMBER_HEADSTAGE 0x10
#define MEA_SELECT_HEADSTAGE 0x11
#define MEA_SCAN_FOR_HEADSTAGES 0x12
#define MEA_GET_SCAN_HEADSTAGES_RESULT 0x13
#define MEA_FILTER_PARAMETERS_SHORT 0x14
#define MEA_HAS_CHECKSUM 0x15
#define MEA_RESET_FILTER 0x16
#define MEA_SET_DATAMODE 0x17
#define MEA_MEA21_DIGOUT_SOURCE 0x18
#define MEA_MEA21_DIGSTREAM_SOURCE 0x19
#define MEA_MEA21_ADAPTER_TYPE 0x1A
#define MEA_MEA21_MEA_LAYOUT 0x1B
#define MEA_WPA_TYPE 0x1C
#define MEA_WPA_DEBUG_MODE 0x1D
#define MEA_WPA_SET_RF_POWER 0x1E
#define MEA_MEA21_DACQTRIGGER_SOURCE 0x1F
#define MEA_DC_FILTER_ENABLE 0x20
#define MEA_HS_FILTER_ENABLE 0x21
#define MEA_CMOS_SOURCE_DRAIN_PARAM 0x22
#define MEA_CMOS_SOURCE_GATE_PARAM 0x23
#define MEA_CMOS_SOURCE_BULK_PARAM 0x24
#define MEA_CMOS_BATH_PARAM 0x25
#define MEA_CMOS_GATE_PARAM 0x26
#define MEA_CMOS_GNDI_PARAM 0x27
#define MEA_CMOS_VDDI_PARAM 0x28
#define MEA_CMOS_VDD3I_PARAM 0x29
#define MEA_CMOS_UPDATE_TRANSISTOR_PARAM 0x2F
#define MEA_CMOS_ADC_INPUT_OFFSET 0x30
#define MEA_CMOS_COLUMN_BITMASK 0x31
#define MEA_CMOS_ROW_BITMASK 0x32
#define MEA_CMOS_POWER_CHIP_PARAM 0x33
#define MEA_CMOS_CHIPTYPE_PARAM 0x34
#define MEA_CMOS_VOPS_PARAM 0x35
#define MEA_CMOS_BATH_CTRL 0x36
#define MEA_DC_FILTER_SETUP 0x37
#define MEA_HS_FILTER_SETUP 0x38
#define MEA_CMOS_NEUROCHIP_MEMACCESS 0x39
#define MEA_CMOS_NEUROCHIP_MEMSIZE 0x3A
#define MEA_SET_DIGITALDATA 0x3B
#define MEA_CMOS_MAX_COLUMNS 0x3C
#define MEA_CMOS_PCSC_CTRL 0x3D
#define MEA_DC_FILTER_RESET 0x3E
#define MEA_CMOS_VOPS_RESETTIMER 0x3F
#define MEA_SET_BANDWIDTH_BY_INDEX 0x40
#define MEA_SET_DSP_HIPASS_BY_INDEX 0x41
#define MEA_AMPLIFIER_SETTLE 0x42
#define MEA_SET_INTAN_REGISTER 0x43
#define MEA_SET_DIAGNOSTIC_MODE 0x44
#define MEA_BEGIN_IMPEDANCE_CHECK 0x45
#define MEA_W2100_GET_AVAILABLE_HS 0x50
#define MEA_W2100_SELECT_HS 0x51
#define MEA_W2100_GET_SELECTED_HS_STATE 0x52
#define MEA_W2100_HS_SERIALNUMBER 0x53
#define MEA_W2100_HS_TYPE 0x54
#define MEA_W2100_BATTERY_STATE 0x55
#define MEA_W2100_POWER_MODE 0x56
#define MEA_W2100_USER_DEFINED_NAME 0x57
#define MEA_W2100_USER_DEFINED_NAME_FROM_SELECTED_HS 0x58
#define MEA_W2100_MULTI_HEADSTAGE_MODE 0x59
#define MEA_W2100_SAMPLING_ACTIVE 0x5A
#define MEA_W2100_HS_SET_TO_SLEEP 0x5B
#define MEA_W2100_GET_STIMULUS_PARAMETER 0x5C
#define MEA_W2100_SET_ANALOG_OUT_CHANNEL 0x5D
#define MEA_W2100_SET_ANALOG_OUT_FILTER 0x5E
#define MEA_W2100_DAC_RANGE 0x5F
#define MEA_MW_PLATE_STATE 0x60
#define MEA_MW_PLATE_LOCK 0x61
#define MEA_MW_PLATE_TYPE 0x62
#define MEA_MW_INDEX_PLATE_CLAMP_CLOSE 0x00
#define MEA_MW_INDEX_PLATE_CLAMP_OPEN 0x01
#define MEA_MW_INDEX_PLATE_CLAMP_STOP 0x02
#define MEA_MW_INDEX_PLATE_CLAMP_LOCK 0x00
#define MEA_MW_INDEX_PLATE_CLAMP_UNLOCK 0x01
#define MEA_GET_FILTER_CONFIGURATION 0x63
#define MEA_MW_PLATE_MUX 0x64
#define MEA_MW_PLATE_TYPE_IS_VALID 0x65
#define MEA_SET_FILTER_CONFIGURATION 0x66
#define MEA_STORE_FILTER_CONFIGINMEM 0x67
#define MEA_ERASE_FILTER_CONFIGINMEM 0x68
#define MEA_W2100_GENERATOR_PERIOD 0x70
#define MEA_W2100_GENERATOR_PULSE_LENGTH 0x71
#define MEA_W2100_GENERATOR_MODE_SELECT 0x72
#define MEA_W2100_ENABLE_ACCEL_GYRO 0x78
#define MEA_W2100_ACCEL_GYRO_DESIREDGRATE 0x79
#define MEA_W2100_ACCEL_GYRO_CURRENTRATE 0x7A
#define MEA_W2100_ACCEL_RANGE 0x7B
#define MEA_W2100_GYRO_RANGE 0x7C
#define MEA_DIGOUT_STG_START_TRIGGER_SOURCE 0x80
#define MEA_DIGOUT_STG_STOP_TRIGGER_SOURCE 0x81
#define MEA_DIGSTREAMTORECEIVER_SOURCE 0x84
#define MEA_W2100_DIGTRIGGER_SLOPE 0x85
#define MEA_SCU_AVAILABLE_HEADSTAGES 0x90
#define MEA_SCU_MAX_CHANNELS_PER_HEADSTAGE 0x91
#define MEA_SCU_MAX_NUMBER_OF_HEADSTAGES 0x92
#define MEA_SCU_GET_HEADSTAGE_ID 0x93
#define MEA_SCU_MAX_STIMULUS_CHANNELS_PER_HEADSTAGE 0x94
#define MEA_SCU_DACQ_LEGACY_MODE 0x95
#define MEA_SCU_HEADSTAGE_POWER 0x96
#define MEA_SCU_HEADSTAGE_HAS_POWERSWITCHES 0x97
#define MEA_SCU_HEADSTAGE_IS_AVAILABLE 0x98
#define MEA_SCU_HEADSTAGE_SERIALNUMBER 0x99
#define MEA_SCU_HEADSTAGE_ANALOG_CHANNELS 0x9A
#define MEA_SCU_HEADSTAGE_STIMULUS_CHANNELS 0x9B
#define MEA_SCU_HEADSTAGE_REFERENCE_ELECTRODE_SWITCHSTATE 0x9C
#define MEA_SCU_HEADSTAGE_REFERENCE_ELECTRODE_MODE 0x9D
#define MEA_SCU_HEADSTAGE_GAIN 0xA0
#define MEA_SCU_HEADSTAGE_ADC_RANGE 0xA1
#define MEA_SCU_HEADSTAGE_ADC_BITS 0xA2
#define MEA_SCU_HEADSTAGE_DAC_VOLTAGE_RANGE 0xA3
#define MEA_SCU_HEADSTAGE_DAC_VOLTAGE_RESOLUTION 0xA4
#define MEA_SCU_HEADSTAGE_DAC_CURRENT_RANGE 0xA5
#define MEA_SCU_HEADSTAGE_DAC_CURRENT_RESOLUTION 0xA6
#define MEA_SCU_HEADSTAGE_DAC_BITS 0xA7
#define MEA_SCU_ANALOG_OUT_ENABLE 0xB0
#define MEA_SCU_ANALOG_OUT_DAC_RANGE 0xB1
#define MEA_SCU_ANALOG_OUT_ADC_RANGE 0xB2
#define MEA_SCU_ANALOG_OUT_AUTOMATIC 0xB3
#define MEA_SCU_ANALOG_OUT_CHANNELS 0xB4
#define MEA_SCU_HAS_ANALOG_OUT 0xB5
#define MEA_SCU_HAS_GALVANIC_ISOLATION 0xC0
#define OCTOPOT_COMMAND 0x2f
// subids for OCTOPOT_COMMAND
#define OCTOPOT_SET_BATHCLAMP 0x01
#define OCTOPOT_SET_DAC_VALUE 0x02
#define OCTOPOT_SET_DAC_AUTOCONTROL 0x03
#define OCTOPOT_SET_PID_PARAMETER 0x04
#define OCTOPOT_SET_RAMP_PARAMETER 0x05
#define OCTOPOT_RAMP_START 0x06
#define OCTOPOT_SET_DAC_OFFSET 0x07
#define OCTOPOT_SET_ADC_OFFSET 0x08
#define OCTOPOT_BURN_DAC_OFFSET 0x09
#define OCTOPOT_BURN_ADC_OFFSET 0x10
#define OCTOPOT_RESET_DAC_OFFSET 0x11
#define OCTOPOT_RESET_ADC_OFFSET 0x12
#define OCTOPOT_SET_SINE_PARAMETER 0x13
#define OCTOPOT_SINE_START 0x14
#define OCTOPOT_SET_PATTERN_LIST_ENTRY 0x15
#define OCTOPOT_PATTERN_LIST_START 0x16
#define OCTOPOT_SET_ADC_GPIO0 0x1f
#define OCTOPOT_SET_ADC_GPIO1 0x20
// end of subids
#define RETINA_LED 0x30
#define RETINA_SET_TRIGGER 0x01 /* enable/disable trigger */
#define RETINA_SET_LED 0x03 /* set pattern on LED Array */
#define RETINA_SET_TABLEPOINTER 0x04 /* set table pointer to entry */
#define RETINA_CLEAR_TABLE 0x05 /* delete table */
#define RETINA_ADD_TABLE_ENTRY 0x06 /* add table enry, 8 byte data, 2 byte repeat */
#define RETINA_SET_REPEAT 0x07 /* global repeat of table, 2 byte */
#define RETINA_SET_LUMI 0x08 /* luminosity, 2 byte */
#define RETINA_SET_PERSISTENCY 0x09 /* Nachleuchtzeit in ms */
#define RETINA_ADD_LOOP_ENTRY 0x10 /* add a loop entry to the table */
#define RETINA_GET_TABLEPOINTER 0x84 /* retrieve current position of the table pointer */
/* + callback for current table position */
#define MCS_FLUID_COMMAND 0x31
#define FLUID_SET_VALVE 0x01 /* Set Valve */
#define FLUID_SET_DIGOUT 0x02
#define FLUID_SET_PWM 0x03 /* Set PWM in 1/1000 steps */
#define FLUID_SET_SINGLE_VALVE 0x04 /* Sets a single Valve */
#define FLUID_CALIBRATE_TERMO 0x21 /* Calibrate Temperature */
#define FLUID_SET_NANOVOLTPERKELVIN 0x22
#define FLUID_GET_VALVE 0x81
#define FLUID_GET_DIGOUT 0x82
#define FLUID_GET_PWM 0x83
#define FLUID_GET_SINGLE_VALVE 0x84 /* Gets a single Valve */
#define FLUID_GET_ADC 0x90
#define FLUID_GET_DIGIN 0x91
#define FLUID_GET_REF_TEMP 0x92 /* Temp at reference point */
#define FLUID_GET_THERMO_TEMP 0x93 /* Differential Temp of ThermoCouple */
#define FLUID_GET_CHANNEL_TEMP 0x94 /* Absolute Temp */
#define FLUID_GET_THERMO_CALIB 0xa1
#define FLUID_GET_NANOVOLTPERKELVIN 0xa2
#define HEKA_LIH3_COMMAND 0x32
#define LIH3_DUMMY_COMMAND 0x01
#define LIH3_GET_EEPROM_BYTE 0x02
#define LIH3_SAMPLE_INTERVAL 0x03
#define LIH3_EEPROM_START_COMADDR 0x04
#define LIH3_EEPROM_PAGE 0x05
#define LIH3_ADC_OFFSET 0x06
#define LIH3_CLIPPING 0x07
#define LIH3_DIGITAL_IO 0x08
#define LIH3_SEND_COMMAND 0x09
#define LIH3_DACQ_RUN_STATUS 0x0A
#define LIH3_MIN_SAMPLEINTERVAL 0x0B
#define LIH3_SAMPLEINTERVAL_STEPSIZE 0x0C
#define LIH3_DAC_USE_IDLE_VALUE 0x0D
#define LIH3_DAC_IDLE_VALUE 0x0E
/* starting with our our Vendor ID (0x1e..)
The "GET_VERSION (0x43)" call changed its parameters
and is renamed to "GET_FIRMWARE_VERSION".
Now, depending on req_index, the destination is choosen,
and the return value is a single 32bit integer
The Hardware Revision is queried now with the new
"GET_HW_REVISION" call, which returns a string
*/
#define GET_IDENT 0x40
#define GET_DESTINATION_INFO 0x41 // supported for all devices with our new Vendor ID
#define GET_NUM_DESTINATIONS 0x00
#define GET_DESTINATION_CODE 0x01
#define GET_DESTINATION_NAME_BY_IDX 0x02
#define GET_DESTINATION_NAME_BY_CODE 0x03
#define GET_DESTINATION_TARGETADDRESS 0x04
#define DESTINATION_SERIALNUMBER 0x08
#define MULTIBOOT_GET_IMAGE_ID 0x11
#define MULTIBOOT_GET_SELECTED_IMAGE 0x12
#define MULTIBOOT_SELECT_IMAGE 0x13
#define MULTIBOOT_GET_CYPRESS_IMAGE_ID 0x14
#define GET_HEADSTAGE_ID 0x21
#define GET_HEADSTAGE_PRESENT 0x22
#define GET_HEADSTAGE_ACTIVE 0x23
#define RESCAN_HEADSTAGE 0x24
#define GET_FIRMWARE_VERSION 0x43 // has MCSUSB_DEST_... as wValue
#define GET_HW_REVISION 0x44 // new for all devices with our real Vendor ID
#define GET_DACQ_SAMPLERATE 0x46
#define SOFTWARE_KEY_COMMAND 0x47
#define GET_SOFTWARE_KEY 0x01
#define SET_SOFTWARE_KEY 0x02
#define MISC_USB_COMMAND1 0x4a // Device specific commands (1) ==> to save request numbers
// Devices use the upper 8 bits of wValue / commands use the 8 lower bits
#define MEA_SWITCH_MISC_COMMAND 0x0100
#define MEA_SWITCH_GET_NUMBER (MEA_SWITCH_MISC_COMMAND | 0x01) /* gets the number of meas to switch to: 1 or 2 */
#define MEA_SWITCH_SET_NUMBER (MEA_SWITCH_MISC_COMMAND | 0x02) /* sets the number of meas to switch to: 1 or 2 */
#define MEA_SWITCH_GET_PATTERN (MEA_SWITCH_MISC_COMMAND | 0x03) /* gets the current pattern */
#define MEA_SWITCH_SET_PATTERN (MEA_SWITCH_MISC_COMMAND | 0x04) /* sets the current pattern */
// commands for the MCS ChannelTest
#define MEA_CHANNELTEST_SET_WAVEFORM (MEA_SWITCH_MISC_COMMAND | 0x30) /* sets the waveform for Amplifier test (sine/square) */
#define MEA_CHANNELTEST_SET_FREQUENCY (MEA_SWITCH_MISC_COMMAND | 0x31) /* sets the frequency for Amplifier test */
#define MEA_CHANNELTEST_SET_AMPLITUDE (MEA_SWITCH_MISC_COMMAND | 0x32) /* sets the amplitude for Amplifier test */
#define MEA_CHANNELTEST_SET_ATTENUATION (MEA_SWITCH_MISC_COMMAND | 0x33) /* sets the attenutation */
#define MEA_IMPEDANCE_MISC_COMMAND 0x0200
#define MEA_IMPEDANCE_RANGE (MEA_IMPEDANCE_MISC_COMMAND | 0x06)
#define MEA_IMPEDANCE_FREQUENCY (MEA_IMPEDANCE_MISC_COMMAND | 0x07) /* impedance sampling test frequency; unit: Hz */
#define MEA_IMPEDANCE_START_MEASUREMENT (MEA_IMPEDANCE_MISC_COMMAND | 0x08) /* starts the measurement on the given channels */
#define MEA_IMPEDANCE_GET_READY (MEA_IMPEDANCE_MISC_COMMAND | 0x09) /* checks if the the measurement is ready */
#define MEA_IMPEDANCE_GET_ARRAYSIZE (MEA_IMPEDANCE_MISC_COMMAND | 0x0A) /* get the current array size */
#define MEA_IMPEDANCE_GET_RESULT (MEA_IMPEDANCE_MISC_COMMAND | 0x0B) /* gets the result of one period */
#define MEA_IMPEDANCE_GET_ADAPTERCODE (MEA_IMPEDANCE_MISC_COMMAND | 0x0C) /* gets the code of the adapter */
#define SW2TO64_MISC_COMMAND 0x0300
#define SW2TO64_GET_NUMBER (SW2TO64_MISC_COMMAND | 0x01) /* gets the number of channels of the device */
#define SW2TO64_SET_NUMBER (SW2TO64_MISC_COMMAND | 0x02) /* Not used */
#define SW2TO64_GET_CHANNELS (SW2TO64_MISC_COMMAND | 0x03) /* gets the current channel settings */
#define SW2TO64_SET_CHANNELS (SW2TO64_MISC_COMMAND | 0x04) /* sets the current channel settings */
#define SW2TO64_GET_CHANNEL (SW2TO64_MISC_COMMAND | 0x05) /* gets the current setting of one channel */
#define SW2TO64_SET_CHANNEL (SW2TO64_MISC_COMMAND | 0x06) /* sets the current setting of one channel */
#define SERIAL_PORT_MISC_COMMAND 0x0400
#define SERIAL_PORT_SEND (SERIAL_PORT_MISC_COMMAND | 0x01) /* send a line that is equivalent to a COM line */
#define SERIAL_PORT_RECEIVE (SERIAL_PORT_MISC_COMMAND | 0x02) /* gets an answer from the last command send */
#define SERIAL_PORT_BYTES_AVAILABLE (SERIAL_PORT_MISC_COMMAND | 0x03) /* gets the number of bytes available in the receive buffer */
#define PATHIDENT_MISC_COMMAND 0x0500
#define PATHIDENT_SET_VALUES (PATHIDENT_MISC_COMMAND | 0x01)
#define PATHIDENT_MEASURE (PATHIDENT_MISC_COMMAND | 0x02)
#define OKUVISION_STIMULATOR_MISC_COMMAND 0x0600
#define OKUVISION_STIMULATOR_PULSEFORM (OKUVISION_STIMULATOR_MISC_COMMAND | 0x01)
#define OKUVISION_STIMULATOR_MAX_POWER (OKUVISION_STIMULATOR_MISC_COMMAND | 0x03)
#define OKUVISION_STIMULATOR_MAX_VOLTAGE (OKUVISION_STIMULATOR_MISC_COMMAND | 0x04)
#define OKUVISION_STIMULATOR_CHECK_VOLTAGE (OKUVISION_STIMULATOR_MISC_COMMAND | 0x06)
#define OKUVISION_STIMULATOR_GETVOLTAGE (OKUVISION_STIMULATOR_MISC_COMMAND | 0x07)
#define OKUVISION_STIMULATOR_DACOFFSET (OKUVISION_STIMULATOR_MISC_COMMAND | 0x08)
#define OKUVISION_STIMULATOR_RTC (OKUVISION_STIMULATOR_MISC_COMMAND | 0x09)
#define OKUVISION_STIMULATOR_STATUS (OKUVISION_STIMULATOR_MISC_COMMAND | 0x10)
#define OKUVISION_STIMULATOR_CURRENTFACTOR (OKUVISION_STIMULATOR_MISC_COMMAND | 0x11)
#define NF_GEN_MISC_COMMAND 0x0700
#define NF_GEN_SET_VALUES (NF_GEN_MISC_COMMAND | 0x01)
#define SAFEIS_MISC_COMMAND 0x0800
#define SAFEIS_SET_SWITCHES (SAFEIS_MISC_COMMAND | 0x01)
#define SAFEIS_SET_ADC_CHANNELS (SAFEIS_MISC_COMMAND | 0x02)
#define SAFEIS_SET_ADC_SAMPLEPOS (SAFEIS_MISC_COMMAND | 0x03)
#define SAFEIS_SET_DAC_MODE (SAFEIS_MISC_COMMAND | 0x04)
#define SAFEIS_SET_DAC_PULSEFORM (SAFEIS_MISC_COMMAND | 0x05)
#define SAFEIS_SET_DAC_PERIODE (SAFEIS_MISC_COMMAND | 0x06)
#define GILSON_BRIDGE_MISC_COMMAND 0x0900
#define GILSON_BRIDGE_CONNECT_SLAVE (GILSON_BRIDGE_MISC_COMMAND | 0x01)
#define GILSON_BRIDGE_SEND_IMMEDIATE (GILSON_BRIDGE_MISC_COMMAND | 0x02)
#define GILSON_BRIDGE_SEND_BUFFERED (GILSON_BRIDGE_MISC_COMMAND | 0x03)
#define GILSON_BRIDGE_GET_LAST_ANSWER (GILSON_BRIDGE_MISC_COMMAND | 0x04)
#define EXTERN_BC_TESTER_MISC_COMMAND 0x0A00
#define EXTERN_BC_TESTER_SET_CALIB (EXTERN_BC_TESTER_MISC_COMMAND | 0x01)
#define SOFTWAREDONGLE_MISC_COMMAND 0x0B00
#define SOFTWAREDONGLE_CODE (SOFTWAREDONGLE_MISC_COMMAND | 0x01)
#define PPS_MISC_COMMAND 0x0C00
#define PPS_MISC_QUERY_COMMAND 0x0D00 // triggers a corresponding PPS_MISC_COOMAND towards the PPS2 Display
//#define PPS_PUMP_MODE (PPS_MISC_COMMAND | 0x01)
#define PPS_PUMP_MAXSPEED (PPS_MISC_COMMAND | 0x02)
#define PPS_PUMP_SPEEDUNIT (PPS_MISC_COMMAND | 0x03)
#define PPS_PUMP_MODE_TYPE (PPS_MISC_COMMAND | 0x04)
#define PPS_PUMP_COUPLE (PPS_MISC_COMMAND | 0x05)
#define PPS_PUMP_ENABLE_SPEEDRATIO (PPS_MISC_COMMAND | 0x06)
#define PPS_PUMP_MANUALONOFF (PPS_MISC_COMMAND | 0x10)
#define PPS_PUMP_FUNCTIONSPEED (PPS_MISC_COMMAND | 0x11)
#define PPS_PUMP_SPEEDRATIO (PPS_MISC_COMMAND | 0x12)
#define PPS_PUMP_FASTONOFF (PPS_MISC_COMMAND | 0x13)
#define PPS_PUMP_FASTSPEED (PPS_MISC_COMMAND | 0x14)
#define PPS_ANALOGVOLTAGE (PPS_MISC_COMMAND | 0x21)
#define PPS_USE_BUBBLEDETECTOR (PPS_MISC_COMMAND | 0x22)
//#define PPS_DIGITAL_IN (PPS_MISC_COMMAND | 0x23) // ?
//#define PPS_DIGITAL_OUT (PPS_MISC_COMMAND | 0x24) // ?
#define PPS_GET_SUPPLYVOLTAGE (PPS_MISC_COMMAND | 0x30)
#define PPS_GET_ANALOGVOLTAGE (PPS_MISC_COMMAND | 0x31)
#define PPS_GET_DIGITALIN (PPS_MISC_COMMAND | 0x32)
#define PPS_GET_BUBBLESTATE (PPS_MISC_COMMAND | 0x33)
#define MEA_CLEAN_COMMAND 0x0E00
#define MEA_CLEAN_START_STOP (MEA_CLEAN_COMMAND | 0x01)
#define MEA_CLEAN_SLOPE (MEA_CLEAN_COMMAND | 0x02)
#define MEA_CLEAN_CYCLES (MEA_CLEAN_COMMAND | 0x03)
#define MEA_CLEAN_UMIN (MEA_CLEAN_COMMAND | 0x04)
#define MEA_CLEAN_UMAX (MEA_CLEAN_COMMAND | 0x05)
#define MEA_CLEAN_UOUTPUT (MEA_CLEAN_COMMAND | 0x06)
#define MEA_CLEAN_CYCLENOW (MEA_CLEAN_COMMAND | 0x07)
#define MEA_COAT_COMMAND 0x0E80
#define MEA_COAT_START_STOP (MEA_COAT_COMMAND | 0x01)
#define MEA_COAT_SLOPE (MEA_COAT_COMMAND | 0x02)
#define MEA_COAT_DURATION (MEA_COAT_COMMAND | 0x03)
#define MEA_COAT_IMAX (MEA_COAT_COMMAND | 0x04)
#define MEA_COAT_IOFFSET (MEA_COAT_COMMAND | 0x05)
#define MEA_COAT_IOUTPUT (MEA_COAT_COMMAND | 0x06)
#define MEA_COAT_TINPLATEAU (MEA_COAT_COMMAND | 0x07)
#define MEA_COAT_PAUSEDURATION (MEA_COAT_COMMAND | 0x08)
#define MEA_COAT_TINPAUSE (MEA_COAT_COMMAND | 0x09)
#define MEA_COAT_CYCLES (MEA_COAT_COMMAND | 0x0a)
#define MEA_COAT_CYCLENOW (MEA_COAT_COMMAND | 0x0b)
#define EXTERN_D_TESTER_MISC_COMMAND 0x0F00
#define EXTERN_D_TESTER_GET_DATABLOCK (EXTERN_D_TESTER_MISC_COMMAND | 0x01)
#define MBC08_MISC_COMMAND 0x1000
#define MBC08_CHARGE_CURRENT (MBC08_MISC_COMMAND | 0x01)
#define MBC08_DISCHARGE_CURRENT (MBC08_MISC_COMMAND | 0x02)
#define MBC08_FINALDISCHARGE_VOLTAGE (MBC08_MISC_COMMAND | 0x03)
#define MBC08_DISCHARGE_CAPACITY (MBC08_MISC_COMMAND | 0x04)
#define MBC08_BATT_VOLTAGE (MBC08_MISC_COMMAND | 0x05)
#define MBC08_RESET_CHANNEL (MBC08_MISC_COMMAND | 0x06)
#define MBC08_CHANNELS (MBC08_MISC_COMMAND | 0x07)
#define MBC08_CHARGING_MODE (MBC08_MISC_COMMAND | 0x08)
#define MBC08_CAPACITY_TEST (MBC08_MISC_COMMAND | 0x09)
#define MBC08_CHANNEL_STATE (MBC08_MISC_COMMAND | 0x0A)
#define MBC08_CHARGE_CAPACITY (MBC08_MISC_COMMAND | 0x0B)
#define MBC08_SP_DISCHARGE_CURRENT (MBC08_MISC_COMMAND | 0x0C)
#define MBC08_CHARGE_P_COEFF (MBC08_MISC_COMMAND | 0x0D)
#define MBC08_RATED_CAPACITY_VOLATILE (MBC08_MISC_COMMAND | 0x0E)
#define MBC08_RATED_CAPACITY (MBC08_MISC_COMMAND | 0x0F)
// #define *_MISC_COMMAND 0x1100 // is free
#define PPC_MISC_COMMAND 0x1200
#define PPC_MISC_QUERY_COMMAND 0x1300 // triggers a corresponding PPC_MISC_COOMAND towards the PPC Display
#define PPC_MISC_COMMAND_MASK 0xFF00
//#define PPC_PUMP_MODE (PPC_MISC_COMMAND | 0x01)
#define PPC_PUMP_SPEEDUNIT (PPC_MISC_COMMAND | 0x03)
#define PPC_PUMP_MODE_TYPE (PPC_MISC_COMMAND | 0x04)
#define PPC_VALVE_ACTIVE (PPC_MISC_COMMAND | 0x05)
#define PPC_LOAD_PRESSURE (PPC_MISC_COMMAND | 0x06)
#define PPC_BUSY (PPC_MISC_COMMAND | 0x07)
#define PPC_FIRE_PRESSURE_PULSE (PPC_MISC_COMMAND | 0x08)
#define PPC_MEASURE_RESERVOIR (PPC_MISC_COMMAND | 0x09)
#define PPC_ANALOGVOLTAGE (PPC_MISC_COMMAND | 0x20)
#define PPC_PRESSURERANGES (PPC_MISC_COMMAND | 0x21)
//#define PPC_DIGITAL_IN (PPC_MISC_COMMAND | 0x23) // ?
//#define PPC_DIGITAL_OUT (PPC_MISC_COMMAND | 0x24) // ?
#define PPC_GET_SUPPLYVOLTAGE (PPC_MISC_COMMAND | 0x30)
#define PPC_GET_ANALOGVOLTAGE (PPC_MISC_COMMAND | 0x31)
#define PPC_GET_DIGITALIN (PPC_MISC_COMMAND | 0x32)
#define PPC_GETPRESSURE (PPC_MISC_COMMAND | 0x80 | 20) // The same Commands exit on the MCSBUS and are feed through
#define PPC_GETREGULATORSPEED (PPC_MISC_COMMAND | 0x80 | 21)
#define PPC_SOLLPRESSURE (PPC_MISC_COMMAND | 0x80 | 22)
#define PPC_REGULATORONOFF (PPC_MISC_COMMAND | 0x80 | 23)
#define PPC_REGULATORFACTORS (PPC_MISC_COMMAND | 0x80 | 24)
#define PPC_SETPRESSUREOFFSET (PPC_MISC_COMMAND | 0x80 | 25)
#define PPC_REGULATORSTATUS (PPC_MISC_COMMAND | 0x80 | 26)
#define PPC_ROTATE_PERISTALTIC (PPC_MISC_COMMAND | 0x80 | 27)
#define PPC_MOVE_PERISTALTIC (PPC_MISC_COMMAND | 0x80 | 28)
#define PPC_SETTIMEOUTS (PPC_MISC_COMMAND | 0x80 | 29)
#define PEDOTER_MISC_COMMAND 0x1400
#define PEDOTER_COMMAND (PEDOTER_MISC_COMMAND | 0x01)
// #define *_MISC_COMMAND 0x1500 - 0x1E00 // are free
#define DEVICE_STATE_PUSH_TRIGGER_STATUS 0x1F00
#define WVC_MISC_COMMAND 0x2000
#define WVC_DISPLAY_QUERY (WVC_MISC_COMMAND | 0x00) // only used between display and control unit
#define WVC_VALVE_ACTIVE (WVC_MISC_COMMAND | 0x01)
#define WVC_VALVE_MODE (WVC_MISC_COMMAND | 0x02)
#define WVC_VALVE_ACTIVE_MAP (WVC_MISC_COMMAND | 0x03)
#define WVC_VALVE_MANUAL_STATE (WVC_MISC_COMMAND | 0x04)
#define WVC_VALVE_MANUAL_STATE_MAP (WVC_MISC_COMMAND | 0x05)
#define WVC_VALVE_MANUAL_GROUP (WVC_MISC_COMMAND | 0x06)
#define WVC_VALVE_ANALOG_THRESHOLD_LOW (WVC_MISC_COMMAND | 0x08)
#define WVC_VALVE_ANALOG_THRESHOLD_HIGH (WVC_MISC_COMMAND | 0x09)
#define WVC_DIGITAL_PORT_DIRECTION (WVC_MISC_COMMAND | 0x10)
#define WVC_VALVE_DIGITAL_IN_INVERT (WVC_MISC_COMMAND | 0x11)
#define WVC_VALVE_DIGITAL_IN_CHANNEL (WVC_MISC_COMMAND | 0x12)
#define WVC_DIGITAL_OUT_INVERT (WVC_MISC_COMMAND | 0x13)
#define WVC_DIGITAL_OUT_VALVE_CHANNEL (WVC_MISC_COMMAND | 0x14)
#define WVC_SET_DEFAULT_PARAMETER (WVC_MISC_COMMAND | 0x18)
#define WVC_VALVE_IS_OPEN (WVC_MISC_COMMAND | 0x20)
#define WVC_VALVE_IS_OPEN_DIGITAL_MODE (WVC_MISC_COMMAND | 0x21)
#define WVC_VALVE_IS_OPEN_ANALOG_MODE (WVC_MISC_COMMAND | 0x22)
#define WVC_EXTERN_ANALOG_VOLTAGE (WVC_MISC_COMMAND | 0x23)
#define WVC_TABLE_ENTRY (WVC_MISC_COMMAND | 0x30)
#define WVC_TABLE_CLEAR (WVC_MISC_COMMAND | 0x31)
#define WVC_TABLE_LOAD (WVC_MISC_COMMAND | 0x32)
#define WVC_TABLE_STORE (WVC_MISC_COMMAND | 0x33)
#define WVV_TABLE_NAME (WVC_MISC_COMMAND | 0x34)
#define WVC_TABLE_ENTRY_CHANGED (WVC_MISC_COMMAND | 0x35)
#define WVV_TABLE_NAME_BY_INDEX (WVC_MISC_COMMAND | 0x36)
#define WVC_ACTIVE_RUNNING_TABLE_NUMBER (WVC_MISC_COMMAND | 0x38)
#define WVC_CURRENT_EDIT_TABLE_NUMBER (WVC_MISC_COMMAND | 0x39)
#define WVC_TABLE_STEP_TIME (WVC_MISC_COMMAND | 0x40)
#define WVC_TABLE_STEP (WVC_MISC_COMMAND | 0x41)
#define WVC_TABLE_STEP_ALL (WVC_MISC_COMMAND | 0x42)
#define WVC_NUMBER_OF_VALVES (WVC_MISC_COMMAND | 0x50)
#define WVC_NUMBER_OF_DIGITALPORTS (WVC_MISC_COMMAND | 0x51)
#define WVC_TABLESIZE (WVC_MISC_COMMAND | 0x52)
#define WVC_NUMBER_OF_TABLES (WVC_MISC_COMMAND | 0x53)
#define WVC_CONNECTED_NUMBER_OF_VALVES (WVC_MISC_COMMAND | 0x58)
#define WVC_GET_BOARD_REVISION (WVC_MISC_COMMAND | 0x60)
#define WVC_DISPLAY_MODE (WVC_MISC_COMMAND | 0x81)
//#define MANUAL_TRIGGER // bitmap ?
// DeviceTester commands
#define WVC_DEVICETESTER_MASK (0xFFF0)
#define WVC_DEVICETESTER_COMMAND (WVC_MISC_COMMAND | 0xF0)
#define WVC_DEVICETESTER_SET_ADC (WVC_MISC_COMMAND | 0xF1)
#define WVC_DEVICETESTER_SETGET_TRIGGERSYNC (WVC_MISC_COMMAND | 0xF2)
#define WVC_DEVICETESTER_SET_TRIGGERSYNC_DIRECTION (WVC_MISC_COMMAND | 0xF3)
#define WVC_DEVICETESTER_SETGET_IO (WVC_MISC_COMMAND | 0xF4)
#define WVC_DEVICETESTER_SET_IO_DIRECTION (WVC_MISC_COMMAND | 0xF5)
#define POSITIONIMP_MISC_COMMAND 0x3000
#define POSITIONIMP_CONNECT (POSITIONIMP_MISC_COMMAND | 0x00)
#define POSITIONIMP_RFFREQUENCY (POSITIONIMP_MISC_COMMAND | 0x01)
#define POSITIONIMP_DEVICELIST (POSITIONIMP_MISC_COMMAND | 0x02)
#define POSITIONIMP_DEVICEID (POSITIONIMP_MISC_COMMAND | 0x03)
#define TEER_MISC_COMMAND 0x3100
#define TEER_MISC_COMMAND_MASK 0xFF00
#define TEER_PERIOD (TEER_MISC_COMMAND | 0x01)
#define TEER_AMPLITUDE (TEER_MISC_COMMAND | 0x02)
#define TEER_WAVEFORM (TEER_MISC_COMMAND | 0x03)
//#define TEER_SAMPLE (TEER_MISC_COMMAND | 0x04)
#define TEER_CLAMP_MODE (TEER_MISC_COMMAND | 0x05)
#define TEER_START_SAMPLING (TEER_MISC_COMMAND | 0x06)
#define TEER_IS_SAMPLING_FINISHED (TEER_MISC_COMMAND | 0x07)
#define TEER_CONTROL_PARAMS (TEER_MISC_COMMAND | 0x08)
#define TEER_STOP_SAMPLING (TEER_MISC_COMMAND | 0x09)
#define TEER_GET_BUFFER (TEER_MISC_COMMAND | 0x0A)
#define TEER_GET_COMPLIANCE_VOLTAGE_BUFFER (TEER_MISC_COMMAND | 0x0B)
#define TEER_GET_MAX_CHUNKSIZE_BYTE (TEER_MISC_COMMAND | 0x0C)
#define TEER_GET_BYTES_PER_SAMPLE (TEER_MISC_COMMAND | 0x0D)
#define TEER_GET_NUMBER_OF_AVAILABLE_SAMPLES (TEER_MISC_COMMAND | 0x0E)
#define TEER_BUFFER_INDEX (TEER_MISC_COMMAND | 0x0F)
#define TEER_GET_ADAPTER_CODE (TEER_MISC_COMMAND | 0x10)
#define TEER_GET_POSITION_CODE (TEER_MISC_COMMAND | 0x11)
#define TEER_SET_EXTERNAL_LED (TEER_MISC_COMMAND | 0x12)
#define TEER_CURRENT_ENABLE (TEER_MISC_COMMAND | 0x13)
#define TEER_UPTIME_SEC (TEER_MISC_COMMAND | 0x14)
#define TEER_INTERNAL_CALIBRATION (TEER_MISC_COMMAND | 0x15)
#define TEER_DAC_ZERO (TEER_MISC_COMMAND | 0x16)
#define TEER_CANCEL_INTERNAL_CALIBRATION (TEER_MISC_COMMAND | 0x17)
#define USSING_MISC_COMMAND 0x3200
#define USSING_MISC_COMMAND_MASK 0xFF00
#define USSING_CHANNELS_PER_CHAMBER (USSING_MISC_COMMAND | 0x01)
#define USSING_GET_MAX_CHAMBERS (USSING_MISC_COMMAND | 0x02)
#define USSING_GET_AVAILABLE_CHAMBERS (USSING_MISC_COMMAND | 0x03)
#define USSING_IS_CHAMBER_AVAILABLE (USSING_MISC_COMMAND | 0x04)
//#define USSING_SET_PULSE (USSING_MISC_COMMAND | 0x05)
#define USSING_HIGH_CURRENT_MODE (USSING_MISC_COMMAND | 0x06)
#define USSING_CLAMP_MODE (USSING_MISC_COMMAND | 0x07)
#define USSING_CALIB_FINISHED (USSING_MISC_COMMAND | 0x08)
#define USSING_U1_OFFSET (USSING_MISC_COMMAND | 0x09)
#define USSING_U2_OFFSET (USSING_MISC_COMMAND | 0x0A)
#define USSING_U1_REFERENCE (USSING_MISC_COMMAND | 0x0B)
#define USSING_U2_REFERENCE (USSING_MISC_COMMAND | 0x0C)
#define USSING_CONTROL_P (USSING_MISC_COMMAND | 0x0D)
#define USSING_CONTROL_I (USSING_MISC_COMMAND | 0x0E)
#define USSING_CONTROL_D (USSING_MISC_COMMAND | 0x0F)
#define USSING_DAC_ZERO (USSING_MISC_COMMAND | 0x10)
#define USSING_AMPS_PER_DIGIT_LOW (USSING_MISC_COMMAND | 0x11)
#define USSING_AMPS_PER_DIGIT_HIGH (USSING_MISC_COMMAND | 0x12)
#define USSING_LO_CURRENT_RANGE_PAMP (USSING_MISC_COMMAND | 0x13)
#define USSING_VOLTS_PER_DIGIT (USSING_MISC_COMMAND | 0x14)
#define USSING_UNITS_PER_DIGIT (USSING_MISC_COMMAND | 0x15)
#define USSING_UNIT_METRIC_PREFIX (USSING_MISC_COMMAND | 0x16)
#define USSING_UNIT_NAME (USSING_MISC_COMMAND | 0x17)
#define USSING_UNIT_DESC (USSING_MISC_COMMAND | 0x18)
#define USSING_HI_CURRENT_RANGE_NAMP (USSING_MISC_COMMAND | 0x19)
#define USSING_UPTIME_SEC (USSING_MISC_COMMAND | 0x1A)
#define USSING_IDLE_VOLTAGE (USSING_MISC_COMMAND | 0x1B)
#define USSING_IDLE_CURRENT (USSING_MISC_COMMAND | 0x1C)
#define USSING_ENABLE_VOLTAGE_CLAMP (USSING_MISC_COMMAND | 0x1D)
#define USSING_ENABLE_CURRENT_CLAMP (USSING_MISC_COMMAND | 0x1E)
#define USSING_SET_PULSE_AMP (USSING_MISC_COMMAND | 0x1F)
#define USSING_SET_PULSE_DUR (USSING_MISC_COMMAND | 0x20)
#define MISC_USB_COMMAND2 0x4b // Device specific commands (2)
#define MISC_USB_COMMAND3 0x4c // Device specific commands (3)
#define MISC_USB_COMMAND4 0x4d // Device specific commands (4)
#define QUERY_UINT32 0x4e
// values for query_uint32
#define GET_UINT32_NUMBER_OF_AVAIL_ANALOG_CHANNELS 0x000E
#define GET_UINT32_NUMBER_OF_AVAIL_DIGITAL_CHANNELS 0x000F
#define GET_UINT32_NUMBER_OF_CHANNELS 0x0010
#define GET_UINT32_GAIN 0x0011 // was GET_UINT32_AMPLIFICATION; Amplification = Value, when bit 31 is set Amplification = Value/1000
#define GET_UINT32_ADC_OFFSET 0x0012
#define GET_UINT32_DAC_OFFSET 0x0013
#define GET_UINT32_ENUMERATION_SPEED 0x0014
#define GET_UINT32_USB_VERSION 0x0015 // not used any more
#define GET_UINT32_IVOLTAGERANGE 0x0016 // index of currently set voltagerange
#define GET_UINT32_DATAMODE 0x0017 // MEA21: 16, 24 or 32 bit data mode
#define GET_UINT32_MEA21_USB_PORT 0x0018 // 0 or 1 for USB Port 1 or 2
#define GET_UINT32_AVAILABLE_DATAMODES 0x0019 // bitmask 1: 16 bit, 2: 24 bit MC_Rack, 4: 24 bit, 8: 32 bit
#define GET_UINT32_ADC_FORMAT 0x001a // format of the ADC data (12 / 16 / 24 bit)
#define GET_UINT32_ANALOG_GAIN 0x001b // on the MEA2100, the gain of the analog inputs on the IFB, Gain = Value/1000
#define GET_UINT32_MAX_SAMPLING_FREQUENCY 0x0020
#define GET_UINT32_BYTES_PER_MICROFRAME 0x0021
#define GET_UINT32_IS_MEA 0x0022
#define GET_UINT32_SAMPLING_FREQUENCY_STEPSIZE 0x0023
#define GET_UINT32_NUMBER_OF_ANALOG_CHANNELS 0x0101
#define GET_UINT32_NUMBER_OF_DIGITAL_CHANNELS 0x0102
#define GET_UINT32_NUMBER_OF_CHECKSUM_CHANNELS 0x0103
#define GET_UINT32_NUMBER_OF_TIMESTAMP_CHANNELS 0x0104
#define GET_UINT32_NUMBER_OF_CHANNELS_IN_BLOCK 0x010f
#define GET_UINT32_NUMBER_OF_AUDIO_CHANNELS 0x0120
#define GET_UINT32_VOLTAGERANGE_BY_INDEX 0x0130 // list of available voltageranges
#define GET_UINT32_SAMPLERATES_BY_INDEX 0x0131 // list of available samplerates
#define GET_UINT32_UPPER_FREQ_BY_INDEX 0x0140
#define GET_UINT32_LOWER_FREQ_BY_INDEX 0x0141
#define GET_UINT32_DSP_HIPASS_BY_INDEX 0x0142
#define GET_UINT32_INTAN_REGISTER 0x0143
#define GET_UINT32_IMPEDANCE_RESULT 0x0144
#define GET_UINT32_PLL_LOCK_STATUS 0x0150
#define GET_UINT32_XILINX_FLASH_OFFSET 0x0201
#define GET_UINT32_XILINX_FLASH_READ_COMMAND 0x0202
#define GET_UINT32_USB_LAST_ERROR 0x0301
#define GET_UINT32_RF_CONNECTION_STATUS 0x0302
#define GET_UINT32_REQUIRED_ALTERNATE_SETTINGS 0x0303
#define GET_UINT32_DEVICE_CANNOT_STALL_OUT_REQUEST 0x0304
#define GET_UINT32_IMPLANTAT_VOLTAGE 0x0401
#define GET_UINT32_FLAGA_PRE 0xf001
#define GET_UINT32_FLAGB_PRE 0xf002
#define GET_UINT32_FLAGC_PRE 0xf003
#define GET_UINT32_FLAGA_POST 0xf004
#define GET_UINT32_FLAGB_POST 0xf005
#define GET_UINT32_FLAGC_POST 0xf006
#define COMMAND_UPLOAD 0x50 // has MCSUSB_DEST_... as wValue
#define COMMAND_FLASH 0x51 // has MCSUSB_DEST_... as wValue
#define COMMAND_EEPROM 0x52
#define COMMAND_COLDSTART 0x53 // has MCSUSB_DEST_... as wValue
#define COMMAND_BOARD_EEPROM 0x54
#define COMMAND_SETSERIAL 0x55
#define COMMAND_FOR_PIC 0x56
#define COMMAND_USB_COLDSTART 0x01 // not used any more
#define COMMAND_TMS_COLDSTART 0x02 // not used any more
#define COMMAND_PIC2_COLDSTART 0x04 // not used any more
#define COMMAND_BACKUP_EEPROM 0x10 // not used any more
#define COMMAND_RESTORE_EEPROM 0x11 // not used any more
#define COMMAND_ERASE_EEPROM 0x12 // not used any more
#define COMMAND_FLASH_PIC 0x20 // not used any more
#define COMMAND_RELAY_MODE 0x21 // releay i2c commands to 2nd pic
#define COMMAND_POWER_TRANSFORMER 0x30 // turn pwm for transformer on or off
#define COMMAND_ENABLE_SERIAL 0x40 // not used any more
#define COMMAND_PIC_READ_ADC0 0x81
#define COMMAND_PIC_READ_ADC1 0x82 // used with index from COMMAND_PIC_READ_ADC0
#define COMMAND_PIC_READ_VERSION 0x90 // not used any more
#define COMMAND_PIC_GET_FLASHSIZE 0x91 // not used any more
#define COMMAND_PIC_READ_MEMORY 0x57
#define COMMAND_CYPRESS_USB 0x58
#define CYPRESS_USB_INPKTEND 0x01
#define CYPRESS_USB_FIFORESET 0x11
#define CYPRESS_USB_SETEP2ISOINPKTS 0x21
#define CYPRESS_USB_BULK_ERASE_AVAIL 0x80
#define CYPRESS_USB_BULK_ERASE 0x81
#define COMMAND_FOR_PIC2 0x59
#define COMMAND_FOR_PIC3 0x5a
#define COMMAND_DOWNLOAD_EX 0x60 // extension to COMMAND_DOWNLOAD, so that it works on any target and addresses > 24bit
#define COMMAND_DOWNLOAD 0x61
#define COMMAND_FLASHMODE 0x62 // supported for all PIC devices with our new Vendor ID, tell a pic to enter flashmode
#define COMMAND_GET_FLASHSIZE 0x63 // supported for all PIC devices with our new Vendor ID, query the available flash memory
#define COMMAND_HARDWARE_TEST 0x64
#define COMMAND_TXN_TEST_MEMORY_WRITE 0x01 // Check the memory of the TXN module: Write Values
#define COMMAND_TXN_TEST_MEMORY_READ_AND_CHECK 0x02 // Check the memory of the TXN module: Read Values and Check
#define COMMAND_TXN_SETSERIALNUMBER 0x11 // Sets the internal serial number of the TXN module
#define COMMAND_TXN_GETSERIALNUMBER 0x12 // Gets the internal serial number of the TXN module
#define COMMAND_WRITE_REGISTER 0x21 // Write to a Register (used on Xilinx FPGA devices)
#define COMMAND_READ_REGISTER 0x22 // Read from a Register (used on Xilinx FPGA devices)
#define COMMAND_WRITE_REGISTER_TS_0 0x30 // Write to a Register (used on Xilinx FPGA devices) - time slot 0
#define COMMAND_WRITE_REGISTER_TS_1 0x31 // Write to a Register (used on Xilinx FPGA devices) - time slot 1
#define COMMAND_WRITE_REGISTER_TS_2 0x32 // Write to a Register (used on Xilinx FPGA devices) - time slot 2
#define COMMAND_WRITE_REGISTER_TS_3 0x33 // Write to a Register (used on Xilinx FPGA devices) - time slot 3
/* 0x34 - 0x3F reserved in W2100 */
#define COMMAND_READ_REGISTER_TS_0 0x40 // Read from a Register (used on Xilinx FPGA devices) - time slot 0
#define COMMAND_READ_REGISTER_TS_1 0x41 // Read from a Register (used on Xilinx FPGA devices) - time slot 1
#define COMMAND_READ_REGISTER_TS_2 0x42 // Read from a Register (used on Xilinx FPGA devices) - time slot 2
#define COMMAND_READ_REGISTER_TS_3 0x43 // Read from a Register (used on Xilinx FPGA devices) - time slot 3
/* 0x44 - 0x4F reserved in W2100 */
#define COMMAND_RADIO_CONTROL 0x65
#define COMMAND_RADIO_HAS_RADIO_CONTROL 0x01
#define COMMAND_RADIO_GET_DEVICE_NAMES 0x02
#define COMMAND_RADIO_CONNECT_DEVICE 0x03
#define COMMAND_RADIO_DISCONNECT_DEVICE 0x04
#define COMMAND_RADIO_STILL_CONNECTED 0x05
#define COMMAND_RADIO_SET_FREQUENCY 0x06
#define COMMAND_RADIO_GET_FREQUENCY 0x07
#define COMMAND_MCSBUS 0x66 // Commands send to the MCSBUS
// *** AB Commands ***
#define MCSBUS_COMMAND_LEGACY 0x0080 // This bit was always set for AB commands, only needed in firmware to catch old DLL version which send COMMAND_MCSBUS as COMMAND_ROBO
#define MCSBUS_USB 0x0040 // distingish between MCSBUS short commands and USB commands
#define MCSBUS_OUT_SET_COMMAND 0x00
#define MCSBUS_IN_GET_COMMAND 0x20
#define MCSBUS_BUSNUMBER_SHIFT 13 // The bus number is shifted to this position in the index;
#define MCSBUS_BUSNUMBER_MASK (7 << MCSBUS_BUSNUMBER_SHIFT)
#define MCSBUS_MC_COMMAND_SHIFT 3 // 1 bit for 2 axis + 2 bit for size
#define MCSBUS_VM_COMMAND_SHIFT 4 // 2 bit for 4 channels + 2 bit for size
// in MotorControl Mode, bit 2 selects the axis
// in Voltage Mode, bit 2 selects the side, bit 3 selects the subchannel
// 00: Channel 0
// 01: Channel 2
// 10: Channel 1
// 11: Channel 3
// this allows the module to operate one side in MC mode and the other in Voltage mode
// McsBus USB Commands // only 4 bits for usb (different to short commands), because both commands needs to be handled
// Eeprom
#define MCSBUS_EEPROM_PARAMETER (0x00 << MCSBUS_VM_COMMAND_SHIFT)
#define MCSBUS_PARAMETER (0x08 << MCSBUS_VM_COMMAND_SHIFT)
#define MCSBUS_PARAMETER_INDEX_MODE 0 // define the mode (MotorControl, Voltage, ..
#define MCSBUS_PARAMETER_INDEX_MC_SCALINGFACTOR 1
#define MCSBUS_PARAMETER_INDEX_MC_MAXSPEED 2
#define MCSBUS_PARAMETER_INDEX_MC_MAXTRAVEL 3
#define MCSBUS_PARAMETER_INDEX_MC_CURRENT 4
#define MCSBUS_PARAMETER_INDEX_MC_MAXCURRENT 5
#define MCSBUS_PARAMETER_INDEX_MC_REGULATORGAIN 6
#define MCSBUS_PARAMETER_INDEX_BUSADDRESS 7 // must be implemented in all MCSBUS devices
#define MCSBUS_PARAMETER_INDEX_MC_MAXACCELERATION 8
#define MCSBUS_PARAMETER_INDEX_MC_STANDBYCURRENT 9
#define MCSBUS_PARAMETER_INDEX_MC_STANDBYTIME 10
#define MCSBUS_PARAMETER_INDEX_MC_BREAKCURRENT 11
#define MCSBUS_PARAMETER_INDEX_MC_CONFIG 12
#define MCSBUS_PARAMETER_INDEX_MC_DEFAULTSPEED 13
#define MCSBUS_PARAMETER_INDEX_MC_DEFAULTACCELERATION 14
#define MCSBUS_PARAMETER_INDEX_MC_REFERENCECURRENT 15
#define MCSBUS_PARAMETER_INDEX_MC_CURRENTMODE 16
#define MCSBUS_PARAMETER_INDEX_MC_AXISREVISION 17
#define MCSBUS_PARAMETER_INDEX_HWREVISION 18
#define MCSBUS_PARAMETER_INDEX_VM_MAX_POS_CURRENT 30
#define MCSBUS_PARAMETER_INDEX_VM_MAX_NEG_CURRENT 31
#define MCSBUS_PARAMETER_INDEX_VM_MAX_POS_VOLTAGE 32
#define MCSBUS_PARAMETER_INDEX_VM_MAX_NEG_VOLTAGE 33
#define MCSBUS_PARAMETER_INDEX_AXIS_PARAMETER 64 // only for command MCSBUS_EEPROM_PARAMETER
// ... 78 15 Axis Parameter indices per axis
#define MCSBUS_PARAMETER_INDEX_SPEED_UNIT 64 // This position of axis parameter is used for SPEED UNIT
#define MCSBUS_SENSOR (0x01 << MCSBUS_VM_COMMAND_SHIFT) // to modules connected via i2c slave to AB_RevA module
// index bits 8 .. 12 are used in some commands to select channel
#define MCSBUS_SENSOR_INDEX_MINIMAL_THRESHOLD 1 // Bubble detector
#define MCSBUS_SENSOR_INDEX_DETECTION_THRESHOLD 2
#define MCSBUS_SENSOR_INDEX_LATENCY 3
#define MCSBUS_SENSOR_INDEX_BUBBLE_STATUS 10
#define MCSBUS_SENSOR_INDEX_LATENCY_COUNTER 11
#define MCSBUS_SENSOR_INDEX_RESTART 12
#define MCSBUS_SENSOR_INDEX_DETECTORVALUE 13
#define MCSBUS_SENSOR_INDEX_GETPRESSURE 20 // FYI pressure module, PressureRegulator8 module
#define MCSBUS_SENSOR_INDEX_GETREGULATORSPEED 21
#define MCSBUS_SENSOR_INDEX_SOLLPRESSURE 22
#define MCSBUS_SENSOR_INDEX_REGULATORONOFF 23
#define MCSBUS_SENSOR_INDEX_REGULATORFACTORS 24
#define MCSBUS_SENSOR_INDEX_SETPRESSUREOFFSET 25
#define MCSBUS_SENSOR_INDEX_REGULATORSTATUS 26
#define MCSBUS_SENSOR_INDEX_ROTATE_PERISTALTIC 27
#define MCSBUS_SENSOR_INDEX_MOVE_PERISTALTIC 28
#define MCSBUS_SENSOR_INDEX_SETTIMEOUTS 29
// reserved bit 8 to 10 is used as index to the motor
#define MCSBUS_SENSOR_INDEX_GET4ADC 30 // Patch Server DAC ADC module
#define MCSBUS_SENSOR_INDEX_SET4DAC 31
#define MCSBUS_SENSOR_INDEX_4ADC_MODE 32
#define MCSBUS_SENSOR_INDEX_GET4ADC_AVERAGE 33
#define MCSBUS_SENSOR_INDEX_CATCHAMP_AVERAGE_SHIFT 34
#define MCSBUS_SENSOR_INDEX_GET2ANALOGINPUT 35
#define MCSBUS_SENSOR_INDEX_GET2DIGITALINPUT 36
#define MCSBUS_SENSOR_INDEX_GETBUFFER 40 // Patch Server get data buffer
#define MCSBUS_SENSOR_INDEX_SETPIEZO 41
#define MCSBUS_SENSOR_INDEX_SETDAC 50 // Patch Server DAC ADC module DAC programm
// reserved - 53
#define MCSBUS_SENSOR_INDEX_SAMPLEPERIODE 60 // Patch Server DAC ADC module
#define MCSBUS_SENSOR_INDEX_SYNCSTART 61 // Patch Server DAC ADC module start in sync
#define MCSBUS_SENSOR_INDEX_CATCHAMP_DACAMPLITUDE 70
#define MCSBUS_SENSOR_INDEX_CATCHAMP_DACOFFSET 71
#define MCSBUS_SENSOR_INDEX_CATCHAMP_ADCMEAN 72
#define MCSBUS_SENSOR_INDEX_CATCHAMP_ADCVALUE 73
#define MCSBUS_SENSOR_INDEX_CATCHAMP_ADCVALUE_H 74
#define MCSBUS_SENSOR_INDEX_CATCHAMP_ADCVALUE_L 75
#define MCSBUS_SENSOR_INDEX_CATCHAMP_PWM_ENABLE 76
#define MCSBUS_SENSOR_INDEX_CATCHAMP_DAC_ENABLE 77
#define MCSBUS_SENSOR_INDEX_TACTSWITCH_GETSTATE 90
#define MCSBUS_SENSOR_INDEX_TACTSWITCH_DISPLAY 91
#define MCSBUS_SENSOR_INDEX_TACTSWITCH_SET_LEDS 92
#define MCSBUS_SENSOR_INDEX_PROGRAM 100
#define MCSBUS_SENSOR_INDEX_PROGRAM_PRESSURE 101
#define MCSBUS_SENSOR_INDEX_PROGRAM_PRESSURE_STEPS 102
#define MCSBUS_SENSOR_INDEX_PROGRAM_DURATION 103
#define MCSBUS_SENSOR_INDEX_PROGRAM_SIZE 104
#define MCSBUS_SENSOR_INDEX_PROGRAM_REPEAT 105
// max allowed value for index: 255
#define MCSBUS_TEMP_SENSOR (0x02 << MCSBUS_VM_COMMAND_SHIFT)
#define MCSBUS_TEMP_SENSOR_INDEX_TEMPERATUR 1
// reserved - 5
#define MCSBUS_TEMP_SENSOR_INDEX_NANOVOLTPERKELVIN 0x10
#define MCSBUS_TEMP_SENSOR_INDEX_GET_THERMO_VOLTAGE 0x11
// reserved - 0x15
#define MCSBUS_TEMP_SENSOR_INDEX_GET_THERMO_TEMP 0x21
// reserved - 0x25
#define MCSBUS_TEMP_SENSOR_INDEX_OFFSET 0x31
// reserved - 0x35
#define MCSBUS_EXTENSION (0x03 << MCSBUS_VM_COMMAND_SHIFT)
#define MCSBUS_EXTENSION_INDEX_LED 1
#define MCSBUS_FYI_EXTENSION (0x04 << MCSBUS_VM_COMMAND_SHIFT)
#define MCSBUS_FYI_EXTENSION_VALVES 1
// #define MCSBUS_FYI_EXTENSION_HEATER 2
#define MCSBUS_FYI_EXTENSION_DIO 3
#define MCSBUS_FYI_EXTENSION_DATADIR 4
#define MCSBUS_FYI_EXTENSION_SINGLE_HEATER 5
// reserved - 9
// SEE_ABOVE after MCSBUS_EEPROM_PARAMETER (0x08 << MCSBUS_VM_COMMAND_SHIFT)
// McsBus Short Commands
// for AB Module in MotorControl mode
#define MCSBUS_MC_ONOFF (0x00 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_SPEED (0x01 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_ACCELERATION (0x02 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_CURRENT (0x03 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_MAXTRAVEL (0x04 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_CURRENTPOSITION (0x05 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_NEWPOSITION (0x06 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_MOVEMENT (0x07 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_REFERENCE (0x08 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_STOPMOVEMENT (0x09 << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_CURRENTSPEED (0x0a << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_CURRENTMODE (0x0b << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_PHASE (0x0c << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_PHASEOFFSET (0x0d << MCSBUS_MC_COMMAND_SHIFT)
#define MCSBUS_MC_SETSUBCHANNEL (0x0e << MCSBUS_MC_COMMAND_SHIFT)
//0x0f
//0x10
//0x11
//...
//0x1f
// for AB Module in Voltage mode
#define MCSBUS_VM_ONOFF (0x00 << MCSBUS_VM_COMMAND_SHIFT)
#define MCSBUS_VM_VOLTAGE (0x01 << MCSBUS_VM_COMMAND_SHIFT)
//0x02
//...
//0x0f
#define COMMAND_ROBO 0x67 // All commands for Robo class devices
// Other Robo Commands (bit 7 set is not allowed here, because this is for MCSBUS_COMMAND)
#define COMMAND_ROBO_FIND_REFERENCE 0x0100
#define COMMAND_ROBO_MOVEABS 0x0200
#define COMMAND_ROBO_STOPMOVEMENT 0x0300
#define COMMAND_ROBO_XYPLANEPREPARATION 0x0400
#define COMMAND_ROBO_USB_INTERRUPT_BUFFER 0x0700
#define COMMAND_ROBO_AIRVALVE 0x0800
// Setting on pic32 general
#define COMMAND_ROBO_SETTINGS 0x0b00
#define COMMAND_ROBO_SETTINGS_INDEX_HWREVISION 0x00
#define COMMAND_ROBO_SETTINGS_INDEX_CONFIG 0x01
#define COMMAND_ROBO_SETTINGS_INDEX_MINPRESSUREWAITTIME 0x02
#define COMMAND_ROBO_SETTINGS_INDEX_MINPRESSURE 0x03
#define COMMAND_ROBO_SETTINGS_INDEX_MAXPRESSUREWAITTIME 0x04
#define COMMAND_ROBO_SETTINGS_INDEX_MINNOPRESSUREWAITTIME 0x05
#define COMMAND_ROBO_SETTINGS_INDEX_MAXNOPRESSURE 0x06
#define COMMAND_ROBO_SETTINGS_INDEX_MAXNOPRESSUREWAITTIME 0x07
#define COMMAND_ROBO_SETTINGS_INDEX_FIRMWAREVERSION 0x20 // Not implemented as command, eeprom pos
#define COMMAND_USER_SETTINGS 0x0C00
// Measured values on robo main
#define COMMAND_ROBO_MAIN_MEASURE 0x1000
#define COMMAND_ROBO_MAIN_MEASURE_VALUES (COMMAND_ROBO_MAIN_MEASURE | 0x01)
#define COMMAND_ROBO_MAIN_MEASURE_LIMITS (COMMAND_ROBO_MAIN_MEASURE | 0x02)
#define COMMAND_ROBO_MAIN_MEASURE_ERROR (COMMAND_ROBO_MAIN_MEASURE | 0x03)
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_ERROR 0x01
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_V_VALVES 0x02
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_V_RS485A 0x03
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_V_RS485B 0x04
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_V_AIRVALVE 0x05
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_I_AIRVALVE 0x06
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_V_12V 0x07
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_AIRPRESSURE 0x08
#define COMMAND_ROBO_MAIN_MEASURE_INDEX_V_5V 0x09
// Settings on pic32 for axes
#define COMMAND_ROBO_PARAMETER_AXIS 0x1100
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_SEARCHREFERENCEMETHOD 0x00
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_REFERENCEOFFSET 0x01
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_SEARCHREFERENCEFASTSPEED 0x02
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_SEARCHREFERENCEFASTACCEL 0x03
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_SEARCHREFERENCEFINESPEED 0x04
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_SEARCHREFERENCEFINEACCEL 0x05
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_SEARCHREFERENCEMOVEOUT 0x06
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_CONFIG 0x07
#define COMMAND_ROBO_PARAMETER_AXIS_INDEX_PHASE0 0x08 // internal usage
#define COMMAND_ROBO_GETPHASES 0x1200
#define COMMAND_ROBO_SEND_BROADCAST 0x1300
#define COMMAND_ROBO_FYI 0x1400
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_REGULATORONOFF 0x00
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_SOLLTEMP 0x01
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_PCOEFF 0x02
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_ICOEFF 0x03
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_MAXPOWER 0x04
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_PROGRAM_VALVE1 0x05
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_PROGRAM_VALVE2 0x06
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_PROGRAM_LENGTH 0x07
#define COMMAND_ROBO_FYI_PARAMETER_INDEX_PROGRAM_STATE 0x08
#define COMMAND_ROBO_MCSBUS 0x4000
#define COMMAND_FILTERFEEDBACK_CONTROL 0x68
// Use higher 8bit for commands
#define COMMAND_FILTERFEEDBACK_BASE 0x0000
#define COMMAND_FILTERFEEDBACK_SET_FILTERFEEDBACK 0x0000
#define COMMAND_FILTERFEEDBACK_GET_SAMPLETIMERCOUNT 0x0001
#define COMMAND_FILTERFEEDBACK_SET_DIGITALMAPPING 0x0002
#define COMMAND_FILTERFEEDBACK_SET_FILTER_PARAMETER 0x0100 // lower 8bit are filter number
#define COMMAND_FILTERFEEDBACK_SET_CHANNELFILTER 0x0200
#define COMMAND_FILTERFEEDBACK_SPIKEDETECTOR 0x0300
#define COMMAND_FILTERFEEDBACK_SET_NUMBER_OF_SPIKEDETECTOR_THRESHOLD 0x0300
#define COMMAND_FILTERFEEDBACK_SET_SPIKEDETECTOR_THRESHOLD 0x0301
#define COMMAND_FILTERFEEDBACK_SET_NUMBER_OF_SPIKEDETECTOR_SLOPE 0x0310
#define COMMAND_FILTERFEEDBACK_SET_SPIKEDETECTOR_SLOPE 0x0311
#define COMMAND_FILTERFEEDBACK_RATEDETECTOR 0x0400
#define COMMAND_FILTERFEEDBACK_SET_NUMBER_OF_RATECOUNTER 0x0400
#define COMMAND_FILTERFEEDBACK_SET_RATECOUNTER 0x0401
#define COMMAND_FILTERFEEDBACK_SET_NUMBER_OF_RATEDETECTOR 0x0410
#define COMMAND_FILTERFEEDBACK_SET_RATEDETECTOR 0x0411
#define COMMAND_FILTERFEEDBACK_LOGIC 0x0500
#define COMMAND_FILTERFEEDBACK_SET_NUMBER_OF_LOGIC 0x0500
#define COMMAND_FILTERFEEDBACK_SET_LOGIC 0x0501
#define COMMAND_FILTERFEEDBACK_TRIGGER 0x0600
#define COMMAND_FILTERFEEDBACK_SET_NUMBER_OF_TRIGGER 0x0600
#define COMMAND_FILTERFEEDBACK_SET_TRIGGER 0x0601
#define COMMAND_FILTERFEEDBACK_ANALOGSOURCE 0x0700 // lower 8bit are AnalogSource Enumeration (HS1, HS2, ...)
#define COMMAND_CLAMPAMP 0x69
#define COMMAND_CLAMPAMP_SIMULATION 0x0002
#define COMMAND_CLAMPAMP_RAMP 0x0011
#define COMMAND_CLAMPAMP_RECORDINGNUMBER 0x0012
#define COMMAND_CLAMPAMP_GET_SERIALNUMBER 0x0141
#define COMMAND_CLAMPAMP_GET_RESISTANCE_C 0x0156 // Resistance on current electrode
#define COMMAND_CLAMPAMP_GET_RESISTANCE_V 0x0157 // Resistance on voltage electrode
#define COMMAND_CLAMPAMP_GET_CAPACITY_C 0x0158 // Capacity on current electrode
#define COMMAND_CLAMPAMP_GET_CAPACITY_V 0x0159 // Capacity on voltage electrode
#define COMMAND_CLAMPAMP_GET_CAPACITY_X 0x015a // Capacity between current and voltage electrode
#define COMMAND_CLAMPAMP_GET_UV 0x015c // Voltage on voltage electrode
#define COMMAND_CLAMPAMP_GET_UC 0x015d // Voltage on current electrode
#define COMMAND_CLAMPAMP_GET_IC 0x015e // Current on current electrode
#define COMMAND_CLAMPAMP_RESTART 0x0160
#define COMMAND_CLAMPAMP_CONFIGURATION 0x0170
#define COMMAND_CLAMPAMP_UCLAMP 0x0171
#define COMMAND_CLAMPAMP_ICLAMP 0x0172
#define COMMAND_CLAMPAMP_PGAIN 0x0173
#define COMMAND_CLAMPAMP_IGAIN 0x0174
#define COMMAND_CLAMPAMP_FILTER 0x0175
#define COMMAND_CLAMPAMP_CONFIGURATIONBIT 0x0176 // For bitwise get or set of configuration (status)
#define COMMAND_CLAMPAMP_CROSSTALK 0x017A
#define COMMAND_CLAMPAMP_XGAIN 0x017B
#define COMMAND_CLAMPAMP_UV_OFS 0x017c
#define COMMAND_CLAMPAMP_UC_OFS 0x017d
#define COMMAND_CLAMPAMP_IC_OFS 0x017e
#define COMMAND_CLAMPAMP_CX_OPT 0x017f
#define COMMAND_CLAMPAMP_COMP 0x0180
#define COMMAND_CLAMPAMP_GET_NUV_MS 0x018C
#define COMMAND_CLAMPAMP_GET_NUC_MS 0x018D
#define COMMAND_CLAMPAMP_GET_NIC_MS 0x018E
#define COMMAND_CLAMPAMP_TABLE_DEF_BGN 0x0200
#define COMMAND_CLAMPAMP_TABLE_DEF_END 0x0201
#define COMMAND_CLAMPAMP_TABLE_WAIT 0x0202
#define COMMAND_CLAMPAMP_TABLE_RUN 0x0210
#define COMMAND_CLAMPAMP_TABLE_STOP 0x0211
#define COMMAND_CLAMPAMP_DOWNSAMPLE_FACTOR 0x0400
#define COMMAND_CLAMPAMP_FILTER_COEFFS 0x0401
#define COMMAND_CLAMPAMP_FILTERCHANNEL_MASK 0x0402
#define COMMAND_CLAMPAMP_USB_INTERRUPT_BUFFER 0x0700
#define COMMAND_CLAMPAMP_DIGOUT 0x0800
#define COMMAND_CLAMPAMP_EMU_ELECTRODE_RESIST 0x4001
#define COMMAND_CLAMPAMP_EMU_CELL_CAPACITY 0x4003
#define COMMAND_CLAMPAMP_EMU_CELL_RESIST 0x4004
#define COMMAND_CLAMPAMP_EMU_CELL_POTENTIAL 0x4005
#define COMMAND_CLAMPAMP_EMU_NOISE 0x4011
#define COMMAND_CLAMPAMP_SET_DISPLAY 0x5001
#define COMMAND_CLAMPAMP_SET_SCREEN 0x5002
#define COMMAND_CLAMPAMP_UPDATE_DISPLAY 0x5003
#define COMMAND_CLAMPAMP_GETSET_COMMAND 0xF000 // - 0xF0FF OR with the command to/from ClampAmp
#define COMMAND_CLAMPAMP_GETSET_COMMAND_MASK 0xFF00
#define COMMAND_CLAMPAMP_GETSET_VALUE_MASK 0x00FF
#define CLAMPAMP_INTERNAL_GETSET_DIGOUT 0x20 // Internal command in robo_omapl138 to get and set the digouts, this command is NOT send to the ClampAmp
#define CLAMPAMP_INTERNAL_GET_VERSION 0x40
#define CLAMPAMP_INTERNAL_GET_SER_NO 0x41
#define CLAMPAMP_INTERNAL_GET_FLASH_SRC 0x42
#define CLAMPAMP_INTERNAL_GET_FLASH_DST 0x43
#define CLAMPAMP_INTERNAL_GET_FLASH_LEN 0x44
#define CLAMPAMP_INTERNAL_GET_FLASH_STATUS 0x45
#define CLAMPAMP_INTERNAL_FLASH_WP_CLEAR 0x46
#define CLAMPAMP_INTERNAL_FLASH_WP_SET 0x47
#define CLAMPAMP_INTERNAL_FLASH_ERASE 0x48
#define CLAMPAMP_INTERNAL_FLASH_GET_ID 0x49
#define CLAMPAMP_INTERNAL_FLASH_COPY 0x4a
#define CLAMPAMP_INTERNAL_START_XMODEM 0x4e
#define CLAMPAMP_INTERNAL_GET_STATUS 0x50
#define CLAMPAMP_INTERNAL_GET_VOLTAGE_SP 0x51
#define CLAMPAMP_INTERNAL_GET_CURRENT_SP 0x52
#define CLAMPAMP_INTERNAL_GET_GAIN_P 0x53
#define CLAMPAMP_INTERNAL_GET_GAIN_I 0x54
#define CLAMPAMP_INTERNAL_GET_FILTER 0x55
#define CLAMPAMP_INTERNAL_GET_RESI_V 0x56
#define CLAMPAMP_INTERNAL_GET_RESI_C 0x57
#define CLAMPAMP_INTERNAL_GET_CAPA_V 0x58
#define CLAMPAMP_INTERNAL_GET_CAPA_C 0x59
#define CLAMPAMP_INTERNAL_GET_CAPA_X 0x5a
#define CLAMPAMP_INTERNAL_GET_GAIN_X 0x5b
#define CLAMPAMP_INTERNAL_GET_ADC_V 0x5c
#define CLAMPAMP_INTERNAL_GET_ADC_C 0x5d
#define CLAMPAMP_INTERNAL_GET_DAC_C 0x5e
#define CLAMPAMP_INTERNAL_RESTART 0x60
#define CLAMPAMP_INTERNAL_SET_FLASH_SRC 0x62
#define CLAMPAMP_INTERNAL_SET_FLASH_DST 0x63
#define CLAMPAMP_INTERNAL_SET_FLASH_LEN 0x64
#define CLAMPAMP_INTERNAL_SET_FLASH_STATUS 0x65
#define CLAMPAMP_INTERNAL_SET_STATUS 0x70
#define CLAMPAMP_INTERNAL_SET_VOLTAGE_SP 0x71
#define CLAMPAMP_INTERNAL_SET_CURRENT_SP 0x72
#define CLAMPAMP_INTERNAL_SET_GAIN_P 0x73
#define CLAMPAMP_INTERNAL_SET_GAIN_I 0x74
#define CLAMPAMP_INTERNAL_SET_FILTER 0x75
#define CLAMPAMP_INTERNAL_SET_CROSSTALK 0x7A
#define CLAMPAMP_INTERNAL_SET_GAIN_X 0x7B
#define CLAMPAMP_INTERNAL_SET_UV_OFS 0x7c
#define CLAMPAMP_INTERNAL_SET_UC_OFS 0x7d
#define CLAMPAMP_INTERNAL_SET_IC_OFS 0x7e
#define CLAMPAMP_INTERNAL_SET_CX_OPT 0x7f
#define CLAMPAMP_INTERNAL_GET_NUV_MS 0x8C
#define CLAMPAMP_INTERNAL_GET_NUC_MS 0x8D
#define CLAMPAMP_INTERNAL_GET_NIC_MS 0x8E
#define CLAMPAMP_INTERNAL_MAX_FIRMWARE_SIZE_WORDS 0x4000 // 16384 16 bit words == 32768 bytes
#define CLAMPAMP_INTERNAL_MAX_NACK_COUNT 8 // accept maximum 8 NACKs from ClampAmp
#define COMMAND_ACCESS_REGISTER_32 0x6A
#define COMMAND_MCSUSB_DEVELOP 0x70 /* to be used for development purposes to send all kind of data to the device */
#define GET_PRODUCT 0x71 /* used in STG200x and Cytoamp from linux */
#define GET_MANUFACTURER 0x72 /* used in STG200x and Cytoamp from linux */
#define GET_SERIALNUMBER 0x73 /* used in STG200x and Cytoamp from linux */
#define GET_BCDDEVICE 0x74 /* used in STG200x and Cytoamp from linux */
#define GET_BOARD_EEPROM 0x75 /* read content of Board EEPROM on STG200x */
#define GET_ASCII_VERSION 0x76 /* used in STG200x and Cytoamp from linux */
#define GET_BUILT_DATE 0x77 /* used in STG200x and Cytoamp from linux */
#define GET_BUILT_TIME 0x78 /* used in STG200x and Cytoamp from linux */
#define COMMAND_CYPRESS_FIRMWARE_LOAD 0xa0 /* Cypress build in Firmware load */
// Multiwell plate type definitions
#define HS_PLATETYPE_AUTO_DETECT 0xffffffff
#define HS_PLATETYPE_0 0
#define HS_PLATETYPE_6 6
#define HS_PLATETYPE_7 7
#define HS_PLATETYPE_33 33
#define HS_PLATETYPE_36 36
#define HS_PLATETYPE_40 40
#define HS_PLATETYPE_44 44
#define HS_PLATETYPE_48 48
#define HS_PLATETYPE_126 126
#define HS_PLATETYPE_193 193
#define HS_PLATETYPE_195 195
#define HS_PLATETYPE_224 224
#define HS_PLATETYPE_232 232
#define HS_PLATETYPE_244 244
#endif
/********************************************************************/
// -------------------------------------------------------------------------------------------
// -------------------------------------------------------------------------------------------
/*! Structure to define the memory layout of the current segment.
* Used by STG200x_SetCapacity()
*/
/* for the new STG, the capacity is passed as a pointer to uint32
with the following definition:
typedef struct new_capacity {
uint32_t channels; // number of channels we define
uint32_t channel_data[channels]; // one entry for each channel
uint32_t syncouts; // number of sync_out we define
uint32_t capacity_data[syncouts]; // one entry for each sync_out
} new_capacity;
*/
// -------------------------------------------------------------------------------------------
typedef struct programinfo_t {
char info[STG200x_PROGINFO_LENGTH] ;
} programinfo_t;
// -------------------------------------------------------------------------------------------
/*! Structure for version information of the STG.
* Used by STG200x_GetVersionInfo()
*
*/
typedef struct version {
char swmajor; /*!< major number of the software in STG firmware */
char swminor; /*!< minor number of the software in STG firmware */
char hwversion[MCS_USB_VERSION_LENGTH]; /*!< hardware revision of the STG as found in onboard EEPROM */
} version;
/*! Structure holds a bitmap of triggers which are to be enabled or disabled
* bit 0 to 3 : Trigger 0 to 3
* bit 4 : Front Side button
*/
// TMS320F6413 aligns uint32 to 4 byte boundaries, and we need more than 8 bits:
typedef struct new_endistrigger_t {
uint32_t triggermask; /*!< Bitmap of triggers to enable or disable */
uint32_t triggercount; /*!< Number of allowed trigger */
} new_endistrigger_t;
/*! Structure holds the segment number and
* a bitmap of triggers which are started or stopped.
* Used by STG200x_SegmentStart().
*
*/
typedef struct segmentstart_t {
uint32_t segment ; /*!< Segment number to switch to before starting the STG */
uint8_t triggermap ; /*!< Bitmap of triggers to start (see ::startstop) */
} segmentstart_t;
// -------------------------------------------------------------------------------------------
/*! Structure to define the connection between trigger,
* channels and syncout.
* Used by STG200x_SetupTrigger().
*/
typedef struct new_setuptrigger_t {
uint32_t channelmap;
uint32_t syncmap;
uint32_t repeat;
uint32_t digoutmap;
uint32_t autostart;
} new_setuptrigger_t;
/*! Structure which holds to current sweep and tigger count.
* Used by STG200x_GetSweepCount().
*/
typedef struct new_sweepcount_t {
uint32_t sweeps;
uint32_t triggers;
} new_sweepcount_t;
// -------------------------------------------------------------------------------------------
/*! Structure which holds data for channels and syncout
* Only used internally.
*/
#ifndef __C51__
typedef struct channeldata_t {
uint16_t command ; /*!< command (needed for bulk transfer) */
uint16_t channel ; /*!< channel for which the data is */
uint16_t len ; /*!< number of data points */
int16_t data[STG200x_DATA_BLOCKSIZE] ; /*!< list of data */
} channeldata_t;
#endif
#ifndef __C51__
typedef struct syncoutdata_t {
uint16_t command ; // command (needed for bulk out)
uint16_t syncout ; // syncout for which the data is
uint16_t len ; // number of data points
int16_t data[STG200x_DATA_BLOCKSIZE] ; // list of data
} syncoutdata_t;
#endif
// -------------------------------------------------------------------------------------------
typedef struct filtersetup {
int64_t B0; // Filter Coefficients for MEA System B0 in Q1.62
int64_t B1; // Filter Coefficients for MEA System B1 in Q1.62
int64_t A1; // Filter Coefficients for MEA System A1 in Q1.62
int64_t B2; // Filter Coefficients for MEA System B2 in Q1.62
int64_t A2; // Filter Coefficients for MEA System A2 in Q1.62
} filtersetup;
// -------------------------------------------------------------------------------------------
/*! Structure for information on STG resolution.
* Used by STG200x_GetIVal() and STG200x_GetUVal()
*
*/
typedef struct getval_t {
uint32_t range ; /*!< range of Voltage or Current outputs in mV and uA */
uint32_t res ; /*!< resolution of Voltage or Current outputs in mV and uA */
} getval_t;
// -------------------------------------------------------------------------------------------
/*! Structure for information on STG.
* Used by STG200x_GetIdent()
*
*/
typedef struct getident {
char buffer[MCS_USB_IDENT_LENGTH];
} getident;
// -------------------------------------------------------------------------------------------
/*! Structure to hold data to be sent to STG.
* Used by STG200x_UploadBlock()
*
*/
#ifndef __C51__
typedef struct upload_block {
uint16_t block_address ; /*!< Block destination address */
char data[MCS_USB_UL_BLOCKSIZE] ; /*!< list of data */
} upload_block;
#endif
// -------------------------------------------------------------------------------------------
//
// the flash_command structure must NOT be a multiple of 8 bytes
// STG200x Firmware revision ealier than 2.30 have a bug and
// can not handle transfers on EP0 with a packet size of multiple of 8
//
typedef struct flash_command {
uint32_t flash_addr;
uint32_t flash_size;
uint16_t dummy; // dummy entry to avoid multiple of 8 size, DO NOT DELETE!!
} flash_command;
/*! Structure to hold information about the current trigger status of the STG.
*
*/
typedef struct trigger_status_t {
uint8_t active_map; /*!< Bitmap of currently active tiggers */
uint8_t finished_map; /*!< Bitmap of finished trigger */
uint8_t armed_map; /*!< Bitmap of armed triggers (for single mode) */
uint8_t reserved2; /*!< reserved */
} trigger_status_t;
/*! Structure used to reset the ::trigger_status of the STG.
* Used by STG200x_ResetStatus().
*/
typedef struct reset_status_t {
uint8_t reserved0; /*!< reserved */
uint8_t finished_map; /*!< Bitmap of triggers for which status is to be reset to zero */
uint8_t reserved1; /*!< reserved */
uint8_t reserved2; /*!< reserved */
} reset_status_t;
typedef struct retrigger_mode_t {
uint32_t same_trigger;
uint32_t other_trigger;
} retrigger_mode_t;
/* data format in the user <-> kernel interface */
typedef struct dev_channeldata {
uint16_t channel[STG200x_NUM_CHANNELS];
uint8_t digout;
uint8_t syncout;
} dev_channeldata;
union device_data_record
{
struct {
uint8_t geraet [32];
uint8_t typ [32];
uint8_t firma [32];
uint8_t jahr [8];
uint8_t ser_no [32];
uint8_t hw_stand[32];
uint8_t sw_stand[32];
uint8_t gap1 [8];
uint8_t gap2 [16];
uint8_t baud;
uint8_t echo;
uint8_t debug;
uint8_t gap3 [5];
uint8_t gap4 [24];
int16_t offset_1;
int16_t offset_2;
int16_t offset_3;
int16_t offset_4;
int16_t offset_5;
int16_t offset_6;
int16_t offset_7;
int16_t offset_8;
uint16_t ures;
uint16_t ires;
uint16_t pres;
uint16_t urange;
uint16_t irange;
uint32_t prange;
uint8_t gap5[50];
uint8_t dig_init;
uint8_t trig_slope;
uint8_t sweep_mode;
uint8_t sync_mode;
uint8_t prgdat_valid;
uint8_t gap6[137];
uint8_t password[32];
uint8_t checksum;
uint8_t komplement;
} device_data;
unsigned char field[512];
};
union active_map_record {
struct {
uint8_t channel;
uint8_t syncout;
uint16_t digout;
} active_map;
uint32_t all;
};
typedef struct outputMap_t {
int32_t channel[STG200x_NUM_CHANNELS] ; /*!< Capacity in bytes for each channel */
} outputMap_t;
typedef struct s_uint16 {
uint16_t value;
} s_uint16;
typedef struct s_uint32 {
uint32_t value;
} s_uint32;
typedef struct s_2uint32 {
uint32_t value1;
uint32_t value2;
} s_2uint32;
typedef struct s_3uint32 {
uint32_t value1;
uint32_t value2;
uint32_t value3;
} s_3uint32;
typedef struct s_4uint32 {
uint32_t value1;
uint32_t value2;
uint32_t value3;
uint32_t value4;
} s_4uint32;
typedef struct s_1uint32_2uint16 {
uint32_t value1;
uint16_t value2;
uint16_t value3;
} s_1uint32_2uint16;
typedef struct s_int32 {
int32_t value;
} s_int32;
typedef struct s_2int32 {
int32_t value1;
int32_t value2;
} s_2int32;
typedef struct s_3int32 {
int32_t value1;
int32_t value2;
int32_t value3;
} s_3int32;
typedef struct s_4int32 {
int32_t value1;
int32_t value2;
int32_t value3;
int32_t value4;
} s_4int32;
typedef struct s_samplerate {
uint32_t rate; /* samplerate in Hz */
uint32_t oversample;
} s_samplerate;
typedef struct s_setaudio {
int32_t channel;
int32_t amplification;
} s_setaudio;
typedef struct s_channelmap{
uint8_t position;
uint8_t channel;
} s_channelmap;
typedef struct s_setdacvalue {
uint16_t channel;
int32_t value; // PJ: extended to 32bit, still compatible to old request, since lower 16 bit are at the same possition
} s_setdacvalue;
typedef struct s_setdacautocontrol {
uint16_t channel;
} s_setdacautocontrol;
typedef struct s_setpidparameter {
uint16_t channel; ///< channel
int16_t const_p; ///< P for PI control
int16_t const_i; ///< I for PI control
int16_t shift_p; ///< number of bits to shift P
int16_t shift_i;
} s_setpidparameter;
typedef struct s_rampstart {
int16_t channelmap;
} s_rampstart;
typedef struct s_sinestart {
int16_t channelmap;
} s_sinestart;
typedef struct s_patternliststart {
int16_t channelmap;
} s_patternliststart;
typedef struct s_setrampparameter {
uint16_t channel;
int16_t ramp_start;
int16_t ramp_min;
int16_t ramp_max;
int32_t ramp_slope;
int32_t ramp_pause;
int32_t ramp_slope2; // new for dotria, 2nd step
uint32_t ramp_samples; // number of samples after which a ramp should stop
} s_setrampparameter;
typedef struct s_setsineparameter {
uint16_t channel;
int16_t amplitude;
} s_setsineparameter;
typedef struct s_setpatternlistentry {
uint16_t channel;
uint16_t position;
uint32_t duration;
int32_t value;
} s_setpatternlistentry;
typedef struct s_setbathclamp {
uint16_t enable;
} s_setbathclamp;
typedef struct s_resetoffset {
uint16_t channel;
} s_resetoffset;
typedef struct s_setdacoffset {
uint16_t channel;
int16_t dac_offset;
} s_setdacoffset;
typedef struct s_setadcoffset {
uint16_t channel;
int32_t adc_offset;
} s_setadcoffset;
typedef struct s_setchannelswitch {
uint16_t channel;
uint16_t state;
} s_setchannelswitch;
typedef struct s_setfilterfeedback {
uint8_t on;
uint16_t digoutmask;
uint16_t diginmask;
} s_setfilterfeedback;
typedef struct s_ClampAmpRamp
{
int32_t ramp_start;
int32_t ramp_end;
uint32_t ramp_steps;
uint32_t ramp_mode; // 0 = Current Clamp; 1 = Voltage Clamp
} s_ClampAmpRamp;
typedef struct s_SpikeDetectorThreshold
{
unsigned short position;
unsigned short sourcechannel;
unsigned short resultchannel;
unsigned short trigger;
unsigned short totzeit;
int threshold1;
int threshold2;
short slope;
} s_SpikeDetectorThreshold;
typedef struct s_FilterAttributesOneSet
{
// Filter coeficients
uint64_t ULongA1;
uint64_t ULongA2;
uint64_t ULongB0;
uint64_t ULongB1;
uint64_t ULongB2;
// Filter infos
uint32_t CornerFrequency_mHz;
uint32_t Info;
uint32_t Order;
uint32_t FilterBand;
uint32_t FilterFamily;
uint32_t FilterType;
uint32_t FilterActive;
} s_FilterAttributesOneSet;
typedef struct s_FilterAttributesTwoSets
{
// Filter coeficients Filter 1
uint64_t ULongA1_1;
uint64_t ULongA2_1;
uint64_t ULongB0_1;
uint64_t ULongB1_1;
uint64_t ULongB2_1;
// Filter coeficients Filter 2
uint64_t ULongA1_2;
uint64_t ULongA2_2;
uint64_t ULongB0_2;
uint64_t ULongB1_2;
uint64_t ULongB2_2;
// Filter infos
uint32_t CornerFrequency_mHz;
uint32_t Info;
uint32_t Order;
uint32_t FilterBand;
uint32_t FilterFamily;
uint32_t FilterType;
uint32_t FilterActive;
} s_FilterAttributesTwoSets;
/*
typedef struct s_detectorstruct {
};
*/
#ifndef __C30
#ifndef __18CXX
#ifndef __TMS320C28XX__
#ifndef __TMS320C55XX__
#ifndef _TMS320C6X
#ifndef __C51__
#pragma pack()
#endif
#endif
#endif
#endif
#endif
#endif
#endif
/*! \endcond */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_memprot_L2.h
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_memprot_L2.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for MEMPROTL2
*/
#ifndef _CSLR_MEMPROT_L2_H_
#define _CSLR_MEMPROT_L2_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 MPFAR;
volatile Uint32 MPFSR;
volatile Uint32 MPFCR;
volatile Uint8 RSVD0[244];
volatile Uint32 MPLK0;
volatile Uint32 MPLK1;
volatile Uint32 MPLK2;
volatile Uint32 MPLK3;
volatile Uint32 MPLKCMD;
volatile Uint32 MPLKSTAT;
volatile Uint8 RSVD1[232];
volatile Uint32 MPPA[64];
} CSL_Memprotl2Regs;
typedef volatile CSL_Memprotl2Regs *CSL_Memprotl2RegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* MPFAR */
#define CSL_MEMPROTL2_MPFAR_ADDR_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL2_MPFAR_ADDR_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPFAR_ADDR_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPFAR_RESETVAL (0x00000000u)
/* MPFSR */
#define CSL_MEMPROTL2_MPFSR_FID_MASK (0x0000FE00u)
#define CSL_MEMPROTL2_MPFSR_FID_SHIFT (0x00000009u)
#define CSL_MEMPROTL2_MPFSR_FID_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPFSR_LOCAL_MASK (0x00000100u)
#define CSL_MEMPROTL2_MPFSR_LOCAL_SHIFT (0x00000008u)
#define CSL_MEMPROTL2_MPFSR_LOCAL_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPFSR_SR_MASK (0x00000020u)
#define CSL_MEMPROTL2_MPFSR_SR_SHIFT (0x00000005u)
#define CSL_MEMPROTL2_MPFSR_SR_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPFSR_SW_MASK (0x00000010u)
#define CSL_MEMPROTL2_MPFSR_SW_SHIFT (0x00000004u)
#define CSL_MEMPROTL2_MPFSR_SW_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPFSR_UR_MASK (0x00000004u)
#define CSL_MEMPROTL2_MPFSR_UR_SHIFT (0x00000002u)
#define CSL_MEMPROTL2_MPFSR_UR_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPFSR_UW_MASK (0x00000002u)
#define CSL_MEMPROTL2_MPFSR_UW_SHIFT (0x00000001u)
#define CSL_MEMPROTL2_MPFSR_UW_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPFSR_RESETVAL (0x00000000u)
/* MPFCR */
#define CSL_MEMPROTL2_MPFCR_MPFCLR_MASK (0x00000001u)
#define CSL_MEMPROTL2_MPFCR_MPFCLR_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPFCR_MPFCLR_RESETVAL (0x00000000u)
/*----MPFCLR Tokens----*/
#define CSL_MEMPROTL2_MPFCR_MPFCLR_CLEAR (0x00000001u)
#define CSL_MEMPROTL2_MPFCR_RESETVAL (0x00000000u)
/* MPLK0 */
#define CSL_MEMPROTL2_MPLK0_RESERVED_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL2_MPLK0_RESERVED_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPLK0_RESERVED_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPLK0_RESETVAL (0x00000000u)
/* MPLK1 */
#define CSL_MEMPROTL2_MPLK1_RESERVED_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL2_MPLK1_RESERVED_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPLK1_RESERVED_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPLK1_RESETVAL (0x00000000u)
/* MPLK2 */
#define CSL_MEMPROTL2_MPLK2_RESERVED_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL2_MPLK2_RESERVED_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPLK2_RESERVED_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPLK2_RESETVAL (0x00000000u)
/* MPLK3 */
#define CSL_MEMPROTL2_MPLK3_RESERVED_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL2_MPLK3_RESERVED_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPLK3_RESERVED_RESETVAL (0x00000000u)
#define CSL_MEMPROTL2_MPLK3_RESETVAL (0x00000000u)
/* MPLKCMD */
#define CSL_MEMPROTL2_MPLKCMD_KEYR_MASK (0x00000004u)
#define CSL_MEMPROTL2_MPLKCMD_KEYR_SHIFT (0x00000002u)
#define CSL_MEMPROTL2_MPLKCMD_KEYR_RESETVAL (0x00000000u)
/*----KEYR Tokens----*/
#define CSL_MEMPROTL2_MPLKCMD_KEYR_YES (0x00000001u)
#define CSL_MEMPROTL2_MPLKCMD_KEYR_NO (0x00000000u)
#define CSL_MEMPROTL2_MPLKCMD_LOCK_MASK (0x00000002u)
#define CSL_MEMPROTL2_MPLKCMD_LOCK_SHIFT (0x00000001u)
#define CSL_MEMPROTL2_MPLKCMD_LOCK_RESETVAL (0x00000000u)
/*----LOCK Tokens----*/
#define CSL_MEMPROTL2_MPLKCMD_LOCK_YES (0x00000001u)
#define CSL_MEMPROTL2_MPLKCMD_LOCK_NO (0x00000000u)
#define CSL_MEMPROTL2_MPLKCMD_UNLOCK_MASK (0x00000001u)
#define CSL_MEMPROTL2_MPLKCMD_UNLOCK_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPLKCMD_UNLOCK_RESETVAL (0x00000000u)
/*----UNLOCK Tokens----*/
#define CSL_MEMPROTL2_MPLKCMD_UNLOCK_YES (0x00000001u)
#define CSL_MEMPROTL2_MPLKCMD_UNLOCK_NO (0x00000000u)
#define CSL_MEMPROTL2_MPLKCMD_RESETVAL (0x00000000u)
/* MPLKSTAT */
#define CSL_MEMPROTL2_MPLKSTAT_LK_MASK (0x00000001u)
#define CSL_MEMPROTL2_MPLKSTAT_LK_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPLKSTAT_LK_RESETVAL (0x00000000u)
/*----LK Tokens----*/
#define CSL_MEMPROTL2_MPLKSTAT_LK_YES (0x00000001u)
#define CSL_MEMPROTL2_MPLKSTAT_LK_NO (0x00000000u)
#define CSL_MEMPROTL2_MPLKSTAT_RESETVAL (0x00000000u)
/* MPPA */
#define CSL_MEMPROTL2_MPPA_AID5_MASK (0x00008000u)
#define CSL_MEMPROTL2_MPPA_AID5_SHIFT (0x0000000Fu)
#define CSL_MEMPROTL2_MPPA_AID5_RESETVAL (0x00000001u)
/*----AID5 Tokens----*/
#define CSL_MEMPROTL2_MPPA_AID5_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_AID5_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_AID4_MASK (0x00004000u)
#define CSL_MEMPROTL2_MPPA_AID4_SHIFT (0x0000000Eu)
#define CSL_MEMPROTL2_MPPA_AID4_RESETVAL (0x00000001u)
/*----AID4 Tokens----*/
#define CSL_MEMPROTL2_MPPA_AID4_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_AID4_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_AID3_MASK (0x00002000u)
#define CSL_MEMPROTL2_MPPA_AID3_SHIFT (0x0000000Du)
#define CSL_MEMPROTL2_MPPA_AID3_RESETVAL (0x00000001u)
/*----AID3 Tokens----*/
#define CSL_MEMPROTL2_MPPA_AID3_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_AID3_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_AID2_MASK (0x00001000u)
#define CSL_MEMPROTL2_MPPA_AID2_SHIFT (0x0000000Cu)
#define CSL_MEMPROTL2_MPPA_AID2_RESETVAL (0x00000001u)
/*----AID2 Tokens----*/
#define CSL_MEMPROTL2_MPPA_AID2_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_AID2_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_AID1_MASK (0x00000800u)
#define CSL_MEMPROTL2_MPPA_AID1_SHIFT (0x0000000Bu)
#define CSL_MEMPROTL2_MPPA_AID1_RESETVAL (0x00000001u)
/*----AID1 Tokens----*/
#define CSL_MEMPROTL2_MPPA_AID1_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_AID1_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_AID0_MASK (0x00000400u)
#define CSL_MEMPROTL2_MPPA_AID0_SHIFT (0x0000000Au)
#define CSL_MEMPROTL2_MPPA_AID0_RESETVAL (0x00000001u)
/*----AID0 Tokens----*/
#define CSL_MEMPROTL2_MPPA_AID0_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_AID0_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_ADX_MASK (0x00000200u)
#define CSL_MEMPROTL2_MPPA_ADX_SHIFT (0x00000009u)
#define CSL_MEMPROTL2_MPPA_ADX_RESETVAL (0x00000001u)
/*----ADX Tokens----*/
#define CSL_MEMPROTL2_MPPA_ADX_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_ADX_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_LOCAL_MASK (0x00000100u)
#define CSL_MEMPROTL2_MPPA_LOCAL_SHIFT (0x00000008u)
#define CSL_MEMPROTL2_MPPA_LOCAL_RESETVAL (0x00000001u)
/*----LOCAL Tokens----*/
#define CSL_MEMPROTL2_MPPA_LOCAL_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_LOCAL_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_SR_MASK (0x00000020u)
#define CSL_MEMPROTL2_MPPA_SR_SHIFT (0x00000005u)
#define CSL_MEMPROTL2_MPPA_SR_RESETVAL (0x00000001u)
/*----SR Tokens----*/
#define CSL_MEMPROTL2_MPPA_SR_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_SR_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_SW_MASK (0x00000010u)
#define CSL_MEMPROTL2_MPPA_SW_SHIFT (0x00000004u)
#define CSL_MEMPROTL2_MPPA_SW_RESETVAL (0x00000001u)
/*----SW Tokens----*/
#define CSL_MEMPROTL2_MPPA_SW_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_SW_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_SX_MASK (0x00000008u)
#define CSL_MEMPROTL2_MPPA_SX_SHIFT (0x00000003u)
#define CSL_MEMPROTL2_MPPA_SX_RESETVAL (0x00000001u)
/*----SX Tokens----*/
#define CSL_MEMPROTL2_MPPA_SX_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_SX_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_UR_MASK (0x00000004u)
#define CSL_MEMPROTL2_MPPA_UR_SHIFT (0x00000002u)
#define CSL_MEMPROTL2_MPPA_UR_RESETVAL (0x00000001u)
/*----UR Tokens----*/
#define CSL_MEMPROTL2_MPPA_UR_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_UR_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_UW_MASK (0x00000002u)
#define CSL_MEMPROTL2_MPPA_UW_SHIFT (0x00000001u)
#define CSL_MEMPROTL2_MPPA_UW_RESETVAL (0x00000001u)
/*----UW Tokens----*/
#define CSL_MEMPROTL2_MPPA_UW_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_UW_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_UX_MASK (0x00000001u)
#define CSL_MEMPROTL2_MPPA_UX_SHIFT (0x00000000u)
#define CSL_MEMPROTL2_MPPA_UX_RESETVAL (0x00000001u)
/*----UX Tokens----*/
#define CSL_MEMPROTL2_MPPA_UX_NO (0x00000000u)
#define CSL_MEMPROTL2_MPPA_UX_YES (0x00000001u)
#define CSL_MEMPROTL2_MPPA_RESETVAL (0x0000FFFFu)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcOpen.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** @file csl_pllcOpen.c
*
* @brief File for functional layer of CSL API @a CSL_pllcOpen()
*
* Path: \(CSLPATH)\src\pllc
*
*/
/* ============================================================================
* Revision History
* ===============
* 10-Feb-2004 kpn CSL3X Upgradation.
* 25-Aug-2005 Tej Modified for c64xx support.
* ============================================================================
*/
#include <csl_pllc.h>
/** ============================================================================
* @n@b CSL_pllcOpen
*
* @b Description
* @n This function returns the handle to the PLLC
* instance. This handle is passed to all other CSL APIs.
*
* @b Arguments
* @verbatim
pPllcObj Pointer to pllc object.
pllcNum Instance of pllc CSL to be opened.
pPllcParam Module specific parameters.
status Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_PllcHandle
* @n Valid pllc handle will be returned if
* status value is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK - Valid pllc handle is returned
* @li CSL_ESYS_FAIL - The pllc instance is invalid
* @li CSL_ESYS_INVPARAMS - Invalid parameter
* @n 2. PLLC object structure is populated
*
* @b Modifies
* @n 1. The status variable
* @n 2. PLLC object structure
*
* @b Example
* @verbatim
CSL_status status;
CSL_PllcObj pllcObj;
CSL_PllcHandle hPllc;
...
hPllc = CSL_pllcOpen(&pllcObj, CSL_PLLC_1, NULL, &status);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pllcOpen, ".text:csl_section:pllc");
CSL_PllcHandle CSL_pllcOpen (
CSL_PllcObj *pPllcObj,
CSL_InstNum pllcNum,
CSL_PllcParam *pPllcParam,
CSL_Status *pStatus
)
{
CSL_Status status;
CSL_PllcHandle hPllc = NULL;
CSL_PllcBaseAddress baseAddress;
if (pStatus == NULL) {
/* do nothing */
}
else if (pPllcObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
status = CSL_pllcGetBaseAddress (pllcNum, pPllcParam, &baseAddress);
if (status == CSL_SOK) {
pPllcObj->regs = baseAddress.regs;
pPllcObj->pllcNum = (CSL_InstNum) pllcNum;
hPllc = (CSL_PllcHandle) pPllcObj;
}
else {
pPllcObj->regs = (CSL_PllcRegsOvly)NULL;
pPllcObj->pllcNum = (CSL_InstNum)-1;
}
*pStatus = status;
}
return hPllc;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspHwSetup.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_mcbspHwSetup.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API CSL_mcbspHwSetup()
*
*/
/* ============================================================================
* Revision History
* ================
* July 04, 2005 ds - Removed support for DX Mode. Hence removed
* dxState from CSL_McbspHwSetup
* - Removed support for enhanced sample clock mode
* Feb 02 , 2006 ds - Supported the Transmit & Receive Int Mode
* ============================================================================
*/
#include <csl_mcbsp.h>
/** ============================================================================
* @n@b CSL_mcbspHwSetup
*
* @b Description
* @n Configures the MCBSP using the values passed in the setup structure.
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
setup Pointer to setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hwsetup successful
* @li CSL_ESYS_INVPARAMS - The param passed is invalid
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before CSL_mcbspHwSetup() can be called.
*
* <b> Post Condition </b>
* @n Mcbsp registers are configured according to the hardware setup
* parameters
*
* @b Modifies
* @n MCBSP registers
*
* @b Example
* @verbatim
CSL_mcbspHandle hMcbsp;
CSL_McbspObj mcbspObj;
CSL_McbspHwSetup hwSetup = CSL_MCBSP_HWSETUP_DEFAULTS;
CSL_Status status;
// Init Successfully done
CSL_mcbspInit (NULL);
// Open Successfully done
hMcbsp = CSL_mcbspOpen (&mcbspObj, CSL_MCBSP_0, NULL, &status);
CSL_mcbspHwSetup(hMcbsp, &hwSetup);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_mcbspHwSetup, ".text:csl_section:mcbsp");
CSL_Status CSL_mcbspHwSetup (
CSL_McbspHandle hMcbsp,
CSL_McbspHwSetup *setup
)
{
CSL_Status status = CSL_SOK;
CSL_McbspRegsOvly mcbspRegs = hMcbsp->regs;
if(setup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else if (hMcbsp == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else {
/* Set Emulation Mode Configuration */
CSL_FINS(mcbspRegs->SPCR, MCBSP_SPCR_SOFT, setup->emumode );
CSL_FINS(mcbspRegs->SPCR, MCBSP_SPCR_FREE, setup->emumode >> 1);
/*Clock and Frame Sync Configuration*/
if(setup->clkset != NULL ) {
CSL_McbspClkSetup clkCfg = *(setup->clkset);
mcbspRegs->PCR = CSL_FMK( MCBSP_PCR_FSRM, clkCfg.frmSyncRxMode)
| CSL_FMK( MCBSP_PCR_FSXM, clkCfg.frmSyncTxMode)
| CSL_FMK( MCBSP_PCR_FSRP, clkCfg.frmSyncRxPolarity)
| CSL_FMK( MCBSP_PCR_FSXP, clkCfg.frmSyncTxPolarity)
| CSL_FMK( MCBSP_PCR_CLKRM, clkCfg.clkRxMode )
| CSL_FMK( MCBSP_PCR_CLKXM, clkCfg.clkTxMode )
| CSL_FMK( MCBSP_PCR_CLKRP, clkCfg.clkRxPolarity )
| CSL_FMK( MCBSP_PCR_CLKXP, clkCfg.clkTxPolarity);
mcbspRegs->SRGR = CSL_FMK( MCBSP_SRGR_FWID, clkCfg.srgFrmPulseWidth)
| CSL_FMK( MCBSP_SRGR_CLKGDV, clkCfg.srgClkDivide)
| CSL_FMK( MCBSP_SRGR_FPER, clkCfg.srgFrmPeriod)
| CSL_FMK( MCBSP_SRGR_GSYNC, clkCfg.srgClkSync)
| CSL_FMK( MCBSP_SRGR_CLKSM, clkCfg.srgInputClkMode)
| CSL_FMK( MCBSP_SRGR_CLKSP, clkCfg.srgClkPolarity )
| CSL_FMK( MCBSP_SRGR_FSGM, clkCfg.srgTxFrmSyncMode);
}
/*McBSP Global Configuration*/
if(setup->global!= NULL) {
CSL_McbspGlobalSetup globalCfg = *(setup->global);
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_DLB, globalCfg.dlbMode );
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_CLKSTP, globalCfg.clkStopMode);
CSL_FINS( mcbspRegs->PCR, MCBSP_PCR_RIOEN, globalCfg.ioEnableMode & 0x1);
CSL_FINS( mcbspRegs->PCR, MCBSP_PCR_XIOEN, globalCfg.ioEnableMode >> 1 );
}
/*Transmitter Configuration*/
if(setup->txdataset != NULL) {
CSL_McbspDataSetup transmitterCfg = *(setup->txdataset);
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_XRST, 0 );
mcbspRegs->XCR = CSL_FMK( MCBSP_XCR_XWDLEN1, transmitterCfg.wordLength1)
| CSL_FMK( MCBSP_XCR_XWDREVRS,transmitterCfg.wordReverse)
| CSL_FMK( MCBSP_XCR_XPHASE, transmitterCfg.numPhases )
| CSL_FMK( MCBSP_XCR_XWDLEN2, transmitterCfg.wordLength2)
| CSL_FMK( MCBSP_XCR_XFRLEN2,(transmitterCfg.frmLength2 - 1))
| CSL_FMK( MCBSP_XCR_XFIG, transmitterCfg.frmSyncIgn )
| CSL_FMK( MCBSP_XCR_XCOMPAND, transmitterCfg.compand )
| CSL_FMK( MCBSP_XCR_XDATDLY, transmitterCfg.dataDelay );
CSL_FINS(mcbspRegs->XCR, MCBSP_XCR_XFRLEN1, \
(transmitterCfg.frmLength1 - 1));
CSL_FINS(mcbspRegs->SPCR, MCBSP_SPCR_DXENA, \
transmitterCfg.rjust_dxenable);
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_XINTM, transmitterCfg.intEvent );
}
/*Receiver Configuration*/
if(setup->rxdataset != NULL) {
CSL_McbspDataSetup receiverCfg = *(setup->rxdataset);
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_RRST, 0 );
mcbspRegs->RCR = CSL_FMK( MCBSP_RCR_RWDLEN1, receiverCfg.wordLength1 )
| CSL_FMK( MCBSP_RCR_RWDREVRS, receiverCfg.wordReverse)
| CSL_FMK( MCBSP_RCR_RPHASE, receiverCfg.numPhases )
| CSL_FMK( MCBSP_RCR_RWDLEN2, receiverCfg.wordLength2 )
| CSL_FMK( MCBSP_RCR_RFRLEN2, (receiverCfg.frmLength2 - 1))
| CSL_FMK( MCBSP_RCR_RFIG, receiverCfg.frmSyncIgn )
| CSL_FMK( MCBSP_RCR_RCOMPAND, receiverCfg.compand )
| CSL_FMK( MCBSP_RCR_RDATDLY, receiverCfg.dataDelay );
CSL_FINS(mcbspRegs->RCR, MCBSP_RCR_RFRLEN1, \
(receiverCfg.frmLength1 - 1) );
CSL_FINS(mcbspRegs->SPCR, MCBSP_SPCR_RJUST, \
receiverCfg.rjust_dxenable );
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_RINTM, receiverCfg.intEvent);
}
/* Multi Channel Configuration */
if(setup->mulCh != NULL) {
CSL_McbspMulChSetup multiChCfg = *(setup->mulCh);
mcbspRegs->MCR = CSL_FMK( MCBSP_MCR_RMCM, multiChCfg.rxMulChSel)
| CSL_FMK( MCBSP_MCR_RMCME, multiChCfg.rxPartition)
| CSL_FMK( MCBSP_MCR_RPABLK, multiChCfg.rxPartABlk)
| CSL_FMK( MCBSP_MCR_RPBBLK, multiChCfg.rxPartBBlk)
| CSL_FMK( MCBSP_MCR_XMCM, multiChCfg.txMulChSel)
| CSL_FMK( MCBSP_MCR_XMCME, multiChCfg.txPartition)
| CSL_FMK( MCBSP_MCR_XPABLK, multiChCfg.txPartABlk)
| CSL_FMK( MCBSP_MCR_XPBBLK, multiChCfg.txPartBBlk);
}
}
return(status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrHwSetupRaw.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/timer/csl_tmrHwSetupRaw.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ===========================================================================
* @file csl_tmrHwSetupRaw.c
*
* @brief File for functional layer of CSL API CSL_tmrHwSetupRaw()
*
* @path $(CSLPATH)\src\timer
*
* @desc The CSL_tmrHwSetupRaw() function definition & it's associated
* functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 1-Sept-2004 HMM File Created.
* 29-Jul-2005 PSK Updated changes acooriding to revised timer spec. The number
* convention TIM12, TIM34 are changed to TIMLO and TIMHI.
* 03-Apr-2006 ds Removed "EMUMGT_CLKSPD" configuration
* ============================================================================
*/
#include <csl_tmr.h>
#include <csl_tmrAux.h>
/** ============================================================================
* @n@b CSL_tmrHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the config data structure.
*
* @b Arguments
* @verbatim
hTmr Pointer to the object that holds reference to the
instance of TIMER requested after the call
config Pointer to the config structure containing the
device register values
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration structure
* pointer is not properly
* initialized
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The registers of the specified timer instance will be setup according
* to the values passed through the config structure
*
* @b Modifies
* @n Hardware registers of the specified timer instance
*
* @b Example
* @verbatim
CSL_TmrHandle hTmr;
CSL_TmrConfig config = CSL_TMR_CONFIG_DEFAULTS;
CSL_Status status;
...
status = CSL_tmrHwSetupRaw(hTmr, &config);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION(CSL_tmrHwSetupRaw, ".text:csl_section:tmr");
CSL_Status CSL_tmrHwSetupRaw (
CSL_TmrHandle hTmr,
CSL_TmrConfig *config
)
{
CSL_Status status = CSL_SOK ;
if (hTmr == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (config == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
/* General purpose timer Timer Counter Register Low */
hTmr->regs->TIMLO = config->TIMLO;
/* General purpose timer Timer Counter Register High */
hTmr->regs->TIMHI = config->TIMHI;
/* General purpose timer Timer Period Register Low */
hTmr->regs->PRDLO = config->PRDLO;
/* General purpose timer Timer Period Register High */
hTmr->regs->PRDHI = config->PRDHI;
/* General purpose timer Timer Control Register */
hTmr->regs->TCR = config->TCR;
/* General purpose timer Timer Global Control Register */
hTmr->regs->TGCR = config->TGCR;
/* General purpose timer General purpose Timer Control Register */
hTmr->regs->WDTCR = config->WDTCR;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_tcp2.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_tcp2.h
*
* @path $(CSLPATH)\tcp2\inc
*
* @desc API header file for TCP2 CSL
*
*/
/* =============================================================================
* Revision History
* ===============
* 15-Mar-2005 sd File Created.
* 21-Jul-2005 sd Updated for the requirement changes
* 15-Sep-2005 sd Changed TCP to TCP2 in all the names
* 30-Jan-2006 sd Minor changes in the descriptions
* =============================================================================
*/
#ifndef _CSL_TCP2_H_
#define _CSL_TCP2_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <tistdtypes.h>
#include <cslr_tcp2.h>
#include <soc.h>
/****************************************\
* TCP global typedef declarations
\****************************************/
/** Address of the TCP2 registers */
#define tcp2Regs ((CSL_Tcp2Regs*)CSL_TCP2_0_REGS)
/** Address of the configuration registers */
#define tcp2CfgRegs ((CSL_Tcp2CfgRegs*)CSL_TCP2_CFG_REGS)
/****************************************\
* TCP global defines
\****************************************/
/** define for TCP2 code rate 3/4 */
#define TCP2_RATE_3_4 CSL_TCP2_TCPIC0_RATE_3_4
/** define for TCP2 code rate 1/2 */
#define TCP2_RATE_1_2 CSL_TCP2_TCPIC0_RATE_1_2
/** define for TCP2 code rate 1/3 */
#define TCP2_RATE_1_3 CSL_TCP2_TCPIC0_RATE_1_3
/** define for TCP2 code rate 1/4 */
#define TCP2_RATE_1_4 CSL_TCP2_TCPIC0_RATE_1_4
/** define for TCP2 code rate 1/5 */
#define TCP2_RATE_1_5 CSL_TCP2_TCPIC0_RATE_1_5
/** Number of sliding windows per block is <= 128 */
#define TCP2_SW_LEQ128 CSL_TCP2_TCPIC0_NUMSW_LEQ_128
/** Number of sliding windows per block is > 128 */
#define TCP2_SW_G128 CSL_TCP2_TCPIC0_NUMSW_G_128
/** TCP stand alone mode */
#define TCP2_MODE_SA CSL_TCP2_TCPIC0_OPMOD_SA
/** TCP shared processing, first sub frame */
#define TCP2_FIRST_SF CSL_TCP2_TCPIC0_OPMOD_SP_FF
/** TCP shared processing, middle sub frame */
#define TCP2_MIDDLE_SF CSL_TCP2_TCPIC0_OPMOD_SP_MF
/** TCP shared processing, last sub frame */
#define TCP2_LAST_SF CSL_TCP2_TCPIC0_OPMOD_SP_LF
/** TCP shared processing mode */
#define TCP2_MODE_SP 1
/** Decoder standard 3GPP */
#define TCP2_STANDARD_3GPP 0
/** Decoder standard IS2000 */
#define TCP2_STANDARD_IS2000 1
/** TCP maximum reliability length */
#define TCP2_RLEN_MAX 128
/** TCP maximum sub frame size */
#define TCP2_SUB_FRAME_SIZE_MAX 20480
/** TCP maximum standalone mode frame size */
#define TCP2_FLEN_MAX 20730
/** TCP shared processing non interleaved MAP*/
#define TCP2_MAP_MAP1 0
/** TCP shared processing interleaved MAP*/
#define TCP2_MAP_MAP2 1
/* typedefs */
/** This data type is used to define the TCP standards */
typedef Uint8 TCP2_Standard;
/** This data type is used to define the TCP mode
* (stand alone or shared processing)
*/
typedef Uint8 TCP2_Mode;
/** This data type is used to define the TCP map (1,2) */
typedef Uint8 TCP2_Map;
/** This data type is used to define the number of sliding
* windows per block
*/
typedef Uint8 TCP2_NumSW;
/** This data type is used to define the TCP code rates
* (1/2, 1/3, 1/4, 1/5, 3/4)
*/
typedef Uint8 TCP2_Rate;
/** This data type is used to represent the TCP data */
typedef Uint8 TCP2_UserData;
/** This data type is used to represent the TCP tail data */
typedef Int8 TCP2_TailData;
/** This data type is used to represent the TCP extrinsic data */
typedef Uint8 TCP2_ExtrinsicData;
/** This data type is used to represent the TCP input data*/
typedef Uint32 TCP2_InputData;
/** Enum for the input sign values */
typedef enum {
/** Multiply the channel input by +1 */
TCP2_INPUT_SIGN_POSITIVE = CSL_TCP2_TCPIC3_INPUTSIGN_POSITIVE,
/** Multiply the channel input by -1 */
TCP2_INPUT_SIGN_NEGATIVE = CSL_TCP2_TCPIC3_INPUTSIGN_NEGATIVE
}TCP2_InputSign;
/** Enum for the output order values */
typedef enum {
/** Order of the bits in the output data is 0-31 */
TCP2_OUT_ORDER_0_31 = CSL_TCP2_TCPIC3_OUTORDER_0_31,
/** Order of the bits in the output data is 31-0 */
TCP2_OUT_ORDER_31_0 = CSL_TCP2_TCPIC3_OUTORDER_31_0
}TCP2_OutputOrder;
/** The TCP input configuration structure holds all the
* configuration values that are to be transferred to the
* TCP via the EDMA
*/
typedef struct {
Uint32 ic0; /**< TCP input configuration word 0 value */
Uint32 ic1; /**< TCP input configuration word 1 value */
Uint32 ic2; /**< TCP input configuration word 2 value */
Uint32 ic3; /**< TCP input configuration word 3 value */
Uint32 ic4; /**< TCP input configuration word 4 value */
Uint32 ic5; /**< TCP input configuration word 5 value */
Uint32 ic6; /**< TCP input configuration word 6 value */
Uint32 ic7; /**< TCP input configuration word 7 value */
Uint32 ic8; /**< TCP input configuration word 8 value */
Uint32 ic9; /**< TCP input configuration word 9 value */
Uint32 ic10; /**< TCP input configuration word 10 value */
Uint32 ic11; /**< TCP input configuration word 11 value */
Uint32 ic12; /**< TCP input configuration word 12 value */
Uint32 ic13; /**< TCP input configuration word 13 value */
Uint32 ic14; /**< TCP input configuration word 14 value */
Uint32 ic15; /**< TCP input configuration word 15 value */
} TCP2_ConfigIc;
/** The TCP parameters structure holds all the information concerning
* the user channel. These values are used to generate the appropriate
* input configuration values for the TCP.
*/
typedef struct {
TCP2_Standard standard; /**< TCP standard */
/* IC0 parameters */
TCP2_Mode mode; /**< TCP mode */
TCP2_Map map; /**< TCP shared processing MAP */
TCP2_Rate rate; /**< TCP code rate */
TCP2_NumSW numSlideWin; /**< Number of sliding window per sub block */
Uint32 intFlag; /**< Interleaver write flag */
Uint32 outParmFlag; /**< Output parameters read flag */
Uint32 frameLen; /**< Frame length */
/* IC1 parameters */
Uint32 relLen; /**< Reliability length */
/* IC2 parameters */
Uint32 prologSize; /**< Prolog length */
Uint32 numSubBlock; /**< Number of sub blocks */
Uint32 maxIter; /**< Maximum number of iterations */
Uint32 snr; /**< SNR threshold used for stopping test */
/* IC3 parameters */
Bool maxStarEn; /**< Enable/disable the max star */
Bool prologRedEn; /**< Enable/disable the prolog reduction */
Uint8 minIter; /**< Minimum number of iterations to be executed */
TCP2_InputSign inputSign;/**< The sign of the input data (+/-) */
TCP2_OutputOrder outputOrder; /**< The bit ordering of the output data */
/* IC4 parameters */
Uint8 numCrcPass; /**< Number of passed CRC iterations required
* before decoder termination
*/
Uint8 crcLen; /**< CRC polynomial length */
/* IC5 parameters */
Uint32 crcPoly; /**< CRC polynomial */
/* IC12 - IC15 parameters */
Uint8 extrScaling [16]; /**< Extrinsic scaling factors */
} TCP2_Params;
/** The TCP base parameters structure is used to set up the TCP programmable
* parameters. You create the object and pass it to the TCP2_genParams()
* function which returns the TCP2_Params structure.
*/
typedef struct {
TCP2_Standard standard; /**< TCP decoder standards */
TCP2_Rate rate; /**< TCP code rate */
TCP2_Map map; /**< TCP shared processing MAP */
Uint32 intFlag; /**< Interleaver write flag */
Uint32 outParmFlag; /**< Output parameters read flag */
Uint32 frameLen; /**< Frame length */
Uint32 prologSize; /**< Prolog length */
Uint32 maxIter; /**< Maximum number of iterations */
Uint32 snr; /**< SNR threshold used for stopping test */
Bool maxStarEn; /**< Enable/disable the max star */
Bool prologRedEn; /**< Enable/disable the prolog reduction */
Uint8 minIter; /**< Minimum number of iterations to be executed*/
TCP2_InputSign inputSign;/**< The sign of the input data (+/-) */
TCP2_OutputOrder outputOrder; /**< The bit ordering of the output data */
Uint8 numCrcPass; /**< Number of passed CRC iterations required
* before decoder termination
*/
Uint8 crcLen; /**< CRC polynomial length */
Uint32 crcPoly; /**< CRC polynomial */
Uint8 extrScaling [16]; /**< Extrinsic scaling factors */
} TCP2_BaseParams;
/* function declarations */
/* ============================================================================
* @n@b TCP2_setParams
*
* @b Description
* @n This function sets up the TCP2 input configuration parameters in the
* TCP2_ConfigIc structure. The configuration values are passed in the
* configParms input argument.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
configIc Pointer to the TCP2_ConfigIc structure to be filled.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
TCP2_ConfigIc *configIc;
...
TCP2_setParams(configParms, configIc);
@endverbatim
* ===========================================================================
*/
void TCP2_setParams (
TCP2_Params *restrict configParms,
TCP2_ConfigIc *restrict configIc
);
/* ============================================================================
* @n@b TCP2_tailConfig
*
* @b Description
* @n This function generates the input control values IC6-IC11 based on the
* processing to be performed by the TCP. These values consist of the tail
* data following the systematics and parities data. This function
* calls specific tail generation functions depending on the
* standard followed.
*
* @b Arguments
@verbatim
standard 3G standard to be decoded.
mode TCP processing mode (SA or SP)
map TCP shared processing MAP
rate Code rate of the TCP
xabData Pointer to the tail data
configIc Pointer to the TCP2_ConfigIc structure to be filled.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
TCP2_ConfigIc *configIc;
TCP2_UserData *xabData = &userData[fraemLen];
...
TCP2_tailConfig (configParms->mode, configParms->map,
configParms->standard, configParms->rate,
userData, configIc);
@endverbatim
* ===========================================================================
*/
void TCP2_tailConfig (
TCP2_Standard standard,
TCP2_Mode mode,
TCP2_Map map,
TCP2_Rate rate,
TCP2_TailData *restrict tailData,
TCP2_ConfigIc *restrict configIc
);
/* ============================================================================
* @n@b TCP2_genIc
*
* @b Description
* @n This function sets up the TCP2 input configuration parameters in the
* TCP2_ConfigIc structure. The configuration values are passed in the
* configParms input argument.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
tailData Tail data
configIc Pointer to the TCP2_ConfigIc structure to be filled.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
extern TCP2_UserData *userData;
TCP2_BaseParams configBase;
TCP2_Params configParams;
TCP2_TailData *xabData;
Uint32 frameLen = 40;
xabData = &userData [frameLen];
// assign the configuration parameters
configBase.frameLen = frameLen;
configBase.inputSign = TCP2_INPUT_SIGN_POSITIVE;
configBase.intFlag = 1;
configBase.maxIter = 8;
configBase.maxStarEn = TRUE;
configBase.standard = TCP2_STANDARD_3GPP;
configBase.crcLen = 0;
configBase.crcPoly = 0;
configBase.minIter = 1;
configBase.numCrcPass = 1;
configBase.outParmFlag = 0;
configBase.outputOrder = TCP2_OUT_ORDER_0_31;
configBase.prologRedEn = FALSE;
configBase.prologSize = 24;
configBase.rate = TCP2_RATE_1_3;
configBase.snr = 0;
for (cnt = 0; cnt < 16; cnt++)
configBase.extrScaling [cnt] = 32;
// setup the TCP configuration registers parmeters
TCP2_genParams (&configBase, &configParams);
// generate the configuration register values
TCP2_genIc (&configParams, xabData, &configIc);
@endverbatim
* ===========================================================================
*/
void TCP2_genIc (
TCP2_Params *restrict configParms,
TCP2_TailData *restrict tailData,
TCP2_ConfigIc *restrict configIc
);
/* ============================================================================
* @n@b TCP2_genParams
*
* @b Description
* @n This function copies the basic parameters, to the configParams
* parameters structure.
*
* @b Arguments
@verbatim
configBase Pointer to the TCP2_BaseParams structure
configParams Pointer to the TCP configuration parameters
structure.
@endverbatim
*
* <b> Return Value </b> Uint32
* @n The number sub frames for shared processing mode
*
* <b> Pre Condition </b>
* @n configBase is populated with all the configurtaion parameters
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configParams argument passed.
*
* @b Example
* @verbatim
extern TCP2_UserData *userData;
TCP2_BaseParams configBase;
TCP2_Params configParams;
TCP2_TailData *xabData;
Uint32 frameLen = 40;
xabData = &userData [frameLen];
// assign the configuration parameters
configBase.frameLen = frameLen;
configBase.inputSign = TCP2_INPUT_SIGN_POSITIVE;
configBase.intFlag = 1;
configBase.maxIter = 8;
configBase.maxStarEn = TRUE;
configBase.standard = TCP2_STANDARD_3GPP;
configBase.crcLen = 0;
configBase.crcPoly = 0;
configBase.minIter = 1;
configBase.numCrcPass = 1;
configBase.outParmFlag = 0;
configBase.outputOrder = TCP2_OUT_ORDER_0_31;
configBase.prologRedEn = FALSE;
configBase.prologSize = 24;
configBase.rate = TCP2_RATE_1_3;
configBase.snr = 0;
for (cnt = 0; cnt < 16; cnt++)
configBase.extrScaling [cnt] = 32;
// setup the TCP configuration registers parmeters
TCP2_genParams (&configBase, &configParams);
@endverbatim
* ===========================================================================
*/
Uint32 TCP2_genParams (
TCP2_BaseParams *restrict configBase,
TCP2_Params *restrict configParams
);
/* ============================================================================
* @n@b TCP2_calcSubBlocksSA
*
* @b Description
* @n This function calculates the number of sub blocks for the TCP
* standalone processing. The reliability length is also calculated and the
* configParms structure is populated.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configParms argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
...
TCP2_calcSubBlocksSA (configParms);
@endverbatim
* ===========================================================================
*/
void TCP2_calcSubBlocksSA (
TCP2_Params *configParms
);
/* ============================================================================
* @n@b TCP2_calcSubBlocksSP
*
* @b Description
* @n This function calculates the number of sub blocks for the TCP
* shared processing. The reliability length is also calculated and the
* configParms structure is populated.
*
* @b Arguments
@verbatim
configParms Pointer to the structure holding the TCP
configuration parameters.
@endverbatim
*
* <b> Return Value </b> Uint32
* @n Number of sub frames the frame is divided into
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The configParms argument passed.
*
* @b Example
* @verbatim
extern TCP2_Params *configParms;
...
TCP2_calcSubBlocksSP (configParms);
@endverbatim
* ===========================================================================
*/
Uint32 TCP2_calcSubBlocksSP (
TCP2_Params *configParms
);
/* ============================================================================
* @n@b TCP2_tailConfig3GPP
*
* @b Description
* @n This function generates the input control values IC6-IC11 for 3GPP
* channels. These values consist of the tail data following the
* systematics and parities data. This function is called from the generic
* TCP2_tailConfig function.
*
* @b Arguments
@verbatim
mode TCP processing mode (SA or SP)
map TCP shared processing MAP
rate TCP data code rate
tailData Pointer to the tail data
configIc Pointer to the IC values structure
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The configIc structure is assigned the tail configuration values
* based on the tailData.
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
@endverbatim
* ===========================================================================
*/
void TCP2_tailConfig3GPP (
TCP2_Mode mode,
TCP2_Map map,
TCP2_Rate rate,
TCP2_TailData *restrict tailData,
TCP2_ConfigIc *restrict configIc
);
/* ============================================================================
* @n@b TCP2_tailConfigIs2000
*
* @b Description
* @n This function generates the input control values IC6-IC11 for IS2000
* channels. These values consist of the tail data following the
* systematics and parities data. This function is called from the generic
* TCP2_tailConfig function.
*
* @b Arguments
@verbatim
mode TCP processing mode (SA or SP)
map TCP shared processing MAP
rate TCP data code rate
tailData Pointer to the tail data
configIc Pointer to the IC values structure
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The configIc structure is assigned the tail configuration values
* based on the taildata.
*
* @b Modifies
* @n The configIc argument passed.
*
* @b Example
* @verbatim
@endverbatim
* ===========================================================================
*/
void TCP2_tailConfigIs2000 (
TCP2_Mode mode,
TCP2_Map map,
TCP2_Rate rate,
TCP2_TailData *restrict tailData,
TCP2_ConfigIc *restrict configIc
);
/* ============================================================================
* @n@b TCP2_deinterleaveExt
*
* @b Description
* @n This function de-interleaves the MAP2 extrinsics data to generate
* apriori data for the MAP1 decode. This function is for use in
* performing shared processing.
*
* @b Arguments
@verbatim
aprioriMap1 Apriori data for MAP1 decode
extrinsicsMap2 Extrinsics data
interleaverTable Interleaver data table
numExt Number of Extrinsics
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The aprioriMap1 will contain the deinterleaved data.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
<...MAP 2 decode...>
TCP2_deinterleaveExt(aprioriMap1, extrinsicsMap2,
interleaverTable, numExt);
<...MAP 1 decode...>
@endverbatim
* ===========================================================================
*/
void TCP2_deinterleaveExt (
TCP2_ExtrinsicData *aprioriMap1,
const TCP2_ExtrinsicData *extrinsicsMap2,
const Uint16 *interleaverTable,
Uint32 numExt
);
/* ============================================================================
* @n@b TCP2_interleaveExt
*
* @b Description
* @n This function interleaves the MAP1 extrinsics data to generate
* apriori data for the MAP2 decode. This function is for used in
* performing shared processing.
*
* @b Arguments
@verbatim
aprioriMap2 Apriori data for MAP2 decode
extrinsicsMap1 Extrinsics data
interleaverTable Interleaver data table
numExt Number of Extrinsics
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The aprioriMap2 will contain the interleaved data.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
<...MAP 1 decode...>
TCP2_interleaveExt(aprioriMap2, extrinsicsMap1,
interleaverTable, numExt);
<...MAP 2 decode...>
@endverbatim
* ===========================================================================
*/
void TCP2_interleaveExt (
TCP2_ExtrinsicData *aprioriMap2,
const TCP2_ExtrinsicData *extrinsicsMap1,
const Uint16 *interleaverTable,
Uint32 numExt
);
/* ============================================================================
* @n@b TCP2_depunctInputs
*
* @b Description
* @n This function scales and sorts input data into a code rate 1/5 format.
*
* @b Arguments
@verbatim
frameLen Input data length in bytes
inputData Input data
rate Input data code rate
scalingFact Scaling factor
depunctData Depunctured data
@endverbatim
*
* <b> Return Value </b> Uint32
* @n Length of output data in 32 bit words
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The depunctData will contain the data depunctured to rate 1/5.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
TCP2_depunctInputs (length, inputData, rate
scalingFact, depunctData);
@endverbatim
* ===========================================================================
*/
void TCP2_depunctInputs (
Uint32 frameLen,
TCP2_UserData* inputData,
TCP2_Rate rate,
Uint32 scalingFact,
TCP2_InputData* depunctData
);
/* ============================================================================
* @n@b TCP2_calculateHd
*
* @b Description
* @n This function calculates the hard decisions following multiple MAP
* decodings in shared processing mode.
*
* @b Arguments
@verbatim
extrinsicsMap1 Extrinsics data following MAP1 decode
apriori Apriori data following MAP2 decode
channel_data Input channel data
hardDecisions Hard decisions
numExt Number of extrinsics
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The hardDecisions will contain the calculated hard decisions.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
void TCP2_calculateHd(extrinsicsMap1, apriori,
channel_data, hardDecisions, numExt);
@endverbatim
* ===========================================================================
*/
void TCP2_calculateHd (
const TCP2_ExtrinsicData *extrinsicsMap1,
const TCP2_ExtrinsicData *apriori,
const TCP2_UserData *channelData,
Uint32 *hardDecisions,
Uint16 numExt
);
/* ============================================================================
* @n@b TCP2_demuxInput
*
* @b Description
* @n This function splits the input data into two working sets. One set
* contains the non-interleaved input data and is used with the MAP 1
* decoding. The other contains the interleaved input data and is used
* with the MAP2 decoding. This function is used in shared processing mode.
*
* @b Arguments
@verbatim
rate TCP data code rate
frameLen Frame length
input Input channel data
interleaver Interleaver data table
nonInterleaved Non Interleaved data for SP MAP0
interleaved Interleaved data for SP MAP1
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The nonInterleaved will contain the non-interleaved
* data and the interleaved will contain the interleaved data.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
TCP2_demuxInput (frameLen, input,
interleaver, interleaved, nonInterleaved);
@endverbatim
* ===========================================================================
*/
void TCP2_demuxInput (
Uint32 rate,
Uint32 frameLen,
const TCP2_UserData *input,
const Uint16 *interleaver,
TCP2_ExtrinsicData *nonInterleaved,
TCP2_ExtrinsicData *interleaved
);
#ifdef __cplusplus
}
#endif
#endif /* _CSL_TCP2_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspIoWrite.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_mcbspIoWrite.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API CSL_mcbspIoWrite()
*
*/
/* =============================================================================
* Revision History
* ================
* June 29,2004 <NAME> - Created
*
* =============================================================================
*/
#include <csl_mcbsp.h>
/** ============================================================================
* @n@b CSL_mcbspIoWrite
*
* @b Description
* @n Sends the data using MCBSP pin which is configured as general purpose
* output.The 16-bit data transmitted is specified by 'outputData' argument.
* MCBSP pin to use in this write operation is identified by the second
* argument.
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
outputSel MCBSP pin to be used as general purpose output
outputData 1 bit output data to be transmitted
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before CSL_mcbspIoWrite() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n MCBSP registers
*
* @b Example
* @verbatim
Uint16 outData;
CSL_Status status;
CSL_McbspHandle hMcbsp;
...
// MCBSP object defined and HwSetup structure defined and initialized
...
// Init, Open, HwSetup successfully done in that order
...
outData = 1;
CSL_mcbspIoWrite(hMcbsp, CSL_MCBSP_IO_CLKX, outData);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_mcbspIoWrite, ".text:csl_section:mcbsp");
void CSL_mcbspIoWrite (
CSL_McbspHandle hMcbsp,
CSL_BitMask16 outputSel,
Uint16 outputData
)
{
Uint16 bit_val;
Uint16 _pcrval;
_pcrval = hMcbsp->regs->PCR;
if(outputSel & CSL_MCBSP_IO_CLKX) {
bit_val = !(!(outputData & CSL_MCBSP_IO_CLKX));
CSL_FINS( _pcrval, MCBSP_PCR_CLKXP, bit_val);
}
if(outputSel & CSL_MCBSP_IO_FSX) {
bit_val = !(!(outputData & CSL_MCBSP_IO_FSX));
CSL_FINS( _pcrval, MCBSP_PCR_FSXP, bit_val);
}
if(outputSel & CSL_MCBSP_IO_DX) {
bit_val = !(!(outputData & CSL_MCBSP_IO_DX));
CSL_FINS( _pcrval, MCBSP_PCR_DXSTAT, bit_val);
}
if(outputSel & CSL_MCBSP_IO_CLKR) {
bit_val = !(!(outputData & CSL_MCBSP_IO_CLKR));
CSL_FINS( _pcrval, MCBSP_PCR_CLKRP, bit_val);
}
if(outputSel & CSL_MCBSP_IO_FSR) {
bit_val = !(!(outputData & CSL_MCBSP_IO_FSR));
CSL_FINS( _pcrval, MCBSP_PCR_FSRP, bit_val );
}
hMcbsp->regs->PCR = _pcrval;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2Init.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_ddr2Init.c
*
* @path $(CSLPATH)\src\ddr2
*
* @desc File for functional layer of CSL API @a CSL_ddr2Init()
* - The @a CSL_ddr2Init() function definition & it's associated
* functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 10-Apr-2005 RM File Created.
*
* 05-Oct-2005 NG Updation done according to new register layer
*
* =============================================================================
*/
#include <csl_ddr2.h>
/** ============================================================================
* @n@b CSL_ddr2Init
*
* @b Description
* @n This function is idempotent i.e. calling it many times is same as calling
* it once. This function presently does nothing.
*
* <b> Usage Constraints: </b>
* This function should be called before using any of the CSL APIs
*
* @b Arguments
@verbatim
pContext Context information for the instance. Should be NULL
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CSL_ddr2Init( NULL );
...
}
@endverbatim
*
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_ddr2Init, ".text:csl_section:ddr2");
CSL_Status CSL_ddr2Init (
CSL_Ddr2Context *pContext
)
{
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/edma/edma_chain_example/src/Edma_chain_example.c
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
*
* @file Edma_chain_example.c
*
* @path $(CSLPATH)\example\edma\edma_chain_example\src
*
* @desc Example of EDMA
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This is an example of the CSL EDMA usage. This example illustrates a
* chain triggering where the completion of the transfer on one channels
* triggers the transfer on another channel. This example,
* 1. Initializes the CSL EDMA module
* 2. Opens and Sets up Edma module to default values
* 3. Opens EDMA channel 0 in the region 5
* 4. Sets up the EDMA PARAM entry for channel 0 using
* CSL_edma3ParamSetup() API
* 5. Opens EDMA channel 8 in the region 5
* 6. Sets up the EDMA PARAM entry for channel 8 using
* CSL_edma3ParamSetup() API
* 7. Enable the channel 0 and 8
* 8. Manually triggers the channel 0, completion of this transfer
* triggers the transfer on channel 8.
* 9. Waits for EDMA transfer to complete
* 10. Does the data comparision to ensure the transffered data is proper
* or not and
* 11. Displays the messages based on step 10
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Edma_chain_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 08-Feb-2006 ds File Created
* 28-Mar-2006 ds Added clearing the EDMA error registers
* =============================================================================
*/
#include <stdio.h>
#include <csl_edma3.h>
#include <soc.h>
/* Globals */
Uint8 srcBuff1[512];
Uint8 srcBuff2[512];
Uint8 dstBuff1[512];
Uint8 dstBuff2[512];
Uint32 passStatus = 1;
/* Forward declaration */
void edma_chain_example (void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main(void)
{
/* Invoke example */
edma_chain_example ();
return;
}
/*
* =============================================================================
* @func edma_chain_example
*
* @arg
* NONE
*
* @desc
* This is the example routine which perform edma interrupt.
* It implements following steps
* 1. Intializes and Opens the Edma
* 2. Sets up the edma module using the API csl_edma3Hwsetup ()
* 4. Enables the edma region5 using CSL_EDMA3_CMD_DMAREGION_ENABLE.
* 5. Opens the channel 0 and get the param handle.
* 6. Sets up the edma param entry for channel 0
* 7. Opens the channel 8 and get the param handle.
* 8. Sets up the edma param entry for channel 8
* 9. Enables the channels using CSL_EDMA3_CMD_CHANNEL_ENABLE
* 10. Manually trigger the channel 0 using CSL_EDMA3_CMD_CHANNEL_SET.
* 10. Waits for transfer to complete.
* 11. Compares the data in the destination buffer is proper or not.
* 12. Closes the edma module and channel.
*
* @return
* NONE
*
* =============================================================================
*/
void edma_chain_example (void)
{
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamBasic;
CSL_Edma3ParamHandle hParamBasic1;
CSL_Edma3ChannelObj chObj;
CSL_Edma3ChannelObj chObj1;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ChannelHandle hChannel1;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3ParamSetup myParamSetup1;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3ChannelAttr chAttr1;
CSL_Status status;
CSL_Edma3HwDmaChannelSetup dmahwSetup;
CSL_Edma3ChannelErr chErrClear;
volatile Uint32 loopIndex;
printf ("Running Edma Example\n");
/* Module Initialization */
status = CSL_edma3Init(&context);
if (status != CSL_SOK) {
printf ("Edma module initialization failed\n");
return;
}
/* Module level open */
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
if ( (hModule == NULL) || (status != CSL_SOK)) {
printf ("Edma module open failed\n");
return;
}
/* Module setup */
dmahwSetup.paramNum = 0;
dmahwSetup.que = CSL_EDMA3_QUE_0;
hwSetup.dmaChaSetup = &dmahwSetup;
hwSetup.qdmaChaSetup = NULL;
status = CSL_edma3HwSetup(hModule,&hwSetup);
if (status != CSL_SOK) {
printf ("Hardware setup failed\n");
CSL_edma3Close (hModule);
return;
}
/* DRAE enable(Bits 0-15) for the shadow region 5 */
regionAccess.region = CSL_EDMA3_REGION_5 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
if (status != CSL_SOK) {
printf ("Edma region enable command failed\n");
return;
}
/* Channel 0 open in context of shadow region 5 */
chAttr.regionNum = CSL_EDMA3_REGION_5;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status);
if ((hChannel == NULL) || (status != CSL_SOK)) {
printf ("Edma channel open failed\n");
return;
}
/* Obtain a handle to parameter set 0 */
hParamBasic = CSL_edma3GetParamHandle(hChannel, 0, &status);
if (hParamBasic == NULL) {
printf ("Edma get param handle for param entry 0 failed\n");
return;
}
/* Setup the param set */
myParamSetup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_EN, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
8,
CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_AB, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR
);
myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(512,2);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(512,512);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1);
myParamSetup.cCnt = 1;
status = CSL_edma3ParamSetup(hParamBasic, &myParamSetup);
if (status != CSL_SOK) {
printf("Edma parameter entry setup is failed\n");
return;
}
/* Channel 8 open in context of shadow region 5 */
chAttr1.regionNum = CSL_EDMA3_REGION_5;
chAttr1.chaNum = CSL_EDMA3_CHA_8;
hChannel1 = CSL_edma3ChannelOpen(&chObj1, CSL_EDMA3, &chAttr1, &status);
if ((hChannel1 == NULL) || (status != CSL_SOK)) {
printf ("Edma channel open failed\n");
return;
}
/* Obtain a handle to parameter set 8 */
hParamBasic1 = CSL_edma3GetParamHandle(hChannel1, 8, &status);
/* Setup the param set */
myParamSetup1.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_EN, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
1, \
CSL_EDMA3_TCC_NORMAL, \
CSL_EDMA3_FIFOWIDTH_NONE, \
TRUE,CSL_EDMA3_SYNC_AB, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR
);
myParamSetup1.srcAddr = (Uint32)srcBuff2;
myParamSetup1.aCntbCnt = CSL_EDMA3_CNT_MAKE(512,2);
myParamSetup1.dstAddr = (Uint32)dstBuff2;
myParamSetup1.srcDstBidx = CSL_EDMA3_BIDX_MAKE(512,512);
myParamSetup1.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
myParamSetup1.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1);
myParamSetup1.cCnt = 1;
status = CSL_edma3ParamSetup(hParamBasic1,&myParamSetup1);
if (status != CSL_SOK) {
printf("Edma parameter entry setup is failed\n");
return;
}
/* Enable channel 0 */
status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL);
if (status != CSL_SOK) {
printf("Edma channel enable command for channel 0 is failed\n");
return;
}
/* Enable channel 8 */
status = CSL_edma3HwChannelControl(hChannel1,CSL_EDMA3_CMD_CHANNEL_ENABLE, \
NULL);
if (status != CSL_SOK) {
printf("Edma channel enable command for channel 8 is failed\n");
return;
}
/* Initialize data */
for (loopIndex = 0; loopIndex < 512; loopIndex++) {
srcBuff1[loopIndex] = loopIndex;
srcBuff2[loopIndex] = loopIndex;
dstBuff1[loopIndex] = 0;
dstBuff2[loopIndex] = 0;
}
/* Trigger Channel 0 */
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
regionIntr.region = CSL_EDMA3_REGION_5;
do {
/* Poll on interrupt bit 8 */
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
} while (!(regionIntr.intr & 0x100));
/* Clear interrupt bit 8 */
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \
®ionIntr);
if (status != CSL_SOK) {
printf("Edma clear interrupt bit 0 command is failed\n");
return;
}
/* Check transfer */
if(Verify_Transfer(512, 1, 1, 0, 0, 0, 0, srcBuff1, dstBuff1,TRUE) == FALSE)
passStatus = 0;
if(Verify_Transfer(512, 1, 1, 0, 0, 0, 0, srcBuff2, dstBuff2,TRUE) == FALSE)
passStatus = 0;
if (passStatus == 1)
printf ("<<EXAMPLE PASSED>>: Edma Chain Transfer Passed\n");
else {
printf ("<<EXAMPLE FAILED>>: Edma Chain Transfer Failed\n");
return;
}
/* Disable the region 5 */
regionAccess.region = CSL_EDMA3_REGION_5 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
/* clear the EDMA error registers */
chErrClear.missed = TRUE;
chErrClear.secEvt = TRUE;
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
/* Close channel */
status = CSL_edma3ChannelClose(hChannel);
if (status != CSL_SOK) {
printf("Edma channel close failed\n");
return;
}
/* Close edma module */
status = CSL_edma3Close(hModule);
if (status != CSL_SOK) {
printf("Edma module close failed\n");
return;
}
printf ("=============================================================\n");
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/cfg/csl_cfgHwControl.c
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_cfgHwControl.c
*
* @path $(CSLPATH)\src\cfg
*
* @desc File for functional layer of CSL API CSL_cfgHwControl()
*
*/
/* =============================================================================
* Revision History
* ===============
* 14-Apr-2005 Brn File Created
* =============================================================================
*/
#include <csl_cfg.h>
#include <csl_cfgAux.h>
/** ============================================================================
* @n@b CSL_cfgHwControl
*
* @b Description
* @n Takes a command of CFG with an optional argument & implements it.
*
* @b Arguments
* @verbatim
hCfg Handle to the CFG instance
cmd The command to this API indicates the action to be
taken on CFG.
arg An optional argument.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful.
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n Both CSL_cfgInit() and CSL_cfgOpen() must be called successfully in
* that order before CSL_cfgHwControl() can be called
*
* <b> Post Condition </b>
* @n CFG registers are configured according to the command and the command
* arguments. The command determines which registers are modified
*
* @b Modifies
* @n The registers of CFG.
*
* @b Example
* @verbatim
CSL_CfgHandle hCfg;
CSL_Status status;
...
status = CSL_cfgHwControl(hCfg, CSL_CFG_CMD_CLEAR, NULL);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_cfgHwControl, ".text:csl_section:cfg");
CSL_Status CSL_cfgHwControl(
CSL_CfgHandle hCfg,
CSL_CfgHwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK;
if ((cmd == 0) && (hCfg == NULL))
status = CSL_ESYS_BADHANDLE;
else {
switch(cmd){
case CSL_CFG_CMD_CLEAR:
CSL_cfgCmdClear(hCfg);
break;
default:
status = CSL_ESYS_INVCMD ;
break;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/edma/edma2x_example/inc/edma_int_dispatcher.h
|
/* =====================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* =====================================================================
*/
/** =====================================================================
* @file edma_int_desp.h
*
* @path $(CSLPATH)\example\edma\inc
*
* @desc This is part of an example of CSL 2.x usage of EDMA. A header
* file to support the EDMA interrupt handlers.
*
* ======================================================================
*/
/* ======================================================================
* Revision History
* ================
* 01-Aug-2005 Chandra File created.
* 11-Aug-2005 Chandra Minor format changes.
* ======================================================================
*/
#ifndef _EDMA_INT_DESP_H_
#define _EDMA_INT_DESP_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* ======================================================================
* @func eventEdmaHandler
*
* @desc
* This calls all the handlers of the TCC interrupts.
*
* @n <b> Procedure </b>
* @verbatim
For each TCC
1. Check if the interrupt is pending for that TCC
If pending
2. Call the corresponding handler
3. Clear the interrupt
@endverbatim
* ======================================================================
*/
void eventEdmaHandler (
void *handle
);
/*
* ======================================================================
* @func edmaEventHook
*
* @desc
* Hooks an interrupt for a given TCC number.
*
* @n <b> Procedure </b>
* @verbatim
1. Copies the address of given ISR into the given entry of
the TCC handler table.
@endverbatim
* ======================================================================
*/
void edmaEventHook (
Int tcc,
void fxn ()
);
#ifdef __cplusplus
}
#endif
#endif /*_EDMA_INT_DESP_H_*/
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/chip/src/Chip_example.c
|
<gh_stars>0
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file Chip_example.c
*
* @path $(CSLPATH)\example\chip\src
*
* @desc Example of CHIP
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n The example shows how to use CHIP CSL for following operation
* 1. Reads the value from the chip register
* 2. Writes the value to the chip register
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Chip_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 26-Jul-2005 ds File created
*
* 16-Dec-2005 ds Updated documentation
* ============================================================================
*/
#include <csl_chip.h>
#include <soc.h>
#include <stdio.h>
/* Forward declaration */
void chip_example (void);
/* Globals variable */
Uint16 chipExampleFail = 0;
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main (void)
{
/* Invoke example */
chip_example ();
if (chipExampleFail > 0) {
printf ("Example Failed:Chip write/read Reg Failed\n");
return;
}
else
printf ("Example Passed:Chip write/read Reg Passed\n");
printf("==============================================================\n");
return;
}
/*
* =============================================================================
* @func chip_example
*
* @arg
* NONE
*
* @desc
* This example shows how chip csl can be utilized to read and write chip
registers
*
* @return
* NONE
*
* =============================================================================
*/
void chip_example (void)
{
Uint32 val;
Uint32 prevValue;
printf ("Running CHIP module CSL example\n\n");
/* write value into CSL_CHIP_ISR register */
val = 0x00008000;
CSL_chipWriteReg(CSL_CHIP_ISR , val);
/* write one more value into CSL_CHIP_ISR register and get the old value */
val = 0x00001000;
prevValue = CSL_chipWriteReg(CSL_CHIP_ISR , val);
/* Check the previously written value */
if (prevValue == 0x00008000)
printf("Chip write reg passed\n");
else {
printf("Chip write reg failed\n");
chipExampleFail++;
return;
}
/* read the value from CSL_CHIP_ISR */
prevValue = CSL_chipReadReg(CSL_CHIP_ISR);
/* Check the previously written value */
if (prevValue == 0x00009000)
printf("Chip read reg passed\n");
else {
printf("Chip read reg failed \n");
chipExampleFail++;
return;
}
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/edma/edma_interrupt/src/edmaIntDispatcher.c
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
*
* @file edmaIntDispatcher.c
*
* @path $(CSLPATH)\example\edma\edma_interrupt\src
*
* @desc This is utility function used by edma as Interrupt dispather
*
* ============================================================================
*/
#include <csl_edma3.h>
#include <edmaCommon.h>
/* Global Edma Tcc handler table */
#pragma DATA_SECTION(TccHandlerTable,".testMem");
EdmaTccHandler TccHandlerTable[64];
/*
* =============================================================================
* @func eventEdmaHandler
*
* @arg
* handle - Edma module handle
*
* @desc
* This is the interrupt handler routine for edma interrupt
*
* @return
* NONE
*
* =============================================================================
*/
void eventEdmaHandler (
void *handle
)
{
CSL_Edma3Handle hModule = (CSL_Edma3Handle)handle;
CSL_BitMask32 maskVal;
CSL_Edma3CmdIntr regionIntr;
Uint32 tcc;
Uint32 intr;
Uint32 intrh;
/* Read the IPR */
regionIntr.region = CSL_EDMA3_REGION_1;
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND, ®ionIntr);
while (regionIntr.intr || regionIntr.intrh) {
intr = regionIntr.intr;
intrh = regionIntr.intrh;
tcc = 0;
while (intr) {
maskVal = 1 << tcc;
if (intr & maskVal) {
InvokeHandle(tcc);
intr &= ~maskVal;
}
tcc++;
}
tcc = 0;
while (intrh) {
maskVal = 1 << tcc;
if (intrh & maskVal) {
InvokeHandle((tcc+32));
intrh &= ~maskVal;
}
tcc++;
}
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,®ionIntr);
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
}
}
/*
* =============================================================================
* @func EdmaEventHook
*
* @arg
* tcc - Tcc number
* fxn - Pointer to function which points to edma isr
*
* @desc
* This is the interrupt handler routine for edma interrupt
*
* @return
* NONE
*
* =============================================================================
*/
void EdmaEventHook (
Uint16 tcc,
EdmaTccHandler fxn
)
{
TccHandlerTable[tcc] = (fxn);
}
/*
* =============================================================================
* @func Verify_Transfer
*
*
* @desc
* This is utility function used by the edma example to verify the
* Data transfer.
*
* @return
* NONE
*
* =============================================================================
*/
Bool Verify_Transfer (
Uint16 aCnt,
Uint16 bCnt,
Uint16 cCnt,
Uint16 srcBIdx,
Uint16 dstBIdx,
Uint16 srcCIdx,
Uint16 dstCIdx,
Uint8 *srcBuff,
Uint8 *dstBuff,
Bool abSync
)
{
Uint32 loopIndex1;
Uint32 loopIndex2;
Uint32 loopIndex3;
Uint8 *srcArrayPtr = srcBuff;
Uint8 *dstArrayPtr = dstBuff;
Uint8 *srcFramePtr = srcBuff;
Uint8 *dstFramePtr = dstBuff;
for (loopIndex1 = 0; loopIndex1 < cCnt; loopIndex1++) {
for (loopIndex2 = 0; loopIndex2 < bCnt; loopIndex2++) {
for (loopIndex3 = 0; loopIndex3 < aCnt; loopIndex3++)
if (srcArrayPtr[loopIndex3] != dstArrayPtr[loopIndex3])
return FALSE;
srcArrayPtr = srcArrayPtr + srcBIdx;
dstArrayPtr = dstArrayPtr + dstBIdx;
}
if (abSync) {
srcFramePtr = srcFramePtr + srcCIdx;
srcArrayPtr = srcFramePtr;
dstFramePtr = dstFramePtr + dstCIdx;
dstArrayPtr = dstFramePtr;
}
else {
srcFramePtr = srcArrayPtr + srcCIdx - srcBIdx;
srcArrayPtr = srcFramePtr;
dstFramePtr = dstArrayPtr + dstCIdx - dstBIdx;
dstArrayPtr = dstFramePtr;
}
}
return TRUE;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/i2c/src/I2c_example.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file I2C_Example.c
*
* @path $(CSLPATH)\example\i2c\src
*
* @desc Example of i2c
*
* =============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n The example shows the functionality of I2C in Loop back mode
* - Enables the I2C power saver clock
* - It configures the i2c in Digital Loopback mode.
* - Initalizes and Opens I2C instance.
* - Sets up up I2C in Digital Loopback mode, clock
* - Takes i2c out of reset
* - Sets data count
* - Enables and starts I2C
* - Waits for the transfer to start
* - verifies the data received
* - Stops the transmission and
* - Closes the opened instance
*
*==============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project I2c_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
* =============================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 23-Sep-2005 PSK File Created.
*
* 07-Nov-2005 NG - Removed the test bench specific details
* - Removed power saver disable
* 30-Nov-2005 NG Updated documentation
*
* =============================================================================
*/
#include <csl_i2c.h>
#include <csl_i2cAux.h>
#include <soc.h>
#include <cslr_dev.h>
#include <stdio.h>
#define CSL_I2C_MASTER_ADDR 0x10
#define CSL_I2C_SLAVE_ADDR 0x10
#define DATA_SIZE 26
#define CSL_I2C_CLOCK_PRESCALAR 0x13
#define CSL_I2C_CLOCK_CLKL 0x4
#define CSL_I2C_CLOCK_CLKH 0x4
#define CSL_I2C_DISABLE_INTR 0x7F
/* No of command that fails. */
Uint32 i2cFailCnt = 0;
/* Handle for the I2C instance */
CSL_I2cHandle hI2c;
CSL_I2cObj i2cObj;
/* Locals & Forwards */
void i2c_txRx_data(void);
/* clk set up */
CSL_I2cClkSetup clksetup = {
CSL_I2C_CLOCK_PRESCALAR,
CSL_I2C_CLOCK_CLKL,
CSL_I2C_CLOCK_CLKH,
};
/*---------Global data ---------*/
Uint8 xmtBuf[DATA_SIZE];
Uint8 rcvBuf[DATA_SIZE];
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine,which invokes the I2C example scripts
* =============================================================================
*/
void main (
void
)
{
Bool i2cEn;
/* Unlock the control register */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the I2C */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_I2CCTL,
ENABLE);
do {
i2cEn = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_I2CSTAT);
} while (i2cEn != TRUE);
printf("Powersaver clock for I2C is enabled\n");
/* Invoking of example Demo Script */
i2c_txRx_data();
return;
}
/*
* =============================================================================
* @func i2c_txRx_data
*
* @arg
* NONE
*
* @desc
* This function demonstrates the I2C functionality.
*
* @return
* NONE
*
* =============================================================================
*/
void i2c_txRx_data (
void
)
{
CSL_I2cHwSetup hwSetup;
CSL_Status status = CSL_SOK;
CSL_I2cObj i2cObj;
Uint32 response;
Uint32 datalen = DATA_SIZE,count = 0;
Uint32 DataCount = DATA_SIZE;
Uint8 success = TRUE;
Uint32 BbResponse;
Uint32 cmd_arg,index = 0;
hwSetup.mode = CSL_I2C_MODE_MASTER;
hwSetup.dir = CSL_I2C_DIR_TRANSMIT;
hwSetup.addrMode = CSL_I2C_ADDRSZ_SEVEN;
hwSetup.sttbyteen = CSL_I2C_STB_DISABLE;
hwSetup.ownaddr = CSL_I2C_SLAVE_ADDR;
hwSetup.ackMode = CSL_I2C_ACK_ENABLE;
hwSetup.runMode = CSL_I2C_FREE_MODE_DISABLE;
hwSetup.repeatMode = CSL_I2C_REPEAT_MODE_DISABLE;
hwSetup.loopBackMode = CSL_I2C_DLB_ENABLE;
hwSetup.freeDataFormat = CSL_I2C_FDF_DISABLE;
hwSetup.resetMode = CSL_I2C_IRS_ENABLE;
hwSetup.bcm = CSL_I2C_BCM_DISABLE;
hwSetup.inten = 0x00;
hwSetup.clksetup = &clksetup;
/* Clear local data structures */
memset(&i2cObj, 0, sizeof(CSL_I2cObj));
/* initializes the transmit buffer */
for (index = 0; index < DATA_SIZE; index++) {
xmtBuf[index] = 0x41 + index;
}
printf("Example of I2C\n");
/* Initialize I2C module */
status = CSL_i2cInit(NULL);
if (status != CSL_SOK) {
printf("I2C: Initialization error.\n");
printf("\tReason: CSL_i2cInit [status = 0x%x].\n", status);
i2cFailCnt++;
return;
}
/* open i2c */
hI2c = CSL_i2cOpen(&i2cObj, CSL_I2C, NULL, &status);
if ((status != CSL_SOK) || (hI2c == NULL)) {
printf("I2C: Error opening the instance. \
[status = 0x%x, hI2c = 0x%x]\n", status, hI2c);
i2cFailCnt++;
return;
}
/* i2c hwsetup */
status = CSL_i2cHwSetup(hI2c, &hwSetup);
if (status != CSL_SOK) {
printf("I2C: Error in I2C Hw Setup. [status = 0x%x]\n",status);
i2cFailCnt++;
return;
}
/* i2c out of reset */
CSL_i2cHwControl(hI2c, CSL_I2C_CMD_OUTOFRESET, NULL);
/* set data count */
CSL_i2cHwControl(hI2c, CSL_I2C_CMD_SET_DATA_COUNT, &DataCount);
/* Enable I2C */
status = CSL_i2cHwControl(hI2c, CSL_I2C_CMD_ENABLE, NULL);
if (status != CSL_SOK) {
printf("I2C: Error while enabling I2C. [status = 0x%x]\n", status);
i2cFailCnt++;
return;
}
/* Start I2C */
status = CSL_i2cHwControl(hI2c, CSL_I2C_CMD_START, NULL);
if (status != CSL_SOK) {
printf("I2C: Error while starting I2C. [status = 0x%x]\n", status);
return;
}
/* Wait for the transfer to start */
do {
CSL_i2cGetBusBusy(hI2c,&BbResponse);
} while(BbResponse != 1);
while (datalen) {
/* If Transmit Data Ready interrupt flag bit is set */
do {
CSL_i2cGetHwStatus(hI2c, CSL_I2C_QUERY_TX_RDY, &response);
} while(response != 1 );
/* Write the data into Data Transmit register*/
CSL_i2cWrite(hI2c, &xmtBuf[count]);
/* Clear the flag */
cmd_arg = CSL_I2C_CLEAR_XRDY;
if (CSL_i2cHwControl(hI2c,CSL_I2C_CMD_CLEAR_STATUS,&cmd_arg) !=
CSL_SOK) {
return;
}
/* If Recieve Data Ready , then read the data */
do {
CSL_i2cGetHwStatus(hI2c, CSL_I2C_QUERY_RX_RDY, &response);
} while (response != 1 /*CSL_I2C_ICSTR_RX_RDY_CHECK*/);
/* Copy the data from Data Recieve register */
CSL_i2cRead(hI2c, &rcvBuf[count]);
/* Clear the receive ready flag */
cmd_arg = CSL_I2C_CLEAR_RRDY;
if (CSL_i2cHwControl(hI2c,CSL_I2C_CMD_CLEAR_STATUS,&cmd_arg) !=
CSL_SOK) {
return;
}
datalen--;
count++;
}
/* verify the data recieved */
for (index = 0; index < DATA_SIZE ; index++) {
if ( rcvBuf[index] != xmtBuf[index] ) {
printf("Received data is invalid\n");
success = FALSE;
break;
}
}
if (success == TRUE) {
printf("\nData transmit and receive is Successful\n");
}
else {
printf("\nData transmit and receive is NOT Successful\n");
}
/* Stop the transmission */
if (CSL_i2cHwControl(hI2c, CSL_I2C_CMD_STOP ,NULL) != CSL_SOK) {
return;
}
/* Close the opened instance */
if (CSL_i2cClose(hI2c) != CSL_SOK) {
return;
}
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/tcp2/tcp2_shared_mode/src/tcp2_apriori.c
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004 , 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file tcp2_apriori.c
*
* @path $(CSLPATH)\example\c6455\tcp2\tcp2_shared_mode\src
*
* @desc Apriori data for the TCP2 shared mode
*
*/
#include <tistdtypes.h>
Uint32 aprioriData [] = {
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000,
0x00000000,0x00000000
};
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2HwSetup.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_ddr2HwSetup.c
*
* @path: $(CSLPATH)\src\ddr2
*
* @desc File for functional layer of CSL API @a CSL_ddr2HwSetup()
* - The @a CSL_ddr2HwSetup() function definition & it's associated
* functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 11-Apr-2005 RM File Created.
*
* 05-Oct-2005 NG Updation done according to new register layer
*
* 03-Feb-2006 ds Updated according to TCI6482/C6455 user guide
* (Added ddrDrive Configuration)
* =============================================================================
*/
#include <csl_ddr2.h>
/** ============================================================================
* @n@b CSL_ddr2HwSetup
*
* @b Description
* @n This function initializes the device registers with the appropriate values
* provided through the HwSetup data structure.
*
* @b Arguments
* @verbatim
hDdr2 Pointer to the peripheral data object of the
DDR2 external memory interface instance
setup Pointer to setup structure which contains the
information to program DDR2 to a useful state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK Hwsetup successful
* @li CSL_ESYS_BADHANDLE The handle passed is invalid
* @li CSL_ESYS_INVPARAMS The param passed is invalid
*
* <b> Pre Condition </b>
* Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called
* successfully in that order before this function can be called. The user
* has to allocate space for & fill in the main setup structure appropriately
* before calling this function
*
* <b> Post Condition </b>
* @n DDR2 registers are configured according to the hardware setup parameters
*
* @b Modifies
* @n DDR2 registers
*
* @b Example:
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Ddr2Timing1 tim1 = CSL_DDR2_TIMING1_DEFAULTS;
CSL_Ddr2Timing2 tim2 = CSL_DDR2_TIMING2_DEFAULTS;
CSL_Ddr2Settings set = CSL_DDR2_SETTING_DEFAULTS;
CSL_Ddr2HwSetup hwSetup ;
hwSetup.refreshRate = (Uint16)0x753;
hwSetup.timing1Param = &tim1;
hwSetup.timing2Param = &tim2;
hwSetup.setParam = &set;
CSL_ddr2HwSetup(hDdr2, &hwSetup);
@endverbatim
*
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_ddr2HwSetup, ".text:csl_section:ddr2");
CSL_Status CSL_ddr2HwSetup (
CSL_Ddr2Handle hDdr2,
CSL_Ddr2HwSetup *setup
)
{
CSL_Status status = CSL_SOK;
Uint32 mask;
/* invalid parameter checking */
if (setup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else if (hDdr2 == NULL) {
/* bad handle checking*/
status = CSL_ESYS_BADHANDLE;
}
else {
/* Refresh rate*/
CSL_FINS(hDdr2->regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, setup->refreshRate);
/* Writing the ddr2 sdram Settings in SDRAM Config register */
if (setup->setParam != NULL) {
mask = ~(
(CSL_DDR2_SDCFG_TIMUNLOCK_MASK) |
(CSL_DDR2_SDCFG_CL_MASK) |
(CSL_DDR2_SDCFG_IBANK_MASK) |
(CSL_DDR2_SDCFG_PAGESIZE_MASK)|
(CSL_DDR2_SDCFG_NM_MASK));
hDdr2->regs->SDCFG = (hDdr2->regs->SDCFG & mask ) |
(CSL_FMK(DDR2_SDCFG_TIMUNLOCK,
CSL_DDR2_SDCFG_TIMUNLOCK_SET)) |
(CSL_FMK(DDR2_SDCFG_CL,
setup->setParam->casLatncy)) |
(CSL_FMK(DDR2_SDCFG_IBANK,
setup->setParam->ibank)) |
(CSL_FMK(DDR2_SDCFG_NM,
setup->setParam->narrowMode)) |
(CSL_FMK(DDR2_SDCFG_PAGESIZE,
setup->setParam->pageSize));
CSL_FINS(hDdr2->regs->SDCFG, DDR2_SDCFG_BOOT_UNLOCK, \
CSL_DDR2_SDCFG_BOOT_UNLOCK_UNLOCKED);
CSL_FINS(hDdr2->regs->SDCFG, DDR2_SDCFG_DDR_DRIVE, \
setup->setParam->ddrDrive);
CSL_FINS(hDdr2->regs->SDCFG, DDR2_SDCFG_BOOT_UNLOCK, \
CSL_DDR2_SDCFG_BOOT_UNLOCK_LOCKED);
}
/* Setup the SDRAM Timing1 Register */
/* All fields which are writable with timing_unlock set are edited since the
* unlock bit is set above
*/
if(setup->timing1Param != NULL) {
if(setup->setParam == NULL) {
CSL_FINS(hDdr2->regs->SDCFG, DDR2_SDCFG_TIMUNLOCK,
CSL_DDR2_SDCFG_TIMUNLOCK_SET);
}
mask = ~( (CSL_DDR2_SDTIM1_T_RFC_MASK) |
(CSL_DDR2_SDTIM1_T_RP_MASK) |
(CSL_DDR2_SDTIM1_T_RCD_MASK) |
(CSL_DDR2_SDTIM1_T_WR_MASK) |
(CSL_DDR2_SDTIM1_T_RAS_MASK) |
(CSL_DDR2_SDTIM1_T_RC_MASK) |
(CSL_DDR2_SDTIM1_T_RRD_MASK) |
(CSL_DDR2_SDTIM1_T_WTR_MASK));
hDdr2->regs->SDTIM1 = (hDdr2->regs->SDTIM1 & mask) |
(CSL_FMK(DDR2_SDTIM1_T_RFC, setup->timing1Param->trfc)) |
(CSL_FMK(DDR2_SDTIM1_T_RP, setup->timing1Param->trp)) |
(CSL_FMK(DDR2_SDTIM1_T_RCD, setup->timing1Param->trcd)) |
(CSL_FMK(DDR2_SDTIM1_T_WR, setup->timing1Param->twr)) |
(CSL_FMK(DDR2_SDTIM1_T_RAS, setup->timing1Param->tras)) |
(CSL_FMK(DDR2_SDTIM1_T_RC, setup->timing1Param->trc)) |
(CSL_FMK(DDR2_SDTIM1_T_RRD, setup->timing1Param->trrd)) |
(CSL_FMK(DDR2_SDTIM1_T_WTR, setup->timing1Param->twtr));
}
/* Setup the SDRAM Timing2 Register */
/* All fields which are writable with timing_unlock set are edited since the
* unlock bit is set above
*/
if (setup->timing2Param != NULL) {
if((setup->setParam == NULL) && (setup->timing1Param == NULL)) {
CSL_FINS(hDdr2->regs->SDCFG, DDR2_SDCFG_TIMUNLOCK,
CSL_DDR2_SDCFG_TIMUNLOCK_SET);
}
mask = ~( (CSL_DDR2_SDTIM2_T_ODT_MASK)|
(CSL_DDR2_SDTIM2_T_SXNR_MASK) |
(CSL_DDR2_SDTIM2_T_SXRD_MASK) |
(CSL_DDR2_SDTIM2_T_RTP_MASK) |
(CSL_DDR2_SDTIM2_T_CKE_MASK));
hDdr2->regs->SDTIM2 = (hDdr2->regs->SDTIM2 & mask) |
(CSL_FMK(DDR2_SDTIM2_T_ODT,
setup->timing2Param->todt)) |
(CSL_FMK(DDR2_SDTIM2_T_SXNR,
setup->timing2Param->tsxnr)) |
(CSL_FMK(DDR2_SDTIM2_T_SXRD,
setup->timing2Param->tsxrd)) |
(CSL_FMK(DDR2_SDTIM2_T_RTP,
setup->timing2Param->trtp)) |
(CSL_FMK(DDR2_SDTIM2_T_CKE,
setup->timing2Param->tcke));
}
/* Locking the timing_unlock to prevent further changes */
CSL_FINS(hDdr2->regs->SDCFG, DDR2_SDCFG_TIMUNLOCK,
CSL_DDR2_SDCFG_TIMUNLOCK_CLEAR);
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c64xplus_intc_src/src/intc/csl_intcHwControl.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/**
* @file csl_intcHwControl.c
*
* @brief File for functional layer of CSL API CSL_intcHwControl()
*
* PATH $(CSLPATH)\src\intc
*/
/* =============================================================================
* Revision History
* ===============
* 12-Jun-2004 <NAME> File Created
*
* 16-Mar-2005 brn modified for doxygen documentation
* =============================================================================
*/
#include <csl_intc.h>
#include <_csl_intc.h>
#include <csl_intcAux.h>
/** ============================================================================
* @n@b CSL_intcHwControl
*
* @b Description
* @n Perform a control-operation. This API is used to invoke any of the
* supported control-operations supported by the module.
*
* @b Arguments
* @verbatim
hIntc Handle identifying the event
command The command to this API indicates the action to be
taken on INTC.
commandArg An optional argument.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - HwControl successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
*
* <b> Pre Condition </b>
* @n CSL_intcOpen() must be invoked before this call.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of INTC.
*
* @b Example
* @verbatim
CSL_IntcObj intcObj20;
CSL_IntcGlobalEnableState state;
CSL_IntcContext context;
CSL_Status intStat;
CSL_IntcParam vectId;
context.numEvtEntries = 0;
context.eventhandlerRecord = NULL;
// Init Module
CSL_intcInit(&context);
// NMI Enable
CSL_intcGlobalNmiEnable();
// Enable Global Interrupts
intStat = CSL_intcGlobalEnable(&state);
// Opening a handle for the Event 20 at vector id 4
vectId = CSL_INTC_VECTID_4;
hIntc20 = CSL_intcOpen (&intcObj20, CSL_INTC_EVENTID_20, &vectId , NULL);
CSL_intcHwControl(hIntc20,CSL_INTC_CMD_EVTENABLE,NULL);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_intcHwControl, ".text:csl_section:intc");
CSL_Status CSL_intcHwControl(
CSL_IntcHandle hIntc,
CSL_IntcHwControlCmd controlCommand,
void* commandArg
)
{
CSL_Status status = CSL_SOK;
if (hIntc == NULL)
status = CSL_ESYS_BADHANDLE;
switch(controlCommand) {
case CSL_INTC_CMD_EVTENABLE:
if (hIntc->vectId < CSL_INTC_VECTID_EXCEP) {
if (hIntc->vectId < CSL_INTC_VECTID_COMBINE) {
if (hIntc->eventId < 4) {
if (commandArg)
CSL_intcCombinedEventEnable(hIntc->eventId,\
*(CSL_BitMask32*)commandArg);
}
CSL_intcInterruptEnable(hIntc->vectId);
CSL_intcEventDisable(hIntc->eventId);
}
else
CSL_intcEventEnable(hIntc->eventId);
}
else
CSL_intcExcepEnable(hIntc->eventId);
break;
case CSL_INTC_CMD_EVTDISABLE:
if (hIntc->vectId < CSL_INTC_VECTID_EXCEP) {
if (hIntc->vectId < CSL_INTC_VECTID_COMBINE) {
if (hIntc->eventId < 4) {
if (commandArg)
CSL_intcCombinedEventDisable(hIntc->eventId, \
*(CSL_BitMask32*)commandArg);
}
CSL_intcInterruptDisable(hIntc->vectId);
}
else
CSL_intcEventDisable(hIntc->eventId);
}
else
CSL_intcExcepDisable(hIntc->eventId);
break;
case CSL_INTC_CMD_EVTSET:
CSL_intcEventSet(hIntc->eventId);
break;
case CSL_INTC_CMD_EVTCLEAR:
if (hIntc->vectId < CSL_INTC_VECTID_EXCEP) {
if (hIntc->eventId < 4) {
if (commandArg)
CSL_intcCombinedEventClear(hIntc->eventId, \
*(CSL_BitMask32*)commandArg);
}
else
CSL_intcEventClear(hIntc->eventId);
}
else
CSL_intcExcepClear(hIntc->eventId);
break;
case CSL_INTC_CMD_EVTDROPENABLE:
if (hIntc->vectId < CSL_INTC_VECTID_COMBINE)
CSL_intcInterruptDropEnable(1 << hIntc->vectId);
else
status = CSL_ESYS_INVCMD;
break;
case CSL_INTC_CMD_EVTDROPDISABLE:
if (hIntc->vectId < CSL_INTC_VECTID_COMBINE)
CSL_intcInterruptDropDisable(1 << hIntc->vectId);
else
status = CSL_ESYS_INVCMD;
break;
case CSL_INTC_CMD_EVTINVOKEFUNCTION:
CSL_intcInvokeEventHandle (hIntc->eventId);
break;
default:
status = CSL_ESYS_INVCMD;
break;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/vcp2/vcp2_soft_decisions/src/vcp2_soft_decisions_example.c
|
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file Vcp2_soft_decisions_example.c
*
* @path $(CSLPATH)\example\vcp2\vcp2_soft_decisions\src
*
* @desc Example of usage of CSL of VCP2 for computing soft decisions
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Description </b>
* This is an example for the VCP2 CSL usage for computing soft decision
* against the given branch metric values.
*
* @n The branch metrics are transferred to the VCP and soft decisions are
* read from the VCP using EDMA.
* @verbatim
1. Configure the 2 EDMA channels
2. Configure the input configuration registers of VCP
3. Enable EDMA channels
4. Start VCP
5. Wait until VCP run is complete
@endverbatim
*=============================================================================
*
* @n <b> Procedure to run the example </b>
* @verbatim
1. Configure the CCS setup
2. Please refer CCS manual for setup configuration and loading
proper GEL file
3. Launch CCS window
4. Open project Vcp2_soft_decisions_example.pjt
5. Build the project and load the .out file of the project.
@endverbatim
*
*
* ============================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 08-Oct-2005 SD File Created.
* 19-Dec-2005 SD Added clearing of EDMA channel error registers
* 06-Feb-2006 SD changes for the spec changes
* 24-Feb-2006 DS Added clearing of EDMA channel error registers at the
* end of example
* =============================================================================
*/
#include "csl_vcp2.h"
#include "csl_vcp2Aux.h"
#include "csl_edma3.h"
#include "stdio.h"
#include "string.h"
#include "cslr_dev.h"
#include "vcp2_example.h"
#define BITS_IN_A_BYTE 8
/* Constraint length */
#define CONSTRAINT_LEN 9
/* Frame length */
#define FRAME_LENGTH 186
/* EDMA frame size */
#define DMA_BURST_SIZE 128
/* VCP2 input configuration transfer size */
#define VCPIC_DMA_SIZE 24
/* VCP2 out register transfer size */
#define VCPOUT_DMA_SIZE 8
/* VCP2 yamamoto threshold */
#define YAMAMOTO_THRESHOLD 80
/* VCP2 initial state metric value */
#define INITIAL_STATE 63
/* Forward declarations */
Uint16 vcp2_configEdma(Uint32 inputBM, Uint32 outputHD);
/* EDMA global declarations */
CSL_Edma3Context context;
CSL_Edma3ChannelObj ChObj,ChObj1;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelHandle hChannel,hChannel1;
CSL_Edma3ParamHandle hParam[4];
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3ChannelAttr chParam, chParam1;
CSL_Edma3ChannelErr chErrClear;
/* Globals */
VCP2_ConfigIc vcpConfig;
Uint32 ouputParams[2];
/*
* =============================================================================
* @func main
* @desc
* Various parameters of the input data (Branch metrics) provided along
* with this example are as follows.
* Frame length...................................186
* rate...........................................1/2
* constraint length..............................9
* Decision mode..................................Soft
* Traceback Mode.................................Mixed
* Index of the initial max state metric(IMAXI)...63
* output parameters read flag....................TRUE
* Yamamoto enable................................TRUE
* Yamamoto threshold.............................80
* Traceback state enable.........................False
* Traceback state index..........................N/A
* DSP endian.....................................Little
* Endian Register................................bm_endian
* Output order...................................1
*
* @expected result
* Appropriate message will be logged depending on
* the result
*
* @eg
* main();
* =============================================================================
*/
void main()
{
volatile Uint16 frameLen, constLen;
Uint32 numSymProc;
Uint32 inputBM;
Uint32 outputHD;
Uint32 outputHD_bytes;
Uint32 outputHD_words;
VCP2_Params vcpParams;
VCP2_BaseParams vcpBaseParams;
VCP2_Errors errors;
Uint32 index;
VCP2_Poly poly = {0x6c, 0xe4, 0,0}; /* polynomials used */
/* Enable the VCP2 in power saver */
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
CSL_FINST (((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_VCPCTL,
ENABLE);
while (CSL_DEV_PERSTAT0_VCPSTAT_ENABLE !=
CSL_FEXT (((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_VCPSTAT));
/* VCP configuration */
vcpBaseParams.rate = VCP2_RATE_1_2;
vcpBaseParams.constLen = CONSTRAINT_LEN;
vcpBaseParams.frameLen = FRAME_LENGTH;
vcpBaseParams.yamTh = YAMAMOTO_THRESHOLD;
vcpBaseParams.stateNum = INITIAL_STATE;
vcpBaseParams.tbConvrgMode = FALSE;
vcpBaseParams.decision = VCP2_DECISION_SOFT;
vcpBaseParams.readFlag = TRUE;
vcpBaseParams.tailBitEnable = FALSE;
vcpBaseParams.traceBackIndex = 0;
vcpBaseParams.outOrder = 1;
/* VCP configuration */
VCP2_genParams (&vcpBaseParams, &vcpParams);
/* Number of EDMA frames (transfers) for branch metrics */
inputBM = vcpParams.numBmFrames;
/* Output hard decisions in terms of bytes rounded to upper byte */
outputHD_bytes = vcpBaseParams.frameLen + vcpBaseParams.constLen - 1;
/* Output hard decisions in terms of words rounded to upper words */
outputHD_words = VCP2_normalCeil (outputHD_bytes, sizeof (Uint32));
/* Total number of bytes required to be transfered */
outputHD = outputHD_words * sizeof (Uint32);
/* Configure EDMA */
if (!(vcp2_configEdma (inputBM, outputHD)))
{
printf("\nError in configuring EDMA\n");
return;
}
else
printf("\nConfiguring EDMA......... Success\n");
/* update the polynomials */
VCP2_addPoly (&poly, &vcpParams);
frameLen = vcpParams.frameLen;
constLen = vcpParams.constLen;
VCP2_genIc (&vcpParams, &vcpConfig);
/* clear the error registers */
chErrClear.missed = TRUE;
chErrClear.secEvt = TRUE;
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
/* Enable Channel */
CSL_edma3HwChannelControl(hChannel1, CSL_EDMA3_CMD_CHANNEL_ENABLE , NULL);
/* Enable Channel */
CSL_edma3HwChannelControl(hChannel, CSL_EDMA3_CMD_CHANNEL_ENABLE , NULL);
/* Start VCP2 */
VCP2_reset ();
VCP2_emuDisable ();
VCP2_start ();
printf("VCP2 is started...\n");
/* Wait till processing is over */
while (VCP2_statRun());
printf("VCP2 processing of data over\n");
printf("\nRESULTS\n");
printf("~~~~~~~\n");
printf("FMINS = %d\n", ((ouputParams[0] & 0x0FFF0000)>>16));
printf("FMAXS = %d\n", (ouputParams[0] & 0x00000FFF));
printf("FMAXI = %d\n", (ouputParams[1] & 0x0000000F));
/* Get the number of symbols processed */
numSymProc = VCP2_statSymProc();
printf("Number of symbols processed = %d \n", numSymProc);
/* Verify the soft decisions output */
for (index = 0; index < ((vcpParams.frameLen)/4); index++) {
if (soft_decision [index] != soft_decisionRef [index]) {
break;
}
}
if (index == ((vcpParams.frameLen)/4)) {
printf ("\nSoft decisions are computed properly\n");
}
else {
printf ("\nSoft decisions are not computed properly %d\n", index);
VCP2_getErrors(&errors);
if(errors.tbnaErr == FALSE &&
errors.ftlErr == FALSE &&
errors.fctlErr == FALSE &&
errors.maxminErr == FALSE &&
errors.symxErr == FALSE &&
errors.symrErr == FALSE) {
printf("No errors found set\n");
}
}
/* clear the error registers */
chErrClear.missed = TRUE;
chErrClear.secEvt = TRUE;
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEARERR,
&chErrClear);
CSL_edma3HwChannelControl (hChannel, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
CSL_edma3HwChannelControl (hChannel1, CSL_EDMA3_CMD_CHANNEL_CLEAR, NULL);
/* Close EDMA channels */
CSL_edma3ChannelClose (hChannel);
CSL_edma3ChannelClose (hChannel1);
}
/*
* =============================================================================
* @func vcp2_configEdma
* @desc
* Configures EDMA channels 28 and 29.
* For channel 29 there are 2 param entries(0 &1) which are linked.
* Link 0 transfers the VCP2 input configuration register values.
* Link 1 transfer Branch metrics.
* For channel 28 there 2 param entry (2 & 3).
* Link 2 transfers the soft decisions.
* Link 3 transfers the VCPOUT values
*
* @expected result
* Appropriate message will be logged depending on
* the result
*
* @eg
* vcp2_configEdma();
* =============================================================================
*/
Uint16 vcp2_configEdma(Uint32 inputBM, Uint32 outputHD)
{
volatile Uint16 count;
CSL_Status chStatus, chStatus1;
CSL_edma3Init(&context);
CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&chStatus);
/* Channel Configuration for VCP2XEVT event */
/* Channel Open */
chParam.regionNum = CSL_EDMA3_REGION_GLOBAL;
chParam.chaNum = CSL_EDMA3_CHA_VCP2XEVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chParam, &chStatus);
if ((chStatus != CSL_SOK) || (hChannel == NULL)) {
printf("Error in EDMA channel open function\n");
return 0;
}
/* Channel Setup */
if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel, 0 /* PaRAM entry */)){
printf("Error in EDMA channel setup for channel #29\n");
return 0;
}
if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel, CSL_EDMA3_QUE_0)) {
printf("Error in EDMA channel setup for channel #29\n");
return 0;
}
/* Setup link to transmit Input configuration */
hParam[0] = CSL_edma3GetParamHandle (hChannel, 0, &chStatus);
myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE,FALSE,FALSE,FALSE,0,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_NONE,
FALSE,CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)&vcpConfig;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(VCPIC_DMA_SIZE, 1);
myParamSetup.dstAddr = (Uint32)hVcp2Vbus;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0, 0);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(0x20, 0);
/* offset to the next param entry */
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0, 0);
myParamSetup.cCnt = 1;
if (CSL_SOK != CSL_edma3ParamSetup (hParam[0], &myParamSetup)) {
printf("Error in EDMA paRam setup for entry #0\n");
return 0;
}
/* Setup link to transmit branch metrics */
hParam[1] = CSL_edma3GetParamHandle(hChannel,1,&chStatus);
myParamSetup.option = CSL_EDMA3_OPT_MAKE(FALSE, FALSE, FALSE, FALSE, 0,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_64BIT,
FALSE,CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_CONST,
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)branch_metric;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(DMA_BURST_SIZE, 0);
myParamSetup.dstAddr = (Uint32)&(hVcp2Vbus->VCPWBM);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(
CSL_EDMA3_LINK_NULL, 0);
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(DMA_BURST_SIZE, inputBM);
myParamSetup.cCnt = 1;
if (CSL_SOK != CSL_edma3ParamSetup (hParam[1], &myParamSetup)) {
printf("Error in EDMA paRam setup for entry #1\n");
return 0;
}
/* Channel Configuration for VCP2REVT event */
/* Channel Open */
chParam1.regionNum = CSL_EDMA3_REGION_GLOBAL;
chParam1.chaNum = CSL_EDMA3_CHA_VCP2REVT;
hChannel1 = CSL_edma3ChannelOpen (&ChObj1, CSL_EDMA3, &chParam1,
&chStatus1);
if ((chStatus1 != CSL_SOK) | (hChannel1 == NULL)) {
printf("Error in EDMA channel open function\n");
return 0;
}
/* Channel Setup */
if (CSL_SOK != CSL_edma3HwChannelSetupParam(hChannel1, 2 )) {
printf("Error in EDMA channel setup for channel #29\n");
return 0;
}
if (CSL_SOK != CSL_edma3HwChannelSetupQue(hChannel1, CSL_EDMA3_QUE_0)) {
printf("Error in EDMA channel setup for channel #29\n");
return 0;
}
hParam[2] = CSL_edma3GetParamHandle (hChannel1, 2, &chStatus);
myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_64BIT,
FALSE,CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_CONST);
myParamSetup.srcAddr = (Uint32)&(hVcp2Vbus->VCPRDECS);
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (outputHD, 1);
myParamSetup.dstAddr = (Uint32)soft_decision;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE (0, outputHD);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (0x60, 0);
/* offset to the next param entry */
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE (0, 0);
myParamSetup.cCnt = 1;
if (CSL_SOK != CSL_edma3ParamSetup (hParam[2], &myParamSetup)) {
printf("Error in EDMA paRam setup for entry #2\n");
return 0;
}
hParam[3] = CSL_edma3GetParamHandle (hChannel1, 3, &chStatus);
myParamSetup.option = CSL_EDMA3_OPT_MAKE (FALSE, FALSE, FALSE, FALSE, 0,
CSL_EDMA3_TCC_NORMAL,
CSL_EDMA3_FIFOWIDTH_NONE,
FALSE,CSL_EDMA3_SYNC_A,
CSL_EDMA3_ADDRMODE_INCR,
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)&(hVcp2Vbus->VCPOUT0);
myParamSetup.dstAddr = (Uint32)&ouputParams[0];
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE (VCPOUT_DMA_SIZE, 1);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (
CSL_EDMA3_LINK_NULL, 0);
if (CSL_SOK != CSL_edma3ParamSetup (hParam[3], &myParamSetup)) {
printf("Error in EDMA paRam setup for entry #3\n");
return 0;
}
return 1;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioInit.c
|
/* ==========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* provided
* ==========================================================================
*/
/** ===========================================================================
* @file csl_gpioInit.c
*
* @path $(CSLPATH)\src\gpio
*
* @desc The CSL_gpioInit() function definition & it's associated functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 09-Jun-2004 PGR File created
* 04-Sep-2004 Nsr Updated the function and documentation for CSL_gpioInit.
* 11-oct-2004 Nsr updated the code to avoid compiler warning/remark.
* 06-Mar-2006 ds Updated the documentation
* ============================================================================
*/
#include <csl_gpio.h>
/** ===========================================================================
* @n@b CSL_gpioInit
*
* @b Description
* @n This is the initialization function for the GPIO CSL. The function must
* be called before calling any other API from this CSL. This function does
* not modify any registers or check status. It returns status CSL_SOK. It
* has been kept for future use.
*
* @b Arguments
* @verbatim
* pContext Pointer to module-context. Context information for the
* instance. Should be NULL
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The CSL for GPIO is initialized
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
* ...
* CSL_gpioInit(NULL);
* @endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_gpioInit, ".text:csl_section:gpio");
CSL_Status CSL_gpioInit (
CSL_GpioContext *pContext
)
{
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaGetHwStatus.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_emifaGetHwStatus.c
*
* @path $(CSLPATH)\src\emifa
*
* $desc File for functional layer of CSL API @a CSL_emifaGetHwStatus()
* - The @a CSL_emifaGetHwStatus() function definition & it's
* associated functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 12-May-2005 RM File Created.
*
* 09-Sep-2005 NG Updation according to coding guidelines
*
* =============================================================================
*/
#include <csl_emifa.h>
#include <csl_emifaAux.h>
/** ============================================================================
* @n@b CSL_emifaGetHwStatus
*
* @b Description
* @n This function is used to read the current device configuration, status
* flags and the value present associated registers. User should allocate
* memory for the said data type and pass its pointer as an unadorned void*
* argument to the status query call. For details about the various status
* queries supported & the associated data structure to record the response,
* refer to @a CSL_EmifaHwStatusQuery.
*
* @b Arguments
* @verbatim
hEmifa Pointer to the object that holds reference to the
instance of EMIFA requested after the call
query The query to this API which indicates the status
to be returned
response Placeholder to return the status. @a void* casted
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - successful on getting hardware
* status
* @li CSL_ESYS_INVQUERY - Query is not valid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling @a CSL_emifaGetHwStatus().
* For the argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_EmifaHwStatusQuery
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Third parameter response vlaue
*
* @b Example:
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_Status status;
Uint8 *response;
...
status = CSL_emifaGetHwStatus(hEmifa,
CSL_EMIFA_QUERY_ENDIAN,
&response);
@endverbatim
*
* ============================================================================
*/
#pragma CODE_SECTION (CSL_emifaGetHwStatus,".text:csl_section:emifa");
CSL_Status CSL_emifaGetHwStatus (
CSL_EmifaHandle hEmifa,
CSL_EmifaHwStatusQuery query,
void *response
)
{
CSL_Status status = CSL_SOK;
if(hEmifa == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (query) {
case CSL_EMIFA_QUERY_REV_ID:
CSL_emifaGetRevId (hEmifa,(CSL_EmifaModIdRev *)response);
break;
case CSL_EMIFA_QUERY_ASYNC_TIMEOUT_EN:
*(Uint8 *)response = CSL_emifaGetAsyncEnStatus (hEmifa);
break;
case CSL_EMIFA_QUERY_ASYNC_TIMEOUT_STATUS:
*(Uint8 *)response = CSL_emifaGetAsyncStatus (hEmifa);
break;
case CSL_EMIFA_QUERY_ENDIAN:
CSL_emifaGetEndian (hEmifa,(Uint8*)response);
break;
default:
status = CSL_ESYS_INVQUERY ;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspClose.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/mcbsp/csl_mcbspClose.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_mcbspClose.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API CSL_mcbspClose()
*
*/
/* =============================================================================
* Revision History
* ================
* June 29,2004 <NAME> - Created
*
* =============================================================================
*/
#include <csl_mcbsp.h>
/** ============================================================================
* @n@b CSL_mcbspClose
*
* @b Description
* @n Unreserves the MCBSP identified by the handle passed.
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - close successful
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before CSL_mcbspClose() can be called.
*
* <b> Post Condition </b>
* @n The mcbsp CSL APIs can not be called until the mcbsp CSL is reopened
* again using CSL_mcbspOpen()
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_mcbspHandle hMcbsp;
...
CSL_mcbspClose(hMcbsp);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_mcbspClose, ".text:csl_section:mcbsp");
CSL_Status CSL_mcbspClose (
CSL_McbspHandle hMcbsp
)
{
CSL_Status status;
if (hMcbsp != NULL) {
hMcbsp->regs = (CSL_McbspRegsOvly) NULL;
hMcbsp->perNum = (CSL_InstNum) - 1;
status = CSL_SOK;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/utopia2/src/Utopia2_example.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file Utopia_example.c
*
* @path $(CSLPATH)\example\utopia2\utopia_txRx_sphy\src
*
* @desc This is an example for UTOPIA2 of CSL2x.
*
* =============================================================================
* @n Target Platform : VDB
* =============================================================================
* @n <b> Example Description </b>
* @verbatim
This Example,
1. Enables the powersaver clock of UTOPIA2.
2. Configures the UTOPIA2.
3. Queries for transmit address, receive address and event id of Utopia.
4. Enables the transmit port and checks for the presence of transmit
clock.
5. Enables the receive port and checks for the presence of receive
clock.
@endverbatim
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Utopia_txRx_sphy.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 22-Sep-2005 NG Created
*
* 07-Dec-2005 NG Updated documentation
*
* 25-Jan-2006 NG Updated Example
* =============================================================================
*/
/*
* <include file>
*/
#include <stdio.h>
#include <csl_utopia2.h>
#include <cslr_utopia2.h>
#include <cslr_dev.h>
#include <tistdtypes.h>
#include <csl.h>
/*
* <Macros>
*/
/* Error Interrupt bits */
#define UTOP_ERR_RCF 0x01
#define UTOP_ERR_RCP 0x02
#define UTOP_ERR_XCF 0x11
#define UTOP_ERR_XCP 0x12
/* Utopia event Id */
Uint32 g_utopEventId;
Uint32 g_utopXmtAddr;
Uint32 g_utopEvent;
Uint32 g_clkSts;
Uint32 g_txIntrFlag;
void utopia_example(void);
void utopia_config_disp(void);
/*
* =============================================================================
* @func utopia_example
*
* @desc
* This function will initialize the UTOPIA module and also write and read
* back the value from the UTOPIA register.
*
* @arg
* NONE
*
* @return
* NONE
*
* =============================================================================
*/
void
utopia_example(
void
)
{
Uint32 val;
UTOPIA2_Config config;
config.ucr = 0x00000000;
/*
* Transmit Interface Clock Count Value : 0x00FF0000
* Receive Interface Clock Count Value : 0x000000FF
*/
config.cdr = 0x00FF00FF;
UTOPIA2_config(&config);
/*
* Clear all the pending error bit
* NOTE: Both clearing and disabling of error condition can be achieved by
* calling UTOP_errReset() function.
*/
printf("Clearing all pending errors...");
UTOPIA2_errClear(UTOP_ERR_RCF);
UTOPIA2_errClear(UTOP_ERR_RCP);
UTOPIA2_errClear(UTOP_ERR_XCF);
UTOPIA2_errClear(UTOP_ERR_XCP);
printf("Done\n");
/* Disable all error condition interrupt */
UTOPIA2_errDisable(UTOP_ERR_RCF);
UTOPIA2_errDisable(UTOP_ERR_RCP);
UTOPIA2_errDisable(UTOP_ERR_XCF);
UTOPIA2_errDisable(UTOP_ERR_XCP);
utopia_config_disp();
/* Transmit Address of Utopia */
val = UTOPIA2_getXmtAddr();
printf("Utopia Transmit Address : %x", val);
/* Receive Address of Utopia */
val = UTOPIA2_getRcvAddr();
printf("Utopia Receive Address : %x", val);
val = UTOPIA2_getEventId();
printf("Utopia Event Id : %x", val);
/* *********** TX clock check ****************** */
/* Enable the transmit port */
UTOPIA2_enableXmt();
g_clkSts = UTOPIA2_errTest(UTOP_ERR_XCP);
/* checks for presence of transmit clock */
if (g_clkSts) {
printf("UTOPIA: Transmit Clock present\n");
}
else {
printf("UTOPIA: Transmit Clock not present \n");
printf("Reason: Utopia Master transmit clock is not enabled\n");
}
/* *********** RX clock check ****************** */
/* Initiate the receive port enable */
UTOPIA2_enableRcv();
g_clkSts = UTOPIA2_errTest(UTOP_ERR_RCP);
/* checks for presence of receive clock */
if (g_clkSts) {
printf("UTOPIA: Receive Clock present\n");
}
else {
printf("UTOPIA: Receive Clock not present \n");
printf("Reason: Utopia Master receive clock is not enabled\n");
}
printf("UTOPIA: Example complete\n");
}
/*
* =============================================================================
* @func utopia_config_disp
*
* @desc
* Displays the configurations of UTOPIA2
*
* @arg
* NONE
*
* @return
* NONE
*
* =============================================================================
*/
void
utopia_config_disp (
void
)
{
UTOPIA2_Config myConfig;
printf("UTOPIA Configurations:\n");
UTOPIA2_getConfig(&myConfig);
printf("\tUCR Register\n");
if (myConfig.ucr & 0x10000000) {
printf("\t\tEndian : Big\n");
}
else {
printf("\t\tEndian : Little\n");
}
printf("\t\tSlave Id : %d\n",((myConfig.ucr & 0x1F000000) >> 24));
printf("\t\tTransmit Cell : %s\n",(((myConfig.ucr & 0x003C0000)==0)? \
"Standard Cell":"User Defined Cell") );
printf("\t\tTranmit Port : %s\n", \
((myConfig.ucr & 0x00010000)?"Enabled":"Disabled"));
printf("\t\tSlave Mode : Single\n", \
(myConfig.ucr & 0x00004000)?"Multi":"Single");
/*
* Receive User defined cell
* NOTE: 1. UTOPIA receives standard ATM cell size of 53B
*/
printf("\t\tReceive Cell : %s\n",(((myConfig.ucr & 0x0000003C)==0)? \
"Standard Cell":"User Defined Cell") );
printf("\t\tReceive Port : %s\n", \
((myConfig.ucr & 0x00000001)?"Enabled":"Disabled"));
/* Clock Detect Register (CDR) related stuffs
* NOTE:
* 1.The other way of setting this CDR is
* UTOP_CDR_RMK(UTOP_CDR_XCCNT_DEFAULT | UTOP_CDR_RCCNT_DEFAULT)
*
* Transmit/Receive Interface Clock Count Value
*
* 2.UTOP_CDR_XCCNT_OF(x) & UTOP_CDR_RCCNT_OF(x) is used to choose
* the value.
*/
printf("\tCDR Register\n");
printf("\t\tReceive Clock Detection : CLOCK %s\n", \
(((myConfig.cdr & 0x00FF0000) == 0)?"DISABLED":"ENABLED"));
printf("\t\tTransmit Clock Detection : CLOCK %s\n", \
(((myConfig.cdr & 0x000000FF) == 0)?"DISABLED":"ENABLED"));
}
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void
main (
void
)
{
Bool utopia2En;
/* Unlock the control register */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the UTOPIA2 */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_UTOPIACTL,
ENABLE);
do {
utopia2En = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT1,
DEV_PERSTAT1_UTOPIASTAT);
} while(utopia2En != TRUE);
g_clkSts = 0;
g_txIntrFlag = 1;
utopia_example();
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/vcp2/csl_vcp2.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ===========================================================================
* @file csl_vcp2.c
*
* @path $(CSLPATH)\src\vcp2
*
* @desc VCP API implementation
*
*/
/* ============================================================================
* Revision History
* ================
* 30-March-2005 SPrasad File Created.
* 21-April-2005 Sprasad Bug fix.
* 27-May-2005 SPrasad Updated with new requirements' specification.
* 03-Aug-2005 Chandra Minor beautification changes.
* 20-Sep-2005 Chandra Replaced the hardcodes with hash defines.
* 8-dec-2005 sd changed the maxSm and minSm to be signed
* integers
* 3-Feb-2005 sd Changes for the user guide changes
* ============================================================================
*/
#include <csl_vcp2.h>
#include <csl_vcp2Aux.h>
/* Polynomials for different constraint lengths and
code rates
- All these are octal numbers
- Default values
*/
#define VCP2_POLY0_FOR_CONST9_RATE_1_2 0561
#define VCP2_POLY1_FOR_CONST9_RATE_1_2 0753
#define VCP2_POLY0_FOR_CONST8_RATE_1_2 0712
#define VCP2_POLY1_FOR_CONST8_RATE_1_2 0476
#define VCP2_POLY0_FOR_CONST7_RATE_1_2 0554
#define VCP2_POLY1_FOR_CONST7_RATE_1_2 0744
#define VCP2_POLY0_FOR_CONST6_RATE_1_2 0650
#define VCP2_POLY1_FOR_CONST6_RATE_1_2 0570
#define VCP2_POLY0_FOR_CONST5_RATE_1_2 0460
#define VCP2_POLY1_FOR_CONST5_RATE_1_2 0720
#define VCP2_POLY0_FOR_CONST9_RATE_1_3_1_4 0557
#define VCP2_POLY1_FOR_CONST9_RATE_1_3_1_4 0663
#define VCP2_POLY2_FOR_CONST9_RATE_1_3_1_4 0711
#define VCP2_POLY3_FOR_CONST9_RATE_1_3_1_4 0557
#define VCP2_POLY0_FOR_CONST8_RATE_1_3_1_4 0452
#define VCP2_POLY1_FOR_CONST8_RATE_1_3_1_4 0662
#define VCP2_POLY2_FOR_CONST8_RATE_1_3_1_4 0756
#define VCP2_POLY3_FOR_CONST8_RATE_1_3_1_4 0452
#define VCP2_POLY0_FOR_CONST7_RATE_1_3_1_4 0544
#define VCP2_POLY1_FOR_CONST7_RATE_1_3_1_4 0624
#define VCP2_POLY2_FOR_CONST7_RATE_1_3_1_4 0764
#define VCP2_POLY3_FOR_CONST7_RATE_1_3_1_4 0544
#define VCP2_POLY0_FOR_CONST6_RATE_1_3_1_4 0470
#define VCP2_POLY1_FOR_CONST6_RATE_1_3_1_4 0530
#define VCP2_POLY2_FOR_CONST6_RATE_1_3_1_4 0750
#define VCP2_POLY3_FOR_CONST6_RATE_1_3_1_4 0470
#define VCP2_POLY0_FOR_CONST5_RATE_1_3_1_4 0520
#define VCP2_POLY1_FOR_CONST5_RATE_1_3_1_4 0660
#define VCP2_POLY2_FOR_CONST5_RATE_1_3_1_4 0760
#define VCP2_POLY3_FOR_CONST5_RATE_1_3_1_4 0520
/* Maxmimum frame sizes, maximum (reliability length +
convergence distance) and the number of trellis stages
processed in 2 passes for different constraint
lengths of soft and hard decisions
*/
/* For Hard Decisions */
#define VCP2_MAX_FRAME_SIZE_FOR_HD_CONST9 120
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST9 124
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST9 4
#define VCP2_MAX_FRAME_SIZE_FOR_HD_CONST8 217
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST8 217
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST8 7
#define VCP2_MAX_FRAME_SIZE_FOR_HD_CONST7 378
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST7 378
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST7 6
#define VCP2_MAX_FRAME_SIZE_FOR_HD_CONST6 635
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST6 635
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST6 5
#define VCP2_MAX_FRAME_SIZE_FOR_HD_CONST5 2044
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST5 2044
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST5 4
/* For Soft Decisions */
#define VCP2_MAX_FRAME_SIZE_FOR_SD_CONST9 56
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST9 60
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST9 4
#define VCP2_MAX_FRAME_SIZE_FOR_SD_CONST8 105
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST8 105
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST8 7
#define VCP2_MAX_FRAME_SIZE_FOR_SD_CONST7 186
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST7 186
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST7 6
#define VCP2_MAX_FRAME_SIZE_FOR_SD_CONST6 315
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST6 315
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST6 5
#define VCP2_MAX_FRAME_SIZE_FOR_SD_CONST5 1020
#define VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST5 1020
#define VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST5 4
/* Limit on sliding window length in case more than 1 sliding
window is required. (see section 2.4.5.4) */
#define VCP2_REL_LEN_LIMIT_FOR_A_SILDING_WINDOW 248
/* Branch metrics buffer length and branch metrics per
trellis state for different code rates */
#define VCP2_BM_PER_TRL_FOR_RATE_1_4 8
#define VCP2_SYMX_FOR_128_BYTE_PER_RXEVENT_RATE_1_4 3
#define VCP2_BM_PER_TRL_FOR_RATE_1_3 4
#define VCP2_SYMX_FOR_128_BYTE_PER_RXEVENT_RATE_1_3 7
#define VCP2_BM_PER_TRL_FOR_RATE_1_2 2
#define VCP2_SYMX_FOR_128_BYTE_PER_RXEVENT_RATE_1_2 15
/* Number of bytes transfered to the VCP2 per receive event */
#define VCP2_BYTE_COUNT_PER_RXEVENT 128
/* Maximum hard decisions in out FIFO */
#define VCP2_MAX_HD_IN_OUTFIFO 2048
/* Number of hard decisions per FIFO word */
#define VCP2_HD_PER_OUTFIFO_WORD 64
/* Maximum soft decisions in out FIFO */
#define VCP2_MAX_SD_IN_OUTFIFO 256
/* Number of hard decisions per FIFO word */
#define VCP2_SD_PER_OUTFIFO_WORD 8
/* Number of words in out FIFO */
#define VCP2_OUTFIFO_WORDS 32
/** ===========================================================================
* @n@b VCP2_genParams
*
* @b Description
* @n This function calculates the VCP parameters based on the input
* VCP2_BaseParams object values and set the values to the output
* VCP2_Params parameters structure.
*
* @b Arguments
@verbatim
pConfigBase Pointer to VCP base parameters structure.
pConfigParams Pointer to output VCP channel parameters structure.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Input VCP2_Params structure instance pointed by pConfigParams.
*
* @b Example
* @verbatim
VCP2_Params vcpParam;
VCP2_BaseParams vcpBaseParam;
...
vcpBaseParam.rate = VCP2_RATE_1_4;
vcpBaseParam.constLen = 5;
vcpBaseParam.frameLen = 2042;
vcpBaseParam.yamTh = 50;
vcpBaseParam.stateNum = 2048;
vcpBaseParam.tbConvrgMode = FALSE;
vcpBaseParam.decision = VCP2_DECISION_HARD;
vcpBaseParam.readFlag = VCP2_OUTF_YES;
vcpBaseParam.tailBitEnable = FALSE;
vcpBaseParam.traceBackIndex = 0x0;
vcpBaseParam.outOrder = VCP2_OUTORDER_0_31;
vcpBaseParam.perf = VCP2_SPEED_CRITICAL;
...
VCP2_genParams (&vcpBaseParam, &vcpParam);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (VCP2_genParams, ".text:csl_section:vcp2");
void
VCP2_genParams (
VCP2_BaseParams * restrict pConfigBase,
VCP2_Params * restrict pConfigParams
)
{
VCP2_Rate rate = pConfigBase->rate;
Bool tbConvrgMode = pConfigBase->tbConvrgMode;
Bool tailBitEnable = pConfigBase->tailBitEnable;
Uint8 constLen = pConfigBase->constLen;
Uint8 decision = pConfigBase->decision;
Uint8 readFlag = pConfigBase->readFlag;
Uint8 stateNum = pConfigBase->stateNum;
Uint8 outOrder = pConfigBase->outOrder;
Uint8 perf = pConfigBase->perf;
Uint16 frameLen = pConfigBase->frameLen;
Uint16 yamTh = pConfigBase->yamTh;
Uint16 traceBackIndex = pConfigBase->traceBackIndex;
Uint8 poly0 = 0;
Uint8 poly1 = 0;
Uint8 poly2 = 0;
Uint8 poly3 = 0;
Uint16 relLen = 0;
Uint16 convDist = 0;
Int16 minSm = 0;
Int16 maxSm = 0x400; /* Select a maximum value for initial state metric */
Uint8 bmBuffLen;
Uint8 decBuffLen;
Uint16 numBmFrames;
Uint16 numDecFrames;
Uint8 traceBack;
Uint8 i;
Uint8 convMultiplier;
Uint16 polynomes[4];
Uint16 fMax;
Uint16 rcMax;
Uint16 multiple;
Uint16 nsw;
Uint16 mask;
Uint16 bmNum;
Uint32 bmCnt;
/* VCPIC0 parameters */
if (rate == VCP2_RATE_1_2) {
if (constLen == 9) {
polynomes[0] = VCP2_POLY0_FOR_CONST9_RATE_1_2;
polynomes[1] = VCP2_POLY1_FOR_CONST9_RATE_1_2;
} /* end if constLen == 9 */
else if (constLen == 8) {
polynomes[0] = VCP2_POLY0_FOR_CONST8_RATE_1_2;
polynomes[1] = VCP2_POLY1_FOR_CONST8_RATE_1_2;
} /* end if constLen == 8 */
else if (constLen == 7) {
polynomes[0] = VCP2_POLY0_FOR_CONST7_RATE_1_2;
polynomes[1] = VCP2_POLY1_FOR_CONST7_RATE_1_2;
} /* end if constLen == 7 */
else if (constLen == 6) {
polynomes[0] = VCP2_POLY0_FOR_CONST6_RATE_1_2;
polynomes[1] = VCP2_POLY1_FOR_CONST6_RATE_1_2;
} /* end if constLen == 6 */
else { /* (constLen == 5) */
polynomes[0] = VCP2_POLY0_FOR_CONST5_RATE_1_2;
polynomes[1] = VCP2_POLY1_FOR_CONST5_RATE_1_2;
} /* end if constLen == 5 */
} /* end if rate 1/2 */
else { /* if rate 1/3 or 1/4 */
if (constLen == 9) {
polynomes[0] = VCP2_POLY0_FOR_CONST9_RATE_1_3_1_4;
polynomes[1] = VCP2_POLY1_FOR_CONST9_RATE_1_3_1_4;
polynomes[2] = VCP2_POLY2_FOR_CONST9_RATE_1_3_1_4;
polynomes[3] = VCP2_POLY3_FOR_CONST9_RATE_1_3_1_4;
} /* end if constLen == 9 */
else if (constLen == 8) {
polynomes[0] = VCP2_POLY0_FOR_CONST8_RATE_1_3_1_4;
polynomes[1] = VCP2_POLY1_FOR_CONST8_RATE_1_3_1_4;
polynomes[2] = VCP2_POLY2_FOR_CONST8_RATE_1_3_1_4;
polynomes[3] = VCP2_POLY3_FOR_CONST8_RATE_1_3_1_4;
} /* end if constLen == 8 */
else if (constLen == 7) {
polynomes[0] = VCP2_POLY0_FOR_CONST7_RATE_1_3_1_4;
polynomes[1] = VCP2_POLY1_FOR_CONST7_RATE_1_3_1_4;
polynomes[2] = VCP2_POLY2_FOR_CONST7_RATE_1_3_1_4;
polynomes[3] = VCP2_POLY3_FOR_CONST7_RATE_1_3_1_4;
} /* end if constLen == 7 */
else if (constLen == 6) {
polynomes[0] = VCP2_POLY0_FOR_CONST6_RATE_1_3_1_4;
polynomes[1] = VCP2_POLY1_FOR_CONST6_RATE_1_3_1_4;
polynomes[2] = VCP2_POLY2_FOR_CONST6_RATE_1_3_1_4;
polynomes[3] = VCP2_POLY3_FOR_CONST6_RATE_1_3_1_4;
} /* end if constLen == 6 */
else { /* (constLen == 5) */
polynomes[0] = VCP2_POLY0_FOR_CONST5_RATE_1_3_1_4;
polynomes[1] = VCP2_POLY1_FOR_CONST5_RATE_1_3_1_4;
polynomes[2] = VCP2_POLY2_FOR_CONST5_RATE_1_3_1_4;
polynomes[3] = VCP2_POLY3_FOR_CONST5_RATE_1_3_1_4;
} /* end if constLen == 5 */
} /* end if rate 1/3 or 1/4 */
/* zero out any unneeded polynomials, based on the data rate */
for (i = VCP2_RATE_1_4; i > rate; i--) {
polynomes[i - 1] = 0;
}
/* the polynome sent to the coprocessor has always the most
significant bit masked */
mask = 0x00FF;
/* Polynomes coefficients */
poly0 = polynomes[0] & mask;
poly1 = polynomes[1] & mask;
poly2 = polynomes[2] & mask;
poly3 = polynomes[3] & mask;
/* Calculation of reliability length */
/* Identify Fmax for a given constraint length and decision type */
if (decision == VCP2_DECISION_HARD) {
if (constLen == 9) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_HD_CONST9;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST9;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST9;
} /* end if constLen == 9 */
if (constLen == 8) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_HD_CONST8;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST8;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST8;
} /* end if constLen == 8 */
if (constLen == 7) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_HD_CONST7;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST7;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST7;
} /* end if constLen == 7 */
if (constLen == 6) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_HD_CONST6;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST6;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST6;
} /* end if constLen == 6 */
if (constLen == 5) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_HD_CONST5;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_HD_CONST5;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_HD_CONST5;
} /* end if constLen == 5 */
} /* end if hard decision */
else { /* if soft decision */
if (constLen == 9) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_SD_CONST9;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST9;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST9;
} /* end if constLen == 9 */
if (constLen == 8) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_SD_CONST8;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST8;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST8;
} /* end if constLen == 8 */
if (constLen == 7) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_SD_CONST7;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST7;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST7;
} /* end if constLen == 7 */
if (constLen == 6) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_SD_CONST6;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST6;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST6;
} /* end if constLen == 6 */
if (constLen == 5) {
fMax = VCP2_MAX_FRAME_SIZE_FOR_SD_CONST5;
rcMax = VCP2_MAX_RELLEN_CONV_DIST_FOR_SD_CONST5;
multiple = VCP2_TRL_STAGES_IN_2_PASSES_FOR_SD_CONST5;
} /* end if constLen == 5 */
} /* end if soft decision */
/* If mixed or convergent traceback mode */
if ((tbConvrgMode == TRUE) || (frameLen > fMax)) {
if (perf == VCP2_SPEED_MOST_CRITICAL) { /* Speed most critical */
convMultiplier = 3; /* convMultiplier
values - as
specified in the
'TPC2_VCP2_API_
Requirements_v1.4'
spread sheet */
}
else if (perf == VCP2_PERF_CRITICAL) { /* Performance critical */
if (constLen == 9) {
convMultiplier = 6;
}
else {
convMultiplier = 9;
}
}
else if (perf == VCP2_PERF_MOST_CRITICAL) {
/* Performance most critical */
if (constLen == 9) {
convMultiplier = 6;
}
else if (constLen == 8) {
convMultiplier = 12;
}
else {
convMultiplier = 18;
}
}
else { /* for speed critical and default case */
if (constLen == 9) {
convMultiplier = 3;
}
else {
convMultiplier = 6;
}
}
/* Calculation of Reliability length and Convergence distance */
convDist = convMultiplier * (constLen - 1);
nsw = VCP2_normalCeil (frameLen, rcMax - convDist);
relLen = multiple * VCP2_normalCeil (frameLen, nsw * multiple);
if ((decision == VCP2_DECISION_SOFT) & (constLen < 7)) {
while (relLen > VCP2_REL_LEN_LIMIT_FOR_A_SILDING_WINDOW) {
nsw++;
relLen = multiple * VCP2_normalCeil (frameLen, nsw * multiple);
}
}
} /* end if mixed or convergent traceback modes */
/* Trace back mode */
if (tbConvrgMode == TRUE) {
traceBack = VCP2_TRACEBACK_CONVERGENT;
}
else {
if (frameLen > fMax)
traceBack = VCP2_TRACEBACK_MIXED;
else
traceBack = VCP2_TRACEBACK_TAILED;
}
/* Calculation of branch metric buffer length */
/* Number of branch metrics per trellis stage */
if (rate == VCP2_RATE_1_4) {
bmNum = VCP2_BM_PER_TRL_FOR_RATE_1_4;
bmBuffLen = VCP2_SYMX_FOR_128_BYTE_PER_RXEVENT_RATE_1_4;
}
else if (rate == VCP2_RATE_1_3) {
bmNum = VCP2_BM_PER_TRL_FOR_RATE_1_3;
bmBuffLen = VCP2_SYMX_FOR_128_BYTE_PER_RXEVENT_RATE_1_3;
}
else if (rate == VCP2_RATE_1_2) {
bmNum = VCP2_BM_PER_TRL_FOR_RATE_1_2;
bmBuffLen = VCP2_SYMX_FOR_128_BYTE_PER_RXEVENT_RATE_1_2;
}
/* Maximum number of branch metrics */
if (traceBack == VCP2_TRACEBACK_CONVERGENT)
bmCnt = bmNum * (frameLen + convDist);
else
bmCnt = bmNum * (frameLen + constLen - 1);
/* Number of frame transfers */
numBmFrames = VCP2_normalCeil (bmCnt, VCP2_BYTE_COUNT_PER_RXEVENT);
/* Calculation of Decision buffer length */
if (decision == VCP2_DECISION_HARD) {
if (frameLen > VCP2_MAX_HD_IN_OUTFIFO)
decBuffLen = (VCP2_OUTFIFO_WORDS) - 1;
else {
decBuffLen = VCP2_normalCeil (frameLen, VCP2_HD_PER_OUTFIFO_WORD)
- 1;
numDecFrames = 1; /* Not being used here */
}
}
else {
if (frameLen > VCP2_MAX_SD_IN_OUTFIFO)
decBuffLen = (VCP2_OUTFIFO_WORDS) - 1;
else {
decBuffLen = VCP2_normalCeil (frameLen, VCP2_SD_PER_OUTFIFO_WORD)
- 1;
numDecFrames = 1; /* Not being used here */
}
}
pConfigParams->rate = rate;
pConfigParams->constLen = constLen;
pConfigParams->poly0 = poly0;
pConfigParams->poly1 = poly1;
pConfigParams->poly2 = poly2;
pConfigParams->poly3 = poly3;
pConfigParams->yamTh = yamTh;
pConfigParams->frameLen = frameLen;
pConfigParams->relLen = relLen;
pConfigParams->convDist = convDist;
pConfigParams->traceBackEn = tailBitEnable;
pConfigParams->traceBackIndex = traceBackIndex;
pConfigParams->outOrder = outOrder;
pConfigParams->maxSm = maxSm;
pConfigParams->minSm = minSm;
pConfigParams->stateNum = stateNum;
pConfigParams->bmBuffLen = bmBuffLen;
pConfigParams->decBuffLen = decBuffLen;
pConfigParams->traceBack = traceBack;
pConfigParams->readFlag = readFlag;
pConfigParams->decision = decision;
pConfigParams->numBmFrames = numBmFrames;
pConfigParams->numDecFrames = numDecFrames;
}
/** ==========================================================================
* @n@b VCP2_genIc
*
* @b Description
* @n This function generates the required input configuration registers'
* values needed to program the VCP based on the parameters provided by
* VCP2_Params object values.
*
* @b Arguments
@verbatim
pConfigParams Pointer to channel parameters structure.
pConfigIc Pointer to input configuration structure.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n The members of the channel parameter structure should
* be populated by calling the function 'VCP2_genParams()'
* before calling this function.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Input VCP2_ConfigIc structure instance pointed by pConfigIc.
*
* @b Example
* @verbatim
VCP2_Params vcpParam;
VCP2_BaseParams vcpBaseParam;
...
vcpBaseParam.rate = VCP2_RATE_1_4;
vcpBaseParam.constLen = 5;
vcpBaseParam.frameLen = 2042;
vcpBaseParam.yamTh = 50;
vcpBaseParam.stateNum = 2048;
vcpBaseParam.tbConvrgMode = FALSE;
vcpBaseParam.decision = VCP2_DECISION_HARD;
vcpBaseParam.readFlag = VCP2_OUTF_YES;
vcpBaseParam.tailBitEnable = FALSE;
vcpBaseParam.traceBackIndex = 0x0;
vcpBaseParam.outOrder = VCP2_OUTORDER_0_31;
vcpBaseParam.perf = VCP2_SPEED_CRITICAL;
...
VCP2_genParams (&vcpBaseParam, &vcpParam);
VCP2_genIc (&vcpParam, &vcpConfig);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (VCP2_genIc, ".text:csl_section:vcp2");
void
VCP2_genIc (
VCP2_Params * restrict pConfigParams,
VCP2_ConfigIc * restrict pConfigIc
)
{
Uint8 poly0 = pConfigParams->poly0;
Uint8 poly1 = pConfigParams->poly1;
Uint8 poly2 = pConfigParams->poly2;
Uint8 poly3 = pConfigParams->poly3;
Uint16 yamTh = pConfigParams->yamTh;
Uint16 frameLen = pConfigParams->frameLen;
Uint16 relLen = pConfigParams->relLen;
Uint16 convDist = pConfigParams->convDist;
Uint16 traceBackIndex = pConfigParams->traceBackIndex;
Bool traceBackEn = pConfigParams->traceBackEn;
Uint8 outOrder = pConfigParams->outOrder;
Int16 minSm = pConfigParams->minSm;
Int16 maxSm = pConfigParams->maxSm;
Uint8 stateNum = pConfigParams->stateNum;
Uint8 bmBuffLen = pConfigParams->bmBuffLen;
Uint8 decBuffLen = pConfigParams->decBuffLen;
Uint8 traceBack = pConfigParams->traceBack;
Uint8 readFlag = pConfigParams->readFlag;
Uint8 decision = pConfigParams->decision;
Uint32 ic0 = 0;
Uint32 ic1 = 0;
Uint32 ic2 = 0;
Uint32 ic3 = 0;
Uint32 ic4 = 0;
Uint32 ic5 = 0;
/* VCPIC0 parameters */
ic0 = CSL_FMK (VCP2_VCPIC0_POLY0, poly0) |
CSL_FMK (VCP2_VCPIC0_POLY1, poly1) |
CSL_FMK (VCP2_VCPIC0_POLY2, poly2) |
CSL_FMK (VCP2_VCPIC0_POLY3, poly3);
/* VCPIC1 parameters */
if (yamTh) {
CSL_FINST (ic1, VCP2_VCPIC1_YAMEN, ENABLE);
CSL_FINS (ic1, VCP2_VCPIC1_YAMT, yamTh);
}
/* VCPIC2 parameters */
ic2 = CSL_FMK (VCP2_VCPIC2_FL, frameLen) |
CSL_FMK (VCP2_VCPIC2_R, relLen);
/* VCPIC3 parameters */
ic3 = CSL_FMK (VCP2_VCPIC3_C, convDist) |
CSL_FMK (VCP2_VCPIC3_ITBI, traceBackIndex) |
CSL_FMK (VCP2_VCPIC3_ITBEN, traceBackEn) |
CSL_FMK (VCP2_VCPIC3_OUT_ORDER, outOrder);
/* VCPIC4 parameters */
ic4 = CSL_FMK (VCP2_VCPIC4_IMAXS, maxSm) |
CSL_FMK (VCP2_VCPIC4_IMINS, minSm);
/* VCPIC5 parameters */
ic5 = CSL_FMK (VCP2_VCPIC5_IMAXI, stateNum) |
CSL_FMK (VCP2_VCPIC5_SYMX, bmBuffLen) |
CSL_FMK (VCP2_VCPIC5_SYMR, decBuffLen) |
CSL_FMK (VCP2_VCPIC5_TB, traceBack) |
CSL_FMK (VCP2_VCPIC5_OUTF, readFlag) |
CSL_FMK (VCP2_VCPIC5_SDHD, decision);
pConfigIc->ic0 = ic0;
pConfigIc->ic1 = ic1;
pConfigIc->ic2 = ic2;
pConfigIc->ic3 = ic3;
pConfigIc->ic4 = ic4;
pConfigIc->ic5 = ic5;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/edma/edma_ping_pong_xfer_gbl_reg/src/edmaCheckTransfer.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004,2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
*
* @file edmaCheckTransfer.c
*
* @path $(CSLPATH)\example\edma\edma_ping_pong_xfer_gbl_reg\src
*
* @desc This is utility function used by the edma example to verify the
* Data transfer.
* ============================================================================
*/
#include <csl_edma3.h>
/* Forward declaration */
Bool Verify_Transfer (Uint16 aCnt, Uint16 bCnt, Uint16 cCnt,Uint16 srcBIdx,
Uint16 dstBIdx, Uint16 srcCIdx, Uint16 dstCIdx,
Uint8 *srcBuff, Uint8 *dstBuff, Bool abSync);
/*
* =============================================================================
* @func Verify_Transfer
*
*
* @desc
* This is utility function used by the edma example to verify the
* Data transfer.
*
* @return
* NONE
*
* =============================================================================
*/
Bool Verify_Transfer (
Uint16 aCnt,
Uint16 bCnt,
Uint16 cCnt,
Uint16 srcBIdx,
Uint16 dstBIdx,
Uint16 srcCIdx,
Uint16 dstCIdx,
Uint8 *srcBuff,
Uint8 *dstBuff,
Bool abSync
)
{
Uint32 loopIndex1;
Uint32 loopIndex2;
Uint32 loopIndex3;
Uint8 *srcArrayPtr = (Uint8*)srcBuff;
Uint8 *dstArrayPtr = (Uint8*)dstBuff;
Uint8 *srcFramePtr = (Uint8*)srcBuff;
Uint8 *dstFramePtr = (Uint8*)dstBuff;
for (loopIndex1 = 0; loopIndex1 < cCnt; loopIndex1++) {
for (loopIndex2 = 0; loopIndex2 < bCnt; loopIndex2++) {
for (loopIndex3 = 0; loopIndex3 < aCnt; loopIndex3++)
if (srcArrayPtr[loopIndex3] != dstArrayPtr[loopIndex3])
return FALSE;
srcArrayPtr = srcArrayPtr + srcBIdx;
dstArrayPtr = dstArrayPtr + dstBIdx;
}
if (abSync) {
srcFramePtr = srcFramePtr + srcCIdx;
srcArrayPtr = srcFramePtr;
dstFramePtr = dstFramePtr + dstCIdx;
dstArrayPtr = dstFramePtr;
}
else {
srcFramePtr = srcArrayPtr + srcCIdx - srcBIdx;
srcArrayPtr = srcFramePtr;
dstFramePtr = dstArrayPtr + dstCIdx - dstBIdx;
dstArrayPtr = dstFramePtr;
}
}
return TRUE;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/timer/src/Timer_example.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* =============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ==========================================================================*/
/** ===========================================================================
* @file Timer_example.c
*
* @path $(CSLPATH)\example\timer\src
*
* @desc Example for the usage of General purpose timer CSL APIs
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n The example illustartes the usage of CSL APIs for using timer.
* 1. This example configures the first instance of timer
* as interrupt or event to be sourced normally by the timer.
* 2. This enables the timer in one shot mode (for watchdog mode timer is
* enabled in continuos mode).
* 3. The interrupt handler announces occurance of each interupt
* to the application.
* 4. The above said procedure is followed for all the modes of the timer
* (i.e. 64 bit timer, dual 32 bit timer(chained and unchained)
* and watchdog).
*==============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Timer_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
* =============================================================================
*/
/** ============================================================================
* Revision History
* ===============
* 21-Apr-2005 PSK - File Created.
* 29-Jul-2005 PSK - Updted changes acooriding to revised timer spec. The
* number convention TIM12, TIM34 are changed to TIMLO and
* TIMHI.
* 30-Nov-2005 NG - Updated documentation
* 06-Feb-2006 ds - Updated example according to C6455 user guide.(Removed
* tmrClksrcHi and tmrIpGateHi hwsetup configuration)
* 23-Mar-2006 ds - Fixed Bug PSG00001172
* =============================================================================
*/
#include <csl_tmr.h>
#include <stdio.h>
#include <csl_intc.h>
#include <soc.h>
#include <csl_intcAux.h>
#include <cslr_dev.h>
/* Handle for the TMR instance */
CSL_TmrHandle hTmr;
/* NOTE: change the Instance of the timer for different timer instances */
Uint8 IntcInstance = CSL_TMR_0;
/* Locals & Forwards */
void tmrIntcPrdLoLoadDemo(void);
void tmrIntcPrdHiLoadDemo(void);
void tmrIntcChainedDemo(void);
void tmrIntcGptDemo(void);
void tmrWdtModeDemo(void);
/*
*****************************************************************************
* INTC related code
*****************************************************************************
*/
/* Intc Declarations */
CSL_IntcObj tmrIntcObj, tmrIntcObj1;
CSL_IntcHandle tmrIntcHandle, tmrIntcHandle1;
CSL_IntcContext context, context1;
CSL_IntcEventHandlerRecord eventHandler[30];
CSL_IntcEventHandlerRecord record[1];
/* count for ISR */
volatile int intrCnt = 0;
/*
* =============================================================================
* @func TimerInterruptHandler
*
* @arg
* event - interrupt event id
*
* @desc
* Handler for Timer Interrupt
*
* @return
* NONE
*
* =============================================================================
*/
void TimerInterruptHandler (
CSL_IntcEventId *event
)
{
intrCnt++;
CSL_intcEventClear(*event);
}
/** ===========================================================================
* @n@b main
*
* @b Description
* @n This is the main function for the file.This initializes the CSL for
* INTC, installs interrupt handler for first instance of general purpose
* timer and invokes the routine which demonstrates the usage of CSL APis
* for General purpose timer
* ============================================================================
*/
void main (
void
)
{
CSL_IntcGlobalEnableState state;
Bool timer0En;
/* Unlock the control register */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL,
UNLOCK);
/* Enable the Powersaver clock for TIMER */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_TIMER0CTL,
ENABLE);
do {
timer0En = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0,
DEV_PERSTAT0_TIMER0STAT);
} while ((timer0En) != TRUE);
printf("Powersaver clock for TIMER is enabled\n");
/* Initialize INTC */
context.numEvtEntries = 1;
context.eventhandlerRecord = record;
CSL_intcInit(&context);
/* Enable NMIS */
CSL_intcGlobalNmiEnable();
/* Enable all interrupts */
CSL_intcGlobalEnable(&state);
tmrIntcPrdLoLoadDemo();
tmrIntcPrdHiLoadDemo();
tmrIntcChainedDemo();
tmrIntcGptDemo();
tmrWdtModeDemo();
printf(">>>>>> Example for all the modes of timer are \
completed <<<<<<<< \n");
}
/*
* =============================================================================
* @func tmrIntcPrdLoLoadDemo
*
* @arg
* NONE
*
* @desc
* This funtion is example for the Period register loading with value.
*
* @return
* NONE
*
* =============================================================================
*/
void tmrIntcPrdLoLoadDemo (
void
)
{
CSL_TmrObj TmrObj;
CSL_Status intStat, status;
CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
Uint32 LoadValue = 100;
CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;
/* Clear local data structures */
memset(&TmrObj, 0, sizeof(CSL_TmrObj));
printf("Running Gp Timer Interrupt DUAL UNCHAINED Low....\n");
/**************************************************************
* INTC related code *
**************************************************************/
/* Open INTC */
vectId = CSL_INTC_VECTID_12;
tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_INTC_EVENTID_TINTLO0, &vectId,
&intStat);
/* Bind ISR to Interrupt */
EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
EventRecord.arg = (void *)tmrIntcHandle;
CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);
/* Event Enable */
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);
/**************************************************************/
/* Initialize timer CSL module */
CSL_tmrInit(NULL);
hTmr = CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);
CSL_tmrHwSetup(hTmr, &hwSetup);
/* Stop the Timer */
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL);
/* set the timer mode to unchained dual mode */
hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED;
CSL_tmrHwSetup(hTmr, &hwSetup);
/* Load the period register */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void *)&LoadValue);
/* Start the timer with one shot*/
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, (void *)&TimeCountMode);
/* INTC related code */
while (1) {
if (intrCnt == 1)
break;
}
/**************************************************************/
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);
printf("INTR: The Total number of Events occured are: 0x%d\n", intrCnt);
intrCnt = 0;
/* Stop the Timer */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMLO, NULL);
printf("Example for TIMLO completed\n");
/* Close the Tmr instance */
CSL_tmrClose(hTmr);
CSL_intcClose(tmrIntcHandle);
}
/*
* =============================================================================
* @func tmrIntcPrdHiLoadDemo
*
* @arg
* NONE
*
* @desc
* This function is example for the Period register 34 loading with value.
*
* @return
* NONE
*
* =============================================================================
*/
void tmrIntcPrdHiLoadDemo (
void
)
{
CSL_TmrObj TmrObj;
CSL_Status status;
CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
Uint32 LoadValue = 100;
CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;
/* Clear local data structures */
memset(&TmrObj, 0, sizeof(CSL_TmrObj));
printf("\n\n\n\n\nRunning Gp Timer Interrupt DUAL UNCHAINED TIMHI....\n");
/**************************************************************
* INTC related code *
**************************************************************/
/* Open INTC */
vectId = CSL_INTC_VECTID_13;
tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_INTC_EVENTID_TINTHI0, &vectId,
NULL);
/* Bind ISR to Interrupt */
EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
EventRecord.arg = (void *)tmrIntcHandle;
CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);
/* Event Enable */
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);
/**************************************************************/
/* Initialize timer CSL module */
CSL_tmrInit(NULL);
hTmr = CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);
CSL_tmrHwSetup(hTmr, &hwSetup);
/* Stop the Timer */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMHI, NULL);
/* set the timer mode to unchained dual mode */
hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_UNCHAINED;
CSL_tmrHwSetup(hTmr, &hwSetup);
/* Load the period register */
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDHI, (void *)&LoadValue);
/* Start the timer with one shot*/
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMHI, (void *)&TimeCountMode);
/* INTC related code */
while (1) {
if (intrCnt == 1)
break;
}
/**************************************************************/
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);
printf("INTR: The Total number of Events occured are: 0x%d\n", intrCnt);
intrCnt = 0;
/* Stop the Timer */
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET_TIMHI, NULL);
printf("Example for TIM34 completed\n");
/* Close the Tmr instance */
CSL_tmrClose(hTmr);
CSL_intcClose(tmrIntcHandle);
}
/*
* =============================================================================
* @func tmrIntcChainedDemo
*
* @arg
* NONE
*
* @desc
* This is example to verify the setting of timer in dual 32 bit chained
* and one shot mode with INTC.
*
* @return
* NONE
*
* =============================================================================
*/
void tmrIntcChainedDemo (
void
)
{
CSL_TmrObj TmrObj;
CSL_Status status;
CSL_IntcEventHandlerRecord EventRecord;
CSL_IntcParam vectId;
Uint32 LoadValue = 100;
Uint32 LoadValue1 = 0;
Uint8 preScalValue = 0;
CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
/* set the timer in to one shot mode */
CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;
/* Clear local data structures */
memset(&TmrObj, 0, sizeof(CSL_TmrObj));
printf("\n\n\n\n\nRunning Gp Timer Interrupt DUAL CHAINED....\n");
/**************************************************************
* INTC related code *
**************************************************************/
/* Open INTC */
vectId = CSL_INTC_VECTID_12;
tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_INTC_EVENTID_TINTLO0, \
&vectId, NULL);
/* Bind ISR to Interrupt */
EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
EventRecord.arg = (void *)tmrIntcHandle;
CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);
/* Event Enable */
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);
/**************************************************************/
/* Initialize timer CSL module */
CSL_tmrInit(NULL);
hTmr = CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);
CSL_tmrHwSetup(hTmr, &hwSetup);
/* Reset the Timer */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);
/* set the timer mode to dual chained mode */
hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_DUAL_CHAINED;
CSL_tmrHwSetup(hTmr, &hwSetup);
/* Load the prescale value */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PSCHI, (void *)&preScalValue);
/* Load the period register */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDLO, (void *)&LoadValue);
/* Load the period register */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_PRDHI, (void *)&LoadValue1);
/* Start the timer with one shot*/
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START64, (void *)&TimeCountMode);
/**************************************************************
* INTC related code *
**************************************************************/
while (1) {
if (intrCnt == 1)
break;
}
/**************************************************************/
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);
printf("INTR: The Total number of Events occured are: 0x%d\n", intrCnt);
intrCnt = 0;
/* Stop the Timer */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);
printf("Example for timer chained mode completed\n");
/* Close the Tmr instance */
CSL_tmrClose(hTmr);
CSL_intcClose(tmrIntcHandle);
}
/*
* =============================================================================
* @func tmrIntcGptDemo
*
* @arg
* NONE
*
* @desc
* This is example to verify the setting of timer in GPT mode with INTC.
*
* @return
* NONE
*
* =============================================================================
*/
void tmrIntcGptDemo (
void
)
{
CSL_TmrObj TmrObj;
CSL_IntcEventHandlerRecord EventRecord, EventRecord1;
CSL_IntcParam vectId;
CSL_Status status;
CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
/* set the timer in to one shot mode */
CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_ENABLE;
/* set the timer mode to GPT mode */
hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_GPT;
/* load the PRDLO */
hwSetup.tmrTimerPeriodLo = 0x0f;
/* load the PRDHI */
hwSetup.tmrTimerPeriodHi = 0x00;
/* Clear local data structures */
memset(&TmrObj, 0, sizeof(CSL_TmrObj));
printf("\n\n\n\nRunning Gp Timer with INTC....\n");
/**************************************************************
* INTC related code *
**************************************************************/
/* Open INTC */
vectId = CSL_INTC_VECTID_12;
tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, CSL_INTC_EVENTID_TINTLO0,\
&vectId, NULL);
vectId = CSL_INTC_VECTID_13;
tmrIntcHandle1 = CSL_intcOpen(&tmrIntcObj1, CSL_INTC_EVENTID_TINTHI0,\
&vectId, NULL);
/* Bind ISR to Interrupt */
EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
EventRecord.arg = (void *)tmrIntcHandle;
CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);
EventRecord1.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
EventRecord1.arg = (void *)tmrIntcHandle1;
CSL_intcPlugEventHandler(tmrIntcHandle1, &EventRecord1);
/* Event Enable */
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);
CSL_intcHwControl(tmrIntcHandle1, CSL_INTC_CMD_EVTENABLE, NULL);
/**************************************************************/
/* Initialize timer CSL module */
CSL_tmrInit(NULL);
hTmr = CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);
CSL_tmrHwSetup(hTmr, &hwSetup);
/* Reset the Timer */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);
/* Start the timer with one shot*/
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START64, (void *)&TimeCountMode);
/**************************************************************
* INTC related code *
**************************************************************/
while (1) {
if (intrCnt == 1)
break;
}
/**************************************************************/
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);
CSL_intcHwControl(tmrIntcHandle1, CSL_INTC_CMD_EVTDISABLE, NULL);
printf("INTR: The Total number of Events occured are: 0x%d\n", intrCnt);
intrCnt = 0;
/* Stop the Timer */
CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);
printf("Example for 64-bit timer mode completed\n");
/* Close the Tmr instance */
CSL_tmrClose(hTmr);
CSL_intcClose(tmrIntcHandle);
}
/*
* =============================================================================
* @func tmrWdtModeDemo
*
* @arg
* NONE
*
* @desc
* This demonstrates the Setting of timer to watchdog mode with INTC.
*
* @return
* NONE
*
* =============================================================================
*/
void tmrWdtModeDemo (
void
)
{
CSL_TmrObj TmrObj;
CSL_Status status;
CSL_IntcParam vectId;
CSL_IntcEventHandlerRecord EventRecord;
Uint16 loadVal;
CSL_TmrHwSetup hwSetup = CSL_TMR_HWSETUP_DEFAULTS;
/* set the timer in to countinuos mode and it is must for watchdog mode */
CSL_TmrEnamode TimeCountMode = CSL_TMR_ENAMODE_CONT;
CSL_IntcEventId eventId = CSL_INTC_EVENTID_TINTLO0;
/* set the timer mode to WATCHDOG mode */
hwSetup.tmrTimerMode = CSL_TMR_TIMMODE_WDT;
hwSetup.tmrPulseWidthLo = CSL_TMR_PWID_THREECLKS;
hwSetup.tmrClksrcLo = CSL_TMR_CLKSRC_INTERNAL;
hwSetup.tmrClockPulseLo = CSL_TMR_CP_PULSE;
hwSetup.tmrClockPulseHi = CSL_TMR_CP_PULSE;
hwSetup.tmrIpGateLo = CSL_TMR_CLOCK_INP_NOGATE;
/* load the PRDLO */
hwSetup.tmrTimerPeriodLo = 0x100;
/* load the PRDHI */
hwSetup.tmrTimerPeriodHi = 0x0;
/* Clear local data structures */
memset(&TmrObj, 0, sizeof(CSL_TmrObj));
printf("\n\n\n\n Running the GP timer in watchdog mode with INTC......\n");
/**************************************************************
* INTC related code *
**************************************************************/
/* Open INTC */
vectId = CSL_INTC_VECTID_12;
if (IntcInstance == 1)
eventId = eventId + 2;
tmrIntcHandle = CSL_intcOpen(&tmrIntcObj, eventId, &vectId, NULL);
/* Bind ISR to Interrupt */
EventRecord.handler = (CSL_IntcEventHandler)&TimerInterruptHandler;
EventRecord.arg = (void *)tmrIntcHandle;
CSL_intcPlugEventHandler(tmrIntcHandle, &EventRecord);
/* Event Enable */
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);
/**************************************************************/
/* Initialize timer CSL module */
status = CSL_tmrInit(NULL);
hTmr = CSL_tmrOpen(&TmrObj, IntcInstance, NULL, &status);
CSL_tmrHwSetup(hTmr, &hwSetup);
/* Reset the Timer */
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_RESET64, NULL);
/* Start the timer in continuous mode*/
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_WDT, \
(void *)&TimeCountMode);
/* Watchdog timer service key1 */
loadVal = CSL_TMR_WDTCR_WDKEY_CMD1;
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_WDKEY, \
(Uint16 *) &loadVal);
/* Watchdog timer service key2 */
loadVal = CSL_TMR_WDTCR_WDKEY_CMD2;
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_LOAD_WDKEY, \
(Uint16 *)&loadVal);
/**************************************************************
* INTC related code *
**************************************************************/
while (1) {
if (intrCnt == 1)
break;
}
/**************************************************************/
CSL_intcHwControl(tmrIntcHandle, CSL_INTC_CMD_EVTDISABLE, NULL);
printf("INTR: The Total number of Events occured are: 0x%d\n", intrCnt);
intrCnt = 0;
printf("Example for Watch dog mode completed\n");
/* Close the Tmr instance */
status = CSL_tmrClose(hTmr);
CSL_intcClose(tmrIntcHandle);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/mcbsp/_csl_mcbspResetCtrl.c
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file _csl_mcbspResetCtrl.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API _CSL_mcbspResetCtrl()
*
*/
/* =============================================================================
* Revision History
* ================
* June 29,2004 <NAME> - Created
*
* =============================================================================
*/
#include <csl_mcbsp.h>
#include <_csl_mcbsp.h>
/* ============================================================================
* @n@b _CSL_mcbspResetCtrl
*
* @b Description
* @n Enable/Disable Frame Sync Logic/Sample Rate Generator and Receiver and
* Transmitter Operation
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
selectMask Selects enable/disable of receiverCfg/transmitter.
Bitwise OR of MCBSP_CTRL_XXXX
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before _CSL_mcbspResetCtrl() can be called.
*
* <b> Post Condition </b>
* @n Sets/Resets Frame Sync Logic/Sample Rate Generator and Receiver and
* Transmitter Operation
*
* @b Modifies
* @n MCBSP registers
*
* @b Example
* @verbatim
CSL_McbspHandle hMcbsp;
...
hMcbsp = CSL_mcbspOpen(hMcbsp, CSL_MCBSP_1,NULL, &status );
...
_CSL_mcbspResetCtrl( hMcbsp, CSL_MCBSP_CTRL_SRG_ENABLE
|CSL_MCBSP_CTRL_FSYNC_DISABLE
|CSL_MCBSP_CTRL_RX_ENABLE
|CSL_MCBSP_CTRL_TX_ENABLE );
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (_CSL_mcbspResetCtrl, ".text:csl_section:mcbsp");
void _CSL_mcbspResetCtrl (
CSL_McbspHandle hMcbsp,
CSL_BitMask16 selectMask
)
{
CSL_McbspRegsOvly mcbspRegs = hMcbsp->regs;
if(selectMask & CSL_MCBSP_CTRL_FSYNC_ENABLE)
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_FRST, 1);
if(selectMask & CSL_MCBSP_CTRL_SRG_ENABLE)
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_GRST, 1);
if(selectMask & CSL_MCBSP_CTRL_FSYNC_DISABLE)
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_FRST, 0);
if(selectMask & CSL_MCBSP_CTRL_SRG_DISABLE)
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_GRST, 0);
if(selectMask & CSL_MCBSP_CTRL_RX_ENABLE)
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_RRST, 1);
if(selectMask & CSL_MCBSP_CTRL_TX_ENABLE)
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_XRST, 1);
if(selectMask & CSL_MCBSP_CTRL_RX_DISABLE)
CSL_FINS( mcbspRegs->SPCR, MCBSP_SPCR_RRST, 0);
if(selectMask & CSL_MCBSP_CTRL_TX_DISABLE)
CSL_FINS(mcbspRegs->SPCR, MCBSP_SPCR_XRST, 0);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/common/csl_edma3GetBaseAddress.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/src/common/csl_edma3GetBaseAddress.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3GetBaseAddress.c
*
* @path $(CSLPATH)\src\common
*
* @desc CSL Implementation of CSL_edma3ccGetModuleBaseAddr
*
*/
/* =============================================================================
* Revision History
* ===============
* 01-Jun-2004 <NAME> File Created.
* 09-Aug-2006 NG Added condition to check the invalid parameter
*
* =============================================================================
*/
#include <soc.h>
#include <csl_edma3.h>
/** ============================================================================
* @n@b CSL_edma3ccGetModuleBaseAddr
*
* @b Description
* @n This function is used for getting the base-address of the peripheral
* instance. This function will be called inside the @ CSL_edma3Open()/
* CSL_edma3ChannelOpen() function call.
*
* Note: This function is open for re-implementing if the user wants to
* modify the base address of the peripheral object to point to a
* different location and there by allow CSL initiated write/reads into
* peripheral MMR's go to an alternate location.
*
* @b Arguments
* @verbatim
edmaNum Specifies the instance of the edma to be opened.
pParam Module specific parameters.
pBaseAddress Pointer to baseaddress structure containing base
address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK Successful on getting the base
* address of edma3
* @li CSL_ESYS_FAIL The instance number is invalid.
* @li CSL_ESYS_INVPARAMS Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base Address structure is populated
*
* @b Modifies
* @li The status variable
* @li Base address structure is modified.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_Edma3ModuleBaseAddress baseAddress;
...
status = CSL_edma3ccGetModuleBaseAddr(CSL_EDMA3, NULL, &baseAddress);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_edma3ccGetModuleBaseAddr, ".text:csl_section:edma");
CSL_Status CSL_edma3ccGetModuleBaseAddr (
CSL_InstNum edmaNum,
CSL_Edma3ModuleAttr *pParam,
CSL_Edma3ModuleBaseAddress *pBaseAddress
)
{
CSL_Status status = CSL_SOK;
if (pBaseAddress == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (edmaNum) {
case CSL_EDMA3:
pBaseAddress->regs = (CSL_Edma3ccRegsOvly)CSL_EDMA3CC_0_REGS;
break;
default:
pBaseAddress->regs = (CSL_Edma3ccRegsOvly)NULL;
status = CSL_ESYS_FAIL;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_edma3Aux.h
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/inc/csl_edma3Aux.h
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file csl_edmaAux.h
*
* @path $(CSLPATH)\inc
*
* @desc Auxillary Header file for EDMA
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* =============================================================================
*/
#ifndef _CSL_EDMA3AUX_H_
#define _CSL_EDMA3AUX_H_
#define CSL_IDEF_INLINE static inline
/*
* Status query functions of the Edma Module
*/
/* ============================================================================
* @n@b CSL_edma3GetEventMissed
*
* @b Description
* @n Queries all the events missed.Since there may be upto 64 EDMA
* channels + upto 8 QDMA channels,this points to an array of 3,
* 32 bit elements.Gets the status of the missed events.
*
* @b Arguments
* @verbatim
hModule Module Handle
missedLo missed [0] - holds status from EMR
missedHi missed [1] - holds status from EMRH
missedQdma missed [2] - holds status from QEMR
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always returns CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3GetEventsMissed() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_BitMask32 missedEdmaHi,missedEdma, missedQdma;
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
// Get missed events
status = CSL_edma3GetEventMissed(hModule, &missedEdma, &missedEdmaHi,
&missedQdma);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3GetEventMissed (
CSL_Edma3Handle hModule,
CSL_BitMask32 *missedLo,
CSL_BitMask32 *missedHi,
CSL_BitMask32 *missedQdma
)
{
/* Reading the missed Status registers */
*missedLo = hModule->regs->EMR;
*missedHi = hModule->regs->EMRH;
*missedQdma = hModule->regs->QEMR;
return CSL_SOK;
}
/* ============================================================================
* @n@b CSL_edma3GetControllerError
*
* @b Description
* @n Gets the status of the controller Error.
*
* @b Arguments
* @verbatim
hModule Module Handle
ccStat This points to a structure allocated by the user
program that can hold the queried status values.
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always returns CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3GetControllerError() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i,passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj,
CSL_EDMA3,
&chAttr,
&status);
// Get Controller Error
status = CSL_edma3GetControllerError(hModule,&ccError);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3GetControllerError (
CSL_Edma3Handle hModule,
CSL_Edma3CtrlErrStat *ccStat
)
{
ccStat->error = hModule->regs->CCERR & 0xFF ;
ccStat->exceedTcc = (Bool)(CSL_FEXT(hModule->regs->CCERR, \
EDMA3CC_CCERR_TCCERR)) ;
return CSL_SOK;
}
/* ============================================================================
* @n@b CSL_edma3GetIntrPendStatus
*
* @b Description
* @n Queries the interrupt status of the interrupts.This is read from the
* Global Channel Register.Gets the interrupt pend status.
*
* @b Arguments
* @verbatim
hModule Module Handle
region Region
intrLo Status 0-31 of the interrupts
intrHi Status 32-63 of the interrupts
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Returns CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3GetIntrPendStatus() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj,
CSL_EDMA3,
&chAttr,
&status);
// Get interrupt pend status
status = CSL_edma3GetIntrPendStatus(hModule,CSL_EDMA3_REGION_0,
&edmaIntrLo, &edmaIntrHi);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3GetIntrPendStatus (
CSL_Edma3Handle hModule,
Int region,
CSL_BitMask32 *intrLo,
CSL_BitMask32 *intrHi
)
{
if (region != CSL_EDMA3_REGION_GLOBAL) {
*intrLo = hModule->regs->SHADOW[region].IPR ;
*intrHi = hModule->regs->SHADOW[region].IPRH ;
}
else {
*intrLo = hModule->regs->IPR ;
*intrHi = hModule->regs->IPRH ;
}
return CSL_SOK;
}
#if CSL_EDMA3_MEMPROTECT
/* ============================================================================
* @n@b CSL_edma3GetMemoryProtectionAttrib
*
* @b Description
* @n Queries the Memory Access rights of the specified region. This
* may be global/view.Gets the memory protection attributes.
*
* @b Arguments
* @verbatim
hModule Module Handle
region Region queried. This may refer to the global channel
register space or a specific region/view.
* @endverbatim
*
* <b> Return Value </b> CSL_BitMask32
* @n Memory protection attributes - MPPAG/MPPA[0/1../n]
* value
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3GetMemoryProtectAttrib() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1,memprot;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj,
CSL_EDMA3,
&chAttr,
&status);
// Get memory protection attributes
memProt = CSL_edma3GetMemoryProtectAttrib(hModule,CSL_EDMA3_REGION_2);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_BitMask32 CSL_edma3GetMemoryProtectionAttrib (
CSL_Edma3Handle hModule,
Int region
)
{
/* Memory protection page fault attribute */
CSL_BitMask32 mppa;
if (region < 0) {
mppa = hModule->regs->MPPAG;
}
else {
mppa = hModule->regs->MPPA[region];
}
return mppa;
}
/* ============================================================================
* @n@b CSL_edma3GetMemoryFaultError
*
* @b Description
* @n Queries the Channel controllers memory fault error and the error
* attributes.Gets the memory fault status details, clears the fault.
*
* @b Arguments
* @verbatim
hModule Module Handle
memFault This points to a structure alloctaed by the user
program that can hold the queried the memory fault
status values
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always returns CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3GetMemoryFaultError() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3,&chAttr, &status);
// Get memory protection fault
status = CSL_edma3GetMemoryFaultError(hModule,&memFault);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3GetMemoryFaultError (
CSL_Edma3Handle hModule,
CSL_Edma3MemFaultStat *memFault
)
{
/* Reading the Memory Fault Status registers */
memFault->addr = hModule->regs->MPFAR;
memFault->error = CSL_FEXTR(hModule->regs->MPFSR, 8, 0);
memFault->fid = CSL_FEXTR(hModule->regs->MPFSR, 12, 9);
return CSL_SOK;
}
#endif
/* =============================================================================
* @n@b CSL_edma3SetMemoryProtectionAttrib
*
* @b Description
* @n This API sets the memory protection attributes for the specified region.
* Sets specified memory protection attributes for the specifed region.
*
* @b Arguments
* @verbatim
hModule Module Handle
edmaRegion region - this may be specified as one of the many view
supported by the chip or the global memory protection
attributes themselves.
mpa Value to be programmed into the MPPAG/MPPA[0/1/2/../n]
This is a Bitmask of the protection attributes.
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always returns CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3SetMemoryProtectionAttrib() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i,passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3,&chAttr, &status);
// Module Control API
status = CSL_edma3SetMemoryProtectionAttrib (
hModule,CSL_EDMA3_REGION_0,
(CSL_EDMA3_MEMACCESS_UX \
|CSL_EDMA3_MEMACCESS_UW \
|CSL_EDMA3_MEMACCESS_UR \
|CSL_EDMA3_MEMACCESS_AID2));
...
@endverbatim
* ===========================================================================
*/
#if CSL_EDMA3_MEMPROTECT
CSL_IDEF_INLINE CSL_Status CSL_edma3SetMemoryProtectionAttrib(
CSL_Edma3Handle hModule,
Int edmaRegion,
CSL_BitMask32 mppa
)
{
if (edmaRegion == CSL_EDMA3_REGION_GLOBAL) {
hModule->regs->MPPAG = mppa;
}
else {
hModule->regs->MPPA[edmaRegion] = mppa;
}
return CSL_SOK;
}
#endif
/* =============================================================================
* @n@b CSL_edma3DmaRegionAccessEnable
*
* @b Description
* @n This API sets the DRAE/DRAEH BitMask.Enables shadow region access bits
* DRAE,DRAEH.
*
* @b Arguments
* @verbatim
hModule Module Handle
edmaRegion Region - this may be specified as one of the many view
supported by the chip or the global memory protection
attributes themselves.
access Region bits to be programmed
drae Bitmask to be enabled in DRAE
draeh Bitmask to be enabled in DRAEH
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n CSL_SOK - Region access enable success
* @n CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3DmaRegionAccessEnable() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Enable shadow region access bits DRAE,DRAEH
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj,
CSL_EDMA3,
&chAttr,
&status);
// Module Control API
status = CSL_edma3DmaRegionAccessEnable(hModule, CSL_EDMA3_REGION_0,
0x000000FF, 0x000000FF);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3DmaRegionAccessEnable (
CSL_Edma3Handle hModule,
Int edmaRegion,
CSL_BitMask32 drae,
CSL_BitMask32 draeh
)
{
if (edmaRegion == CSL_EDMA3_REGION_GLOBAL) {
return CSL_ESYS_INVPARAMS;
}
hModule->regs->DRA[edmaRegion].DRAE |= drae;
hModule->regs->DRA[edmaRegion].DRAEH |= draeh;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3DmaRegionAccessDisable
*
* @b Description
* @n This API clears the DRAE/DRAEH BitMask..Disable shadow region access bits
* DRAE,DRAEH.
*
* @b Arguments
* @verbatim
hModule Module Handle
edmaRegion Region - this may be specified as one of the many view
supported by the chip or the global memory protection
attributes themselves.
access Region bits to be programmed
drae Bitmask to be enabled in DRAE
draeh Bitmask to be enabled in DRAEH
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n CSL_SOK - Region access disable success
* @n CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3DmaRegionAccessEnable() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Disables shadow region access bits DRAE,DRAEH
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3,&chAttr, &status);
// Module Control API
status = CSL_edma3DmaRegionAccessDisable(hModule,CSL_EDMA3_REGION_0,
0x000000FF,0x000000FF);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3DmaRegionAccessDisable (
CSL_Edma3Handle hModule,
Int edmaRegion,
CSL_BitMask32 drae,
CSL_BitMask32 draeh
)
{
if (edmaRegion == CSL_EDMA3_REGION_GLOBAL) {
return CSL_ESYS_INVPARAMS;
}
hModule->regs->DRA[edmaRegion].DRAE &= ~drae;
hModule->regs->DRA[edmaRegion].DRAEH &= ~draeh;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3QdmaRegionAccessEnable
*
* @b Description
* @n This API sets the QRAE BitMask.Enables shadow region access bits QRAE
*
* @b Arguments
* @verbatim
hModule Module Handle
edmaRegion Region - this may be specified as one of the many view
supported by the chip or the global memory protection
attributes themselves.
qrae Bitmask to be enabled in QRAE
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n CSL_SOK - Qdma Region access enable success
* @n CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3QdmaRegionAccessEnable() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Enable Qdma shadow region access bits QRAE
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
// Module Control API
status = CSL_edma3QdmaRegionAccessEnable(hModule,CSL_EDMA3_REGION_0,
0x0000000F);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3QdmaRegionAccessEnable (
CSL_Edma3Handle hModule,
Int edmaRegion,
CSL_BitMask32 qrae
)
{
if (edmaRegion == CSL_EDMA3_REGION_GLOBAL) {
return CSL_ESYS_INVPARAMS;
}
hModule->regs->QRAE[edmaRegion] |= qrae;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3QdmaRegionAccessDisable
*
* @b Description
* @n This API clears the QRAE BitMask.Disables shadow region access bits QRAE
*
* @b Arguments
* @verbatim
hModule Module Handle
edmaRegion Region - this may be specified as one of the many view
supported by the chip or the global memory protection
attributes themselves.
access Region bits to be programmed
qrae Bitmask to be enabled in QRAE
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n CSL_SOK - Qdma Region access enable success
* @n CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3QdmaRegionAccessDisable() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Disables Qdma shadow region access bits QRAE
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
// 4 channels disallowed
status = CSL_edma3QdmaRegionAccessDisable(hModule,CSL_EDMA3_REGION_0,
0x000000FF);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3QdmaRegionAccessDisable (
CSL_Edma3Handle hModule,
Int edmaRegion,
CSL_BitMask32 qrae
)
{
if (edmaRegion == CSL_EDMA3_REGION_GLOBAL) {
return CSL_ESYS_INVPARAMS;
}
hModule->regs->QRAE[edmaRegion] &= ~qrae;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3EventQueuePrioritySet
*
* @b Description
* @n This API sets the Queue priority level to the appropriate value.
*
* @b Arguments
* @verbatim
hModule Module Handle
que Event queue
pri Priority needed to be set for above Event queue
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3EventQueuePrioritySet() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Set event queue priority
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
status = CSL_edma3EventQueuePrioritySet(hModule,CSL_EDMA3_QUE_0,
CSL_EDMA3_QUE_PRI2);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3EventQueuePrioritySet (
CSL_Edma3Handle hModule,
CSL_Edma3Que que,
CSL_Edma3QuePri pri
)
{
CSL_FINSR(hModule->regs->QUEPRI, (4 * que + 2), (4 * que), pri);
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_Edma3QueThresholdSet
*
* @b Description
* @n Sets the specified threshold for the specified queue.This API sets the
* Queue threshold to the appropriate level.
*
* @b Arguments
* @verbatim
hModule Module Handle
que Event queue
threshold Target threshold value for the above queue.
* @endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_Edma3QueThresholdSet() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
status = CSL_edma3EventQueueThresholdSet(hModule,CSL_EDMA3_QUE_0,
CSL_EDMA3_QUE_THR9);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3EventQueueThresholdSet (
CSL_Edma3Handle hModule,
CSL_Edma3Que que,
CSL_Edma3QueThr threshold
)
{
CSL_FINSR(hModule->regs->QWMTHRA, (8 * que + 4),(8 * que),threshold);
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3ErrorEval
*
* @b Description
* @n This API enables enables evaluation of errros for the specified
* view/shadow region.Sets EVAL bit of the EEVAL register in the Global
* register space
*
* @b Arguments
* @verbatim
hModule Module Handle
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3ErrorEval() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
status = CSL_edma3ErrorEval(hModule);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3ErrorEval (
CSL_Edma3Handle hModule
)
{
hModule->regs->EEVAL = 1;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3InterruptEnable
*
* @b Description
* @n Enables the specified interrupt in the Global Channel register space.
* This API enables the interrupts as specified in the BitMask.
*
* @b Arguments
* @verbatim
hModule Module Handle
region Region Number
intrLo Interrupt 0-31 (BitMask32) to be enabled
intrHi Interrupt 32-63 (BitMask32) to be enabled
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3InterruptEnable() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
// Interrupts 5-7 enabled
status = CSL_edma3InterruptEnable(hModule,0x000000E0, 0x0);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3InterruptEnable (
CSL_Edma3Handle hModule,
Int region,
CSL_BitMask32 intrLo,
CSL_BitMask32 intrHi
)
{
if (region != CSL_EDMA3_REGION_GLOBAL) {
hModule->regs->SHADOW[region].IESR = intrLo;
hModule->regs->SHADOW[region].IESRH = intrHi;
}
else {
hModule->regs->IESR = intrLo;
hModule->regs->IESRH = intrHi;
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3InterruptDisable
*
* @b Description
* @n Disables the specified interrupt in the Global Channel register space.
* This API disables the interrupts as specified in the BitMask.
*
* @b Arguments
* @verbatim
hModule Module Handle
region Region Number
intrLo Interrupt 0-31 (BitMask32) to be disabled
intrHi Interrupt 32-63 (BitMask32) to be disabled
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3InterruptEnable() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
// Interrupts 5-7 disabled
status = CSL_edma3InterruptDisable(hModule,0x000000E0, 0x0);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3InterruptDisable (
CSL_Edma3Handle hModule,
Int region,
CSL_BitMask32 intrLo,
CSL_BitMask32 intrHi
)
{
if (region !=CSL_EDMA3_REGION_GLOBAL) {
hModule->regs->SHADOW[region].IECR = intrLo;
hModule->regs->SHADOW[region].IECRH = intrHi;
}
else {
hModule->regs->IECR = intrLo;
hModule->regs->IECRH = intrHi;
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3InterruptClear
*
* @b Description
* @n This API clears the interrupt as specified.Clears the specified
* interrupt in the Global Channel register space.
*
* @b Arguments
* @verbatim
hModule Module Handle
region Region Number
intrLo Interrupt 0-31 (BitMask32) to be cleared
intrHi Interrupt 32-63 (BitMask32) to be cleared
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3InterruptClear() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
// 5,6,7 cleared
status = CSL_edma3InterruptClear(hModule,0x000000E0,0);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3InterruptClear (
CSL_Edma3Handle hModule,
Int region,
CSL_BitMask32 intrLo,
CSL_BitMask32 intrHi
)
{
if (region != CSL_EDMA3_REGION_GLOBAL) {
hModule->regs->SHADOW[region].ICR = intrLo;
hModule->regs->SHADOW[region].ICRH = intrHi;
}
else {
hModule->regs->ICR = intrLo;
hModule->regs->ICRH = intrHi;
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3InterruptEval
*
* @b Description
* @n If any enabled interrutps are pending, the tpcc_intN output signal
* to be pulsed.
*
* @b Arguments
* @verbatim
hModule Module Handle
region Region Number
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3InterruptEval() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj,CSL_EDMA3, &chAttr, &status);
// Interrupt Evaluate
status = CSL_edma3InterruptEval(hModule);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3InterruptEval (
CSL_Edma3Handle hModule,
Int region
)
{
if (region != CSL_EDMA3_REGION_GLOBAL) {
hModule->regs->SHADOW[region].IEVAL = 1;
}
else {
hModule->regs->IEVAL = 1;
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3MemFaultClear
*
* @b Description
* @n Clear Memory Fault.
*
* @b Arguments
* @verbatim
hModule Module Handle
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3MemFaultClear() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
//... Channel Setup, trigger
status = CSL_edma3MemFaultClear(hModule);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3MemFaultClear (
CSL_Edma3Handle hModule
)
{
hModule->regs->MPFCR = 1;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3ControllerErrorClear
*
* @b Description
* @n Channel Controller Error Fault.
*
* @b Arguments
* @verbatim
hModule Module Handle
ccStat Error Status Handle
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3ControllerErrorClear() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
CSL_Edma3CtrlErrStat ccstatErr;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
//... Channel Setup, trigger
// Obtain the status error
status = CSL_edma3GetControllerError(hModule,&ccstatErr);
// Clear the error
CSL_edma3ControllerErrorClear(hModule,&ccstatErr);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3ControllerErrorClear (
CSL_Edma3Handle hModule,
CSL_Edma3CtrlErrStat *ccStat
)
{
/* Clears the errors */
hModule->regs->CCERRCLR = CSL_FMK(EDMA3CC_CCERRCLR_TCCERR, \
ccStat->exceedTcc) | ccStat->error;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3EventMissedClear
*
* @b Description
* @n Clear the Event missed errors
*
* @b Arguments
* @verbatim
hModule Module Handle
missedLo Lower 32 of of the Event Missed register needing to
be cleared
missedHi Upper 32 of of the Event Missed register needing to
be cleared
missedQdma Bit mask of Qdma events missed needing to be cleared
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3EventMissedClear() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
CSL_BitMask32 missedLo, missedHi,qdmamissed;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
//... Channel Setup, trigger
// Obtain the events missed errors
status = CSL_edma3GetEventMissed(hModule,&missedLo, &missedHi, \
&qdmamissed);
// Clear the error
CSL_edma3EventMissedClear(hModule,missedLo, missedHi,qdmamissed);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3EventsMissedClear (
CSL_Edma3Handle hModule,
CSL_BitMask32 missedLo,
CSL_BitMask32 missedHi,
CSL_BitMask32 missedQdma
)
{
hModule->regs->EMCR = missedLo;
hModule->regs->EMCRH = missedHi;
hModule->regs->QEMCR = missedQdma;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3GetQueStatus
*
* @b Description
* @n Obtains the queue status
*
* @b Arguments
* @verbatim
hModule Module Handle
que queue for which status needs to be obtained
queStat Structure containing fields for the watermark,
threshold,number of valid entries, start pointer etc.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3GetQueStatus() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
CSL_Edma3QueStat queStat;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
// Get queue status
CSL_edma3GetQueStatus(hModule,CSL_EDMA3_QUE_0, &queStat);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3GetQueStatus (
CSL_Edma3Handle hModule,
CSL_Edma3Que que,
CSL_Edma3QueStat *queStat
)
{
Uint32 qstat = hModule->regs->QSTAT[que];
queStat->waterMark = (CSL_BitMask16)CSL_FEXT(qstat,EDMA3CC_QSTAT_WM);
queStat->numVal = (CSL_BitMask16)CSL_FEXT(qstat,EDMA3CC_QSTAT_NUMVAL);
queStat->startPtr = (Uint8)CSL_FEXT(qstat,EDMA3CC_QSTAT_STRTPTR);
queStat->exceed = (Bool)CSL_FEXT(qstat,EDMA3CC_QSTAT_THRXD);
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3GetActivityStatus
*
* @b Description
* @n Obtains the Channel Controller Activity Status
*
* @b Arguments
* @verbatim
hModule Module Handle
activityStat Activity Status
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3GetActivityStatus() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
CSL_Edma3ActivityStat activityStat;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr, &status);
// Obtain the Controller activity
status = CSL_edma3GetActivityStatus(hModule,&activityStat);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3GetActivityStatus (
CSL_Edma3Handle hModule,
CSL_Edma3ActivityStat *activityStat
)
{
Uint32 ccstat = hModule->regs->CCSTAT;
activityStat->active = (Bool)CSL_FEXT(ccstat,EDMA3CC_CCSTAT_ACTV);
activityStat->evtActive = (Bool)CSL_FEXT(ccstat,EDMA3CC_CCSTAT_EVTACTV);
activityStat->outstandingTcc = CSL_FEXT(ccstat,EDMA3CC_CCSTAT_COMPACTV);
activityStat->qevtActive = (Bool)CSL_FEXT(ccstat,EDMA3CC_CCSTAT_QEVTACTV);
activityStat->queActive = CSL_FEXTR(ccstat,23,16);
activityStat->trActive = (Bool)CSL_FEXT(ccstat,EDMA3CC_CCSTAT_TRACTV);
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3GetInfo
*
* @b Description
* @n Obtains the Channel Controller's Information
*
* @b Arguments
* @verbatim
hModule Module Handle
response Placeholder for the configuration and revision
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open(), must be called successfully in
* that order before CSL_edma3GetInfo() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
CSL_Edma3QueryInfo info;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Get Module Info
status = CSL_edma3GetInfo(hModule,&info);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3GetInfo (
CSL_Edma3Handle hModule,
CSL_Edma3QueryInfo *response
)
{
response->config = hModule->regs->CCCFG;
response->revision = hModule->regs->PID;
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3HwChannelEnable
*
* @b Description
* @n This API enables the event associated with the Channel. Enables
* the channel
*
* @b Arguments
* @verbatim
hEdma Channel Handle
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before CSL_edma3HwChannelEnable()
* can be called.If the channel is opened in context of a Region,may also
* need to be invoked before this API. If a Shadow region is used it
* should be ensured the DRAE/DRAEH is setup properly.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr,&status);
// Channel Enable
status = CSL_edma3ChannelEnable(hChannel);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3ChannelEnable(
CSL_Edma3ChannelHandle hEdma
)
{
/* Ensure this is a normal channel and not a QDMA channel */
if (hEdma->region == CSL_EDMA3_REGION_GLOBAL) {
if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH)
hEdma->regs->QEESR = (1 << (hEdma->chaNum - CSL_EDMA3_NUM_DMACH));
else if (hEdma->chaNum < 32)
hEdma->regs->EESR = (1 << hEdma->chaNum);
else
hEdma->regs->EESRH = (1 << (hEdma->chaNum - 32));
}
else {
if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH)
hEdma->regs->SHADOW[hEdma->region].QEESR = \
(1 << (hEdma->chaNum - CSL_EDMA3_NUM_DMACH));
else if (hEdma->chaNum < 32)
hEdma->regs->SHADOW[hEdma->region].EESR = (1 << hEdma->chaNum);
else
hEdma->regs->SHADOW[hEdma->region].EESRH =
(1 << (hEdma->chaNum - 32));
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3HwChannelDisable
*
* @b Description
* @n This API disables the event associated with the Channel. Disables
* the channel
*
* @b Arguments
* @verbatim
hEdma Channel Handle
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before CSL_edma3HwChannelDisable()
* can be called.If the channel is opened in context of a Region,
* CSL_edma3RegionOpen() may also need to be invoked before this API.
* If a Shadow region is used then care of the DRAE settings must be
* taken.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr,&status);
// Channel Disable
status = CSL_edma3ChannelDisable(hChannel);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3ChannelDisable(
CSL_Edma3ChannelHandle hEdma
)
{
/* Ensure this is a normal channel and not a QDMA channel */
if (hEdma->region ==CSL_EDMA3_REGION_GLOBAL) {
if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH)
hEdma->regs->QEECR = (1 << (hEdma->chaNum - CSL_EDMA3_NUM_DMACH));
else if (hEdma->chaNum < 32)
hEdma->regs->EECR = (1 << hEdma->chaNum);
else
hEdma->regs->EECRH = (1 << (hEdma->chaNum - 32));
} else {
if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH)
hEdma->regs->SHADOW[hEdma->region].QEECR =
(1 << (hEdma->chaNum - CSL_EDMA3_NUM_DMACH));
else if (hEdma->chaNum < 32)
hEdma->regs->SHADOW[hEdma->region].EECR = (1 << hEdma->chaNum);
else
hEdma->regs->SHADOW[hEdma->region].EECRH =
(1 << (hEdma->chaNum - 32));
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3ChannelEventSet
*
* @b Description
* @n Manually triggers an EDMA event by setting the ER register
*
* @b Arguments
* @verbatim
hEdma Channel Handle
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n CSL_SOK - Channel event set cmd success
* @n CSL_ESYS_INVPARAMS - Invalid Parameter
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before CSL_edma3ChannelEventSet()
* can be called.If the channel is opened in context of a Region, If a
* Shadow region is used then care of the @a CSL_edma3RegionOpen() may
* also need to be invoked before this API. DRAE settings must be taken.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr,&status);
// Channel Event set
status = CSL_edma3ChannelEventSet(hChannel);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3ChannelEventSet (
CSL_Edma3ChannelHandle hEdma
)
{
if (hEdma->region == CSL_EDMA3_REGION_GLOBAL) {
if (hEdma->chaNum < 32)
hEdma->regs->ESR = (1 << hEdma->chaNum);
else if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH)
hEdma->regs->ESRH = (1 << (hEdma->chaNum - 32));
else
return CSL_ESYS_INVPARAMS;
}
else {
if (hEdma->chaNum < 32)
hEdma->regs->SHADOW[hEdma->region].ESR = (1 << hEdma->chaNum);
else if (hEdma->chaNum < CSL_EDMA3_NUM_DMACH)
hEdma->regs->SHADOW[hEdma->region].ESRH =
(1 << (hEdma->chaNum - 32));
else
return CSL_ESYS_INVPARAMS;
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_edma3ChannelEventClear
*
* @b Description
* @n This API clears the event (if set) for the channel .Clears the EDMA
* event by writing the ECR register for normal channels for QDMA channels
*
* @b Arguments
* @verbatim
hEdma Channel Handle
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n CSL_SOK - Channel event clear cmd success
* @n CSL_ESYS_INVPARAMS - Invalid Parameter
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before CSL_edma3ChannelEventClear()
* can be called.If the channel is opened in context of a Region, If a
* Shadow region is used then care of the @a CSL_edma3RegionOpen() may
* also need to be invoked before this API. DRAE settings must be taken.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr,&status);
// Channel Event clear
status = CSL_edma3ChannelEventClear(hChannel);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_edma3ChannelEventClear (
CSL_Edma3ChannelHandle hEdma
)
{
if (hEdma->region ==CSL_EDMA3_REGION_GLOBAL) {
if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH)
return CSL_ESYS_INVPARAMS;
else if (hEdma->chaNum < 32)
hEdma->regs->ECR = (1 << hEdma->chaNum);
else
hEdma->regs->ECRH = (1 << (hEdma->chaNum - 32));
}
else {
if (hEdma->chaNum >= CSL_EDMA3_NUM_DMACH)
return CSL_ESYS_INVPARAMS;
else {
if (hEdma->chaNum < 32)
hEdma->regs->SHADOW[hEdma->region].ECR = (1 << hEdma->chaNum);
else
hEdma->regs->SHADOW[hEdma->region].ECRH =
(1 << (hEdma->chaNum - 32));
}
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_Edma3GetChannelStatus
*
* @b Description
* @n Obtains the Channel Status i.e whether an even is set.
*
* @b Arguments
* @verbatim
hChannel Channel Handle
response Place holder for whether an event is set or not
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before CSL_Edma3GetChannelStatus()
* can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr,&status);
// Get Channel Status
status = CSL_Edma3GetChannelStatus(hChannel,&event);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_Edma3GetChannelStatus(
CSL_Edma3ChannelHandle hChannel,
Bool *response
)
{
if (hChannel->chaNum < CSL_EDMA3_NUM_DMACH) {
if (hChannel->chaNum < 32) {
if (CSL_FEXTR(hChannel->regs->ER,hChannel->chaNum,hChannel->chaNum))
*response = TRUE;
else
*response = FALSE;
}
else {
if (CSL_FEXTR(hChannel->regs->ERH,hChannel->chaNum-32, \
hChannel->chaNum-32))
*response = TRUE;
else
*response = FALSE;
}
}
else {
if (CSL_FEXTR(hChannel->regs->QER,hChannel->chaNum-CSL_EDMA3_NUM_DMACH,\
hChannel->chaNum-CSL_EDMA3_NUM_DMACH))
*response = TRUE;
else
*response = FALSE;
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_Edma3GetChannelErrStatus
*
* @b Description
* @n Obtains the Channel Error Status.
*
* @b Arguments
* @verbatim
hChannel Channel Handle
response Place holder for whether an event error is set or not
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before CSL_Edma3GetChannelErrStatus()
* can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr,&status);
// Get Channel Error Status
status = CSL_Edma3GetChannelErrStatus(hChannel,&event);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_Edma3GetChannelErrStatus (
CSL_Edma3ChannelHandle hChannel,
CSL_Edma3ChannelErr *errClr
)
{
errClr->missed = FALSE;
errClr->secEvt = FALSE;
if (hChannel->chaNum < CSL_EDMA3_NUM_DMACH) {
if (hChannel->chaNum < 32) {
if (CSL_FEXTR(hChannel->regs->EMR,hChannel->chaNum,
hChannel->chaNum))
errClr->missed = TRUE;
if (CSL_FEXTR(hChannel->regs->SER,hChannel->chaNum,
hChannel->chaNum))
errClr->secEvt = TRUE;
}
else {
if (CSL_FEXTR(hChannel->regs->EMRH,hChannel->chaNum-32, \
hChannel->chaNum-32))
errClr->missed = TRUE;
if (CSL_FEXTR(hChannel->regs->SERH,hChannel->chaNum-32, \
hChannel->chaNum-32))
errClr->secEvt = TRUE;
}
}
else {
if (CSL_FEXTR(hChannel->regs->QEMR,hChannel->chaNum-CSL_EDMA3_NUM_DMACH,
hChannel->chaNum-CSL_EDMA3_NUM_DMACH))
errClr->missed = TRUE;
if (CSL_FEXTR(hChannel->regs->QSER,hChannel->chaNum-CSL_EDMA3_NUM_DMACH,
hChannel->chaNum-CSL_EDMA3_NUM_DMACH))
errClr->secEvt = TRUE;
}
return CSL_SOK;
}
/* =============================================================================
* @n@b CSL_Edma3ChannelErrorClear
*
* @b Description
* @n Clears the channel and associated error conditions:- Clears
* EMR/EMRH/QEMR and SER/SERH/QSER.
*
* @b Arguments
* @verbatim
hChannel Channel Handle
errClr Channel clear error bit
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @n Always return CSL_SOK
*
* <b> Pre Condition </b>
* @n All CSL_edma3Init(), CSL_edma3Open() and CSL_edma3ChannelOpen() must be
* called successfully in that order before CSL_Edma3ChannelErrorClear()
* can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup,gethwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing,hParamPong,hParamBasic;
CSL_Edma3ChannelObj ChObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
Uint32 i, passStatus = 1;
CSL_Edma3ChannelErr errClr;
// Module Initialization
CSL_edma3Init(&context);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&ChObj, CSL_EDMA3, &chAttr,&status);
// Clear Channel Error, clears SER/SERH/QSER and EMR/EMRH/QEMR.
CSL_Edma3ChannelErrorClear(hChannel, &errClr);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE CSL_Status CSL_Edma3ChannelErrorClear (
CSL_Edma3ChannelHandle hChannel,
CSL_Edma3ChannelErr *errClr
)
{
if (errClr->missed == TRUE) {
if (hChannel->chaNum < CSL_EDMA3_NUM_DMACH) {
if (hChannel->chaNum < 32) {
hChannel->regs->EMCR = 1 << hChannel->chaNum;
if (errClr->secEvt == TRUE)
hChannel->regs->SECR = 1 << hChannel->chaNum;
}
else {
hChannel->regs->EMCRH = 1 << (hChannel->chaNum - 32);
if (errClr->secEvt == TRUE)
hChannel->regs->SECRH = 1 << (hChannel->chaNum - 32);
}
}
else {
hChannel->regs->QEMR = 1 << (hChannel->chaNum - CSL_EDMA3_NUM_DMACH);
if (errClr->secEvt == TRUE)
hChannel->regs->QSECR = 1 << \
(hChannel->chaNum - CSL_EDMA3_NUM_DMACH);
}
}
return CSL_SOK;
}
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioHwSetupRaw.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioHwSetupRaw.c
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file csl_gpioHwSetupRaw.c
*
* @path $(CSLPATH)\src\gpio
*
* @desc File for functional layer of CSL API CSL_gpioHwSetupRaw()
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 07-Sep-2004 Nsr File Created.
* 28-Jul-2005 PSK updated changes to support only one BANK
* 06-Mar-2006 ds Updated the documentation
* ============================================================================
*/
#include <csl_gpio.h>
/** ===========================================================================
* @n@b CSL_gpioHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the Config Data structure. This configures registers
* based on a structure of register values, as compared to HwSetup, which
* configures registers based on structure of bit field values.
*
* @b Arguments
* @verbatim
hGpio Handle to the Gpio instance
config Pointer to config structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Invalid Parameters
*
* <b> Pre Condition </b>
* @n Both CSL_gpioInit() and CSL_gpioOpen() must be called successfully in
* order before this function.
*
* <b> Post Condition </b>
* @n The registers of the specified GPIO instance will be setup
* according to value passed.
*
* @b Modifies
* @n Hardware registers of the specified GPIO instance.
*
* @b Example
* @verbatim
CSL_GpioHandle hGpio;
CSL_GpioConfig config = CSL_GPIO_CONFIG_DEFAULTS;
CSL_Status status;
status = CSL_gpioHwSetupRaw (hGpio, &config);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_gpioHwSetupRaw, ".text:csl_section:gpio");
CSL_Status CSL_gpioHwSetupRaw (
CSL_GpioHandle hGpio,
CSL_GpioConfig *config
)
{
CSL_Status status = CSL_SOK;
if (hGpio == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (config == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
hGpio->regs->BINTEN = config->BINTEN;
hGpio->regs->DIR = config->DIR;
hGpio->regs->OUT_DATA = config->OUT_DATA;
hGpio->regs->SET_DATA = config->SET_DATA;
hGpio->regs->CLR_DATA = config->CLR_DATA;
hGpio->regs->SET_RIS_TRIG = config->SET_RIS_TRIG;
hGpio->regs->CLR_RIS_TRIG = config->CLR_RIS_TRIG;
hGpio->regs->SET_FAL_TRIG = config->SET_FAL_TRIG;
hGpio->regs->CLR_FAL_TRIG = config->CLR_FAL_TRIG;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2GetHwStatus.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2GetHwStatus.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_ddr2GetHwStatus.c
*
* @path $(CSLPATH)\src\ddr2
*
* @desc File for functional layer of CSL API @a CSL_ddr2GetHwStatus()
* - The @a CSL_ddr2GetHwStatus() function definition & it's
* associated functions.
*
*/
/* =============================================================================
* Revision History
* ===============
* 12-Apr-2005 RM File Created.
*
* 05-Oct-2005 NG Updation done according to new register layer
*
* =============================================================================
*/
#include <csl_ddr2.h>
#include <csl_ddr2Aux.h>
/** ============================================================================
* @n@b CSL_ddr2GetHwStatus
*
* @b Description
* @n This function is used to read the current device configuration, status
* flags and the value present associated registers. Following table details
* the various status queries supported and the associated data structure to
* record the response. User should allocate memory for the said data type and
* pass its pointer as an unadorned void* argument to the status query call.
* For details about the various status queries supported and the associated
* data structure to record the response, refer to @a CSL_Ddr2HwStatusQuery
*
* @b Arguments
* @verbatim
hDdr2 Pointer to the peripheral data object of the
DDR2 external memory interface instance
query The query to this API which indicates the status
to be returned
response Placeholder to return the status. @a void* casted
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware status call is
* successful
* @li CSL_ESYS_BADHANDLE - Not a valid Handle
* @li CSL_ESYS_INVPARAMS - Not a valid parameter
* @li CSL_ESYS_INVQUERY - Invalid Query
*
* <b> Pre Condition </b>
* Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called successfully
* in order before callinbg @a CSL_ddr2GetHwStatus(). For the argument type
* that can be @a void* casted & passed with a particular command refer to
* @a CSL_Ddr2HwStatusQuery
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Third parameter, response vlaue
*
* @b Example:
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Status status;
Uint16 response;
...
status = CSL_ddr2GetHwStatus(hDdr2,
CSL_DDR2_QUERY_REFRESH_RATE,
&response);
@endverbatim
*
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_ddr2GetHwStatus,".text:csl_section:ddr2");
CSL_Status CSL_ddr2GetHwStatus (
CSL_Ddr2Handle hDdr2,
CSL_Ddr2HwStatusQuery query,
void *response
)
{
CSL_Status status = CSL_SOK;
if(hDdr2 == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (response == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch(query) {
case CSL_DDR2_QUERY_REV_ID:
CSL_ddr2GetRevId(hDdr2,(CSL_Ddr2ModIdRev *)response);
break;
case CSL_DDR2_QUERY_REFRESH_RATE:
*(Uint16 *)response = CSL_ddr2GetRefreshRate(hDdr2);
break;
case CSL_DDR2_QUERY_SELF_REFRESH:
*(CSL_Ddr2SelfRefresh *)response = CSL_ddr2GetSlfRfrsh(hDdr2);
break;
case CSL_DDR2_QUERY_ENDIAN:
CSL_ddr2GetEndian(hDdr2,(Uint8*)response);
break;
case CSL_DDR2_QUERY_IFRDY:
CSL_ddr2GetIFRDY(hDdr2,(Uint8*)response);
break;
default:
status = CSL_ESYS_INVQUERY ;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_edma3tc.h
|
<filename>DSP/TI-Header/csl_c6455_src/inc/cslr_edma3tc.h
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_edma3tc.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for EDMA3TC
*/
#ifndef _CSLR_EDMA3TC_H_
#define _CSLR_EDMA3TC_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure for DFIREG
\**************************************************************************/
typedef struct {
volatile Uint32 DFOPT;
volatile Uint32 DFSRC;
volatile Uint32 DFCNT;
volatile Uint32 DFDST;
volatile Uint32 DFBIDX;
volatile Uint32 DFMPPRXY;
volatile Uint8 RSVD0[40];
} CSL_Edma3tcDfiregRegs;
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 PID;
volatile Uint32 TCCFG;
volatile Uint8 RSVD0[248];
volatile Uint32 TCSTAT;
volatile Uint8 RSVD1[28];
volatile Uint32 ERRSTAT;
volatile Uint32 ERREN;
volatile Uint32 ERRCLR;
volatile Uint32 ERRDET;
volatile Uint32 ERRCMD;
volatile Uint8 RSVD2[12];
volatile Uint32 RDRATE;
volatile Uint8 RSVD3[252];
volatile Uint32 SAOPT;
volatile Uint32 SASRC;
volatile Uint32 SACNT;
volatile Uint32 SADST;
volatile Uint32 SABIDX;
volatile Uint32 SAMPPRXY;
volatile Uint32 SACNTRLD;
volatile Uint32 SASRCBREF;
volatile Uint32 SADSTBREF;
volatile Uint8 RSVD4[28];
volatile Uint32 DFCNTRLD;
volatile Uint32 DFSRCBREF;
volatile Uint32 DFDSTBREF;
volatile Uint8 RSVD5[116];
CSL_Edma3tcDfiregRegs DFIREG[4];
} CSL_Edma3tcRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_Edma3tcRegs *CSL_Edma3tcRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* PID */
#define CSL_EDMA3TC_PID_PID_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_PID_PID_SHIFT (0x00000000u)
#define CSL_EDMA3TC_PID_PID_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_PID_RESETVAL (0x00000000u)
/* TCCFG */
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_MASK (0x00000300u)
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_SHIFT (0x00000008u)
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_RESETVAL (0x00000000u)
/*----DREGDEPTH Tokens----*/
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_2ENTRY (0x00000001u)
#define CSL_EDMA3TC_TCCFG_DREGDEPTH_4ENTRY (0x00000002u)
#define CSL_EDMA3TC_TCCFG_BUSWIDTH_MASK (0x00000030u)
#define CSL_EDMA3TC_TCCFG_BUSWIDTH_SHIFT (0x00000004u)
#define CSL_EDMA3TC_TCCFG_BUSWIDTH_RESETVAL (0x00000000u)
/*----BUSWIDTH Tokens----*/
#define CSL_EDMA3TC_TCCFG_BUSWIDTH_16BYTE (0x00000002u)
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_MASK (0x00000007u)
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_SHIFT (0x00000000u)
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_RESETVAL (0x00000000u)
/*----FIFOSIZE Tokens----*/
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_128BYTE (0x00000002u)
#define CSL_EDMA3TC_TCCFG_FIFOSIZE_256BYTE (0x00000003u)
#define CSL_EDMA3TC_TCCFG_RESETVAL (0x00000000u)
/* TCSTAT */
#define CSL_EDMA3TC_TCSTAT_DFSTRTPTR_MASK (0x00003000u)
#define CSL_EDMA3TC_TCSTAT_DFSTRTPTR_SHIFT (0x0000000Cu)
#define CSL_EDMA3TC_TCSTAT_DFSTRTPTR_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_MASK (0x00000070u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_SHIFT (0x00000004u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_RESETVAL (0x00000000u)
/*----DSTACTV Tokens----*/
#define CSL_EDMA3TC_TCSTAT_DSTACTV_EMPTY (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_1TR (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_2TR (0x00000002u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_3TR (0x00000003u)
#define CSL_EDMA3TC_TCSTAT_DSTACTV_4TR (0x00000004u)
#define CSL_EDMA3TC_TCSTAT_WSACTV_MASK (0x00000004u)
#define CSL_EDMA3TC_TCSTAT_WSACTV_SHIFT (0x00000002u)
#define CSL_EDMA3TC_TCSTAT_WSACTV_RESETVAL (0x00000000u)
/*----WSACTV Tokens----*/
#define CSL_EDMA3TC_TCSTAT_WSACTV_NONE (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_WSACTV_PEND (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_SRCACTV_MASK (0x00000002u)
#define CSL_EDMA3TC_TCSTAT_SRCACTV_SHIFT (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_SRCACTV_RESETVAL (0x00000000u)
/*----SRCACTV Tokens----*/
#define CSL_EDMA3TC_TCSTAT_SRCACTV_IDLE (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_SRCACTV_BUSY (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_MASK (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_SHIFT (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_RESETVAL (0x00000000u)
/*----PROGBUSY Tokens----*/
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_IDLE (0x00000000u)
#define CSL_EDMA3TC_TCSTAT_PROGBUSY_BUSY (0x00000001u)
#define CSL_EDMA3TC_TCSTAT_RESETVAL (0x00000100u)
/* ERRSTAT */
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_MASK (0x00000008u)
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_SHIFT (0x00000003u)
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_RESETVAL (0x00000000u)
/*----MMRAERR Tokens----*/
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_NONE (0x00000000u)
#define CSL_EDMA3TC_ERRSTAT_MMRAERR_ERROR (0x00000001u)
#define CSL_EDMA3TC_ERRSTAT_TRERR_MASK (0x00000004u)
#define CSL_EDMA3TC_ERRSTAT_TRERR_SHIFT (0x00000002u)
#define CSL_EDMA3TC_ERRSTAT_TRERR_RESETVAL (0x00000000u)
/*----TRERR Tokens----*/
#define CSL_EDMA3TC_ERRSTAT_TRERR_NONE (0x00000000u)
#define CSL_EDMA3TC_ERRSTAT_TRERR_ERROR (0x00000001u)
#define CSL_EDMA3TC_ERRSTAT_BUSERR_MASK (0x00000001u)
#define CSL_EDMA3TC_ERRSTAT_BUSERR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERRSTAT_BUSERR_RESETVAL (0x00000000u)
/*----BUSERR Tokens----*/
#define CSL_EDMA3TC_ERRSTAT_BUSERR_NONE (0x00000000u)
#define CSL_EDMA3TC_ERRSTAT_BUSERR_ERROR (0x00000001u)
#define CSL_EDMA3TC_ERRSTAT_RESETVAL (0x00000000u)
/* ERREN */
#define CSL_EDMA3TC_ERREN_MMRAERR_MASK (0x00000008u)
#define CSL_EDMA3TC_ERREN_MMRAERR_SHIFT (0x00000003u)
#define CSL_EDMA3TC_ERREN_MMRAERR_RESETVAL (0x00000000u)
/*----MMRAERR Tokens----*/
#define CSL_EDMA3TC_ERREN_MMRAERR_ENABLE (0x00000001u)
#define CSL_EDMA3TC_ERREN_MMRAERR_DISABLE (0x00000000u)
#define CSL_EDMA3TC_ERREN_TRERR_MASK (0x00000004u)
#define CSL_EDMA3TC_ERREN_TRERR_SHIFT (0x00000002u)
#define CSL_EDMA3TC_ERREN_TRERR_RESETVAL (0x00000000u)
/*----TRERR Tokens----*/
#define CSL_EDMA3TC_ERREN_TRERR_ENABLE (0x00000001u)
#define CSL_EDMA3TC_ERREN_TRERR_DISABLE (0x00000000u)
#define CSL_EDMA3TC_ERREN_BUSERR_MASK (0x00000001u)
#define CSL_EDMA3TC_ERREN_BUSERR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERREN_BUSERR_RESETVAL (0x00000000u)
/*----BUSERR Tokens----*/
#define CSL_EDMA3TC_ERREN_BUSERR_ENABLE (0x00000001u)
#define CSL_EDMA3TC_ERREN_BUSERR_DISABLE (0x00000000u)
#define CSL_EDMA3TC_ERREN_RESETVAL (0x00000000u)
/* ERRCLR */
#define CSL_EDMA3TC_ERRCLR_MMRAERR_MASK (0x00000008u)
#define CSL_EDMA3TC_ERRCLR_MMRAERR_SHIFT (0x00000003u)
#define CSL_EDMA3TC_ERRCLR_MMRAERR_RESETVAL (0x00000000u)
/*----MMRAERR Tokens----*/
#define CSL_EDMA3TC_ERRCLR_MMRAERR_CLEAR (0x00000001u)
#define CSL_EDMA3TC_ERRCLR_TRERR_MASK (0x00000004u)
#define CSL_EDMA3TC_ERRCLR_TRERR_SHIFT (0x00000002u)
#define CSL_EDMA3TC_ERRCLR_TRERR_RESETVAL (0x00000000u)
/*----TRERR Tokens----*/
#define CSL_EDMA3TC_ERRCLR_TRERR_CLEAR (0x00000001u)
#define CSL_EDMA3TC_ERRCLR_BUSERR_MASK (0x00000001u)
#define CSL_EDMA3TC_ERRCLR_BUSERR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERRCLR_BUSERR_RESETVAL (0x00000000u)
/*----BUSERR Tokens----*/
#define CSL_EDMA3TC_ERRCLR_BUSERR_CLEAR (0x00000001u)
#define CSL_EDMA3TC_ERRCLR_RESETVAL (0x00000000u)
/* ERRDET */
#define CSL_EDMA3TC_ERRDET_TCCHEN_MASK (0x00020000u)
#define CSL_EDMA3TC_ERRDET_TCCHEN_SHIFT (0x00000011u)
#define CSL_EDMA3TC_ERRDET_TCCHEN_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_ERRDET_TCINTEN_MASK (0x00010000u)
#define CSL_EDMA3TC_ERRDET_TCINTEN_SHIFT (0x00000010u)
#define CSL_EDMA3TC_ERRDET_TCINTEN_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_ERRDET_TCC_MASK (0x00003F00u)
#define CSL_EDMA3TC_ERRDET_TCC_SHIFT (0x00000008u)
#define CSL_EDMA3TC_ERRDET_TCC_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_ERRDET_STAT_MASK (0x0000000Fu)
#define CSL_EDMA3TC_ERRDET_STAT_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERRDET_STAT_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_ERRDET_RESETVAL (0x00000000u)
/* ERRCMD */
#define CSL_EDMA3TC_ERRCMD_EVAL_MASK (0x00000001u)
#define CSL_EDMA3TC_ERRCMD_EVAL_SHIFT (0x00000000u)
#define CSL_EDMA3TC_ERRCMD_EVAL_RESETVAL (0x00000000u)
/*----EVAL Tokens----*/
#define CSL_EDMA3TC_ERRCMD_EVAL_EVAL (0x00000001u)
#define CSL_EDMA3TC_ERRCMD_RESETVAL (0x00000000u)
/* RDRATE */
#define CSL_EDMA3TC_RDRATE_RDRATE_MASK (0x00000007u)
#define CSL_EDMA3TC_RDRATE_RDRATE_SHIFT (0x00000000u)
#define CSL_EDMA3TC_RDRATE_RDRATE_RESETVAL (0x00000000u)
/*----RDRATE Tokens----*/
#define CSL_EDMA3TC_RDRATE_RDRATE_AFAP (0x00000000u)
#define CSL_EDMA3TC_RDRATE_RDRATE_4CYCLE (0x00000001u)
#define CSL_EDMA3TC_RDRATE_RDRATE_8CYCLE (0x00000002u)
#define CSL_EDMA3TC_RDRATE_RDRATE_16CYCLE (0x00000003u)
#define CSL_EDMA3TC_RDRATE_RDRATE_32CYCLE (0x00000004u)
#define CSL_EDMA3TC_RDRATE_RESETVAL (0x00000000u)
/* SAOPT */
#define CSL_EDMA3TC_SAOPT_TCCHEN_MASK (0x00400000u)
#define CSL_EDMA3TC_SAOPT_TCCHEN_SHIFT (0x00000016u)
#define CSL_EDMA3TC_SAOPT_TCCHEN_RESETVAL (0x00000000u)
/*----TCCHEN Tokens----*/
#define CSL_EDMA3TC_SAOPT_TCCHEN_DISABLE (0x00000000u)
#define CSL_EDMA3TC_SAOPT_TCCHEN_ENABLE (0x00000001u)
#define CSL_EDMA3TC_SAOPT_TCINTEN_MASK (0x00100000u)
#define CSL_EDMA3TC_SAOPT_TCINTEN_SHIFT (0x00000014u)
#define CSL_EDMA3TC_SAOPT_TCINTEN_RESETVAL (0x00000000u)
/*----TCINTEN Tokens----*/
#define CSL_EDMA3TC_SAOPT_TCINTEN_DISABLE (0x00000000u)
#define CSL_EDMA3TC_SAOPT_TCINTEN_ENABLE (0x00000001u)
#define CSL_EDMA3TC_SAOPT_TCC_MASK (0x0003F000u)
#define CSL_EDMA3TC_SAOPT_TCC_SHIFT (0x0000000Cu)
#define CSL_EDMA3TC_SAOPT_TCC_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SAOPT_FWID_MASK (0x00000700u)
#define CSL_EDMA3TC_SAOPT_FWID_SHIFT (0x00000008u)
#define CSL_EDMA3TC_SAOPT_FWID_RESETVAL (0x00000000u)
/*----FWID Tokens----*/
#define CSL_EDMA3TC_SAOPT_FWID_8BIT (0x00000000u)
#define CSL_EDMA3TC_SAOPT_FWID_16BIT (0x00000001u)
#define CSL_EDMA3TC_SAOPT_FWID_32BIT (0x00000002u)
#define CSL_EDMA3TC_SAOPT_FWID_64BIT (0x00000003u)
#define CSL_EDMA3TC_SAOPT_FWID_128BIT (0x00000004u)
#define CSL_EDMA3TC_SAOPT_FWID_256BIT (0x00000005u)
#define CSL_EDMA3TC_SAOPT_PRI_MASK (0x00000070u)
#define CSL_EDMA3TC_SAOPT_PRI_SHIFT (0x00000004u)
#define CSL_EDMA3TC_SAOPT_PRI_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SAOPT_DAM_MASK (0x00000002u)
#define CSL_EDMA3TC_SAOPT_DAM_SHIFT (0x00000001u)
#define CSL_EDMA3TC_SAOPT_DAM_RESETVAL (0x00000000u)
/*----DAM Tokens----*/
#define CSL_EDMA3TC_SAOPT_DAM_INCR (0x00000000u)
#define CSL_EDMA3TC_SAOPT_DAM_CONST (0x00000001u)
#define CSL_EDMA3TC_SAOPT_SAM_MASK (0x00000001u)
#define CSL_EDMA3TC_SAOPT_SAM_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SAOPT_SAM_RESETVAL (0x00000000u)
/*----SAM Tokens----*/
#define CSL_EDMA3TC_SAOPT_SAM_INCR (0x00000000u)
#define CSL_EDMA3TC_SAOPT_SAM_CONST (0x00000001u)
#define CSL_EDMA3TC_SAOPT_RESETVAL (0x00000000u)
/* SASRC */
#define CSL_EDMA3TC_SASRC_SADDR_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_SASRC_SADDR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SASRC_SADDR_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SASRC_RESETVAL (0x00000000u)
/* SACNT */
#define CSL_EDMA3TC_SACNT_BCNT_MASK (0xFFFF0000u)
#define CSL_EDMA3TC_SACNT_BCNT_SHIFT (0x00000010u)
#define CSL_EDMA3TC_SACNT_BCNT_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SACNT_ACNT_MASK (0x0000FFFFu)
#define CSL_EDMA3TC_SACNT_ACNT_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SACNT_ACNT_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SACNT_RESETVAL (0x00000000u)
/* SADST */
#define CSL_EDMA3TC_SADST_DADDR_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_SADST_DADDR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SADST_DADDR_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SADST_RESETVAL (0x00000000u)
/* SABIDX */
#define CSL_EDMA3TC_SABIDX_DSTBIDX_MASK (0xFFFF0000u)
#define CSL_EDMA3TC_SABIDX_DSTBIDX_SHIFT (0x00000010u)
#define CSL_EDMA3TC_SABIDX_DSTBIDX_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SABIDX_SRCBIDX_MASK (0x0000FFFFu)
#define CSL_EDMA3TC_SABIDX_SRCBIDX_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SABIDX_SRCBIDX_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SABIDX_RESETVAL (0x00000000u)
/* SAMPPRXY */
#define CSL_EDMA3TC_SAMPPRXY_PRIV_MASK (0x00000100u)
#define CSL_EDMA3TC_SAMPPRXY_PRIV_SHIFT (0x00000008u)
#define CSL_EDMA3TC_SAMPPRXY_PRIV_RESETVAL (0x00000000u)
/*----PRIV Tokens----*/
#define CSL_EDMA3TC_SAMPPRXY_PRIV_USER (0x00000000u)
#define CSL_EDMA3TC_SAMPPRXY_PRIV_SUPERVISOR (0x00000001u)
#define CSL_EDMA3TC_SAMPPRXY_PRIVID_MASK (0x0000000Fu)
#define CSL_EDMA3TC_SAMPPRXY_PRIVID_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SAMPPRXY_PRIVID_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SAMPPRXY_RESETVAL (0x00000000u)
/* SACNTRLD */
#define CSL_EDMA3TC_SACNTRLD_ACNTRLD_MASK (0x0000FFFFu)
#define CSL_EDMA3TC_SACNTRLD_ACNTRLD_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SACNTRLD_ACNTRLD_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SACNTRLD_RESETVAL (0x00000000u)
/* SASRCBREF */
#define CSL_EDMA3TC_SASRCBREF_SADDRBREF_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_SASRCBREF_SADDRBREF_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SASRCBREF_SADDRBREF_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SASRCBREF_RESETVAL (0x00000000u)
/* SADSTBREF */
#define CSL_EDMA3TC_SADSTBREF_DADDRBREF_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_SADSTBREF_DADDRBREF_SHIFT (0x00000000u)
#define CSL_EDMA3TC_SADSTBREF_DADDRBREF_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_SADSTBREF_RESETVAL (0x00000000u)
/* DFCNTRLD */
#define CSL_EDMA3TC_DFCNTRLD_ACNTRLD_MASK (0x0000FFFFu)
#define CSL_EDMA3TC_DFCNTRLD_ACNTRLD_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFCNTRLD_ACNTRLD_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFCNTRLD_RESETVAL (0x00000000u)
/* DFSRCBREF */
#define CSL_EDMA3TC_DFSRCBREF_SADDRBREF_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_DFSRCBREF_SADDRBREF_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFSRCBREF_SADDRBREF_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFSRCBREF_RESETVAL (0x00000000u)
/* DFDSTBREF */
#define CSL_EDMA3TC_DFDSTBREF_DADDRBREF_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_DFDSTBREF_DADDRBREF_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFDSTBREF_DADDRBREF_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFDSTBREF_RESETVAL (0x00000000u)
/* DFOPT */
#define CSL_EDMA3TC_DFOPT_TCCHEN_MASK (0x00400000u)
#define CSL_EDMA3TC_DFOPT_TCCHEN_SHIFT (0x00000016u)
#define CSL_EDMA3TC_DFOPT_TCCHEN_RESETVAL (0x00000000u)
/*----TCCHEN Tokens----*/
#define CSL_EDMA3TC_DFOPT_TCCHEN_DISABLE (0x00000000u)
#define CSL_EDMA3TC_DFOPT_TCCHEN_ENABLE (0x00000001u)
#define CSL_EDMA3TC_DFOPT_TCINTEN_MASK (0x00100000u)
#define CSL_EDMA3TC_DFOPT_TCINTEN_SHIFT (0x00000014u)
#define CSL_EDMA3TC_DFOPT_TCINTEN_RESETVAL (0x00000000u)
/*----TCINTEN Tokens----*/
#define CSL_EDMA3TC_DFOPT_TCINTEN_DISABLE (0x00000000u)
#define CSL_EDMA3TC_DFOPT_TCINTEN_ENABLE (0x00000001u)
#define CSL_EDMA3TC_DFOPT_TCC_MASK (0x0003F000u)
#define CSL_EDMA3TC_DFOPT_TCC_SHIFT (0x0000000Cu)
#define CSL_EDMA3TC_DFOPT_TCC_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFOPT_FWID_MASK (0x00000700u)
#define CSL_EDMA3TC_DFOPT_FWID_SHIFT (0x00000008u)
#define CSL_EDMA3TC_DFOPT_FWID_RESETVAL (0x00000000u)
/*----FWID Tokens----*/
#define CSL_EDMA3TC_DFOPT_FWID_8BIT (0x00000000u)
#define CSL_EDMA3TC_DFOPT_FWID_16BIT (0x00000001u)
#define CSL_EDMA3TC_DFOPT_FWID_32BIT (0x00000002u)
#define CSL_EDMA3TC_DFOPT_FWID_64BIT (0x00000003u)
#define CSL_EDMA3TC_DFOPT_FWID_128BIT (0x00000004u)
#define CSL_EDMA3TC_DFOPT_FWID_256BIT (0x00000005u)
#define CSL_EDMA3TC_DFOPT_PRI_MASK (0x00000070u)
#define CSL_EDMA3TC_DFOPT_PRI_SHIFT (0x00000004u)
#define CSL_EDMA3TC_DFOPT_PRI_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFOPT_DAM_MASK (0x00000002u)
#define CSL_EDMA3TC_DFOPT_DAM_SHIFT (0x00000001u)
#define CSL_EDMA3TC_DFOPT_DAM_RESETVAL (0x00000000u)
/*----DAM Tokens----*/
#define CSL_EDMA3TC_DFOPT_DAM_INCR (0x00000000u)
#define CSL_EDMA3TC_DFOPT_DAM_FIFO (0x00000001u)
#define CSL_EDMA3TC_DFOPT_SAM_MASK (0x00000001u)
#define CSL_EDMA3TC_DFOPT_SAM_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFOPT_SAM_RESETVAL (0x00000000u)
/*----SAM Tokens----*/
#define CSL_EDMA3TC_DFOPT_SAM_INCR (0x00000000u)
#define CSL_EDMA3TC_DFOPT_SAM_FIFO (0x00000001u)
#define CSL_EDMA3TC_DFOPT_RESETVAL (0x00000000u)
/* DFSRC */
#define CSL_EDMA3TC_DFSRC_SADDR_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_DFSRC_SADDR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFSRC_SADDR_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFSRC_RESETVAL (0x00000000u)
/* DFCNT */
#define CSL_EDMA3TC_DFCNT_BCNT_MASK (0xFFFF0000u)
#define CSL_EDMA3TC_DFCNT_BCNT_SHIFT (0x00000010u)
#define CSL_EDMA3TC_DFCNT_BCNT_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFCNT_ACNT_MASK (0x0000FFFFu)
#define CSL_EDMA3TC_DFCNT_ACNT_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFCNT_ACNT_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFCNT_RESETVAL (0x00000000u)
/* DFDST */
#define CSL_EDMA3TC_DFDST_DADDR_MASK (0xFFFFFFFFu)
#define CSL_EDMA3TC_DFDST_DADDR_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFDST_DADDR_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFDST_RESETVAL (0x00000000u)
/* DFBIDX */
#define CSL_EDMA3TC_DFBIDX_DSTBIDX_MASK (0xFFFF0000u)
#define CSL_EDMA3TC_DFBIDX_DSTBIDX_SHIFT (0x00000010u)
#define CSL_EDMA3TC_DFBIDX_DSTBIDX_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFBIDX_SRCBIDX_MASK (0x0000FFFFu)
#define CSL_EDMA3TC_DFBIDX_SRCBIDX_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFBIDX_SRCBIDX_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFBIDX_RESETVAL (0x00000000u)
/* DFMPPRXY */
#define CSL_EDMA3TC_DFMPPRXY_PRIV_MASK (0x00000100u)
#define CSL_EDMA3TC_DFMPPRXY_PRIV_SHIFT (0x00000008u)
#define CSL_EDMA3TC_DFMPPRXY_PRIV_RESETVAL (0x00000000u)
/*----PRIV Tokens----*/
#define CSL_EDMA3TC_DFMPPRXY_PRIV_USER (0x00000000u)
#define CSL_EDMA3TC_DFMPPRXY_PRIV_SUPERVISOR (0x00000001u)
#define CSL_EDMA3TC_DFMPPRXY_PRIVID_MASK (0x0000000Fu)
#define CSL_EDMA3TC_DFMPPRXY_PRIVID_SHIFT (0x00000000u)
#define CSL_EDMA3TC_DFMPPRXY_PRIVID_RESETVAL (0x00000000u)
#define CSL_EDMA3TC_DFMPPRXY_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/cfg/csl_cfgClose.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<filename>DSP/TI-Header/csl_c6455_src/src/cfg/csl_cfgClose.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_cfgClose.c
*
* @path $(CSLPATH)\src\cfg
*
* @desc File for functional layer of CSL API CSL_cfgClose()
*
*/
/* ============================================================================
* Revision History
* ===============
* 11-Apr-2005 Brn updated the file for doxygen compatibiliy
* 31-Jan-2006 ds Added error checking
* ============================================================================
*/
#include <csl_cfg.h>
/** ============================================================================
* @n@b CSL_cfgClose
*
* @b Description
* @n This function closes the specified instance of CFG.
*
* @b Arguments
* @verbatim
hCfg Handle to the CFG instance
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - close successful
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n CSL_cfgInit() and @a CSL_cfgOpen() must be called successfully
* in that order before @a CSL_cfgClose() can be called.
*
* <b> Post Condition </b>
* @n The cfg CSL APIs can not be called until the cfg CSL is reopened
* again using CSL_cfgOpen()
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_cfgHandle hCfg;
...
CSL_cfgClose(hCfg);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_cfgClose, ".text:csl_section:cfg");
CSL_Status CSL_cfgClose (
CSL_CfgHandle hCfg
)
{
/* indicate in the CSL global data structure that the peripheral
* has been unreserved
*/
CSL_Status status = CSL_SOK;
if (hCfg != NULL) {
hCfg->regs = (CSL_CfgRegsOvly) NULL;
hCfg->cfgNum = (CSL_InstNum) - 1;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcHwSetup.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** @file csl_pllcHwSetup.c
*
* @brief File for functional layer of CSL API @a CSL_pllcHwSetup()
*
* Path: \(CSLPATH)\src\pllc
*/
/* ============================================================================
* Revision History
* ===============
* 25-Aug-2005 Tej File Created.
* 27-oct-2005 sd changes for multiplier configuration
* 18-Jan-2006 sd Changes according to spec changes
* ============================================================================
*/
#include <csl_pllc.h>
/** ============================================================================
* @n@b CSL_pllcHwSetup
*
* @b Description
* @n It configures the pllc registers as per the values passed
* in the hardware setup structure.
*
* @b Arguments
* @verbatim
hPllc Handle to the pllc
hwSetup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Hardware structure is not
properly initialized
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n PLLC registers are configured according
* to the hardware setup parameters
*
* @b Modifies
* @n PLLC registers
*
* @b Example
* @verbatim
CSL_PllcHandle hPllc;
CSL_PllcObj pllcObj;
CSL_PllcHwSetup hwSetup;
CSL_status status;
...
hPllc = CSL_pllcOpen(&pllcObj, CSL_PLLC_1, NULL, &status);
...
status = CSL_pllcHwSetup(hPllc, &hwSetup);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pllcHwSetup, ".text:csl_section:pllc");
CSL_Status CSL_pllcHwSetup (
CSL_PllcHandle hPllc,
CSL_PllcHwSetup *hwSetup
)
{
CSL_PllcRegsOvly pllcRegs = hPllc->regs;
CSL_Status status = CSL_SOK;
volatile unsigned int loopCount;
if (hPllc == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (hwSetup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
if (hPllc->pllcNum == CSL_PLLC_1) {
/*
* The registers PLLCTL, PREDIV, PLLM, PLLDIV4, PLLDIV5 are valid only for
* PLLC instance 1
*/
/* Set PLLCTL, PLLENSRC bit to 0 first to modify PLLEN bit */
CSL_FINS (pllcRegs->PLLCTL, PLLC_PLLCTL_PLLENSRC,
CSL_PLLC_PLLCTL_PLLENSRC_REGBIT);
/* Ensure that PLLCTL is not in the PLL Mode */
CSL_FINS (pllcRegs->PLLCTL, PLLC_PLLCTL_PLLEN,
CSL_PLLC_PLLCTL_PLLEN_BYPASS);
CSL_FINS (pllcRegs->PLLCTL, PLLC_PLLCTL_PLLRST,
CSL_PLLC_PLLCTL_PLLRST_YES);
/* Ensure that PLL is not in the Power-Down state */
CSL_FINS (pllcRegs->PLLCTL, PLLC_PLLCTL_PLLPWRDN,
CSL_PLLC_PLLCTL_PLLPWRDN_NO);
if (hwSetup->divEnable & CSL_PLLC_DIVEN_PREDIV) {
CSL_FINS (pllcRegs->PREDIV, PLLC_PREDIV_PREDEN,
CSL_PLLC_PREDIV_PREDEN_ENABLE);
CSL_FINS (pllcRegs->PREDIV, PLLC_PREDIV_RATIO, hwSetup->preDiv - 1);
}
else {
CSL_FINS (pllcRegs->PREDIV, PLLC_PREDIV_PREDEN,
CSL_PLLC_PREDIV_PREDEN_DISABLE);
}
CSL_FINS (pllcRegs->PLLM, PLLC_PLLM_PLLM, hwSetup->pllM - 1);
if (hwSetup->divEnable & CSL_PLLC_DIVEN_PLLDIV4) {
CSL_FINS (pllcRegs->PLLDIV4, PLLC_PLLDIV4_D4EN,
CSL_PLLC_PLLDIV4_D4EN_ENABLE);
CSL_FINS (pllcRegs->PLLDIV4, PLLC_PLLDIV4_RATIO, hwSetup->pllDiv4 - 1);
}
else {
CSL_FINS (pllcRegs->PLLDIV4, PLLC_PLLDIV4_D4EN,
CSL_PLLC_PLLDIV4_D4EN_DISABLE);
}
if (hwSetup->divEnable & CSL_PLLC_DIVEN_PLLDIV5) {
CSL_FINS (pllcRegs->PLLDIV5, PLLC_PLLDIV5_D5EN,
CSL_PLLC_PLLDIV5_D5EN_ENABLE);
CSL_FINS (pllcRegs->PLLDIV5, PLLC_PLLDIV5_RATIO, hwSetup->pllDiv5 - 1);
}
else {
CSL_FINS (pllcRegs->PLLDIV5, PLLC_PLLDIV5_D5EN,
CSL_PLLC_PLLDIV5_D5EN_DISABLE);
}
}
/* If Instance no. is CSL_PLLC_2 then only change PLLDIV1 */
if (hPllc->pllcNum == CSL_PLLC_2) {
if (hwSetup->divEnable & CSL_PLLC_DIVEN_PLLDIV1) {
CSL_FINS (pllcRegs->PLLDIV1, PLLC_PLLDIV1_D1EN,
CSL_PLLC_PLLDIV1_D1EN_ENABLE);
CSL_FINS (pllcRegs->PLLDIV1, PLLC_PLLDIV1_RATIO, hwSetup->pllDiv1 - 1);
}
else {
CSL_FINS (pllcRegs->PLLDIV1, PLLC_PLLDIV1_D1EN,
CSL_PLLC_PLLDIV1_D1EN_DISABLE);
}
}
/* Set GOSET bit to change/set the dividers */
CSL_FINS (pllcRegs->PLLCMD, PLLC_PLLCMD_GOSET, CSL_PLLC_PLLCMD_GOSET_SET);
while (CSL_FEXT (pllcRegs->PLLSTAT, PLLC_PLLSTAT_GOSTAT)) {
/* Poll for divide-ratio change and clock alignment to complete */
}
if (hPllc->pllcNum == CSL_PLLC_1) {
CSL_FINS (pllcRegs->PLLCTL, PLLC_PLLCTL_PLLRST, CSL_PLLC_PLLCTL_PLLRST_NO);
/* Wait for 4 cycles of the slowest of the CLKIN/OSCIN
* Introducing some arbitrary delay.
*/
loopCount = CSL_PLLC_DELAY_2000;
while (loopCount--) {
asm(" NOP");
}
CSL_FINS (pllcRegs->PLLCTL, PLLC_PLLCTL_PLLEN, hwSetup->pllMode);
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/edma/edma_ping_pong_xfer_gbl_reg/src/Edma_ping_pong_xfer_gbl_reg.c
|
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
*
* @file Edma_ping_pong_xfer_gbl_reg.c
*
* @path $(CSLPATH)\example\edma\edma_ping_pong_xfer_gbl_reg\src
*
* @desc Example of EDMA
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This is an example of the CSL EDMA usage for the channel Initialization
* for ping pong buffer transfer where channels are opened in the
* global region. This example,
* 1. Initializes and opens the CSL EDMA module
* 2. Sets up Edma module to default values
* 3. Opens EDMA channel 0 in the region 1
* 4. Sets up the channel queue 3
* 5. Gets the param handle for PARAM 0, 1, 2
* 6. Sets up the EDMA PARAM for ping and pong buffers
* 7. Enables Interrupt (Bit 0-2) for the global region interrupts
* 8. Manually triggers the channel 0
* 9. Polls 0n IPR bit 0 and 2
* 10. Clears the pending bit
* 11. Does the data comparision to ensure the transffered data is proper
* or not
* 12. Displays the result based on step 11
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Edma_ping_pong_xfer_gbl_reg.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* 16-Dec-2005 ds Updated documentation
* ============================================================================
*/
#include <stdio.h>
#include <csl_edma3.h>
#include <soc.h>
/* Globals */
Uint8 srcBuff1[256];
Uint8 srcBuff2[256];
Uint8 dstBuff1[256];
Uint8 dstBuff2[256];
Uint32 passStatus = 1;
/* Forward declaration */
void edma_ping_pong_xfer_gbl_region (void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main(void)
{
/* Invoke example */
edma_ping_pong_xfer_gbl_region ();
return;
}
/*
* =============================================================================
* @func edma_ping_pong_xfer_gbl_region
*
* @arg
* NONE
*
* @desc
* This is the example routine which perform edma ping pong buffer transfer
* where channel is open in the global region.
* It implements following steps
* 1. Intializes and Opens the Edma and Intc module.
* 2. Sets up the interrupt for the edma global region.
* 3. Sets up the edma module using the API csl_edma3Hwsetup ()
* 4. Enables the edma global region
* 5. Opens the channel nd get the param handle for PARAM 0, 1, 2
* 6. Sets up the edma param entry for ping and pong buffers
* 7. Enables the edma interrupt using CSL_EDMA3_CMD_INTR_ENABLE.
* 7. Enables Interrupt (Bit 0-2) for the global region interrupts
* 8. Manually triggers the channel 0
* 9. Polls 0n IPR bit 0
* 10. Clear the pending bit
* 11. Manually triggers the channel 0
* 12. Polls 0n IPR bit 2
* 13. Clears the pending bit
* 14. Compares the data in the destination buffer is proper or not.
* 15. Closes the edma module and channel.
*
* @return
* NONE
*
* =============================================================================
*/
void edma_ping_pong_xfer_gbl_region (void)
{
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPing;
CSL_Edma3ParamHandle hParamPong;
CSL_Edma3ParamHandle hParamBasic;
CSL_Edma3ChannelObj chObj;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Status status;
CSL_Edma3HwDmaChannelSetup dmahwSetup;
Uint32 loopIndex;
/* Initialize data */
for (loopIndex = 0; loopIndex < 256; loopIndex++) {
srcBuff1[loopIndex] = loopIndex;
srcBuff2[loopIndex] = loopIndex;
dstBuff1[loopIndex] = 0;
dstBuff2[loopIndex] = 0;
}
/* Module initialization */
status = CSL_edma3Init(&context);
if (status != CSL_SOK) {
printf ("Edma module initialization failed\n");
return;
}
/* Module level open */
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
if ( (hModule == NULL) || (status != CSL_SOK)) {
printf ("Edma module open failed\n");
return;
}
/* Module setup */
dmahwSetup.paramNum = 0;
dmahwSetup.que = CSL_EDMA3_QUE_0;
hwSetup.dmaChaSetup = &dmahwSetup;
hwSetup.qdmaChaSetup = NULL;
status = CSL_edma3HwSetup(hModule,&hwSetup);
if (status != CSL_SOK) {
printf ("Hardware setup failed\n");
CSL_edma3Close (hModule);
return;
}
/* Channel open */
chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status);
if ((hChannel == NULL) || (status != CSL_SOK)) {
printf ("Edma channel open failed\n");
return;
}
/* Change Channel Default queue setup from 0 to 3 */
status = CSL_edma3HwChannelSetupQue(hChannel,CSL_EDMA3_QUE_3);
if (status != CSL_SOK) {
printf ("Edma channel setup que failed\n");
return;
}
/* Obtain a handle to parameter set 0 */
hParamBasic = CSL_edma3GetParamHandle(hChannel,0,&status);
if (hParamBasic == NULL) {
printf ("Edma get param handle for param entry 0 failed\n");
return;
}
/* Obtain a handle to parameter set 2 */
hParamPing = CSL_edma3GetParamHandle(hChannel,2,&status);
if (hParamPing == NULL) {
printf ("Edma get param handle for param entry 2 failed\n");
return;
}
/* Obtain a handle to parameter set 1 */
hParamPong = CSL_edma3GetParamHandle(hChannel,1,&status);
if (hParamPong == NULL) {
printf ("Edma get param handle for param entry 1 failed\n");
return;
}
/* Setup the parameter entry parameters (Ping buffer) */
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN, \
0,CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR );
myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParamPong,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1);
myParamSetup.cCnt = 1;
status = CSL_edma3ParamSetup(hParamBasic,&myParamSetup);
if (status != CSL_SOK) {
printf("Edma parameter entry setup is failed\n");
return;
}
/* Ping setup */
status = CSL_edma3ParamSetup(hParamPing,&myParamSetup);
if (status != CSL_SOK) {
printf("Edma ping parameter entry setup is failed\n");
return;
}
/* Pong setup */
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParamPing,0);
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
1,CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_EN, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR );
myParamSetup.srcAddr = (Uint32)srcBuff2;
myParamSetup.dstAddr = (Uint32)dstBuff2;
status = CSL_edma3ParamSetup(hParamPong,&myParamSetup);
if (status != CSL_SOK) {
printf("Edma ping parameter entry setup is failed\n");
return;
}
/* Interrupt enable (Bits 0-1) for the global region interrupts */
regionIntr.region = CSL_EDMA3_REGION_GLOBAL ;
regionIntr.intr = 0x3 ;
regionIntr.intrh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,®ionIntr);
/* Trigger channel */
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
regionIntr.region = CSL_EDMA3_REGION_GLOBAL ;
regionIntr.intr = 0 ;
regionIntr.intrh = 0 ;
/* Poll on IPR bit 0 */
do {
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
} while (!(regionIntr.intr & 0x1));
/* Clear the pending bit */
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,®ionIntr);
/* Trigger Channel */
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
/* Poll on IPR bit 2 */
do {
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
} while (!(regionIntr.intr & 0x2));
/* Check transfer by comparing the source and destination buffers */
if(Verify_Transfer( 256, 1, 1, 0, 0, 0, 0, srcBuff1, dstBuff1, \
TRUE) == FALSE)
passStatus = 0;
if(Verify_Transfer( 256, 1, 1, 0, 0, 0, 0, srcBuff2, dstBuff2, \
TRUE) == FALSE)
passStatus = 0;
if (passStatus == 1)
printf ("<<EXAMPLE PASSED>>: Edma Ping Pong Buffer Transfer Passed\n");
else {
printf ("<<EXAMPLE FAILED>>: Edma Ping Pong Buffer Transfer Failed\n");
return;
}
/* Close channel */
status = CSL_edma3ChannelClose(hChannel);
if (status != CSL_SOK) {
printf("Edma channel close failed\n");
return;
}
/* Close edma module */
status = CSL_edma3Close(hModule);
if (status != CSL_SOK) {
printf("Edma module close failed\n");
return;
}
printf ("=============================================================\n");
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_utopia2.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_utopia2.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for UTOPIA
*/
#ifndef _CSLR_UTOPIA2_H_
#define _CSLR_UTOPIA2_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 UCR;
volatile Uint32 RSVD0[4];
volatile Uint32 CDR;
volatile Uint32 EIER;
volatile Uint32 EIPR;
} CSL_Utopia2Regs;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* UCR */
#define CSL_UTOPIA2_UCR_BEND_MASK (0x80000000u)
#define CSL_UTOPIA2_UCR_BEND_SHIFT (0x0000001Fu)
#define CSL_UTOPIA2_UCR_BEND_RESETVAL (0x00000000u)
/*----BEND Tokens----*/
#define CSL_UTOPIA2_UCR_BEND_LITTLE (0x00000000u)
#define CSL_UTOPIA2_UCR_BEND_BIG (0x00000001u)
#define CSL_UTOPIA2_UCR_SLID_MASK (0x1F000000u)
#define CSL_UTOPIA2_UCR_SLID_SHIFT (0x00000018u)
#define CSL_UTOPIA2_UCR_SLID_RESETVAL (0x00000000u)
#define CSL_UTOPIA2_UCR_XUDC_MASK (0x003C0000u)
#define CSL_UTOPIA2_UCR_XUDC_SHIFT (0x00000012u)
#define CSL_UTOPIA2_UCR_XUDC_RESETVAL (0x00000000u)
/*----XUDC Tokens----*/
#define CSL_UTOPIA2_UCR_XUDC_STANDARD (0x00000000u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER1 (0x00000001u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER2 (0x00000002u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER3 (0x00000003u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER4 (0x00000004u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER5 (0x00000005u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER6 (0x00000006u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER7 (0x00000007u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER8 (0x00000008u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER9 (0x00000009u)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER10 (0x0000000Au)
#define CSL_UTOPIA2_UCR_XUDC_EXTRAHEADER11 (0x0000000Bu)
#define CSL_UTOPIA2_UCR_UXEN_MASK (0x00010000u)
#define CSL_UTOPIA2_UCR_UXEN_SHIFT (0x00000010u)
#define CSL_UTOPIA2_UCR_UXEN_RESETVAL (0x00000000u)
/*----UXEN Tokens----*/
#define CSL_UTOPIA2_UCR_UXEN_TX_PORT_DISABLE (0x00000000u)
#define CSL_UTOPIA2_UCR_UXEN_TX_PORT_ENABLE (0x00000001u)
#define CSL_UTOPIA2_UCR_MPHY_MASK (0x00004000u)
#define CSL_UTOPIA2_UCR_MPHY_SHIFT (0x0000000Eu)
#define CSL_UTOPIA2_UCR_MPHY_RESETVAL (0x00000000u)
/*----MPHY Tokens----*/
#define CSL_UTOPIA2_UCR_MPHY_SINGLE_PHYMODE (0x00000000u)
#define CSL_UTOPIA2_UCR_MPHY_MULTI_PHYMODE (0x00000001u)
#define CSL_UTOPIA2_UCR_RUDC_MASK (0x0000003Cu)
#define CSL_UTOPIA2_UCR_RUDC_SHIFT (0x00000002u)
#define CSL_UTOPIA2_UCR_RUDC_RESETVAL (0x00000000u)
/*----RUDC Tokens----*/
#define CSL_UTOPIA2_UCR_RUDC_STANDARD (0x00000000u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER1 (0x00000001u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER2 (0x00000002u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER3 (0x00000003u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER4 (0x00000004u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER5 (0x00000005u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER6 (0x00000006u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER7 (0x00000007u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER8 (0x00000008u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER9 (0x00000009u)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER10 (0x0000000Au)
#define CSL_UTOPIA2_UCR_RUDC_EXTRAHEADER11 (0x0000000Bu)
#define CSL_UTOPIA2_UCR_UREN_MASK (0x00000001u)
#define CSL_UTOPIA2_UCR_UREN_SHIFT (0x00000000u)
#define CSL_UTOPIA2_UCR_UREN_RESETVAL (0x00000000u)
/*----UREN Tokens----*/
#define CSL_UTOPIA2_UCR_UREN_RX_PORT_DISABLE (0x00000000u)
#define CSL_UTOPIA2_UCR_UREN_RX_PORT_ENABLE (0x00000001u)
#define CSL_UTOPIA2_UCR_RESETVAL (0x00000000u)
/* CDR */
#define CSL_UTOPIA2_CDR_XCCNT_MASK (0x00FF0000u)
#define CSL_UTOPIA2_CDR_XCCNT_SHIFT (0x00000010u)
#define CSL_UTOPIA2_CDR_XCCNT_RESETVAL (0x000000FFu)
/*----XCCNT Tokens----*/
#define CSL_UTOPIA2_CDR_XCCNT_DISABLE (0x00000000u)
#define CSL_UTOPIA2_CDR_RCCNT_MASK (0x000000FFu)
#define CSL_UTOPIA2_CDR_RCCNT_SHIFT (0x00000000u)
#define CSL_UTOPIA2_CDR_RCCNT_RESETVAL (0x000000FFu)
/*----RCCNT Tokens----*/
#define CSL_UTOPIA2_CDR_RCCNT_DISABLE (0x00000000u)
#define CSL_UTOPIA2_CDR_RESETVAL (0x00FF00FFu)
/* EIER */
#define CSL_UTOPIA2_EIER_XCPE_MASK (0x00040000u)
#define CSL_UTOPIA2_EIER_XCPE_SHIFT (0x00000012u)
#define CSL_UTOPIA2_EIER_XCPE_RESETVAL (0x00000000u)
/*----XCPE Tokens----*/
#define CSL_UTOPIA2_EIER_XCPE_DISABLE (0x00000000u)
#define CSL_UTOPIA2_EIER_XCPE_ENABLE (0x00000001u)
#define CSL_UTOPIA2_EIER_XCFE_MASK (0x00020000u)
#define CSL_UTOPIA2_EIER_XCFE_SHIFT (0x00000011u)
#define CSL_UTOPIA2_EIER_XCFE_RESETVAL (0x00000000u)
/*----XCFE Tokens----*/
#define CSL_UTOPIA2_EIER_XCFE_DISABLE (0x00000000u)
#define CSL_UTOPIA2_EIER_XCFE_ENABLE (0x00000001u)
#define CSL_UTOPIA2_EIER_XQSE_MASK (0x00010000u)
#define CSL_UTOPIA2_EIER_XQSE_SHIFT (0x00000010u)
#define CSL_UTOPIA2_EIER_XQSE_RESETVAL (0x00000000u)
/*----XQSE Tokens----*/
#define CSL_UTOPIA2_EIER_XQSE_DISABLE (0x00000000u)
#define CSL_UTOPIA2_EIER_XQSE_ENABLE (0x00000001u)
#define CSL_UTOPIA2_EIER_RCPE_MASK (0x00000004u)
#define CSL_UTOPIA2_EIER_RCPE_SHIFT (0x00000002u)
#define CSL_UTOPIA2_EIER_RCPE_RESETVAL (0x00000000u)
/*----RCPE Tokens----*/
#define CSL_UTOPIA2_EIER_RCPE_DISABLE (0x00000000u)
#define CSL_UTOPIA2_EIER_RCPE_ENABLE (0x00000001u)
#define CSL_UTOPIA2_EIER_RCFE_MASK (0x00000002u)
#define CSL_UTOPIA2_EIER_RCFE_SHIFT (0x00000001u)
#define CSL_UTOPIA2_EIER_RCFE_RESETVAL (0x00000000u)
/*----RCFE Tokens----*/
#define CSL_UTOPIA2_EIER_RCFE_DISABLE (0x00000000u)
#define CSL_UTOPIA2_EIER_RCFE_ENABLE (0x00000001u)
#define CSL_UTOPIA2_EIER_RQSE_MASK (0x00000001u)
#define CSL_UTOPIA2_EIER_RQSE_SHIFT (0x00000000u)
#define CSL_UTOPIA2_EIER_RQSE_RESETVAL (0x00000000u)
/*----RQSE Tokens----*/
#define CSL_UTOPIA2_EIER_RQSE_DISABLE (0x00000000u)
#define CSL_UTOPIA2_EIER_RQSE_ENABLE (0x00000001u)
#define CSL_UTOPIA2_EIER_RESETVAL (0x00000000u)
/* EIPR */
#define CSL_UTOPIA2_EIPR_XCPP_MASK (0x00040000u)
#define CSL_UTOPIA2_EIPR_XCPP_SHIFT (0x00000012u)
#define CSL_UTOPIA2_EIPR_XCPP_RESETVAL (0x00000000u)
#define CSL_UTOPIA2_EIPR_XCFP_MASK (0x00020000u)
#define CSL_UTOPIA2_EIPR_XCFP_SHIFT (0x00000011u)
#define CSL_UTOPIA2_EIPR_XCFP_RESETVAL (0x00000000u)
#define CSL_UTOPIA2_EIPR_XQSP_MASK (0x00010000u)
#define CSL_UTOPIA2_EIPR_XQSP_SHIFT (0x00000010u)
#define CSL_UTOPIA2_EIPR_XQSP_RESETVAL (0x00000000u)
#define CSL_UTOPIA2_EIPR_RCPP_MASK (0x00000004u)
#define CSL_UTOPIA2_EIPR_RCPP_SHIFT (0x00000002u)
#define CSL_UTOPIA2_EIPR_RCPP_RESETVAL (0x00000000u)
#define CSL_UTOPIA2_EIPR_RCFP_MASK (0x00000002u)
#define CSL_UTOPIA2_EIPR_RCFP_SHIFT (0x00000001u)
#define CSL_UTOPIA2_EIPR_RCFP_RESETVAL (0x00000000u)
#define CSL_UTOPIA2_EIPR_RQSP_MASK (0x00000001u)
#define CSL_UTOPIA2_EIPR_RQSP_SHIFT (0x00000000u)
#define CSL_UTOPIA2_EIPR_RQSP_RESETVAL (0x00000000u)
#define CSL_UTOPIA2_EIPR_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/memprot/src/Memprot_example.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file memprot_example.c
*
* @path $(CSLPATH)\example\memprot\src
*
* @desc This is an example illustrating usage of the Memory protection
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This example,
* 1. Intializes and opens memory protection module
* 2. Sets up for the L2 Memory protection
* 3. Get the Lock Status
* 4. Get the Fault Status, which will clear the previous fault
* 5. Locks the Unit if not Locked
* 6. Writes wrong key to UnLock which will generate Fault
* 7. The address of MPLKCMD register will be stores the
* fault address in MPFAR register
* 8. Get the Fault Status, which will clear the previous fault
* 9. Compares the fault address
* 10. Displays the messages based on step 9
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Memprot_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* =============================================================================
* Revision History
* ===============
* 23-sept-2005 PSK File Created.
* 16-Dec-2005 ds Updated documentation
* =============================================================================
*/
#include <stdio.h>
#include <csl_memprot.h>
/* defining the attributes for pages */
#define PAGE_ATTR 0xFFFF
/* Function forwards */
void memprot_example (void);
/* Global variable declarations */
Uint32 demoFail = 0;
Uint16 pageAttrTable[32] = {
PAGE_ATTR, PAGE_ATTR, PAGE_ATTR, PAGE_ATTR,
PAGE_ATTR, PAGE_ATTR, PAGE_ATTR, PAGE_ATTR,
PAGE_ATTR, PAGE_ATTR, PAGE_ATTR, PAGE_ATTR,
PAGE_ATTR, PAGE_ATTR, PAGE_ATTR, PAGE_ATTR,
PAGE_ATTR, PAGE_ATTR, PAGE_ATTR, PAGE_ATTR,
PAGE_ATTR, PAGE_ATTR, PAGE_ATTR, PAGE_ATTR,
PAGE_ATTR, PAGE_ATTR, PAGE_ATTR, PAGE_ATTR,
PAGE_ATTR, PAGE_ATTR, 0xFFF0, 0xFFF0
};
/* key values */
Uint32 key1[2] = {0xFFFF, 0xFFFF};
Uint32 key2[2] = {0xABCD, 0xDEFA};
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* @expected result
* If the example passes, it displays the message "PASSED"
* If the example fails, it displays the messae "FAILED"
*
* =============================================================================
*/
void main(void)
{
printf("L2 MEMPROT EXAMPLE DEMO\n");
/* Invoke example */
memprot_example();
if (demoFail > 0) {
printf("Example FAILED\n");
}
else {
printf("Example PASSED\n");
}
return;
}
/*
* =============================================================================
* @func memprot_example
*
* @desc
* This function invokes example that prove functionalites of fault
* occurence when something to be written to the reserved memory.
* The CSL API is used to retrieve the fault address parameters. this
* example gives the idea for the MEMPROT CSL usage
* It implements following steps
* 1. It opens the MEMPROT module CSL
* 2. The CSL_memprotHwSetup is called for module configuration
* 3. Locks the Unit if not Locked
* 4. Writes wrong key to UnLock which will generate Fault
* 5. Get the Fault Status, which will clear the previous fault
* 6. Compares the fault address
* 7. Closes CSL MEMPROT module.
*
* @arg
* None
*
* @eg
* memport_csl_example();
* =============================================================================
*/
void memprot_example (void)
{
CSL_MemprotObj mpL2Obj;
CSL_MemprotHandle hmpL2;
CSL_Status status;
CSL_MemprotHwSetup L2MpSetup;
CSL_MemprotLockStatus lockStat;
CSL_MemprotFaultStatus queryFaultStatus;
/* Initializing the module */
status = CSL_memprotInit(NULL);
if (status != CSL_SOK) {
printf ("MEMPROT: Initialization... Failed.\n");
printf ("\tReason: CSL_memprotInit failed. [status = 0x%x].\n", status);
demoFail++;
return;
}
/* Opening the Handle for the L2 */
hmpL2 = CSL_memprotOpen(&mpL2Obj, CSL_MEMPROT_L2, NULL, &status);
if (status != CSL_SOK || hmpL2 == NULL) {
printf ("MEMPROT: Opening instance... Failed.\n");
printf ("\tReason: Error opening the instance. \
[status = 0x%x, hmpL2 = 0x%x]\n", status, hmpL2);
demoFail++;
return;
}
/* setup parameters */
L2MpSetup. memPageAttr = pageAttrTable;
L2MpSetup.numPages = 32;
L2MpSetup.key = NULL;
/* Do Setup for the L2 Memory protection */
status = CSL_memprotHwSetup (hmpL2,&L2MpSetup);
if (status != CSL_SOK){
printf ("MEMPROT: Hardware setup validation... Failed.\n");
printf ("\tReason: CSL_memprotHwSetup failed. \
[status = 0x%x].\n", status);
demoFail++;
return;
}
/* Query Lock Status */
status = CSL_memprotGetHwStatus(hmpL2,CSL_MEMPROT_QUERY_LOCKSTAT,&lockStat);
if (status != CSL_SOK) {
printf ("MEMPROT: CSL_MEMPROT_QUERY_LOCKSTAT query command Failed.\n");
demoFail++;
return;
}
/* Query Fault Status. By doing this previous fault will be cleared(i.e once
* the fault is read, the fault registers are cleared automatically)
*/
status = CSL_memprotGetHwStatus(hmpL2, CSL_MEMPROT_QUERY_FAULT,
&queryFaultStatus);
if (status != CSL_SOK) {
printf ("MEMPROT: CSL_MEMPROT_QUERY_FAULT query command... Failed.\n");
demoFail++;
return;
}
/* lock the Unit if not Locked */
if ((lockStat & 0x1) == CSL_MEMPROT_LOCKSTAT_UNLOCK) {
status = CSL_memprotHwControl(hmpL2, CSL_MEMPROT_CMD_LOCK, key1);
if (status != CSL_SOK) {
printf ("MEMPROT: Control command CSL_MEMPROT_CMD_LOCK Failed.\n");
demoFail++;
return;
}
}
/* Try UnLocking with the wrong key. Fault occurs and the address of MPLKCMD
* register will be stored as the fault address in MPFAR register */
status = CSL_memprotHwControl(hmpL2, CSL_MEMPROT_CMD_UNLOCK, key2);
if (status != CSL_SOK) {
printf ("MEMPROT: Control command CSL_MEMPROT_CMD_UNLOCK Failed.\n");
demoFail++;
return;
}
/* Query Fault Status */
status = CSL_memprotGetHwStatus(hmpL2, CSL_MEMPROT_QUERY_FAULT,
&queryFaultStatus);
if (status != CSL_SOK) {
printf ("MEMPROT: CSL_MEMPROT_QUERY_FAULT query command... Failed.\n");
demoFail++;
return;
}
/* check for the fault address */
if (queryFaultStatus.addr == (Uint32)&(hmpL2->regs->MPLKCMD)) {
printf("L2 MEMPROT Functionality Example passed\n");
}
else {
printf("L2 MEMPROT Functionality Example Failed\n");
demoFail++;
return;
}
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/mcbsp/_csl_mcbspChannelControl.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/mcbsp/_csl_mcbspChannelControl.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file _csl_mcbspChannelControl.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API _CSL_mcbspChannelControl()
*
*/
/* ============================================================================
* Revision History
* ================
* July 04, 2005 ds - Register Naming convention used for
* Multichannel registers are changed according
* the changes in cslr_mcbsp.h
* ============================================================================
*/
#include <csl_mcbsp.h>
#include <_csl_mcbsp.h>
/* ============================================================================
* @n@b _CSL_mcbspChannelControl
*
* @b Description
* @n Enable channel in Multi Channel Selection Mode
*
* @b Arguments
* @verbatim
hMcbsp Handle to MCBSP Obj used
channelNo Channel Number
block Block to which the channel belongs
operation The operation to be performed
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Successful completion
* @li CSL_ESYS_FAIL - Operation could not the done
* @li CSL_ESYS_BADHANDLE - Invalid Handle
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before _CSL_mcbspChannelControl() can be called.
*
* <b> Post Condition </b>
* @n Enables the specified channel
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_McbspHandle hMcbsp;
...
hMcbsp = CSL_mcbspOpen(hMcbsp, CSL_MCBSP_1,NULL, &status );
CSL_mcbspChannelControl( hMcbsp, 11, 1, CSL_MCBSP_CHAN_RX_ENABLE);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (_CSL_mcbspChannelControl, ".text:csl_section:mcbsp");
CSL_Status _CSL_mcbspChannelControl (
CSL_McbspHandle hMcbsp,
Uint16 channelNo,
CSL_McbspBlock block,
CSL_McbspChCtrl operation
)
{
CSL_McbspRstStat txEnableChk, rxEnableChk;
CSL_McbspBlock blkCheck;
CSL_Status status;
if (hMcbsp == NULL) {
status = CSL_ESYS_BADHANDLE;
return status;
}
status = CSL_mcbspGetHwStatus(hMcbsp, CSL_MCBSP_QUERY_CUR_RX_BLK, \
&blkCheck);
if(status != CSL_SOK) {
return(CSL_ESYS_FAIL);
}
status = CSL_mcbspGetHwStatus(hMcbsp, CSL_MCBSP_QUERY_RX_RST_STAT, \
&rxEnableChk);
if(((status == CSL_SOK) && (rxEnableChk == 1)) && (blkCheck == block)) {
return(CSL_ESYS_FAIL);
}
status = CSL_mcbspGetHwStatus(hMcbsp, CSL_MCBSP_QUERY_CUR_TX_BLK, \
&blkCheck);
if(status != CSL_SOK) {
return(CSL_ESYS_FAIL);
}
status = CSL_mcbspGetHwStatus(hMcbsp, CSL_MCBSP_QUERY_TX_RST_STAT, \
&txEnableChk);
if(((status == CSL_SOK) && (rxEnableChk == 1)) && (blkCheck == block)) {
return(CSL_ESYS_FAIL);
}
switch(block) {
/* To Enable or disable One channel in block 0 in Receiver
* and Transmitter
*/
case CSL_MCBSP_BLOCK_0:
if(operation == CSL_MCBSP_CHCTRL_RX_ENABLE)
CSL_FINSR( hMcbsp->regs->RCERE0, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_RX_DISABLE)
CSL_FINSR( hMcbsp->regs->RCERE0, channelNo, channelNo, 0);
if(operation == CSL_MCBSP_CHCTRL_TX_ENABLE)
CSL_FINSR( hMcbsp->regs->XCERE0, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_TX_DISABLE)
CSL_FINSR( hMcbsp->regs->XCERE0, channelNo, channelNo, 0);
break;
/* To Enable or disable One channel in block 1 in Receiver
* and Transmitter
*/
case CSL_MCBSP_BLOCK_1:
channelNo += 16;
if(operation == CSL_MCBSP_CHCTRL_RX_ENABLE)
CSL_FINSR( hMcbsp->regs->RCERE0, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_RX_DISABLE)
CSL_FINSR( hMcbsp->regs->RCERE0, channelNo, channelNo, 0);
if(operation == CSL_MCBSP_CHCTRL_TX_ENABLE)
CSL_FINSR( hMcbsp->regs->XCERE0, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_TX_DISABLE)
CSL_FINSR( hMcbsp->regs->XCERE0, channelNo, channelNo, 0);
break;
/* To Enable One channel in Partition-C in Receiver and Transmitter */
case CSL_MCBSP_BLOCK_2:
if(operation == CSL_MCBSP_CHCTRL_RX_ENABLE)
CSL_FINSR( hMcbsp->regs->RCERE1, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_RX_DISABLE)
CSL_FINSR( hMcbsp->regs->RCERE1, channelNo, channelNo, 0);
if(operation == CSL_MCBSP_CHCTRL_TX_ENABLE)
CSL_FINSR( hMcbsp->regs->XCERE1, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_TX_DISABLE)
CSL_FINSR( hMcbsp->regs->XCERE1, channelNo, channelNo, 0);
break;
/* To Enable One channel in Partition-D in Receiver and Transmitter */
case CSL_MCBSP_BLOCK_3:
channelNo += 16;
if(operation == CSL_MCBSP_CHCTRL_RX_ENABLE)
CSL_FINSR( hMcbsp->regs->RCERE1, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_RX_DISABLE)
CSL_FINSR( hMcbsp->regs->RCERE1, channelNo, channelNo, 0);
if(operation == CSL_MCBSP_CHCTRL_TX_ENABLE)
CSL_FINSR( hMcbsp->regs->XCERE1, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_TX_DISABLE)
CSL_FINSR( hMcbsp->regs->XCERE1, channelNo, channelNo, 0);
break;
/* To Enable One channel in Partition-E in Receiver and Transmitter */
case CSL_MCBSP_BLOCK_4:
if(operation == CSL_MCBSP_CHCTRL_RX_ENABLE)
CSL_FINSR( hMcbsp->regs->RCERE2, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_RX_DISABLE)
CSL_FINSR( hMcbsp->regs->RCERE2, channelNo, channelNo, 0);
if(operation == CSL_MCBSP_CHCTRL_TX_ENABLE)
CSL_FINSR( hMcbsp->regs->XCERE2, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_TX_DISABLE)
CSL_FINSR( hMcbsp->regs->XCERE2, channelNo, channelNo, 0);
break;
/* To Enable One channel in Partition-F in Receiver and Transmitter */
case CSL_MCBSP_BLOCK_5:
channelNo += 16;
if(operation == CSL_MCBSP_CHCTRL_RX_ENABLE)
CSL_FINSR( hMcbsp->regs->RCERE2, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_RX_DISABLE)
CSL_FINSR( hMcbsp->regs->RCERE2, channelNo, channelNo, 0);
if(operation == CSL_MCBSP_CHCTRL_TX_ENABLE)
CSL_FINSR( hMcbsp->regs->XCERE2, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_TX_DISABLE)
CSL_FINSR( hMcbsp->regs->XCERE2, channelNo, channelNo, 0);
break;
/* To Enable One channel in Partition-G in Receiver and Transmitter */
case CSL_MCBSP_BLOCK_6:
if(operation == CSL_MCBSP_CHCTRL_RX_ENABLE)
CSL_FINSR( hMcbsp->regs->RCERE3, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_RX_DISABLE)
CSL_FINSR( hMcbsp->regs->RCERE3, channelNo, channelNo, 0);
if(operation == CSL_MCBSP_CHCTRL_TX_ENABLE)
CSL_FINSR( hMcbsp->regs->XCERE3, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_TX_DISABLE)
CSL_FINSR( hMcbsp->regs->XCERE3, channelNo, channelNo, 0);
break;
/* To Enable One channel in Partition-H in Receiver and Transmitter */
case CSL_MCBSP_BLOCK_7:
channelNo += 16;
if(operation == CSL_MCBSP_CHCTRL_RX_ENABLE)
CSL_FINSR( hMcbsp->regs->RCERE3, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_RX_DISABLE)
CSL_FINSR( hMcbsp->regs->RCERE3, channelNo, channelNo, 0);
if(operation == CSL_MCBSP_CHCTRL_TX_ENABLE)
CSL_FINSR( hMcbsp->regs->XCERE3, channelNo, channelNo, 1);
if(operation == CSL_MCBSP_CHCTRL_TX_DISABLE)
CSL_FINSR( hMcbsp->regs->XCERE3, channelNo, channelNo, 0);
break;
default:
return(CSL_ESYS_FAIL);
}
return(CSL_SOK);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_idma.h
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_idma.h
*
* @path $(CSLPATH)\inc
*
* @desc File for functional layer of IDMA
*
*/
/** @mainpage IDMA Module
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to detail the CSL APIs for the IDMA
* Module. The CSL developer is expected to refer to this document
* while designing APIs for the modules which use IDMA module. Some of the
* listed APIs may not be applicable to a given module. While other cases
* this list of APIs may not be sufficient to cover all the features required
* for a particular Module. The CSL developer should use his discretion
* designing new APIs or extending the existing ones to cover these.
* modules .
*
* @subsection aaa Terms and Abbreviations
* -# CSL : Chip Support Library
* -# API : Application Programmer Interface
* -# IDMA : Internal DMA Module
*
* @subsection Assumptions
* The abbreviations CSL, IDMA have been used throughout this document to
* refer to the C64Plus IDMA Module.
*/
/* =============================================================================
* Revision History
* ===============
* 23-Jun-2004 <NAME> File Created
*
******************************************************************************/
/*
* REVISION HISTORY:
* 03-25-04...Initial version of Channel 1 routines.......S.Jagadeesh
* 05-20-04...Integration of CSL Register Layer...........C.Courtney
* 06-10-04...Changed Return Types of all functions except Open to
* Status......................................C.Courtney
* 06-14-04...Removed Open/Close APIs and re-implemented Init API
* Also redocumented...........................C.Courtney
*
* DESCRIPTION:
* This file contains various function defeinitions that define a
* IDMA (Internal DMA). Functions for Channel0 contain
* support for transferring from internal memory to memory
* hooked to Config space. Channel 1 functions contain support
* for paging from local memories. These may be from Level 1
* data memory to Level 2 memory or shared L2 memory.
*
* PRIVATE DATA STRUCTURES:
*
* Private data structures are defined in the header file "idma.h"
* and are shown below:
*
* typedef struct idma1_handle
* {
* Uint32 status;
* Uint32 reserved;
* Uint32 *src;
* Uint32 *dst;
* Uint32 cnt;
* }IDMA1_handle;
*
* This handle holds all the descriptors needed to issue a Channel 1
* transfer. In the routines shown below, the cnt register
* fields of this structure is used to hold information regarding
* the priority of IDMA relative to CPU, and whether interrupt is
* desired or not. Once these properties are set in the IDMA1_init()
* function, all transfers performed on Channel 1, use this field
* to submit transfers, unless they are re-configured again by
* seperate calls to setpriority and setInt.
*
* The following configuration structure holds all the fields needed
* to describe a Channel 0 transfer and has trhe following structure.
*
* typedef struct idma0_config
* {
* Uint32 status;
* Uint32 mask;
* Uint32 *src;
* Uint32 *dst;
* Uint32 cnt;
* }IDMA0_Config;
*
* The "src" contains the start address in internal memory or
* configspace, the "dst" contains the destination address in
* configspace or internal memory respectively. Transfers from
* configspace to configspace using Channel 1 will raise an
* exception. The mask is a 32-bit field of 1-hot encoding of
* registers to access within the 32-bit register window. The cnt
* register fields of this structure is used to hold information
* regarding whether interrupt is desired or not. Along with the
* the number of 32-bit fields will be transfered
*
* FUNCTIONS SUPPORTED:
*
* CHANNEL 0:
*
* void IDMA0_config( IDMA_Config *config): This function performs
* a Channel 0 transfer using the paremeters contained in the
* configuration structure pointer "config".
*
* void IDMA0_configArgs
* (
* Uint32 mask,
* Uint32 *src,
* Uint32 *dst,
* Uint8 cnt
* )
*
* This function issues a Channel 0 transfer from source "src"
* to destination "dst" performing "cnt" 32-word transfers in
* which the individual 32-word transfers are controlled by a
* "1-hot" encoding in a 32-bit field "mask". "src" and "dst"
* must be word aligned, cnt must be <=15.
*
*
* Uint32 IDMA0_getStatus(): This function returns the ACTV
* and PEND bits.
*
* Uint32 IDMA0_wait(): This function waits for all previous
* transfers on Channel 0 to complete by waiting for ACTV == 0
* && PEND==0.
*
* int IDMA0_setInt(interrupt): This function is used to set
* the IDMA to interrupt the DSP on completion.
*
* CHANNEL 1:
*
* int IDMA1_init(priority, interrupt): This function sets the
* priority and interrupt for transfers on Channel 1, for all
* further transfers. This returns the value of the formatted
* IDMA1_COUNT.
*
* int IDMA1_copy(src, dst, byteCnt): This function transfers
* "byteCnt" bytes from source "src" to destination "dst".
*
* int IDMA1_fill(fillValue, dst, byteCnt): This function fills
* destination "dst" with "byteCnt" bytes of the fill, contained
* in fill_value (32-bit field". This requires the "byteCnt" to
* be a multiple of four.
*
* Uint32 IDMA1_getStatus(): This function returns the ACTV and
* PEND bits.
*
* int IDMA1_wait(): This function waits to make sure that
* all previous transfers on Channel 1 have completed by
* waiting for ACTV==0 && PEND==0.
*
* int IDMA1_setPriority(priority): This function is used to
* set the priority between CPU and IDMA. A value of 0x111
* implies that CPU is higher priority than IDMA. A value
* of 0x0 implies IDMA is higher priority than CPU. These are
* the only values that are allowed.
*
* int IDMA1_setInt(interrupt): This function is used to set
* the IDMA to interrupt the DSP on completion.
*
*/
#ifndef _CSL_IDMA_H_
#define _CSL_IDMA_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <cslr_idma.h>
#include <soc.h>
/** Specifies which IDMA channel will be used
* Used to indicate which IDMA channel (0 or 1) will be used by API
*/
typedef enum {
/** IDMA channel 0 */
IDMA_CHAN_0 = 0,
/** IDMA channel 1 */
IDMA_CHAN_1 = 1
} IDMA_Chan;
/** Specifies whether the interrupt event generation is enabled or
* disabled.
* Used to indicate whether the interrupt event generation is enabled
* or disabled
*/
typedef enum {
/** Idma Int Disable */
IDMA_INT_DIS = 0,
/** Idma Int Enable */
IDMA_INT_EN = 1
} IDMA_intEn;
/** Specifies what priority level the IDMA channel is set to.
* Used to specify what priority level the IDMA channel is set to.
*/
typedef enum {
/** Set Priority level 0 */
IDMA_PRI_0 = CSL_IDMA_IDMA1_CNT_PRI_PRI0,
/** Set Priority level 1 */
IDMA_PRI_1 = CSL_IDMA_IDMA1_CNT_PRI_PRI1,
/** Set Priority level 2 */
IDMA_PRI_2 = CSL_IDMA_IDMA1_CNT_PRI_PRI2,
/** Set Priority level 3 */
IDMA_PRI_3 = CSL_IDMA_IDMA1_CNT_PRI_PRI3,
/** Set Priority level 4 */
IDMA_PRI_4 = CSL_IDMA_IDMA1_CNT_PRI_PRI4,
/** Set Priority level 5 */
IDMA_PRI_5 = CSL_IDMA_IDMA1_CNT_PRI_PRI5,
/** Set Priority level 6 */
IDMA_PRI_6 = CSL_IDMA_IDMA1_CNT_PRI_PRI6,
/** Set Priority level 7 */
IDMA_PRI_7 = CSL_IDMA_IDMA1_CNT_PRI_PRI7,
/** NoPriority level */
IDMA_PRI_NULL = -1
}IDMA_priSet;
/*
* The pointer to this is passed to all IDMA CSL APIs.
* This structure has the fields required to configure IDMA for any test
* case/application. It should be initialized as per requirements of a
* test case/application and passed on to the setup function.
*/
/** IDMA1_handle IDMA Channel 1 handle - Contains Status, Source and
* Destination locations and count for channel 1 transfer.
*/
typedef struct idma1_handle {
/** IDMA channel 1 status */
Uint32 status;
/** reserved area */
Uint32 reserved;
/** IDMA channel 1 source location */
Uint32 *src;
/** IDMA channel 1 destination */
Uint32 *dst;
/** Number of bytes to be transfered */
Uint32 cnt;
}IDMA1_handle;
/** IDMA0_Config IDMA Channel 0 configuration - Contains Status, Mask,
* Source and Destination locations and count for channel 0 (configuration)
* transfer.
*/
typedef struct idma0_config {
/** IDMA channel 0 status */
Uint32 status;
/** IDMA channel 0 mask value */
Uint32 mask;
/** IDMA channel 0 source location */
Uint32 *src;
/** IDMA channel 0 destination */
Uint32 *dst;
/** Number of bytes to be transfered */
Uint32 cnt;
}IDMA0_Config;
/** status */
typedef Uint32 Status;
/** Pointer to the register overlay structure of the IDMA */
typedef CSL_IdmaRegs *CSL_idmaOvly;
/* ===========================================================================
* @n@b IDMA1_init
*
* @b Description
* @n This function obtains a priority and an interrupt flag and remembers
* them so that all future transfers on Channel 1 will use these
* priorities. The priority is contained in the argument "priority" and
* interrupt flag in "interr".
* This function performs IDMA Channel 1 initialization by setting the
* priority level and the enabling/disabling the interrupt event
* generation for the channel.
*
* @b Arguments
* @verbatim
priority Priority 0-7 of handle
interr interrupt event generated on/off
@endverbatim
*
* <b> Return Value </b> idma1_handle_priv.cnt
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 cnt1;
// Initialize IDMA Channel 1
// Set Chan 1 to have Priority 7 and Interrupt Event Gen On
...
cnt1 = IDMA1_init( IDMA_PRI_7, IDMA_INT_EN);
@endverbatim
* ============================================================================
*/
Int IDMA1_init (
IDMA_priSet priority,
IDMA_intEn interr
);
/* ===========================================================================
* @n@b IDMA1_copy
*
* @b Description
* @n IDMA1_copy() transfers "byteCnt" bytes from a source "src"
* to a destination "dst". It is assumed that both the source and
* destination addresses are in internal memory. Transfers from
* addresses that are not in the internal memory will raise an
* exception. No checking is performed by this function to check
* the correctness of any of the passed in arguments.
*
* Used to transfer "byteCnt" bytes from source "src" to destination "dst"
*
* @b Arguments
* @verbatim
src Pointer to the source address
dst Pointer to the destination address
byteCnt Number of bytes to be transferred.
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of IDMA.
*
* @b Example
* @verbatim
Uint32 src;
Uint32 dst;
...
// Copy src to dst1 - 80 bytes - 20 words
IDMA1_copy(src, dst1, 80);
@endverbatim
* ============================================================================
*/
Int IDMA1_copy (
Uint32 *src,
Uint32 *dst,
Uint32 byteCnt
);
/* ===========================================================================
* @n@b IDMA1_fill
*
* @b Description
* @n IDMA1_fill() Takes a fill value in "fill_value" and fills
* "byteCnt" bytes of the "fill_value" to destination "dst".
*
* Used to write "byteCnt" bytes of the fill value "fill_value" to
* destination "dst"
*
* @b Arguments
* @verbatim
dst Pointer to the destination address
byteCnt Number of bytes to be transferred.
fill_value Data to be filled
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of IDMA.
*
* @b Example
* @verbatim
Uint32 dst1[100];
...
IDMA1_fill(dst1, 0x800, 0xAAAABABA);
@endverbatim
* ============================================================================
*/
Int IDMA1_fill (
Uint32 *dst,
Uint32 byteCnt,
Uint32 fill_value
);
/* ===========================================================================
* @n@b IDMA1_getStatus
*
* @b Description
* @n IDMA1_getStatus() gets the active and pending status of IMDA
* Channel 1 and returns ACTV in the least significant bit and PEND
* in the 2nd least significant bit
*
* Gets the active and pending status of IDMA channel 1
*
* @b Arguments
* @n None
*
* <b> Return Value </b> IDMA channel 1 status.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 stat;
...
stat = IDMA1_getStatus();
@endverbatim
* ============================================================================
*/
Uint32 IDMA1_getStatus(void);
/* ===========================================================================
* @n@b IDMA1_wait
*
* @b Description
* @n IDMA1_wait() waits until all previous transfers for IDMA Channel
* 1 have been completed by making sure that both active and pend
* bits are zero. These are the two least significant bits of the
* status register for the channel.
*
* Waits until previous transfers have completed for IDMA channel 1
* before returning.
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 stat;
...
stat = IDMA1_getStatus();
IDMA1_wait();
@endverbatim
* ============================================================================
*/
void IDMA1_wait(void);
/** ===========================================================================
* @n@b IDMA1_setPriority
*
* @b Description
* @n IDMA1_setPriority() sets a "3-bit" priority field which has
* a valid range of 0-7 for priorities 0-7. It returns the a
* "32-bit" count register field back to the user. This 32-bit
* register field will be used in IDMA1_copy() and IDMA1_fill()
* to program the Priority and Interrupt options for IDMA Chan 1
*
* Sets the priority level for IDMA channel 1 transfers
*
* @b Arguments
* @verbatim
priority Priority 0-7 of handle
@endverbatim
*
* <b> Return Value </b> idma1_handle_priv.cnt
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 tempCnt;
...
// Set and test Priority level for IDMA1
tempCnt = IDMA1_setPriority(IDMA_PRI_2);
@endverbatim
* ============================================================================
*/
Int IDMA1_setPriority (
IDMA_priSet priority
);
/* ===========================================================================
* @n@b IDMA1_setInt
*
* @b Description
* @n IDMA1_setInt() sets a the interrupt enable field which
* is used to enable/disable interrupts for IDMA Channel 1.
* It returns the a "32-bit" count register field back to the
* user. This 32-bit register field will be used in IDMA1_copy()
* and IDMA1_fill() to program the Priority and Interrupt options
* for IDMA Channel 1
*
* Enables/Disables interrupt event generation for IDMA channel 1
* transfers
*
* @b Arguments
* @verbatim
interr interrupt event generated on/off
@endverbatim
*
* <b> Return Value </b> idma1_handle_priv.cnt
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 tempCnt;
...
// Set and test Interrupt event gen for IDMA1
tempCnt = IDMA1_setInt(IDMA_INT_DIS);
@endverbatim
* ============================================================================
*/
Int IDMA1_setInt (
IDMA_intEn interr
);
/* ===========================================================================
* @n@b IDMA0_init
*
* @b Description
* @n This function obtains a interrupt enable setting and
* remembers them so that all future transfers on Channel 0
* generate interrupts or not.
* Initializes the Interrupt Event Generation for IDMA Channel 0
*
* @b Arguments
* @verbatim
interr interrupt event generated on/off
@endverbatim
*
* <b> Return Value </b> idma0_configHandle_priv.cnt
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 cnt0;
...
// Initialize IDMA Channel 0
// Set Chan 0 to have Interrupt Event Gen On
cnt0 = IDMA0_init(IDMA_INT_EN);
@endverbatim
* ============================================================================
*/
Int IDMA0_init (
IDMA_intEn interr
);
/* ===========================================================================
* @n@b IDMA0_config
*
* @b Description
* @n IDMA0_config() - Configures IMDA Channel 0 to perform a transfer
* between Internal Memory and Configuration Space based on the
* data in the *config structure. "mask" provides a 1-hot encoding
* for the 32-word tranfer that determines which of the 32-words
* are to be transfered. In the *config structure "src" provides
* the source location of the transfer and "dst provides the
* destination location of the transfer and both must be word
* aligned. While "cnt" provides the number of 32-word transfers to
* perform and must not be greater than 15.
* Initializes the configuration for IDMA Channel 0 including 1-hot
* encoding mask, source location, destination location and count.
* This is done using the structure IDMA0_Config.
*
* @b Arguments
* @verbatim
config Pointer to the Configuration structure
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of IDMA.
*
* @b Example
* @verbatim
IDMA0_Config config
...
IDMA0_config(&config);
IDMA0_wait();
@endverbatim
* ============================================================================
*/
void IDMA0_config(
IDMA0_Config *config
);
/* ===========================================================================
* @n@b IDMA0_configArgs
*
* @b Description
* @n IDMA0_configArgs() - Configures IMDA Channel 0 to perform a
* transfer between Internal Memory and Configuration Space based
* on the inputs to the function. "mask" provides a 1-hot encoding
* for the 32-word tranfer that determines which of the 32-words
* are to be transfered. "src" provides the source location of the
* transfer and "dst provides the destination location of the
* transfer and both must be word aligned. While "cnt" provides the
* number of 32-word transfers to perform and must not be greater
* than 15.
* Initializes the configuration for IDMA Channel 0 including 1-hot
* encoding mask, source location, destination location and count.
*
* @b Arguments
* @verbatim
mask encoding value for the 32-word tranfer
src Pointer to the source location of the transfer
dst Pointer to the destination location of the transfer
cnt number of 32-word transfers
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of IDMA.
*
* @b Example
* @verbatim
Uint32 src,dst;
Uint32 mask;
...
IDMA0_configArgs(mask, src, dst, 1);
IDMA0_wait();
@endverbatim
* ============================================================================
*/
void IDMA0_configArgs (
Uint32 mask,
Uint32 *src,
Uint32 *dst,
Uint32 cnt
);
/* ===========================================================================
* @n@b IDMA0_getStatus
*
* @b Description
* @n IDMA0_getStatus() gets the active and pending status of IMDA
* Channel 0 and returns ACTV in the least significant bit and PEND
* in the 2nd least significant bit
*
* Gets the active and pending status of IDMA channel 0
*
* @b Arguments
* @n None
*
* <b> Return Value </b> IDMA channel 0 status.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 stat;
...
stat = IDMA0_getStatus();
@endverbatim
* ============================================================================
*/
Uint32 IDMA0_getStatus(void);
/* ===========================================================================
* @n@b IDMA0_wait
*
* @b Description
* @n IDMA0_wait() waits until all previous transfers for IDMA Channel
* 0 have been completed by making sure that both active and pend
* bits are zero. These are the two least significant bits of the
* status register for the channel.
*
* Waits until previous transfers have completed for IDMA channel 0
* before returning.
*
* @b Arguments
* @n None
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 stat;
...
stat = IDMA0_getStatus();
IDMA0_wait();
@endverbatim
* ============================================================================
*/
void IDMA0_wait(void);
/* ===========================================================================
* @n@b IDMA0_setInt
*
* @b Description
* @n IDMA0_setInt() sets a the interrupt enable field which
* is used to enable/disable interrupts for IDMA Channel 0.
* It returns the a "32-bit" count register field back to the
* user. This 32-bit register field will be used in
* IDMA0_config() and IDMA0_configArgs() to program the Interrupt
* option for IDMA Channel 0
*
* Enables/Disables interrupt event generation for IDMA channel 0
* transfers
*
* @b Arguments
* @verbatim
interr interrupt event generated on/off
@endverbatim
*
* <b> Return Value </b> idma0_handle_priv.cnt
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
Uint32 tempCnt;
...
// Set and test Interrupt event gen for IDMA0
tempCnt = IDMA0_setInt(IDMA_INT_DIS);
@endverbatim
* ============================================================================
*/
Int IDMA0_setInt (
IDMA_intEn interr
);
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_emifa.h
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_emifa.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for EMIFA
*/
#ifndef _CSLR_EMIFA_H_
#define _CSLR_EMIFA_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 MIDR;
volatile Uint32 STAT;
volatile Uint8 RSVD0[24];
volatile Uint32 BPRIO;
volatile Uint8 RSVD1[92];
volatile Uint32 CE2CFG;
volatile Uint32 CE3CFG;
volatile Uint32 CE4CFG;
volatile Uint32 CE5CFG;
volatile Uint8 RSVD2[16];
volatile Uint32 AWCC;
volatile Uint8 RSVD3[28];
volatile Uint32 INTRAW;
volatile Uint32 INTMSK;
volatile Uint32 INTMSKSET;
volatile Uint32 INTMSKCLR;
} CSL_EmifaRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_EmifaRegs *CSL_EmifaRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* MIDR */
#define CSL_EMIFA_MIDR_MOD_ID_MASK (0x3FFF0000u)
#define CSL_EMIFA_MIDR_MOD_ID_SHIFT (0x00000010u)
#define CSL_EMIFA_MIDR_MOD_ID_RESETVAL (0x00000032u)
#define CSL_EMIFA_MIDR_MJ_REV_MASK (0x0000FF00u)
#define CSL_EMIFA_MIDR_MJ_REV_SHIFT (0x00000008u)
#define CSL_EMIFA_MIDR_MJ_REV_RESETVAL (0x00000003u)
#define CSL_EMIFA_MIDR_MN_REV_MASK (0x000000FFu)
#define CSL_EMIFA_MIDR_MN_REV_SHIFT (0x00000000u)
#define CSL_EMIFA_MIDR_MN_REV_RESETVAL (0x00000010u)
#define CSL_EMIFA_MIDR_RESETVAL (0x00320310u)
/* STAT */
#define CSL_EMIFA_STAT_BE_MASK (0x80000000u)
#define CSL_EMIFA_STAT_BE_SHIFT (0x0000001Fu)
#define CSL_EMIFA_STAT_BE_RESETVAL (0x00000000u)
/*----BE Tokens----*/
#define CSL_EMIFA_STAT_BE_B_ENDIAN (0x00000001u)
#define CSL_EMIFA_STAT_BE_L_ENDIAN (0x00000000u)
#define CSL_EMIFA_STAT_RESETVAL (0x40000000u)
/* BPRIO */
#define CSL_EMIFA_BPRIO_PRIO_RAISE_MASK (0x000000FFu)
#define CSL_EMIFA_BPRIO_PRIO_RAISE_SHIFT (0x00000000u)
#define CSL_EMIFA_BPRIO_PRIO_RAISE_RESETVAL (0x000000FFu)
#define CSL_EMIFA_BPRIO_RESETVAL (0x000000FFu)
/* CE2CFG */
#define CSL_EMIFA_CE2CFG_SSEL_MASK (0x80000000u)
#define CSL_EMIFA_CE2CFG_SSEL_SHIFT (0x0000001Fu)
#define CSL_EMIFA_CE2CFG_SSEL_RESETVAL (0x00000000u)
/*----SSEL Tokens----*/
#define CSL_EMIFA_CE2CFG_SSEL_SYNCMEM (0x00000001u)
#define CSL_EMIFA_CE2CFG_SSEL_ASYNCMEM (0x00000000u)
#define CSL_EMIFA_CE2CFG_SS_MASK (0x40000000u)
#define CSL_EMIFA_CE2CFG_SS_SHIFT (0x0000001Eu)
#define CSL_EMIFA_CE2CFG_SS_RESETVAL (0x00000000u)
/*----SS Tokens----*/
#define CSL_EMIFA_CE2CFG_SS_SSMEN (0x00000001u)
#define CSL_EMIFA_CE2CFG_SS_SSMDIS (0x00000000u)
#define CSL_EMIFA_CE2CFG_BWEM_MASK (0x20000000u)
#define CSL_EMIFA_CE2CFG_BWEM_SHIFT (0x0000001Du)
#define CSL_EMIFA_CE2CFG_BWEM_RESETVAL (0x00000000u)
/*----BWEM Tokens----*/
#define CSL_EMIFA_CE2CFG_BWEM_WESEN (0x00000001u)
#define CSL_EMIFA_CE2CFG_BWEM_WESDIS (0x00000000u)
#define CSL_EMIFA_CE2CFG_AE_MASK (0x10000000u)
#define CSL_EMIFA_CE2CFG_AE_SHIFT (0x0000001Cu)
#define CSL_EMIFA_CE2CFG_AE_RESETVAL (0x00000000u)
/*----AE Tokens----*/
#define CSL_EMIFA_CE2CFG_AE_ARDYEN (0x00000001u)
#define CSL_EMIFA_CE2CFG_AE_ARDYDIS (0x00000000u)
#define CSL_EMIFA_CE2CFG_W_SETUP_MASK (0x0F000000u)
#define CSL_EMIFA_CE2CFG_W_SETUP_SHIFT (0x00000018u)
#define CSL_EMIFA_CE2CFG_W_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIFA_CE2CFG_W_STROBE_MASK (0x00FC0000u)
#define CSL_EMIFA_CE2CFG_W_STROBE_SHIFT (0x00000012u)
#define CSL_EMIFA_CE2CFG_W_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIFA_CE2CFG_W_HOLD_MASK (0x00038000u)
#define CSL_EMIFA_CE2CFG_W_HOLD_SHIFT (0x0000000Fu)
#define CSL_EMIFA_CE2CFG_W_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIFA_CE2CFG_R_SETUP_MASK (0x00007800u)
#define CSL_EMIFA_CE2CFG_R_SETUP_SHIFT (0x0000000Bu)
#define CSL_EMIFA_CE2CFG_R_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIFA_CE2CFG_R_STROBE_MASK (0x000007E0u)
#define CSL_EMIFA_CE2CFG_R_STROBE_SHIFT (0x00000005u)
#define CSL_EMIFA_CE2CFG_R_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIFA_CE2CFG_R_HOLD_MASK (0x0000001Cu)
#define CSL_EMIFA_CE2CFG_R_HOLD_SHIFT (0x00000002u)
#define CSL_EMIFA_CE2CFG_R_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIFA_CE2CFG_ASIZE_MASK (0x00000003u)
#define CSL_EMIFA_CE2CFG_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIFA_CE2CFG_ASIZE_RESETVAL (0x00000000u)
/*----ASIZE Tokens----*/
#define CSL_EMIFA_CE2CFG_ASIZE_8BIT (0x00000000u)
#define CSL_EMIFA_CE2CFG_ASIZE_16BIT (0x00000001u)
#define CSL_EMIFA_CE2CFG_ASIZE_32BIT (0x00000002u)
#define CSL_EMIFA_CE2CFG_ASIZE_64BIT (0x00000003u)
/* The default macro name CSL_EMIFA_CE2CFG_RESETVAL is changed to
* CSL_EMIFA_CE2CFG_SSEL0_RESETVAL
*/
#define CSL_EMIFA_CE2CFG_SSEL0_RESETVAL (0x0FFFFFFCu)
/* CE3CFG */
#define CSL_EMIFA_CE3CFG_SSEL_MASK (0x80000000u)
#define CSL_EMIFA_CE3CFG_SSEL_SHIFT (0x0000001Fu)
#define CSL_EMIFA_CE3CFG_SSEL_RESETVAL (0x00000000u)
/*----SSEL Tokens----*/
#define CSL_EMIFA_CE3CFG_SSEL_SYNCMEM (0x00000001u)
#define CSL_EMIFA_CE3CFG_SSEL_ASYNCMEM (0x00000000u)
#define CSL_EMIFA_CE3CFG_SS_MASK (0x40000000u)
#define CSL_EMIFA_CE3CFG_SS_SHIFT (0x0000001Eu)
#define CSL_EMIFA_CE3CFG_SS_RESETVAL (0x00000000u)
/*----SS Tokens----*/
#define CSL_EMIFA_CE3CFG_SS_SSMEN (0x00000001u)
#define CSL_EMIFA_CE3CFG_SS_SSMDIS (0x00000000u)
#define CSL_EMIFA_CE3CFG_BWEM_MASK (0x20000000u)
#define CSL_EMIFA_CE3CFG_BWEM_SHIFT (0x0000001Du)
#define CSL_EMIFA_CE3CFG_BWEM_RESETVAL (0x00000000u)
/*----BWEM Tokens----*/
#define CSL_EMIFA_CE3CFG_BWEM_WESEN (0x00000001u)
#define CSL_EMIFA_CE3CFG_BWEM_WESDIS (0x00000000u)
#define CSL_EMIFA_CE3CFG_AE_MASK (0x10000000u)
#define CSL_EMIFA_CE3CFG_AE_SHIFT (0x0000001Cu)
#define CSL_EMIFA_CE3CFG_AE_RESETVAL (0x00000000u)
/*----AE Tokens----*/
#define CSL_EMIFA_CE3CFG_AE_ARDYEN (0x00000001u)
#define CSL_EMIFA_CE3CFG_AE_ARDYDIS (0x00000000u)
#define CSL_EMIFA_CE3CFG_W_SETUP_MASK (0x0F000000u)
#define CSL_EMIFA_CE3CFG_W_SETUP_SHIFT (0x00000018u)
#define CSL_EMIFA_CE3CFG_W_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIFA_CE3CFG_W_STROBE_MASK (0x00FC0000u)
#define CSL_EMIFA_CE3CFG_W_STROBE_SHIFT (0x00000012u)
#define CSL_EMIFA_CE3CFG_W_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIFA_CE3CFG_W_HOLD_MASK (0x00038000u)
#define CSL_EMIFA_CE3CFG_W_HOLD_SHIFT (0x0000000Fu)
#define CSL_EMIFA_CE3CFG_W_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIFA_CE3CFG_R_SETUP_MASK (0x00007800u)
#define CSL_EMIFA_CE3CFG_R_SETUP_SHIFT (0x0000000Bu)
#define CSL_EMIFA_CE3CFG_R_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIFA_CE3CFG_R_STROBE_MASK (0x000007E0u)
#define CSL_EMIFA_CE3CFG_R_STROBE_SHIFT (0x00000005u)
#define CSL_EMIFA_CE3CFG_R_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIFA_CE3CFG_R_HOLD_MASK (0x0000001Cu)
#define CSL_EMIFA_CE3CFG_R_HOLD_SHIFT (0x00000002u)
#define CSL_EMIFA_CE3CFG_R_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIFA_CE3CFG_ASIZE_MASK (0x00000003u)
#define CSL_EMIFA_CE3CFG_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIFA_CE3CFG_ASIZE_RESETVAL (0x00000000u)
/*----ASIZE Tokens----*/
#define CSL_EMIFA_CE3CFG_ASIZE_8BIT (0x00000000u)
#define CSL_EMIFA_CE3CFG_ASIZE_16BIT (0x00000001u)
#define CSL_EMIFA_CE3CFG_ASIZE_32BIT (0x00000002u)
#define CSL_EMIFA_CE3CFG_ASIZE_64BIT (0x00000003u)
/* The default macro name CSL_EMIFA_CE3CFG_RESETVAL is changed to
* CSL_EMIFA_CE3CFG_SSEL0_RESETVAL
*/
#define CSL_EMIFA_CE3CFG_SSEL0_RESETVAL (0x0FFFFFFCu)
/* CE4CFG */
#define CSL_EMIFA_CE4CFG_SSEL_MASK (0x80000000u)
#define CSL_EMIFA_CE4CFG_SSEL_SHIFT (0x0000001Fu)
#define CSL_EMIFA_CE4CFG_SSEL_RESETVAL (0x00000000u)
/*----SSEL Tokens----*/
#define CSL_EMIFA_CE4CFG_SSEL_SYNCMEM (0x00000001u)
#define CSL_EMIFA_CE4CFG_SSEL_ASYNCMEM (0x00000000u)
#define CSL_EMIFA_CE4CFG_SS_MASK (0x40000000u)
#define CSL_EMIFA_CE4CFG_SS_SHIFT (0x0000001Eu)
#define CSL_EMIFA_CE4CFG_SS_RESETVAL (0x00000000u)
/*----SS Tokens----*/
#define CSL_EMIFA_CE4CFG_SS_SSMEN (0x00000001u)
#define CSL_EMIFA_CE4CFG_SS_SSMDIS (0x00000000u)
#define CSL_EMIFA_CE4CFG_BWEM_MASK (0x20000000u)
#define CSL_EMIFA_CE4CFG_BWEM_SHIFT (0x0000001Du)
#define CSL_EMIFA_CE4CFG_BWEM_RESETVAL (0x00000000u)
/*----BWEM Tokens----*/
#define CSL_EMIFA_CE4CFG_BWEM_WESEN (0x00000001u)
#define CSL_EMIFA_CE4CFG_BWEM_WESDIS (0x00000000u)
#define CSL_EMIFA_CE4CFG_AE_MASK (0x10000000u)
#define CSL_EMIFA_CE4CFG_AE_SHIFT (0x0000001Cu)
#define CSL_EMIFA_CE4CFG_AE_RESETVAL (0x00000000u)
/*----AE Tokens----*/
#define CSL_EMIFA_CE4CFG_AE_ARDYEN (0x00000001u)
#define CSL_EMIFA_CE4CFG_AE_ARDYDIS (0x00000000u)
#define CSL_EMIFA_CE4CFG_W_SETUP_MASK (0x0F000000u)
#define CSL_EMIFA_CE4CFG_W_SETUP_SHIFT (0x00000018u)
#define CSL_EMIFA_CE4CFG_W_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIFA_CE4CFG_W_STROBE_MASK (0x00FC0000u)
#define CSL_EMIFA_CE4CFG_W_STROBE_SHIFT (0x00000012u)
#define CSL_EMIFA_CE4CFG_W_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIFA_CE4CFG_W_HOLD_MASK (0x00038000u)
#define CSL_EMIFA_CE4CFG_W_HOLD_SHIFT (0x0000000Fu)
#define CSL_EMIFA_CE4CFG_W_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIFA_CE4CFG_R_SETUP_MASK (0x00007800u)
#define CSL_EMIFA_CE4CFG_R_SETUP_SHIFT (0x0000000Bu)
#define CSL_EMIFA_CE4CFG_R_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIFA_CE4CFG_R_STROBE_MASK (0x000007E0u)
#define CSL_EMIFA_CE4CFG_R_STROBE_SHIFT (0x00000005u)
#define CSL_EMIFA_CE4CFG_R_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIFA_CE4CFG_R_HOLD_MASK (0x0000001Cu)
#define CSL_EMIFA_CE4CFG_R_HOLD_SHIFT (0x00000002u)
#define CSL_EMIFA_CE4CFG_R_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIFA_CE4CFG_ASIZE_MASK (0x00000003u)
#define CSL_EMIFA_CE4CFG_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIFA_CE4CFG_ASIZE_RESETVAL (0x00000000u)
/*----ASIZE Tokens----*/
#define CSL_EMIFA_CE4CFG_ASIZE_8BIT (0x00000000u)
#define CSL_EMIFA_CE4CFG_ASIZE_16BIT (0x00000001u)
#define CSL_EMIFA_CE4CFG_ASIZE_32BIT (0x00000002u)
#define CSL_EMIFA_CE4CFG_ASIZE_64BIT (0x00000003u)
/* The default macro name CSL_EMIFA_CE4CFG_RESETVAL is changed to
* CSL_EMIFA_CE4CFG_SSEL0_RESETVAL
*/
#define CSL_EMIFA_CE4CFG_SSEL0_RESETVAL (0x0FFFFFFCu)
/* CE5CFG */
#define CSL_EMIFA_CE5CFG_SSEL_MASK (0x80000000u)
#define CSL_EMIFA_CE5CFG_SSEL_SHIFT (0x0000001Fu)
#define CSL_EMIFA_CE5CFG_SSEL_RESETVAL (0x00000000u)
/*----SSEL Tokens----*/
#define CSL_EMIFA_CE5CFG_SSEL_SYNCMEM (0x00000001u)
#define CSL_EMIFA_CE5CFG_SSEL_ASYNCMEM (0x00000000u)
#define CSL_EMIFA_CE5CFG_SS_MASK (0x40000000u)
#define CSL_EMIFA_CE5CFG_SS_SHIFT (0x0000001Eu)
#define CSL_EMIFA_CE5CFG_SS_RESETVAL (0x00000000u)
/*----SS Tokens----*/
#define CSL_EMIFA_CE5CFG_SS_SSMEN (0x00000001u)
#define CSL_EMIFA_CE5CFG_SS_SSMDIS (0x00000000u)
#define CSL_EMIFA_CE5CFG_BWEM_MASK (0x20000000u)
#define CSL_EMIFA_CE5CFG_BWEM_SHIFT (0x0000001Du)
#define CSL_EMIFA_CE5CFG_BWEM_RESETVAL (0x00000000u)
/*----BWEM Tokens----*/
#define CSL_EMIFA_CE5CFG_BWEM_WESEN (0x00000001u)
#define CSL_EMIFA_CE5CFG_BWEM_WESDIS (0x00000000u)
#define CSL_EMIFA_CE5CFG_AE_MASK (0x10000000u)
#define CSL_EMIFA_CE5CFG_AE_SHIFT (0x0000001Cu)
#define CSL_EMIFA_CE5CFG_AE_RESETVAL (0x00000000u)
/*----AE Tokens----*/
#define CSL_EMIFA_CE5CFG_AE_ARDYEN (0x00000001u)
#define CSL_EMIFA_CE5CFG_AE_ARDYDIS (0x00000000u)
#define CSL_EMIFA_CE5CFG_W_SETUP_MASK (0x0F000000u)
#define CSL_EMIFA_CE5CFG_W_SETUP_SHIFT (0x00000018u)
#define CSL_EMIFA_CE5CFG_W_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIFA_CE5CFG_W_STROBE_MASK (0x00FC0000u)
#define CSL_EMIFA_CE5CFG_W_STROBE_SHIFT (0x00000012u)
#define CSL_EMIFA_CE5CFG_W_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIFA_CE5CFG_W_HOLD_MASK (0x00038000u)
#define CSL_EMIFA_CE5CFG_W_HOLD_SHIFT (0x0000000Fu)
#define CSL_EMIFA_CE5CFG_W_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIFA_CE5CFG_R_SETUP_MASK (0x00007800u)
#define CSL_EMIFA_CE5CFG_R_SETUP_SHIFT (0x0000000Bu)
#define CSL_EMIFA_CE5CFG_R_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIFA_CE5CFG_R_STROBE_MASK (0x000007E0u)
#define CSL_EMIFA_CE5CFG_R_STROBE_SHIFT (0x00000005u)
#define CSL_EMIFA_CE5CFG_R_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIFA_CE5CFG_R_HOLD_MASK (0x0000001Cu)
#define CSL_EMIFA_CE5CFG_R_HOLD_SHIFT (0x00000002u)
#define CSL_EMIFA_CE5CFG_R_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIFA_CE5CFG_ASIZE_MASK (0x00000003u)
#define CSL_EMIFA_CE5CFG_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIFA_CE5CFG_ASIZE_RESETVAL (0x00000000u)
/*----ASIZE Tokens----*/
#define CSL_EMIFA_CE5CFG_ASIZE_8BIT (0x00000000u)
#define CSL_EMIFA_CE5CFG_ASIZE_16BIT (0x00000001u)
#define CSL_EMIFA_CE5CFG_ASIZE_32BIT (0x00000002u)
#define CSL_EMIFA_CE5CFG_ASIZE_64BIT (0x00000003u)
/* The default macro name CSL_EMIFA_CE5CFG_RESETVAL is changed to
* CSL_EMIFA_CE5CFG_SSEL0_RESETVAL
*/
#define CSL_EMIFA_CE5CFG_SSEL0_RESETVAL (0x0FFFFFFCu)
/* AWCC */
#define CSL_EMIFA_AWCC_AP_MASK (0x40000000u)
#define CSL_EMIFA_AWCC_AP_SHIFT (0x0000001Eu)
#define CSL_EMIFA_AWCC_AP_RESETVAL (0x00000001u)
/*----AP Tokens----*/
#define CSL_EMIFA_AWCC_AP_ACTHIGH (0x00000001u)
#define CSL_EMIFA_AWCC_AP_ACTLOW (0x00000000u)
#define CSL_EMIFA_AWCC_TA_MASK (0x00000700u)
#define CSL_EMIFA_AWCC_TA_SHIFT (0x00000008u)
#define CSL_EMIFA_AWCC_TA_RESETVAL (0x00000003u)
#define CSL_EMIFA_AWCC_MAX_EXT_WAIT_MASK (0x000000FFu)
#define CSL_EMIFA_AWCC_MAX_EXT_WAIT_SHIFT (0x00000000u)
#define CSL_EMIFA_AWCC_MAX_EXT_WAIT_RESETVAL (0x00000080u)
#define CSL_EMIFA_AWCC_RESETVAL (0x40000380u)
/* INTRAW */
#define CSL_EMIFA_INTRAW_AT_MASK (0x00000001u)
#define CSL_EMIFA_INTRAW_AT_SHIFT (0x00000000u)
#define CSL_EMIFA_INTRAW_AT_RESETVAL (0x00000000u)
/*----AT Tokens----*/
#define CSL_EMIFA_INTRAW_AT_SET (0x00000001u)
#define CSL_EMIFA_INTRAW_AT_CLEAR (0x00000000u)
#define CSL_EMIFA_INTRAW_RESETVAL (0x00000000u)
/* INTMSK */
#define CSL_EMIFA_INTMSK_AT_MASKED_MASK (0x00000001u)
#define CSL_EMIFA_INTMSK_AT_MASKED_SHIFT (0x00000000u)
#define CSL_EMIFA_INTMSK_AT_MASKED_RESETVAL (0x00000000u)
/*----AT_MASKED Tokens----*/
#define CSL_EMIFA_INTMSK_AT_MASKED_SET (0x00000001u)
#define CSL_EMIFA_INTMSK_AT_MASKED_CLEAR (0x00000000u)
#define CSL_EMIFA_INTMSK_RESETVAL (0x00000000u)
/* INTMSKSET */
#define CSL_EMIFA_INTMSKSET_AT_MASK_SET_MASK (0x00000001u)
#define CSL_EMIFA_INTMSKSET_AT_MASK_SET_SHIFT (0x00000000u)
#define CSL_EMIFA_INTMSKSET_AT_MASK_SET_RESETVAL (0x00000000u)
/*----AT_MASK_SET Tokens----*/
#define CSL_EMIFA_INTMSKSET_AT_MASK_SET_SET (0x00000001u)
#define CSL_EMIFA_INTMSKSET_AT_MASK_SET_CLEAR (0x00000000u)
#define CSL_EMIFA_INTMSKSET_RESETVAL (0x00000000u)
/* INTMSKCLR */
#define CSL_EMIFA_INTMSKCLR_AT_MASK_CLR_MASK (0x00000001u)
#define CSL_EMIFA_INTMSKCLR_AT_MASK_CLR_SHIFT (0x00000000u)
#define CSL_EMIFA_INTMSKCLR_AT_MASK_CLR_RESETVAL (0x00000000u)
/*----AT_MASK_CLR Tokens----*/
#define CSL_EMIFA_INTMSKCLR_AT_MASK_CLR_SET (0x00000001u)
#define CSL_EMIFA_INTMSKCLR_AT_MASK_CLR_CLEAR (0x00000000u)
#define CSL_EMIFA_INTMSKCLR_RESETVAL (0x00000000u)
/* CE2CFG when ssel=1 */
#define CSL_EMIFA_CE2CFG_SSEL_MASK (0x80000000u)
#define CSL_EMIFA_CE2CFG_SSEL_SHIFT (0x0000001Fu)
#define CSL_EMIFA_CE2CFG_SSEL_RESETVAL (0x00000000u)
/*----SSEL Tokens----*/
#define CSL_EMIFA_CE2CFG_SSEL_SYNCMEM (0x00000001u)
#define CSL_EMIFA_CE2CFG_SSEL_ASYNCMEM (0x00000000u)
#define CSL_EMIFA_CE2CFG_RD_BE_EN_MASK (0x00000400u)
#define CSL_EMIFA_CE2CFG_RD_BE_EN_SHIFT (0x0000000Au)
#define CSL_EMIFA_CE2CFG_RD_BE_EN_RESETVAL (0x00000000u)
/*----RD_BE_EN Tokens----*/
#define CSL_EMIFA_CE2CFG_RD_BE_EN_SET (0x00000001u)
#define CSL_EMIFA_CE2CFG_RD_BE_EN_CLR (0x00000000u)
#define CSL_EMIFA_CE2CFG_CE_EXT_MASK (0x00000200u)
#define CSL_EMIFA_CE2CFG_CE_EXT_SHIFT (0x00000009u)
#define CSL_EMIFA_CE2CFG_CE_EXT_RESETVAL (0x00000000u)
/*----CE_EXT Tokens----*/
#define CSL_EMIFA_CE2CFG_CE_EXT_SET (0x00000001u)
#define CSL_EMIFA_CE2CFG_CE_EXT_CLR (0x00000000u)
#define CSL_EMIFA_CE2CFG_R_ENABLE_MASK (0x00000100u)
#define CSL_EMIFA_CE2CFG_R_ENABLE_SHIFT (0x00000008u)
#define CSL_EMIFA_CE2CFG_R_ENABLE_RESETVAL (0x00000000u)
/*----R_ENABLE Tokens----*/
#define CSL_EMIFA_CE2CFG_R_ENABLE_SET (0x00000001u)
#define CSL_EMIFA_CE2CFG_R_ENABLE_CLR (0x00000000u)
#define CSL_EMIFA_CE2CFG_W_LTNCY_MASK (0x000000C0u)
#define CSL_EMIFA_CE2CFG_W_LTNCY_SHIFT (0x00000006u)
#define CSL_EMIFA_CE2CFG_W_LTNCY_RESETVAL (0x00000000u)
/*----W_LTNCY Tokens----*/
#define CSL_EMIFA_CE2CFG_W_LTNCY_ZEROCYCLE (0x00000000u)
#define CSL_EMIFA_CE2CFG_W_LTNCY_ONECYCLE (0x00000001u)
#define CSL_EMIFA_CE2CFG_W_LTNCY_TWOCYCLE (0x00000002u)
#define CSL_EMIFA_CE2CFG_W_LTNCY_THREECYCLE (0x00000003u)
#define CSL_EMIFA_CE2CFG_R_LTNCY_MASK (0x0000000Cu)
#define CSL_EMIFA_CE2CFG_R_LTNCY_SHIFT (0x00000002u)
#define CSL_EMIFA_CE2CFG_R_LTNCY_RESETVAL (0x00000000u)
/*----R_LTNCY Tokens----*/
#define CSL_EMIFA_CE2CFG_R_LTNCY_ONECYCLE (0x00000001u)
#define CSL_EMIFA_CE2CFG_R_LTNCY_TWOCYCLE (0x00000002u)
#define CSL_EMIFA_CE2CFG_R_LTNCY_THREECYCLE (0x00000003u)
#define CSL_EMIFA_CE2CFG_SBSIZE_MASK (0x00000003u)
#define CSL_EMIFA_CE2CFG_SBSIZE_SHIFT (0x00000000u)
#define CSL_EMIFA_CE2CFG_SBSIZE_RESETVAL (0x00000000u)
/*----SBSIZE Tokens----*/
#define CSL_EMIFA_CE2CFG_SBSIZE_8BIT (0x00000000u)
#define CSL_EMIFA_CE2CFG_SBSIZE_16BIT (0x00000001u)
#define CSL_EMIFA_CE2CFG_SBSIZE_32BIT (0x00000002u)
#define CSL_EMIFA_CE2CFG_SBSIZE_64BIT (0x00000003u)
/* The default macro name CSL_EMIFA_CE2CFG_RESETVAL is changed to
* CSL_EMIFA_CE2CFG_SSEL1_RESETVAL
*/
#define CSL_EMIFA_CE2CFG_SSEL1_RESETVAL (0x00000000u)
/* CE3CFG when ssel=1 */
#define CSL_EMIFA_CE3CFG_SSEL_MASK (0x80000000u)
#define CSL_EMIFA_CE3CFG_SSEL_SHIFT (0x0000001Fu)
#define CSL_EMIFA_CE3CFG_SSEL_RESETVAL (0x00000000u)
/*----SSEL Tokens----*/
#define CSL_EMIFA_CE3CFG_SSEL_SYNCMEM (0x00000001u)
#define CSL_EMIFA_CE3CFG_SSEL_ASYNCMEM (0x00000000u)
#define CSL_EMIFA_CE3CFG_RD_BE_EN_MASK (0x00000400u)
#define CSL_EMIFA_CE3CFG_RD_BE_EN_SHIFT (0x0000000Au)
#define CSL_EMIFA_CE3CFG_RD_BE_EN_RESETVAL (0x00000000u)
/*----RD_BE_EN Tokens----*/
#define CSL_EMIFA_CE3CFG_RD_BE_EN_SET (0x00000001u)
#define CSL_EMIFA_CE3CFG_RD_BE_EN_CLR (0x00000000u)
#define CSL_EMIFA_CE3CFG_CE_EXT_MASK (0x00000200u)
#define CSL_EMIFA_CE3CFG_CE_EXT_SHIFT (0x00000009u)
#define CSL_EMIFA_CE3CFG_CE_EXT_RESETVAL (0x00000000u)
/*----CE_EXT Tokens----*/
#define CSL_EMIFA_CE3CFG_CE_EXT_SET (0x00000001u)
#define CSL_EMIFA_CE3CFG_CE_EXT_CLR (0x00000000u)
#define CSL_EMIFA_CE3CFG_R_ENABLE_MASK (0x00000100u)
#define CSL_EMIFA_CE3CFG_R_ENABLE_SHIFT (0x00000008u)
#define CSL_EMIFA_CE3CFG_R_ENABLE_RESETVAL (0x00000000u)
/*----R_ENABLE Tokens----*/
#define CSL_EMIFA_CE3CFG_R_ENABLE_SET (0x00000001u)
#define CSL_EMIFA_CE3CFG_R_ENABLE_CLR (0x00000000u)
#define CSL_EMIFA_CE3CFG_W_LTNCY_MASK (0x000000C0u)
#define CSL_EMIFA_CE3CFG_W_LTNCY_SHIFT (0x00000006u)
#define CSL_EMIFA_CE3CFG_W_LTNCY_RESETVAL (0x00000000u)
/*----W_LTNCY Tokens----*/
#define CSL_EMIFA_CE3CFG_W_LTNCY_ZEROCYCLE (0x00000000u)
#define CSL_EMIFA_CE3CFG_W_LTNCY_ONECYCLE (0x00000001u)
#define CSL_EMIFA_CE3CFG_W_LTNCY_TWOCYCLE (0x00000002u)
#define CSL_EMIFA_CE3CFG_W_LTNCY_THREECYCLE (0x00000003u)
#define CSL_EMIFA_CE3CFG_R_LTNCY_MASK (0x0000000Cu)
#define CSL_EMIFA_CE3CFG_R_LTNCY_SHIFT (0x00000002u)
#define CSL_EMIFA_CE3CFG_R_LTNCY_RESETVAL (0x00000000u)
/*----R_LTNCY Tokens----*/
#define CSL_EMIFA_CE3CFG_R_LTNCY_ONECYCLE (0x00000001u)
#define CSL_EMIFA_CE3CFG_R_LTNCY_TWOCYCLE (0x00000002u)
#define CSL_EMIFA_CE3CFG_R_LTNCY_THREECYCLE (0x00000003u)
#define CSL_EMIFA_CE3CFG_SBSIZE_MASK (0x00000003u)
#define CSL_EMIFA_CE3CFG_SBSIZE_SHIFT (0x00000000u)
#define CSL_EMIFA_CE3CFG_SBSIZE_RESETVAL (0x00000000u)
/*----SBSIZE Tokens----*/
#define CSL_EMIFA_CE3CFG_SBSIZE_8BIT (0x00000000u)
#define CSL_EMIFA_CE3CFG_SBSIZE_16BIT (0x00000001u)
#define CSL_EMIFA_CE3CFG_SBSIZE_32BIT (0x00000002u)
#define CSL_EMIFA_CE3CFG_SBSIZE_64BIT (0x00000003u)
/* The default macro name CSL_EMIFA_CE3CFG_RESETVAL is changed to
* CSL_EMIFA_CE3CFG_SSEL1_RESETVAL
*/
#define CSL_EMIFA_CE3CFG_SSEL1_RESETVAL (0x00000000u)
/* CE4CFG when ssel=1 */
#define CSL_EMIFA_CE4CFG_SSEL_MASK (0x80000000u)
#define CSL_EMIFA_CE4CFG_SSEL_SHIFT (0x0000001Fu)
#define CSL_EMIFA_CE4CFG_SSEL_RESETVAL (0x00000000u)
/*----SSEL Tokens----*/
#define CSL_EMIFA_CE4CFG_SSEL_SYNCMEM (0x00000001u)
#define CSL_EMIFA_CE4CFG_SSEL_ASYNCMEM (0x00000000u)
#define CSL_EMIFA_CE4CFG_RD_BE_EN_MASK (0x00000400u)
#define CSL_EMIFA_CE4CFG_RD_BE_EN_SHIFT (0x0000000Au)
#define CSL_EMIFA_CE4CFG_RD_BE_EN_RESETVAL (0x00000000u)
/*----RD_BE_EN Tokens----*/
#define CSL_EMIFA_CE4CFG_RD_BE_EN_SET (0x00000001u)
#define CSL_EMIFA_CE4CFG_RD_BE_EN_CLR (0x00000000u)
#define CSL_EMIFA_CE4CFG_CE_EXT_MASK (0x00000200u)
#define CSL_EMIFA_CE4CFG_CE_EXT_SHIFT (0x00000009u)
#define CSL_EMIFA_CE4CFG_CE_EXT_RESETVAL (0x00000000u)
/*----CE_EXT Tokens----*/
#define CSL_EMIFA_CE4CFG_CE_EXT_SET (0x00000001u)
#define CSL_EMIFA_CE4CFG_CE_EXT_CLR (0x00000000u)
#define CSL_EMIFA_CE4CFG_R_ENABLE_MASK (0x00000100u)
#define CSL_EMIFA_CE4CFG_R_ENABLE_SHIFT (0x00000008u)
#define CSL_EMIFA_CE4CFG_R_ENABLE_RESETVAL (0x00000000u)
/*----R_ENABLE Tokens----*/
#define CSL_EMIFA_CE4CFG_R_ENABLE_SET (0x00000001u)
#define CSL_EMIFA_CE4CFG_R_ENABLE_CLR (0x00000000u)
#define CSL_EMIFA_CE4CFG_W_LTNCY_MASK (0x000000C0u)
#define CSL_EMIFA_CE4CFG_W_LTNCY_SHIFT (0x00000006u)
#define CSL_EMIFA_CE4CFG_W_LTNCY_RESETVAL (0x00000000u)
/*----W_LTNCY Tokens----*/
#define CSL_EMIFA_CE4CFG_W_LTNCY_ZEROCYCLE (0x00000000u)
#define CSL_EMIFA_CE4CFG_W_LTNCY_ONECYCLE (0x00000001u)
#define CSL_EMIFA_CE4CFG_W_LTNCY_TWOCYCLE (0x00000002u)
#define CSL_EMIFA_CE4CFG_W_LTNCY_THREECYCLE (0x00000003u)
#define CSL_EMIFA_CE4CFG_R_LTNCY_MASK (0x0000000Cu)
#define CSL_EMIFA_CE4CFG_R_LTNCY_SHIFT (0x00000002u)
#define CSL_EMIFA_CE4CFG_R_LTNCY_RESETVAL (0x00000000u)
/*----R_LTNCY Tokens----*/
#define CSL_EMIFA_CE4CFG_R_LTNCY_ONECYCLE (0x00000001u)
#define CSL_EMIFA_CE4CFG_R_LTNCY_TWOCYCLE (0x00000002u)
#define CSL_EMIFA_CE4CFG_R_LTNCY_THREECYCLE (0x00000003u)
#define CSL_EMIFA_CE4CFG_SBSIZE_MASK (0x00000003u)
#define CSL_EMIFA_CE4CFG_SBSIZE_SHIFT (0x00000000u)
#define CSL_EMIFA_CE4CFG_SBSIZE_RESETVAL (0x00000000u)
/*----SBSIZE Tokens----*/
#define CSL_EMIFA_CE4CFG_SBSIZE_8BIT (0x00000000u)
#define CSL_EMIFA_CE4CFG_SBSIZE_16BIT (0x00000001u)
#define CSL_EMIFA_CE4CFG_SBSIZE_32BIT (0x00000002u)
#define CSL_EMIFA_CE4CFG_SBSIZE_64BIT (0x00000003u)
/* The default macro name CSL_EMIFA_CE4CFG_RESETVAL is changed to
* CSL_EMIFA_CE4CFG_SSEL1_RESETVAL
*/
#define CSL_EMIFA_CE4CFG_SSEL1_RESETVAL (0x00000000u)
/* CE5CFG when ssel=1*/
#define CSL_EMIFA_CE5CFG_SSEL_MASK (0x80000000u)
#define CSL_EMIFA_CE5CFG_SSEL_SHIFT (0x0000001Fu)
#define CSL_EMIFA_CE5CFG_SSEL_RESETVAL (0x00000000u)
/*----SSEL Tokens----*/
#define CSL_EMIFA_CE5CFG_SSEL_SYNCMEM (0x00000001u)
#define CSL_EMIFA_CE5CFG_SSEL_ASYNCMEM (0x00000000u)
#define CSL_EMIFA_CE5CFG_RD_BE_EN_MASK (0x00000400u)
#define CSL_EMIFA_CE5CFG_RD_BE_EN_SHIFT (0x0000000Au)
#define CSL_EMIFA_CE5CFG_RD_BE_EN_RESETVAL (0x00000000u)
/*----RD_BE_EN Tokens----*/
#define CSL_EMIFA_CE5CFG_RD_BE_EN_SET (0x00000001u)
#define CSL_EMIFA_CE5CFG_RD_BE_EN_CLR (0x00000000u)
#define CSL_EMIFA_CE5CFG_CE_EXT_MASK (0x00000200u)
#define CSL_EMIFA_CE5CFG_CE_EXT_SHIFT (0x00000009u)
#define CSL_EMIFA_CE5CFG_CE_EXT_RESETVAL (0x00000000u)
/*----CE_EXT Tokens----*/
#define CSL_EMIFA_CE5CFG_CE_EXT_SET (0x00000001u)
#define CSL_EMIFA_CE5CFG_CE_EXT_CLR (0x00000000u)
#define CSL_EMIFA_CE5CFG_R_ENABLE_MASK (0x00000100u)
#define CSL_EMIFA_CE5CFG_R_ENABLE_SHIFT (0x00000008u)
#define CSL_EMIFA_CE5CFG_R_ENABLE_RESETVAL (0x00000000u)
/*----R_ENABLE Tokens----*/
#define CSL_EMIFA_CE5CFG_R_ENABLE_SET (0x00000001u)
#define CSL_EMIFA_CE5CFG_R_ENABLE_CLR (0x00000000u)
#define CSL_EMIFA_CE5CFG_W_LTNCY_MASK (0x000000C0u)
#define CSL_EMIFA_CE5CFG_W_LTNCY_SHIFT (0x00000006u)
#define CSL_EMIFA_CE5CFG_W_LTNCY_RESETVAL (0x00000000u)
/*----W_LTNCY Tokens----*/
#define CSL_EMIFA_CE5CFG_W_LTNCY_ZEROCYCLE (0x00000000u)
#define CSL_EMIFA_CE5CFG_W_LTNCY_ONECYCLE (0x00000001u)
#define CSL_EMIFA_CE5CFG_W_LTNCY_TWOCYCLE (0x00000002u)
#define CSL_EMIFA_CE5CFG_W_LTNCY_THREECYCLE (0x00000003u)
#define CSL_EMIFA_CE5CFG_R_LTNCY_MASK (0x0000000Cu)
#define CSL_EMIFA_CE5CFG_R_LTNCY_SHIFT (0x00000002u)
#define CSL_EMIFA_CE5CFG_R_LTNCY_RESETVAL (0x00000000u)
/*----R_LTNCY Tokens----*/
#define CSL_EMIFA_CE5CFG_R_LTNCY_ONECYCLE (0x00000001u)
#define CSL_EMIFA_CE5CFG_R_LTNCY_TWOCYCLE (0x00000002u)
#define CSL_EMIFA_CE5CFG_R_LTNCY_THREECYCLE (0x00000003u)
#define CSL_EMIFA_CE5CFG_SBSIZE_MASK (0x00000003u)
#define CSL_EMIFA_CE5CFG_SBSIZE_SHIFT (0x00000000u)
#define CSL_EMIFA_CE5CFG_SBSIZE_RESETVAL (0x00000000u)
/*----SBSIZE Tokens----*/
#define CSL_EMIFA_CE5CFG_SBSIZE_8BIT (0x00000000u)
#define CSL_EMIFA_CE5CFG_SBSIZE_16BIT (0x00000001u)
#define CSL_EMIFA_CE5CFG_SBSIZE_32BIT (0x00000002u)
#define CSL_EMIFA_CE5CFG_SBSIZE_64BIT (0x00000003u)
/* The default macro name CSL_EMIFA_CE5CFG_RESETVAL is changed to
* CSL_EMIFA_CE5CFG_SSEL1_RESETVAL
*/
#define CSL_EMIFA_CE5CFG_SSEL1_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/idma/src/Idma_example.c
|
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ============================================================================
*
* @file Idma_example.c
*
* @path $(CSLPATH)\example\idma\src
*
* @desc Example of IDMA CSL
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n The example shows how to use the idma for data transfer from one memory
* area to another memory area
* This example demonstrates the following operations.
* - Initializes IDMA channel 1
* - Sets channel 1 to have priority 7 and interrupt event generation on
* - Initializes IDMA channel 0
* - Sets channel 0 to have interrupt event generation on
* - Clears dst1 array
* - Perform copy of data from src to dst1
* - Waits until copying is completed
* - Compars the source and destination buffers
* - Fill the dst1 array with the value "0xAAAABABA"
* - Copies dst1 data into dst0.
* - Gets IDMA1 status is active after the submission for the transfer
* - Does the data comparision to ensure the copied data is proper or
* not and
* - Displays the result based on previous step
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Idma_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 27-Jul-2005 ds File Created
*
* 16-Dec-2005 ds Updated documentation
* ============================================================================
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <csl_idma.h>
/* Align various arrays to a double word address, in internal L2 */
#pragma DATA_SECTION(src, "ISRAM");
#pragma DATA_SECTION(dst0, "ISRAM1");
#pragma DATA_SECTION(dst1, "ISRAM1");
#pragma DATA_ALIGN(src, 8);
#pragma DATA_ALIGN(dst0, 8);
#pragma DATA_ALIGN(dst1, 8);
/* Static 80 byte array of data in "src" */
Uint32 src[20] =
{
0xDEADBEEF, 0xFADEBABE, 0x5AA51C3A, 0xD4536BA3,
0x5E69BA23, 0x4884A01F, 0x9265ACDA, 0xFFFF0123,
0xBEADDABE, 0x234A76B2, 0x9675ABCD, 0xABCDEF12,
0xEEEECDEA, 0x01234567, 0x00000000, 0xFEEDFADE,
0x0A1B2C3D, 0x4E5F6B7C, 0x5AA5ECCE, 0xFABEFACE
};
/* Static 80 byte array of data in "dst0" */
Uint32 dst0[0x200] =
{
0x00010203, 0x04050607, 0x08090A0B, 0x10111213,
0x14151617, 0x18191A1B, 0x1C1D1E1F, 0x20212123,
0x24252627, 0x28292A2B, 0x2C2D2E2F, 0x30313233,
0x34353637, 0x38393A3B, 0x3C3D3E3F, 0x40414243,
0x44454647, 0x48494A4B, 0x4C4D4E4F, 0x50515253
};
/* Forward declaration */
void idma_example (void);
/* Array in which results will be copied over */
Uint32 dst1[0x200];
/* Global variable to check fail status of example */
Uint32 idmaExampleFailed = 0;
void main(void)
{
/* Invoke a example */
idma_example ();
if (idmaExampleFailed > 0) {
printf ("<<Example Failed>>: example failed. [Examples failed: %d]\n", \
idmaExampleFailed);
}
else {
printf ("<<Example Passed>>: Idma example passed.\n");
}
printf("===============================================================\n");
return;
}
/*
* =============================================================================
* @func idma_example
*
* @arg
* NONE
*
* @desc
* This example shows how idma csl performs the data transfer between
* source and destination buffers
*
* @return
* NONE
*
* =============================================================================
*/
void idma_example (void)
{
Uint32 cnt0;
Uint32 cnt1;
Uint32 stat;
Uint32 count;
/* Initialize IDMA Channel 1
* Set Chan 1 to have Priority 7 and Interrupt Event Gen On
*/
cnt1 = IDMA1_init(IDMA_PRI_7, IDMA_INT_EN);
printf("Runnning IDMA Example \n");
if (cnt1 != 0xF0000000){
printf("Set the channel 1 to have priority 7 and interrupt event ");
printf("generation enable failed.\n");
idmaExampleFailed++;
return;
}
else {
printf("Set the channel 1 to have priority 7 and interrupt event ");
printf("generation enable passed.\n");
printf("Channel 0 initialization passed.\n");
}
/* Initialize IDMA channel 0
* Set channel 0 to have interrupt event generation ON
*/
cnt0 = IDMA0_init(IDMA_INT_EN);
if (cnt0 != 0x10000000){
printf("Set the channel 0 to have interrupt event generation ");
printf("enable failed.\n");
idmaExampleFailed++;
return;
}
else {
printf("Set the channel 0 to have interrupt event generation ");
printf("enable passed.\n");
}
/* Clear dst1 array */
memset(dst1, 0, sizeof(dst1));
/* Copy src to dst1 - 80 bytes - 20 words */
IDMA1_copy(src, dst1, 80);
/* Wait until copying is completed */
IDMA1_wait();
/* Comparing the source and destination buffers */
if (memcmp(src, dst1, sizeof(src))) {
printf("IDMA: data copy from source to destination using idma is ");
printf("failed\n");
idmaExampleFailed++;
return;
}
else {
for(count = 0; count < 20; count++)
printf("value of src[%d]: 0x%x,value of dst[%d]: 0x%x\n", \
count, src[count], count, dst1[count]);
printf("IDMA: data copy from source to destination using idma is ");
printf("passed\n");
}
printf("===============================================================\n");
/*
* The following shows fill capability of Channel
* 1. First fill the dst1 array with the value "0xAAAABABA".
* 2. Now copy dst1 into dst0.
*
* This is an example of a backward transfer where address of
* "dst0" is less than "dst1".
*/
printf("Data fill example\n");
IDMA1_fill(dst1, 0x800, 0xAAAABABA);
/* This simulator requires IDMA1_wait between all transfers for
* the transfers to work correctly.
*/
IDMA1_wait();
for(count = 0; count < 20; count++)
printf("value of dst[%d]: 0x%x\n",count,dst1[count]);
/* Perform the transfer from "dst1" to "dst0". Recall that
* "dst1" was just filled with a constant pattern 0xAAAABABA.
* Also verify that getStatus function is working by checking if
* IDMA1 status is ACTV after the submission for the transfer
*/
IDMA1_copy(dst1, dst0, 0x800);
stat = IDMA1_getStatus();
if(stat != 1) {
printf("IDMA channel 1 not in the active status.\n");
idmaExampleFailed++;
return;
}
else {
printf("IDMA channel 1 in the active status.\n");
}
/* IDMA1_wait() waits until all previous transfers for IDMA Channel 1
* have been completed
*/
IDMA1_wait();
if (memcmp(dst0, dst1, sizeof(dst0))) {
printf("IDMA: data fill failed.\n");
idmaExampleFailed++;
return;
}
else {
printf("IDAM: data fill passed.\n");
}
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cClose.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cClose.c<gh_stars>0
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ===========================================================================
* @file csl_i2cClose.c
*
* @brief File for functional layer of CSL API CSL_i2cClose()
*
* @path $(CSLPATH)\i2c\src
*
* Description
* - The CSL_i2cClose() function definition & it's associated functions
*
*
* Modification 1
* - Created on: 28/5/2004
* - Reason: created the sources
*
* @date 28th May, 2004
* @author <NAME>.
* ============================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 31-aug-2004 Hs Updated function and documentation for CSL_i2cclose.
* - Removed the include file, csl_resource.h.
* 11-oct-2004 Hs updated according to code review comments.
*
* =============================================================================
*/
#include <csl_i2c.h>
/** ============================================================================
* @n@b CSL_i2cClose
*
* @b Description
* @n This function closes the specified instance of I2C.
*
* @b Arguments
* @verbatim
hI2c Handle to the I2C
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close Successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n The device should be successfully opened.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n I2C Handle
*
* @b Example
* @verbatim
CSL_I2cHandle hI2c;
...
status = CSL_i2cClose(hI2c);
...
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_i2cClose, ".text:csl_section:i2c");
CSL_Status CSL_i2cClose (
CSL_I2cHandle hI2c
)
{
CSL_Status status = CSL_SOK;
if (hI2c != NULL) {
hI2c->regs = (CSL_I2cRegsOvly)NULL;
hI2c->perNum = (CSL_InstNum)-1;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_pwrdwnAux.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ===========================================================================
* @file csl_pwrdwnAux.h
*
* @brief API Auxilary header file for PWRDWN CSL
*
* @path $(CSLPATH)\inc
*
* @desc PWRDWN module
* Modification : 30th Aug 2004
* Modified function
* Added documentation
* ============================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 20-Dec-2005 Modified CSL_pwrdwnGetPage1SleepStatus () and
* CSL_pwrdwnGetPage0SleepStatus () to fix issue in release
* mode
* 01-Mar-2006 Modified CSL_pwrdwnPage1Wake () to fix bug PSG00000880
* =============================================================================
*/
#ifndef _CSL_PWRDWNAUX_H
#define _CSL_PWRDWNAUX_H
#ifdef __cplusplus
extern "C" {
#endif
#define CSL_IDEF_INLINE static inline
/** @addtogroup CSL_PWRDWN_FUNCTION_INTERNAL
@{ */
/** ============================================================================
* @n@b CSL_pwrdwnPage0Sleep
*
* @b Description
* @n Manual power down. Puts page0 on specified port to sleep
*
* @b Arguments
* @verbatim
hPwr Handle to the power down module
arg consists of port number and page0 on the port that need
to be put to sleep
@endverbatim
*
* <b> Return Value </b> Status (CSL_SOK)
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Puts page0 on specified port to sleep
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
CSL_PwrdwnPortData *arg
arg.portNum = 0x0;
arg.data = 0x1;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
CSL_pwrdwnPage0Sleep(hPwr, (CSL_PwrdwnPortData *)&arg);
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE
CSL_Status CSL_pwrdwnPage0Sleep (
CSL_PwrdwnHandle hPwr,
CSL_PwrdwnPortData *arg
)
{
CSL_FINS(hPwr->l2pwrdwnRegs->L2PDSLEEP[arg->portNum],
L2PWRDWN_L2PDSLEEP_P0, arg->data);
return CSL_SOK;
}
/** ============================================================================
* @n@b CSL_pwrdwnPage1Sleep
*
* @b Description
* @n Manual power down. Puts page1 on specified port to sleep
*
* @b Arguments
* @verbatim
hPwr Handle to the power down module
arg consists of port number and page1 on the port that need
to be put to sleep
@endverbatim
*
* <b> Return Value </b> Status (CSL_SOK)
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Puts page1 on specified port to sleep
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
CSL_PwrdwnPortData *arg
arg.portNum = 0x0;
arg.data = 0x1;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
CSL_pwrdwnPage1Sleep(hPwr, (CSL_PwrdwnPortData *)&arg);
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE
CSL_Status CSL_pwrdwnPage1Sleep (
CSL_PwrdwnHandle hPwr,
CSL_PwrdwnPortData *arg
)
{
CSL_FINS(hPwr->l2pwrdwnRegs->L2PDSLEEP[arg->portNum],
L2PWRDWN_L2PDSLEEP_P1, arg->data);
return CSL_SOK;
}
/** ============================================================================
* @n@b CSL_pwrdwnPage0Wake
*
* @b Description
* @n Manual page wake. Awakes page0 on specified port.
*
* @b Arguments
* @verbatim
hPwr Handle to the power down module
wake consists of port number and page0 on the port that need
to be put to woken
@endverbatim
*
* <b> Return Value </b> Status (CSL_SOK)
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Awakes page0 on specified port
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
arg.portNum = 0x0;
arg.data = 0x1;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
CSL_pwrdwnPage0Wake(hPwr, (CSL_PwrdwnPortData *)&arg);
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE
CSL_Status CSL_pwrdwnPage0Wake (
CSL_PwrdwnHandle hPwr,
CSL_PwrdwnPortData *arg
)
{
CSL_FINS(hPwr->l2pwrdwnRegs->L2PDWAKE[arg->portNum],
L2PWRDWN_L2PDWAKE_P0, arg->data);
return CSL_SOK;
}
/** ============================================================================
* @n@b CSL_pwrdwnPage1Wake
*
* @b Description
* @n Manual page wake. Awakes page0 on specified port.
*
* @b Arguments
* @verbatim
hPwr Handle to the power down module
wake consists of port number and page1 on the port that need
to be put to woken
@endverbatim
*
* <b> Return Value </b> Status (CSL_SOK)
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Awakes page1 on specified port
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
arg.portNum = 0x0;
arg.data = 0x1;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
CSL_pwrdwnPage1Wake(hPwr, (CSL_PwrdwnPortData *)&arg);
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE
CSL_Status CSL_pwrdwnPage1Wake (
CSL_PwrdwnHandle hPwr,
CSL_PwrdwnPortData *arg
)
{
CSL_FINS(hPwr->l2pwrdwnRegs->L2PDWAKE[arg->portNum],
L2PWRDWN_L2PDWAKE_P1, arg->data);
return CSL_SOK;
}
/** ============================================================================
* @n@b CSL_pwrdwnGetPage0SleepStatus
*
* @b Description
* @n Queries page0 status.
*
* @b Arguments
* @verbatim
hPwr Handle to the power down module
response Place holder for sleep status of the page0 on specified port
@endverbatim
*
* <b> Return Value </b> Status (CSL_SOK)
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
CSL_PwrdwnPortData response;
response.portNum = 0x0;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
CSL_pwrdwnGetPage0SleepStatus(hPwr, (CSL_PwrdwnPortData *)&response);
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE
void CSL_pwrdwnGetPage0SleepStatus (
CSL_PwrdwnHandle hPwr,
CSL_PwrdwnPortData *response
)
{
volatile Uint8 data;
data = CSL_FEXT(hPwr->l2pwrdwnRegs->L2PDSTAT[response->portNum],
L2PWRDWN_L2PDSTAT_P0);
response->data = data;
}
/** ============================================================================
* @n@b CSL_pwrdwnGetPage1SleepStatus
*
* @b Description
* @n Queries page1 status.
*
* @b Arguments
* @verbatim
hPwr Handle to the power down module
response Place holder for sleep status of the page1 on specified port
@endverbatim
*
* <b> Return Value </b> Status (CSL_SOK)
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
CSL_PwrdwnPortData response;
response.portNum = 0x0;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
CSL_pwrdwnGetPage1SleepStatus(hPwr, (CSL_PwrdwnPortData *)&response);
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE
void CSL_pwrdwnGetPage1SleepStatus (
CSL_PwrdwnHandle hPwr,
CSL_PwrdwnPortData *response
)
{
volatile Uint8 data;
data = CSL_FEXT(hPwr->l2pwrdwnRegs->L2PDSTAT[response->portNum],
L2PWRDWN_L2PDSTAT_P1);
response->data = data;
}
#ifdef __cplusplus
extern "C" {
#endif
/**
@}
*/
#endif /* _CSL_PWRDWNAUX_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/i2c/csl_i2cRead.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_i2cRead.c
*
* @brief File for functional layer of CSL API @a CSL_i2cRead()
*
* @path $(CSLPATH)\i2c\src
*
* Description
* - The @a CSL_i2cRead() function definition & it's associated functions
*
* Modification 1
* - Created on: 28/5/2004
* - Reason: created the sources
*
* @date 28th May, 2004
* @author <NAME>.
*/
#include <csl_i2c.h>
/** ============================================================================
* @n@b CSL_i2cRead
*
* @b Description
* @n This function reads I2C data.
*
* @b Arguments
* @verbatim
hI2c Handle to I2C instance
buf Buffer to store the data read
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Operation Successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n Both @a CSL_i2cInit() and @a CSL_i2cOpen() must be called successfully
* in that order before @a CSL_i2cRead() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
Uint16 outData;
CSL_Status status;
CSL_I2cHandle hI2c;
...
// I2C object defined and HwSetup structure defined and initialized
...
// Init, Open, HwSetup successfully done in that order
...
status = CSL_i2cRead (hI2c, &outData);
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_i2cRead, ".text:csl_section:i2c");
CSL_Status CSL_i2cRead (
CSL_I2cHandle hI2c,
void *buf
)
{
CSL_Status status = CSL_SOK;
if (hI2c == NULL) {
return CSL_ESYS_BADHANDLE;
}
else if (buf == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
*(Uint8 *)buf = CSL_FEXT(hI2c->regs->ICDRR,I2C_ICDRR_D);
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/ddr2/csl_ddr2Close.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_ddr2Close.c
*
* @path $(CSLPATH)\src\ddr2
*
* @desc File for functional layer of CSL API @a CSL_ddr2Close()
* - The @a CSL_ddr2Close() function definition & it's associated
* functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 11-Apr-2005 RM File Created.
*
* 05-Oct-2005 NG Updation done according to new register layer
*
* =============================================================================
*/
#include <csl_ddr2.h>
/** ============================================================================
* @n@b csl_ddr2Close.c
*
* @b Description
* @n This function marks that CSL for the external memory interface instance
* is CSL for the external memory interface instance need to be reopened
* before external memory interface CSL API.
*
* @b Arguments
* @verbatim
hDdr2 Pointer to the object that holds reference to the
instance of DDR2 requested after the call
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - external memory interface is
* close successfully
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called
* successfully in that order before @a CSL_ddr2Close() can be called.
*
* <b> Post Condition </b>
* @n 1. The external memory interface CSL APIs can not be called until the
* external memory interface CSL is reopened again using CSL_ddr2Open()
*
* @b Modifies
* @n hDdr2 structure
*
* @b Example
* @verbatim
CSL_Ddr2Handle hDdr2;
...
CSL_ddr2Close (hDdr2);
...
@endverbatim
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_ddr2Close, ".text:csl_section:ddr2");
CSL_Status CSL_ddr2Close (
CSL_Ddr2Handle hDdr2
)
{
CSL_Status status = CSL_SOK;
if (hDdr2 != NULL) {
hDdr2->regs = (CSL_Ddr2RegsOvly)NULL;
hDdr2->perNum = (CSL_InstNum)-1;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/emifa/csl_emifaHwControl.c
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_emifaHwControl.c
*
* @path $(CSLPATH)\src\emifa
*
* $desc File for functional layer of CSL API @a CSL_emifaHwControl()
* - The @a CSL_emifaHwControl() function definition & it's associated
* functions
*
*/
/* =============================================================================
* Revision History
* ===============
* 12-May-2005 RM File Created.
*
* 09-Sep-2005 NG Updation according to coding guidelines
*
* =============================================================================
*/
#include <csl_emifa.h>
#include <csl_emifaAux.h>
/** ============================================================================
* @n@b CSL_emifaHwControl
*
* @b Description
* @n Control operations for the EMIFA. For a particular control operation, the
* pointer to the corresponding data type needs to be passed as argument
* HwControl function Call. All the arguments (structure elements included)
* passed to the HwControl function are inputs. For the list of commands
* supported and argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_EmifaHwControlCmd.
*
* @b Arguments
* @verbatim
hEmifa Pointer to the object that holds reference to the
instance of EMIFA requested after the call
cmd The command to this API indicates the action to be
taken
arg An optional argument @a void* casted
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware control call is
* successful
* @li CSL_ESYS_INVCMD - command is not valid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* @n Both @a CSL_emifaInit() and @a CSL_emifaOpen() must be called
* successfully in order before calling @a CSL_emifaHwControl().
* For the argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_EmifaHwControlCmd
*
* <b> Post Condition </b>
* @n EMIFA registers are configured according to the command passed
*
* @b Modifies
* @n EMIFA registers
*
* @b Example:
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_Status status;
Uint8 * command;
...
status = CSL_emifaHwControl(hEmifa,
CSL_EMIFA_CMD_PRIO_RAISE,
&command);
@endverbatim
*
* =============================================================================
*/
#pragma CODE_SECTION (CSL_emifaHwControl, ".text:csl_section:emifa");
CSL_Status CSL_emifaHwControl (
CSL_EmifaHandle hEmifa,
CSL_EmifaHwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK;
if(hEmifa == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if ((cmd == CSL_EMIFA_CMD_PRIO_RAISE) && (arg == NULL)) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch(cmd) {
case CSL_EMIFA_CMD_ASYNC_TIMEOUT_CLEAR:
CSL_emifaAsyncClear (hEmifa);
break;
case CSL_EMIFA_CMD_ASYNC_TIMEOUT_DISABLE:
CSL_emifaAsyncDisable (hEmifa);
break;
case CSL_EMIFA_CMD_ASYNC_TIMEOUT_ENABLE:
CSL_emifaAsyncEnable (hEmifa);
break;
case CSL_EMIFA_CMD_PRIO_RAISE:
CSL_emifaPrioRaise (hEmifa,(*(Uint8*)arg));
break;
default:
status = CSL_ESYS_INVCMD ;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3ChannelOpen.c
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3ChannelOpen.c
*
* @path $(CSLPATH)\src\edma
*
* @desc EDMA3 CSL Implementation on DSP side
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
* 08-Feb-2006 ds Added error checking
* =============================================================================
*/
#include <csl_edma3.h>
/** ============================================================================
* @n@b CSL_edma3ChannelOpen
*
* @b Description
* @n The API returns a handle for the specified EDMA Channel for use. The
* channel can be re-opened anytime after it has been normally closed if so
* required. The handle returned by this call is input as an essential
* argument for many of the APIs described for this module.
*
* @b Arguments
* @verbatim
pEdmaObj pointer to the object that holds reference to the
channel instance of the Specified DMA
edmaNum Instance of EDMA whose channel is requested
pChAttr Instance of Channel requested
status Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_Edma3ChannelHandle
* @n The requested channel instance of the EDMA
* if the call is successful,else a NULL is returned
*
* <b> Pre Condition </b>
* @n CSL_edma3Init(), CSL_edma3Open() must be invoked successfully in that
* order before this API can be invoked
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid channel handle is returned
* @li CSL_ESYS_FAIL The Edma instance or channel is invalid
* @li CSL_ESYS_INVPARAMS The Parameter passed is invalid
*
* 2. Edma channel object structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Edma channel object structure
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelObj chObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] =
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// DRAE Enable(Bits 0-15) for the Shadow Region 0.
regionAccess.region = CSL_EDMA3_REGION_0 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj,
CSL_EDMA3,
&chAttr,
&status);
// Setup a Parameter Entry
...
// Manually trigger the Channel
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
// Close Channel
CSL_edma3ChannelClose(hChannel);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3ChannelOpen, ".text:csl_section:edma3");
CSL_Edma3ChannelHandle CSL_edma3ChannelOpen (
CSL_Edma3ChannelObj *pEdmaObj,
CSL_InstNum edmaNum,
CSL_Edma3ChannelAttr *pChAttr,
CSL_Status *pStatus
)
{
CSL_Edma3ChannelHandle hEdma = (CSL_Edma3ChannelHandle)NULL;
CSL_Edma3ModuleBaseAddress baseAddress;
if (pStatus == NULL) {
/* Do nothing : Module handle already initialised to NULL */
}
else if (pEdmaObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
if (pChAttr != NULL) {
*pStatus = CSL_edma3ccGetModuleBaseAddr(edmaNum, NULL, &baseAddress);
if (*pStatus == CSL_SOK) {
pEdmaObj->regs = baseAddress.regs;
pEdmaObj->edmaNum = edmaNum;
pEdmaObj->chaNum = pChAttr->chaNum;
pEdmaObj->region = pChAttr->regionNum;
hEdma = (CSL_Edma3ChannelHandle)pEdmaObj;
}
else {
pEdmaObj->regs = (CSL_Edma3ccRegsOvly)NULL;
pEdmaObj->edmaNum = (CSL_InstNum) -1;
pEdmaObj->chaNum = -1;
pEdmaObj->region = -2;
}
}
else {
*pStatus = CSL_ESYS_INVPARAMS;
}
}
return (hEdma);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/_csl_mcbsp.h
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file _csl_mcbsp.h
*
* @path $(CSLPATH)\inc
*
* @desc Header file for private functional layer of McBSP CSL
*
*/
#ifndef __CSL_MCBSP_H_
#define __CSL_MCBSP_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <csl_mcbsp.h>
/******************************************************************************\
* MCBSP Private function declarations
\******************************************************************************/
/*
* =============================================================================
* @func _csl_mcbspBlockAssign
*
* @desc
* The funtion is used to assign block to a particular partition This is an
* Internal function and is used by the CSL_mcbspHwControl function
*
* @arg hMcbsp
* Handle of the McBSP
*
* @arg partition
* Partition to which the block is to be assigned to
*
* @arg block
* Identifies the block
*
* @ret CSL_Status
* CSL_SOK - Successful completion
* CSL_ESYS_FAIL - Operation could not the done
*
* @eg
* CSL_McbspHandle hMcbsp;
_CSL_mcbspBlockAssign(hMcbsp, CSL_MCBSP_PARTITION_ATX,
CSL_MCBSP_BLOCK0);
...
*
* =============================================================================
*/
CSL_Status _CSL_mcbspBlockAssign (
CSL_McbspHandle hMcbsp,
CSL_McbspPartition partition,
CSL_McbspBlock block
);
/*
* =============================================================================
* @func _csl_mcbspChannelControl.c
*
* @desc Eanble one Channel in Multi Channel Selection Mode
*
*
* @arg hMcbsp
* Device Handle;
*
* @arg channelNo
* Channel Number
*
* @arg block
* Block to which the channel belongs to
*
* @arg operation
* The operation to be performed
*
* @ret CSL_Status
* CSL_SOK - Successful completion
* CSL_EMCBSP_INVPARAMS - Invalid Parameter
* CSL_EMCBSP_INVMODE - Invalid Mode
*
* @eg
* MCBSP_Handle hMcbsp;
* hMcbsp = CSL_mcbspOpen(hMcbsp, CSL_MCBSP_1, NULL, &status);
* _CSL_mcbspChannelControl( hMcbsp, 11, 1, CSL_MCBSP_CHAN_RX_ENABLE);
*
*
* =============================================================================
*/
CSL_Status _CSL_mcbspChannelControl (
CSL_McbspHandle hMcbsp,
Uint16 channelNo,
CSL_McbspBlock block,
CSL_McbspChCtrl operation
);
/*
* =============================================================================
* @func _csl_mcbspClearFrmSyncErr.c
*
* @desc Clear Frame Sync Error for Receiver and Transmitter.
*
* @arg hMcbsp
* Device Handle;
*
* @arg chanType
* Selects receiver/transmitter.
*
* @ret void
* None
*
* @eg
* CSL_McbspHandle hMcbsp;
* hMcbsp = CSL_mcbspOpen(hMcbsp, CSL_MCBSP_1,NULL, &status );
* _CSL_mcbspClearFrmSyncErr( hMcbsp, CSL_MCBSP_RX);
*
*
* =============================================================================
*/
void _CSL_mcbspClearFrmSyncErr (
CSL_McbspHandle hMcbsp,
CSL_McbspChType chanType
);
/*
* =============================================================================
* @func _csl_mcbspResetCtrl.c
*
* @desc Enable/Disable Frame Sync Logic/Sample Rate Generator and Receiver
* and Transmitter Operation
*
* @arg hMcbsp
* Device Handle
*
* @arg selectMask
* Selects enable/disable of receiverCfg/transmitter. Bitwise OR
* of MCBSP_CTRL_XXXX
*
* @ret void
* None
*
* @eg
* CSL_McbspHandle hMcbsp;
* hMcbsp = CSL_mcbspOpen(hMcbsp, CSL_MCBSP_1,NULL, &status );
* _CSL_mcbspResetCtrl (hMcbsp, CSL_MCBSP_CTRL_SRG_ENABLE
* |CSL_MCBSP_CTRL_FSYNC_DISABLE
* |CSL_MCBSP_CTRL_RX_ENABLE
* |CSL_MCBSP_CTRL_TX_ENABLE );
*
* =============================================================================
*/
void _CSL_mcbspResetCtrl (
CSL_McbspHandle hMcbsp,
CSL_BitMask16 selectMask
);
/*
* =============================================================================
* @func _csl_mcbspRegReset.c
*
* @desc Function to reset all the registers values
*
*
* @arg hMcbsp
* Device Handle;
*
* @ret void
* None
*
* @eg
* CSL_McbspHandle hMcbsp;
* hMcbsp = CSL_mcbspOpen(hMcbsp, CSL_MCBSP_1,NULL, &status );
* _CSL_mcbspRegReset(hMcbsp);
*
*
* =============================================================================
*/
void _CSL_mcbspRegReset (
CSL_McbspHandle hMcbsp
);
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_bwmngmt.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_bwmngmt.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for BWMNGMT
*/
#ifndef _CSLR_BWMNGMT_H_
#define _CSLR_BWMNGMT_H_
#include <cslr.h>
#include <csl_types.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 CPUARBEXT;
volatile Uint32 IDMAARBEXT;
volatile Uint32 SLAPARBEXT;
volatile Uint32 MAPARBEXT;
volatile Uint8 RSVD0[134640];
volatile Uint32 CPUARBL2;
volatile Uint32 IDMAARBL2;
volatile Uint32 SLAPARBL2;
volatile Uint32 UCARBL2;
volatile Uint8 RSVD1[48];
volatile Uint32 CPUARBL1D;
volatile Uint32 IDMAARBL1D;
volatile Uint32 SLAPARBL1D;
volatile Uint32 UCARBL1D;
} CSL_BwmngmtRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_BwmngmtRegs *CSL_BwmngmtRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* CPUARBL1D */
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_RESETVAL (0x00000010u)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_MASK (0x00070000u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_SHIFT (0x00000010u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_RESETVAL (0x00000001u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_PRI0 (0x00000000u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_PRI1 (0x00000001u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_PRI2 (0x00000002u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_PRI3 (0x00000003u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_PRI4 (0x00000004u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_PRI5 (0x00000005u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_PRI6 (0x00000006u)
#define CSL_BWMNGMT_CPUARBL1D_PRI_PRI7 (0x00000007u)
#define CSL_BWMNGMT_CPUARBL1D_RESETVAL (0x00010010u)
/* CPUARBL2 */
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_RESETVAL (0x00000010u)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_CPUARBL2_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_CPUARBL2_PRI_MASK (0x00070000u)
#define CSL_BWMNGMT_CPUARBL2_PRI_SHIFT (0x00000010u)
#define CSL_BWMNGMT_CPUARBL2_PRI_RESETVAL (0x00000001u)
#define CSL_BWMNGMT_CPUARBL2_PRI_PRI0 (0x00000000u)
#define CSL_BWMNGMT_CPUARBL2_PRI_PRI1 (0x00000001u)
#define CSL_BWMNGMT_CPUARBL2_PRI_PRI2 (0x00000002u)
#define CSL_BWMNGMT_CPUARBL2_PRI_PRI3 (0x00000003u)
#define CSL_BWMNGMT_CPUARBL2_PRI_PRI4 (0x00000004u)
#define CSL_BWMNGMT_CPUARBL2_PRI_PRI5 (0x00000005u)
#define CSL_BWMNGMT_CPUARBL2_PRI_PRI6 (0x00000006u)
#define CSL_BWMNGMT_CPUARBL2_PRI_PRI7 (0x00000007u)
#define CSL_BWMNGMT_CPUARBL2_RESETVAL (0x00010010u)
/* CPUARBEXT */
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_RESETVAL (0x00000010u)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_CPUARBEXT_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_MASK (0x00070000u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_SHIFT (0x00000010u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_RESETVAL (0x00000001u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_PRI0 (0x00000000u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_PRI1 (0x00000001u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_PRI2 (0x00000002u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_PRI3 (0x00000003u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_PRI4 (0x00000004u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_PRI5 (0x00000005u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_PRI6 (0x00000006u)
#define CSL_BWMNGMT_CPUARBEXT_PRI_PRI7 (0x00000007u)
#define CSL_BWMNGMT_CPUARBEXT_RESETVAL (0x00010010u)
/* IDMAARBL1D */
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_RESETVAL (0x00000010u)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_IDMAARBL1D_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_IDMAARBL1D_RESETVAL (0x00000010u)
/* IDMAARBL2 */
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_RESETVAL (0x00000010u)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_IDMAARBL2_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_IDMAARBL2_RESETVAL (0x00000010u)
/* IDMAARBEXT */
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_RESETVAL (0x00000010u)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_IDMAARBEXT_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_IDMAARBEXT_RESETVAL (0x00000010u)
/* SLAPARBL1D */
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_RESETVAL (0x00000001u)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_SLAPARBL1D_RESETVAL (0x00000001u)
/* SLAPARBL2 */
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_RESETVAL (0x00000001u)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_SLAPARBL2_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_SLAPARBL2_RESETVAL (0x00000001u)
/* SLAPARBEXT */
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_RESETVAL (0x00000001u)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_SLAPARBEXT_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_SLAPARBEXT_RESETVAL (0x00000001u)
/* UCARBL1D */
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_RESETVAL (0x00000020u)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_UCARBL1D_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_UCARBL1D_RESETVAL (0x00000020u)
/* UCARBL2 */
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_MASK (0x0000003Fu)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_SHIFT (0x00000000u)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_RESETVAL (0x00000020u)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_MAXWAIT0 (0x00000000u)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_MAXWAIT1 (0x00000001u)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_MAXWAIT2 (0x00000002u)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_MAXWAIT4 (0x00000004u)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_MAXWAIT8 (0x00000008u)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_MAXWAIT16 (0x00000010u)
#define CSL_BWMNGMT_UCARBL2_MAXWAIT_MAXWAIT32 (0x00000020u)
#define CSL_BWMNGMT_UCARBL2_RESETVAL (0x00000020u)
/* MAPARBEXT */
#define CSL_BWMNGMT_MAPARBEXT_PRI_MASK (0x00070000u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_SHIFT (0x00000010u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_RESETVAL (0x00000007u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_PRI0 (0x00000000u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_PRI1 (0x00000001u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_PRI2 (0x00000002u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_PRI3 (0x00000003u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_PRI4 (0x00000004u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_PRI5 (0x00000005u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_PRI6 (0x00000006u)
#define CSL_BWMNGMT_MAPARBEXT_PRI_PRI7 (0x00000007u)
#define CSL_BWMNGMT_MAPARBEXT_RESETVAL (0x00070000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/FB_W2100_SCU_MEA256/typedef.h
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback<gh_stars>0
#ifndef _TYPEDEF_H_
#define _TYPEDEF_H_
#define DAC8555_CHANNELS 4
typedef Uint16 uint16;
typedef Uint32 uint32;
typedef Uint8 uint8;
typedef Int32 int32;
typedef Int16 int16;
typedef Int8 int8;
typedef struct dac_command
{
Uint16 value;
Uint16 command;
} dac_command;
typedef struct dac8555_data
{
dac_command dac[DAC8555_CHANNELS];
} dac8555_data;
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_bwmngmt.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* provided
* ============================================================================
*/
/** ===========================================================================
* @file csl_bwmngmt.h
*
* @brief Header file for functional layer of CSL
*
* @path $(CSLPATH)\bwmngmt\src
*
* Description
* - The different enumerations, structure definitions
* and function declaration
*
* @date 28th May, 2004
* @author <NAME>
* ===========================================================================
*/
/** ===========================================================================
* @mainpage BWMNGMT Module
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to identify a set of common CSL APIs for
* the BWMNGMT Module across various devices. The CSL developer
* is expected to refer to this document while implementing APIs for these
* modules . Some of the listed APIs may not be applicable to a given BWMNGMT
*
*
*
* @subsection aaa Terms and Abbreviations
* -# CSL : Chip Support Library
* -# API : Application Programmer Interface
* -# BWMNGMT : Bandwidth Management Module
*
* @subsection References
* -# CSL 3.x Technical Requirements Specifications Version 0.5, dated
* May 14th, 2003
* -# Bandwidth Management Specification (Revision 0.22)
*
* @subsection Assumptions
* The abbreviations CSL, BWMNGMT have been used throughout this
* document to refer to the C64Plus Bandwidth Management Module.
* ============================================================================
*/
/* =============================================================================
* Revision History
* ===============
* 11-Apr-2005 Brn updated the file for doxygen compatibiliy
*
* 16-Nov-2005 ds updated the documentation
* =============================================================================
*/
#ifndef _CSL_BWMNGMT_H_
#define _CSL_BWMNGMT_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <cslr_bwmngmt.h>
#include <soc.h>
/** Control Block Set for BWMNGMT
* This is used to indicate which control blocks (L1D, L2, and/or EXT) are to
* be set within BWMNGMT for the given requestor (CPU, IDMA, SLAP, MAP, UC)
* arbitration settings.
*/
typedef enum {
/** All controller blocks will be update with given requestors arbitration
* setting
*/
CSL_BWMNGMT_BLOCK_ALL = 7,
/** L1D controller block will be update with given requestors arbitration
* setting
*/
CSL_BWMNGMT_BLOCK_L1D = 1,
/** L2 controller block will be update with given requestors arbitration
* setting
*/
CSL_BWMNGMT_BLOCK_L2 = 2,
/** EXT controller block will be update with given requestors arbitration
* setting
*/
CSL_BWMNGMT_BLOCK_EXT = 4
} CSL_BwmngmtControlBlocks;
/** @brief Priority Settings for BWMNGMT
*
* This is used to indicate to set the Priority arbitration settings for
* the Requestors (CPU, IDMA, SLAP, MAP, UC)
*/
typedef enum {
/** Priority arbitration setting 0 - Highest priority requestor */
CSL_BWMNGMT_PRI_0 = CSL_BWMNGMT_CPUARBL1D_PRI_PRI0,
/** Priority arbitration setting 1 - 2nd Highest priority requestor */
CSL_BWMNGMT_PRI_1 = CSL_BWMNGMT_CPUARBL1D_PRI_PRI1,
/** Priority arbitration setting 2 - 3rd Highest priority requestor */
CSL_BWMNGMT_PRI_2 = CSL_BWMNGMT_CPUARBL1D_PRI_PRI2,
/** Priority arbitration setting 3 - 4th Highest priority requestor */
CSL_BWMNGMT_PRI_3 = CSL_BWMNGMT_CPUARBL1D_PRI_PRI3,
/** Priority arbitration setting 4 - 5th Highest priority requestor */
CSL_BWMNGMT_PRI_4 = CSL_BWMNGMT_CPUARBL1D_PRI_PRI4,
/** Priority arbitration setting 5 - 6th Highest priority requestor */
CSL_BWMNGMT_PRI_5 = CSL_BWMNGMT_CPUARBL1D_PRI_PRI5,
/** Priority arbitration setting 6 - 7th Highest priority requestor */
CSL_BWMNGMT_PRI_6 = CSL_BWMNGMT_CPUARBL1D_PRI_PRI6,
/** Priority arbitration setting 7 - Lowest priority requestor */
CSL_BWMNGMT_PRI_7 = CSL_BWMNGMT_CPUARBL1D_PRI_PRI7,
/** Priority arbitration setting NULL - Due Not Program PRIORITY for this
* requestor
*/
CSL_BWMNGMT_PRI_NULL = -1
} CSL_BwmngmtPriority;
/** @brief Maxwait Settings for BWMNGMT
*
* This is used to indicate to set Maxwait arbitration settings for
* the Requestors (CPU, IDMA, SLAP, MAP, UC)
*/
typedef enum {
/** Maxwait arbitration setting 0 - Always stall due to higher priority
* requestor
*/
CSL_BWMNGMT_MAXWAIT_0 = CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT0,
/** Maxwait arbitration setting 1 - Stall max of 1 cycle due to higher
* priority requestor
*/
CSL_BWMNGMT_MAXWAIT_1 = CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT1,
/** Maxwait arbitration setting 2 - Stall max of 2 cycle due to higher
* priority requestor
*/
CSL_BWMNGMT_MAXWAIT_2 = CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT2,
/** Maxwait arbitration setting 4 - Stall max of 4 cycle due to higher
* priority requestor
*/
CSL_BWMNGMT_MAXWAIT_4 = CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT4,
/** Maxwait arbitration setting 8 - Stall max of 8 cycle due to higher
* priority requestor
*/
CSL_BWMNGMT_MAXWAIT_8 = CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT8,
/** Maxwait arbitration setting 16 - Stall max of 16 cycle due to higher
* priority requestor
*/
CSL_BWMNGMT_MAXWAIT_16 = CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT16,
/** Maxwait arbitration setting 32 - Stall max of 32 cycle due to higher
* priority requestor
*/
CSL_BWMNGMT_MAXWAIT_32 = CSL_BWMNGMT_CPUARBL1D_MAXWAIT_MAXWAIT32,
/** Maxwait arbitration setting NULL - Due Not Program MAXWAIT for this
* requestor
*/
CSL_BWMNGMT_MAXWAIT_NULL = -1
} CSL_BwmngmtMaxwait;
/** Enumaration for Hardware status query */
typedef enum {
PLACEHOLDER0 = 0
} CSL_BwmngmtHwStatusQuery;
/** Enumaration for Hardware control command */
typedef enum {
PLACEHOLDER2 = 0
} CSL_BwmngmtHwControlCmd;
/** @brief CSL_BwmngmtHwSetup has all the fields required to configure BWMNGMT
*
* This structure has the substructures required to configure BWMNGMT at
* Power-Up/Reset.
*
*/
typedef struct {
/** CPU - Requestor Arbitration Settings - PRI */
CSL_BwmngmtPriority cpuPriority;
/** CPU - Requestor Arbitration Settings - MAXWAIT */
CSL_BwmngmtMaxwait cpuMaxwait;
/** IDMA (Internal DMA) Requestor Arbitration Settings - MAXWAIT */
CSL_BwmngmtMaxwait idmaMaxwait;
/** SLAP (Slave Port) Requestor Arbitration Settings - MAXWAIT */
CSL_BwmngmtMaxwait slapMaxwait;
/** MAP (Master Port) Requestor Arbitration Settings - PRI */
CSL_BwmngmtPriority mapPriority;
/** UC (User Coherence) Requestor Arbitration Settings - MAXWAIT */
CSL_BwmngmtMaxwait ucMaxwait;
/** Controller(s) to be set with Requestors Settings
* L1D, L2 and/or EXT
*/
CSL_BwmngmtControlBlocks control;
} CSL_BwmngmtHwSetup;
/*
The following #define CSL_BWMNGMT_HWSETUP_DEFAULTS is meant to simplify the
implementation in C code by the customer.
CSL_BwmngmtHwSetup defaultSetup;
defaultSetup.cpuPriority = CSL_BWMNGMT_CPUARBL1D_PRI_RESETVAL;
defaultSetup.cpuMaxwait = CSL_BWMNGMT_CPUARBL1D_MAXWAIT_RESETVAL;
defaultSetup.idmaMaxwait = CSL_BWMNGMT_IDMAARBL2_MAXWAIT_RESETVAL;
defaultSetup.slapMaxwait = CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_RESETVAL;
defaultSetup.mapPriority = CSL_BWMNGMT_MAPARBEXT_PRI_RESETVAL;
defaultSetup.ucMaxwait = CSL_BWMNGMT_UCARBL1D_MAXWAIT_RESETVAL;
defaultSetup.control = CSL_BWMNGMT_BLOCK_ALL;
*/
/* Default Setup Structure */
/**
* The following #define CSL_BWMNGMT_HWSETUP_DEFAULTS is meant to simplify the
* implementation in C code by the customer
*/
#define CSL_BWMNGMT_HWSETUP_DEFAULTS { \
(CSL_BwmngmtPriority)CSL_BWMNGMT_CPUARBL1D_PRI_RESETVAL, \
(CSL_BwmngmtMaxwait)CSL_BWMNGMT_CPUARBL1D_MAXWAIT_RESETVAL, \
(CSL_BwmngmtMaxwait)CSL_BWMNGMT_IDMAARBL2_MAXWAIT_RESETVAL, \
(CSL_BwmngmtMaxwait)CSL_BWMNGMT_SLAPARBL1D_MAXWAIT_RESETVAL, \
(CSL_BwmngmtPriority)CSL_BWMNGMT_MAPARBEXT_PRI_RESETVAL, \
(CSL_BwmngmtMaxwait)CSL_BWMNGMT_UCARBL1D_MAXWAIT_RESETVAL, \
(CSL_BwmngmtControlBlocks)CSL_BWMNGMT_BLOCK_ALL \
}
/**
* This will have the base-address information for the peripheral instance
*/
typedef struct {
/** Base-address of the Configuration registers of BWMNGMT */
CSL_BwmngmtRegsOvly regs;
} CSL_BwmngmtBaseAddress;
/**
* BWMNGMT specific parameters. Present implementation doesn't have
* any specific parameters.
*/
typedef struct {
/** Bit mask to be used for module specific parameters.
* The below declaration is just a place-holder for future
* implementation.
*/
CSL_BitMask16 flags;
} CSL_BwmngmtParam;
/**
* BWMNGMT specific context information. Present implementation doesn't
* have any Context information.
*/
typedef struct {
/** Context information of BWMNGMT.
* The below declaration is just a place-holder for future
* implementation.
*/
Uint16 contextInfo;
} CSL_BwmngmtContext;
/** @brief This object contains the reference to the instance of BWMNGMT
* opened using the @a CSL_bwmngmtOpen(). The pointer to this object is passed
* as BWMNGMT handle to all BWMNGMT CSL APIs. . CSL_bwmngmtOpen() function
* initializes this structure based on the parameters passed.
*/
typedef struct {
/** This is a pointer to the registers of the instance of BWMNGMT
* referred to by this object */
CSL_BwmngmtRegsOvly regs;
/** This is the instance of BWMNGMT being referred to by this object */
CSL_InstNum bwmngmtNum;
} CSL_BwmngmtObj;
/** @brief this is a pointer to @a CSL_BwmngmtObj & is passed as the first
* parameter to all BWMNGMT CSL APIs
*/
typedef CSL_BwmngmtObj *CSL_BwmngmtHandle;
/** ===========================================================================
* @n@b CSL_bwmngmtOpen
*
* @b Description
* This function populates the peripheral data object for the instance
* and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of BWMNGMT device. The device can be re-opened anytime after it has
* been normally closed if so required. BWMNGMT Hardware setup will be
* performed at the end of the open call only if the HwSetup Pointer
* supplied was non- NULL. The handle returned by this call is input as
* an essential argument for rest of the APIs described for this module.
*
* @b Arguments
* @verbatim
pBwmngmtObj Pointer to the BWMNGMT instance object
bwmngmtNum Instance of the BWMNGMT to be opened.
pBwmngmtParam Pointer to module specific parameters
pStatus pointer for returning status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_BwmngmtHandle
* Valid BWMNGMT instance handle will be returned if status value is
* equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n The CSL system as well as BWMNGMT must be succesfully initialized
* via @a CSL_sysInit() and @a CSL_bwmngmtInit() before calling this
* function. Memory for the @a CSL_BwmngmtObj must be allocated outside
* this call. This object must be retained while usage of this peripheral.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_BwmngmtObj bwmngmtObj;
CSL_BwmngmtHandle hBwmngmt;
...
hBwmngmt = CSL_bwmngmtOpen(&bwmngmtObj, CSL_BWMNGMT_0, NULL, &status);
...
@endverbatim
* ============================================================================
*/
CSL_BwmngmtHandle CSL_bwmngmtOpen (
/* Pointer to the handle object - to be allocated by the user */
CSL_BwmngmtObj *hBwmngmtObj,
/* Specifies the instance of BWMNGMT to be opened */
CSL_InstNum bwmngmtNum,
/* Module specific parameters;
* Currently there are none; the user should pass 'NULL'
*/
CSL_BwmngmtParam *pBwmParam,
/* Pointer to the variable that holds the holds the status of the open
* call
*/
CSL_Status *status
);
/* ===========================================================================
* @n@b CSL_bwmngmtOpen
*
* @b Description
* This function populates the peripheral data object for the instance
* and returns a handle to the BWMNGMT instance.
* The open call sets up the data structures for the particular instance
* of BWMNGMT device. The device can be re-opened anytime after it has
* been normally closed, if so required.The handle returned by this call
* is input as an essential argument for rest of the APIs described for
* this module.
*
* @b Arguments
* @verbatim
pBwmngmtObj Pointer to the BWMNGMT instance object
bwmngmtNum Instance of the BWMNGMT to be opened.
pBwmngmtParam Pointer to module specific parameters
pStatus pointer for returning status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_BwmngmtHandle
* Valid BWMNGMT instance handle will be returned if status value is
* equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n The BWMNGMT module must be successfully initialized via
* CSL_bwmngmtInit() before calling this function.
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status returned is
* CSL_SOK - Valid BWMNGMT handle is returned.
* CSL_ESYS_FAIL - The BWMNGMT instance is invalid.
* 2. BWMNGMT object structure is populated.
*
*
* @b Modifies
* @n 1. The status variable
* 2. BWMNGMT object structure
*
* @b Example
* @verbatim
...
CSL_bwmngmtClose(hBwmngmt);
...
@endverbatim
* ============================================================================
*/
CSL_Status CSL_bwmngmtClose (
/* Pointer to the object that holds reference to the
* instance of BWMNGMT requested after the call
*/
CSL_BwmngmtHandle hBwmngmt
);
/* ============================================================================
* @n@b CSL_bwmngmtHwSetup
*
* @b Description
* @n Configures the BWMNGMT using the values passed in through the
* setup structure.
*
* @b Arguments
* @verbatim
hBwmngmt Handle to the BWMNGMT instance
setup Setup structure for BWMNGMT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* CSL_SOK - Close successful
* CSL_ESYS_BADHANDLE - Invalid handle
* CSL_ESYS_INVPARAMS - If setup is NULL
*
* <b> Pre Condition </b>
* @n Both @a CSL_bwmngmtInit() and @a CSL_bwmngmtOpen() must be called
* successfully in that order before this function can be called. The
* main setup structure consists of fields used for the configuration at
* start up. The user must allocate space for it and fill in the main
* setup structure fields appropriately before a call to this function
* is made. \n
*
* <b> Post Condition </b>
* @n BWMNGMT registers are configured according to the hardware setup
* parameters
*
* @b Modifies
* @n The following registers and fields are programmed by this API \n
* 1. CPU Arbitration Parameters \n
* - PRI field set in L1D, L2 and/or EXT \n
* - MAXWAIT field set in L1D, L2 and/or EXT \n
*
* 2. IDMA Arbitration Parameter \n
* - MAXWAIT field set in L1D, L2 and/or EXT \n
*
* 3. SLAP Arbitration Parameter \n
* - MAXWAIT field set in L1D, L2 and/or EXT \n
*
* 4. MAP Arbitration Parameter \n
* - PRI field set in EXT \n
*
* 5. UC Arbitration Parameter \n
* - MAXWAIT field set in L1D and/or L2 \n
*
* The @b control: bitmask indicates which of the three control blocks
* (L1D, L2 and EXT) will be set with the associated PRI and MAXWAIT values
* Note: That if associated control block is not programmable for given
* requestor then it will not ignored but no error will be provide. This
* allows the user to set control to CSL_BWMNGMT_BLOCK_ALL which is the
* default value. This will set all programmed arbitration values for a given
* requestor to the same value across \n the blocks which is recommended.
* If PRI is set to CSL_BWMNGMT_PRI_NULL (-1) then no change will be made
* for the corresponding requestors priority level.
* If MAXWAIT is set to CSL_BWMNGMT_MAXWAIT_NULL (-1) then no change will be
* made for the corresponding requestors maxwait setting.
* @b Examples:
* @verbatim
Example 1: Sets Priorities and Maxwaits to default values
CSL_BwmngmtHandle hBwmngmt;
CSL_BwmngmtHwSetup hwSetup;
hwSetup = CSL_BWMNGMT_HWSETUP_DEFAULTS;
...
// Init Successfully done
...
// Open Successfully done
...
CSL_bwmngmtHwSetup(hBwmngmt, &hwSetup);
Example 2: Sets CPU Priority to 1, CPU Maxwait to 8, MAP Priority to 6 for
all blocks (L1D, L2 and EXT)
CSL_BwmngmtHandle hBwmngmt;
CSL_BwmngmtHwSetup hwSetup;
hwSetup.cpuPriority = CSL_BWMNGMT_PRI_1;
hwSetup.cpuMaxwait = CSL_BWMNGMT_MAXWAIT_8;
hwSetup.idmaMaxwait = CSL_BWMNGMT_MAXWAIT_NULL;
hwSetup.slapMaxwait = CSL_BWMNGMT_MAXWAIT_NULL;
hwSetup.mapPriority = CSL_BWMNGMT_PRI_6;
hwSetup.ucMaxwait = CSL_BWMNGMT_MAXWAIT_NULL;
hwSetup.control = CSL_BWMNGMT_BLOCK_ALL;
...
// Init Successfully done
...
// Open Successfully done
...
CSL_bwmngmtHwSetup(hBwmngmt, &hwSetup);
@endverbatim
*
* ===========================================================================
*/
CSL_Status CSL_bwmngmtHwSetup (
/* Pointer to the object that holds reference to the
* instance of BWMNGMT requested after the call
*/
CSL_BwmngmtHandle hBwmngmt,
/* Pointer to setup structure which contains the
* information to program BWMNGMT to a useful state
*/
CSL_BwmngmtHwSetup *setup
);
/* ============================================================================
* @n@b CSL_bwmngmtGetHwSetup
*
* @b Description
* @n Gets the current set up of BWMNGMT
*
* @b Arguments
* @verbatim
hBwmngmt Handle to the BWMNGMT instance
setup Setup structure for BWMNGMT
@endverbatim
*
* <b> Return Value </b> CSL_Status
* CSL_SOK - Close successful
* CSL_ESYS_BADHANDLE - Invalid handle
* CSL_ESYS_INVPARAMS - IF setup is NULL
*
* <b> Pre Condition </b>
* @n Both CSL_bwmngmtInit() and CSL_bwmngmtOpen() must be called
* successfully in that order before this function can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n
* 1. CPU Arbitration Parameters
* - PRI field set in Control Block Specified by "control" \n
* - MAXWAIT field set in Control Block Specified by "control" \n
*
* 2. IDMA Arbitration Parameter \n
* - MAXWAIT field set in Control Block Specified by "control" \n
*
* 3. SLAP Arbitration Parameter \n
* - MAXWAIT field set in Control Block Specified by "control" \n
*
* 4. MAP Arbitration Parameter \n
* - PRI field set in Control Block Specified by "control" \n
* if not EXT then returns CSL_BWMNGMT_PRI_NULL \n
*
* 5. UC Arbitration Parameter \n
* - MAXWAIT field set in Control Block Specified by "control" \n
* if not L1D or L2 then returns CSL_BWMNGMT_MAXWAIT_NULL \n
*
* @b Example:
* @verbatim
CSL_BwmngmtHandle hBwmngmt;
CSL_BwmngmtHwSetup hwSetup;
hwSetup.control = CSL_BWMNGMT_BLOCK_L1D;
// only CSL_BWMNGMT_BLOCK_L1D, CSL_BWMNGMT_BLOCK_L2, or
// CSL_BWMNGMT_BLOCK_EXT are valid
...
// Init Successfully done
...
// Open Successfully done
...
CSL_bwmngmtGetHwSetup(hBwmngmt, &hwSetup);
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_bwmngmtGetHwSetup (
/* Pointer to the object that holds reference to the
* instance of BWMNGMT requested after the call
*/
CSL_BwmngmtHandle hBwmngmt,
/* Placeholder to return the status; @a CSL_BwmngmtHwSetup* */
CSL_BwmngmtHwSetup *mySetup
);
/* ============================================================================
* @n@b CSL_bwmngmtHwControl
*
* @b Description
* @n Takes a command of BWMNGMT with an optional argument & implements it.
* Not Implemented. For future use
*
* @b Arguments
* @verbatim
hBwmngmt Handle to the BWMNGMT instance
cmd The command to this API indicates the action to be
taken on BWMNGMT.
arg An optional argument.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Control info return successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The hardware registers of BWMNGMT.
*
* @b Example
* @verbatim
CSL_BwmngmtHandle hBwmngmt;
CSL_BwmngmtHwControlCmd cmd;
void arg;
...
status = CSL_bwmngmtHwControl (hBwmngmt, cmd, &arg);
...
@endverbatim
* =============================================================================
*/
CSL_Status CSL_bwmngmtHwControl (
/* Pointer to the object that holds reference to the
* instance of BWMNGMT requested after the call
*/
CSL_BwmngmtHandle hBwmngmt,
/* The command to this API which indicates the action to be taken */
CSL_BwmngmtHwControlCmd cmd,
/* Optional argument @a void* casted */
void *cmdArg
);
/* ============================================================================
* @n@b CSL_bwmngmtInit
*
* @b Description
* @n This is the initialization function for the BWMNGMT. This function must
* be called before calling any other API from this CSL.This function is
* idem-potent. Currently, the function just returns status CSL_SOK,
* without doing anything.
*
* @b Arguments
@verbatim
pContext Context information for the instance. Should be NULL
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CSL_bwmngmtInit();
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_bwmngmtInit (
/* BWMNGMT Context */
CSL_BwmngmtContext *pContext
);
/* ============================================================================
* @n@b CSL_bwmngmtGetHwStatus
*
* @b Description
* @n Gets the status of the different operations of BWMNGMT. Not Implemented.
* For future use
*
* @b Arguments
* @verbatim
hBwmngmt Handle to the BWMNGMT instance
query The query to this API of BWMNGMT which indicates the
status to be returned.
response Placeholder to return the status.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful
* @li CSL_ESYS_INVQUERY - Invalid query
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_BwmngmtHandle hBwmngmt;
CSL_BwmngmtHwStatusQuery query;
void reponse;
...
status = CSL_GetbwmngmtHwStatus(hBwmngmt, query, &response);
...
@endverbatim
* =============================================================================
*/
CSL_Status CSL_bwmngmtGetHwStatus (
/* Pointer to the object that holds reference to the
* instance of BWMNGMT requested after the call
*/
CSL_BwmngmtHandle hBwmngmt,
/* The query to this API which indicates the status/setup
* to be returned
*/
CSL_BwmngmtHwStatusQuery myQuery,
/* Placeholder to return the status; @a void* casted */
void *response
);
/** ============================================================================
* @n@b CSL_bwmngmtGetBaseAddress
*
* @b Description
* @n Function to get the base address of the peripheral instance.
* This function is used for getting the base address of the peripheral
* instance. This function will be called inside the CSL_bwmngmtOpen()
* function call. This function is open for re-implementing if the user
* wants to modify the base address of the peripheral object to point to
* a different location and there by allow CSL initiated write/reads into
* peripheral. MMR's go to an alternate location.
*
* @b Arguments
* @verbatim
bwmngmtNum Specifies the instance of the bwmngmt to be opened.
pBwmngmtParam Module specific parameters.
pBaseAddress Pointer to baseaddress structure containing base
address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Successful on getting the base
* address of bwmngmt
* @li CSL_ESYS_FAIL The instance number is invalid.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base Address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure is modified.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_BwmngmtBaseAddress baseAddress;
...
status = CSL_bwmngmtGetBaseAddress(CSL_BWMNGMT, NULL, &baseAddress);
@endverbatim
* ===========================================================================
*/
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_emifaAux.h
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_emifaAux.h
*
* @path $(CSLPATH)\inc
*
* @desc Header file for functional layer of CSL
* - The defines inline function definitions
*
*/
/* =============================================================================
* Revision History
* ===============
* 12-May-2005 RM File Created.
*
* 08-Jul-2005 RM Changes made in accordance to the change in cslr_emifa.h
*
* 09-Sep-2005 NG Updation according to coding guidelines
*
* =============================================================================
*/
#ifndef _CSL_EMIFAAUX_H_
#define _CSL_EMIFAAUX_H_
#include <csl_emifa.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Status query functions of the EMIFA EMIF */
/** ============================================================================
* @n@b CSL_emifaGetRevId
*
* @b Description
* @n Gets the current value of Rev ID value of EMIFA external memory
* interface
*
* @b Arguments
* @verbatim
hEmifa Handle to the external memory interface instance
status Revision status structure
* @endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Assigns the current value of the revision status of EMIFA external
* @n memory interface to the rev status structure parameter passed as
* parameter.
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
CSL_EmifaModIdRev *status;
CSL_emifaGetRevId(hEmifa, status);
...
@endverbatim
* ===========================================================================
*/
CSL_IDEF_INLINE
void CSL_emifaGetRevId (
CSL_EmifaHandle hEmifa,
CSL_EmifaModIdRev *status
)
{
status->modId = (Uint16)CSL_FEXT(hEmifa->regs->MIDR, EMIFA_MIDR_MOD_ID);
status->majRev = (Uint8)CSL_FEXT(hEmifa->regs->MIDR, EMIFA_MIDR_MJ_REV);
status->minRev = (Uint8)CSL_FEXT(hEmifa->regs->MIDR, EMIFA_MIDR_MN_REV);
}
/** ============================================================================
* @n@b CSL_emifaGetEndian
*
* @b Description
* @n Gets the the current endian of EMIFA emif from the Status register
*
* @b Arguments
* @verbatim
hEmifa Handle to the external memory interface instance
response holds the edian of EMIFA after function call
* @endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
Uint8 *response;
CSL_emifaGetEndian(hEmifa, response);
...
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
void CSL_emifaGetEndian (
CSL_EmifaHandle hEmifa,
Uint8 *response
)
{
*(response) = (Uint8)CSL_FEXT(hEmifa->regs->STAT, EMIFA_STAT_BE);
}
/** ============================================================================
* @n@b CSL_emifaGetAsyncEnStatus
*
* @b Description
* @n Gets the Async Timeout interrupt enable status in Interrupt Masked Set
* Register and Interrupt Masked Clear Register.
*
* @b Arguments
* @verbatim
hEmifa Handle to the EMIFA external memory interface instance
* @endverbatim
*
* <b> Return Value </b> Uint8
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
Uint8 status;
status = CSL_emifaGetAsyncEnStatus(hEmifa);
...
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
Uint8 CSL_emifaGetAsyncEnStatus (
CSL_EmifaHandle hEmifa
)
{
Uint8 status;
status = ((Uint8) CSL_FEXT(hEmifa->regs->INTMSKCLR,
EMIFA_INTMSKCLR_AT_MASK_CLR)) &
((Uint8) CSL_FEXT(hEmifa->regs->INTMSKSET,
EMIFA_INTMSKSET_AT_MASK_SET)) ;
return status;
}
/** ============================================================================
* @n@b CSL_emifaGetAsyncStatus
*
* @b Description
* @n Gets the Async Timeout interrupt status in Interrupt Raw Register and
* Interrupt Masked register.
*
* @b Arguments
* @verbatim
hEmifa Handle to the EMIFA external memory interface instance
* @endverbatim
*
* <b> Return Value </b> Uint8
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
Uint8 status;
status = CSL_emifaGetAsyncStatus(hEmifa);
...
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
Uint8 CSL_emifaGetAsyncStatus (
CSL_EmifaHandle hEmifa
)
{
Uint8 status;
status = (Uint8) CSL_FEXT(hEmifa->regs->INTRAW, EMIFA_INTRAW_AT) ||
(Uint8) CSL_FEXT(hEmifa->regs->INTMSK, EMIFA_INTMSK_AT_MASKED);
return status;
}
/** Control command functions external memory interface */
/** ============================================================================
* @n@b CSL_emifaAsyncClear
*
* @b Description
* This API clears the Asynchronous Timeout interrupt
*
* @b Arguments
* @verbatim
hEmifa Handle to the EMIFA
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n CSL_emifaInit () and CSL_emifaOpen should be successfully called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Interrupt Raw register and Interrupt Masked Register
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
...
CSL_emifaAsyncClear(hEmifa);
...
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
void CSL_emifaAsyncClear (
CSL_EmifaHandle hEmifa
)
{
CSL_FINST(hEmifa->regs->INTRAW, EMIFA_INTRAW_AT, SET);
}
/** ============================================================================
* @n@b CSL_emifaAsyncDisable
*
* @b Description
* This API disables the Asynchronous Timeout interrupt
*
* @b Arguments
* @verbatim
hEmifa Handle to the EMIFA
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n CSL_emifaInit () and CSL_emifaOpen should be successfully called.
*
* <b> Post Condition </b>
* @n Interrupt doesn't reach the cpu boundary
*
* @b Modifies
* @n Interrupt Mask Clear register and Interrupt Mask Set register
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
...
CSL_emifaAsyncDisable(hEmifa);
...
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
void CSL_emifaAsyncDisable (
CSL_EmifaHandle hEmifa
)
{
CSL_FINST(hEmifa->regs->INTMSKCLR, EMIFA_INTMSKCLR_AT_MASK_CLR, SET);
}
/** ============================================================================
* @n@b CSL_emifaAsyncEnable
*
* @b Description
* This API enables the Asynchronous Timeout interrupt
*
* @b Arguments
* @verbatim
hEmifa Handle to the EMIFA
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n CSL_emifaInit () and CSL_emifaOpen should be successfully called.
*
* <b> Post Condition </b>
* @n Interrupt enabled
*
* @b Modifies
* @n Interrupt Mask Clear register and Interrupt Mask Set register
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
...
CSL_emifaAsyncEnable(hEmifa);
...
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
void CSL_emifaAsyncEnable (
CSL_EmifaHandle hEmifa
)
{
CSL_FINST(hEmifa->regs->INTMSKSET, EMIFA_INTMSKSET_AT_MASK_SET, SET);
}
/** ============================================================================
* @n@b CSL_emifaPrioRaise
*
* @b Description
* This API writes the arg passed into the pr_old_count field of Burst
* Priority register.
*
* @b Arguments
* @verbatim
hEmifa Handle to the EMIFA EMIF
val Value to set to raise the priority value
@endverbatim
*
* <b> Return Value </b>
* None
*
* <b> Pre Condition </b>
* @n CSL_emifaInit () and CSL_emifaOpen should be successfully called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Burst Priority register
*
* @b Example
* @verbatim
CSL_EmifaHandle hEmifa;
void *arg;
(Uint8) *arg = 0x00010;
...
CSL_emifaPrioRaise(hEmifa, arg);
...
@endverbatim
* =============================================================================
*/
CSL_IDEF_INLINE
void CSL_emifaPrioRaise (
CSL_EmifaHandle hEmifa,
Uint8 val
)
{
CSL_FINS(hEmifa->regs->BPRIO, EMIFA_BPRIO_PRIO_RAISE, val);
}
#ifdef __cplusplus
}
#endif
#endif /* _CSL_EMIFAAUX_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_tmr.h
|
<filename>DSP/TI-Header/csl_c6455_src/inc/csl_tmr.h
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ===========================================================================
* @file csl_tmr.h
*
* @brief Header file for functional layer of CSL
*
* @Path $(CSLPATH)\inc
*
* @desc The different enumerations, structure definitions
* and function declarations
* ============================================================================
* @mainpage TIMER
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to identify a set of common CSL APIs for
* the TMR Module across various devices. The CSL developer is expected
* to refer to this document while designing APIs for these modules. Some
* of the listed APIs may not be applicable to a given TMR Module. While
* in other cases this list of APIs may not be sufficient to cover all the
* features of a particular TMR Module. The CSL developer should use his
* discretion in designing new APIs or extending the existing ones to cover
* these.
*
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 20-may-2005 PSK File Created.
* 29-Jul-2005 PSK Updted changes acooriding to revised timer spec. the number
* convention TIM12, TIM34 are changed to TIMLO and TIMHI.
* 01-Feb-2006 ds Updated According to TCI6482/C6455 UserGuide
* (Removed tmrClksrcHi, tmrIpGateHi and tmrInvInpHi fields
* from the hwSetup structure).
* 03-Apr-2006 ds Removed "EMUMGT_CLKSPD" from CSL_TmrConfig structure
* ============================================================================
*/
#ifndef _CSL_TMR_H_
#define _CSL_TMR_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <cslr_tmr.h>
/**
* General purpose global typedef declarations
*/
/**
* @brief This enum describes the commands used to control the GP timer through
* CSL_tmrHwControl()
*/
typedef enum {
/**
* @brief Loads the GP Timer Period Register Low
* @param Uint32 *
*/
CSL_TMR_CMD_LOAD_PRDLO = 0,
/**
* @brief Loads the GP Timer Period Register High
* @param Uint32 *
*/
CSL_TMR_CMD_LOAD_PRDHI = 1,
/**
* @brief Loads the GP Timer Pre-scalar value for TIMHI
* @param Uint8 *
*/
CSL_TMR_CMD_LOAD_PSCHI = 2,
/**
* @brief Enable the GP timer Low
* @param CSL_TmrEnamode
*/
CSL_TMR_CMD_START_TIMLO = 3,
/**
* @brief Enable the GP timer High
* @param CSL_TmrEnamode
*/
CSL_TMR_CMD_START_TIMHI = 4,
/**
* @brief Stop the GP timer Low
* @param None
*/
CSL_TMR_CMD_STOP_TIMLO = 5,
/**
* @brief Stop the GP timer High
* @param None
*/
CSL_TMR_CMD_STOP_TIMHI = 6,
/**
* @brief Reset the GP timer Low
* @param None
*/
CSL_TMR_CMD_RESET_TIMLO = 7,
/**
* @brief Reset the GP timer High
* @param None
*/
CSL_TMR_CMD_RESET_TIMHI = 8,
/**
* @brief Start the timer in GPtimer64 OR Chained mode
* @param None
*/
CSL_TMR_CMD_START64 = 9,
/**
* @brief Stop the timer of GPtimer64 OR Chained
* @param CSL_TmrEnamode
*/
CSL_TMR_CMD_STOP64 = 10,
/**
* @brief Reset the timer of GPtimer64 OR Chained
* @param None
*/
CSL_TMR_CMD_RESET64 = 11,
/**
* @brief Enable the timer in watchdog mode
* @param CSL_TmrEnamode
*/
CSL_TMR_CMD_START_WDT = 12,
/**
* @brief Loads the watchdog key
* @param Uint16
*/
CSL_TMR_CMD_LOAD_WDKEY = 13
} CSL_TmrHwControlCmd;
/**
* @brief This enum describes the commands used to get status of various parameters of the
* GP timer. These values are used in CSL_tmrGetHwStatus()
*/
typedef enum {
/**
* @brief Gets the current value of the GP timer TIMLO register
* @param Uint32 *
*/
CSL_TMR_QUERY_COUNT_LO = 0,
/**
* @brief Gets the current value of the GP timer TIMHI register
* @param Uint32 *
*/
CSL_TMR_QUERY_COUNT_HI = 1,
/**
* @brief This query command returns the status
* about whether the TIMLO is running or stopped
*
* @param CSL_TmrTstat
*/
CSL_TMR_QUERY_TSTAT_LO = 2,
/**
* @brief This query command returns the status
* about whether the TIMHI is running or stopped
*
* @param CSL_TmrTstat
*/
CSL_TMR_QUERY_TSTAT_HI = 3,
/**
* @brief This query command returns the status about whether the timer
* is in watchdog mode or not
* @param CSL_WdflagBitStatus
*/
CSL_TMR_QUERY_WDFLAG_STATUS = 4
} CSL_TmrHwStatusQuery;
/**
* @brief This enum describes whether the Timer Clock input is gated or not gated.
*/
typedef enum {
/** timer input not gated */
CSL_TMR_CLOCK_INP_NOGATE = 0,
/** timer input gated */
CSL_TMR_CLOCK_INP_GATE = 1
} CSL_TmrIpGate;
/**
* @brief This enum describes the Timer Clock source selection.
*/
typedef enum {
/** timer clock INTERNAL source selection */
CSL_TMR_CLKSRC_INTERNAL = 0,
/** timer clock Timer input pin source selection */
CSL_TMR_CLKSRC_TMRINP = 1
} CSL_TmrClksrc;
/**
* @brief This enum describes the enabling/disabling of Timer.
*/
typedef enum {
/** The timer is disabled and maintains current value */
CSL_TMR_ENAMODE_DISABLE = 0,
/** The timer is enabled one time */
CSL_TMR_ENAMODE_ENABLE = 1,
/** The timer is enabled continuously */
CSL_TMR_ENAMODE_CONT = 2
} CSL_TmrEnamode;
/**
* @brief This enum describes the Timer Clock cycles (1/2/3/4).
*/
typedef enum {
/** One timer clock cycle */
CSL_TMR_PWID_ONECLK = 0,
/** Two timer clock cycle */
CSL_TMR_PWID_TWOCLKS = 1,
/** Three timer clock cycle */
CSL_TMR_PWID_THREECLKS = 2,
/** Four timer clock cycle */
CSL_TMR_PWID_FOURCLKS = 3
} CSL_TmrPulseWidth;
/**
* @brief This enum describes the mode of Timer Clock (Pulse/Clock).
*/
typedef enum {
/** Pulse mode */
CSL_TMR_CP_PULSE = 0,
/** Clock mode */
CSL_TMR_CP_CLOCK = 1
} CSL_TmrClockPulse;
/**
* @brief This enum describes the Timer input inverter control
*/
typedef enum {
/** Uninverted timer input drives timer */
CSL_TMR_INVINP_UNINVERTED = 0,
/** Inverted timer input drives timer */
CSL_TMR_INVINP_INVERTED = 1
} CSL_TmrInvInp;
/**
* @brief This enum describes the Timer output inverter control
*/
typedef enum {
/** Uninverted timer output */
CSL_TMR_INVOUTP_UNINVERTED = 0,
/** Inverted timer output */
CSL_TMR_INVOUTP_INVERTED = 1
} CSL_TmrInvOutp;
/**
* @brief This enum describes the mode of Timer (GPT/WDT/Chained/Unchained).
*/
typedef enum {
/** The timer is in 64-bit GP timer mode */
CSL_TMR_TIMMODE_GPT = 0,
/** The timer is in dual 32-bit timer, unchained mode */
CSL_TMR_TIMMODE_DUAL_UNCHAINED = 1,
/** The timer is in 64-bit Watchdog timer mode */
CSL_TMR_TIMMODE_WDT = 2,
/** The timer is in dual 32-bit timer, chained mode */
CSL_TMR_TIMMODE_DUAL_CHAINED = 3
} CSL_TmrMode;
/**
* @brief This enum describes the reset condition of Timer (ON/OFF).
*/
typedef enum {
/** timer TIMxx is in reset */
CSL_TMR_TIMxxRS_RESET_ON = 0,
/** timer TIMHI is not in reset. TIMHI can be used as a 32-bit timer */
CSL_TMR_TIMxxRS_RESET_OFF = 1
} CSL_TmrState;
/** @brief This enum describes the status of Timer.
*/
typedef enum {
/** Timer status drives High */
CSL_TMR_TSTAT_HIGH = 1,
/** Timer status drives Low */
CSL_TMR_TSTAT_LOW = 0
} CSL_TmrTstat;
/** @brief This enmeration describes the flag bit status of the timer in watchdog mode
*/
typedef enum {
/** No watchdog timeout occured */
CSL_TMR_WDFLAG_NOTIMEOUT = 0,
/** Watchdog timeout occured */
CSL_TMR_WDFLAG_TIMEOUT = 1
} CSL_TmrWdflagBitStatus;
/**
* @brief Hardware setup structure.
*/
typedef struct {
/** 32 bit load value to be loaded to Timer Period Register low */
Uint32 tmrTimerPeriodLo;
/** 32 bit load value to be loaded to Timer Period Register High */
Uint32 tmrTimerPeriodHi;
/** 32 bit load value to be loaded to Timer Counter Register Low */
Uint32 tmrTimerCounterLo;
/** 32 bit load value to be loaded to Timer Counter Register High */
Uint32 tmrTimerCounterHi;
/** Pulse width. used in pulse mode (C/P_=0) by the timer */
CSL_TmrPulseWidth tmrPulseWidthHi;
/** Clock/Pulse mode for timerHigh output */
CSL_TmrClockPulse tmrClockPulseHi;
/** Timer output inverter control */
CSL_TmrInvOutp tmrInvOutpHi;
/** TIEN determines if the timer clock is gated by the timer input.
* Applicable only when CLKSRC=0
*/
CSL_TmrIpGate tmrIpGateLo;
/** CLKSRC determines the selected clock source for the timer */
CSL_TmrClksrc tmrClksrcLo;
/** Pulse width. used in pulse mode (C/P_=0) by the timer */
CSL_TmrPulseWidth tmrPulseWidthLo;
/** Clock/Pulse mode for timerLow output */
CSL_TmrClockPulse tmrClockPulseLo;
/** Timer input inverter control. Only affects operation
* if CLKSRC=1, Timer Input pin
*/
CSL_TmrInvInp tmrInvInpLo;
/** Timer output inverter control */
CSL_TmrInvOutp tmrInvOutpLo;
/** TIMHI pre-scalar counter specifies the count for TIMHI */
Uint8 tmrPreScalarCounterHi;
/** Configures the GP timer in GP mode or in
* general purpose timer mode or Dual 32 bit timer mode
*/
CSL_TmrMode tmrTimerMode;
} CSL_TmrHwSetup;
/**
* @brief Config-structure Used to configure the GP timer using CSL_tmrHwSetupRaw()
*/
typedef struct {
/** Timer Counter Register Low */
Uint32 TIMLO;
/** Timer Counter Register High */
Uint32 TIMHI;
/** Timer Period Register Low */
Uint32 PRDLO;
/** Timer Period Register High */
Uint32 PRDHI;
/** Timer Control Register */
Uint32 TCR;
/** Timer Global Control Register */
Uint32 TGCR;
/** Watchdog Timer Control Register */
Uint32 WDTCR;
} CSL_TmrConfig;
/**
* @brief Module specific context information. Present implementation of
* Timer CSL doesn't have any context information.
*/
typedef struct {
/** Context information of Timer CSL.
* The below declaration is just a place-holder for future implementation.
*/
Uint16 contextInfo;
} CSL_TmrContext;
/** @brief Module specific parameters. Present implementation of Timer CSL
* doesn't have any module specific parameters.
*/
typedef struct {
/** Bit mask to be used for module specific parameters. The below
* declaration is just a place-holder for future implementation.
*/
CSL_BitMask16 flags;
} CSL_TmrParam;
/** @brief This structure contains the base-address information for the
* peripheral instance
*/
typedef struct {
/** Base-address of the configuration registers of the peripheral
*/
CSL_TmrRegsOvly regs;
} CSL_TmrBaseAddress;
/**
* @brief Timer object structure.
*/
typedef struct {
/** Pointer to the register overlay structure of the Timer */
CSL_TmrRegsOvly regs;
/** Instance of timer being referred by this object */
CSL_InstNum perNum;
} CSL_TmrObj;
/** @brief Default hardware setup parameters */
#define CSL_TMR_HWSETUP_DEFAULTS { \
CSL_TMR_PRDLO_RESETVAL, \
CSL_TMR_PRDHI_RESETVAL, \
CSL_TMR_TIMLO_RESETVAL, \
CSL_TMR_TIMHI_RESETVAL, \
(CSL_TmrPulseWidth)CSL_TMR_TCR_PWID_HI_RESETVAL, \
(CSL_TmrClockPulse)CSL_TMR_TCR_CP_HI_RESETVAL, \
(CSL_TmrInvOutp)CSL_TMR_TCR_INVOUTP_HI_RESETVAL, \
(CSL_TmrIpGate)CSL_TMR_TCR_TIEN_LO_RESETVAL, \
(CSL_TmrClksrc)CSL_TMR_TCR_CLKSRC_LO_RESETVAL, \
(CSL_TmrPulseWidth)CSL_TMR_TCR_PWID_LO_RESETVAL, \
(CSL_TmrClockPulse)CSL_TMR_TCR_CP_LO_RESETVAL, \
(CSL_TmrInvInp)CSL_TMR_TCR_INVINP_LO_RESETVAL, \
(CSL_TmrInvOutp)CSL_TMR_TCR_INVOUTP_LO_RESETVAL, \
CSL_TMR_TGCR_PSCHI_RESETVAL, \
(CSL_TmrMode)CSL_TMR_TGCR_TIMMODE_RESETVAL \
}
/** @brief Default values for config structure */
#define CSL_TMR_CONFIG_DEFAULTS { \
CSL_TMR_TIMLO_RESETVAL, \
CSL_TMR_TIMHI_RESETVAL, \
CSL_TMR_PRDLO_RESETVAL, \
CSL_TMR_PRDHI_RESETVAL, \
CSL_TMR_TCR_RESETVAL, \
CSL_TMR_TGCR_RESETVAL, \
CSL_TMR_WDTCR_RESETVAL \
}
/**
* @brief This data type is used to return the handle to the CSL of the GP timer
*/
typedef CSL_TmrObj *CSL_TmrHandle;
/*******************************************************************************
* Timer global function declarations
******************************************************************************/
/** ============================================================================
* @n@b CSL_tmrInit
*
* @b Description
* @n This is the initialization function for the General purpose timer CSL.
* The function must be called before calling any other API from this CSL.
* This function is idem-potent. Currently, the function just return
* status CSL_SOK, without doing anything.
*
* @b Arguments
* @verbatim
pContext Pointer to module-context. As General purpose timer doesn't
have any context based information user is expected to pass
NULL.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The CSL for gptimer is initialized
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_tmrInit();
@endverbatim
* =============================================================================
*/
CSL_Status CSL_tmrInit (
CSL_TmrContext *pContext
);
/** ============================================================================
* @n@b CSL_tmrOpen
*
* @b Description
* @n This function populates the peripheral data object for the TIMER instance
* and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of TIMER device. The device can be re-opened anytime after it has been
* normally closed if so required. The handle returned by this call is
* input as an essential argument for rest of the APIs described
* for this module.
*
* @b Arguments
* @verbatim
tmrObj Pointer to gptimer object.
tmrNum Instance of gptimer CSL to be opened.
There are three instance of the gptimer
available. So, the value for this parameter will be
based on the instance.
pTmrParam Module specific parameters.
status Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_TmrHandle
* @n Valid gptimer handle will be returned if
* status value is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK Valid gptimer handle is returned
* @li CSL_ESYS_FAIL The gptimer instance is invalid
* @li CSL_ESYS_INVPARAMS The object structure is not
* properly initialized
*
* 2. Gptimer object structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Gptimer object structure
*
* @b Example
* @verbatim
CSL_status status;
CSL_TmrObj tmrObj;
CSL_TmrHandle hTmr;
hTmr = CSL_tmrOpen(&tmrObj, CSL_TMR_1, NULL, &status);
...
@endverbatim
* =============================================================================
*/
CSL_TmrHandle CSL_tmrOpen (
CSL_TmrObj *tmrObj,
CSL_InstNum tmrNum,
CSL_TmrParam *pTmrParam,
CSL_Status *status
);
/** ============================================================================
* @n@b CSL_tmrGetBaseAddress
*
* @b Description
* @n This function gets the base address of the given gptimer
* instance.
*
* @b Arguments
* @verbatim
tmrNum Specifies the instance of the gptimer to be opened
pTmrParam Gptimer module specific parameters
pBaseAddress Pointer to base address structure containing base
address details
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Open call is successful
* @li CSL_ESYS_FAIL gptimer instance is not
* available.
* @li CSL_ESYS_INVPARAMS Invalid Parameters
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure is modified.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_TmrBaseAddress baseAddress;
...
status = CSL_tmrGetBaseAddress(CSL_TMR_1, NULL, &baseAddress);
...
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_tmrGetBaseAddress (
CSL_InstNum tmrNum,
CSL_TmrParam *pTmrParam,
CSL_TmrBaseAddress *pBaseAddress
);
/** ============================================================================
* @n@b CSL_tmrClose
*
* @b Description
* @n This function marks that CSL for the GP timer instance is closed.
* CSL for the GP timer instance need to be reopened before using any
* GP timer CSL API.
*
* @b Arguments
* @verbatim
hTmr Handle to the GP timer instance
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - GP timer is closed
* successfully
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n 1. The GP timer CSL APIs can not be called until the GP timer
* CSL is reopened again using CSL_tmrOpen()
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_tmrClose(hTmr);
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_tmrClose (
CSL_TmrHandle hTmr
);
/** ============================================================================
* @n@b CSL_tmrHwSetup
*
* @b Description
* @n It configures the timer instance registers as per the values passed
* in the hardware setup structure.
*
* @b Arguments
* @verbatim
htmr Handle to the timer instance
setup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Hardware structure is not
* properly initialized
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The specified instance will be setup according to value passed
*
* @b Modifies
* @n Hardware registers for the specified instance
*
* @b Example
* @verbatim
CSL_status status;
CSL_tmrHwSetup hwSetup;
status = CSL_tmrHwSetup(htmr, &hwSetup);
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_tmrHwSetup (
CSL_TmrHandle hTmr,
CSL_TmrHwSetup *hwSetup
);
/** ============================================================================
* @n@b CSL_tmrHwControl
*
* @b Description
* @n This function performs various control operations on the timer instance,
* based on the command passed.
*
* @b Arguments
* @verbatim
hTmr Handle to the timer instance
cmd Operation to be performed on the timer
cmdArg Arguement specific to the command
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Command execution successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_ESYS_INVPARAMS - Invalid Parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Registers of the timer instance are configured according to the command
* and the command arguments. The command determines which registers are
* modified.
*
* @b Modifies
* @n Registers determined by the command
*
* @b Example
* @verbatim
CSL_Status status;
status = CSL_tmrHwControl(hTmr, CSL_TMR_CMD_START_TIMLO, NULL);
@endverbatim
* ============================================================================
*/
CSL_Status CSL_tmrHwControl(
CSL_TmrHandle hTmr,
CSL_TmrHwControlCmd cmd,
void *cmdArg
);
/** ===========================================================================
* @n@b CSL_tmrGetHwStatus
*
* @b Description
* @n This function is used to get the value of various parameters of the
* timer instance. The value returned depends on the query passed.
*
* @b Arguments
* @verbatim
hTmr Handle to the timer instance
query Query to be performed
response Pointer to buffer to return the data requested by
the query passed
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Successful completion of the
* query
*
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* @li CSL_ESYS_INVQUERY - Query command not supported
*
* @li CSL_ESYS_INVPARAMS - Invalid Parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* Data requested by the query is returned through the variable "response"
*
* @b Modifies
* @n The input arguement "response" is modified
*
* @b Example
* @verbatim
CSL_status status;
Uint8 response;
status = CSL_tmrGetHwStatus(hGptimer, CSL_TMR_QUERY_COUNT_LO,
&response);
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_tmrGetHwStatus (
CSL_TmrHandle hTmr,
CSL_TmrHwStatusQuery query,
void *response
);
/** ============================================================================
* @n@b CSL_tmrHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the config data structure.
*
* @b Arguments
* @verbatim
hTmr Pointer to the object that holds reference to the
instance of TIMER requested after the call
config Pointer to the config structure containing the
device register values
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration structure
* pointer is not properly
* initialized
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The registers of the specified General purpose timer instance will be setup
* according to the values passed through the config structure
*
* @b Modifies
* @n Hardware registers of the specified General purpose timer instance
*
* @b Example
* @verbatim
CSL_TmrHandle hTmr;
CSL_TmrConfig config = CSL_TMR_CONFIG_DEFAULTS;
CSL_Status status;
status = CSL_tmrHwSetupRaw (hTmr, &config);
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_tmrHwSetupRaw (
CSL_TmrHandle hTmr,
CSL_TmrConfig *config
);
/** ============================================================================
* @n@b CSL_tmrGetHwSetup
*
* @b Description
* @n It retrives the hardware setup parameters
*
* @b Arguments
* @verbatim
hTmr Handle to the timer instance
hwSetup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup retrived
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The hardware set up structure will be populated with values from
* the registers
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_TmrHwSetup hwSetup;
status = CSL_tmrGetHwsetup (hTmr, &hwSetup);
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_tmrGetHwSetup (
CSL_TmrHandle hTmr,
CSL_TmrHwSetup *hwSetup
);
#ifdef __cplusplus
}
#endif
#endif /* _CSL_TMR_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/srio/csl_srioLsuSetup.c
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* =============================================================================
*/
/** ===========================================================================
* @file csl_srioLsuSetup.c
*
* @brief File for functional layer of CSL API CSL_srioLsuSetup()
*
* @path $(CSLPATH)\srio\src
*
* @desc The CSL_srioLsuSetup() function definition & it's associated functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 25-Aug-2005 PSK File Created.
* ============================================================================
*/
#include <csl_srio.h>
/** ============================================================================
* @n@b CSL_srioLsuSetup
*
* @b Description
* @n Function to configure the LSU module for Direct IO transfer
*
* @b Arguments
* @verbatim
hSrio Handle to the SRIO instance
lsuConfig Pointer to the direct IO configuration structure
index index to the LSU block number
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Successfully configured the
LSU module
* @li CSL_ESYS_BADHANDLE - Invalid handle is passed
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The LSU module registers are configured with the passed parameters
* and the data transfer starts.
*
* @b Modifies
* @n LSU module registers
*
* @b Example
* @verbatim
CSL_status status;
CSL_SrioDirectIO_ConfigXfr lsuConfig;
Uint8 index;
index = 1;
lsuConfig.srcNodeAdd = 0x2ffe550;
lsuConfig.priority = 2;
...
Status = CSL_srioLsuSetup(hSrio, &lsuConfig, index);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_srioLsuSetup, ".text:csl_section:srio");
CSL_Status CSL_srioLsuSetup (
CSL_SrioHandle hSrio,
CSL_SrioDirectIO_ConfigXfr *lsuConfig,
Uint8 index
)
{
CSL_Status status = CSL_SOK;
if (hSrio == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (lsuConfig == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
/* Configures LSU control register 0 */
hSrio->regs->LSU[index].LSU_REG0 = lsuConfig->dstNodeAddr.addressHi;
/* Configures LSU control register 1 */
hSrio->regs->LSU[index].LSU_REG1 = lsuConfig->dstNodeAddr.addressLo;
/* Configures LSU control register 2 */
hSrio->regs->LSU[index].LSU_REG2 = lsuConfig->srcNodeAddr;
/* Configures LSU control register 3 */
CSL_FINS(hSrio->regs->LSU[index].LSU_REG3, SRIO_LSU_REG3_BYTE_COUNT,
lsuConfig->byteCnt);
/* Configures LSU control register 4 */
hSrio->regs->LSU[index].LSU_REG4 =
CSL_FMK(SRIO_LSU_REG4_OUTPORTID, lsuConfig->outPortId)|
CSL_FMK(SRIO_LSU_REG4_PRIORITY, lsuConfig->priority)|
CSL_FMK(SRIO_LSU_REG4_XAMBS, lsuConfig->xambs)|
CSL_FMK(SRIO_LSU_REG4_ID_SIZE, lsuConfig->idSize)|
CSL_FMK(SRIO_LSU_REG4_DESTID, lsuConfig->dstId)|
CSL_FMK(SRIO_LSU_REG4_INTERRUPT_REQ, lsuConfig->intrReq);
/* Configures LSU control register 5 */
hSrio->regs->LSU[index].LSU_REG5 =
CSL_FMK(SRIO_LSU_REG5_DRBLL_INFO, lsuConfig->doorbellInfo)|
CSL_FMK(SRIO_LSU_REG5_HOP_COUNT, lsuConfig->hopCount)|
CSL_FMK(SRIO_LSU_REG5_PACKET_TYPE, lsuConfig->pktType);
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_tcp2.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_tcp2.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for TCP2
*/
#ifndef _CSLR_TCP2_H_
#define _CSLR_TCP2_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 PID;
volatile Uint8 RSVD0[72];
volatile Uint32 TCPEXE;
volatile Uint32 TCPEND;
volatile Uint8 RSVD1[12];
volatile Uint32 TCPERR;
volatile Uint8 RSVD2[4];
volatile Uint32 TCPSTAT;
volatile Uint8 RSVD3[4];
volatile Uint32 TCPEMU;
} CSL_Tcp2Regs;
/**************************************************************************\
* Register Overlay Structure for input and output configuration registers
\**************************************************************************/
typedef struct {
volatile Uint32 TCPIC0;
volatile Uint32 TCPIC1;
volatile Uint32 TCPIC2;
volatile Uint32 TCPIC3;
volatile Uint32 TCPIC4;
volatile Uint32 TCPIC5;
volatile Uint32 TCPIC6;
volatile Uint32 TCPIC7;
volatile Uint32 TCPIC8;
volatile Uint32 TCPIC9;
volatile Uint32 TCPIC10;
volatile Uint32 TCPIC11;
volatile Uint32 TCPIC12;
volatile Uint32 TCPIC13;
volatile Uint32 TCPIC14;
volatile Uint32 TCPIC15;
volatile Uint32 TCPOUT0;
volatile Uint32 TCPOUT1;
volatile Uint32 TCPOUT2;
} CSL_Tcp2CfgRegs;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* PID */
#define CSL_TCP2_PID_TYPE_MASK (0x00FF0000u)
#define CSL_TCP2_PID_TYPE_SHIFT (0x00000010u)
#define CSL_TCP2_PID_TYPE_RESETVAL (0x00000002u)
#define CSL_TCP2_PID_CLASS_MASK (0x0000FF00u)
#define CSL_TCP2_PID_CLASS_SHIFT (0x00000008u)
#define CSL_TCP2_PID_CLASS_RESETVAL (0x00000011u)
#define CSL_TCP2_PID_REV_MASK (0x000000FFu)
#define CSL_TCP2_PID_REV_SHIFT (0x00000000u)
#define CSL_TCP2_PID_REV_RESETVAL (0x00000211u)
#define CSL_TCP2_PID_RESETVAL (0x00021311u)
/* TCPEXE */
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_MASK (0x00000007u)
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_SHIFT (0x00000000u)
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_RESETVAL (0x00000000u)
/*----EXECUTION_INSTR Tokens----*/
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_NO (0x00000000u)
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_START (0x00000001u)
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_DEBUG0 (0x00000004u)
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_DEBUG6 (0x00000005u)
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_DEBUG (0x00000006u)
#define CSL_TCP2_TCPEXE_EXECUTION_INSTR_SOFTRESET (0x00000007u)
#define CSL_TCP2_TCPEXE_RESETVAL (0x00000000u)
/* TCPEND */
#define CSL_TCP2_TCPEND_SLPZVSS_EN_MASK (0x00000200u)
#define CSL_TCP2_TCPEND_SLPZVSS_EN_SHIFT (0x00000009u)
#define CSL_TCP2_TCPEND_SLPZVSS_EN_RESETVAL (0x00000001u)
/*----SLPZVSS_EN Tokens----*/
#define CSL_TCP2_TCPEND_SLPZVSS_EN_DISABLE (0x00000000u)
#define CSL_TCP2_TCPEND_SLPZVSS_EN_ENABLE (0x00000001u)
#define CSL_TCP2_TCPEND_SLPZVDD_EN_MASK (0x00000100u)
#define CSL_TCP2_TCPEND_SLPZVDD_EN_SHIFT (0x00000008u)
#define CSL_TCP2_TCPEND_SLPZVDD_EN_RESETVAL (0x00000001u)
/*----SLPZVDD_EN Tokens----*/
#define CSL_TCP2_TCPEND_SLPZVDD_EN_DISABLE (0x00000000u)
#define CSL_TCP2_TCPEND_SLPZVDD_EN_ENABLE (0x00000001u)
#define CSL_TCP2_TCPEND_ENDIAN_EXTR_MASK (0x00000002u)
#define CSL_TCP2_TCPEND_ENDIAN_EXTR_SHIFT (0x00000001u)
#define CSL_TCP2_TCPEND_ENDIAN_EXTR_RESETVAL (0x00000000u)
/*----ENDIAN_EXTR Tokens----*/
#define CSL_TCP2_TCPEND_ENDIAN_EXTR_32BITS (0x00000000u)
#define CSL_TCP2_TCPEND_ENDIAN_EXTR_NATIVE8 (0x00000001u)
#define CSL_TCP2_TCPEND_ENDIAN_INTR_MASK (0x00000001u)
#define CSL_TCP2_TCPEND_ENDIAN_INTR_SHIFT (0x00000000u)
#define CSL_TCP2_TCPEND_ENDIAN_INTR_RESETVAL (0x00000000u)
/*----ENDIAN_INTR Tokens----*/
#define CSL_TCP2_TCPEND_ENDIAN_INTR_32BITS (0x00000000u)
#define CSL_TCP2_TCPEND_ENDIAN_INTR_NATIVE16 (0x00000001u)
#define CSL_TCP2_TCPEND_RESETVAL (0x00000300u)
/* TCPERR */
#define CSL_TCP2_TCPERR_MAXMINITER_MASK (0x00004000u)
#define CSL_TCP2_TCPERR_MAXMINITER_SHIFT (0x0000000Eu)
#define CSL_TCP2_TCPERR_MAXMINITER_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_ACC_MASK (0x00000800u)
#define CSL_TCP2_TCPERR_ACC_SHIFT (0x0000000Bu)
#define CSL_TCP2_TCPERR_ACC_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_OP_MASK (0x00000400u)
#define CSL_TCP2_TCPERR_OP_SHIFT (0x0000000Au)
#define CSL_TCP2_TCPERR_OP_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_INT_MASK (0x00000200u)
#define CSL_TCP2_TCPERR_INT_SHIFT (0x00000009u)
#define CSL_TCP2_TCPERR_INT_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_SNR_MASK (0x00000100u)
#define CSL_TCP2_TCPERR_SNR_SHIFT (0x00000008u)
#define CSL_TCP2_TCPERR_SNR_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_R_MASK (0x00000080u)
#define CSL_TCP2_TCPERR_R_SHIFT (0x00000007u)
#define CSL_TCP2_TCPERR_R_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_SF_MASK (0x00000010u)
#define CSL_TCP2_TCPERR_SF_SHIFT (0x00000004u)
#define CSL_TCP2_TCPERR_SF_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_P_MASK (0x00000004u)
#define CSL_TCP2_TCPERR_P_SHIFT (0x00000002u)
#define CSL_TCP2_TCPERR_P_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_F_MASK (0x00000002u)
#define CSL_TCP2_TCPERR_F_SHIFT (0x00000001u)
#define CSL_TCP2_TCPERR_F_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_ERR_MASK (0x00000001u)
#define CSL_TCP2_TCPERR_ERR_SHIFT (0x00000000u)
#define CSL_TCP2_TCPERR_ERR_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPERR_RESETVAL (0x00000000u)
/* TCPSTAT */
#define CSL_TCP2_TCPSTAT_TCP_STATE_MASK (0x0F000000u)
#define CSL_TCP2_TCPSTAT_TCP_STATE_SHIFT (0x00000018u)
#define CSL_TCP2_TCPSTAT_TCP_STATE_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_CRC_PASS_MASK (0x00800000u)
#define CSL_TCP2_TCPSTAT_CRC_PASS_SHIFT (0x00000017u)
#define CSL_TCP2_TCPSTAT_CRC_PASS_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_SNR_EXCEED_MASK (0x00600000u)
#define CSL_TCP2_TCPSTAT_SNR_EXCEED_SHIFT (0x00000015u)
#define CSL_TCP2_TCPSTAT_SNR_EXCEED_RESETVAL (0x00000000u)
/*----SNR_EXCEED Tokens----*/
#define CSL_TCP2_TCPSTAT_SNR_EXCEED_MAP01_FAIL (0x00000000u)
#define CSL_TCP2_TCPSTAT_SNR_EXCEED_MAP0_PASS (0x00000001u)
#define CSL_TCP2_TCPSTAT_SNR_EXCEED_MAP1_PASS (0x00000002u)
#define CSL_TCP2_TCPSTAT_ACTIVE_ITER_MASK (0x001F0000u)
#define CSL_TCP2_TCPSTAT_ACTIVE_ITER_SHIFT (0x00000010u)
#define CSL_TCP2_TCPSTAT_ACTIVE_ITER_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_ACTIVE_STATE_MASK (0x0000F000u)
#define CSL_TCP2_TCPSTAT_ACTIVE_STATE_SHIFT (0x0000000Cu)
#define CSL_TCP2_TCPSTAT_ACTIVE_STATE_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_ACTIVE_MAP_MASK (0x00000800u)
#define CSL_TCP2_TCPSTAT_ACTIVE_MAP_SHIFT (0x0000000Bu)
#define CSL_TCP2_TCPSTAT_ACTIVE_MAP_RESETVAL (0x00000000u)
/*----ACTIVE_MAP Tokens----*/
#define CSL_TCP2_TCPSTAT_ACTIVE_MAP_MAP0 (0x00000000u)
#define CSL_TCP2_TCPSTAT_ACTIVE_MAP_MAP1 (0x00000001u)
#define CSL_TCP2_TCPSTAT_EMUHALT_MASK (0x00000400u)
#define CSL_TCP2_TCPSTAT_EMUHALT_SHIFT (0x0000000Au)
#define CSL_TCP2_TCPSTAT_EMUHALT_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_ROP_MASK (0x00000200u)
#define CSL_TCP2_TCPSTAT_ROP_SHIFT (0x00000009u)
#define CSL_TCP2_TCPSTAT_ROP_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_RHD_MASK (0x00000100u)
#define CSL_TCP2_TCPSTAT_RHD_SHIFT (0x00000008u)
#define CSL_TCP2_TCPSTAT_RHD_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_REXT_MASK (0x00000080u)
#define CSL_TCP2_TCPSTAT_REXT_SHIFT (0x00000007u)
#define CSL_TCP2_TCPSTAT_REXT_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_WAP_MASK (0x00000040u)
#define CSL_TCP2_TCPSTAT_WAP_SHIFT (0x00000006u)
#define CSL_TCP2_TCPSTAT_WAP_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_WSP_MASK (0x00000020u)
#define CSL_TCP2_TCPSTAT_WSP_SHIFT (0x00000005u)
#define CSL_TCP2_TCPSTAT_WSP_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_WINT_MASK (0x00000010u)
#define CSL_TCP2_TCPSTAT_WINT_SHIFT (0x00000004u)
#define CSL_TCP2_TCPSTAT_WINT_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_WIC_MASK (0x00000008u)
#define CSL_TCP2_TCPSTAT_WIC_SHIFT (0x00000003u)
#define CSL_TCP2_TCPSTAT_WIC_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_ERR_MASK (0x00000004u)
#define CSL_TCP2_TCPSTAT_ERR_SHIFT (0x00000002u)
#define CSL_TCP2_TCPSTAT_ERR_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPSTAT_DEC_BUSY_MASK (0x00000002u)
#define CSL_TCP2_TCPSTAT_DEC_BUSY_SHIFT (0x00000001u)
#define CSL_TCP2_TCPSTAT_DEC_BUSY_RESETVAL (0x00000000u)
/*----DEC_BUSY Tokens----*/
#define CSL_TCP2_TCPSTAT_DEC_BUSY_STATE0 (0x00000000u)
#define CSL_TCP2_TCPSTAT_DEC_BUSY_STATE1_8 (0x00000001u)
#define CSL_TCP2_TCPSTAT_RESETVAL (0x00000000u)
/* TCPEMU */
#define CSL_TCP2_TCPEMU_SOFT_MASK (0x00000002u)
#define CSL_TCP2_TCPEMU_SOFT_SHIFT (0x00000001u)
#define CSL_TCP2_TCPEMU_SOFT_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPEMU_FREE_MASK (0x00000001u)
#define CSL_TCP2_TCPEMU_FREE_SHIFT (0x00000000u)
#define CSL_TCP2_TCPEMU_FREE_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPEMU_RESETVAL (0x00000000u)
/* TCPIC0 */
#define CSL_TCP2_TCPIC0_FL_MASK (0x7FFF0000u)
#define CSL_TCP2_TCPIC0_FL_SHIFT (0x00000010u)
#define CSL_TCP2_TCPIC0_FL_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC0_NUMSW_MASK (0x00004000u)
#define CSL_TCP2_TCPIC0_NUMSW_SHIFT (0x0000000Eu)
#define CSL_TCP2_TCPIC0_NUMSW_RESETVAL (0x00000000u)
/*----NUMSW Tokens----*/
#define CSL_TCP2_TCPIC0_NUMSW_LEQ_128 (0x00000000u)
#define CSL_TCP2_TCPIC0_NUMSW_G_128 (0x00000001u)
#define CSL_TCP2_TCPIC0_OUTF_MASK (0x00002000u)
#define CSL_TCP2_TCPIC0_OUTF_SHIFT (0x0000000Du)
#define CSL_TCP2_TCPIC0_OUTF_RESETVAL (0x00000000u)
/*----OUTF Tokens----*/
#define CSL_TCP2_TCPIC0_OUTF_NO (0x00000000u)
#define CSL_TCP2_TCPIC0_OUTF_YES (0x00000001u)
#define CSL_TCP2_TCPIC0_INTER_MASK (0x00001000u)
#define CSL_TCP2_TCPIC0_INTER_SHIFT (0x0000000Cu)
#define CSL_TCP2_TCPIC0_INTER_RESETVAL (0x00000000u)
/*----INTER Tokens----*/
#define CSL_TCP2_TCPIC0_INTER_NO (0x00000000u)
#define CSL_TCP2_TCPIC0_INTER_YES (0x00000001u)
#define CSL_TCP2_TCPIC0_RATE_MASK (0x00000700u)
#define CSL_TCP2_TCPIC0_RATE_SHIFT (0x00000008u)
#define CSL_TCP2_TCPIC0_RATE_RESETVAL (0x00000000u)
/*----RATE Tokens----*/
#define CSL_TCP2_TCPIC0_RATE_3_4 (0x00000001u)
#define CSL_TCP2_TCPIC0_RATE_1_2 (0x00000002u)
#define CSL_TCP2_TCPIC0_RATE_1_3 (0x00000003u)
#define CSL_TCP2_TCPIC0_RATE_1_4 (0x00000004u)
#define CSL_TCP2_TCPIC0_RATE_1_5 (0x00000005u)
#define CSL_TCP2_TCPIC0_OPMOD_MASK (0x00000006u)
#define CSL_TCP2_TCPIC0_OPMOD_SHIFT (0x00000001u)
#define CSL_TCP2_TCPIC0_OPMOD_RESETVAL (0x00000000u)
/*----OPMOD Tokens----*/
#define CSL_TCP2_TCPIC0_OPMOD_SA (0x00000000u)
#define CSL_TCP2_TCPIC0_OPMOD_SP_FF (0x00000001u)
#define CSL_TCP2_TCPIC0_OPMOD_SP_MF (0x00000002u)
#define CSL_TCP2_TCPIC0_OPMOD_SP_LF (0x00000003u)
#define CSL_TCP2_TCPIC0_RESETVAL (0x00000000u)
/* TCPIC1 */
#define CSL_TCP2_TCPIC1_R_MASK (0x007F0000u)
#define CSL_TCP2_TCPIC1_R_SHIFT (0x00000010u)
#define CSL_TCP2_TCPIC1_R_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC1_RESETVAL (0x00000000u)
/* TCPIC2 */
#define CSL_TCP2_TCPIC2_SNR_MASK (0xFF000000u)
#define CSL_TCP2_TCPIC2_SNR_SHIFT (0x00000018u)
#define CSL_TCP2_TCPIC2_SNR_RESETVAL (0x00000000u)
/*----SNR Tokens----*/
#define CSL_TCP2_TCPIC2_SNR_DISABLE (0x00000000u)
#define CSL_TCP2_TCPIC2_MAXIT_MASK (0x001F0000u)
#define CSL_TCP2_TCPIC2_MAXIT_SHIFT (0x00000010u)
#define CSL_TCP2_TCPIC2_MAXIT_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC2_NSB_MASK (0x00007F00u)
#define CSL_TCP2_TCPIC2_NSB_SHIFT (0x00000008u)
#define CSL_TCP2_TCPIC2_NSB_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC2_P_MASK (0x0000003Fu)
#define CSL_TCP2_TCPIC2_P_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC2_P_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC2_RESETVAL (0x00000000u)
/* TCPIC3 */
#define CSL_TCP2_TCPIC3_OUTORDER_MASK (0x00004000u)
#define CSL_TCP2_TCPIC3_OUTORDER_SHIFT (0x0000000Eu)
#define CSL_TCP2_TCPIC3_OUTORDER_RESETVAL (0x00000000u)
/*----OUTORDER Tokens----*/
#define CSL_TCP2_TCPIC3_OUTORDER_0_31 (0x00000000u)
#define CSL_TCP2_TCPIC3_OUTORDER_31_0 (0x00000001u)
#define CSL_TCP2_TCPIC3_INPUTSIGN_MASK (0x00001000u)
#define CSL_TCP2_TCPIC3_INPUTSIGN_SHIFT (0x0000000Cu)
#define CSL_TCP2_TCPIC3_INPUTSIGN_RESETVAL (0x00000000u)
/*----INPUTSIGN Tokens----*/
#define CSL_TCP2_TCPIC3_INPUTSIGN_POSITIVE (0x00000000u)
#define CSL_TCP2_TCPIC3_INPUTSIGN_NEGATIVE (0x00000001u)
#define CSL_TCP2_TCPIC3_MINITER_MASK (0x000001F0u)
#define CSL_TCP2_TCPIC3_MINITER_SHIFT (0x00000004u)
#define CSL_TCP2_TCPIC3_MINITER_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC3_EPRORED_MASK (0x00000002u)
#define CSL_TCP2_TCPIC3_EPRORED_SHIFT (0x00000001u)
#define CSL_TCP2_TCPIC3_EPRORED_RESETVAL (0x00000000u)
/*----EPRORED Tokens----*/
#define CSL_TCP2_TCPIC3_EPRORED_DISABLE (0x00000000u)
#define CSL_TCP2_TCPIC3_EPRORED_ENABLE (0x00000001u)
#define CSL_TCP2_TCPIC3_EMAXSTR_MASK (0x00000001u)
#define CSL_TCP2_TCPIC3_EMAXSTR_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC3_EMAXSTR_RESETVAL (0x00000000u)
/*----EMAXSTR Tokens----*/
#define CSL_TCP2_TCPIC3_EMAXSTR_DISABLE (0x00000000u)
#define CSL_TCP2_TCPIC3_EMAXSTR_ENABLE (0x00000001u)
#define CSL_TCP2_TCPIC3_RESETVAL (0x00000000u)
/* TCPIC4 */
#define CSL_TCP2_TCPIC4_CRCITERPASS_MASK (0x00001F00u)
#define CSL_TCP2_TCPIC4_CRCITERPASS_SHIFT (0x00000008u)
#define CSL_TCP2_TCPIC4_CRCITERPASS_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC4_CRCLEN_MASK (0x0000003Fu)
#define CSL_TCP2_TCPIC4_CRCLEN_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC4_CRCLEN_RESETVAL (0x00000000u)
/*----CRCLEN Tokens----*/
#define CSL_TCP2_TCPIC4_CRCLEN_DISABLE (0x00000000u)
#define CSL_TCP2_TCPIC4_RESETVAL (0x00000000u)
/* TCPIC5 */
#define CSL_TCP2_TCPIC5_CRCPOLY_MASK (0xFFFFFFFFu)
#define CSL_TCP2_TCPIC5_CRCPOLY_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC5_CRCPOLY_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC5_RESETVAL (0x00000000u)
/* TCPIC6 */
#define CSL_TCP2_TCPIC6_TAIL1_MASK (0x0003FFFFu)
#define CSL_TCP2_TCPIC6_TAIL1_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC6_TAIL1_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC6_RESETVAL (0x00000000u)
/* TCPIC7 */
#define CSL_TCP2_TCPIC7_TAIL2_MASK (0x0003FFFFu)
#define CSL_TCP2_TCPIC7_TAIL2_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC7_TAIL2_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC7_RESETVAL (0x00000000u)
/* TCPIC8 */
#define CSL_TCP2_TCPIC8_TAIL3_MASK (0x0003FFFFu)
#define CSL_TCP2_TCPIC8_TAIL3_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC8_TAIL3_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC8_RESETVAL (0x00000000u)
/* TCPIC9 */
#define CSL_TCP2_TCPIC9_TAIL4_MASK (0x0003FFFFu)
#define CSL_TCP2_TCPIC9_TAIL4_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC9_TAIL4_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC9_RESETVAL (0x00000000u)
/* TCPIC10 */
#define CSL_TCP2_TCPIC10_TAIL5_MASK (0x0003FFFFu)
#define CSL_TCP2_TCPIC10_TAIL5_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC10_TAIL5_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC10_RESETVAL (0x00000000u)
/* TCPIC11 */
#define CSL_TCP2_TCPIC11_TAIL6_MASK (0x0003FFFFu)
#define CSL_TCP2_TCPIC11_TAIL6_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC11_TAIL6_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC11_RESETVAL (0x00000000u)
/* TCPIC12 */
#define CSL_TCP2_TCPIC12_EXT_SCALE_0_3_MASK (0x00FFFFFFu)
#define CSL_TCP2_TCPIC12_EXT_SCALE_0_3_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC12_EXT_SCALE_0_3_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC12_RESETVAL (0x00000000u)
/* TCPIC13 */
#define CSL_TCP2_TCPIC13_EXT_SCALE_4_7_MASK (0x00FFFFFFu)
#define CSL_TCP2_TCPIC13_EXT_SCALE_4_7_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC13_EXT_SCALE_4_7_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC13_RESETVAL (0x00000000u)
/* TCPIC14 */
#define CSL_TCP2_TCPIC14_EXT_SCALE_8_11_MASK (0x00FFFFFFu)
#define CSL_TCP2_TCPIC14_EXT_SCALE_8_11_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC14_EXT_SCALE_8_11_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC14_RESETVAL (0x00000000u)
/* TCPIC15 */
#define CSL_TCP2_TCPIC15_EXT_SCALE_12_15_MASK (0x00FFFFFFu)
#define CSL_TCP2_TCPIC15_EXT_SCALE_12_15_SHIFT (0x00000000u)
#define CSL_TCP2_TCPIC15_EXT_SCALE_12_15_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPIC15_RESETVAL (0x00000000u)
/* TCPOUT0 */
#define CSL_TCP2_TCPOUT0_FINAL_ITER_MASK (0x1F000000u)
#define CSL_TCP2_TCPOUT0_FINAL_ITER_SHIFT (0x00000018u)
#define CSL_TCP2_TCPOUT0_FINAL_ITER_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPOUT0_SNR_M1_MASK (0x000FFFFFu)
#define CSL_TCP2_TCPOUT0_SNR_M1_SHIFT (0x00000000u)
#define CSL_TCP2_TCPOUT0_SNR_M1_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPOUT0_RESETVAL (0x00000000u)
/* TCPOUT1 */
#define CSL_TCP2_TCPOUT1_SNR_EXCEED_MASK (0xC0000000u)
#define CSL_TCP2_TCPOUT1_SNR_EXCEED_SHIFT (0x0000001Eu)
#define CSL_TCP2_TCPOUT1_SNR_EXCEED_RESETVAL (0x00000000u)
/*----SNR_EXCEED Tokens----*/
#define CSL_TCP2_TCPOUT1_SNR_EXCEED_MAP01_FAIL (0x00000000u)
#define CSL_TCP2_TCPOUT1_SNR_EXCEED_MAP0_PASS (0x00000001u)
#define CSL_TCP2_TCPOUT1_SNR_EXCEED_MAP1_PASS (0x00000002u)
#define CSL_TCP2_TCPOUT1_CRC_PASS_MASK (0x20000000u)
#define CSL_TCP2_TCPOUT1_CRC_PASS_SHIFT (0x0000001Du)
#define CSL_TCP2_TCPOUT1_CRC_PASS_RESETVAL (0x00000000u)
/*----CRC_PASS Tokens----*/
#define CSL_TCP2_TCPOUT1_CRC_PASS_NO (0x00000000u)
#define CSL_TCP2_TCPOUT1_CRC_PASS_YES (0x00000001u)
#define CSL_TCP2_TCPOUT1_ACTIVE_MAP_MASK (0x10000000u)
#define CSL_TCP2_TCPOUT1_ACTIVE_MAP_SHIFT (0x0000001Cu)
#define CSL_TCP2_TCPOUT1_ACTIVE_MAP_RESETVAL (0x00000000u)
/*----ACTIVE_MAP Tokens----*/
#define CSL_TCP2_TCPOUT1_ACTIVE_MAP_MAP0 (0x00000000u)
#define CSL_TCP2_TCPOUT1_ACTIVE_MAP_MAP1 (0x00000001u)
#define CSL_TCP2_TCPOUT1_SNR_M2_MASK (0x00FFFFFFu)
#define CSL_TCP2_TCPOUT1_SNR_M2_SHIFT (0x00000000u)
#define CSL_TCP2_TCPOUT1_SNR_M2_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPOUT1_RESETVAL (0x00000000u)
/* TCPOUT2 */
#define CSL_TCP2_TCPOUT2_CNT_RE_MAP1_MASK (0xFFFF0000u)
#define CSL_TCP2_TCPOUT2_CNT_RE_MAP1_SHIFT (0x00000010u)
#define CSL_TCP2_TCPOUT2_CNT_RE_MAP1_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPOUT2_CNT_RE_MAP0_MASK (0x0000FFFFu)
#define CSL_TCP2_TCPOUT2_CNT_RE_MAP0_SHIFT (0x00000000u)
#define CSL_TCP2_TCPOUT2_CNT_RE_MAP0_RESETVAL (0x00000000u)
#define CSL_TCP2_TCPOUT2_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/pllc/src/pllc_example.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file Pllc_example.c
*
* @path $(CSLPATH)\example\pllc\src
*
* @desc Example of PLLC module CSL
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n The example shows PLLC module CSL usage
* 1. Initalize the PLLC hardware setup data structure with default values
* 2. Intialize PLLC module
* 3. Set new values for divider 4
* 4. Set the value using hardware control command
* 5. Close the module
* ============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used.
* Refer CCS manual for setup configuration.
* 2. Load required GEL file depending on the board used.
* 3. Launch CCS window.
* 4. Open project pllc_example.pjt.
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 22-Sep-2005 Tej File Modified.
* 19-Dec-2005 SD Modified according to the review comments
* 06-Feb-2006 SD Modified according to the spec changes
*
* ============================================================================
*/
#include <stdio.h>
#include <csl_pllc.h>
/* PLLC module handle structure */
CSL_PllcHandle hPllc = NULL;
/* forward declarations*/
void pllc_csl_example (void);
void pllc_error_exit (void);
/*
* ============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* @arg
* NONE
*
* @return
* NONE
* ============================================================================
*/
void main (
void
)
{
/* Call the example routine */
pllc_csl_example ();
}
/*
* ============================================================================
* @func pllc_csl_example
*
* @desc
* 1. Initalize the PLLC hardware setup data structure with default values
* 2. Intialize PLLC module
* 3. Set new values for divider 4
* 4. Set the value using hardware control command
* 5. Close the module
*
* @arg
* NONE
*
* @return
* NONE
* ============================================================================
*/
void pllc_csl_example (
void
)
{
CSL_PllcObj pllcObj;
CSL_Status status;
CSL_PllcHwSetup hwSetup;
CSL_PllcHwSetup hwSetupRead;
CSL_PllcDivideControl arg;
CSL_PllcDivRatio arg1;
CSL_BitMask32 response;
CSL_BitMask32 argPllCtrl;
/* Initialize the PLLC CSL module */
status = CSL_pllcInit(NULL);
if (status != CSL_SOK) {
printf ("PLLC: Initialization... Failed.\n");
printf ("\tReason: CSL_pllcInit failed. [status = 0x%x].\n", status);
return;
}
/* Clear local data structures */
memset(&pllcObj, 0, sizeof(CSL_PllcObj));
/* Open the PLLC CSL module */
hPllc = CSL_pllcOpen (&pllcObj, CSL_PLLC_1, NULL, &status);
if ((hPllc == NULL) || (status != CSL_SOK)) {
printf ("PLLC: Open... Failed.\n");
printf ("\tReason: Error opening the instance. [status = 0x%x, "\
"hPllc = 0x%x].\n", status, hPllc);
return;
}
/* Setup PLLC hardware parameters */
hwSetup.divEnable = (CSL_BitMask32) CSL_PLLC_DIVEN_PLLDIV4 | CSL_PLLC_DIVEN_PREDIV |
CSL_PLLC_DIVEN_PLLDIV5;
hwSetup.preDiv = (Uint32) 0x00000002;
hwSetup.pllM = (Uint32) 0x000000015;
hwSetup.pllDiv4 = (Uint32) 0x00000002;
hwSetup.pllDiv5 = (Uint32) 0x00000002;
status = CSL_pllcHwSetup (hPllc, &hwSetup);
if (status != CSL_SOK) {
printf ("PLLC: HwSetup... Failed.\n");
printf ("\tReason: Error setting up the hardware."\
" [status = 0x%x, hPllc = 0x%x].\n", status, hPllc);
pllc_error_exit ();
return;
}
/* Read back */
status = CSL_pllcGetHwSetup (hPllc, &hwSetupRead);
if (status != CSL_SOK) {
printf ("PLLC: Hardware setup parameters reading... Failed.\n");
printf ("\tReason: Error setting in hardware validation."\
" [status = 0x%x, hPllc = 0x%x].\n", status, hPllc);
pllc_error_exit ();
}
/* Change divider settings for PLLDIV4 */
/* Wait if another GO operation is currently in progress.*/
do {
CSL_pllcGetHwStatus (hPllc, CSL_PLLC_QUERY_STATUS, &response);
} while (response & CSL_PLLC_STATUS_GO);
/* Command to enable PLLDIV4 */
arg.divNum = CSL_PLLC_DIVSEL_PLLDIV4;
arg.divCtrl = CSL_PLLC_PLLDIV_ENABLE;
status = CSL_pllcHwControl (hPllc, CSL_PLLC_CMD_PLLDIV_CONTROL,
&arg);
if (status != CSL_SOK) {
printf ("PLLC: HwControl for PLL Divider Control... Failed.\n");
printf ("\tReason: Error in Divider Control."\
" [status = 0x%x, hPllc = 0x%x].\n", status, hPllc);
pllc_error_exit ();
return;
}
/* Command to change PLLDIV4 Divider Ratio */
arg1.divNum = CSL_PLLC_DIVSEL_PLLDIV4;
arg1.divRatio = 0x00000004;
status = CSL_pllcHwControl (hPllc, CSL_PLLC_CMD_SET_PLLRATIO,
&arg1);
if ((status != CSL_SOK) || (status == CSL_ESYS_INVPARAMS))
{
printf ("PLLC: HwControl for PLL Divider Ratio Set Command "\
"Control... Failed.\n");
printf ("\tReason: Error in Control for Divider Ratio Set Command."\
" [status = 0x%x, hPllc = 0x%x].\n", status, hPllc);
pllc_error_exit ();
return;
}
/* Set GOSET bit to change/set the dividers */
argPllCtrl = 0x010000; /* value to set the GOSET bit */
status = CSL_pllcHwControl (hPllc, CSL_PLLC_CMD_PLLCONTROL,
&argPllCtrl);
if (status != CSL_SOK) {
printf ("PLLC: HwControl for PLL command control... Failed.\n");
printf ("\tReason: Error in PLL Command Control."\
" [status = 0x%x, hPllc = 0x%x].\n", status, hPllc);
pllc_error_exit ();
return;
}
/* Poll for divide-ratio change and clock alignment to complete */
do {
CSL_pllcGetHwStatus (hPllc, CSL_PLLC_QUERY_STATUS, &response);
} while (response & CSL_PLLC_STATUS_GO);
/* Close the module */
status = CSL_pllcClose (hPllc);
if (status != CSL_SOK) {
printf ("PLLC: Close the instance ... Failed\n");
}
printf("PLLC example complete \n");
return;
}
/*
* ============================================================================
* @func pllc_error_exit
*
* @desc
* This calls the module close function in case of error
*
* @arg
* NONE
*
* @return
* NONE
* ============================================================================
*/
void pllc_error_exit (
void
)
{
CSL_Status status;
/* Closes the module */
status = CSL_pllcClose (hPllc);
if (status != CSL_SOK) {
printf ("PLLC: Close Pllc instance... Failed\n");
}
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_cfg.h
|
<reponame>adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_cfg.h
*
* @path $(CSLPATH)\inc
*
* @desc Header file for functional layer of CFG CSL
*
*/
/** ===========================================================================
* @mainpage CFG Module
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to identify a set of common CSL APIs for
* the CFG Module across various devices. The CSL developer
* is expected to refer to this document while implementing APIs for these
* modules. Some of the listed APIs may not be applicable to a given CFG
*
*
*
* @subsection aaa Terms and Abbreviations
* -# CSL : Chip Support Library
* -# API : Application Programmer Interface
* -# CFG : Configuration
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 14-Apr-2005 Brn file created
* 16-Nov-2005 ds updated the documentation
* 31-Jan-2006 ds added CSL_cfgGetbaseaddress () API and CSL_CfgBaseAddress
* structure
* ============================================================================
*/
#ifndef _CSL_CFG_H_
#define _CSL_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <cslr_cfg.h>
#include <soc.h>
/** Mask value of Fault ID */
#define CSL_CFG_FAULT_STAT_FID (0x0000F700u)
/** Mask value to get the status of Local memory (L1/L2) */
#define CSL_CFG_FAULT_STAT_LOCAL (0x00000080u)
/** Mask value for Supervisor Read */
#define CSL_CFG_FAULT_STAT_SR (0x00000020u)
/** Mask value for Supervisor Write */
#define CSL_CFG_FAULT_STAT_SW (0x00000010u)
/** Mask value for Supervisor Execute */
#define CSL_CFG_FAULT_STAT_SX (0x00000008u)
/** Mask value for User Read */
#define CSL_CFG_FAULT_STAT_UR (0x00000004u)
/** Mask value for User Write */
#define CSL_CFG_FAULT_STAT_UW (0x00000002u)
/** Mask value for User Execute */
#define CSL_CFG_FAULT_STAT_UX (0x00000001u)
/** @brief Enumeration for queries passed to @a CSL_cfgHwControl()
*
* This is used to select the commands to control the operations
* existing setup of CFG. The arguments to be passed with each
* enumeration if any are specified next to the enumeration.
*/
typedef enum {
/** @brief CFG Hardware control command to clears the error conditions
* stored in MPFAR and MPFSR
* @param None
*/
CSL_CFG_CMD_CLEAR = 0
} CSL_CfgHwControlCmd;
/** @brief Enumeration for queries passed to @a CSL_cfgGetHwStatus()
*
* This is used to get the status of different operations or to get the
* existing setup of CFG.
*/
typedef enum {
/**
* @brief Status query command to get the Fault Address
* @param (Uint32 *)
*/
CSL_CFG_QUERY_FAULT_ADDR = 1,
/**
* @brief Status query command to get the Status information of
* CSL_CfgStatus
* @param (CSL_CfgFaultStatus *)
*/
CSL_CFG_QUERY_FAULT_STATUS = 2
} CSL_CfgHwStatusQuery;
/** @brief CSL_CfgStatus has all the fields required for the status information
* of CFG module.
*/
typedef struct {
/** Bit Mask of the Errors */
CSL_BitMask16 errorMask;
/** Fault Id. The IDof the originator of the faulting access */
Uint16 faultId;
} CSL_CfgFaultStatus;
/**
* This will have the base-address information for the peripheral instance
*/
typedef struct {
/** Base-address of the Configuration registers of CFG */
CSL_CfgRegsOvly regs;
} CSL_CfgBaseAddress;
/**
* CFG specific parameters. Present implementation doesn't have
* any specific parameters.
*/
typedef struct {
/** Bit mask to be used for module specific parameters.
* The below declaration is just a place-holder for future
* implementation.
*/
CSL_BitMask16 flags;
} CSL_CfgParam;
/**
* CFG specific context information. Present implementation doesn't
* have any Context information.
*/
typedef struct {
/** Context information of CFG.
* The below declaration is just a place-holder for future
* implementation.
*/
Uint16 contextInfo;
} CSL_CfgContext;
/** @brief This object contains the reference to the instance of CFG
* opened using the @a CSL_cfgOpen()
*
* The pointer to this is passed as CFG Handle to all CFG CSL APIs.
* CSL_cfgOpen() function initializes this structure based on the parameters
* passed
*/
typedef struct CSL_CfgObj {
/** This is a pointer to the registers of the instance of CFG
* referred to by this object
*/
CSL_CfgRegsOvly regs;
/** This is the instance of CFG being referred to by this object */
CSL_InstNum cfgNum;
} CSL_CfgObj;
/** @brief this is a pointer to @a CSL_CfgObj & is passed as the first
* parameter to all CFG CSL APIs
*/
typedef CSL_CfgObj *CSL_CfgHandle;
/* ===========================================================================
* @n@b CSL_cfgOpen
*
* @b Description
* @n This function populates the peripheral data object for the instance
* and returns a handle to the instance.
* The open call sets up the data structures for the particular instance
* of CFG device. The device can be re-opened anytime after it has
* been normally closed, if so required. The handle returned by this call
* is input as an essential argument for rest of the APIs described for
* this module.
*
* @b Arguments
* @verbatim
pCfgObj Pointer to the CFG instance object
cfgNum Instance of the CFG to be opened.
pCfgParam Pointer to module specific parameters
pStatus pointer for returning status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_CfgHandle
* @n Valid CFG instance handle will be returned if status value is
* equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n CSL_cfgInit has to be called defore this function get called
*
* <b> Post Condition </b>
* @n CSL_cfgInit has to be called before calling this function.
* Post Condition
* 1. The status is returned in the status variable. If status returned is
* - CSL_SOK - Valid CFG handle is returned.
* - CSL_ESYS_FAIL - The CFG instance is invalid.
* 2. CFG object structure is populated.
*
*
* @b Modifies
* @n 1. The status variable
* 2. CFG object structure
*
* @b Example
* @verbatim
CSL_status status;
CSL_CfgObj cfgObj;
CSL_CfgHandle hCfg;
hCfg = CSL_cfgOpen (&cfgObj, CSL_MEMPROT_CONFIG, NULL, &status);
@endverbatim
* ===========================================================================
*/
CSL_CfgHandle CSL_cfgOpen (
/* Pointer to the handle object - to be allocated by the user */
CSL_CfgObj *hCfgObj,
/* Specifies the instance of CFG to be opened */
CSL_InstNum cfgNum,
/* Module specific parameters;
* Currently there are none; the user should pass 'NULL'
*/
CSL_CfgParam *pCfgParam,
/* Pointer to the variable that holds the holds the status of the open
* call
*/
CSL_Status *status
);
/* ============================================================================
* @n@b CSL_cfgClose
*
* @b Description
* @n This function closes the specified instance of CFG.
*
* <b> Usage Constraints: </b>
* Both @a CSL_cfgInit() and @a CSL_cfgOpen() must be called successfully
* in that order before @a CSL_cfgClose() can be called.
*
* @arg hCfg Handle to the CFG instance
*
* <b> Return Value </b> CSL_Status
* CSL_SOK - Close successful
* CSL_ESYS_BADHANDLE - Invalid handle
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CSL_cfgClose(hCfg);
...
@endverbatim
* =============================================================================
*/
CSL_Status CSL_cfgClose (
/* Handle to the CFG instance */
CSL_CfgHandle hCfg
);
/* ============================================================================
* @n@b CSL_cfgHwControl
*
* @b Description
* @n Takes a command of CFG with an optional argument & implements it.
*
* @b Arguments
* @verbatim
hCfg Handle to the CFG instance
cmd The command to this API indicates the action to be
taken on CFG.
arg An optional argument.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful.
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n The registers of CFG.
*
* @b Example
* @verbatim
CSL_CfgHandle hCfg;
CSL_CfgHwControlCmd cmd;
void arg;
...
status = CSL_cfgHwControl(hCfg, cmd, &arg);
...
@endverbatim
* =============================================================================
*/
CSL_Status CSL_cfgHwControl (
/* Handle to the CFG instance */
CSL_CfgHandle hCfg,
/* The command to this API which indicates the action to be taken */
CSL_CfgHwControlCmd cmd,
/* Optional argument @a void* casted */
void *cmdArg
);
/* ============================================================================
* @n@b CSL_cfgInit
*
* @b Description
* @n This is the initialization function for the CFG. This function is
* idempotent in that calling it many times is same as calling it once.
* This function initializes the CSL data structures, and doesn't affect
* the H/W.
*
* @b Arguments
@verbatim
pContext Context information for the instance. Should be NULL
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CSL_cfgInit();
...
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_cfgInit (
/* CFG Context */
CSL_CfgContext *pContext
);
/* ============================================================================
* @n@b CSL_cfgGetHwStatus
*
* @b Description
* @n Gets the status of the different operations of CFG.
*
* @b Arguments
* @verbatim
hCfg Handle to the CFG instance
query The query to this API of CFG which indicates the
status to be returned.
response Placeholder to return the status.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful
* @li CSL_ESYS_INVQUERY - Invalid query command
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* None
*
* @b Example
* @verbatim
CSL_CfgHandle hCfg;
CSL_CfgHwStatusQuery query;
void reponse;
status = CSL_GetcfgHwStatus (hCfg, query, &response);
@endverbatim
* =============================================================================
*/
CSL_Status CSL_cfgGetHwStatus (
/* Handle to the CFG instance */
CSL_CfgHandle hCfg,
/* The query to this API which indicates the status/setup
* to be returned
*/
CSL_CfgHwStatusQuery myQuery,
/* Placeholder to return the status; @a void* casted */
void *response
);
/** ============================================================================
* @n@b CSL_cfgGetBaseAddress
*
* @b Description
* @n Function to get the base address of the peripheral instance.
* This function is used for getting the base address of the peripheral
* instance. This function will be called inside the CSL_cfgOpen()
* function call. This function is open for re-implementing if the user
* wants to modify the base address of the peripheral object to point to
* a different location and there by allow CSL initiated write/reads into
* peripheral. MMR's go to an alternate location.
*
* @b Arguments
* @verbatim
cfgNum Specifies the instance of the CFG to be opened.
pCfgParam Module specific parameters.
pBaseAddress Pointer to baseaddress structure.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Successful on getting the base
* address of CFG
* @li CSL_ESYS_FAIL The instance number is invalid.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n Base Address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure is modified.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_CfgBaseAddress baseAddress;
...
status = CSL_cfgGetBaseAddress(CSL_MEMPROT_CONFIG, NULL, &baseAddress);
@endverbatim
* ===========================================================================
*/
CSL_Status CSL_cfgGetBaseAddress (
CSL_InstNum cfgNum,
CSL_CfgParam *pCfgParam,
CSL_CfgBaseAddress *pBaseAddress
);
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/mcbsp/_csl_mcbspClearFrmSyncErr.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/mcbsp/_csl_mcbspClearFrmSyncErr.c<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file _csl_mcbspClearFrmSyncErr.c
*
* @path $(CSLPATH)\src\mcbsp
*
* @desc File for functional layer of CSL API _CSL_mcbspClearFrmSyncErr()
*
*/
/* =============================================================================
* Revision History
* ================
* June 29,2004 <NAME> - Created
*
* =============================================================================
*/
#include <csl_mcbsp.h>
#include <_csl_mcbsp.h>
/* ============================================================================
* @n@b _CSL_mcbspClearFrmSyncErr
*
* @b Description
* @n Clear Frame Sync Error for Receiver and Transmitter
*
* @b Arguments
* @verbatim
hMcbsp MCBSP handle returned by successful 'open'
chanType Selects receiver/transmitter
@endverbatim
*
* <b> Return Value </b>
* @n None
*
* <b> Pre Condition </b>
* @n CSL_mcbspInit() and CSL_mcbspOpen() must be called successfully
* in that order before _CSL_mcbspClearFrmSyncErr() can be called.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_McbspHandle hMcbsp;
...
hMcbsp = CSL_mcbspOpen(hMcbsp, CSL_MCBSP_1,NULL, &status );
_CSL_mcbspClearFrmSyncErr( hMcbsp, CSL_MCBSP_RX);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (_CSL_mcbspClearFrmSyncErr, ".text:csl_section:mcbsp");
void _CSL_mcbspClearFrmSyncErr (
CSL_McbspHandle hMcbsp,
CSL_McbspChType chanType
)
{
/* NOTE: The extra step of storing register value in a temporary
* variable is done to avoid the Codegen tool bug: SDSsq32003
*/
/* Clear Receive Frame Sync Error */
if( chanType == CSL_MCBSP_CHTYPE_RX ) {
CSL_FINS( hMcbsp->regs->SPCR, MCBSP_SPCR_RSYNCERR, \
CSL_MCBSP_SPCR_RSYNCERR_CLEAR );
}
/* Clear Transmit Frame Sync Error */
if( chanType == CSL_MCBSP_CHTYPE_TX ) {
CSL_FINS( hMcbsp->regs->SPCR, MCBSP_SPCR_XSYNCERR, \
CSL_MCBSP_SPCR_XSYNCERR_CLEAR );
}
/* Clear Transmit & Receive Frame Sync Errors */
if( chanType == CSL_MCBSP_CHTYPE_TXRX ) {
CSL_FINS( hMcbsp->regs->SPCR, MCBSP_SPCR_XSYNCERR, \
CSL_MCBSP_SPCR_XSYNCERR_CLEAR );
CSL_FINS( hMcbsp->regs->SPCR, MCBSP_SPCR_RSYNCERR, \
CSL_MCBSP_SPCR_RSYNCERR_CLEAR );
}
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/cslr_memprot_L1P.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file cslr_memprot_L1P.h
*
* @path $(CSLPATH)\inc
*
* @desc This file contains the Register Descriptions for MEMPROTL1P
*/
#ifndef _CSLR_MEMPROT_L1P_H_
#define _CSLR_MEMPROT_L1P_H_
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 MPFAR;
volatile Uint32 MPFSR;
volatile Uint32 MPFCR;
volatile Uint8 RSVD0[244];
volatile Uint32 MPLK0;
volatile Uint32 MPLK1;
volatile Uint32 MPLK2;
volatile Uint32 MPLK3;
volatile Uint32 MPLKCMD;
volatile Uint32 MPLKSTAT;
volatile Uint8 RSVD1[232];
volatile Uint32 MPPA[32];
} CSL_Memprotl1pRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_Memprotl1pRegs *CSL_Memprotl1pRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* MPFAR */
#define CSL_MEMPROTL1P_MPFAR_ADDR_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL1P_MPFAR_ADDR_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPFAR_ADDR_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFAR_RESETVAL (0x00000000u)
/* MPFSR */
#define CSL_MEMPROTL1P_MPFSR_FID_MASK (0x0000FE00u)
#define CSL_MEMPROTL1P_MPFSR_FID_SHIFT (0x00000009u)
#define CSL_MEMPROTL1P_MPFSR_FID_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_LOCAL_MASK (0x00000100u)
#define CSL_MEMPROTL1P_MPFSR_LOCAL_SHIFT (0x00000008u)
#define CSL_MEMPROTL1P_MPFSR_LOCAL_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_SR_MASK (0x00000020u)
#define CSL_MEMPROTL1P_MPFSR_SR_SHIFT (0x00000005u)
#define CSL_MEMPROTL1P_MPFSR_SR_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_SW_MASK (0x00000010u)
#define CSL_MEMPROTL1P_MPFSR_SW_SHIFT (0x00000004u)
#define CSL_MEMPROTL1P_MPFSR_SW_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_SX_MASK (0x00000008u)
#define CSL_MEMPROTL1P_MPFSR_SX_SHIFT (0x00000003u)
#define CSL_MEMPROTL1P_MPFSR_SX_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_UR_MASK (0x00000004u)
#define CSL_MEMPROTL1P_MPFSR_UR_SHIFT (0x00000002u)
#define CSL_MEMPROTL1P_MPFSR_UR_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_UW_MASK (0x00000002u)
#define CSL_MEMPROTL1P_MPFSR_UW_SHIFT (0x00000001u)
#define CSL_MEMPROTL1P_MPFSR_UW_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_UX_MASK (0x00000001u)
#define CSL_MEMPROTL1P_MPFSR_UX_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_UX_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPFSR_RESETVAL (0x00000000u)
/* MPFCR */
#define CSL_MEMPROTL1P_MPFCR_MPFCLR_MASK (0x00000001u)
#define CSL_MEMPROTL1P_MPFCR_MPFCLR_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPFCR_MPFCLR_RESETVAL (0x00000000u)
/*----MPFCLR Tokens----*/
#define CSL_MEMPROTL1P_MPFCR_MPFCLR_CLEAR (0x00000001u)
#define CSL_MEMPROTL1P_MPFCR_RESETVAL (0x00000000u)
/* MPLK0 */
#define CSL_MEMPROTL1P_MPLK0_RESERVED_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL1P_MPLK0_RESERVED_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPLK0_RESERVED_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPLK0_RESETVAL (0x00000000u)
/* MPLK1 */
#define CSL_MEMPROTL1P_MPLK1_RESERVED_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL1P_MPLK1_RESERVED_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPLK1_RESERVED_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPLK1_RESETVAL (0x00000000u)
/* MPLK2 */
#define CSL_MEMPROTL1P_MPLK2_RESERVED_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL1P_MPLK2_RESERVED_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPLK2_RESERVED_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPLK2_RESETVAL (0x00000000u)
/* MPLK3 */
#define CSL_MEMPROTL1P_MPLK3_RESERVED_MASK (0xFFFFFFFFu)
#define CSL_MEMPROTL1P_MPLK3_RESERVED_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPLK3_RESERVED_RESETVAL (0x00000000u)
#define CSL_MEMPROTL1P_MPLK3_RESETVAL (0x00000000u)
/* MPLKCMD */
#define CSL_MEMPROTL1P_MPLKCMD_KEYR_MASK (0x00000004u)
#define CSL_MEMPROTL1P_MPLKCMD_KEYR_SHIFT (0x00000002u)
#define CSL_MEMPROTL1P_MPLKCMD_KEYR_RESETVAL (0x00000000u)
/*----KEYR Tokens----*/
#define CSL_MEMPROTL1P_MPLKCMD_KEYR_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPLKCMD_KEYR_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPLKCMD_LOCK_MASK (0x00000002u)
#define CSL_MEMPROTL1P_MPLKCMD_LOCK_SHIFT (0x00000001u)
#define CSL_MEMPROTL1P_MPLKCMD_LOCK_RESETVAL (0x00000000u)
/*----LOCK Tokens----*/
#define CSL_MEMPROTL1P_MPLKCMD_LOCK_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPLKCMD_LOCK_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPLKCMD_UNLOCK_MASK (0x00000001u)
#define CSL_MEMPROTL1P_MPLKCMD_UNLOCK_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPLKCMD_UNLOCK_RESETVAL (0x00000000u)
/*----UNLOCK Tokens----*/
#define CSL_MEMPROTL1P_MPLKCMD_UNLOCK_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPLKCMD_UNLOCK_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPLKCMD_RESETVAL (0x00000000u)
/* MPLKSTAT */
#define CSL_MEMPROTL1P_MPLKSTAT_LK_MASK (0x00000001u)
#define CSL_MEMPROTL1P_MPLKSTAT_LK_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPLKSTAT_LK_RESETVAL (0x00000000u)
/*----LK Tokens----*/
#define CSL_MEMPROTL1P_MPLKSTAT_LK_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPLKSTAT_LK_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPLKSTAT_RESETVAL (0x00000000u)
/* MPPA */
#define CSL_MEMPROTL1P_MPPA_AID5_MASK (0x00008000u)
#define CSL_MEMPROTL1P_MPPA_AID5_SHIFT (0x0000000Fu)
#define CSL_MEMPROTL1P_MPPA_AID5_RESETVAL (0x00000000u)
/*----AID5 Tokens----*/
#define CSL_MEMPROTL1P_MPPA_AID5_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_AID5_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_AID4_MASK (0x00004000u)
#define CSL_MEMPROTL1P_MPPA_AID4_SHIFT (0x0000000Eu)
#define CSL_MEMPROTL1P_MPPA_AID4_RESETVAL (0x00000000u)
/*----AID4 Tokens----*/
#define CSL_MEMPROTL1P_MPPA_AID4_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_AID4_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_AID3_MASK (0x00002000u)
#define CSL_MEMPROTL1P_MPPA_AID3_SHIFT (0x0000000Du)
#define CSL_MEMPROTL1P_MPPA_AID3_RESETVAL (0x00000000u)
/*----AID3 Tokens----*/
#define CSL_MEMPROTL1P_MPPA_AID3_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_AID3_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_AID2_MASK (0x00001000u)
#define CSL_MEMPROTL1P_MPPA_AID2_SHIFT (0x0000000Cu)
#define CSL_MEMPROTL1P_MPPA_AID2_RESETVAL (0x00000000u)
/*----AID2 Tokens----*/
#define CSL_MEMPROTL1P_MPPA_AID2_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_AID2_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_AID1_MASK (0x00000800u)
#define CSL_MEMPROTL1P_MPPA_AID1_SHIFT (0x0000000Bu)
#define CSL_MEMPROTL1P_MPPA_AID1_RESETVAL (0x00000000u)
/*----AID1 Tokens----*/
#define CSL_MEMPROTL1P_MPPA_AID1_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_AID1_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_AID0_MASK (0x00000400u)
#define CSL_MEMPROTL1P_MPPA_AID0_SHIFT (0x0000000Au)
#define CSL_MEMPROTL1P_MPPA_AID0_RESETVAL (0x00000000u)
/*----AID0 Tokens----*/
#define CSL_MEMPROTL1P_MPPA_AID0_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_AID0_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_ADX_MASK (0x00000200u)
#define CSL_MEMPROTL1P_MPPA_ADX_SHIFT (0x00000009u)
#define CSL_MEMPROTL1P_MPPA_ADX_RESETVAL (0x00000000u)
/*----ADX Tokens----*/
#define CSL_MEMPROTL1P_MPPA_ADX_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_ADX_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_LOCAL_MASK (0x00000100u)
#define CSL_MEMPROTL1P_MPPA_LOCAL_SHIFT (0x00000008u)
#define CSL_MEMPROTL1P_MPPA_LOCAL_RESETVAL (0x00000000u)
/*----LOCAL Tokens----*/
#define CSL_MEMPROTL1P_MPPA_LOCAL_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_LOCAL_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_SR_MASK (0x00000020u)
#define CSL_MEMPROTL1P_MPPA_SR_SHIFT (0x00000005u)
#define CSL_MEMPROTL1P_MPPA_SR_RESETVAL (0x00000000u)
/*----SR Tokens----*/
#define CSL_MEMPROTL1P_MPPA_SR_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_SR_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_SW_MASK (0x00000010u)
#define CSL_MEMPROTL1P_MPPA_SW_SHIFT (0x00000004u)
#define CSL_MEMPROTL1P_MPPA_SW_RESETVAL (0x00000000u)
/*----SW Tokens----*/
#define CSL_MEMPROTL1P_MPPA_SW_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_SW_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_SX_MASK (0x00000008u)
#define CSL_MEMPROTL1P_MPPA_SX_SHIFT (0x00000003u)
#define CSL_MEMPROTL1P_MPPA_SX_RESETVAL (0x00000000u)
/*----SX Tokens----*/
#define CSL_MEMPROTL1P_MPPA_SX_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_SX_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_UR_MASK (0x00000004u)
#define CSL_MEMPROTL1P_MPPA_UR_SHIFT (0x00000002u)
#define CSL_MEMPROTL1P_MPPA_UR_RESETVAL (0x00000000u)
/*----UR Tokens----*/
#define CSL_MEMPROTL1P_MPPA_UR_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_UR_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_UW_MASK (0x00000002u)
#define CSL_MEMPROTL1P_MPPA_UW_SHIFT (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_UW_RESETVAL (0x00000000u)
/*----UW Tokens----*/
#define CSL_MEMPROTL1P_MPPA_UW_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_UW_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_UX_MASK (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_UX_SHIFT (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_UX_RESETVAL (0x00000000u)
/*----UX Tokens----*/
#define CSL_MEMPROTL1P_MPPA_UX_NO (0x00000000u)
#define CSL_MEMPROTL1P_MPPA_UX_YES (0x00000001u)
#define CSL_MEMPROTL1P_MPPA_RESETVAL (0x00000000u)
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/pwrdwn/csl_pwrdwnHwSetupRaw.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_pwrdwnHwSetupRaw.c
*
* @path $(CSLPATH)\src\pwrdwn
*
* @desc File for functional layer of CSL API CSL_pwrdwnHwSetupRaw ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 16-Jul-2004 <NAME> File Created
* =============================================================================
*/
#include <csl_pwrdwn.h>
/** ===========================================================================
* @n@b CSL_pwrdwnHwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the config data structure.
*
* @b Arguments
* @verbatim
hPwrdwn Pointer to the object that holds reference to the
instance of PWRDWN requested after the call
config Pointer to the config structure containing the
device register values
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration structure
* pointer is not properly
* initialized
*
* <b> Pre Condition </b>
* @n CSL_pwrdwnInit(), CSL_pwrdwnOpen() must be opened prior to this call
*
* <b> Post Condition </b>
* @n The registers of the specified PWRDWN instance will be setup
* according to the values passed through the config structure
*
* @b Modifies
* @n Hardware registers of the specified PWRDWN instance
*
* @b Example
@verbatim
CSL_PwrdwnObj pwrObj;
CSL_PwrdwnConfig pwrConfig;
CSL_PwrdwnHandle hPwr;
// Init Module
...
if (CSL_pwrdwnInit(NULL) != CSL_SOK)
exit;
// Opening a handle for the Module
hPwr = CSL_pwrdwnOpen (&pwrObj, CSL_PWRDWN, NULL, NULL);
// Setup the arguments for the Config structure
...
// Setup
CSL_pwrdwnHwSetupRaw(hPwr,&pwrConfig);
// Close handle
CSL_pwrdwnClose(hPwr);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pwrdwnHwSetupRaw, ".text:csl_section:pwrdwn");
CSL_Status CSL_pwrdwnHwSetupRaw (
CSL_PwrdwnHandle hPwrdwn,
CSL_PwrdwnConfig *config
)
{
CSL_Status status = CSL_SOK;
if (hPwrdwn == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (config == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
hPwrdwn->pdcRegs->PDCCMD = config->PDCCMD;
hPwrdwn->l2pwrdwnRegs->L2PDWAKE[0] = config->L2PDWAKE0;
hPwrdwn->l2pwrdwnRegs->L2PDWAKE[1] = config->L2PDWAKE1;
hPwrdwn->l2pwrdwnRegs->L2PDSLEEP[0] = config->L2PDSLEEP0;
hPwrdwn->l2pwrdwnRegs->L2PDSLEEP[1] = config->L2PDSLEEP1;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/edma/edma2x_example/src/edma_int_dispatcher.c
|
/* =====================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* =====================================================================
*/
/** =====================================================================
* @file edma_int_desp.c
*
* @path $(CSLPATH)\example\edma\src
*
* @desc This file has routines to handle the EDMA interrupts.
*
* ======================================================================
*/
/* ======================================================================
* Revision History
* ================
* 01-Aug-2005 Chandra File created.
* 11-Aug-2005 Chandra Minor format changes.
* ======================================================================
*/
#include <csl_edma2.h>
#include <edma_int_dispatcher.h>
/* Global Edma Tcc handler table */
#pragma DATA_SECTION(TccHandlerTable,".exampleMem");
static void (*TccHandlerTable[EDMA_CHA_CNT]) () = { 0 };
/**
* ======================================================================
* @func eventEdmaHandler
*
* @desc
* This calls all the handlers of the TCC interrupts.
*
* @n <b> Procedure </b>
* @verbatim
For each TCC
1. Check if the interrupt is pending for that TCC
if pending
2. Call the corresponding handler
3. Clear the interrupt
@endverbatim
* ======================================================================
*/
void eventEdmaHandler (
void *handle
)
{
Uint32 tcc, status;
for (tcc = 0; tcc < EDMA_CHA_CNT; tcc++) {
status = EDMA_intTest (tcc);
if (status) {
TccHandlerTable[tcc] (tcc);
EDMA_intClear (tcc);
}
}
}
/**
* ======================================================================
* @func edmaEventHook
*
* @desc
* Hooks an interrupt for a given TCC number.
*
* @n <b> Procedure </b>
* @verbatim
1. Copies the address of given ISR into the given entry of
the TCC handler table.
@endverbatim
* ======================================================================
*/
void edmaEventHook (
Int tcc,
void fxn ()
)
{
TccHandlerTable[tcc] = fxn;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/common/csl_emifaGetBaseAddress.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_emifaGetBaseAddress.c
*
* @path $(CSLPATH)\src\common
*
* @desc CSL Implementation of CSL_emifaGetBaseAddress
*
*/
/* ============================================================================
* Revision History
* ===============
* 13-May-2005 <NAME> File Created.
* 25-Jan-2006 SD Modified the code section start address
* 09-Aug-2006 NG Added condition to check the invalid parameter
*
* ============================================================================
*/
#include <soc.h>
#include <csl_emifa.h>
/** ============================================================================
* @n@b CSL_emifaGetBaseAddress
*
* @b Description
* @n The get base address call will give the External memory interface current
* current instance base address
*
* @b Arguments
* @verbatim
emifaNum Specifies the instance of the EMIFA external memory
interface for which the base address is requested
pEmifaParam Module specific parameters.
pBaseAddress Pointer to the base address structure to return the
base address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Successful on getting the base
* address of emifa
* @li CSL_ESYS_FAIL The external memory interface
* instance is not available.
* @li CSL_ESYS_INVPARAMS Invalid parameter
*
* <b> Pre Condition </b>
* @n @a CSL_emifaInit() and CSL_emifaOpen () must be called successfully.
*
* <b> Post Condition </b>
* @n Base address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_EmifaBaseAddress baseAddress;
...
status = CSL_emifaGetBaseAddress(CSL_EMIFA, NULL, &baseAddress);
@endverbatim
* @return Returns the status of the get base address operation
*
* ============================================================================
*/
#pragma CODE_SECTION (CSL_emifaGetBaseAddress, ".text:csl_section:emifa");
CSL_Status CSL_emifaGetBaseAddress (
CSL_InstNum emifaNum,
CSL_EmifaParam *pEmifaParam,
CSL_EmifaBaseAddress *pBaseAddress
)
{
CSL_Status status = CSL_SOK;
if (pBaseAddress == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (emifaNum) {
case CSL_EMIFA:
pBaseAddress->regs = (CSL_EmifaRegsOvly)CSL_EMIFA_0_REGS;
break;
default:
pBaseAddress->regs = (CSL_EmifaRegsOvly)NULL;
status = CSL_ESYS_FAIL;
break;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/_csl_cache.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/* ============================================================================
* @file _csl_cache.h
*
* @path $(CSLPATH)\inc
*
* @desc This file defines the functions in the Cache
*
*/
/* =============================================================================
* Revision History
* ===============
* 23-Mar-2004 <NAME> File Created.
*
* =============================================================================
*/
#ifndef __CSL_CACHE_H_
#define __CSL_CACHE_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Enum for CACHE Wait State */
typedef enum {
/* Cache no wait */
CACHE_WAIT_NONE = 0,
/* Cache wait L1D invalidate all */
CACHE_WAIT_L1DINVALL = 1,
/* Cache wait LID invalidate */
CACHE_WAIT_L1DINV = 2,
/* Cache wait L1D Write back all */
CACHE_WAIT_L1DWBALL = 3,
/* Cache wait L1D Write back */
CACHE_WAIT_L1DWB = 4,
/* Cache wait Write back invalidate all */
CACHE_WAIT_L1DWBINVALL= 5,
/* Cache wait L1D Write back invalidate */
CACHE_WAIT_L1DWBINV = 6,
/* Cache wait L1P invaliate all */
CACHE_WAIT_L1PINVALL = 7,
/* Cache wait L1P invalidate */
CACHE_WAIT_L1PINV = 8,
/* Cache wait L2 invalidate all */
CACHE_WAIT_L2INVALL = 9,
/* Cache wait L2 invalidate */
CACHE_WAIT_L2INV = 10,
/* Cache wait L2 Write back all */
CACHE_WAIT_L2WBALL = 11,
/* Cache wait L2 Write back */
CACHE_WAIT_L2WB = 12,
/* Cache wait L2 Write back invalidate all */
CACHE_WAIT_L2WBINVALL = 13,
/* Cache wait L2 Write back invalidate */
CACHE_WAIT_L2WBINV = 14
} CACHE_waitState;
extern volatile CACHE_waitState _CSL_cachebusyState;
/* Enum for CACHE Emif State */
typedef enum {
/* No CACHE EMIFA */
CACHE_EMIF_NONE = 0,
/* CACHE EMIFA */
CACHE_EMIF_A = 1,
/* CACHE EMIFB */
CACHE_EMIF_B = 2,
/* CACHE EMIFAB */
CACHE_EMIF_AB = 3
}CACHE_emifState;
extern volatile CACHE_emifState _CSL_cacheEmifState;
#define CSL_CACHE_EMIF_ISRANGE(addr) \
((CSL_CACHE_EMIF_MASK >> ((addr >> 27) & 0x1f)) & 0x1)
#define CSL_CACHE_EMIF_ISEMIFBRANGE(addr) \
((CSL_CACHE_EMIFB_MASK >> ((addr >> 27) & 0x1f)) & 0x1)
void _CSL_cacheApplyPatch();
void _CACHE_wait(CACHE_Wait);
#define CSL_CACHE_EMIF_MASK 0x3ff30000
#define CSL_CACHE_EMIFB_MASK 0x30000000
/* Emif A Config */
#define CSL_CACHE_EMIFA_REG *(volatile unsigned int*) 0x70000000
/* Emif B Config */
#define CSL_CACHE_EMIFB_REG *(volatile unsigned int*) 0x78000000
#define CSL_CACHE_EMIFA_PATCH() { CSL_CACHE_EMIFA_REG = 0; CSL_CACHE_EMIFA_REG;}
#define CSL_CACHE_EMIFB_PATCH() { CSL_CACHE_EMIFB_REG = 0; CSL_CACHE_EMIFB_REG;}
#ifdef __cplusplus
}
#endif
#endif /*__CSL_CACHE_H_ */
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotClose.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/memprot/csl_memprotClose.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_memprotClose.c
*
* @path $(CSLPATH)\src\memprot
*
* @desc File for functional layer of CSL API CSL_memprotClose ()
*
*/
/* =============================================================================
* Revision History
* ===============
* 01-Feb-2006 ds Added error checking
* =============================================================================
*/
#include <csl_memprot.h>
/** ===========================================================================
* @n@b CSL_memprotClose
*
* @b Description
* @n This function closes the specified instance of MEMPROT.
*
* @b Arguments
* @verbatim
hMem Handle to the MEMPROT instance
@endverbatim
*
* <b> Usage Constraints: </b>
* CSL_memprotInit(), CSL_memprotOpen() must be opened prior to this call.
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Close successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* @b Example
* @verbatim
CSL_MemprotHandle hMem;
CSL_status status;
...
status = CSL_memprotClose(hMem);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_memprotClose, ".text:csl_section:memprot");
CSL_Status CSL_memprotClose (
CSL_MemprotHandle hMemprot
)
{
/* Indicate in the CSL global data structure that the peripheral
* has been unreserved
*/
CSL_Status status = CSL_SOK;
if (hMemprot != NULL) {
hMemprot->regs = (CSL_MemprotRegsOvly) NULL;
hMemprot->modNum = (CSL_InstNum) - 1;
}
else {
status = CSL_ESYS_BADHANDLE;
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/tsc/src/Tsc_example.c
|
<filename>DSP/TI-Header/csl_c6455/example/tsc/src/Tsc_example.c
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file Tsc_example.c
*
* @path $(CSLPATH)\example\tsc\src
*
* @desc Example of TSC CSL
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n The example shows how to use the TSC.
* 1. Enables the counter.
* 2. Waits for some time.
* 3. Reads the timer counter value
* 4. Waits for some time.
* 5. Reads the timer counter value
* 6. Compares the counter values to ensure the counter is incremented
* 7. Displays the messages based on step 6
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Tsc_example.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 27-Jul-2005 ds created
* 14-Nov-2005 ds modified - Removed Ctimer related APIs and Added TSC APIs
* 16-Dec-2005 ds Updated documentation
* ============================================================================
*/
#include <stdio.h>
#include <csl_tsc.h>
/* Macro that gives 1 CLK delay cycles */
#define WAIT_FOR_1_CLK do { \
volatile int delayCnt = 1; \
while(delayCnt > 0) --delayCnt; \
}while (0)
/* Forward declaration */
void tsc_example (void);
/* Globals */
Uint32 exampleFailed = 0;
/*
* ============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* ============================================================================
*/
void main(void)
{
/* Invoke example */
tsc_example ();
if (exampleFailed > 0) {
printf ("Time Stamp Counter Example Failed[Example Failed: %d]\n", \
exampleFailed);
}
else {
printf ("Time Stamp Counter Example Passed\n");
}
printf("==============================================================\n");
}
/*
* =============================================================================
* @func tsc_example
*
* @arg
* NONE
*
* @desc
* It implements following steps
* 1. Enables the counter.
* 2. Waits for some time.
* 3. Reads the timer counter value
* 4. Waits for some time.
* 5. Reads the timer counter value
* 6. Compares the counter values to ensure the counter is incremented
* 7. Print the result
*
* @return
* NONE
*
* =============================================================================
*/
void tsc_example (void)
{
CSL_Uint64 counterVal;
printf("Running TSC CSL example\n");
printf("Enable the Time Stamp Counter\n");
/* Enable the TSC */
CSL_tscEnable();
/* Give small delay */
WAIT_FOR_1_CLK;
/* Read the counter value */
counterVal = CSL_tscRead();
/* Give small delay */
WAIT_FOR_1_CLK;
/* Read the counter value */
counterVal = CSL_tscRead();
/* Verify the counter value incremented or not */
if(counterVal > 0) {
printf("Increment in the time stamp counter value\n");
printf ("counterVal = 0x%lX\n", counterVal);
}
else {
printf("Not increment in the time stamp counter value\n");
printf ("counterVal = 0x%lX\n", counterVal);
exampleFailed++;
return;
}
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/vcp2/vcp2_soft_decisions/inc/vcp2_example.h
|
<filename>DSP/TI-Header/csl_c6455/example/vcp2/vcp2_soft_decisions/inc/vcp2_example.h
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in
* the license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
* @file vcp2_example.h
*
* @path $(CSLPATH)\example\c6455\vcp2\vcp2_soft_decisions\inc
*
* @desc Example header file for VCP2.
*
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 09-10-2005 SD File created
* ============================================================================
*/
#ifndef _VCP2_EXAMPLE_H_
#define _VCP2_EXAMPLE_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Space for the branch metrics */
extern Uint32 branch_metric[];
/* Space for the soft decisions */
extern Uint32 soft_decision[];
/* Space for the pre-computed soft decisions */
extern Uint32 soft_decisionRef[];
#ifdef __cplusplus
}
#endif
#endif /*_VCP2_EXAMPLE_H_*/
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_ddr2.h
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ============================================================================
*/
/** ============================================================================
* @file csl_ddr2.h
*
* @Path $(CSLPATH)\inc
*
* @desc Header file for functional layer of CSL
* - The different enumerations, structure definitions
* and function declarations
*
*/
/* =============================================================================
* Revision History
* ===============
* 11-Apr-2005 RM File Created.
*
* 05-Oct-2005 NG Updation done according to new register layer
*
* 03-Feb-2006 ds ddrDrive field added to CSL_Ddr2Settings
* =============================================================================
*/
/**
* @mainpage DDR2 EMIF CSL 3.x
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to identify a set of common CSL APIs for
* the DDR2 EMIF module across various devices. The CSL developer is expected
* to refer to this document while designing APIs for these modules. Some of
* the cases listed APIs may not be applicable to a given DDR2 EMIF module.
* While other in this list of APIs may not be sufficient to cover all the
* features of a particular DDR2 EMIF Module. The CSL developer should use his
* discretion designing new APIs or extending the existing ones to cover these.
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
*
* @subsection References
* -# EMIF_SPEC, EMIF Module Specifications Document; Version 3.16.1
* Jan 18,2005
*
*/
#ifndef _CSL_DDR2_H_
#define _CSL_DDR2_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <cslr.h>
#include <soc.h>
#include <csl_error.h>
#include <csl_types.h>
#include <cslr_ddr2.h>
/*
* The defaults of DDR2 SDRAM Timing1 Control structure
*/
#define CSL_DDR2_TIMING1_TRFC_DEFAULT 0x7F
#define CSL_DDR2_TIMING1_TRP_DEFAULT 0x07
#define CSL_DDR2_TIMING1_TRCD_DEFAULT 0x07
#define CSL_DDR2_TIMING1_TWR_DEFAULT 0x07
#define CSL_DDR2_TIMING1_TRAS_DEFAULT 0x1F
#define CSL_DDR2_TIMING1_TRC_DEFAULT 0x1F
#define CSL_DDR2_TIMING1_TRRD_DEFAULT 0x07
#define CSL_DDR2_TIMING1_TWTR_DEFAULT 0x03
/*
* The defaults of DDR2 SDRAM Timing2 Control structure.
*/
#define CSL_DDR2_TIMING2_T_ODT_DEFAULT 0x03
#define CSL_DDR2_TIMING2_TSXNR_DEFAULT 0x7F
#define CSL_DDR2_TIMING2_TSXRD_DEFAULT 0xFF
#define CSL_DDR2_TIMING2_TRTP_DEFAULT 0x07
#define CSL_DDR2_TIMING2_TCKE_DEFAULT 0x1F
/*
* The default values of SDRAM config, refresh, timing1 and timing2 registers
* which are other than the reset values.
*/
#define CSL_DDR2_SDCFG_DEFAULT (0x00130630u)
#define CSL_DDR2_SDRFC_DEFAULT (0x00000753u)
#define CSL_DDR2_SDTIM1_DEFAULT (0x10912A09u)
#define CSL_DDR2_SDTIM2_DEFAULT (0x00850566u)
/******************************************************************************
* DDR2 global typedef declarations
******************************************************************************
*/
/** @brief Enumeration for bit field narrow_mode of SDRAM Config Register */
typedef enum {
/** DDR2 SDRAM data bus width is 32 bits */
CSL_DDR2_NORMAL_MODE = 0,
/** DDR2 SDRAM data bus width is 16 bits */
CSL_DDR2_NARROW_MODE = 1
}CSL_Ddr2Mode;
/** @brief Enumeration for bit field cl of SDRAM Config Register */
typedef enum {
/** Cas Latency is 2 */
CSL_DDR2_CAS_LATENCY_2 = 2,
/** Cas Latency is 3 */
CSL_DDR2_CAS_LATENCY_3 = 3,
/** Cas Latency is 4 */
CSL_DDR2_CAS_LATENCY_4 = 4,
/** Cas Latency is 5 */
CSL_DDR2_CAS_LATENCY_5 = 5
} CSL_Ddr2CasLatency;
/** @brief Enumeration for bit field ibank of SDRAM Config Register */
typedef enum {
/** DDR2 SDRAM has one internal bank */
CSL_DDR2_1_SDRAM_BANKS = 0,
/** DDR2 SDRAM has two internal banks */
CSL_DDR2_2_SDRAM_BANKS = 1,
/** DDR2 SDRAM has four internal bank */
CSL_DDR2_4_SDRAM_BANKS = 2,
/** DDR2 SDRAM has eight internal banks */
CSL_DDR2_8_SDRAM_BANKS = 3
} CSL_Ddr2IntBank;
/** @brief Enumeration for bit field pagesize of SDRAM Config Register */
typedef enum {
/** 256-word pages requiring 8 column address bits */
CSL_DDR2_256WORD_8COL_ADDR = 0,
/** 512-word pages requiring 9 column address bits */
CSL_DDR2_512WORD_9COL_ADDR = 1,
/** 1024-word pages requiring 10 column address bits */
CSL_DDR2_1024WORD_10COL_ADDR = 2,
/** 2048-word pages requiring 11 column address bits */
CSL_DDR2_2048WORD_11COL_ADDR = 3
} CSL_Ddr2PageSize;
/** @brief Enumeration for bit field SR of SDRAM Config Register */
typedef enum {
/** Disables Self Refresh on DDR2 */
CSL_DDR2_SELF_REFRESH_DISABLE = 0,
/** Connected DDR2 SDRAM device will enter Self Refresh Mode
* and DDR2 EMIF enters Self Refresh State
*/
CSL_DDR2_SELF_REFRESH_ENABLE = 1
} CSL_Ddr2SelfRefresh;
/** @brief Enumeration for bit field ddr_drive of SDRAM Config Register */
typedef enum {
/** Normal drive strength */
CSL_DDR2_NORM_DRIVE = 0,
/** Weak drive strengths */
CSL_DDR2_WEAK_DRIVE = 1
}CSL_Ddr2Drive;
/**
* @brief Module specific context information.
*/
typedef struct {
/** Context information of DDR2 external memory interface CSL passed as an
* argument to CSL_ddr2Init().Present implementation of DDR2 CSL doesn't
* have any context information; hence assigned NULL.
* The below declaration is just a place-holder for future implementation.
*/
Uint16 contextInfo;
} CSL_Ddr2Context;
/**
* @brief This structure contains the base-address information for the DDR2
* instance
*/
typedef struct {
/** Base-address of the configuration registers of the peripheral */
CSL_Ddr2RegsOvly regs;
} CSL_Ddr2BaseAddress;
/**
* @brief This Object contains the reference to the instance of DDR2 opened
* using the @a CSL_ddr2Open().
*
* The pointer to this, is passed to all DDR2 CSL APIs.
*/
typedef struct CSL_Ddr2Obj {
/** This is a pointer to the registers of the instance of DDR2
* referred to by this object
*/
CSL_Ddr2RegsOvly regs;
/** This is the instance of DDR2 being referred to by this object */
CSL_InstNum perNum;
} CSL_Ddr2Obj;
/**
* @brief this is a pointer to @a CSL_Ddr2Obj and is passed as the first
* parameter to all DDR2 CSL APIs
*/
typedef struct CSL_Ddr2Obj *CSL_Ddr2Handle;
/**
* @brief This is module specific parameters. Present implementation of DDR2
* CSL doesn't have any module specific parameters.
*/
typedef struct {
/** Bit mask to be used for module specific parameters. The below
* declaration is just a place-holder for future implementation. Passed as
* an argument to CSL_ddr2Open().
*/
CSL_BitMask16 flags;
} CSL_Ddr2Param;
/**
* @brief DDR2 SDRAM Timing1 structure.
* All fields needed for DDR2 SDRAM Timing1 are present in this structure.
*/
typedef struct {
/** Specifies TRFC value: Minimum number of DDR2 EMIF cycles from Refresh
* or Load command to Refresh or Activate command, minus one
*/
Uint8 trfc;
/** Specifies TRP value: Minimum number of DDR2 EMIF cycles from Pre-charge
* to Active or Refresh command, minus one
*/
Uint8 trp;
/** Specifies TRCD value: Minimum number of DDR2 EMIF cycles from Active to
* Read or Write command, minus one
*/
Uint8 trcd;
/** Specifies TWR value: Minimum number of DDR2 EMIF cycles from last write
* transfer to Pre-charge command, minus one
*/
Uint8 twr;
/** Specifies TRAS value: Minimum number of DDR2 EMIF cycles from Activate
* to Pre-charge command, minus one
*/
Uint8 tras;
/** Specifies TRC value: Minimum number of DDR2 EMIF cycles from Activate
* command to Activate command, minus one
*/
Uint8 trc;
/** Specifies TRRD value: Minimum number of DDR2 EMIF cycles from Activate
* command to Activate command for a differnt bank, minus one
*/
Uint8 trrd;
/** Specifies the minimum number of DDR2 EMIF clock cycles from last DDR
* Write to DDR Read, minus one
*/
Uint8 twtr;
} CSL_Ddr2Timing1;
/** @brief DDR2 SDRAM Timing2 structure.
*
* All fields needed for DDR2 SDRAM Timing2 are present in this structure.
*/
typedef struct {
/** Specifies the minimum number of DDR2 EMIF clock cycles from ODT enable
* to write data driven for DDR2 SDRAM.
*/
Uint8 todt;
/** Specifies the minimum number of DDR2 EMIF clock cycles from Self-Refresh
* exit to any command other than a Read command, minus one.
*/
Uint8 tsxnr;
/** Specifies the minimum number of DDR2 EMIF clock cycles from Self-Refresh
* exit to a Read command for DDR SDRAM, minus one.
*/
Uint8 tsxrd;
/** Specifies the minimum number of DDR2 EMIF clock cycles from the last
* Read command to a Pre-charge command for DDR2 SDRAM, minus one.
*/
Uint8 trtp;
/** Specifies the minimum number of DDR2 EMIF clock cycles between
* pado_mcke_o changes, minus one.
*/
Uint8 tcke;
} CSL_Ddr2Timing2;
/** @brief DDR2 SDRAM Settings structure.
*
* All fields needed for DDR2 SDRAM settings are present in this structure.
*/
typedef struct {
/** CAS Latency */
CSL_Ddr2CasLatency casLatncy;
/** Defines number of banks inside connected SDRAM devices */
CSL_Ddr2IntBank ibank;
/** Defines the internal page size of connected SDRAM devices */
CSL_Ddr2PageSize pageSize;
/** SDRAM data bus width */
CSL_Ddr2Mode narrowMode;
/** DDR SDRAM drive strength */
CSL_Ddr2Drive ddrDrive;
} CSL_Ddr2Settings;
/**
* @brief This has all the fields required to configure DDR2 at Power Up
* (after a Hardware Reset) or a Soft Reset.
*
* This structure is used to setup or obtain existing setup of
* DDR2 using @a CSL_ddr2HwSetup() & @a CSL_ddr2GetHwSetup() functions
* respectively.
*/
typedef struct {
/** Refresh Rate */
Uint16 refreshRate;
/** Structure for DDR2 SDRAM Timing1 */
CSL_Ddr2Timing1 *timing1Param;
/** Structure for DDR2 SDRAM Timing2 */
CSL_Ddr2Timing2 *timing2Param;
/** Structure for DDR2 SDRAM configuration */
CSL_Ddr2Settings *setParam;
} CSL_Ddr2HwSetup;
/**
* @brief DDR2 Module ID and Revision structure
*
* This structure is used for querying the DDR2 module ID and revision
*/
typedef struct {
/** DDR2 EMIF Module ID */
Uint16 modId;
/** DDR2 EMIF Major Revision */
Uint8 majRev;
/** DDR2 EMIF Minor Revision */
Uint8 minRev;
} CSL_Ddr2ModIdRev;
/**
* @brief DDR2 config structure which is used in CSL_ddr2HwSetupRaw function
*/
typedef struct {
/** SDRAM Config Register */
volatile Uint32 SDCFG;
/** SDRAM Refresh Control Register */
volatile Uint32 SDRFC;
/** SDRAM Timing1 Register*/
volatile Uint32 SDTIM1;
/** SDRAM Timing2 Register */
volatile Uint32 SDTIM2;
/** VBUSM Burst Priority Register */
volatile Uint32 BPRIO;
} CSL_Ddr2Config;
/**
* @brief Enumeration for queries passed to @a CSL_ddr2GetHwStatus()
*
* This is used to get the status of different operations
*/
typedef enum {
/** Get the DDR2 EMIF module ID and revision numbers (response type:
* @a (CSL_Ddr2ModIdRev*))
*/
CSL_DDR2_QUERY_REV_ID,
/** Get the EMIF refresh rate information
* (response type: @a Uint16 *)
*/
CSL_DDR2_QUERY_REFRESH_RATE,
/** Get self refresh bit value(response type:
* @a (CSL_Ddr2SelfRefresh *))
*/
CSL_DDR2_QUERY_SELF_REFRESH,
/** VBUSM Configuration values such as FIFO depths and Bus width
* (response type: @a CSL_Ddr2VbusmCfg*)
*/
CSL_DDR2_QUERY_ENDIAN,
/** Reflects the value on the IFRDY_ready port (active high) that
* defines whether the DDR IFRDY is ready for normal operation.
* (response type: @a Uint8*)
*/
CSL_DDR2_QUERY_IFRDY
} CSL_Ddr2HwStatusQuery;
/**
* @brief Enumeration for commands passed to @a CSL_ddr2HwControl()
*
* This is used to select the commands to control the operations
* existing setup of DDR2. The arguments to be passed with each
* enumeration if any are specified next to the enumeration.
*/
typedef enum {
/** Self refresh enable or disable based on arg passed
* : argument @a (CSL_Ddr2SelfRefresh *)
*/
CSL_DDR2_CMD_SELF_REFRESH = 0,
/** Enters the Refresh rate value : argument @a (Uint16 *) */
CSL_DDR2_CMD_REFRESH_RATE,
/** Number of memory transfers after which the DDR2 EMIF momentarily
* raises the priority of old commands in the VBUSM Command FIFO. :
* argument @a (Uint8 *)
*/
CSL_DDR2_CMD_PRIO_RAISE
} CSL_Ddr2HwControlCmd;
/** @brief The defaults of DDR2 SDRAM Timing1 Control structure */
#define CSL_DDR2_TIMING1_DEFAULTS {\
(Uint8)CSL_DDR2_TIMING1_TRFC_DEFAULT, \
(Uint8)CSL_DDR2_TIMING1_TRP_DEFAULT, \
(Uint8)CSL_DDR2_TIMING1_TRCD_DEFAULT, \
(Uint8)CSL_DDR2_TIMING1_TWR_DEFAULT, \
(Uint8)CSL_DDR2_TIMING1_TRAS_DEFAULT, \
(Uint8)CSL_DDR2_TIMING1_TRC_DEFAULT, \
(Uint8)CSL_DDR2_TIMING1_TRRD_DEFAULT, \
(Uint8)CSL_DDR2_TIMING1_TWTR_DEFAULT \
}
/** @brief The defaults of DDR2 SDRAM Timing2 Control structure */
#define CSL_DDR2_TIMING2_DEFAULTS { \
(Uint8)CSL_DDR2_TIMING2_T_ODT_DEFAULT, \
(Uint8)CSL_DDR2_TIMING2_TSXNR_DEFAULT, \
(Uint8)CSL_DDR2_TIMING2_TSXRD_DEFAULT, \
(Uint8)CSL_DDR2_TIMING2_TRTP_DEFAULT, \
(Uint8)CSL_DDR2_TIMING2_TCKE_DEFAULT \
}
/** @brief The defaults of DDR2 SDRAM Config structure */
#define CSL_DDR2_SETTING_DEFAULTS { \
(CSL_Ddr2CasLatency)CSL_DDR2_CAS_LATENCY_5, \
(CSL_Ddr2IntBank)CSL_DDR2_4_SDRAM_BANKS, \
(CSL_Ddr2PageSize)CSL_DDR2_256WORD_8COL_ADDR, \
(CSL_Ddr2Mode)CSL_DDR2_NORMAL_MODE, \
(CSL_Ddr2Drive)CSL_DDR2_NORM_DRIVE \
}
/** @brief The default Config structure */
#define CSL_DDR2_CONFIG_DEFAULTS { \
CSL_DDR2_SDCFG_DEFAULT, \
CSL_DDR2_SDRFC_DEFAULT, \
CSL_DDR2_SDTIM1_DEFAULT, \
CSL_DDR2_SDTIM2_DEFAULT, \
CSL_DDR2_BPRIO_RESETVAL \
}
/******************************************************************************
* DDR2 global function declarations
******************************************************************************
*/
/** ===========================================================================
* @n@b CSL_ddr2Init
*
* @b Description
* @n This function is idempotent i.e. calling it many times is same as calling
* it once. This function presently does nothing.
*
* <b> Usage Constraints: </b>
* This function should be called before using any of the CSL APIs
*
* @b Arguments
@verbatim
pContext Context information for the instance. Should be NULL
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CSL_ddr2Init( NULL );
...
}
@endverbatim
*
*
* ============================================================================
*/
CSL_Status CSL_ddr2Init (
CSL_Ddr2Context *pContext
);
/** =============================================================================
* @n@b CSL_ddr2Open
*
* @b Description
* @n This function returns the handle to the DDR2 instance. This
* handle is passed to all other CSL APIs.
*
* @b Arguments
* @verbatim
pDdr2Obj Pointer to the object that holds reference to the
instance of DDR2 requested after the call
ddr2Num Instance of DDR2 to which a handle is requested
pDdr2Param Pointer to module specific parameters
pStatus pointer for returning status of the function call
@endverbatim
*
* <b> Return Value </b>
* CSL_Ddr2Handle - Valid DDR2 instance handle will be returned if status
* @li value is equal to CSL_SOK.
*
* <b> Pre Condition </b>
* @n @a The DDR2 must be successfully initialized via CSL_ ddr2Init()
* before calling this function.
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example:
* @verbatim
CSL_Status status;
CSL_Ddr2Obj ddr2Obj;
CSL_Ddr2Handle hDdr2;
hDdr2 = CSL_Ddr2Open(&ddr2Obj,
CSL_DDR2,
NULL,
&status
);
@endverbatim
*
* ===========================================================================
*/
CSL_Ddr2Handle CSL_ddr2Open (
CSL_Ddr2Obj *pDdr2Obj,
CSL_InstNum ddr2Num,
CSL_Ddr2Param *pDdr2Param,
CSL_Status *pStatus
);
/** ===========================================================================
* @n@b csl_ddr2Close.c
*
* @b Description
* @n This function marks that CSL for the external memory interface instance
* is CSL for the external memory interface instance need to be reopened
* before external memory interface CSL API.
*
* @b Arguments
* @verbatim
hDdr2 Pointer to the object that holds reference to the
instance of DDR2 requested after the call
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - external memory interface is
* close successfully
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called
* successfully in that order before @a CSL_ddr2Close() can be called.
*
* <b> Post Condition </b>
* @n 1. The external memory interface CSL APIs can not be called until the
* external memory interface CSL is reopened again using CSL_ddr2Open()
*
* @b Modifies
* @n hDdr2 structure
*
* @b Example
* @verbatim
CSL_Ddr2Handle hDdr2;
...
CSL_ddr2Close (hDdr2);
...
@endverbatim
*
* ============================================================================
*/
CSL_Status CSL_ddr2Close (
CSL_Ddr2Handle hDdr2
);
/** ===========================================================================
* @n@b CSL_ddr2GetBaseAddress
*
* @b Description
* @n Function to get the base address of the peripheral instance.
* This function is used for getting the base address of the peripheral
* instance. This function will be called inside the CSL_mcbspOpen()
* function call.
*
* @b Arguments
* @verbatim
ddr2Num Specifies the instance of the DDR2 external memory
interface for which the base address is requested
pDdr2Param Module specific parameters.
pBaseAddress Pointer to the base address structure to return the
base address details.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Open call is successful
* @li CSL_ESYS_FAIL The external memory interface
* instance is not available.
*
* <b> Pre Condition </b>
* @n @a CSL_ddr2Init() and CSL_ddr2Open () must be called successfully.
*
* <b> Post Condition </b>
* @n Base address structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. Base address structure.
*
* @b Example
* @verbatim
CSL_Status status;
CSL_Ddr2BaseAddress baseAddress;
...
status = CSL_ddr2GetBaseAddress(CSL_DDR2, NULL, &baseAddress);
@endverbatim
*
*
* ============================================================================
*/
CSL_Status CSL_ddr2GetBaseAddress (
CSL_InstNum ddr2Num,
CSL_Ddr2Param *pDdr2Param,
CSL_Ddr2BaseAddress *pBaseAddress
);
/** ============================================================================
* @n@b CSL_ddr2HwSetupRaw
*
* @b Description
* @n This function initializes the device registers with the register-values
* provided through the config data structure.
*
* @b Arguments
* @verbatim
hDdr2 Handle to the DDR2 external memory interface
instance
config Pointer to the config structure containing the
device register values
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Configuration successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Configuration structure
* pointer is not properly
* initialized
*
* <b> Pre Condition </b>
* @n @a CSL_ddr2Init() and @a CSL_ddr2Open () must be called successfully.
* before calling this function.
*
* <b> Post Condition </b>
* @n The registers of the specified DDR2 EMIF instance will be
* setup according to the values passed through the config structure
*
* @b Modifies
* @n Hardware registers of the DDR2 EMIF
*
* @b Example
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Ddr2Config config = CSL_DDR2_CONFIG_DEFAULTS;
CSL_Status status;
...
status = CSL_ddr2HwSetupRaw (hDdr2, &config);
..
@endverbatim
*
* ===========================================================================
*/
CSL_Status CSL_ddr2HwSetupRaw (
CSL_Ddr2Handle hDdr2,
CSL_Ddr2Config *config
);
/** ============================================================================
* @n@b CSL_ddr2HwSetup
*
* @b Description
* @n This function initializes the device registers with the appropriate values
* provided through the HwSetup data structure.
*
* @b Arguments
* @verbatim
hDdr2 Pointer to the peripheral data object of the
DDR2 external memory interface instance
setup Pointer to setup structure which contains the
information to program DDR2 to a useful state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK Hwsetup successful
* @li CSL_ESYS_BADHANDLE The handle passed is invalid
* @li CSL_ESYS_INVPARAMS The param passed is invalid
*
* <b> Pre Condition </b>
* Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called
* successfully in that order before this function can be called. The user
* has to allocate space for & fill in the main setup structure appropriately
* before calling this function
*
* <b> Post Condition </b>
* @n DDR2 registers are configured according to the hardware setup parameters
*
* @b Modifies
* @n DDR2 registers
*
* @b Example:
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Ddr2Timing1 tim1 = CSL_DDR2_TIMING1_DEFAULTS;
CSL_Ddr2Timing2 tim2 = CSL_DDR2_TIMING2_DEFAULTS;
CSL_Ddr2Settings set = CSL_DDR2_SETTING_DEFAULTS;
CSL_Ddr2HwSetup hwSetup ;
hwSetup.refreshRate = (Uint16)0x753;
hwSetup.timing1Param = &tim1;
hwSetup.timing2Param = &tim2;
hwSetup.setParam = &set;
CSL_ddr2HwSetup(hDdr2, &hwSetup);
@endverbatim
*
* @return Returns the status of the setup operation
*
* ============================================================================
*/
CSL_Status CSL_ddr2HwSetup (
CSL_Ddr2Handle hDdr2,
CSL_Ddr2HwSetup *setup
);
/** ============================================================================
* @n@b CSL_ddr2GetHwSetup
*
* @b Description
* @n This function gets the current setup of the DDR2. The status is
* returned through @a CSL_Ddr2HwSetup. The obtaining of status
* is the reverse operation of @a CSL_ddr2HwSetup() function.
*
* @b Arguments
* @verbatim
hDdr2 Handle to the external memory interface instance
setup Pointer to setup structure which contains the
information to program DDR2 to a useful state
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK - Hardware setup successful
* @li CSL_ESYS_INVPARAMS - The param passed is invalid
* @li CSL_ESYS_BADHANDLE - Handle is not valid
*
* <b> Pre Condition </b>
* Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called successfully
* in order before calling @a CSL_ddr2GetHwSetup().
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Second parameter setup value
*
* @b Example:
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Status status;
CSL_Ddr2Timing1 tim1;
CSL_Ddr2Timing2 tim2;
CSL_Ddr2Settings set;
CSL_Ddr2HwSetup hwSetup ;
hwSetup.timing1Param = &tim1;
hwSetup.timing2Param = &tim2;
hwSetup.setParam = &set;
...
status = CSL_ddr2GetHwSetup(hDdr2, &hwSetup);
@endverbatim
*
* @return returns the status of the operation (see @a CSL_Status)
*
* ============================================================================
*/
CSL_Status CSL_ddr2GetHwSetup (
CSL_Ddr2Handle hDdr2,
CSL_Ddr2HwSetup *setup
);
/** ============================================================================
* @n@b CSL_ddr2HwControl
*
* @b Description
* @n Control operations for the DDR2. For a particular control operation, the
* pointer to the corresponding data type needs to be passed as argument
* HwControl function Call. All the arguments (Structure elements included)
* passed to the HwControl function are inputs. For the list of commands
* supported and argument type that can be @a void* casted & passed with a
* particular command refer to @a CSL_Ddr2HwControlCmd.
*
* @b Arguments
* @verbatim
hDdr2 Pointer to the peripheral data object of the
DDR2 external memory interface instance
cmd The command to this API indicates the action to be
taken
arg An optional argument @a void* casted
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK - Command successful
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
* @li CSL_ESYS_INVCMD - The Command passed is invalid
*
* <b> Pre Condition </b>
* Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called successfully
* in order before calling @a CSL_ddr2HwControl(). For the argument type that
* can be @a void* casted & passed with a particular command refer to
* @a CSL_Ddr2HwControlCmd.
*
* <b> Post Condition </b>
* @n DDR2 registers are configured according to the command passed.
*
* @b Modifies
* @n DDR2 registers
*
* @b Example:
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Status status;
CSL_Ddr2SelfRefresh command;
command = CSL_DDR2_SELF_REFRESH_DISABLE;
...
status = CSL_ddr2HwControl(hDdr2,
CCSL_DDR2_CMD_SELF_REFRESH,
&command);
@endverbatim
*
*
* ============================================================================
*/
CSL_Status CSL_ddr2HwControl (
CSL_Ddr2Handle hDdr2,
CSL_Ddr2HwControlCmd cmd,
void *arg
);
/** ============================================================================
* @n@b CSL_ddr2GetHwStatus
*
* @b Description
* @n This function is used to read the current device configuration, status
* flags and the value present associated registers. Following table details
* the various status queries supported and the associated data structure to
* record the response. User should allocate memory for the said data type and
* pass its pointer as an unadorned void* argument to the status query call.
* For details about the various status queries supported and the associated
* data structure to record the response, refer to @a CSL_Ddr2HwStatusQuery
*
* @b Arguments
* @verbatim
hDdr2 Pointer to the peripheral data object of the
DDR2 external memory interface instance
query The query to this API which indicates the status
to be returned
response Placeholder to return the status. @a void* casted
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_OK - Hardware status call is
* successful
* @li CSL_ESYS_BADHANDLE - Not a valid Handle
* @li CSL_ESYS_INVQUERY - Invalid Query
*
* <b> Pre Condition </b>
* Both @a CSL_ddr2Init() and @a CSL_ddr2Open() must be called successfully
* in order before callinbg @a CSL_ddr2GetHwStatus(). For the argument type
* that can be @a void* casted & passed with a particular command refer to
* @a CSL_Ddr2HwStatusQuery
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n Third parameter, response vlaue
*
* @b Example:
* @verbatim
CSL_Ddr2Handle hDdr2;
CSL_Status status;
Uint16 response;
...
status = CSL_ddr2GetHwStatus(hDdr2,
CSL_DDR2_QUERY_REFRESH_RATE,
&response);
@endverbatim
*
*
* ============================================================================
*/
CSL_Status CSL_ddr2GetHwStatus (
CSL_Ddr2Handle hDdr2,
CSL_Ddr2HwStatusQuery query,
void *response
);
#ifdef __cplusplus
}
#endif
#endif
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/srio/csl_srioOpen.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_srioOpen.c
*
* @brief File for functional layer of CSL API CSL_srioOpen()
*
* @Path $(CSLPATH)\srio\src
*
* @desc The CSL_srioOpen() function definition and it's associated functions.
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 29-Aug-2005 PSK File Created.
* ============================================================================
*/
#include <csl_srio.h>
/** ============================================================================
* @n@b CSL_srioOpen
*
* @b Description
* @n This function populates the peripheral data object for the SRIO instance
* and returns a handle to the instance. This handle is passed to all other
* CSL APIs.
*
* @b Arguments
* @verbatim
pSrioObj Pointer to SRIO object.
srioNum Instance of SRIO CSL to be opened.
There is one instance of the SRIO
available. So, the value for this parameter will be
CSL_SRIO always.
pSrioParam Module specific parameters.
pStatus Status of the function call
@endverbatim
*
* <b> Return Value </b> CSL_SrioHandle
* @n Valid SRIO handle will be returned if
* status value is equal to CSL_SOK, otherwise NULL
* is returned.
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n 1. The status is returned in the status variable. If status
* returned is
* @li CSL_SOK - Valid SRIO handle is returned
* @li CSL_ESYS_FAIL - The SRIO instance is invalid
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* 2. SRIO object structure is populated
*
* @b Modifies
* @n 1. The status variable
*
* 2. SRIO object structure
*
* @b Example
* @verbatim
CSL_status status;
CSL_SrioObj srioObj;
CSL_SrioHandle hSrio;
...
hSrio = CSL_srioOpen(&srioObj, CSL_SRIO, NULL, &status);
...
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_srioOpen, ".text:csl_section:srio");
CSL_SrioHandle CSL_srioOpen (
CSL_SrioObj *pSrioObj,
CSL_InstNum srioNum,
CSL_SrioParam *pSrioParam,
CSL_Status *pStatus
)
{
CSL_SrioHandle hSrio = (CSL_SrioHandle)NULL;
CSL_SrioBaseAddress baseAddress;
if (pStatus == NULL) {
/* do nothing : module handle is already initialized to NULL */
}
else if (pSrioObj == NULL) {
*pStatus = CSL_ESYS_INVPARAMS;
}
else {
*pStatus = CSL_srioGetBaseAddress(srioNum, pSrioParam, &baseAddress);
if (*pStatus == CSL_SOK) {
pSrioObj->regs = baseAddress.regs;
pSrioObj->perNum = (CSL_InstNum)srioNum;
hSrio = (CSL_SrioHandle)pSrioObj;
}
else {
pSrioObj->regs = (CSL_SrioRegsOvly)NULL;
pSrioObj->perNum = (CSL_InstNum)-1;
}
}
return (hSrio);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/gpio/csl_gpioHwControl.c
|
/* ==========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied
* provided
* ==========================================================================
*/
/** ===========================================================================
* @file csl_gpioHwControl.c
*
* @path $(CSLPATH)\src\gpio
*
* @Desc File for functional layer of CSL API CSL_gpioHwControl()
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 10-Jun-2004 PGR File created
* 04-Sep-2004 Nsr - Updated the source csl_gpioHwControl.c for the new CSL
* format.
* 22-Feb-2005 Nsr - Added conrol command CSL_GPIO_CMD_GET_BIT according to
* TI Issue PSG00000310.
* 28-Jul-2005 PSK - Updated changes to support only one BANK
*
* 11-Jan-2006 NG - Added CSL_GPIO_CMD_SET_OUT_BIT Control Command
* 06-Mar-2006 ds - Changed CSL_GPIO_CMD_SET_OUT_BIT cmd to clear and set the
* outbit. Renamed CSL_GPIO_CMD_SET_OUT_BIT to
* CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT
* ============================================================================
*/
#include <csl_gpio.h>
#include <csl_gpioAux.h>
/** ============================================================================
* @n@b CSL_gpioHwControl
*
* @b Description
* @n Takes a command of GPIO with an optional argument & implements it.
*
* @b Arguments
* @verbatim
hGpio Handle to the GPIO instance
cmd The command to this API indicates the action to be
taken on GPIO.
arg An optional argument.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Status info return successful.
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Invalid parameter
* @li CSL_ESYS_INVCMD - Invalid command
* @li CSL_EGPIO_INVPARAM - Invalid pin number
*
* <b> Pre Condition </b>
* @n Both CSL_gpioInit() and CSL_gpioOpen() must be called successfully in
* order before this function.
*
* <b> Post Condition </b>
* @n GPIO registers are configured according to the command passed
*
* @b Modifies
* @n The hardware registers of GPIO.
*
* @b Example
* @verbatim
CSL_GpioHandle hGpio;
CSL_GpioHwControlCmd cmd = CSL_GPIO_CMD_BANK_INT_ENABLE;
status = CSL_gpioHwControl(hGpio, cmd, NULL);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_gpioHwControl, ".text:csl_section:gpio");
CSL_Status CSL_gpioHwControl (
CSL_GpioHandle hGpio,
CSL_GpioHwControlCmd cmd,
void *arg
)
{
CSL_Status status = CSL_SOK;
if (hGpio == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if ( ((cmd >= 0) && (cmd <= CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT)) \
&& ((cmd != CSL_GPIO_CMD_BANK_INT_ENABLE) && \
(cmd != CSL_GPIO_CMD_BANK_INT_DISABLE)) && (arg == NULL)) {
status = CSL_ESYS_INVPARAMS;
}
else {
switch (cmd) {
case CSL_GPIO_CMD_BANK_INT_ENABLE:
status = CSL_gpioBankIntEnable(hGpio);
break;
case CSL_GPIO_CMD_BANK_INT_DISABLE:
status = CSL_gpioBankIntDisable(hGpio);
break;
case CSL_GPIO_CMD_CONFIG_BIT:
status = CSL_gpioConfigBit(hGpio, (CSL_GpioPinConfig *)arg);
break;
case CSL_GPIO_CMD_SET_BIT:
status = CSL_gpioSetBit(hGpio, *((CSL_GpioPinNum *)arg));
break;
case CSL_GPIO_CMD_CLEAR_BIT:
status = CSL_gpioClearBit(hGpio, *((CSL_GpioPinNum *)arg));
break;
case CSL_GPIO_CMD_GET_INPUTBIT:
status = CSL_gpioGetInputBit(hGpio, (CSL_BitMask16 *)arg);
break;
case CSL_GPIO_CMD_GET_OUTDRVSTATE:
status = CSL_gpioGetOutDrvState(hGpio, (CSL_BitMask16 *)arg);
break;
case CSL_GPIO_CMD_GET_BIT:
status = CSL_gpioGetBit(hGpio, ((CSL_GpioPinData *)arg));
break;
case CSL_GPIO_CMD_ENABLE_DISABLE_OUTBIT:
status = CSL_gpioEnDisOutBit(hGpio, ((CSL_GpioPinData *)arg));
break;
default:
status = CSL_ESYS_INVCMD;
break;
}
}
return status;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/edma/csl_edma3ChannelClose.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_edma3ChannelClose.c
*
* @path $(CSLPATH)\src\edma
*
* @desc EDMA3 CSL Implementation on DSP side
*
*/
/* =============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
*
* =============================================================================
*/
#include <csl_edma3.h>
/** ============================================================================
* @n@b csl_edma3ChannelClose.c
*
* @b Description
* @n This function marks the channel cannot be accessed anymore using
* the handle. CSL for the EDMA channel need to be reopened before using
* any edma channel.
*
* @b Arguments
* @verbatim
hEdma Handle to the requested channel
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Edma channel is closed successfully.
*
* @li CSL_ESYS_BADHANDLE - The handle passed is invalid
*
* <b> Pre Condition </b>
* @n Functions CSL_edma3Init(), CSL_edma3Open(), CSL_edma3ChannelOpen()
* must be invoked successfully in that order before this API can
* be invoked.
*
* <b> Post Condition </b>
* @n The edma channel related CSL APIs can not be called until the edma
* channel is reopened again using CSL_edma3ChannelOpen()
*
* @b Modifies
* @n CSL_Edma3ChannelObj structure values
*
* @b Example
* @verbatim
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelObj chObj;
CSL_Edma3QueryInfo info;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] =
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwDmaChannelSetup getdmahwSetup[CSL_EDMA3_NUM_DMACH];
CSL_Status status;
// Module Initialization
CSL_edma3Init(NULL);
// Module Level Open
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
// Module Setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
CSL_edma3HwSetup(hModule,&hwSetup);
// DRAE Enable(Bits 0-15) for the Shadow Region 0.
regionAccess.region = CSL_EDMA3_REGION_0 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
CSL_edma3HwControl(hModule, CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
// Channel 0 Open in context of Shadow region 0
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_CHA_DSP_EVT;
hChannel = CSL_edma3ChannelOpen(&chObj,
CSL_EDMA3,
&chAttr,
&status);
// Setup a Parameter Entry
...
// Manually trigger the Channel
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_SET,NULL);
// Close Channel
CSL_edma3ChannelClose(hChannel);
@endverbatim
* =============================================================================
*/
#pragma CODE_SECTION (CSL_edma3ChannelClose, ".text:csl_section:edma3");
CSL_Status CSL_edma3ChannelClose (
CSL_Edma3ChannelHandle hEdma
)
{
CSL_Status status = CSL_SOK;
if(hEdma != NULL) {
hEdma->regs = (CSL_Edma3ccRegsOvly) NULL;
hEdma->edmaNum = (CSL_InstNum) - 1;
hEdma->region = -2; /* -2 specifies the invalid region number */
hEdma->chaNum = -1; /* -1 specifies the invalid channel */
}
else {
status = CSL_ESYS_BADHANDLE;
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/srio/csl_srioGetHwSetup.c
|
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* =============================================================================
*/
/** ===========================================================================
* @file csl_srioGetHwSetup.c
*
* @brief File for functional layer of CSL API CSL_srioGetHwSetup()
*
* @path $(CSLPATH)\srio\src
*
* @desc The CSL_srioGetHwSetup() function definition and it's associated
* functions
* ============================================================================
*/
/* ============================================================================
* Revision History
* ===============
* 25-Aug-2005 PSK File Created.
* 15-Dec-2005 SD Updated the SERDES configuration.
* ============================================================================
*/
#include <csl_srio.h>
/** ============================================================================
* @n@b CSL_srioGetHwSetup
*
* @b Description
* @n It retrives the hardware setup parameters
*
* @b Arguments
* @verbatim
hSrio Handle to the SRIO instance
hwSetup Pointer to hardware setup structure
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup retrived
* @li CSL_ESYS_BADHANDLE - Invalid handle
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n The hardware set up structure will be populated with values from
* the registers
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_status status;
CSL_SrioHwSetup hwSetup;
...
status = CSL_srioGetHwsetup(hSrio, &hwSetup);
...
@endverbatim
* ===========================================================================
*/
#pragma CODE_SECTION (CSL_srioGetHwSetup, ".text:csl_section:srio");
CSL_Status CSL_srioGetHwSetup (
CSL_SrioHandle hSrio,
CSL_SrioHwSetup *hwSetup
)
{
int i;
CSL_Status status = CSL_SOK;
if (hSrio == NULL) {
status = CSL_ESYS_BADHANDLE;
}
else if (hwSetup == NULL) {
status = CSL_ESYS_INVPARAMS;
}
else {
/* Get the peripheral enable/disable setup */
hwSetup->perEn = (Bool)CSL_FEXT(hSrio->regs->PCR, SRIO_PCR_PEREN);
/* Get the sleep/awake mode of memories while shut down */
hwSetup->periCntlSetup.swMemSleepOverride =
(Bool)CSL_FEXT(hSrio->regs->PER_SET_CNTL,
SRIO_PER_SET_CNTL_SW_MEM_SLEEP_OVERRIDE);
/* Get the mode of operation, loopback/normal */
hwSetup->periCntlSetup.loopback =
(Bool)CSL_FEXT(hSrio->regs->PER_SET_CNTL,
SRIO_PER_SET_CNTL_LOOPBACK);
/* Get the setup of control ability to write any register during
* initialization
*/
hwSetup->periCntlSetup.bootComplete =
(Bool)CSL_FEXT(hSrio->regs->PER_SET_CNTL,
SRIO_PER_SET_CNTL_BOOT_COMPLETE);
/* get the setup of logical layer tx buffers needed to send the
* priority 2 packets
*/
hwSetup->periCntlSetup.txPriority2Wm = (CSL_SrioTxPriorityWm)CSL_FEXT(
hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_TX_PRI2_WM);
/* get the setup of logical layer tx buffers needed to send the
* priority 1 packets
*/
hwSetup->periCntlSetup.txPriority1Wm = (CSL_SrioTxPriorityWm)CSL_FEXT(
hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_TX_PRI1_WM);
/* get the setup of logical layer tx buffers needed to send the
* priority 0 packets
*/
hwSetup->periCntlSetup.txPriority0Wm = (CSL_SrioTxPriorityWm)CSL_FEXT(
hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_TX_PRI0_WM);
/* gwt Internal BUS transaction priority setup */
hwSetup->periCntlSetup.busTransPriority =
(CSL_SrioBusTransPriority)CSL_FEXT(hSrio->regs->PER_SET_CNTL,
SRIO_PER_SET_CNTL_CBA_TRANS_PRI);
/* get UDI buffering setup (priority versus port) setup */
hwSetup->periCntlSetup.bufferMode = (CSL_SrioBufMode)CSL_FEXT(
hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_1X_MODE);
/* get Internal clock frequency pre-scalar setup */
hwSetup->periCntlSetup.prescalar = (CSL_SrioClkDiv)CSL_FEXT(
hSrio->regs->PER_SET_CNTL, SRIO_PER_SET_CNTL_PRESCALER_SELECT);
/* get pllc settings */
hwSetup->periCntlSetup.pllEn = (Uint8)CSL_FEXTR(
hSrio->regs->PER_SET_CNTL, 3, 0);
/* get global enable setup */
hwSetup->gblEn = (Bool)CSL_FEXT(hSrio->regs->GBL_EN, SRIO_GBL_EN_EN);
/* get block enable setup */
for (i = 0; i < CSL_SRIO_BLOCKS_MAX; i++) {
hwSetup->blkEn[i] = CSL_FEXT(hSrio->regs->BLK_ENABLE[i].BLK_EN,
SRIO_BLK_EN_EN);
}
/* get the device ids setup */
hwSetup->deviceId1 = hSrio->regs->DEVICEID_REG1;
hwSetup->deviceId2 = hSrio->regs->DEVICEID_REG2;
/* get the hardware packet forwading registers setup */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hwSetup->pktFwdCntl[i].largeUpBoundDevId = CSL_FEXT(
hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL,
SRIO_PF_16BIT_CNTL_16BIT_DEVID_UP_BOUND);
hwSetup->pktFwdCntl[i].largeLowBoundDevId = CSL_FEXT(
hSrio->regs->HW_PKT_FWD[i].PF_16BIT_CNTL,
SRIO_PF_16BIT_CNTL_16BIT_DEVID_LOW_BOUND);
hwSetup->pktFwdCntl[i].outBoundPort = (CSL_SrioPortNum)CSL_FEXT(
hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL,
SRIO_PF_8BIT_CNTL_OUT_BOUND_PORT);
hwSetup->pktFwdCntl[i].smallUpBoundDevId = CSL_FEXT(
hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL,
SRIO_PF_8BIT_CNTL_8BIT_DEVID_UP_BOUND);
hwSetup->pktFwdCntl[i].smallLowBoundDevId = CSL_FEXT(
hSrio->regs->HW_PKT_FWD[i].PF_8BIT_CNTL,
SRIO_PF_8BIT_CNTL_8BIT_DEVID_LOW_BOUND);
}
/* SERDES PLL configuration setup */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
/* Get the enable pll configuration */
hwSetup->serDesPllCfg[i].pllEnable =
CSL_FEXT (hSrio->regs->SERDES_CFG_CNTL[i],
SRIO_SERDES_CFG_CNTL_ENPLL);
if (hwSetup->serDesPllCfg[i].pllEnable) {
/* Get the loop bandwidth configuration */
hwSetup->serDesPllCfg[i].loopBandwidth =
(CSL_SrioSerDesLoopBandwidth) CSL_FEXT (
hSrio->regs->SERDES_CFG_CNTL[i],
SRIO_SERDES_CFG_CNTL_LB);
/* Get the multiplication factor */
hwSetup->serDesPllCfg[i].pllMplyFactor =
(CSL_SrioSerDesPllMply) CSL_FEXT (
hSrio->regs->SERDES_CFG_CNTL[i],
SRIO_SERDES_CFG_CNTL_MPY);
}
}
/* SERDES RX channel enable setup */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
/* Get the receiver enabel configuration */
hwSetup->serDesRxChannelCfg [i].enRx =
CSL_FEXT (hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_ENRX);
if (hwSetup->serDesRxChannelCfg [i].enRx) {
/* Get the bus width configuration */
hwSetup->serDesRxChannelCfg [i].busWidth =
(CSL_SrioSerDesBusWidth) CSL_FEXT (
hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_BUSWIDTH);
/* Get the operating rate configuration */
hwSetup->serDesRxChannelCfg [i].rate =
(CSL_SrioSerDesRate) CSL_FEXT (
hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_RATE);
/* Get the polarity configuration */
hwSetup->serDesRxChannelCfg [i].invertedPolarity =
CSL_FEXT (hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_INVPAIR);
/* Get the termination configuration */
hwSetup->serDesRxChannelCfg [i].termination =
(CSL_SrioSerDesTermination) CSL_FEXT (
hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_TERM);
/* Get the symbol alignment configuration */
hwSetup->serDesRxChannelCfg [i].symAlign =
(CSL_SrioSerDesSymAlignment) CSL_FEXT (
hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_ALIGN);
/* Get the loss of signal detection configuration */
hwSetup->serDesRxChannelCfg [i].los =
(CSL_SrioSerDesLos) CSL_FEXT (
hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_LOS);
/* Get the clock and data recovery algorithm configuration */
hwSetup->serDesRxChannelCfg [i].clockDataRecovery =
CSL_FEXT (hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_CDR);
/* Get the adaptive equalizer configuration */
hwSetup->serDesRxChannelCfg [i].equalizer =
CSL_FEXT (hSrio->regs->SERDES_CFGRX_CNTL[i],
SRIO_SERDES_CFGRX_CNTL_EQ);
}
}
/* SERDES TX channel enable setup */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
/* Get the transmitter enable configuration */
hwSetup->serDesTxChannelCfg [i].enTx =
CSL_FEXT (hSrio->regs->SERDES_CFGTX_CNTL[i],
SRIO_SERDES_CFGTX_CNTL_ENTX);
if (hwSetup->serDesTxChannelCfg [i].enTx) {
/* Get the bus width configuration */
hwSetup->serDesTxChannelCfg [i].busWidth =
(CSL_SrioSerDesBusWidth) CSL_FEXT (
hSrio->regs->SERDES_CFGTX_CNTL[i],
SRIO_SERDES_CFGTX_CNTL_BUSWIDTH);
/* Get the operating rate configuration */
hwSetup->serDesTxChannelCfg [i].rate =
(CSL_SrioSerDesRate) CSL_FEXT (
hSrio->regs->SERDES_CFGTX_CNTL[i],
SRIO_SERDES_CFGTX_CNTL_RATE);
/* Get the polarity configuration */
hwSetup->serDesTxChannelCfg [i].invertedPolarity =
CSL_FEXT (hSrio->regs->SERDES_CFGTX_CNTL[i],
SRIO_SERDES_CFGTX_CNTL_INVPAIR);
/* Get the common mode configuration */
hwSetup->serDesTxChannelCfg [i].commonMode =
(CSL_SrioSerDesCommonMode) CSL_FEXT (
hSrio->regs->SERDES_CFGTX_CNTL[i],
SRIO_SERDES_CFGTX_CNTL_CM);
/* Get the output swing configuration */
hwSetup->serDesTxChannelCfg [i].outputSwing =
(CSL_SrioSerDesSwingCfg) CSL_FEXT (
hSrio->regs->SERDES_CFGTX_CNTL[i],
SRIO_SERDES_CFGTX_CNTL_SWING);
/* Get the output de-emphasis configuration */
hwSetup->serDesTxChannelCfg [i].outputDeEmphasis =
CSL_FEXT (hSrio->regs->SERDES_CFGTX_CNTL[i],
SRIO_SERDES_CFGTX_CNTL_DE);
/* Get the fixed phase configuration */
hwSetup->serDesTxChannelCfg [i].enableFixedPhase =
CSL_FEXT (hSrio->regs->SERDES_CFGTX_CNTL[i],
SRIO_SERDES_CFGTX_CNTL_ENFTP);
}
}
/* get flow control setup */
for (i = 0; i < CSL_SRIO_FLOW_CONTROL_REG_MAX; i++) {
hwSetup->flowCntlIdLen[i] = (Bool)CSL_FEXT(
hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_TT);
hwSetup->flowCntlId[i] = CSL_FEXT(
hSrio->regs->FLOW_CNTL[i], SRIO_FLOW_CNTL_FLOW_CNTL_ID);
}
/* get the processing element address bits setup */
hwSetup->peLlAddrCtrl = (CSL_SrioAddrSelect)hSrio->regs->PE_LL_CTL;
/* get Base device configuration */
hwSetup->devIdSetup.smallTrBaseDevId = CSL_FEXT(
hSrio->regs->BASE_ID, SRIO_BASE_ID_BASE_DEVICEID);
hwSetup->devIdSetup.largeTrBaseDevId = CSL_FEXT(
hSrio->regs->BASE_ID, SRIO_BASE_ID_LARGE_BASE_DEVICEID);
hwSetup->devIdSetup.hostBaseDevId = CSL_FEXT(
hSrio->regs->HOST_BASE_ID_LOCK,
SRIO_HOST_BASE_ID_LOCK_HOST_BASE_DEVICEID);
/* get Software defined component Tag for PE (processing element) */
hwSetup->componentTag = hSrio->regs->COMP_TAG;
/* Port General configuration */
hwSetup->portGenSetup.portLinkTimeout = CSL_FEXT(
hSrio->regs->SP_LT_CTL, SRIO_SP_LT_CTL_TIMEOUT_VALUE);
hwSetup->portGenSetup.portRespTimeout = CSL_FEXT(
hSrio->regs->SP_RT_CTL, SRIO_SP_RT_CTL_TIMEOUT_VALUE);
hwSetup->portGenSetup.hostEn = (Bool)CSL_FEXT(
hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_HOST);
hwSetup->portGenSetup.masterEn = (Bool)CSL_FEXT(
hSrio->regs->SP_GEN_CTL, SRIO_SP_GEN_CTL_MASTER_ENABLE);
/* get port control configuration */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hwSetup->portCntlSetup[i].portDis = (Bool)CSL_FEXT(
hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_DISABLE);
hwSetup->portCntlSetup[i].outPortEn = (Bool)CSL_FEXT(
hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_OUTPUT_PORT_ENABLE);
hwSetup->portCntlSetup[i].inPortEn = (Bool)CSL_FEXT(
hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_INPUT_PORT_ENABLE);
hwSetup->portCntlSetup[i].portWidthOverride =
(CSL_SrioPortWidthOverride)CSL_FEXT(hSrio->regs->PORT[i].SP_CTL,
SRIO_SP_CTL_PORT_WIDTH_OVERRIDE);
hwSetup->portCntlSetup[i].errCheckDis = (Bool)CSL_FEXT(
hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_ERROR_CHECK_DISABLE);
hwSetup->portCntlSetup[i].multicastRcvEn = (Bool)CSL_FEXT(
hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_MULTICAST_PARTICIPANT);
hwSetup->portCntlSetup[i].stopOnPortFailEn = (Bool)CSL_FEXT(
hSrio->regs->PORT[i].SP_CTL,
SRIO_SP_CTL_STOP_PORT_FLD_ENC_ENABLE);
hwSetup->portCntlSetup[i].dropPktEn = (Bool)CSL_FEXT(
hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_DROP_PACKET_ENABLE);
hwSetup->portCntlSetup[i].portLockoutEn = (Bool)CSL_FEXT(
hSrio->regs->PORT[i].SP_CTL, SRIO_SP_CTL_PORT_LOCKOUT);
}
/* get logical/transport layer errors setup */
hwSetup->lgclTransErrEn = hSrio->regs->ERR_EN;
/* get port error configuration */
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hwSetup->portErrSetup[i].portErrRateEn =
hSrio->regs->PORT_ERROR[i].SP_RATE_EN;
hwSetup->portErrSetup[i].prtErrRtBias =
(CSL_SrioErrRtBias)CSL_FEXT(hSrio->regs->PORT_ERROR[i].SP_ERR_RATE,
SRIO_SP_ERR_RATE_ERROR_RATE_BIAS);
hwSetup->portErrSetup[i].portErrRtRec = (CSL_SrioErrRtNum)CSL_FEXT(
hSrio->regs->PORT_ERROR[i].SP_ERR_RATE,
SRIO_SP_ERR_RATE_ERROR_RATE_RECOVERY);
hwSetup->portErrSetup[i].portErrRtFldThresh = CSL_FEXT(
hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH,
SRIO_SP_ERR_THRESH_ERROR_RATE_FAILED_THRESHOLD);
hwSetup->portErrSetup[i].portErrRtDegrdThresh = CSL_FEXT(
hSrio->regs->PORT_ERROR[i].SP_ERR_THRESH,
SRIO_SP_ERR_THRESH_ERROR_RATE_DEGRADED_THRES);
}
/* get the discovery timer value */
hwSetup->discoveryTimer = (CSL_SrioDiscoveryTimer)CSL_FEXT(
hSrio->regs->SP_IP_DISCOVERY_TIMER,
SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER);
/* get the port write timer value */
hwSetup->pwTimer = (CSL_SrioPwTimer)CSL_FEXT(
hSrio->regs->SP_IP_DISCOVERY_TIMER,
SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER);
/* get The configuration of SP_IP_MODE register */
hwSetup->portIpModeSet = hSrio->regs->SP_IP_MODE;
/* get The configuration of SP_IP_PRESCALE register */
hwSetup->portIpPrescalar = CSL_FEXT(hSrio->regs->IP_PRESCAL,
SRIO_IP_PRESCAL_PRESCALE);
/* ge the setups for silence timer and Port control independent error
* register
*/
for (i = 0; i < CSL_SRIO_PORTS_MAX; i++) {
hwSetup->silenceTimer[i] = (CSL_SrioSilenceTimer)CSL_FEXT(
hSrio->regs->PORT_OPTION[i].SP_SILENCE_TIMER, \
SRIO_SP_SILENCE_TIMER_SILENCE_TIMER);
hwSetup->portCntlIndpEn[i] =
hSrio->regs->PORT_OPTION[i].SP_CTL_INDEP;
}
}
return (status);
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455/example/edma/qdma_link_xfer_reg0/src/Qdma_link_xfer_reg0.c
|
<filename>DSP/TI-Header/csl_c6455/example/edma/qdma_link_xfer_reg0/src/Qdma_link_xfer_reg0.c
/* ===========================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ==========================================================================
*/
/** ===========================================================================
*
* @file Qdma_link_xfer_reg0.c
*
* @path $(CSLPATH)\example\edma\qdma_link_xfer_reg0\src
*
* @desc Example of EDMA
*
* ============================================================================
* @n Target Platform: EVM
* ============================================================================
* @n <b> Example Description </b>
* @n This is an example of the CSL EDMA usage for the
* QDMA Channel Initialization for linked transfer where channels are
* opened in region 0. This example do the following operations
* 1. Initializes and Opens the edma module
* 2. Sets up the Module and gets the module setup values
* 3. Enables the DMA and QDMA regions
* 4. Opens qdma channel0 in the region 0.
* 5. Gets the param handle for 0 and 1
* 6. Links the param sets 0 and 1
* 7. Sets up the param
* 8. Enables the channel and poll on the IPR bit
* 9. Clear the pending bit
* 10. Compares the transfered data
* 11. Displays the result based on step 10
*
* =============================================================================
*
* <b> Procedure to run the example </b>
* @verbatim
* 1. Configure the CCS setup to work with the emulator being used
* 2. Please refer CCS manual for setup configuration and loading
* proper GEL file
* 3. Launch CCS window
* 4. Open project Qdma_link_xfer_reg0.pjt
* 5. Build the project and load the .out file of the project.
*
* @endverbatim
*
*/
/* ============================================================================
* Revision History
* ===============
* 29-May-2004 <NAME> File Created.
* 16-Dec-2005 ds Minor documentation changes
* 27-Mar-2006 ds Added disable edma chhnel command
* ============================================================================
*/
#include <stdio.h>
#include <csl_edma3.h>
#include <soc.h>
/* Globals */
Uint8 srcBuff1[256];
Uint8 srcBuff2[256];
Uint8 dstBuff1[256];
Uint8 dstBuff2[256];
Uint32 passStatus = 1;
/* Forward declarations */
void qdma_link_xfer_region0 (void);
/*
* =============================================================================
* @func main
*
* @desc
* This is the main routine for the file.
*
* =============================================================================
*/
void main(void)
{
/* Invoke example */
qdma_link_xfer_region0 ();
return;
}
/*
* =============================================================================
* @func qdma_link_xfer_region0
*
* @arg
* NONE
*
* @desc
* This is the example routine which perform qdma link transfer where
* channel is open in region0
* 1. Initializes and Opens the edma module
* 2. Sets up the Module and gets the module setup values
* 3. Enables the DMA and QDMA regions
* 4. Opens qdma channel0 in the region 0.
* 5. Gets the param handle for 0 and 1
* 6. Links the param sets 0 and 1
* 7. Sets up the param
* 8. Enables the channel and poll on the IPR bit
* 9. Clear the pending bit
* 10. Compares the transfered data
* 11. Closes Edma module
*
* @return
* NONE
*
* =============================================================================
*/
void qdma_link_xfer_region0 (void)
{
CSL_Edma3Handle hModule;
CSL_Edma3HwSetup hwSetup;
CSL_Edma3Obj edmaObj;
CSL_Edma3ParamHandle hParamPong,hParamBasic;
CSL_Edma3ChannelObj chObj;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3Context context;
CSL_Edma3ChannelAttr chAttr;
CSL_Edma3CmdQrae qraeSetup;
CSL_Status status;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;
CSL_Edma3HwQdmaChannelSetup qdmahwSetup[CSL_EDMA3_NUM_QDMACH] = \
CSL_EDMA3_QDMACHANNELSETUP_DEFAULT;
Uint32 loopIndex;
/* Initialize data */
for (loopIndex = 0; loopIndex < 256; loopIndex++) {
srcBuff1[loopIndex] = loopIndex;
srcBuff2[loopIndex] = loopIndex;
dstBuff1[loopIndex] = 0;
dstBuff2[loopIndex] = 0;
}
/* Module initialization */
status = CSL_edma3Init(&context);
if (status != CSL_SOK) {
printf ("Edma module initialization failed\n");
return;
}
/* Module level open */
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
if ((hModule == NULL) || (status != CSL_SOK)) {
printf ("Edma module open failed\n");
return;
}
/* Module Setup */
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = &qdmahwSetup[0];
status = CSL_edma3HwSetup(hModule, &hwSetup);
if (status != CSL_SOK) {
printf ("Hardware setup failed\n");
CSL_edma3Close (hModule);
return;
}
/* DRAE enable(Bits 0-15) for the shadow region 0. */
regionAccess.region = CSL_EDMA3_REGION_0 ;
regionAccess.drae = 0xFFFF ;
regionAccess.draeh = 0x0000 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
if (status != CSL_SOK) {
printf ("Edma region enable command failed\n");
return;
}
if (hModule->regs->DRA[CSL_EDMA3_REGION_0].DRAE != 0xFFFF)
passStatus = 0;
qraeSetup.region = CSL_EDMA3_REGION_0;
qraeSetup.qrae = 0xF;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_QDMAREGION_ENABLE, \
&qraeSetup);
if (status != CSL_SOK) {
printf ("Qdma region enable command failed\n");
return;
}
if (hModule->regs->QRAE[CSL_EDMA3_REGION_0] != 0x000F)
passStatus = 0;
regionAccess.region = CSL_EDMA3_REGION_0;
regionAccess.drae = 0xFFFF;
regionAccess.draeh = 0x0;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
®ionAccess);
if (status != CSL_SOK) {
printf ("Edma region enable command failed\n");
return;
}
/* Channel Open */
chAttr.regionNum = CSL_EDMA3_REGION_0;
chAttr.chaNum = CSL_EDMA3_QCHA_0;
hChannel = CSL_edma3ChannelOpen(&chObj, CSL_EDMA3, &chAttr, &status);
if ((hChannel == NULL) || (status != CSL_SOK)) {
printf ("Edma channel open failed\n");
return;
}
/* Parameter entry 0 */
hParamBasic = CSL_edma3GetParamHandle(hChannel,qdmahwSetup[0].paramNum, \
&status);
if (hParamBasic == NULL) {
printf ("Edma get handle for param entry 0 failed\n");
return;
}
/* Pong Entry 1 */
hParamPong = CSL_edma3GetParamHandle(hChannel,qdmahwSetup[0].paramNum+1, \
&status);
if (hParamPong == NULL) {
printf ("Edma get handle for param entry 1 failed\n");
return;
}
/* Setup param entry */
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_DIS,\
0,CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(1,1);
myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(hParamPong,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,1);
myParamSetup.cCnt = 1;
CSL_edma3ParamSetup(hParamBasic,&myParamSetup);
/* Setting up the next entry */
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
1,CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_EN, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)srcBuff2;
myParamSetup.dstAddr = (Uint32)dstBuff2;
/* Setup for the Pong buffer */
status = CSL_edma3ParamSetup(hParamPong,&myParamSetup);
if (status != CSL_SOK) {
printf ("Edma param setup failed\n");
return;
}
/* Enable Channel */
status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, \
NULL);
if (status != CSL_SOK) {
printf ("Edma channel enable command failed\n");
return;
}
status = CSL_edma3ParamWriteWord(hParamBasic,7,1);
if (status != CSL_SOK) {
printf ("Edma param write word failed\n");
return;
}
/* Poll IPR bit */
regionIntr.region = CSL_EDMA3_REGION_0;
do {
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
} while (!(regionIntr.intr & 0x2));
/* Clear pending interrupt */
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, \
®ionIntr);
if (status != CSL_SOK) {
printf ("Edma clear interrupt pend command failed\n");
return;
}
/* Check transfer by comparing the source and destination buffers */
if(Verify_Transfer( 256, 1, 1, 0, 0, 0, 0, srcBuff1, dstBuff1,TRUE) == \
FALSE)
passStatus = 0;
if(Verify_Transfer( 256, 1, 1, 0, 0, 0, 0, srcBuff2, dstBuff2,TRUE) == \
FALSE)
passStatus = 0;
if (passStatus == 1)
printf ("<<EXAMPLE PASSED>>: Qdma Link Transfer Passed\n");
else {
printf ("<<EXAMPLE FAILED>>: Qdma Link Transfer Failed\n");
return;
}
/* Disable the channel */
status = CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_DISABLE, \
NULL);
/* Close channel */
status = CSL_edma3ChannelClose(hChannel);
if (status != CSL_SOK) {
printf("Edma channel close failed\n");
return;
}
/* Close edma module */
status = CSL_edma3Close(hModule);
if (status != CSL_SOK) {
printf("Edma module close failed\n");
return;
}
printf ("=============================================================\n");
return;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcInit.c
|
<filename>DSP/TI-Header/csl_c6455_src/src/pllc/csl_pllcInit.c
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ============================================================================
*/
/** @file csl_pllcInit.c
*
* @brief File for functional layer of CSL API @a CSL_pllcInit()
*
* Path: \(CSLPATH)\src\pllc
*
*/
/* ============================================================================
* Revision History
* ===============
* 10-Feb-2004 kpn CSL3X Upgradation.
* ============================================================================
*/
#include <csl_pllc.h>
/** ============================================================================
* @n@b CSL_pllcInit
*
* @b Description
* @n This is the initialization function for the pllc CSL. The function
* must be called before calling any other API from this CSL. This
* function is idem-potent. Currently, the function just return status
* CSL_SOK, without doing anything.
*
* @b Arguments
* @verbatim
pContext Pointer to module-context. As pllc doesn't have
any context based information user is expected to pass NULL.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
CSL_pllcInit(NULL);
@endverbatim
* ============================================================================
*/
#pragma CODE_SECTION (CSL_pllcInit, ".text:csl_section:pllc");
CSL_Status CSL_pllcInit (
CSL_PllcContext *pContext
)
{
pContext = pContext;
return CSL_SOK;
}
|
adildahlan/BE-thesis-Repo-McsDspRealtimeFeedback
|
DSP/TI-Header/csl_c6455_src/inc/csl_cache.h
|
<gh_stars>0
/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
/** ============================================================================
* @file csl_cache.h
*
* @path $(CSLPATH)\inc
*
* @desc Header file for functional layer CSL of CACHE
*
*/
/** @mainpage CACHE
*
* @section Introduction
*
* @subsection xxx Purpose and Scope
* The purpose of this document is to detail the Cache APIs
*
* @subsection aaa Terms and Abbreviations
* -# CSL: Chip Support Library
* -# API: Application Programmer Interface
*
* @subsection References
* -# Cache L2
* -# Cache L1D
* -# Cache L1P
*
*/
/* =============================================================================
* Revision History
* ===============
* 23-Mar-2004 <NAME> File Created.
* 21-Jun-2004 <NAME> modified.
* 15-Dec-2005 ds Removed EmifA CE0 ranges from the CE_MAR Enum
* =============================================================================
*/
#ifndef _CSL_CACHE_H_
#define _CSL_CACHE_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <csl.h>
#include <cslr_cache.h>
#include <soc.h>
/** L2 Line Size */
#define CACHE_L2_LINESIZE 128
/** L1D Line Size */
#define CACHE_L1D_LINESIZE 64
/** L1P Line Size */
#define CACHE_L1P_LINESIZE 32
/** Cache Round to Linesize */
#define CACHE_ROUND_TO_LINESIZE(CACHE,ELCNT,ELSIZE) \
((CACHE_##CACHE##_LINESIZE * \
((ELCNT)*(ELSIZE)/CACHE_##CACHE##_LINESIZE) + 1) / \
(ELSIZE))
/******************************************************************************\
* global macro declarations
\******************************************************************************/
/** Enumeration for Emif ranges
* This is used for setting up the cacheability of the EMIF ranges.
*/
typedef enum {
/** EMIFA CE2 Range A0000000 - A0FFFFFF */
CACHE_EMIFA_CE20 = 160,
/** EMIFA CE2 Range A1000000 - A1FFFFFF */
CACHE_EMIFA_CE21 = 161,
/** EMIFA CE2 Range A2000000 - A2FFFFFF */
CACHE_EMIFA_CE22 = 162,
/** EMIFA CE2 Range A3000000 - A3FFFFFF */
CACHE_EMIFA_CE23 = 163,
/** EMIFA CE2 Range A4000000 - A4FFFFFF */
CACHE_EMIFA_CE24 = 164,
/** EMIFA CE2 Range A5000000 - A5FFFFFF */
CACHE_EMIFA_CE25 = 165,
/** EMIFA CE2 Range A6000000 - A6FFFFFF */
CACHE_EMIFA_CE26 = 166,
/** EMIFA CE2 Range A7000000 - A7FFFFFF */
CACHE_EMIFA_CE27 = 167,
/** EMIFA CE2 Range A8000000 - A8FFFFFF */
CACHE_EMIFA_CE28 = 168,
/** EMIFA CE2 Range A9000000 - A9FFFFFF */
CACHE_EMIFA_CE29 = 169,
/** EMIFA CE2 Range AA000000 - AAFFFFFF */
CACHE_EMIFA_CE210 = 170,
/** EMIFA CE2 Range AB000000 - ABFFFFFF */
CACHE_EMIFA_CE211 = 171,
/** EMIFA CE2 Range AC000000 - ACFFFFFF */
CACHE_EMIFA_CE212 = 172,
/** EMIFA CE2 Range AD000000 - ADFFFFFF */
CACHE_EMIFA_CE213 = 173,
/** EMIFA CE2 Range AE000000 - AEFFFFFF */
CACHE_EMIFA_CE214 = 174,
/** EMIFA CE2 Range AF000000 - AFFFFFFF */
CACHE_EMIFA_CE215 = 175,
/** EMIFA CE3 Range B0000000 - B0FFFFFF */
CACHE_EMIFA_CE30 = 176,
/** EMIFA CE3 Range B1000000 - B1FFFFFF */
CACHE_EMIFA_CE31 = 177,
/** EMIFA CE3 Range B2000000 - B2FFFFFF */
CACHE_EMIFA_CE32 = 178,
/** EMIFA CE3 Range B3000000 - B3FFFFFF */
CACHE_EMIFA_CE33 = 179,
/** EMIFA CE3 Range B4000000 - B4FFFFFF */
CACHE_EMIFA_CE34 = 180,
/** EMIFA CE3 Range B5000000 - B5FFFFFF */
CACHE_EMIFA_CE35 = 181,
/** EMIFA CE3 Range B6000000 - B6FFFFFF */
CACHE_EMIFA_CE36 = 182,
/** EMIFA CE3 Range B7000000 - B7FFFFFF */
CACHE_EMIFA_CE37 = 183,
/** EMIFA CE3 Range B8000000 - B8FFFFFF */
CACHE_EMIFA_CE38 = 184,
/** EMIFA CE3 Range B9000000 - B9FFFFFF */
CACHE_EMIFA_CE39 = 185,
/** EMIFA CE3 Range BA000000 - BAFFFFFF */
CACHE_EMIFA_CE310 = 186,
/** EMIFA CE3 Range BB000000 - BBFFFFFF */
CACHE_EMIFA_CE311 = 187,
/** EMIFA CE3 Range BC000000 - BCFFFFFF */
CACHE_EMIFA_CE312 = 188,
/** EMIFA CE3 Range BD000000 - BDFFFFFF */
CACHE_EMIFA_CE313 = 189,
/** EMIFA CE3 Range BE000000 - BEFFFFFF */
CACHE_EMIFA_CE314 = 190,
/** EMIFA CE3 Range BF000000 - BFFFFFFF */
CACHE_EMIFA_CE315 = 191,
/** EMIFA CE4 Range C0000000 - C0FFFFFF */
CACHE_EMIFA_CE40 = 192,
/** EMIFA CE4 Range C1000000 - C1FFFFFF */
CACHE_EMIFA_CE41 = 193,
/** EMIFA CE4 Range C2000000 - C2FFFFFF */
CACHE_EMIFA_CE42 = 194,
/** EMIFA CE4 Range C3000000 - C3FFFFFF */
CACHE_EMIFA_CE43 = 195,
/** EMIFA CE4 Range C4000000 - C4FFFFFF */
CACHE_EMIFA_CE44 = 196,
/** EMIFA CE4 Range C5000000 - C5FFFFFF */
CACHE_EMIFA_CE45 = 197,
/** EMIFA CE4 Range C6000000 - C6FFFFFF */
CACHE_EMIFA_CE46 = 198,
/** EMIFA CE4 Range C7000000 - C7FFFFFF */
CACHE_EMIFA_CE47 = 199,
/** EMIFA CE4 Range C8000000 - C8FFFFFF */
CACHE_EMIFA_CE48 = 200,
/** EMIFA CE4 Range C9000000 - C9FFFFFF */
CACHE_EMIFA_CE49 = 201,
/** EMIFA CE4 Range CA000000 - CAFFFFFF */
CACHE_EMIFA_CE410 = 202,
/** EMIFA CE4 Range CB000000 - CBFFFFFF */
CACHE_EMIFA_CE411 = 203,
/** EMIFA CE4 Range CC000000 - CCFFFFFF */
CACHE_EMIFA_CE412 = 204,
/** EMIFA CE4 Range CD000000 - CDFFFFFF */
CACHE_EMIFA_CE413 = 205,
/** EMIFA CE4 Range CE000000 - CEFFFFFF */
CACHE_EMIFA_CE414 = 206,
/** EMIFA CE4 Range CF000000 - CFFFFFFF */
CACHE_EMIFA_CE415 = 207,
/** EMIFA CE5 Range D0000000 - D0FFFFFF */
CACHE_EMIFA_CE50 = 208,
/** EMIFA CE5 Range D1000000 - D1FFFFFF */
CACHE_EMIFA_CE51 = 209,
/** EMIFA CE5 Range D2000000 - D2FFFFFF */
CACHE_EMIFA_CE52 = 210,
/** EMIFA CE5 Range D3000000 - D3FFFFFF */
CACHE_EMIFA_CE53 = 211,
/** EMIFA CE5 Range D4000000 - D4FFFFFF */
CACHE_EMIFA_CE54 = 212,
/** EMIFA CE5 Range D5000000 - D5FFFFFF */
CACHE_EMIFA_CE55 = 213,
/** EMIFA CE5 Range D6000000 - D6FFFFFF */
CACHE_EMIFA_CE56 = 214,
/** EMIFA CE5 Range D7000000 - D7FFFFFF */
CACHE_EMIFA_CE57 = 215,
/** EMIFA CE5 Range D8000000 - D8FFFFFF */
CACHE_EMIFA_CE58 = 216,
/** EMIFA CE5 Range D9000000 - D9FFFFFF */
CACHE_EMIFA_CE59 = 217,
/** EMIFA CE5 Range DA000000 - DAFFFFFF */
CACHE_EMIFA_CE510 = 218,
/** EMIFA CE5 Range DB000000 - DBFFFFFF */
CACHE_EMIFA_CE511 = 219,
/** EMIFA CE5 Range DC000000 - DCFFFFFF */
CACHE_EMIFA_CE512 = 220,
/** EMIFA CE5 Range DD000000 - DDFFFFFF */
CACHE_EMIFA_CE513 = 221,
/** EMIFA CE5 Range DE000000 - DEFFFFFF */
CACHE_EMIFA_CE514 = 222,
/** EMIFA CE5 Range DF000000 - DFFFFFFF */
CACHE_EMIFA_CE515 = 223,
/** DDR2 CE0 Range E0000000 - E0FFFFFF */
CACHE_EMIFB_CE00 = 224,
/** DDR2 CE0 Range E1000000 - E1FFFFFF */
CACHE_EMIFB_CE01 = 225,
/** DDR2 CE0 Range E2000000 - E2FFFFFF */
CACHE_EMIFB_CE02 = 226,
/** DDR2 CE0 Range E3000000 - E3FFFFFF */
CACHE_EMIFB_CE03 = 227,
/** DDR2 CE0 Range E4000000 - E4FFFFFF */
CACHE_EMIFB_CE04 = 228,
/** DDR2 CE0 Range E5000000 - E5FFFFFF */
CACHE_EMIFB_CE05 = 229,
/** DDR2 CE0 Range E6000000 - E6FFFFFF */
CACHE_EMIFB_CE06 = 230,
/** DDR2 CE0 Range E7000000 - E7FFFFFF */
CACHE_EMIFB_CE07 = 231,
/** DDR2 CE0 Range E8000000 - E8FFFFFF */
CACHE_EMIFB_CE08 = 232,
/** DDR2 CE0 Range E9000000 - E9FFFFFF */
CACHE_EMIFB_CE09 = 233,
/** DDR2 CE0 Range EA000000 - EAFFFFFF */
CACHE_EMIFB_CE010 = 234,
/** DDR2 CE0 Range EB000000 - EBFFFFFF */
CACHE_EMIFB_CE011 = 235,
/** DDR2 CE0 Range EC000000 - ECFFFFFF */
CACHE_EMIFB_CE012 = 236,
/** DDR2 CE0 Range ED000000 - EDFFFFFF */
CACHE_EMIFB_CE013 = 237,
/** DDR2 CE0 Range EE000000 - EEFFFFFF */
CACHE_EMIFB_CE014 = 238,
/** DDR2 CE0 Range EF000000 - EFFFFFFF */
CACHE_EMIFB_CE015 = 239
} CE_MAR;
/** @brief Enumeration for Cache wait flags
*
* This is used for specifying whether the cache operations should block till
* the desired operation is complete.
*/
typedef enum {
/** No blocking, the call exits after programmation of the
* control registers
*/
CACHE_NOWAIT = 0,
/** Blocking Call, the call exits after the relevant cache
* status registers indicate completion
*/
CACHE_WAITINTERNAL = 1,
/** Blocking Call, the call waits not only till the cache status registers
* indicate completion, but also till a write read is issued to the
* EMIF registers (if required)
*/
CACHE_WAIT = 2
}CACHE_Wait;
/** @brief Enumeration for Cache Freeze flags
* This is used for reporting back the current state of the L1.
*/
typedef enum {
/** L1D is in Normal State */
CACHE_L1D_NORMAL = 0,
/** L1D is in Freeze State */
CACHE_L1D_FREEZE = 1,
/** L1P is in Normal State */
CACHE_L1P_NORMAL = 3,
/** L1P is in Freeze State */
CACHE_L1P_FREEZE = 4,
/** L1D, L1P is in Normal State */
CACHE_L1_NORMAL = 5,
/** L1D, L1P is in Freeze State */
CACHE_L1_FREEZE = 6
} CACHE_L1_Freeze;
/** @brief Enumeration for L1 (P or D) Sizes */
typedef enum {
/** No Cache */
CACHE_L1_0KCACHE = 0,
/** 4KB Cache */
CACHE_L1_4KCACHE = 1,
/** 8KB Cache */
CACHE_L1_8KCACHE = 2,
/** 16KB Cache */
CACHE_L1_16KCACHE = 3,
/** 32KB Cache */
CACHE_L1_32KCACHE = 4
} CACHE_L1Size;
/** @brief Enumeration for L2 Sizes */
typedef enum {
/** No Cache */
CACHE_0KCACHE = CSL_CACHE_L2CFG_MODE_0K,
/** 32KB Cache */
CACHE_32KCACHE = CSL_CACHE_L2CFG_MODE_32K,
/** 64KB Cache */
CACHE_64KCACHE = CSL_CACHE_L2CFG_MODE_64K,
/** 128KB Cache */
CACHE_128KCACHE = CSL_CACHE_L2CFG_MODE_128K,
/** 256KB Cache */
CACHE_256KCACHE = CSL_CACHE_L2CFG_MODE_256K
} CACHE_L2Size;
/** @brief Enumeration for L2 Modes */
typedef enum {
/** Enabled/Normal Mode */
CACHE_L2_NORMAL = CSL_CACHE_L2CFG_L2CC_ENABLED,
/** Freeze Mode */
CACHE_L2_FREEZE = CSL_CACHE_L2CFG_L2CC_FREEZE
} CACHE_L2Mode;
/*
* =============================================================================
* @n@b CACHE_enableCaching
*
* @desc
* @n Enables caching for the specified memory range
*
* @arg mar
* EMIF range
*
* @ret None
*
* @eg
* ...
CACHE_enableCaching (CACHE_EMIFB_CE00);
...
*
* ===========================================================================
*/
extern void CACHE_enableCaching (
CE_MAR mar
);
/*
* =============================================================================
* @n@b CACHE_wait
*
* @desc
* @n Waits for previously issued block operations to complete. This does a
* partial wait. i.e waits for the cache status register to read back as
* done.
*
* @arg None
*
* @ret None
*
* @eg
* ...
CACHE_wait();
...
*
* ===========================================================================
*/
extern void CACHE_wait(void);
/*
* =============================================================================
* @n@b CACHE_waitInternal
*
* @desc
* @n Waits for previously issued block operations to complete. This does a
* partial wait. i.e waits for the cache status register to read back as
* done. (if required)
*
* @arg None
*
* @ret None
*
* @eg
* ...
CACHE_waitInternal();
...
*
* ===========================================================================
*/
extern void CACHE_waitInternal(void);
/*
* =============================================================================
* @n@b CACHE_freezeL1
*
* @desc
* @n Freezes the L1P and L1D.
* @n As per the specification,
* @n a. The new freeze state is programmed in L1DCC, L1PCC.
* @n b. The old state is read from the L1DCC, L1PCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new state
* is programmed as well as reading the old programmed value.
*
* @arg None
*
* @ret CACHE_L1_Freeze
* Old Freeze State
* @eg
* ...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_freezeL1();
...
*
* ===========================================================================
*/
extern CACHE_L1_Freeze CACHE_freezeL1(void);
/*
* =============================================================================
* @n@b CACHE_unfreezeL1
*
* @desc
* @n Unfreezes the L1P and L1D.
* @n As per the specification,
* @n a. The new unfreeze state is programmed in L1DCC, L1PCC.
* @n b. The old state is read from the L1DCC, L1PCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new
* state is programmed as well as reading the old programmed value.
*
* @arg None
*
* @ret CACHE_L1_Freeze
* Old Freeze State
* @eg
* ...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_unfreezeL1();
...
*
* ===========================================================================
*/
extern CACHE_L1_Freeze CACHE_unfreezeL1(void);
/*
* =============================================================================
* @n@b CACHE_setL1pSize
*
* @desc
* @n Sets the L1P size.
* @n As per the specification,
* @n a. The new size is programmed in L1PCFG.
* @n b. L1PCFG is read back to ensure it is set.
*
* @arg newSize
* New size to be programmed
*
* @ret CACHE_L1Size
* Old Size set for L1P
* @eg
* ...
CACHE_L1Size oldSize ;
oldSize = CACHE_setL1pSize(CACHE_L1_32KCACHE);
...
*
* ===========================================================================
*/
extern CACHE_L1Size CACHE_setL1pSize (
CACHE_L1Size newSize
);
/*
* =============================================================================
* @n@b CACHE_freezeL1p
*
* @desc
* @n Freezes L1P.
* @n As per the specification,
* @n a. The new freeze state is programmed in L1PCC.
* @n b. The old state is read from the L1PCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new
* state is programmed as well as reading the old programmed value.
*
* @arg None
*
* @ret CACHE_L1_Freeze
* Old Freeze State
* @eg
* ...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_freezeL1p();
...
*
* ===========================================================================
*/
extern CACHE_L1_Freeze CACHE_freezeL1p(void);
/*
* =============================================================================
* @n@b CACHE_unfreezeL1p
*
* @desc
* @n Unfreezes L1P.
* @n As per the specification,
* @n a. The normal state is programmed in L1PCC
* @n b. The old state is read from the L1PCC from the POPER field.
* @n This latter read accomplishes 2 things, viz. Ensuring the new
* state is programmed as well as reading the old programmed value.
*
* @arg None
*
* @ret CACHE_L1_Freeze
* Old Freeze State
* @eg
* ...
CACHE_L1_Freeze oldFreezeState ;
oldFreezeState = CACHE_unfreezeL1p();
...
*
* ============================================================================
*/
extern CACHE_L1_Freeze CACHE_unfreezeL1p(void);
/*
* =============================================================================
* @n@b CACHE_invL1p
*
* @desc
* @n Invalidates range specified in L1P.
* @n As per the specification,
* @n a. The start of the range that needs to be invalidated is written
* into L1PIBAR
* @n b. The byte count is programmed in L1PIWC.
*
* @arg blockPtr
* Pointer to start address of range to be invalidated
*
* @arg byteCnt
* Number of bytes to be invalidated
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_invL1p ((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_invL1p (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_invAllL1p
*
* @desc
* Sets the L1D size. As per the specification,
* - The new size is programmed in L1DCFG
* - L1DCFG is read back to ensure it is set
*
* @arg wait
* Whether the call is blocking(and the extent of wait) till the
* issued operation is completed or not
*
* @ret None
*
* @eg
* ...
oldSize = CACHE_invAllL1p(CACHE_L1_32KCACHE);
...
*
* ===========================================================================
*/
extern void CACHE_invAllL1p (
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_setL1dSize
*
* @desc
* Sets the L1D size. As per the specification,
* - The new size is programmed in L1DCFG
* - L1DCFG is read back to ensure it is set
*
* @arg newSize
* New size to be programmed
*
* @ret CACHE_L1Size
* Old Size set for L1D
* @eg
* CACHE_L1Size oldSize;
...
oldSize = CACHE_setL1dSize(CACHE_L1_32KCACHE);
...
*
* ===========================================================================
*/
extern CACHE_L1Size CACHE_setL1dSize (
CACHE_L1Size newSize
);
/*
* =============================================================================
* @n@b CACHE_freezeL1d
*
* @desc
* Freezes L1D. As per the specification,
* - The normal state is programmed in L1DCC
* - The old state is read from the L1DCC from the POPER field.This latter
* read accomplishes 2 things, viz. Ensuring the new state is programmed
* as well as reading the old programmed value
*
* @arg None
*
* @ret CACHE_L1_Freeze
* Old Freeze State
* @eg
* CACHE_L1_Freeze oldFreezeState ;
...
CACHE_freezeL1d ();
...
*
* ===========================================================================
*/
extern CACHE_L1_Freeze CACHE_freezeL1d(void);
/*
* =============================================================================
* @n@b CACHE_unfreezeL1d
*
* @desc
* Unfreezes L1D. As per the specification,
* - The normal state is programmed in L1DCC
* - The old state is read from the L1DCC from the POPER field.This latter
* read accomplishes 2 things, viz. Ensuring the new state is programmed
* as well as reading the old programmed value
*
* @arg None
*
* @ret CACHE_L1_Freeze
* Old Freeze State
* @eg
* CACHE_L1_Freeze oldFreezeState ;
...
CACHE_unfreezeL1d ();
...
*
* ===========================================================================
*/
extern CACHE_L1_Freeze CACHE_unfreezeL1d (void);
/*
* =============================================================================
* @n@b CACHE_wbL1d
*
* @desc
* Writes back range specified in L1D.As per the specification,
* - The start of the range that needs to be is written back
* into L1DWBAR
* - The byte count is programmed in L1DWWC
*
* @arg blockPtr
* Start address of range to be written back
*
* @arg byteCnt
* Number of bytes to be written back
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_wbL1d ((Uint32*)(0x1000),200,CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_wbL1d (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_invL1d
*
* @desc
* Invalidates range specified in L1D.As per the specification,
* - The start of the range that needs to be invalidated is written
* into L1DIBAR
* - The byte count is programmed in L1DIWC
*
* @arg blockPtr
* Start address of range to be invalidated
*
* @arg byteCnt
* Number of bytes to be invalidated
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_invL1d ((Uint32*)(0x1000),200,CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_invL1d (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_wbInvL1d
*
* @desc
* Writeback invalidates range specified in L1D.As per the specification,
* - The start of the range that needs to be writeback invalidated is
* programmed into L1DWIBAR
* - The byte count is programmed in L1DWIWC
*
* @arg blockPtr
* Start address of range to be written back invalidated
*
* @arg byteCnt
* Number of bytes to be written back invalidated
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_wbInvL1d ((Uint32*)(0x1000),200,CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_wbInvL1d (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_wbAllL1d
*
* @desc
* Invalidates All of L1D.As per the specification,
* - The L1DINV is programmed
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not
*
* @ret None
*
* @eg
* ...
CACHE_wbAllL1d (CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_wbAllL1d (
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_wbInvAllL1d
*
* @desc
* Writeback invalidates All of L1D.As per the specification,
* - The L1DWBINV is programmed
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not
*
* @ret None
*
* @eg
* ...
CACHE_wbInvAllL1d (CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_invAllL1d (
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_wbInvAllL1d
*
* @desc
* Writeback invalidates All of L1D.As per the specification,
* - The L1DWBINV is programmed
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not
*
* @ret None
*
* @eg
* ...
CACHE_wbInvAllL1d (CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_wbInvAllL1d (
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_setL2Size
*
* @desc
* Sets the L2 size.As per the specification,
* - The old mode is read from the L2CFG
* - The new mode is programmed in L2CFG
* - L2CFG is read back to ensure it is set
*
* @arg newSize
* New size to be programmed
*
* @ret CACHE_L2Size
* Old Size set for L2
*
* @eg
* CACHE_L2Mode oldMode;
oldSize = CACHE_setL2Size(CACHE_L2_32KCACHE);
...
*
* ===========================================================================
*/
extern CACHE_L2Size CACHE_setL2Size (
CACHE_L2Size newSize
);
/*
* =============================================================================
* @n@b CACHE_setL2Mode
*
* @desc
* Sets the L2 mode.As per the specification,
* - The old mode is read from the L2CFG
* - The new mode is programmed in L2CFG
* - L2CFG is read back to ensure it is set
*
* @arg newMode
* New mode to be programmed
*
* @ret CACHE_L2Mode
* Old Mode set for L2
*
* @eg
* CACHE_L2Mode oldMode;
oldMode = CACHE_setL2Mode(CACHE_L2_NORMAL);
...
*
* ===========================================================================
*/
extern CACHE_L2Mode CACHE_setL2Mode (
CACHE_L2Mode newMode
);
/*
* =============================================================================
* @n@b CACHE_wbL2
*
* @desc
* Invalidates range specified in L2. As per the specification,
* - The start of the range that needs to be written back is programmed
* into L2WBAR
* - The byte count is programmed in L2WWC
*
* @arg blockPtr
* Start address of range to be written back
*
* @arg byteCnt
* Number of bytes to be written back
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not
*
* @ret None
*
* @eg
* ...
CACHE_wbL2((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_wbL2 (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_invL2
*
* @desc
* Invalidates range specified in L2. As per the specification,
* - The start of the range that needs to be invalidate is programmed
* into L2IBAR
* - The byte count is programmed in L2IWC
*
* @arg blockPtr
* Start address of range to be invalidated
*
* @arg byteCnt
* Number of bytes to be invalidated
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_invL2((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_invL2 (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_wbInvL2
*
* @desc
* Writeback invalidated range specified in L2.As per the specification,
* - The start of the range that needs to be written back is programmed
* into L2WIBAR
* - The byte count is programmed in L2WIWC
*
* @arg blockPtr
* Start address of range to be written back invalidated
*
* @arg byteCnt
* Number of bytes to be written back invalidated
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_wbInvL2((Uint32*)(0x1000), 200, CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_wbInvL2 (
void *blockPtr,
Uint32 byteCnt,
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_wbAllL2
*
* @desc
* Writes back all of L2.As per the specification,The L2WB needs to be
* programmed
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_wbAllL2(CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_wbAllL2 (
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_invAllL2
*
* @desc
* Invalidates All of L2.As per the specification,The L2INV needs to be
* programmed
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_invAllL2(CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_invAllL2 (
CACHE_Wait wait
);
/*
* =============================================================================
* @n@b CACHE_wbInvAllL2
*
* @desc
* Writeback invalidates All of L2.As per the specification,The L2WBINV
* needs to be programmed
*
* @arg wait
* Whether the call is blocking (and the extent of wait) till the
* issued operation is completed or not.
*
* @ret None
*
* @eg
* ...
CACHE_wbInvAllL2(CACHE_NOWAIT);
...
*
* ===========================================================================
*/
extern void CACHE_wbInvAllL2 (
CACHE_Wait wait
);
#ifdef __cplusplus
}
#endif
#endif /*_CSL_CACHE_H_*/
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.